blob: 6f40bfee730466995609381adf1c7c022de03228 [file] [log] [blame]
Eugeni Dodonov85208be2012-04-16 22:20:34 -03001/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
Sam Ravnborgd0e93592019-01-26 13:25:24 +010028#include <linux/module.h>
Chris Wilson08ea70a2018-08-12 23:36:31 +010029#include <linux/pm_runtime.h>
Sam Ravnborgd0e93592019-01-26 13:25:24 +010030
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_fourcc.h>
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -070033#include <drm/drm_plane_helper.h>
Sam Ravnborgd0e93592019-01-26 13:25:24 +010034
Jani Nikuladf0566a2019-06-13 11:44:16 +030035#include "display/intel_atomic.h"
Jani Nikula1d455f82019-08-06 14:39:33 +030036#include "display/intel_display_types.h"
Jani Nikuladf0566a2019-06-13 11:44:16 +030037#include "display/intel_fbc.h"
38#include "display/intel_sprite.h"
39
Andi Shyti0dc3c562019-10-20 19:41:39 +010040#include "gt/intel_llc.h"
41
Eugeni Dodonov85208be2012-04-16 22:20:34 -030042#include "i915_drv.h"
Jani Nikulaa10510a2020-02-27 19:00:47 +020043#include "i915_fixed.h"
Jani Nikula440e2b32019-04-29 15:29:27 +030044#include "i915_irq.h"
Jani Nikulaa09d9a82019-08-06 13:07:28 +030045#include "i915_trace.h"
Jani Nikula696173b2019-04-05 14:00:15 +030046#include "intel_pm.h"
Chris Wilson56c50982019-04-26 09:17:22 +010047#include "intel_sideband.h"
Daniel Vettereb48eb02012-04-26 23:28:12 +020048#include "../../../platform/x86/intel_ips.h"
Eugeni Dodonov85208be2012-04-16 22:20:34 -030049
Jani Nikulaa10510a2020-02-27 19:00:47 +020050/* Stores plane specific WM parameters */
51struct skl_wm_params {
52 bool x_tiled, y_tiled;
53 bool rc_surface;
54 bool is_planar;
55 u32 width;
56 u8 cpp;
57 u32 plane_pixel_rate;
58 u32 y_min_scanlines;
59 u32 plane_bytes_per_line;
60 uint_fixed_16_16_t plane_blocks_per_line;
61 uint_fixed_16_16_t y_tile_minimum;
62 u32 linetime_us;
63 u32 dbuf_block_size;
64};
65
66/* used in computing the new watermarks state */
67struct intel_wm_config {
68 unsigned int num_pipes_active;
69 bool sprites_enabled;
70 bool sprites_scaled;
71};
72
Ville Syrjälä46f16e62016-10-31 22:37:22 +020073static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
Mika Kuoppalab033bb62016-06-07 17:19:04 +030074{
Ville Syrjälä93564042017-08-24 22:10:51 +030075 if (HAS_LLC(dev_priv)) {
76 /*
77 * WaCompressedResourceDisplayNewHashMode:skl,kbl
Lucas De Marchie0403cb2017-12-05 11:01:17 -080078 * Display WA #0390: skl,kbl
Ville Syrjälä93564042017-08-24 22:10:51 +030079 *
80 * Must match Sampler, Pixel Back End, and Media. See
81 * WaCompressedResourceSamplerPbeMediaNewHashMode.
82 */
83 I915_WRITE(CHICKEN_PAR1_1,
84 I915_READ(CHICKEN_PAR1_1) |
85 SKL_DE_COMPRESSED_HASH_MODE);
86 }
87
Rodrigo Vivi82525c12017-06-08 08:50:00 -070088 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
Mika Kuoppalab033bb62016-06-07 17:19:04 +030089 I915_WRITE(CHICKEN_PAR1_1,
90 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
91
Rodrigo Vivi82525c12017-06-08 08:50:00 -070092 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
Mika Kuoppala590e8ff2016-06-07 17:19:13 +030093 I915_WRITE(GEN8_CHICKEN_DCPR_1,
94 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
Mika Kuoppala0f78dee2016-06-07 17:19:16 +030095
Rodrigo Vivi82525c12017-06-08 08:50:00 -070096 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
97 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
Mika Kuoppala303d4ea2016-06-07 17:19:17 +030098 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
99 DISP_FBC_WM_DIS |
100 DISP_FBC_MEMORY_WAKE);
Mika Kuoppalad1b4eef2016-06-07 17:19:19 +0300101
Rodrigo Vivi82525c12017-06-08 08:50:00 -0700102 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
Mika Kuoppalad1b4eef2016-06-07 17:19:19 +0300103 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
104 ILK_DPFC_DISABLE_DUMMY0);
Praveen Paneri32087d12017-08-03 23:02:10 +0530105
106 if (IS_SKYLAKE(dev_priv)) {
107 /* WaDisableDopClockGating */
108 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
109 & ~GEN7_DOP_CLOCK_GATE_ENABLE);
110 }
Mika Kuoppalab033bb62016-06-07 17:19:04 +0300111}
112
Ville Syrjälä46f16e62016-10-31 22:37:22 +0200113static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
Imre Deaka82abe42015-03-27 14:00:04 +0200114{
Ville Syrjälä46f16e62016-10-31 22:37:22 +0200115 gen9_init_clock_gating(dev_priv);
Daniel Vetterdc00b6a2016-05-19 09:14:20 +0200116
Nick Hoatha7546152015-06-29 14:07:32 +0100117 /* WaDisableSDEUnitClockGating:bxt */
118 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
119 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
120
Imre Deak32608ca2015-03-11 11:10:27 +0200121 /*
122 * FIXME:
Ben Widawsky868434c2015-03-11 10:49:32 +0200123 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
Imre Deak32608ca2015-03-11 11:10:27 +0200124 */
Imre Deak32608ca2015-03-11 11:10:27 +0200125 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
Ben Widawsky868434c2015-03-11 10:49:32 +0200126 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
Imre Deakd965e7ac2015-12-01 10:23:52 +0200127
128 /*
129 * Wa: Backlight PWM may stop in the asserted state, causing backlight
130 * to stay fully on.
131 */
Jani Nikula8aeaf642017-02-15 17:21:37 +0200132 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
133 PWM1_GATING_DIS | PWM2_GATING_DIS);
Uma Shankar1d85a292018-08-07 21:15:35 +0530134
135 /*
136 * Lower the display internal timeout.
137 * This is needed to avoid any hard hangs when DSI port PLL
138 * is off and a MMIO access is attempted by any privilege
139 * application, using batch buffers or any other means.
140 */
141 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
Imre Deaka82abe42015-03-27 14:00:04 +0200142}
143
Ander Conselvan de Oliveira9fb50262017-01-26 11:16:58 +0200144static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
145{
146 gen9_init_clock_gating(dev_priv);
147
148 /*
149 * WaDisablePWMClockGating:glk
150 * Backlight PWM may stop in the asserted state, causing backlight
151 * to stay fully on.
152 */
153 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
154 PWM1_GATING_DIS | PWM2_GATING_DIS);
155}
156
Lucas De Marchi1d218222019-12-24 00:40:04 -0800157static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
Daniel Vetterc921aba2012-04-26 23:28:17 +0200158{
Daniel Vetterc921aba2012-04-26 23:28:17 +0200159 u32 tmp;
160
161 tmp = I915_READ(CLKCFG);
162
163 switch (tmp & CLKCFG_FSB_MASK) {
164 case CLKCFG_FSB_533:
165 dev_priv->fsb_freq = 533; /* 133*4 */
166 break;
167 case CLKCFG_FSB_800:
168 dev_priv->fsb_freq = 800; /* 200*4 */
169 break;
170 case CLKCFG_FSB_667:
171 dev_priv->fsb_freq = 667; /* 167*4 */
172 break;
173 case CLKCFG_FSB_400:
174 dev_priv->fsb_freq = 400; /* 100*4 */
175 break;
176 }
177
178 switch (tmp & CLKCFG_MEM_MASK) {
179 case CLKCFG_MEM_533:
180 dev_priv->mem_freq = 533;
181 break;
182 case CLKCFG_MEM_667:
183 dev_priv->mem_freq = 667;
184 break;
185 case CLKCFG_MEM_800:
186 dev_priv->mem_freq = 800;
187 break;
188 }
189
190 /* detect pineview DDR3 setting */
191 tmp = I915_READ(CSHRDDR3CTL);
192 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
193}
194
Lucas De Marchi9eae5e22019-12-24 00:40:09 -0800195static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
Daniel Vetterc921aba2012-04-26 23:28:17 +0200196{
Daniel Vetterc921aba2012-04-26 23:28:17 +0200197 u16 ddrpll, csipll;
198
Tvrtko Ursulin4f5fd912019-06-11 11:45:48 +0100199 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
200 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
Daniel Vetterc921aba2012-04-26 23:28:17 +0200201
202 switch (ddrpll & 0xff) {
203 case 0xc:
204 dev_priv->mem_freq = 800;
205 break;
206 case 0x10:
207 dev_priv->mem_freq = 1066;
208 break;
209 case 0x14:
210 dev_priv->mem_freq = 1333;
211 break;
212 case 0x18:
213 dev_priv->mem_freq = 1600;
214 break;
215 default:
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300216 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
217 ddrpll & 0xff);
Daniel Vetterc921aba2012-04-26 23:28:17 +0200218 dev_priv->mem_freq = 0;
219 break;
220 }
221
Daniel Vetterc921aba2012-04-26 23:28:17 +0200222 switch (csipll & 0x3ff) {
223 case 0x00c:
224 dev_priv->fsb_freq = 3200;
225 break;
226 case 0x00e:
227 dev_priv->fsb_freq = 3733;
228 break;
229 case 0x010:
230 dev_priv->fsb_freq = 4266;
231 break;
232 case 0x012:
233 dev_priv->fsb_freq = 4800;
234 break;
235 case 0x014:
236 dev_priv->fsb_freq = 5333;
237 break;
238 case 0x016:
239 dev_priv->fsb_freq = 5866;
240 break;
241 case 0x018:
242 dev_priv->fsb_freq = 6400;
243 break;
244 default:
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300245 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
246 csipll & 0x3ff);
Daniel Vetterc921aba2012-04-26 23:28:17 +0200247 dev_priv->fsb_freq = 0;
248 break;
249 }
Daniel Vetterc921aba2012-04-26 23:28:17 +0200250}
251
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300252static const struct cxsr_latency cxsr_latency_table[] = {
253 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
254 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
255 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
256 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
257 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
258
259 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
260 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
261 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
262 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
263 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
264
265 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
266 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
267 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
268 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
269 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
270
271 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
272 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
273 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
274 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
275 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
276
277 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
278 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
279 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
280 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
281 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
282
283 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
284 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
285 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
286 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
287 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
288};
289
Tvrtko Ursulin44a655c2016-10-13 11:09:23 +0100290static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
291 bool is_ddr3,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300292 int fsb,
293 int mem)
294{
295 const struct cxsr_latency *latency;
296 int i;
297
298 if (fsb == 0 || mem == 0)
299 return NULL;
300
301 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
302 latency = &cxsr_latency_table[i];
303 if (is_desktop == latency->is_desktop &&
304 is_ddr3 == latency->is_ddr3 &&
305 fsb == latency->fsb_freq && mem == latency->mem_freq)
306 return latency;
307 }
308
309 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
310
311 return NULL;
312}
313
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200314static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
315{
316 u32 val;
317
Chris Wilson337fa6e2019-04-26 09:17:20 +0100318 vlv_punit_get(dev_priv);
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200319
320 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
321 if (enable)
322 val &= ~FORCE_DDR_HIGH_FREQ;
323 else
324 val |= FORCE_DDR_HIGH_FREQ;
325 val &= ~FORCE_DDR_LOW_FREQ;
326 val |= FORCE_DDR_FREQ_REQ_ACK;
327 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
328
329 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
330 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300331 drm_err(&dev_priv->drm,
332 "timed out waiting for Punit DDR DVFS request\n");
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200333
Chris Wilson337fa6e2019-04-26 09:17:20 +0100334 vlv_punit_put(dev_priv);
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200335}
336
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200337static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
338{
339 u32 val;
340
Chris Wilson337fa6e2019-04-26 09:17:20 +0100341 vlv_punit_get(dev_priv);
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200342
Ville Syrjäläc11b8132018-11-29 19:55:03 +0200343 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200344 if (enable)
345 val |= DSP_MAXFIFO_PM5_ENABLE;
346 else
347 val &= ~DSP_MAXFIFO_PM5_ENABLE;
Ville Syrjäläc11b8132018-11-29 19:55:03 +0200348 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200349
Chris Wilson337fa6e2019-04-26 09:17:20 +0100350 vlv_punit_put(dev_priv);
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200351}
352
Ville Syrjäläf4998962015-03-10 17:02:21 +0200353#define FW_WM(value, plane) \
354 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
355
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200356static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300357{
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200358 bool was_enabled;
Imre Deak5209b1f2014-07-01 12:36:17 +0300359 u32 val;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300360
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100361 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200362 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
Imre Deak5209b1f2014-07-01 12:36:17 +0300363 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300364 POSTING_READ(FW_BLC_SELF_VLV);
Jani Nikulac0f86832016-12-07 12:13:04 +0200365 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200366 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
Imre Deak5209b1f2014-07-01 12:36:17 +0300367 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300368 POSTING_READ(FW_BLC_SELF);
Ville Syrjälä9b1e14f2016-10-31 22:37:15 +0200369 } else if (IS_PINEVIEW(dev_priv)) {
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200370 val = I915_READ(DSPFW3);
371 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
372 if (enable)
373 val |= PINEVIEW_SELF_REFRESH_EN;
374 else
375 val &= ~PINEVIEW_SELF_REFRESH_EN;
Imre Deak5209b1f2014-07-01 12:36:17 +0300376 I915_WRITE(DSPFW3, val);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300377 POSTING_READ(DSPFW3);
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100378 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200379 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
Imre Deak5209b1f2014-07-01 12:36:17 +0300380 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
381 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
382 I915_WRITE(FW_BLC_SELF, val);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300383 POSTING_READ(FW_BLC_SELF);
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100384 } else if (IS_I915GM(dev_priv)) {
Ville Syrjäläacb91352016-07-29 17:57:02 +0300385 /*
386 * FIXME can't find a bit like this for 915G, and
387 * and yet it does have the related watermark in
388 * FW_BLC_SELF. What's going on?
389 */
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200390 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
Imre Deak5209b1f2014-07-01 12:36:17 +0300391 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
392 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
393 I915_WRITE(INSTPM, val);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300394 POSTING_READ(INSTPM);
Imre Deak5209b1f2014-07-01 12:36:17 +0300395 } else {
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200396 return false;
Imre Deak5209b1f2014-07-01 12:36:17 +0300397 }
398
Ville Syrjälä1489bba2017-03-02 19:15:07 +0200399 trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
400
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300401 drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
402 enableddisabled(enable),
403 enableddisabled(was_enabled));
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200404
405 return was_enabled;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300406}
407
Ville Syrjälä62571fc2017-04-21 21:14:23 +0300408/**
409 * intel_set_memory_cxsr - Configure CxSR state
410 * @dev_priv: i915 device
411 * @enable: Allow vs. disallow CxSR
412 *
413 * Allow or disallow the system to enter a special CxSR
414 * (C-state self refresh) state. What typically happens in CxSR mode
415 * is that several display FIFOs may get combined into a single larger
416 * FIFO for a particular plane (so called max FIFO mode) to allow the
417 * system to defer memory fetches longer, and the memory will enter
418 * self refresh.
419 *
420 * Note that enabling CxSR does not guarantee that the system enter
421 * this special mode, nor does it guarantee that the system stays
422 * in that mode once entered. So this just allows/disallows the system
423 * to autonomously utilize the CxSR mode. Other factors such as core
424 * C-states will affect when/if the system actually enters/exits the
425 * CxSR mode.
426 *
427 * Note that on VLV/CHV this actually only controls the max FIFO mode,
428 * and the system is free to enter/exit memory self refresh at any time
429 * even when the use of CxSR has been disallowed.
430 *
431 * While the system is actually in the CxSR/max FIFO mode, some plane
432 * control registers will not get latched on vblank. Thus in order to
433 * guarantee the system will respond to changes in the plane registers
434 * we must always disallow CxSR prior to making changes to those registers.
435 * Unfortunately the system will re-evaluate the CxSR conditions at
436 * frame start which happens after vblank start (which is when the plane
437 * registers would get latched), so we can't proceed with the plane update
438 * during the same frame where we disallowed CxSR.
439 *
440 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
441 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
442 * the hardware w.r.t. HPLL SR when writing to plane registers.
443 * Disallowing just CxSR is sufficient.
444 */
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200445bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
Ville Syrjälä3d90e642016-11-28 19:37:11 +0200446{
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200447 bool ret;
448
Ville Syrjälä3d90e642016-11-28 19:37:11 +0200449 mutex_lock(&dev_priv->wm.wm_mutex);
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200450 ret = _intel_set_memory_cxsr(dev_priv, enable);
Ville Syrjälä04548cb2017-04-21 21:14:29 +0300451 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
452 dev_priv->wm.vlv.cxsr = enable;
453 else if (IS_G4X(dev_priv))
454 dev_priv->wm.g4x.cxsr = enable;
Ville Syrjälä3d90e642016-11-28 19:37:11 +0200455 mutex_unlock(&dev_priv->wm.wm_mutex);
Ville Syrjälä11a85d62016-11-28 19:37:12 +0200456
457 return ret;
Ville Syrjälä3d90e642016-11-28 19:37:11 +0200458}
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200459
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300460/*
461 * Latency for FIFO fetches is dependent on several factors:
462 * - memory configuration (speed, channels)
463 * - chipset
464 * - current MCH state
465 * It can be fairly high in some situations, so here we assume a fairly
466 * pessimal value. It's a tradeoff between extra memory fetches (if we
467 * set this value too high, the FIFO will fetch frequently to stay full)
468 * and power consumption (set it too low to save power and we might see
469 * FIFO underruns and display "flicker").
470 *
471 * A value of 5us seems to be a good balance; safe for very low end
472 * platforms but not overly aggressive on lower latency configs.
473 */
Chris Wilson5aef6002014-09-03 11:56:07 +0100474static const int pessimal_latency_ns = 5000;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300475
Ville Syrjäläb5004722015-03-05 21:19:47 +0200476#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
477 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
478
Ville Syrjälä814e7f02017-03-02 19:14:55 +0200479static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
Ville Syrjäläb5004722015-03-05 21:19:47 +0200480{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +0100481 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Ville Syrjäläf07d43d2017-03-02 19:14:52 +0200482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä814e7f02017-03-02 19:14:55 +0200483 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
Ville Syrjäläf07d43d2017-03-02 19:14:52 +0200484 enum pipe pipe = crtc->pipe;
485 int sprite0_start, sprite1_start;
Kees Cook2713eb42020-02-20 16:05:17 -0800486 u32 dsparb, dsparb2, dsparb3;
Ville Syrjäläb5004722015-03-05 21:19:47 +0200487
Ville Syrjäläf07d43d2017-03-02 19:14:52 +0200488 switch (pipe) {
Ville Syrjäläb5004722015-03-05 21:19:47 +0200489 case PIPE_A:
490 dsparb = I915_READ(DSPARB);
491 dsparb2 = I915_READ(DSPARB2);
492 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
493 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
494 break;
495 case PIPE_B:
496 dsparb = I915_READ(DSPARB);
497 dsparb2 = I915_READ(DSPARB2);
498 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
499 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
500 break;
501 case PIPE_C:
502 dsparb2 = I915_READ(DSPARB2);
503 dsparb3 = I915_READ(DSPARB3);
504 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
505 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
506 break;
507 default:
Ville Syrjäläf07d43d2017-03-02 19:14:52 +0200508 MISSING_CASE(pipe);
509 return;
Ville Syrjäläb5004722015-03-05 21:19:47 +0200510 }
511
Ville Syrjäläf07d43d2017-03-02 19:14:52 +0200512 fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
513 fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
514 fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
515 fifo_state->plane[PLANE_CURSOR] = 63;
Ville Syrjäläb5004722015-03-05 21:19:47 +0200516}
517
Ville Syrjäläbdaf8432017-11-17 21:19:11 +0200518static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
519 enum i9xx_plane_id i9xx_plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300520{
Jani Nikula5ce9a6492019-01-18 14:01:20 +0200521 u32 dsparb = I915_READ(DSPARB);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300522 int size;
523
524 size = dsparb & 0x7f;
Ville Syrjäläbdaf8432017-11-17 21:19:11 +0200525 if (i9xx_plane == PLANE_B)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300526 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
527
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300528 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
529 dsparb, plane_name(i9xx_plane), size);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300530
531 return size;
532}
533
Ville Syrjäläbdaf8432017-11-17 21:19:11 +0200534static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
535 enum i9xx_plane_id i9xx_plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300536{
Jani Nikula5ce9a6492019-01-18 14:01:20 +0200537 u32 dsparb = I915_READ(DSPARB);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300538 int size;
539
540 size = dsparb & 0x1ff;
Ville Syrjäläbdaf8432017-11-17 21:19:11 +0200541 if (i9xx_plane == PLANE_B)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300542 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
543 size >>= 1; /* Convert to cachelines */
544
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300545 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
546 dsparb, plane_name(i9xx_plane), size);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300547
548 return size;
549}
550
Ville Syrjäläbdaf8432017-11-17 21:19:11 +0200551static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
552 enum i9xx_plane_id i9xx_plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300553{
Jani Nikula5ce9a6492019-01-18 14:01:20 +0200554 u32 dsparb = I915_READ(DSPARB);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300555 int size;
556
557 size = dsparb & 0x7f;
558 size >>= 2; /* Convert to cachelines */
559
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300560 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
561 dsparb, plane_name(i9xx_plane), size);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300562
563 return size;
564}
565
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300566/* Pineview has different values for various configs */
Lucas De Marchi1d218222019-12-24 00:40:04 -0800567static const struct intel_watermark_params pnv_display_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300568 .fifo_size = PINEVIEW_DISPLAY_FIFO,
569 .max_wm = PINEVIEW_MAX_WM,
570 .default_wm = PINEVIEW_DFT_WM,
571 .guard_size = PINEVIEW_GUARD_WM,
572 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300573};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800574
575static const struct intel_watermark_params pnv_display_hplloff_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300576 .fifo_size = PINEVIEW_DISPLAY_FIFO,
577 .max_wm = PINEVIEW_MAX_WM,
578 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
579 .guard_size = PINEVIEW_GUARD_WM,
580 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300581};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800582
583static const struct intel_watermark_params pnv_cursor_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300584 .fifo_size = PINEVIEW_CURSOR_FIFO,
585 .max_wm = PINEVIEW_CURSOR_MAX_WM,
586 .default_wm = PINEVIEW_CURSOR_DFT_WM,
587 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
588 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300589};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800590
591static const struct intel_watermark_params pnv_cursor_hplloff_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300592 .fifo_size = PINEVIEW_CURSOR_FIFO,
593 .max_wm = PINEVIEW_CURSOR_MAX_WM,
594 .default_wm = PINEVIEW_CURSOR_DFT_WM,
595 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
596 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300597};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800598
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300599static const struct intel_watermark_params i965_cursor_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300600 .fifo_size = I965_CURSOR_FIFO,
601 .max_wm = I965_CURSOR_MAX_WM,
602 .default_wm = I965_CURSOR_DFT_WM,
603 .guard_size = 2,
604 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300605};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800606
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300607static const struct intel_watermark_params i945_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300608 .fifo_size = I945_FIFO_SIZE,
609 .max_wm = I915_MAX_WM,
610 .default_wm = 1,
611 .guard_size = 2,
612 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300613};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800614
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300615static const struct intel_watermark_params i915_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300616 .fifo_size = I915_FIFO_SIZE,
617 .max_wm = I915_MAX_WM,
618 .default_wm = 1,
619 .guard_size = 2,
620 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300621};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800622
Ville Syrjälä9d539102014-08-15 01:21:53 +0300623static const struct intel_watermark_params i830_a_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300624 .fifo_size = I855GM_FIFO_SIZE,
625 .max_wm = I915_MAX_WM,
626 .default_wm = 1,
627 .guard_size = 2,
628 .cacheline_size = I830_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300629};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800630
Ville Syrjälä9d539102014-08-15 01:21:53 +0300631static const struct intel_watermark_params i830_bc_wm_info = {
632 .fifo_size = I855GM_FIFO_SIZE,
633 .max_wm = I915_MAX_WM/2,
634 .default_wm = 1,
635 .guard_size = 2,
636 .cacheline_size = I830_FIFO_LINE_SIZE,
637};
Lucas De Marchi1d218222019-12-24 00:40:04 -0800638
Daniel Vetterfeb56b92013-12-14 20:38:30 -0200639static const struct intel_watermark_params i845_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300640 .fifo_size = I830_FIFO_SIZE,
641 .max_wm = I915_MAX_WM,
642 .default_wm = 1,
643 .guard_size = 2,
644 .cacheline_size = I830_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300645};
646
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300647/**
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300648 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
649 * @pixel_rate: Pipe pixel rate in kHz
650 * @cpp: Plane bytes per pixel
651 * @latency: Memory wakeup latency in 0.1us units
652 *
653 * Compute the watermark using the method 1 or "small buffer"
654 * formula. The caller may additonally add extra cachelines
655 * to account for TLB misses and clock crossings.
656 *
657 * This method is concerned with the short term drain rate
658 * of the FIFO, ie. it does not account for blanking periods
659 * which would effectively reduce the average drain rate across
660 * a longer period. The name "small" refers to the fact the
661 * FIFO is relatively small compared to the amount of data
662 * fetched.
663 *
664 * The FIFO level vs. time graph might look something like:
665 *
666 * |\ |\
667 * | \ | \
668 * __---__---__ (- plane active, _ blanking)
669 * -> time
670 *
671 * or perhaps like this:
672 *
673 * |\|\ |\|\
674 * __----__----__ (- plane active, _ blanking)
675 * -> time
676 *
677 * Returns:
678 * The watermark in bytes
679 */
680static unsigned int intel_wm_method1(unsigned int pixel_rate,
681 unsigned int cpp,
682 unsigned int latency)
683{
Jani Nikula5ce9a6492019-01-18 14:01:20 +0200684 u64 ret;
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300685
Ville Syrjäläd492a292019-04-08 18:27:01 +0300686 ret = mul_u32_u32(pixel_rate, cpp * latency);
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300687 ret = DIV_ROUND_UP_ULL(ret, 10000);
688
689 return ret;
690}
691
692/**
693 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
694 * @pixel_rate: Pipe pixel rate in kHz
695 * @htotal: Pipe horizontal total
696 * @width: Plane width in pixels
697 * @cpp: Plane bytes per pixel
698 * @latency: Memory wakeup latency in 0.1us units
699 *
700 * Compute the watermark using the method 2 or "large buffer"
701 * formula. The caller may additonally add extra cachelines
702 * to account for TLB misses and clock crossings.
703 *
704 * This method is concerned with the long term drain rate
705 * of the FIFO, ie. it does account for blanking periods
706 * which effectively reduce the average drain rate across
707 * a longer period. The name "large" refers to the fact the
708 * FIFO is relatively large compared to the amount of data
709 * fetched.
710 *
711 * The FIFO level vs. time graph might look something like:
712 *
713 * |\___ |\___
714 * | \___ | \___
715 * | \ | \
716 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
717 * -> time
718 *
719 * Returns:
720 * The watermark in bytes
721 */
722static unsigned int intel_wm_method2(unsigned int pixel_rate,
723 unsigned int htotal,
724 unsigned int width,
725 unsigned int cpp,
726 unsigned int latency)
727{
728 unsigned int ret;
729
730 /*
731 * FIXME remove once all users are computing
732 * watermarks in the correct place.
733 */
734 if (WARN_ON_ONCE(htotal == 0))
735 htotal = 1;
736
737 ret = (latency * pixel_rate) / (htotal * 10000);
738 ret = (ret + 1) * width * cpp;
739
740 return ret;
741}
742
743/**
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300744 * intel_calculate_wm - calculate watermark level
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300745 * @pixel_rate: pixel clock
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300746 * @wm: chip FIFO params
Chris Wilson31383412018-02-14 14:03:03 +0000747 * @fifo_size: size of the FIFO buffer
Ville Syrjäläac484962016-01-20 21:05:26 +0200748 * @cpp: bytes per pixel
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300749 * @latency_ns: memory latency for the platform
750 *
751 * Calculate the watermark level (the level at which the display plane will
752 * start fetching from memory again). Each chip has a different display
753 * FIFO size and allocation, so the caller needs to figure that out and pass
754 * in the correct intel_watermark_params structure.
755 *
756 * As the pixel clock runs, the FIFO will be drained at a rate that depends
757 * on the pixel size. When it reaches the watermark level, it'll start
758 * fetching FIFO line sized based chunks from memory until the FIFO fills
759 * past the watermark point. If the FIFO drains completely, a FIFO underrun
760 * will occur, and a display engine hang could result.
761 */
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300762static unsigned int intel_calculate_wm(int pixel_rate,
763 const struct intel_watermark_params *wm,
764 int fifo_size, int cpp,
765 unsigned int latency_ns)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300766{
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300767 int entries, wm_size;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300768
769 /*
770 * Note: we need to make sure we don't overflow for various clock &
771 * latency values.
772 * clocks go from a few thousand to several hundred thousand.
773 * latency is usually a few thousand
774 */
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300775 entries = intel_wm_method1(pixel_rate, cpp,
776 latency_ns / 100);
777 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
778 wm->guard_size;
779 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300780
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300781 wm_size = fifo_size - entries;
782 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300783
784 /* Don't promote wm_size to unsigned... */
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300785 if (wm_size > wm->max_wm)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300786 wm_size = wm->max_wm;
787 if (wm_size <= 0)
788 wm_size = wm->default_wm;
Ville Syrjäläd6feb192014-09-05 21:54:13 +0300789
790 /*
791 * Bspec seems to indicate that the value shouldn't be lower than
792 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
793 * Lets go for 8 which is the burst size since certain platforms
794 * already use a hardcoded 8 (which is what the spec says should be
795 * done).
796 */
797 if (wm_size <= 8)
798 wm_size = 8;
799
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300800 return wm_size;
801}
802
Ville Syrjälä04548cb2017-04-21 21:14:29 +0300803static bool is_disabling(int old, int new, int threshold)
804{
805 return old >= threshold && new < threshold;
806}
807
808static bool is_enabling(int old, int new, int threshold)
809{
810 return old < threshold && new >= threshold;
811}
812
Ville Syrjälä6d5019b2017-04-21 21:14:20 +0300813static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
814{
815 return dev_priv->wm.max_level + 1;
816}
817
Ville Syrjälä24304d812017-03-14 17:10:49 +0200818static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
819 const struct intel_plane_state *plane_state)
820{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +0100821 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Ville Syrjälä24304d812017-03-14 17:10:49 +0200822
823 /* FIXME check the 'enable' instead */
Maarten Lankhorst1326a922019-10-31 12:26:02 +0100824 if (!crtc_state->hw.active)
Ville Syrjälä24304d812017-03-14 17:10:49 +0200825 return false;
826
827 /*
828 * Treat cursor with fb as always visible since cursor updates
829 * can happen faster than the vrefresh rate, and the current
830 * watermark code doesn't handle that correctly. Cursor updates
831 * which set/clear the fb or change the cursor size are going
832 * to get throttled by intel_legacy_cursor_update() to work
833 * around this problem with the watermark code.
834 */
835 if (plane->id == PLANE_CURSOR)
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +0100836 return plane_state->hw.fb != NULL;
Ville Syrjälä24304d812017-03-14 17:10:49 +0200837 else
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +0100838 return plane_state->uapi.visible;
Ville Syrjälä24304d812017-03-14 17:10:49 +0200839}
840
Ville Syrjälä04da7b92019-11-27 22:12:11 +0200841static bool intel_crtc_active(struct intel_crtc *crtc)
842{
843 /* Be paranoid as we can arrive here with only partial
844 * state retrieved from the hardware during setup.
845 *
846 * We can ditch the adjusted_mode.crtc_clock check as soon
847 * as Haswell has gained clock readout/fastboot support.
848 *
849 * We can ditch the crtc->primary->state->fb check as soon as we can
850 * properly reconstruct framebuffers.
851 *
852 * FIXME: The intel_crtc->active here should be switched to
853 * crtc->state->active once we have proper CRTC states wired up
854 * for atomic.
855 */
856 return crtc->active && crtc->base.primary->state->fb &&
857 crtc->config->hw.adjusted_mode.crtc_clock;
858}
859
Ville Syrjäläffc7a762016-10-31 22:37:21 +0200860static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300861{
Ville Syrjäläefc26112016-10-31 22:37:04 +0200862 struct intel_crtc *crtc, *enabled = NULL;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300863
Ville Syrjäläffc7a762016-10-31 22:37:21 +0200864 for_each_intel_crtc(&dev_priv->drm, crtc) {
Ville Syrjäläefc26112016-10-31 22:37:04 +0200865 if (intel_crtc_active(crtc)) {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300866 if (enabled)
867 return NULL;
868 enabled = crtc;
869 }
870 }
871
872 return enabled;
873}
874
Lucas De Marchi1d218222019-12-24 00:40:04 -0800875static void pnv_update_wm(struct intel_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300876{
Ville Syrjäläffc7a762016-10-31 22:37:21 +0200877 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
Ville Syrjäläefc26112016-10-31 22:37:04 +0200878 struct intel_crtc *crtc;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300879 const struct cxsr_latency *latency;
880 u32 reg;
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +0300881 unsigned int wm;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300882
Tvrtko Ursulin86d35d42019-03-26 07:40:54 +0000883 latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100884 dev_priv->is_ddr3,
885 dev_priv->fsb_freq,
886 dev_priv->mem_freq);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300887 if (!latency) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300888 drm_dbg_kms(&dev_priv->drm,
889 "Unknown FSB/MEM found, disable CxSR\n");
Imre Deak5209b1f2014-07-01 12:36:17 +0300890 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300891 return;
892 }
893
Ville Syrjäläffc7a762016-10-31 22:37:21 +0200894 crtc = single_enabled_crtc(dev_priv);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300895 if (crtc) {
Ville Syrjäläefc26112016-10-31 22:37:04 +0200896 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +0100897 &crtc->config->hw.adjusted_mode;
Ville Syrjäläefc26112016-10-31 22:37:04 +0200898 const struct drm_framebuffer *fb =
899 crtc->base.primary->state->fb;
Ville Syrjälä353c8592016-12-14 23:30:57 +0200900 int cpp = fb->format->cpp[0];
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300901 int clock = adjusted_mode->crtc_clock;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300902
903 /* Display SR */
Lucas De Marchi1d218222019-12-24 00:40:04 -0800904 wm = intel_calculate_wm(clock, &pnv_display_wm,
905 pnv_display_wm.fifo_size,
Ville Syrjäläac484962016-01-20 21:05:26 +0200906 cpp, latency->display_sr);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300907 reg = I915_READ(DSPFW1);
908 reg &= ~DSPFW_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200909 reg |= FW_WM(wm, SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300910 I915_WRITE(DSPFW1, reg);
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300911 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300912
913 /* cursor SR */
Lucas De Marchi1d218222019-12-24 00:40:04 -0800914 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
915 pnv_display_wm.fifo_size,
Ville Syrjälä99834b12017-04-21 21:14:24 +0300916 4, latency->cursor_sr);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300917 reg = I915_READ(DSPFW3);
918 reg &= ~DSPFW_CURSOR_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200919 reg |= FW_WM(wm, CURSOR_SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300920 I915_WRITE(DSPFW3, reg);
921
922 /* Display HPLL off SR */
Lucas De Marchi1d218222019-12-24 00:40:04 -0800923 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
924 pnv_display_hplloff_wm.fifo_size,
Ville Syrjäläac484962016-01-20 21:05:26 +0200925 cpp, latency->display_hpll_disable);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300926 reg = I915_READ(DSPFW3);
927 reg &= ~DSPFW_HPLL_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200928 reg |= FW_WM(wm, HPLL_SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300929 I915_WRITE(DSPFW3, reg);
930
931 /* cursor HPLL off SR */
Lucas De Marchi1d218222019-12-24 00:40:04 -0800932 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
933 pnv_display_hplloff_wm.fifo_size,
Ville Syrjälä99834b12017-04-21 21:14:24 +0300934 4, latency->cursor_hpll_disable);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300935 reg = I915_READ(DSPFW3);
936 reg &= ~DSPFW_HPLL_CURSOR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200937 reg |= FW_WM(wm, HPLL_CURSOR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300938 I915_WRITE(DSPFW3, reg);
Wambui Karugaf8d18d52020-01-07 18:13:30 +0300939 drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300940
Imre Deak5209b1f2014-07-01 12:36:17 +0300941 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300942 } else {
Imre Deak5209b1f2014-07-01 12:36:17 +0300943 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300944 }
945}
946
Ville Syrjälä0f95ff82017-04-21 21:14:26 +0300947/*
948 * Documentation says:
949 * "If the line size is small, the TLB fetches can get in the way of the
950 * data fetches, causing some lag in the pixel data return which is not
951 * accounted for in the above formulas. The following adjustment only
952 * needs to be applied if eight whole lines fit in the buffer at once.
953 * The WM is adjusted upwards by the difference between the FIFO size
954 * and the size of 8 whole lines. This adjustment is always performed
955 * in the actual pixel depth regardless of whether FBC is enabled or not."
956 */
Chris Wilson1a1f1282017-11-07 14:03:38 +0000957static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
Ville Syrjälä0f95ff82017-04-21 21:14:26 +0300958{
959 int tlb_miss = fifo_size * 64 - width * cpp * 8;
960
961 return max(0, tlb_miss);
962}
963
Ville Syrjälä04548cb2017-04-21 21:14:29 +0300964static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
965 const struct g4x_wm_values *wm)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300966{
Ville Syrjäläe93329a2017-04-21 21:14:31 +0300967 enum pipe pipe;
968
969 for_each_pipe(dev_priv, pipe)
970 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
971
Ville Syrjälä04548cb2017-04-21 21:14:29 +0300972 I915_WRITE(DSPFW1,
973 FW_WM(wm->sr.plane, SR) |
974 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
975 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
976 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
977 I915_WRITE(DSPFW2,
978 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
979 FW_WM(wm->sr.fbc, FBC_SR) |
980 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
981 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
982 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
983 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
984 I915_WRITE(DSPFW3,
985 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
986 FW_WM(wm->sr.cursor, CURSOR_SR) |
987 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
988 FW_WM(wm->hpll.plane, HPLL_SR));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300989
Ville Syrjälä04548cb2017-04-21 21:14:29 +0300990 POSTING_READ(DSPFW1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300991}
992
Ville Syrjälä15665972015-03-10 16:16:28 +0200993#define FW_WM_VLV(value, plane) \
994 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
995
Ville Syrjälä50f4cae2016-11-28 19:37:15 +0200996static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
Ville Syrjälä0018fda2015-03-05 21:19:45 +0200997 const struct vlv_wm_values *wm)
998{
Ville Syrjälä50f4cae2016-11-28 19:37:15 +0200999 enum pipe pipe;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001000
Ville Syrjälä50f4cae2016-11-28 19:37:15 +02001001 for_each_pipe(dev_priv, pipe) {
Ville Syrjäläc137d662017-03-02 19:15:06 +02001002 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1003
Ville Syrjälä50f4cae2016-11-28 19:37:15 +02001004 I915_WRITE(VLV_DDL(pipe),
1005 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1006 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1007 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1008 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1009 }
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001010
Ville Syrjälä6fe6a7f2016-11-28 19:37:14 +02001011 /*
1012 * Zero the (unused) WM1 watermarks, and also clear all the
1013 * high order bits so that there are no out of bounds values
1014 * present in the registers during the reprogramming.
1015 */
1016 I915_WRITE(DSPHOWM, 0);
1017 I915_WRITE(DSPHOWM1, 0);
1018 I915_WRITE(DSPFW4, 0);
1019 I915_WRITE(DSPFW5, 0);
1020 I915_WRITE(DSPFW6, 0);
1021
Ville Syrjäläae801522015-03-05 21:19:49 +02001022 I915_WRITE(DSPFW1,
Ville Syrjälä15665972015-03-10 16:16:28 +02001023 FW_WM(wm->sr.plane, SR) |
Ville Syrjälä1b313892016-11-28 19:37:08 +02001024 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1025 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1026 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
Ville Syrjäläae801522015-03-05 21:19:49 +02001027 I915_WRITE(DSPFW2,
Ville Syrjälä1b313892016-11-28 19:37:08 +02001028 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1029 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1030 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
Ville Syrjäläae801522015-03-05 21:19:49 +02001031 I915_WRITE(DSPFW3,
Ville Syrjälä15665972015-03-10 16:16:28 +02001032 FW_WM(wm->sr.cursor, CURSOR_SR));
Ville Syrjäläae801522015-03-05 21:19:49 +02001033
1034 if (IS_CHERRYVIEW(dev_priv)) {
1035 I915_WRITE(DSPFW7_CHV,
Ville Syrjälä1b313892016-11-28 19:37:08 +02001036 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1037 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
Ville Syrjäläae801522015-03-05 21:19:49 +02001038 I915_WRITE(DSPFW8_CHV,
Ville Syrjälä1b313892016-11-28 19:37:08 +02001039 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1040 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
Ville Syrjäläae801522015-03-05 21:19:49 +02001041 I915_WRITE(DSPFW9_CHV,
Ville Syrjälä1b313892016-11-28 19:37:08 +02001042 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1043 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
Ville Syrjäläae801522015-03-05 21:19:49 +02001044 I915_WRITE(DSPHOWM,
Ville Syrjälä15665972015-03-10 16:16:28 +02001045 FW_WM(wm->sr.plane >> 9, SR_HI) |
Ville Syrjälä1b313892016-11-28 19:37:08 +02001046 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1047 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1048 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1049 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1050 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1051 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1052 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1053 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1054 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
Ville Syrjäläae801522015-03-05 21:19:49 +02001055 } else {
1056 I915_WRITE(DSPFW7,
Ville Syrjälä1b313892016-11-28 19:37:08 +02001057 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1058 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
Ville Syrjäläae801522015-03-05 21:19:49 +02001059 I915_WRITE(DSPHOWM,
Ville Syrjälä15665972015-03-10 16:16:28 +02001060 FW_WM(wm->sr.plane >> 9, SR_HI) |
Ville Syrjälä1b313892016-11-28 19:37:08 +02001061 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1062 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1063 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1064 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1065 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1066 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
Ville Syrjäläae801522015-03-05 21:19:49 +02001067 }
1068
1069 POSTING_READ(DSPFW1);
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001070}
1071
Ville Syrjälä15665972015-03-10 16:16:28 +02001072#undef FW_WM_VLV
1073
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001074static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1075{
1076 /* all latencies in usec */
1077 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1078 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
Ville Syrjälä79d94302017-04-21 21:14:30 +03001079 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001080
Ville Syrjälä79d94302017-04-21 21:14:30 +03001081 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001082}
1083
1084static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1085{
1086 /*
1087 * DSPCNTR[13] supposedly controls whether the
1088 * primary plane can use the FIFO space otherwise
1089 * reserved for the sprite plane. It's not 100% clear
1090 * what the actual FIFO size is, but it looks like we
1091 * can happily set both primary and sprite watermarks
1092 * up to 127 cachelines. So that would seem to mean
1093 * that either DSPCNTR[13] doesn't do anything, or that
1094 * the total FIFO is >= 256 cachelines in size. Either
1095 * way, we don't seem to have to worry about this
1096 * repartitioning as the maximum watermark value the
1097 * register can hold for each plane is lower than the
1098 * minimum FIFO size.
1099 */
1100 switch (plane_id) {
1101 case PLANE_CURSOR:
1102 return 63;
1103 case PLANE_PRIMARY:
1104 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1105 case PLANE_SPRITE0:
1106 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1107 default:
1108 MISSING_CASE(plane_id);
1109 return 0;
1110 }
1111}
1112
1113static int g4x_fbc_fifo_size(int level)
1114{
1115 switch (level) {
1116 case G4X_WM_LEVEL_SR:
1117 return 7;
1118 case G4X_WM_LEVEL_HPLL:
1119 return 15;
1120 default:
1121 MISSING_CASE(level);
1122 return 0;
1123 }
1124}
1125
Jani Nikula5ce9a6492019-01-18 14:01:20 +02001126static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1127 const struct intel_plane_state *plane_state,
1128 int level)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001129{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01001130 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001131 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1132 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01001133 &crtc_state->hw.adjusted_mode;
Chris Wilson1a1f1282017-11-07 14:03:38 +00001134 unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1135 unsigned int clock, htotal, cpp, width, wm;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001136
1137 if (latency == 0)
1138 return USHRT_MAX;
1139
1140 if (!intel_wm_plane_visible(crtc_state, plane_state))
1141 return 0;
1142
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01001143 cpp = plane_state->hw.fb->format->cpp[0];
Ville Syrjäläd56e8232019-07-03 23:08:22 +03001144
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001145 /*
1146 * Not 100% sure which way ELK should go here as the
1147 * spec only says CL/CTG should assume 32bpp and BW
1148 * doesn't need to. But as these things followed the
1149 * mobile vs. desktop lines on gen3 as well, let's
1150 * assume ELK doesn't need this.
1151 *
1152 * The spec also fails to list such a restriction for
1153 * the HPLL watermark, which seems a little strange.
1154 * Let's use 32bpp for the HPLL watermark as well.
1155 */
1156 if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1157 level != G4X_WM_LEVEL_NORMAL)
Ville Syrjäläd56e8232019-07-03 23:08:22 +03001158 cpp = max(cpp, 4u);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001159
1160 clock = adjusted_mode->crtc_clock;
1161 htotal = adjusted_mode->crtc_htotal;
1162
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01001163 width = drm_rect_width(&plane_state->uapi.dst);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001164
1165 if (plane->id == PLANE_CURSOR) {
1166 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1167 } else if (plane->id == PLANE_PRIMARY &&
1168 level == G4X_WM_LEVEL_NORMAL) {
1169 wm = intel_wm_method1(clock, cpp, latency);
1170 } else {
Chris Wilson1a1f1282017-11-07 14:03:38 +00001171 unsigned int small, large;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001172
1173 small = intel_wm_method1(clock, cpp, latency);
1174 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1175
1176 wm = min(small, large);
1177 }
1178
1179 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1180 width, cpp);
1181
1182 wm = DIV_ROUND_UP(wm, 64) + 2;
1183
Chris Wilson1a1f1282017-11-07 14:03:38 +00001184 return min_t(unsigned int, wm, USHRT_MAX);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001185}
1186
1187static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1188 int level, enum plane_id plane_id, u16 value)
1189{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001190 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001191 bool dirty = false;
1192
1193 for (; level < intel_wm_num_levels(dev_priv); level++) {
1194 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1195
1196 dirty |= raw->plane[plane_id] != value;
1197 raw->plane[plane_id] = value;
1198 }
1199
1200 return dirty;
1201}
1202
1203static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1204 int level, u16 value)
1205{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001206 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001207 bool dirty = false;
1208
1209 /* NORMAL level doesn't have an FBC watermark */
1210 level = max(level, G4X_WM_LEVEL_SR);
1211
1212 for (; level < intel_wm_num_levels(dev_priv); level++) {
1213 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1214
1215 dirty |= raw->fbc != value;
1216 raw->fbc = value;
1217 }
1218
1219 return dirty;
1220}
1221
Maarten Lankhorstec193642019-06-28 10:55:17 +02001222static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1223 const struct intel_plane_state *plane_state,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02001224 u32 pri_val);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001225
1226static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1227 const struct intel_plane_state *plane_state)
1228{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01001229 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Wambui Karugaf8d18d52020-01-07 18:13:30 +03001230 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001231 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1232 enum plane_id plane_id = plane->id;
1233 bool dirty = false;
1234 int level;
1235
1236 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1237 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1238 if (plane_id == PLANE_PRIMARY)
1239 dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1240 goto out;
1241 }
1242
1243 for (level = 0; level < num_levels; level++) {
1244 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1245 int wm, max_wm;
1246
1247 wm = g4x_compute_wm(crtc_state, plane_state, level);
1248 max_wm = g4x_plane_fifo_size(plane_id, level);
1249
1250 if (wm > max_wm)
1251 break;
1252
1253 dirty |= raw->plane[plane_id] != wm;
1254 raw->plane[plane_id] = wm;
1255
1256 if (plane_id != PLANE_PRIMARY ||
1257 level == G4X_WM_LEVEL_NORMAL)
1258 continue;
1259
1260 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1261 raw->plane[plane_id]);
1262 max_wm = g4x_fbc_fifo_size(level);
1263
1264 /*
1265 * FBC wm is not mandatory as we
1266 * can always just disable its use.
1267 */
1268 if (wm > max_wm)
1269 wm = USHRT_MAX;
1270
1271 dirty |= raw->fbc != wm;
1272 raw->fbc = wm;
1273 }
1274
1275 /* mark watermarks as invalid */
1276 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1277
1278 if (plane_id == PLANE_PRIMARY)
1279 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1280
1281 out:
1282 if (dirty) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03001283 drm_dbg_kms(&dev_priv->drm,
1284 "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1285 plane->base.name,
1286 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1287 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1288 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001289
1290 if (plane_id == PLANE_PRIMARY)
Wambui Karugaf8d18d52020-01-07 18:13:30 +03001291 drm_dbg_kms(&dev_priv->drm,
1292 "FBC watermarks: SR=%d, HPLL=%d\n",
1293 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1294 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001295 }
1296
1297 return dirty;
1298}
1299
1300static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1301 enum plane_id plane_id, int level)
1302{
1303 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1304
1305 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1306}
1307
1308static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1309 int level)
1310{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001311 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001312
1313 if (level > dev_priv->wm.max_level)
1314 return false;
1315
1316 return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1317 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1318 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1319}
1320
1321/* mark all levels starting from 'level' as invalid */
1322static void g4x_invalidate_wms(struct intel_crtc *crtc,
1323 struct g4x_wm_state *wm_state, int level)
1324{
1325 if (level <= G4X_WM_LEVEL_NORMAL) {
1326 enum plane_id plane_id;
1327
1328 for_each_plane_id_on_crtc(crtc, plane_id)
1329 wm_state->wm.plane[plane_id] = USHRT_MAX;
1330 }
1331
1332 if (level <= G4X_WM_LEVEL_SR) {
1333 wm_state->cxsr = false;
1334 wm_state->sr.cursor = USHRT_MAX;
1335 wm_state->sr.plane = USHRT_MAX;
1336 wm_state->sr.fbc = USHRT_MAX;
1337 }
1338
1339 if (level <= G4X_WM_LEVEL_HPLL) {
1340 wm_state->hpll_en = false;
1341 wm_state->hpll.cursor = USHRT_MAX;
1342 wm_state->hpll.plane = USHRT_MAX;
1343 wm_state->hpll.fbc = USHRT_MAX;
1344 }
1345}
1346
1347static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1348{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001349 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001350 struct intel_atomic_state *state =
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001351 to_intel_atomic_state(crtc_state->uapi.state);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001352 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
Ville Syrjälä0b14d962019-08-21 20:30:33 +03001353 int num_active_planes = hweight8(crtc_state->active_planes &
1354 ~BIT(PLANE_CURSOR));
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001355 const struct g4x_pipe_wm *raw;
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001356 const struct intel_plane_state *old_plane_state;
1357 const struct intel_plane_state *new_plane_state;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001358 struct intel_plane *plane;
1359 enum plane_id plane_id;
1360 int i, level;
1361 unsigned int dirty = 0;
1362
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001363 for_each_oldnew_intel_plane_in_state(state, plane,
1364 old_plane_state,
1365 new_plane_state, i) {
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01001366 if (new_plane_state->hw.crtc != &crtc->base &&
1367 old_plane_state->hw.crtc != &crtc->base)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001368 continue;
1369
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001370 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001371 dirty |= BIT(plane->id);
1372 }
1373
1374 if (!dirty)
1375 return 0;
1376
1377 level = G4X_WM_LEVEL_NORMAL;
1378 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1379 goto out;
1380
1381 raw = &crtc_state->wm.g4x.raw[level];
1382 for_each_plane_id_on_crtc(crtc, plane_id)
1383 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1384
1385 level = G4X_WM_LEVEL_SR;
1386
1387 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1388 goto out;
1389
1390 raw = &crtc_state->wm.g4x.raw[level];
1391 wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1392 wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1393 wm_state->sr.fbc = raw->fbc;
1394
1395 wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1396
1397 level = G4X_WM_LEVEL_HPLL;
1398
1399 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1400 goto out;
1401
1402 raw = &crtc_state->wm.g4x.raw[level];
1403 wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1404 wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1405 wm_state->hpll.fbc = raw->fbc;
1406
1407 wm_state->hpll_en = wm_state->cxsr;
1408
1409 level++;
1410
1411 out:
1412 if (level == G4X_WM_LEVEL_NORMAL)
1413 return -EINVAL;
1414
1415 /* invalidate the higher levels */
1416 g4x_invalidate_wms(crtc, wm_state, level);
1417
1418 /*
1419 * Determine if the FBC watermark(s) can be used. IF
1420 * this isn't the case we prefer to disable the FBC
1421 ( watermark(s) rather than disable the SR/HPLL
1422 * level(s) entirely.
1423 */
1424 wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1425
1426 if (level >= G4X_WM_LEVEL_SR &&
1427 wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1428 wm_state->fbc_en = false;
1429 else if (level >= G4X_WM_LEVEL_HPLL &&
1430 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1431 wm_state->fbc_en = false;
1432
1433 return 0;
1434}
1435
Matt Ropercd1d3ee2018-12-10 13:54:14 -08001436static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001437{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001438 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001439 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1440 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1441 struct intel_atomic_state *intel_state =
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001442 to_intel_atomic_state(new_crtc_state->uapi.state);
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001443 const struct intel_crtc_state *old_crtc_state =
1444 intel_atomic_get_old_crtc_state(intel_state, crtc);
1445 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001446 enum plane_id plane_id;
1447
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001448 if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001449 *intermediate = *optimal;
1450
1451 intermediate->cxsr = false;
1452 intermediate->hpll_en = false;
1453 goto out;
1454 }
1455
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001456 intermediate->cxsr = optimal->cxsr && active->cxsr &&
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001457 !new_crtc_state->disable_cxsr;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001458 intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001459 !new_crtc_state->disable_cxsr;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001460 intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1461
1462 for_each_plane_id_on_crtc(crtc, plane_id) {
1463 intermediate->wm.plane[plane_id] =
1464 max(optimal->wm.plane[plane_id],
1465 active->wm.plane[plane_id]);
1466
1467 WARN_ON(intermediate->wm.plane[plane_id] >
1468 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1469 }
1470
1471 intermediate->sr.plane = max(optimal->sr.plane,
1472 active->sr.plane);
1473 intermediate->sr.cursor = max(optimal->sr.cursor,
1474 active->sr.cursor);
1475 intermediate->sr.fbc = max(optimal->sr.fbc,
1476 active->sr.fbc);
1477
1478 intermediate->hpll.plane = max(optimal->hpll.plane,
1479 active->hpll.plane);
1480 intermediate->hpll.cursor = max(optimal->hpll.cursor,
1481 active->hpll.cursor);
1482 intermediate->hpll.fbc = max(optimal->hpll.fbc,
1483 active->hpll.fbc);
1484
1485 WARN_ON((intermediate->sr.plane >
1486 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1487 intermediate->sr.cursor >
1488 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1489 intermediate->cxsr);
1490 WARN_ON((intermediate->sr.plane >
1491 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1492 intermediate->sr.cursor >
1493 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1494 intermediate->hpll_en);
1495
1496 WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1497 intermediate->fbc_en && intermediate->cxsr);
1498 WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1499 intermediate->fbc_en && intermediate->hpll_en);
1500
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001501out:
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001502 /*
1503 * If our intermediate WM are identical to the final WM, then we can
1504 * omit the post-vblank programming; only update if it's different.
1505 */
1506 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
Maarten Lankhorst248c2432017-11-15 17:31:57 +01001507 new_crtc_state->wm.need_postvbl_update = true;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001508
1509 return 0;
1510}
1511
1512static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1513 struct g4x_wm_values *wm)
1514{
1515 struct intel_crtc *crtc;
Ville Syrjäläc08e9132019-08-21 20:30:32 +03001516 int num_active_pipes = 0;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001517
1518 wm->cxsr = true;
1519 wm->hpll_en = true;
1520 wm->fbc_en = true;
1521
1522 for_each_intel_crtc(&dev_priv->drm, crtc) {
1523 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1524
1525 if (!crtc->active)
1526 continue;
1527
1528 if (!wm_state->cxsr)
1529 wm->cxsr = false;
1530 if (!wm_state->hpll_en)
1531 wm->hpll_en = false;
1532 if (!wm_state->fbc_en)
1533 wm->fbc_en = false;
1534
Ville Syrjäläc08e9132019-08-21 20:30:32 +03001535 num_active_pipes++;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001536 }
1537
Ville Syrjäläc08e9132019-08-21 20:30:32 +03001538 if (num_active_pipes != 1) {
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001539 wm->cxsr = false;
1540 wm->hpll_en = false;
1541 wm->fbc_en = false;
1542 }
1543
1544 for_each_intel_crtc(&dev_priv->drm, crtc) {
1545 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1546 enum pipe pipe = crtc->pipe;
1547
1548 wm->pipe[pipe] = wm_state->wm;
1549 if (crtc->active && wm->cxsr)
1550 wm->sr = wm_state->sr;
1551 if (crtc->active && wm->hpll_en)
1552 wm->hpll = wm_state->hpll;
1553 }
1554}
1555
1556static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1557{
1558 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1559 struct g4x_wm_values new_wm = {};
1560
1561 g4x_merge_wm(dev_priv, &new_wm);
1562
1563 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1564 return;
1565
1566 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1567 _intel_set_memory_cxsr(dev_priv, false);
1568
1569 g4x_write_wm_values(dev_priv, &new_wm);
1570
1571 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1572 _intel_set_memory_cxsr(dev_priv, true);
1573
1574 *old_wm = new_wm;
1575}
1576
1577static void g4x_initial_watermarks(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02001578 struct intel_crtc *crtc)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001579{
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02001580 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1581 const struct intel_crtc_state *crtc_state =
1582 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001583
1584 mutex_lock(&dev_priv->wm.wm_mutex);
1585 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1586 g4x_program_watermarks(dev_priv);
1587 mutex_unlock(&dev_priv->wm.wm_mutex);
1588}
1589
1590static void g4x_optimize_watermarks(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02001591 struct intel_crtc *crtc)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001592{
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02001593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1594 const struct intel_crtc_state *crtc_state =
1595 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001596
1597 if (!crtc_state->wm.need_postvbl_update)
1598 return;
1599
1600 mutex_lock(&dev_priv->wm.wm_mutex);
Ville Syrjälä88016a92019-07-01 19:05:45 +03001601 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001602 g4x_program_watermarks(dev_priv);
1603 mutex_unlock(&dev_priv->wm.wm_mutex);
1604}
1605
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001606/* latency must be in 0.1us units. */
1607static unsigned int vlv_wm_method2(unsigned int pixel_rate,
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03001608 unsigned int htotal,
1609 unsigned int width,
Ville Syrjäläac484962016-01-20 21:05:26 +02001610 unsigned int cpp,
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001611 unsigned int latency)
1612{
1613 unsigned int ret;
1614
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03001615 ret = intel_wm_method2(pixel_rate, htotal,
1616 width, cpp, latency);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001617 ret = DIV_ROUND_UP(ret, 64);
1618
1619 return ret;
1620}
1621
Ville Syrjäläbb726512016-10-31 22:37:24 +02001622static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001623{
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001624 /* all latencies in usec */
1625 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1626
Ville Syrjälä58590c12015-09-08 21:05:12 +03001627 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1628
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001629 if (IS_CHERRYVIEW(dev_priv)) {
1630 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1631 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
Ville Syrjälä58590c12015-09-08 21:05:12 +03001632
1633 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001634 }
1635}
1636
Jani Nikula5ce9a6492019-01-18 14:01:20 +02001637static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1638 const struct intel_plane_state *plane_state,
1639 int level)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001640{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01001641 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001642 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjäläe339d672016-11-28 19:37:17 +02001643 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01001644 &crtc_state->hw.adjusted_mode;
Chris Wilson1a1f1282017-11-07 14:03:38 +00001645 unsigned int clock, htotal, cpp, width, wm;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001646
1647 if (dev_priv->wm.pri_latency[level] == 0)
1648 return USHRT_MAX;
1649
Ville Syrjäläa07102f2017-03-03 17:19:27 +02001650 if (!intel_wm_plane_visible(crtc_state, plane_state))
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001651 return 0;
1652
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01001653 cpp = plane_state->hw.fb->format->cpp[0];
Ville Syrjäläe339d672016-11-28 19:37:17 +02001654 clock = adjusted_mode->crtc_clock;
1655 htotal = adjusted_mode->crtc_htotal;
1656 width = crtc_state->pipe_src_w;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001657
Ville Syrjälä709f3fc2017-03-03 17:19:26 +02001658 if (plane->id == PLANE_CURSOR) {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001659 /*
1660 * FIXME the formula gives values that are
1661 * too big for the cursor FIFO, and hence we
1662 * would never be able to use cursors. For
1663 * now just hardcode the watermark.
1664 */
1665 wm = 63;
1666 } else {
Ville Syrjäläac484962016-01-20 21:05:26 +02001667 wm = vlv_wm_method2(clock, htotal, width, cpp,
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001668 dev_priv->wm.pri_latency[level] * 10);
1669 }
1670
Chris Wilson1a1f1282017-11-07 14:03:38 +00001671 return min_t(unsigned int, wm, USHRT_MAX);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001672}
1673
Ville Syrjälä1a10ae62017-03-02 19:15:03 +02001674static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1675{
1676 return (active_planes & (BIT(PLANE_SPRITE0) |
1677 BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1678}
1679
Ville Syrjälä5012e602017-03-02 19:14:56 +02001680static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001681{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001683 const struct g4x_pipe_wm *raw =
Ville Syrjälä5012e602017-03-02 19:14:56 +02001684 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
Ville Syrjälä814e7f02017-03-02 19:14:55 +02001685 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
Ville Syrjälä5012e602017-03-02 19:14:56 +02001686 unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
Ville Syrjälä0b14d962019-08-21 20:30:33 +03001687 int num_active_planes = hweight8(active_planes);
Ville Syrjälä5012e602017-03-02 19:14:56 +02001688 const int fifo_size = 511;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001689 int fifo_extra, fifo_left = fifo_size;
Ville Syrjälä1a10ae62017-03-02 19:15:03 +02001690 int sprite0_fifo_extra = 0;
Ville Syrjälä5012e602017-03-02 19:14:56 +02001691 unsigned int total_rate;
1692 enum plane_id plane_id;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001693
Ville Syrjälä1a10ae62017-03-02 19:15:03 +02001694 /*
1695 * When enabling sprite0 after sprite1 has already been enabled
1696 * we tend to get an underrun unless sprite0 already has some
1697 * FIFO space allcoated. Hence we always allocate at least one
1698 * cacheline for sprite0 whenever sprite1 is enabled.
1699 *
1700 * All other plane enable sequences appear immune to this problem.
1701 */
1702 if (vlv_need_sprite0_fifo_workaround(active_planes))
1703 sprite0_fifo_extra = 1;
1704
Ville Syrjälä5012e602017-03-02 19:14:56 +02001705 total_rate = raw->plane[PLANE_PRIMARY] +
1706 raw->plane[PLANE_SPRITE0] +
Ville Syrjälä1a10ae62017-03-02 19:15:03 +02001707 raw->plane[PLANE_SPRITE1] +
1708 sprite0_fifo_extra;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001709
Ville Syrjälä5012e602017-03-02 19:14:56 +02001710 if (total_rate > fifo_size)
1711 return -EINVAL;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001712
Ville Syrjälä5012e602017-03-02 19:14:56 +02001713 if (total_rate == 0)
1714 total_rate = 1;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001715
Ville Syrjälä5012e602017-03-02 19:14:56 +02001716 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001717 unsigned int rate;
1718
Ville Syrjälä5012e602017-03-02 19:14:56 +02001719 if ((active_planes & BIT(plane_id)) == 0) {
1720 fifo_state->plane[plane_id] = 0;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001721 continue;
1722 }
1723
Ville Syrjälä5012e602017-03-02 19:14:56 +02001724 rate = raw->plane[plane_id];
1725 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1726 fifo_left -= fifo_state->plane[plane_id];
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001727 }
1728
Ville Syrjälä1a10ae62017-03-02 19:15:03 +02001729 fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1730 fifo_left -= sprite0_fifo_extra;
1731
Ville Syrjälä5012e602017-03-02 19:14:56 +02001732 fifo_state->plane[PLANE_CURSOR] = 63;
1733
1734 fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001735
1736 /* spread the remainder evenly */
Ville Syrjälä5012e602017-03-02 19:14:56 +02001737 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001738 int plane_extra;
1739
1740 if (fifo_left == 0)
1741 break;
1742
Ville Syrjälä5012e602017-03-02 19:14:56 +02001743 if ((active_planes & BIT(plane_id)) == 0)
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001744 continue;
1745
1746 plane_extra = min(fifo_extra, fifo_left);
Ville Syrjälä5012e602017-03-02 19:14:56 +02001747 fifo_state->plane[plane_id] += plane_extra;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001748 fifo_left -= plane_extra;
1749 }
1750
Ville Syrjälä5012e602017-03-02 19:14:56 +02001751 WARN_ON(active_planes != 0 && fifo_left != 0);
1752
1753 /* give it all to the first plane if none are active */
1754 if (active_planes == 0) {
1755 WARN_ON(fifo_left != fifo_size);
1756 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1757 }
1758
1759 return 0;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001760}
1761
Ville Syrjäläff32c542017-03-02 19:14:57 +02001762/* mark all levels starting from 'level' as invalid */
1763static void vlv_invalidate_wms(struct intel_crtc *crtc,
1764 struct vlv_wm_state *wm_state, int level)
1765{
1766 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1767
Ville Syrjälä6d5019b2017-04-21 21:14:20 +03001768 for (; level < intel_wm_num_levels(dev_priv); level++) {
Ville Syrjäläff32c542017-03-02 19:14:57 +02001769 enum plane_id plane_id;
1770
1771 for_each_plane_id_on_crtc(crtc, plane_id)
1772 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1773
1774 wm_state->sr[level].cursor = USHRT_MAX;
1775 wm_state->sr[level].plane = USHRT_MAX;
1776 }
1777}
1778
Ville Syrjälä26cca0e2016-11-28 19:37:09 +02001779static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1780{
1781 if (wm > fifo_size)
1782 return USHRT_MAX;
1783 else
1784 return fifo_size - wm;
1785}
1786
Ville Syrjäläff32c542017-03-02 19:14:57 +02001787/*
1788 * Starting from 'level' set all higher
1789 * levels to 'value' in the "raw" watermarks.
1790 */
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001791static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
Ville Syrjäläff32c542017-03-02 19:14:57 +02001792 int level, enum plane_id plane_id, u16 value)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001793{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001794 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälä6d5019b2017-04-21 21:14:20 +03001795 int num_levels = intel_wm_num_levels(dev_priv);
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001796 bool dirty = false;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001797
Ville Syrjäläff32c542017-03-02 19:14:57 +02001798 for (; level < num_levels; level++) {
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001799 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001800
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001801 dirty |= raw->plane[plane_id] != value;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001802 raw->plane[plane_id] = value;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001803 }
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001804
1805 return dirty;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001806}
1807
Ville Syrjälä77d14ee2017-04-21 21:14:18 +03001808static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1809 const struct intel_plane_state *plane_state)
Ville Syrjäläff32c542017-03-02 19:14:57 +02001810{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01001811 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Wambui Karugaf8d18d52020-01-07 18:13:30 +03001812 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjäläff32c542017-03-02 19:14:57 +02001813 enum plane_id plane_id = plane->id;
Ville Syrjälä6d5019b2017-04-21 21:14:20 +03001814 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
Ville Syrjäläff32c542017-03-02 19:14:57 +02001815 int level;
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001816 bool dirty = false;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001817
Ville Syrjäläa07102f2017-03-03 17:19:27 +02001818 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001819 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1820 goto out;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001821 }
1822
1823 for (level = 0; level < num_levels; level++) {
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001824 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
Ville Syrjäläff32c542017-03-02 19:14:57 +02001825 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1826 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1827
Ville Syrjäläff32c542017-03-02 19:14:57 +02001828 if (wm > max_wm)
1829 break;
1830
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001831 dirty |= raw->plane[plane_id] != wm;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001832 raw->plane[plane_id] = wm;
1833 }
1834
1835 /* mark all higher levels as invalid */
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001836 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
Ville Syrjäläff32c542017-03-02 19:14:57 +02001837
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001838out:
1839 if (dirty)
Wambui Karugaf8d18d52020-01-07 18:13:30 +03001840 drm_dbg_kms(&dev_priv->drm,
1841 "%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1842 plane->base.name,
1843 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1844 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1845 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001846
1847 return dirty;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001848}
1849
Ville Syrjälä77d14ee2017-04-21 21:14:18 +03001850static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1851 enum plane_id plane_id, int level)
Ville Syrjäläff32c542017-03-02 19:14:57 +02001852{
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001853 const struct g4x_pipe_wm *raw =
Ville Syrjäläff32c542017-03-02 19:14:57 +02001854 &crtc_state->wm.vlv.raw[level];
1855 const struct vlv_fifo_state *fifo_state =
1856 &crtc_state->wm.vlv.fifo_state;
1857
1858 return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1859}
1860
Ville Syrjälä77d14ee2017-04-21 21:14:18 +03001861static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
Ville Syrjäläff32c542017-03-02 19:14:57 +02001862{
Ville Syrjälä77d14ee2017-04-21 21:14:18 +03001863 return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1864 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1865 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1866 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
Ville Syrjäläff32c542017-03-02 19:14:57 +02001867}
1868
1869static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001870{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Ville Syrjälä7c951c02016-11-28 19:37:10 +02001872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjäläff32c542017-03-02 19:14:57 +02001873 struct intel_atomic_state *state =
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001874 to_intel_atomic_state(crtc_state->uapi.state);
Ville Syrjälä855c79f2017-03-02 19:14:54 +02001875 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001876 const struct vlv_fifo_state *fifo_state =
1877 &crtc_state->wm.vlv.fifo_state;
Ville Syrjälä0b14d962019-08-21 20:30:33 +03001878 int num_active_planes = hweight8(crtc_state->active_planes &
1879 ~BIT(PLANE_CURSOR));
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01001880 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001881 const struct intel_plane_state *old_plane_state;
1882 const struct intel_plane_state *new_plane_state;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001883 struct intel_plane *plane;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001884 enum plane_id plane_id;
1885 int level, ret, i;
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001886 unsigned int dirty = 0;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001887
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001888 for_each_oldnew_intel_plane_in_state(state, plane,
1889 old_plane_state,
1890 new_plane_state, i) {
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01001891 if (new_plane_state->hw.crtc != &crtc->base &&
1892 old_plane_state->hw.crtc != &crtc->base)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001893 continue;
1894
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001895 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001896 dirty |= BIT(plane->id);
1897 }
1898
1899 /*
1900 * DSPARB registers may have been reset due to the
1901 * power well being turned off. Make sure we restore
1902 * them to a consistent state even if no primary/sprite
1903 * planes are initially active.
1904 */
1905 if (needs_modeset)
1906 crtc_state->fifo_changed = true;
1907
1908 if (!dirty)
1909 return 0;
1910
1911 /* cursor changes don't warrant a FIFO recompute */
1912 if (dirty & ~BIT(PLANE_CURSOR)) {
1913 const struct intel_crtc_state *old_crtc_state =
Ville Syrjälä7b5104512017-08-23 18:22:22 +03001914 intel_atomic_get_old_crtc_state(state, crtc);
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001915 const struct vlv_fifo_state *old_fifo_state =
1916 &old_crtc_state->wm.vlv.fifo_state;
1917
1918 ret = vlv_compute_fifo(crtc_state);
1919 if (ret)
1920 return ret;
1921
1922 if (needs_modeset ||
1923 memcmp(old_fifo_state, fifo_state,
1924 sizeof(*fifo_state)) != 0)
1925 crtc_state->fifo_changed = true;
Ville Syrjälä5012e602017-03-02 19:14:56 +02001926 }
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001927
Ville Syrjäläff32c542017-03-02 19:14:57 +02001928 /* initially allow all levels */
Ville Syrjälä6d5019b2017-04-21 21:14:20 +03001929 wm_state->num_levels = intel_wm_num_levels(dev_priv);
Ville Syrjäläff32c542017-03-02 19:14:57 +02001930 /*
1931 * Note that enabling cxsr with no primary/sprite planes
1932 * enabled can wedge the pipe. Hence we only allow cxsr
1933 * with exactly one enabled primary/sprite plane.
1934 */
Ville Syrjälä5eeb7982017-03-02 19:15:00 +02001935 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
Ville Syrjäläff32c542017-03-02 19:14:57 +02001936
Ville Syrjälä5012e602017-03-02 19:14:56 +02001937 for (level = 0; level < wm_state->num_levels; level++) {
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001938 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
Jani Nikula24977872019-09-11 12:26:08 +03001939 const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
Ville Syrjälä5012e602017-03-02 19:14:56 +02001940
Ville Syrjälä77d14ee2017-04-21 21:14:18 +03001941 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
Ville Syrjäläff32c542017-03-02 19:14:57 +02001942 break;
Ville Syrjälä5012e602017-03-02 19:14:56 +02001943
Ville Syrjäläff32c542017-03-02 19:14:57 +02001944 for_each_plane_id_on_crtc(crtc, plane_id) {
1945 wm_state->wm[level].plane[plane_id] =
1946 vlv_invert_wm_value(raw->plane[plane_id],
1947 fifo_state->plane[plane_id]);
1948 }
1949
1950 wm_state->sr[level].plane =
1951 vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
Ville Syrjälä5012e602017-03-02 19:14:56 +02001952 raw->plane[PLANE_SPRITE0],
Ville Syrjäläff32c542017-03-02 19:14:57 +02001953 raw->plane[PLANE_SPRITE1]),
1954 sr_fifo_size);
1955
1956 wm_state->sr[level].cursor =
1957 vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1958 63);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001959 }
1960
Ville Syrjäläff32c542017-03-02 19:14:57 +02001961 if (level == 0)
1962 return -EINVAL;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001963
Ville Syrjäläff32c542017-03-02 19:14:57 +02001964 /* limit to only levels we can actually handle */
1965 wm_state->num_levels = level;
1966
1967 /* invalidate the higher levels */
1968 vlv_invalidate_wms(crtc, wm_state, level);
1969
1970 return 0;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001971}
1972
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001973#define VLV_FIFO(plane, value) \
1974 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1975
Ville Syrjäläff32c542017-03-02 19:14:57 +02001976static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02001977 struct intel_crtc *crtc)
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001978{
Ville Syrjäläf07d43d2017-03-02 19:14:52 +02001979 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01001980 struct intel_uncore *uncore = &dev_priv->uncore;
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02001981 const struct intel_crtc_state *crtc_state =
1982 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjälä814e7f02017-03-02 19:14:55 +02001983 const struct vlv_fifo_state *fifo_state =
1984 &crtc_state->wm.vlv.fifo_state;
Ville Syrjäläf07d43d2017-03-02 19:14:52 +02001985 int sprite0_start, sprite1_start, fifo_size;
Kees Cook2713eb42020-02-20 16:05:17 -08001986 u32 dsparb, dsparb2, dsparb3;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001987
Ville Syrjälä236c48e2017-03-02 19:14:58 +02001988 if (!crtc_state->fifo_changed)
1989 return;
1990
Ville Syrjäläf07d43d2017-03-02 19:14:52 +02001991 sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1992 sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1993 fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001994
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05301995 drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63);
1996 drm_WARN_ON(&dev_priv->drm, fifo_size != 511);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001997
Ville Syrjäläc137d662017-03-02 19:15:06 +02001998 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1999
Ville Syrjälä44e921d2017-03-09 17:44:34 +02002000 /*
2001 * uncore.lock serves a double purpose here. It allows us to
2002 * use the less expensive I915_{READ,WRITE}_FW() functions, and
2003 * it protects the DSPARB registers from getting clobbered by
2004 * parallel updates from multiple pipes.
2005 *
2006 * intel_pipe_update_start() has already disabled interrupts
2007 * for us, so a plain spin_lock() is sufficient here.
2008 */
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002009 spin_lock(&uncore->lock);
Ville Syrjälä467a14d2016-12-05 16:13:28 +02002010
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002011 switch (crtc->pipe) {
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002012 case PIPE_A:
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002013 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2014 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002015
2016 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
2017 VLV_FIFO(SPRITEB, 0xff));
2018 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
2019 VLV_FIFO(SPRITEB, sprite1_start));
2020
2021 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
2022 VLV_FIFO(SPRITEB_HI, 0x1));
2023 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
2024 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
2025
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002026 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2027 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002028 break;
2029 case PIPE_B:
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002030 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2031 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002032
2033 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2034 VLV_FIFO(SPRITED, 0xff));
2035 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2036 VLV_FIFO(SPRITED, sprite1_start));
2037
2038 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2039 VLV_FIFO(SPRITED_HI, 0xff));
2040 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2041 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2042
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002043 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2044 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002045 break;
2046 case PIPE_C:
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002047 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2048 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002049
2050 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2051 VLV_FIFO(SPRITEF, 0xff));
2052 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2053 VLV_FIFO(SPRITEF, sprite1_start));
2054
2055 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2056 VLV_FIFO(SPRITEF_HI, 0xff));
2057 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2058 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2059
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002060 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2061 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002062 break;
2063 default:
2064 break;
2065 }
Ville Syrjälä467a14d2016-12-05 16:13:28 +02002066
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002067 intel_uncore_posting_read_fw(uncore, DSPARB);
Ville Syrjälä467a14d2016-12-05 16:13:28 +02002068
Tvrtko Ursuline33a4be2019-06-11 11:45:44 +01002069 spin_unlock(&uncore->lock);
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03002070}
2071
2072#undef VLV_FIFO
2073
Matt Ropercd1d3ee2018-12-10 13:54:14 -08002074static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
Ville Syrjälä4841da52017-03-02 19:14:59 +02002075{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01002076 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
Maarten Lankhorst5b9489c2017-11-15 17:31:56 +01002077 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2078 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2079 struct intel_atomic_state *intel_state =
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01002080 to_intel_atomic_state(new_crtc_state->uapi.state);
Maarten Lankhorst5b9489c2017-11-15 17:31:56 +01002081 const struct intel_crtc_state *old_crtc_state =
2082 intel_atomic_get_old_crtc_state(intel_state, crtc);
2083 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
Ville Syrjälä4841da52017-03-02 19:14:59 +02002084 int level;
2085
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01002086 if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
Maarten Lankhorst5b9489c2017-11-15 17:31:56 +01002087 *intermediate = *optimal;
2088
2089 intermediate->cxsr = false;
2090 goto out;
2091 }
2092
Ville Syrjälä4841da52017-03-02 19:14:59 +02002093 intermediate->num_levels = min(optimal->num_levels, active->num_levels);
Ville Syrjälä5eeb7982017-03-02 19:15:00 +02002094 intermediate->cxsr = optimal->cxsr && active->cxsr &&
Maarten Lankhorst5b9489c2017-11-15 17:31:56 +01002095 !new_crtc_state->disable_cxsr;
Ville Syrjälä4841da52017-03-02 19:14:59 +02002096
2097 for (level = 0; level < intermediate->num_levels; level++) {
2098 enum plane_id plane_id;
2099
2100 for_each_plane_id_on_crtc(crtc, plane_id) {
2101 intermediate->wm[level].plane[plane_id] =
2102 min(optimal->wm[level].plane[plane_id],
2103 active->wm[level].plane[plane_id]);
2104 }
2105
2106 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2107 active->sr[level].plane);
2108 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2109 active->sr[level].cursor);
2110 }
2111
2112 vlv_invalidate_wms(crtc, intermediate, level);
2113
Maarten Lankhorst5b9489c2017-11-15 17:31:56 +01002114out:
Ville Syrjälä4841da52017-03-02 19:14:59 +02002115 /*
2116 * If our intermediate WM are identical to the final WM, then we can
2117 * omit the post-vblank programming; only update if it's different.
2118 */
Ville Syrjälä5eeb7982017-03-02 19:15:00 +02002119 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
Maarten Lankhorst5b9489c2017-11-15 17:31:56 +01002120 new_crtc_state->wm.need_postvbl_update = true;
Ville Syrjälä4841da52017-03-02 19:14:59 +02002121
2122 return 0;
2123}
2124
Ville Syrjälä7c951c02016-11-28 19:37:10 +02002125static void vlv_merge_wm(struct drm_i915_private *dev_priv,
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002126 struct vlv_wm_values *wm)
2127{
2128 struct intel_crtc *crtc;
Ville Syrjäläc08e9132019-08-21 20:30:32 +03002129 int num_active_pipes = 0;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002130
Ville Syrjälä7c951c02016-11-28 19:37:10 +02002131 wm->level = dev_priv->wm.max_level;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002132 wm->cxsr = true;
2133
Ville Syrjälä7c951c02016-11-28 19:37:10 +02002134 for_each_intel_crtc(&dev_priv->drm, crtc) {
Ville Syrjälä7eb49412017-03-02 19:14:53 +02002135 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002136
2137 if (!crtc->active)
2138 continue;
2139
2140 if (!wm_state->cxsr)
2141 wm->cxsr = false;
2142
Ville Syrjäläc08e9132019-08-21 20:30:32 +03002143 num_active_pipes++;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002144 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2145 }
2146
Ville Syrjäläc08e9132019-08-21 20:30:32 +03002147 if (num_active_pipes != 1)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002148 wm->cxsr = false;
2149
Ville Syrjäläc08e9132019-08-21 20:30:32 +03002150 if (num_active_pipes > 1)
Ville Syrjälä6f9c7842015-06-24 22:00:08 +03002151 wm->level = VLV_WM_LEVEL_PM2;
2152
Ville Syrjälä7c951c02016-11-28 19:37:10 +02002153 for_each_intel_crtc(&dev_priv->drm, crtc) {
Ville Syrjälä7eb49412017-03-02 19:14:53 +02002154 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002155 enum pipe pipe = crtc->pipe;
2156
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002157 wm->pipe[pipe] = wm_state->wm[wm->level];
Ville Syrjäläff32c542017-03-02 19:14:57 +02002158 if (crtc->active && wm->cxsr)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002159 wm->sr = wm_state->sr[wm->level];
2160
Ville Syrjälä1b313892016-11-28 19:37:08 +02002161 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2162 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2163 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2164 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002165 }
2166}
2167
Ville Syrjäläff32c542017-03-02 19:14:57 +02002168static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002169{
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002170 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2171 struct vlv_wm_values new_wm = {};
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002172
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002173 vlv_merge_wm(dev_priv, &new_wm);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002174
Ville Syrjäläff32c542017-03-02 19:14:57 +02002175 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002176 return;
2177
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002178 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002179 chv_set_memory_dvfs(dev_priv, false);
2180
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002181 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002182 chv_set_memory_pm5(dev_priv, false);
2183
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002184 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
Ville Syrjälä3d90e642016-11-28 19:37:11 +02002185 _intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002186
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002187 vlv_write_wm_values(dev_priv, &new_wm);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002188
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002189 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
Ville Syrjälä3d90e642016-11-28 19:37:11 +02002190 _intel_set_memory_cxsr(dev_priv, true);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002191
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002192 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002193 chv_set_memory_pm5(dev_priv, true);
2194
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002195 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03002196 chv_set_memory_dvfs(dev_priv, true);
2197
Ville Syrjäläfa292a42016-11-28 19:37:16 +02002198 *old_wm = new_wm;
Ville Syrjälä3c2777f2014-06-26 17:03:06 +03002199}
2200
Ville Syrjäläff32c542017-03-02 19:14:57 +02002201static void vlv_initial_watermarks(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02002202 struct intel_crtc *crtc)
Ville Syrjäläff32c542017-03-02 19:14:57 +02002203{
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02002204 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2205 const struct intel_crtc_state *crtc_state =
2206 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjäläff32c542017-03-02 19:14:57 +02002207
2208 mutex_lock(&dev_priv->wm.wm_mutex);
Ville Syrjälä4841da52017-03-02 19:14:59 +02002209 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2210 vlv_program_watermarks(dev_priv);
2211 mutex_unlock(&dev_priv->wm.wm_mutex);
2212}
2213
2214static void vlv_optimize_watermarks(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02002215 struct intel_crtc *crtc)
Ville Syrjälä4841da52017-03-02 19:14:59 +02002216{
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02002217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2218 const struct intel_crtc_state *crtc_state =
2219 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjälä4841da52017-03-02 19:14:59 +02002220
2221 if (!crtc_state->wm.need_postvbl_update)
2222 return;
2223
2224 mutex_lock(&dev_priv->wm.wm_mutex);
Ville Syrjälä88016a92019-07-01 19:05:45 +03002225 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
Ville Syrjäläff32c542017-03-02 19:14:57 +02002226 vlv_program_watermarks(dev_priv);
2227 mutex_unlock(&dev_priv->wm.wm_mutex);
2228}
2229
Ville Syrjälä432081b2016-10-31 22:37:03 +02002230static void i965_update_wm(struct intel_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002231{
Ville Syrjäläffc7a762016-10-31 22:37:21 +02002232 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
Ville Syrjäläefc26112016-10-31 22:37:04 +02002233 struct intel_crtc *crtc;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002234 int srwm = 1;
2235 int cursor_sr = 16;
Imre Deak98584252014-06-13 14:54:20 +03002236 bool cxsr_enabled;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002237
2238 /* Calc sr entries for one plane configs */
Ville Syrjäläffc7a762016-10-31 22:37:21 +02002239 crtc = single_enabled_crtc(dev_priv);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002240 if (crtc) {
2241 /* self-refresh has much higher latency */
2242 static const int sr_latency_ns = 12000;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002243 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002244 &crtc->config->hw.adjusted_mode;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002245 const struct drm_framebuffer *fb =
2246 crtc->base.primary->state->fb;
Damien Lespiau241bfc32013-09-25 16:45:37 +01002247 int clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -08002248 int htotal = adjusted_mode->crtc_htotal;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002249 int hdisplay = crtc->config->pipe_src_w;
Ville Syrjälä353c8592016-12-14 23:30:57 +02002250 int cpp = fb->format->cpp[0];
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002251 int entries;
2252
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002253 entries = intel_wm_method2(clock, htotal,
2254 hdisplay, cpp, sr_latency_ns / 100);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002255 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2256 srwm = I965_FIFO_SIZE - entries;
2257 if (srwm < 0)
2258 srwm = 1;
2259 srwm &= 0x1ff;
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002260 drm_dbg_kms(&dev_priv->drm,
2261 "self-refresh entries: %d, wm: %d\n",
2262 entries, srwm);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002263
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002264 entries = intel_wm_method2(clock, htotal,
2265 crtc->base.cursor->state->crtc_w, 4,
2266 sr_latency_ns / 100);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002267 entries = DIV_ROUND_UP(entries,
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002268 i965_cursor_wm_info.cacheline_size) +
2269 i965_cursor_wm_info.guard_size;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002270
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002271 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002272 if (cursor_sr > i965_cursor_wm_info.max_wm)
2273 cursor_sr = i965_cursor_wm_info.max_wm;
2274
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002275 drm_dbg_kms(&dev_priv->drm,
2276 "self-refresh watermark: display plane %d "
2277 "cursor %d\n", srwm, cursor_sr);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002278
Imre Deak98584252014-06-13 14:54:20 +03002279 cxsr_enabled = true;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002280 } else {
Imre Deak98584252014-06-13 14:54:20 +03002281 cxsr_enabled = false;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002282 /* Turn off self refresh if both pipes are enabled */
Imre Deak5209b1f2014-07-01 12:36:17 +03002283 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002284 }
2285
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002286 drm_dbg_kms(&dev_priv->drm,
2287 "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2288 srwm);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002289
2290 /* 965 has limitations... */
Ville Syrjäläf4998962015-03-10 17:02:21 +02002291 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2292 FW_WM(8, CURSORB) |
2293 FW_WM(8, PLANEB) |
2294 FW_WM(8, PLANEA));
2295 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2296 FW_WM(8, PLANEC_OLD));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002297 /* update cursor SR watermark */
Ville Syrjäläf4998962015-03-10 17:02:21 +02002298 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
Imre Deak98584252014-06-13 14:54:20 +03002299
2300 if (cxsr_enabled)
2301 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002302}
2303
Ville Syrjäläf4998962015-03-10 17:02:21 +02002304#undef FW_WM
2305
Ville Syrjälä432081b2016-10-31 22:37:03 +02002306static void i9xx_update_wm(struct intel_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002307{
Ville Syrjäläffc7a762016-10-31 22:37:21 +02002308 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002309 const struct intel_watermark_params *wm_info;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002310 u32 fwater_lo;
2311 u32 fwater_hi;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002312 int cwm, srwm = 1;
2313 int fifo_size;
2314 int planea_wm, planeb_wm;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002315 struct intel_crtc *crtc, *enabled = NULL;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002316
Ville Syrjäläa9097be2016-10-31 22:37:20 +02002317 if (IS_I945GM(dev_priv))
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002318 wm_info = &i945_wm_info;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08002319 else if (!IS_GEN(dev_priv, 2))
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002320 wm_info = &i915_wm_info;
2321 else
Ville Syrjälä9d539102014-08-15 01:21:53 +03002322 wm_info = &i830_a_wm_info;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002323
Ville Syrjäläbdaf8432017-11-17 21:19:11 +02002324 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2325 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
Ville Syrjäläefc26112016-10-31 22:37:04 +02002326 if (intel_crtc_active(crtc)) {
2327 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002328 &crtc->config->hw.adjusted_mode;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002329 const struct drm_framebuffer *fb =
2330 crtc->base.primary->state->fb;
2331 int cpp;
2332
Lucas De Marchicf819ef2018-12-12 10:10:43 -08002333 if (IS_GEN(dev_priv, 2))
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01002334 cpp = 4;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002335 else
Ville Syrjälä353c8592016-12-14 23:30:57 +02002336 cpp = fb->format->cpp[0];
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01002337
Damien Lespiau241bfc32013-09-25 16:45:37 +01002338 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01002339 wm_info, fifo_size, cpp,
Chris Wilson5aef6002014-09-03 11:56:07 +01002340 pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002341 enabled = crtc;
Ville Syrjälä9d539102014-08-15 01:21:53 +03002342 } else {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002343 planea_wm = fifo_size - wm_info->guard_size;
Ville Syrjälä9d539102014-08-15 01:21:53 +03002344 if (planea_wm > (long)wm_info->max_wm)
2345 planea_wm = wm_info->max_wm;
2346 }
2347
Lucas De Marchicf819ef2018-12-12 10:10:43 -08002348 if (IS_GEN(dev_priv, 2))
Ville Syrjälä9d539102014-08-15 01:21:53 +03002349 wm_info = &i830_bc_wm_info;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002350
Ville Syrjäläbdaf8432017-11-17 21:19:11 +02002351 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2352 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
Ville Syrjäläefc26112016-10-31 22:37:04 +02002353 if (intel_crtc_active(crtc)) {
2354 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002355 &crtc->config->hw.adjusted_mode;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002356 const struct drm_framebuffer *fb =
2357 crtc->base.primary->state->fb;
2358 int cpp;
2359
Lucas De Marchicf819ef2018-12-12 10:10:43 -08002360 if (IS_GEN(dev_priv, 2))
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01002361 cpp = 4;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002362 else
Ville Syrjälä353c8592016-12-14 23:30:57 +02002363 cpp = fb->format->cpp[0];
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01002364
Damien Lespiau241bfc32013-09-25 16:45:37 +01002365 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01002366 wm_info, fifo_size, cpp,
Chris Wilson5aef6002014-09-03 11:56:07 +01002367 pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002368 if (enabled == NULL)
2369 enabled = crtc;
2370 else
2371 enabled = NULL;
Ville Syrjälä9d539102014-08-15 01:21:53 +03002372 } else {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002373 planeb_wm = fifo_size - wm_info->guard_size;
Ville Syrjälä9d539102014-08-15 01:21:53 +03002374 if (planeb_wm > (long)wm_info->max_wm)
2375 planeb_wm = wm_info->max_wm;
2376 }
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002377
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002378 drm_dbg_kms(&dev_priv->drm,
2379 "FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002380
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002381 if (IS_I915GM(dev_priv) && enabled) {
Matt Roper2ff8fde2014-07-08 07:50:07 -07002382 struct drm_i915_gem_object *obj;
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02002383
Ville Syrjäläefc26112016-10-31 22:37:04 +02002384 obj = intel_fb_obj(enabled->base.primary->state->fb);
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02002385
2386 /* self-refresh seems busted with untiled */
Chris Wilson3e510a82016-08-05 10:14:23 +01002387 if (!i915_gem_object_is_tiled(obj))
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02002388 enabled = NULL;
2389 }
2390
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002391 /*
2392 * Overlay gets an aggressive default since video jitter is bad.
2393 */
2394 cwm = 2;
2395
2396 /* Play safe and disable self-refresh before adjusting watermarks. */
Imre Deak5209b1f2014-07-01 12:36:17 +03002397 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002398
2399 /* Calc sr entries for one plane configs */
Ville Syrjälä03427fc2016-10-31 22:37:18 +02002400 if (HAS_FW_BLC(dev_priv) && enabled) {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002401 /* self-refresh has much higher latency */
2402 static const int sr_latency_ns = 6000;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002403 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002404 &enabled->config->hw.adjusted_mode;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002405 const struct drm_framebuffer *fb =
2406 enabled->base.primary->state->fb;
Damien Lespiau241bfc32013-09-25 16:45:37 +01002407 int clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -08002408 int htotal = adjusted_mode->crtc_htotal;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002409 int hdisplay = enabled->config->pipe_src_w;
2410 int cpp;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002411 int entries;
2412
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002413 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
Ville Syrjälä2d1b5052016-07-29 17:57:01 +03002414 cpp = 4;
Ville Syrjäläefc26112016-10-31 22:37:04 +02002415 else
Ville Syrjälä353c8592016-12-14 23:30:57 +02002416 cpp = fb->format->cpp[0];
Ville Syrjälä2d1b5052016-07-29 17:57:01 +03002417
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002418 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2419 sr_latency_ns / 100);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002420 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002421 drm_dbg_kms(&dev_priv->drm,
2422 "self-refresh entries: %d\n", entries);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002423 srwm = wm_info->fifo_size - entries;
2424 if (srwm < 0)
2425 srwm = 1;
2426
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002427 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002428 I915_WRITE(FW_BLC_SELF,
2429 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
Ville Syrjäläacb91352016-07-29 17:57:02 +03002430 else
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002431 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2432 }
2433
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002434 drm_dbg_kms(&dev_priv->drm,
2435 "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2436 planea_wm, planeb_wm, cwm, srwm);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002437
2438 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2439 fwater_hi = (cwm & 0x1f);
2440
2441 /* Set request length to 8 cachelines per fetch */
2442 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2443 fwater_hi = fwater_hi | (1 << 8);
2444
2445 I915_WRITE(FW_BLC, fwater_lo);
2446 I915_WRITE(FW_BLC2, fwater_hi);
2447
Imre Deak5209b1f2014-07-01 12:36:17 +03002448 if (enabled)
2449 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002450}
2451
Ville Syrjälä432081b2016-10-31 22:37:03 +02002452static void i845_update_wm(struct intel_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002453{
Ville Syrjäläffc7a762016-10-31 22:37:21 +02002454 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
Ville Syrjäläefc26112016-10-31 22:37:04 +02002455 struct intel_crtc *crtc;
Damien Lespiau241bfc32013-09-25 16:45:37 +01002456 const struct drm_display_mode *adjusted_mode;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002457 u32 fwater_lo;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002458 int planea_wm;
2459
Ville Syrjäläffc7a762016-10-31 22:37:21 +02002460 crtc = single_enabled_crtc(dev_priv);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002461 if (crtc == NULL)
2462 return;
2463
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002464 adjusted_mode = &crtc->config->hw.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01002465 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Daniel Vetterfeb56b92013-12-14 20:38:30 -02002466 &i845_wm_info,
Ville Syrjäläbdaf8432017-11-17 21:19:11 +02002467 dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
Chris Wilson5aef6002014-09-03 11:56:07 +01002468 4, pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002469 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2470 fwater_lo |= (3<<8) | planea_wm;
2471
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002472 drm_dbg_kms(&dev_priv->drm,
2473 "Setting FIFO watermarks - A: %d\n", planea_wm);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03002474
2475 I915_WRITE(FW_BLC, fwater_lo);
2476}
2477
Ville Syrjälä37126462013-08-01 16:18:55 +03002478/* latency must be in 0.1us units. */
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002479static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2480 unsigned int cpp,
2481 unsigned int latency)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002482{
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002483 unsigned int ret;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002484
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002485 ret = intel_wm_method1(pixel_rate, cpp, latency);
2486 ret = DIV_ROUND_UP(ret, 64) + 2;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002487
2488 return ret;
2489}
2490
Ville Syrjälä37126462013-08-01 16:18:55 +03002491/* latency must be in 0.1us units. */
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002492static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2493 unsigned int htotal,
2494 unsigned int width,
2495 unsigned int cpp,
2496 unsigned int latency)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002497{
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002498 unsigned int ret;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002499
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002500 ret = intel_wm_method2(pixel_rate, htotal,
2501 width, cpp, latency);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002502 ret = DIV_ROUND_UP(ret, 64) + 2;
Ville Syrjäläbaf69ca2017-04-21 21:14:27 +03002503
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002504 return ret;
2505}
2506
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002507static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
Paulo Zanonicca32e92013-05-31 11:45:06 -03002508{
Matt Roper15126882015-12-03 11:37:40 -08002509 /*
2510 * Neither of these should be possible since this function shouldn't be
2511 * called if the CRTC is off or the plane is invisible. But let's be
2512 * extra paranoid to avoid a potential divide-by-zero if we screw up
2513 * elsewhere in the driver.
2514 */
Ville Syrjäläac484962016-01-20 21:05:26 +02002515 if (WARN_ON(!cpp))
Matt Roper15126882015-12-03 11:37:40 -08002516 return 0;
2517 if (WARN_ON(!horiz_pixels))
2518 return 0;
2519
Ville Syrjäläac484962016-01-20 21:05:26 +02002520 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002521}
2522
Imre Deak820c1982013-12-17 14:46:36 +02002523struct ilk_wm_maximums {
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002524 u16 pri;
2525 u16 spr;
2526 u16 cur;
2527 u16 fbc;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002528};
2529
Ville Syrjälä37126462013-08-01 16:18:55 +03002530/*
2531 * For both WM_PIPE and WM_LP.
2532 * mem_value must be in 0.1us units.
2533 */
Maarten Lankhorstec193642019-06-28 10:55:17 +02002534static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2535 const struct intel_plane_state *plane_state,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002536 u32 mem_value, bool is_lp)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002537{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002538 u32 method1, method2;
Ville Syrjälä83054942016-11-18 21:53:00 +02002539 int cpp;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002540
Ville Syrjälä03981c62018-11-14 19:34:40 +02002541 if (mem_value == 0)
2542 return U32_MAX;
2543
Maarten Lankhorstec193642019-06-28 10:55:17 +02002544 if (!intel_wm_plane_visible(crtc_state, plane_state))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002545 return 0;
2546
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01002547 cpp = plane_state->hw.fb->format->cpp[0];
Ville Syrjälä83054942016-11-18 21:53:00 +02002548
Maarten Lankhorstec193642019-06-28 10:55:17 +02002549 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
Paulo Zanonicca32e92013-05-31 11:45:06 -03002550
2551 if (!is_lp)
2552 return method1;
2553
Maarten Lankhorstec193642019-06-28 10:55:17 +02002554 method2 = ilk_wm_method2(crtc_state->pixel_rate,
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002555 crtc_state->hw.adjusted_mode.crtc_htotal,
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01002556 drm_rect_width(&plane_state->uapi.dst),
Ville Syrjäläac484962016-01-20 21:05:26 +02002557 cpp, mem_value);
Paulo Zanonicca32e92013-05-31 11:45:06 -03002558
2559 return min(method1, method2);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002560}
2561
Ville Syrjälä37126462013-08-01 16:18:55 +03002562/*
2563 * For both WM_PIPE and WM_LP.
2564 * mem_value must be in 0.1us units.
2565 */
Maarten Lankhorstec193642019-06-28 10:55:17 +02002566static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2567 const struct intel_plane_state *plane_state,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002568 u32 mem_value)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002569{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002570 u32 method1, method2;
Ville Syrjälä83054942016-11-18 21:53:00 +02002571 int cpp;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002572
Ville Syrjälä03981c62018-11-14 19:34:40 +02002573 if (mem_value == 0)
2574 return U32_MAX;
2575
Maarten Lankhorstec193642019-06-28 10:55:17 +02002576 if (!intel_wm_plane_visible(crtc_state, plane_state))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002577 return 0;
2578
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01002579 cpp = plane_state->hw.fb->format->cpp[0];
Ville Syrjälä83054942016-11-18 21:53:00 +02002580
Maarten Lankhorstec193642019-06-28 10:55:17 +02002581 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2582 method2 = ilk_wm_method2(crtc_state->pixel_rate,
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002583 crtc_state->hw.adjusted_mode.crtc_htotal,
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01002584 drm_rect_width(&plane_state->uapi.dst),
Ville Syrjäläac484962016-01-20 21:05:26 +02002585 cpp, mem_value);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002586 return min(method1, method2);
2587}
2588
Ville Syrjälä37126462013-08-01 16:18:55 +03002589/*
2590 * For both WM_PIPE and WM_LP.
2591 * mem_value must be in 0.1us units.
2592 */
Maarten Lankhorstec193642019-06-28 10:55:17 +02002593static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2594 const struct intel_plane_state *plane_state,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002595 u32 mem_value)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002596{
Ville Syrjäläa5509ab2017-02-17 17:01:59 +02002597 int cpp;
Matt Roper43d59ed2015-09-24 15:53:07 -07002598
Ville Syrjälä03981c62018-11-14 19:34:40 +02002599 if (mem_value == 0)
2600 return U32_MAX;
2601
Maarten Lankhorstec193642019-06-28 10:55:17 +02002602 if (!intel_wm_plane_visible(crtc_state, plane_state))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002603 return 0;
2604
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01002605 cpp = plane_state->hw.fb->format->cpp[0];
Ville Syrjäläa5509ab2017-02-17 17:01:59 +02002606
Maarten Lankhorstec193642019-06-28 10:55:17 +02002607 return ilk_wm_method2(crtc_state->pixel_rate,
Maarten Lankhorst1326a922019-10-31 12:26:02 +01002608 crtc_state->hw.adjusted_mode.crtc_htotal,
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01002609 drm_rect_width(&plane_state->uapi.dst),
Maarten Lankhorst3a612762019-10-04 13:34:54 +02002610 cpp, mem_value);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002611}
2612
Paulo Zanonicca32e92013-05-31 11:45:06 -03002613/* Only for WM_LP. */
Maarten Lankhorstec193642019-06-28 10:55:17 +02002614static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2615 const struct intel_plane_state *plane_state,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002616 u32 pri_val)
Paulo Zanonicca32e92013-05-31 11:45:06 -03002617{
Ville Syrjälä83054942016-11-18 21:53:00 +02002618 int cpp;
Matt Roper43d59ed2015-09-24 15:53:07 -07002619
Maarten Lankhorstec193642019-06-28 10:55:17 +02002620 if (!intel_wm_plane_visible(crtc_state, plane_state))
Paulo Zanonicca32e92013-05-31 11:45:06 -03002621 return 0;
2622
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01002623 cpp = plane_state->hw.fb->format->cpp[0];
Ville Syrjälä83054942016-11-18 21:53:00 +02002624
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01002625 return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
2626 cpp);
Paulo Zanonicca32e92013-05-31 11:45:06 -03002627}
2628
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002629static unsigned int
2630ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002631{
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002632 if (INTEL_GEN(dev_priv) >= 8)
Ville Syrjälä416f4722013-11-02 21:07:46 -07002633 return 3072;
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002634 else if (INTEL_GEN(dev_priv) >= 7)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002635 return 768;
2636 else
2637 return 512;
2638}
2639
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002640static unsigned int
2641ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2642 int level, bool is_sprite)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002643{
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002644 if (INTEL_GEN(dev_priv) >= 8)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002645 /* BDW primary/sprite plane watermarks */
2646 return level == 0 ? 255 : 2047;
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002647 else if (INTEL_GEN(dev_priv) >= 7)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002648 /* IVB/HSW primary/sprite plane watermarks */
2649 return level == 0 ? 127 : 1023;
2650 else if (!is_sprite)
2651 /* ILK/SNB primary plane watermarks */
2652 return level == 0 ? 127 : 511;
2653 else
2654 /* ILK/SNB sprite plane watermarks */
2655 return level == 0 ? 63 : 255;
2656}
2657
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002658static unsigned int
2659ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002660{
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002661 if (INTEL_GEN(dev_priv) >= 7)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002662 return level == 0 ? 63 : 255;
2663 else
2664 return level == 0 ? 31 : 63;
2665}
2666
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002667static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002668{
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002669 if (INTEL_GEN(dev_priv) >= 8)
Ville Syrjälä4e975082014-03-07 18:32:11 +02002670 return 31;
2671 else
2672 return 15;
2673}
2674
Ville Syrjälä158ae642013-08-07 13:28:19 +03002675/* Calculate the maximum primary/sprite plane watermark */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08002676static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
Ville Syrjälä158ae642013-08-07 13:28:19 +03002677 int level,
Ville Syrjälä240264f2013-08-07 13:29:12 +03002678 const struct intel_wm_config *config,
Ville Syrjälä158ae642013-08-07 13:28:19 +03002679 enum intel_ddb_partitioning ddb_partitioning,
2680 bool is_sprite)
2681{
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002682 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
Ville Syrjälä158ae642013-08-07 13:28:19 +03002683
2684 /* if sprites aren't enabled, sprites get nothing */
Ville Syrjälä240264f2013-08-07 13:29:12 +03002685 if (is_sprite && !config->sprites_enabled)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002686 return 0;
2687
2688 /* HSW allows LP1+ watermarks even with multiple pipes */
Ville Syrjälä240264f2013-08-07 13:29:12 +03002689 if (level == 0 || config->num_pipes_active > 1) {
Jani Nikula24977872019-09-11 12:26:08 +03002690 fifo_size /= INTEL_NUM_PIPES(dev_priv);
Ville Syrjälä158ae642013-08-07 13:28:19 +03002691
2692 /*
2693 * For some reason the non self refresh
2694 * FIFO size is only half of the self
2695 * refresh FIFO size on ILK/SNB.
2696 */
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002697 if (INTEL_GEN(dev_priv) <= 6)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002698 fifo_size /= 2;
2699 }
2700
Ville Syrjälä240264f2013-08-07 13:29:12 +03002701 if (config->sprites_enabled) {
Ville Syrjälä158ae642013-08-07 13:28:19 +03002702 /* level 0 is always calculated with 1:1 split */
2703 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2704 if (is_sprite)
2705 fifo_size *= 5;
2706 fifo_size /= 6;
2707 } else {
2708 fifo_size /= 2;
2709 }
2710 }
2711
2712 /* clamp to max that the registers can hold */
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002713 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
Ville Syrjälä158ae642013-08-07 13:28:19 +03002714}
2715
2716/* Calculate the maximum cursor plane watermark */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08002717static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
Ville Syrjälä240264f2013-08-07 13:29:12 +03002718 int level,
2719 const struct intel_wm_config *config)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002720{
2721 /* HSW LP1+ watermarks w/ multiple pipes */
Ville Syrjälä240264f2013-08-07 13:29:12 +03002722 if (level > 0 && config->num_pipes_active > 1)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002723 return 64;
2724
2725 /* otherwise just report max that registers can hold */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08002726 return ilk_cursor_wm_reg_max(dev_priv, level);
Ville Syrjälä158ae642013-08-07 13:28:19 +03002727}
2728
Matt Ropercd1d3ee2018-12-10 13:54:14 -08002729static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
Ville Syrjälä34982fe2013-10-09 19:18:09 +03002730 int level,
2731 const struct intel_wm_config *config,
2732 enum intel_ddb_partitioning ddb_partitioning,
Imre Deak820c1982013-12-17 14:46:36 +02002733 struct ilk_wm_maximums *max)
Ville Syrjälä158ae642013-08-07 13:28:19 +03002734{
Matt Ropercd1d3ee2018-12-10 13:54:14 -08002735 max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2736 max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2737 max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2738 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
Ville Syrjälä158ae642013-08-07 13:28:19 +03002739}
2740
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002741static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002742 int level,
2743 struct ilk_wm_maximums *max)
2744{
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00002745 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2746 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2747 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2748 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002749}
2750
Ville Syrjäläd9395652013-10-09 19:18:10 +03002751static bool ilk_validate_wm_level(int level,
Imre Deak820c1982013-12-17 14:46:36 +02002752 const struct ilk_wm_maximums *max,
Ville Syrjäläd9395652013-10-09 19:18:10 +03002753 struct intel_wm_level *result)
Ville Syrjäläa9786a12013-08-07 13:24:47 +03002754{
2755 bool ret;
2756
2757 /* already determined to be invalid? */
2758 if (!result->enable)
2759 return false;
2760
2761 result->enable = result->pri_val <= max->pri &&
2762 result->spr_val <= max->spr &&
2763 result->cur_val <= max->cur;
2764
2765 ret = result->enable;
2766
2767 /*
2768 * HACK until we can pre-compute everything,
2769 * and thus fail gracefully if LP0 watermarks
2770 * are exceeded...
2771 */
2772 if (level == 0 && !result->enable) {
2773 if (result->pri_val > max->pri)
2774 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2775 level, result->pri_val, max->pri);
2776 if (result->spr_val > max->spr)
2777 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2778 level, result->spr_val, max->spr);
2779 if (result->cur_val > max->cur)
2780 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2781 level, result->cur_val, max->cur);
2782
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002783 result->pri_val = min_t(u32, result->pri_val, max->pri);
2784 result->spr_val = min_t(u32, result->spr_val, max->spr);
2785 result->cur_val = min_t(u32, result->cur_val, max->cur);
Ville Syrjäläa9786a12013-08-07 13:24:47 +03002786 result->enable = true;
2787 }
2788
Ville Syrjäläa9786a12013-08-07 13:24:47 +03002789 return ret;
2790}
2791
Damien Lespiaud34ff9c2014-01-06 19:17:23 +00002792static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02002793 const struct intel_crtc *crtc,
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002794 int level,
Maarten Lankhorstec193642019-06-28 10:55:17 +02002795 struct intel_crtc_state *crtc_state,
Maarten Lankhorst28283f42017-10-19 17:13:40 +02002796 const struct intel_plane_state *pristate,
2797 const struct intel_plane_state *sprstate,
2798 const struct intel_plane_state *curstate,
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03002799 struct intel_wm_level *result)
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002800{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002801 u16 pri_latency = dev_priv->wm.pri_latency[level];
2802 u16 spr_latency = dev_priv->wm.spr_latency[level];
2803 u16 cur_latency = dev_priv->wm.cur_latency[level];
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002804
2805 /* WM1+ latency values stored in 0.5us units */
2806 if (level > 0) {
2807 pri_latency *= 5;
2808 spr_latency *= 5;
2809 cur_latency *= 5;
2810 }
2811
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002812 if (pristate) {
Maarten Lankhorstec193642019-06-28 10:55:17 +02002813 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002814 pri_latency, level);
Maarten Lankhorstec193642019-06-28 10:55:17 +02002815 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002816 }
2817
2818 if (sprstate)
Maarten Lankhorstec193642019-06-28 10:55:17 +02002819 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002820
2821 if (curstate)
Maarten Lankhorstec193642019-06-28 10:55:17 +02002822 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002823
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002824 result->enable = true;
2825}
2826
Ville Syrjäläbb726512016-10-31 22:37:24 +02002827static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002828 u16 wm[8])
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002829{
Tvrtko Ursulin1cea02d2019-06-10 13:06:07 +01002830 struct intel_uncore *uncore = &dev_priv->uncore;
2831
Paulo Zanoni50682ee2017-08-09 13:52:43 -07002832 if (INTEL_GEN(dev_priv) >= 9) {
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002833 u32 val;
Vandana Kannan4f947382014-11-04 17:06:47 +00002834 int ret, i;
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002835 int level, max_level = ilk_wm_max_level(dev_priv);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002836
2837 /* read the first set of memory latencies[0:3] */
2838 val = 0; /* data0 to be programmed to 0 for first set */
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002839 ret = sandybridge_pcode_read(dev_priv,
2840 GEN9_PCODE_READ_MEM_LATENCY,
Ville Syrjäläd284d512019-05-21 19:40:24 +03002841 &val, NULL);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002842
2843 if (ret) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002844 drm_err(&dev_priv->drm,
2845 "SKL Mailbox read error = %d\n", ret);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002846 return;
2847 }
2848
2849 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2850 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2851 GEN9_MEM_LATENCY_LEVEL_MASK;
2852 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2853 GEN9_MEM_LATENCY_LEVEL_MASK;
2854 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2855 GEN9_MEM_LATENCY_LEVEL_MASK;
2856
2857 /* read the second set of memory latencies[4:7] */
2858 val = 1; /* data0 to be programmed to 1 for second set */
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002859 ret = sandybridge_pcode_read(dev_priv,
2860 GEN9_PCODE_READ_MEM_LATENCY,
Ville Syrjäläd284d512019-05-21 19:40:24 +03002861 &val, NULL);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002862 if (ret) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002863 drm_err(&dev_priv->drm,
2864 "SKL Mailbox read error = %d\n", ret);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002865 return;
2866 }
2867
2868 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2869 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2870 GEN9_MEM_LATENCY_LEVEL_MASK;
2871 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2872 GEN9_MEM_LATENCY_LEVEL_MASK;
2873 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2874 GEN9_MEM_LATENCY_LEVEL_MASK;
2875
Vandana Kannan367294b2014-11-04 17:06:46 +00002876 /*
Paulo Zanoni0727e402016-09-22 18:00:30 -03002877 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2878 * need to be disabled. We make sure to sanitize the values out
2879 * of the punit to satisfy this requirement.
2880 */
2881 for (level = 1; level <= max_level; level++) {
2882 if (wm[level] == 0) {
2883 for (i = level + 1; i <= max_level; i++)
2884 wm[i] = 0;
2885 break;
2886 }
2887 }
2888
2889 /*
Paulo Zanoni50682ee2017-08-09 13:52:43 -07002890 * WaWmMemoryReadLatency:skl+,glk
Damien Lespiau6f972352015-02-09 19:33:07 +00002891 *
Vandana Kannan367294b2014-11-04 17:06:46 +00002892 * punit doesn't take into account the read latency so we need
Paulo Zanoni0727e402016-09-22 18:00:30 -03002893 * to add 2us to the various latency levels we retrieve from the
2894 * punit when level 0 response data us 0us.
Vandana Kannan367294b2014-11-04 17:06:46 +00002895 */
Paulo Zanoni0727e402016-09-22 18:00:30 -03002896 if (wm[0] == 0) {
2897 wm[0] += 2;
2898 for (level = 1; level <= max_level; level++) {
2899 if (wm[level] == 0)
2900 break;
Vandana Kannan367294b2014-11-04 17:06:46 +00002901 wm[level] += 2;
Vandana Kannan4f947382014-11-04 17:06:47 +00002902 }
Paulo Zanoni0727e402016-09-22 18:00:30 -03002903 }
2904
Mahesh Kumar86b59282018-08-31 16:39:42 +05302905 /*
2906 * WA Level-0 adjustment for 16GB DIMMs: SKL+
2907 * If we could not get dimm info enable this WA to prevent from
2908 * any underrun. If not able to get Dimm info assume 16GB dimm
2909 * to avoid any underrun.
2910 */
Ville Syrjälä5d6f36b2018-10-23 21:21:02 +03002911 if (dev_priv->dram_info.is_16gb_dimm)
Mahesh Kumar86b59282018-08-31 16:39:42 +05302912 wm[0] += 1;
2913
Tvrtko Ursulin86527442016-10-13 11:03:00 +01002914 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Tvrtko Ursulin1cea02d2019-06-10 13:06:07 +01002915 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002916
2917 wm[0] = (sskpd >> 56) & 0xFF;
2918 if (wm[0] == 0)
2919 wm[0] = sskpd & 0xF;
Ville Syrjäläe5d50192013-07-05 11:57:22 +03002920 wm[1] = (sskpd >> 4) & 0xFF;
2921 wm[2] = (sskpd >> 12) & 0xFF;
2922 wm[3] = (sskpd >> 20) & 0x1FF;
2923 wm[4] = (sskpd >> 32) & 0x1FF;
Ville Syrjäläbb726512016-10-31 22:37:24 +02002924 } else if (INTEL_GEN(dev_priv) >= 6) {
Tvrtko Ursulin1cea02d2019-06-10 13:06:07 +01002925 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
Ville Syrjälä63cf9a12013-07-05 11:57:23 +03002926
2927 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2928 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2929 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2930 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
Ville Syrjäläbb726512016-10-31 22:37:24 +02002931 } else if (INTEL_GEN(dev_priv) >= 5) {
Tvrtko Ursulin1cea02d2019-06-10 13:06:07 +01002932 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
Ville Syrjälä3a88d0a2013-08-01 16:18:49 +03002933
2934 /* ILK primary LP0 latency is 700 ns */
2935 wm[0] = 7;
2936 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2937 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
Paulo Zanoni50682ee2017-08-09 13:52:43 -07002938 } else {
2939 MISSING_CASE(INTEL_DEVID(dev_priv));
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002940 }
2941}
2942
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002943static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002944 u16 wm[5])
Ville Syrjälä53615a52013-08-01 16:18:50 +03002945{
2946 /* ILK sprite LP0 latency is 1300 ns */
Lucas De Marchicf819ef2018-12-12 10:10:43 -08002947 if (IS_GEN(dev_priv, 5))
Ville Syrjälä53615a52013-08-01 16:18:50 +03002948 wm[0] = 13;
2949}
2950
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +01002951static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002952 u16 wm[5])
Ville Syrjälä53615a52013-08-01 16:18:50 +03002953{
2954 /* ILK cursor LP0 latency is 1300 ns */
Lucas De Marchicf819ef2018-12-12 10:10:43 -08002955 if (IS_GEN(dev_priv, 5))
Ville Syrjälä53615a52013-08-01 16:18:50 +03002956 wm[0] = 13;
Ville Syrjälä53615a52013-08-01 16:18:50 +03002957}
2958
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002959int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03002960{
2961 /* how many WM levels are we expecting */
Tvrtko Ursulin86527442016-10-13 11:03:00 +01002962 if (INTEL_GEN(dev_priv) >= 9)
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002963 return 7;
Tvrtko Ursulin86527442016-10-13 11:03:00 +01002964 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03002965 return 4;
Tvrtko Ursulin86527442016-10-13 11:03:00 +01002966 else if (INTEL_GEN(dev_priv) >= 6)
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03002967 return 3;
2968 else
2969 return 2;
2970}
Daniel Vetter7526ed72014-09-29 15:07:19 +02002971
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002972static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002973 const char *name,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02002974 const u16 wm[8])
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002975{
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002976 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002977
2978 for (level = 0; level <= max_level; level++) {
2979 unsigned int latency = wm[level];
2980
2981 if (latency == 0) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002982 drm_dbg_kms(&dev_priv->drm,
2983 "%s WM%d latency not provided\n",
2984 name, level);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002985 continue;
2986 }
2987
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002988 /*
2989 * - latencies are in us on gen9.
2990 * - before then, WM1+ latency values are in 0.5us units
2991 */
Paulo Zanonidfc267a2017-08-09 13:52:46 -07002992 if (INTEL_GEN(dev_priv) >= 9)
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002993 latency *= 10;
2994 else if (level > 0)
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002995 latency *= 5;
2996
Wambui Karugaf8d18d52020-01-07 18:13:30 +03002997 drm_dbg_kms(&dev_priv->drm,
2998 "%s WM%d latency %u (%u.%u usec)\n", name, level,
2999 wm[level], latency / 10, latency % 10);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03003000 }
3001}
3002
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003003static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
Jani Nikula5ce9a6492019-01-18 14:01:20 +02003004 u16 wm[5], u16 min)
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003005{
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003006 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003007
3008 if (wm[0] >= min)
3009 return false;
3010
3011 wm[0] = max(wm[0], min);
3012 for (level = 1; level <= max_level; level++)
Jani Nikula5ce9a6492019-01-18 14:01:20 +02003013 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003014
3015 return true;
3016}
3017
Ville Syrjäläbb726512016-10-31 22:37:24 +02003018static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003019{
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003020 bool changed;
3021
3022 /*
3023 * The BIOS provided WM memory latency values are often
3024 * inadequate for high resolution displays. Adjust them.
3025 */
3026 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3027 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3028 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3029
3030 if (!changed)
3031 return;
3032
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003033 drm_dbg_kms(&dev_priv->drm,
3034 "WM latency values increased to avoid potential underruns\n");
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003035 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3036 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3037 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003038}
3039
Ville Syrjälä03981c62018-11-14 19:34:40 +02003040static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3041{
3042 /*
3043 * On some SNB machines (Thinkpad X220 Tablet at least)
3044 * LP3 usage can cause vblank interrupts to be lost.
3045 * The DEIIR bit will go high but it looks like the CPU
3046 * never gets interrupted.
3047 *
3048 * It's not clear whether other interrupt source could
3049 * be affected or if this is somehow limited to vblank
3050 * interrupts only. To play it safe we disable LP3
3051 * watermarks entirely.
3052 */
3053 if (dev_priv->wm.pri_latency[3] == 0 &&
3054 dev_priv->wm.spr_latency[3] == 0 &&
3055 dev_priv->wm.cur_latency[3] == 0)
3056 return;
3057
3058 dev_priv->wm.pri_latency[3] = 0;
3059 dev_priv->wm.spr_latency[3] = 0;
3060 dev_priv->wm.cur_latency[3] = 0;
3061
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003062 drm_dbg_kms(&dev_priv->drm,
3063 "LP3 watermarks disabled due to potential for lost interrupts\n");
Ville Syrjälä03981c62018-11-14 19:34:40 +02003064 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3065 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3066 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3067}
3068
Ville Syrjäläbb726512016-10-31 22:37:24 +02003069static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
Ville Syrjälä53615a52013-08-01 16:18:50 +03003070{
Ville Syrjäläbb726512016-10-31 22:37:24 +02003071 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
Ville Syrjälä53615a52013-08-01 16:18:50 +03003072
3073 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3074 sizeof(dev_priv->wm.pri_latency));
3075 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3076 sizeof(dev_priv->wm.pri_latency));
3077
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003078 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +01003079 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03003080
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003081 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3082 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3083 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03003084
Lucas De Marchicf819ef2018-12-12 10:10:43 -08003085 if (IS_GEN(dev_priv, 6)) {
Ville Syrjäläbb726512016-10-31 22:37:24 +02003086 snb_wm_latency_quirk(dev_priv);
Ville Syrjälä03981c62018-11-14 19:34:40 +02003087 snb_wm_lp3_irq_quirk(dev_priv);
3088 }
Ville Syrjälä53615a52013-08-01 16:18:50 +03003089}
3090
Ville Syrjäläbb726512016-10-31 22:37:24 +02003091static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
Pradeep Bhat2af30a52014-11-04 17:06:38 +00003092{
Ville Syrjäläbb726512016-10-31 22:37:24 +02003093 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003094 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00003095}
3096
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003097static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
Matt Ropered4a6a72016-02-23 17:20:13 -08003098 struct intel_pipe_wm *pipe_wm)
3099{
3100 /* LP0 watermark maximums depend on this pipe alone */
3101 const struct intel_wm_config config = {
3102 .num_pipes_active = 1,
3103 .sprites_enabled = pipe_wm->sprites_enabled,
3104 .sprites_scaled = pipe_wm->sprites_scaled,
3105 };
3106 struct ilk_wm_maximums max;
3107
3108 /* LP0 watermarks always use 1/2 DDB partitioning */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003109 ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
Matt Ropered4a6a72016-02-23 17:20:13 -08003110
3111 /* At least LP0 must be valid */
3112 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003113 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
Matt Ropered4a6a72016-02-23 17:20:13 -08003114 return false;
3115 }
3116
3117 return true;
3118}
3119
Matt Roper261a27d2015-10-08 15:28:25 -07003120/* Compute new watermarks for the pipe */
Maarten Lankhorstec193642019-06-28 10:55:17 +02003121static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
Matt Roper261a27d2015-10-08 15:28:25 -07003122{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01003123 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02003124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Matt Roper86c8bbb2015-09-24 15:53:16 -07003125 struct intel_pipe_wm *pipe_wm;
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02003126 struct intel_plane *plane;
3127 const struct intel_plane_state *plane_state;
Maarten Lankhorst28283f42017-10-19 17:13:40 +02003128 const struct intel_plane_state *pristate = NULL;
3129 const struct intel_plane_state *sprstate = NULL;
3130 const struct intel_plane_state *curstate = NULL;
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003131 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
Imre Deak820c1982013-12-17 14:46:36 +02003132 struct ilk_wm_maximums max;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003133
Maarten Lankhorstec193642019-06-28 10:55:17 +02003134 pipe_wm = &crtc_state->wm.ilk.optimal;
Matt Roper86c8bbb2015-09-24 15:53:16 -07003135
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02003136 intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
3137 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3138 pristate = plane_state;
3139 else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3140 sprstate = plane_state;
3141 else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
3142 curstate = plane_state;
Matt Roper43d59ed2015-09-24 15:53:07 -07003143 }
3144
Maarten Lankhorst1326a922019-10-31 12:26:02 +01003145 pipe_wm->pipe_enabled = crtc_state->hw.active;
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01003146 if (sprstate) {
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01003147 pipe_wm->sprites_enabled = sprstate->uapi.visible;
3148 pipe_wm->sprites_scaled = sprstate->uapi.visible &&
3149 (drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
3150 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01003151 }
3152
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01003153 usable_level = max_level;
3154
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02003155 /* ILK/SNB: LP2+ watermarks only w/o sprites */
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00003156 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01003157 usable_level = 1;
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02003158
3159 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
Matt Ropered4a6a72016-02-23 17:20:13 -08003160 if (pipe_wm->sprites_scaled)
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01003161 usable_level = 0;
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02003162
Maarten Lankhorst71f0a622016-03-08 10:57:16 +01003163 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02003164 ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
Maarten Lankhorst28283f42017-10-19 17:13:40 +02003165 pristate, sprstate, curstate, &pipe_wm->wm[0]);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003166
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003167 if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
Maarten Lankhorst1a426d62016-03-02 12:36:03 +01003168 return -EINVAL;
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03003169
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00003170 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03003171
Maarten Lankhorst28283f42017-10-19 17:13:40 +02003172 for (level = 1; level <= usable_level; level++) {
3173 struct intel_wm_level *wm = &pipe_wm->wm[level];
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03003174
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02003175 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01003176 pristate, sprstate, curstate, wm);
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03003177
3178 /*
3179 * Disable any watermark level that exceeds the
3180 * register maximums since such watermarks are
3181 * always invalid.
3182 */
Maarten Lankhorst28283f42017-10-19 17:13:40 +02003183 if (!ilk_validate_wm_level(level, &max, wm)) {
3184 memset(wm, 0, sizeof(*wm));
3185 break;
3186 }
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03003187 }
3188
Matt Roper86c8bbb2015-09-24 15:53:16 -07003189 return 0;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003190}
3191
3192/*
Matt Ropered4a6a72016-02-23 17:20:13 -08003193 * Build a set of 'intermediate' watermark values that satisfy both the old
3194 * state and the new state. These can be programmed to the hardware
3195 * immediately.
3196 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003197static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
Matt Ropered4a6a72016-02-23 17:20:13 -08003198{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01003199 struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003200 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
Matt Ropere8f1f022016-05-12 07:05:55 -07003201 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
Maarten Lankhorstb6b178a2017-10-19 17:13:41 +02003202 struct intel_atomic_state *intel_state =
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01003203 to_intel_atomic_state(newstate->uapi.state);
Maarten Lankhorstb6b178a2017-10-19 17:13:41 +02003204 const struct intel_crtc_state *oldstate =
3205 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3206 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003207 int level, max_level = ilk_wm_max_level(dev_priv);
Matt Ropered4a6a72016-02-23 17:20:13 -08003208
3209 /*
3210 * Start with the final, target watermarks, then combine with the
3211 * currently active watermarks to get values that are safe both before
3212 * and after the vblank.
3213 */
Matt Ropere8f1f022016-05-12 07:05:55 -07003214 *a = newstate->wm.ilk.optimal;
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01003215 if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
Ville Syrjäläf255c622018-11-08 17:10:13 +02003216 intel_state->skip_intermediate_wm)
Maarten Lankhorstb6b178a2017-10-19 17:13:41 +02003217 return 0;
3218
Matt Ropered4a6a72016-02-23 17:20:13 -08003219 a->pipe_enabled |= b->pipe_enabled;
3220 a->sprites_enabled |= b->sprites_enabled;
3221 a->sprites_scaled |= b->sprites_scaled;
3222
3223 for (level = 0; level <= max_level; level++) {
3224 struct intel_wm_level *a_wm = &a->wm[level];
3225 const struct intel_wm_level *b_wm = &b->wm[level];
3226
3227 a_wm->enable &= b_wm->enable;
3228 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3229 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3230 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3231 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3232 }
3233
3234 /*
3235 * We need to make sure that these merged watermark values are
3236 * actually a valid configuration themselves. If they're not,
3237 * there's no safe way to transition from the old state to
3238 * the new state, so we need to fail the atomic transaction.
3239 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003240 if (!ilk_validate_pipe_wm(dev_priv, a))
Matt Ropered4a6a72016-02-23 17:20:13 -08003241 return -EINVAL;
3242
3243 /*
3244 * If our intermediate WM are identical to the final WM, then we can
3245 * omit the post-vblank programming; only update if it's different.
3246 */
Ville Syrjälä5eeb7982017-03-02 19:15:00 +02003247 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3248 newstate->wm.need_postvbl_update = true;
Matt Ropered4a6a72016-02-23 17:20:13 -08003249
3250 return 0;
3251}
3252
3253/*
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003254 * Merge the watermarks from all active pipes for a specific level.
3255 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003256static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003257 int level,
3258 struct intel_wm_level *ret_wm)
3259{
3260 const struct intel_crtc *intel_crtc;
3261
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003262 ret_wm->enable = true;
3263
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003264 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
Matt Ropered4a6a72016-02-23 17:20:13 -08003265 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
Ville Syrjäläfe392ef2014-03-07 18:32:10 +02003266 const struct intel_wm_level *wm = &active->wm[level];
3267
3268 if (!active->pipe_enabled)
3269 continue;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003270
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003271 /*
3272 * The watermark values may have been used in the past,
3273 * so we must maintain them in the registers for some
3274 * time even if the level is now disabled.
3275 */
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003276 if (!wm->enable)
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003277 ret_wm->enable = false;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003278
3279 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3280 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3281 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3282 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3283 }
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003284}
3285
3286/*
3287 * Merge all low power watermarks for all active pipes.
3288 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003289static void ilk_wm_merge(struct drm_i915_private *dev_priv,
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02003290 const struct intel_wm_config *config,
Imre Deak820c1982013-12-17 14:46:36 +02003291 const struct ilk_wm_maximums *max,
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003292 struct intel_pipe_wm *merged)
3293{
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003294 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003295 int last_enabled_level = max_level;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003296
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02003297 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +01003298 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02003299 config->num_pipes_active > 1)
Ville Syrjälä1204d5b2016-04-01 21:53:18 +03003300 last_enabled_level = 0;
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02003301
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02003302 /* ILK: FBC WM must be disabled always */
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00003303 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003304
3305 /* merge each WM1+ level */
3306 for (level = 1; level <= max_level; level++) {
3307 struct intel_wm_level *wm = &merged->wm[level];
3308
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003309 ilk_merge_wm_level(dev_priv, level, wm);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003310
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003311 if (level > last_enabled_level)
3312 wm->enable = false;
3313 else if (!ilk_validate_wm_level(level, max, wm))
3314 /* make sure all following levels get disabled */
3315 last_enabled_level = level - 1;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003316
3317 /*
3318 * The spec says it is preferred to disable
3319 * FBC WMs instead of disabling a WM level.
3320 */
3321 if (wm->fbc_val > max->fbc) {
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003322 if (wm->enable)
3323 merged->fbc_wm_enabled = false;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003324 wm->fbc_val = 0;
3325 }
3326 }
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02003327
3328 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3329 /*
3330 * FIXME this is racy. FBC might get enabled later.
3331 * What we should check here is whether FBC can be
3332 * enabled sometime later.
3333 */
Lucas De Marchicf819ef2018-12-12 10:10:43 -08003334 if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03003335 intel_fbc_is_active(dev_priv)) {
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02003336 for (level = 2; level <= max_level; level++) {
3337 struct intel_wm_level *wm = &merged->wm[level];
3338
3339 wm->enable = false;
3340 }
3341 }
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003342}
3343
Ville Syrjäläb380ca32013-10-09 19:18:01 +03003344static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3345{
3346 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3347 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3348}
3349
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02003350/* The value we need to program into the WM_LPx latency field */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003351static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3352 int level)
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02003353{
Tvrtko Ursulin86527442016-10-13 11:03:00 +01003354 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02003355 return 2 * level;
3356 else
3357 return dev_priv->wm.pri_latency[level];
3358}
3359
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003360static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
Ville Syrjälä0362c782013-10-09 19:17:57 +03003361 const struct intel_pipe_wm *merged,
Ville Syrjälä609cede2013-10-09 19:18:03 +03003362 enum intel_ddb_partitioning partitioning,
Imre Deak820c1982013-12-17 14:46:36 +02003363 struct ilk_wm_values *results)
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03003364{
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003365 struct intel_crtc *intel_crtc;
3366 int level, wm_lp;
Paulo Zanonicca32e92013-05-31 11:45:06 -03003367
Ville Syrjälä0362c782013-10-09 19:17:57 +03003368 results->enable_fbc_wm = merged->fbc_wm_enabled;
Ville Syrjälä609cede2013-10-09 19:18:03 +03003369 results->partitioning = partitioning;
Paulo Zanonicca32e92013-05-31 11:45:06 -03003370
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003371 /* LP1+ register values */
Paulo Zanonicca32e92013-05-31 11:45:06 -03003372 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03003373 const struct intel_wm_level *r;
Paulo Zanonicca32e92013-05-31 11:45:06 -03003374
Ville Syrjäläb380ca32013-10-09 19:18:01 +03003375 level = ilk_wm_lp_to_level(wm_lp, merged);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003376
Ville Syrjälä0362c782013-10-09 19:17:57 +03003377 r = &merged->wm[level];
Paulo Zanonicca32e92013-05-31 11:45:06 -03003378
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003379 /*
3380 * Maintain the watermark values even if the level is
3381 * disabled. Doing otherwise could cause underruns.
3382 */
3383 results->wm_lp[wm_lp - 1] =
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003384 (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
Ville Syrjälä416f4722013-11-02 21:07:46 -07003385 (r->pri_val << WM1_LP_SR_SHIFT) |
3386 r->cur_val;
3387
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003388 if (r->enable)
3389 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3390
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00003391 if (INTEL_GEN(dev_priv) >= 8)
Ville Syrjälä416f4722013-11-02 21:07:46 -07003392 results->wm_lp[wm_lp - 1] |=
3393 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3394 else
3395 results->wm_lp[wm_lp - 1] |=
3396 r->fbc_val << WM1_LP_FBC_SHIFT;
3397
Ville Syrjäläd52fea52014-04-28 15:44:57 +03003398 /*
3399 * Always set WM1S_LP_EN when spr_val != 0, even if the
3400 * level is disabled. Doing otherwise could cause underruns.
3401 */
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00003402 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05303403 drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02003404 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3405 } else
3406 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
Paulo Zanonicca32e92013-05-31 11:45:06 -03003407 }
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003408
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003409 /* LP0 register values */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003410 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003411 enum pipe pipe = intel_crtc->pipe;
Ville Syrjälä0560b0c2020-01-20 19:47:11 +02003412 const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
3413 const struct intel_wm_level *r = &pipe_wm->wm[0];
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03003414
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05303415 if (drm_WARN_ON(&dev_priv->drm, !r->enable))
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003416 continue;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03003417
3418 results->wm_pipe[pipe] =
3419 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3420 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3421 r->cur_val;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003422 }
3423}
3424
Paulo Zanoni861f3382013-05-31 10:19:21 -03003425/* Find the result with the highest level enabled. Check for enable_fbc_wm in
3426 * case both are at the same level. Prefer r1 in case they're the same. */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003427static struct intel_pipe_wm *
3428ilk_find_best_result(struct drm_i915_private *dev_priv,
3429 struct intel_pipe_wm *r1,
3430 struct intel_pipe_wm *r2)
Paulo Zanoni861f3382013-05-31 10:19:21 -03003431{
Matt Ropercd1d3ee2018-12-10 13:54:14 -08003432 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003433 int level1 = 0, level2 = 0;
Paulo Zanoni861f3382013-05-31 10:19:21 -03003434
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003435 for (level = 1; level <= max_level; level++) {
3436 if (r1->wm[level].enable)
3437 level1 = level;
3438 if (r2->wm[level].enable)
3439 level2 = level;
Paulo Zanoni861f3382013-05-31 10:19:21 -03003440 }
3441
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003442 if (level1 == level2) {
3443 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
Paulo Zanoni861f3382013-05-31 10:19:21 -03003444 return r2;
3445 else
3446 return r1;
Ville Syrjälä198a1e92013-10-09 19:17:58 +03003447 } else if (level1 > level2) {
Paulo Zanoni861f3382013-05-31 10:19:21 -03003448 return r1;
3449 } else {
3450 return r2;
3451 }
3452}
3453
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003454/* dirty bits used to track which watermarks need changes */
3455#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003456#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3457#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3458#define WM_DIRTY_FBC (1 << 24)
3459#define WM_DIRTY_DDB (1 << 25)
3460
Damien Lespiau055e3932014-08-18 13:49:10 +01003461static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
Imre Deak820c1982013-12-17 14:46:36 +02003462 const struct ilk_wm_values *old,
3463 const struct ilk_wm_values *new)
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003464{
3465 unsigned int dirty = 0;
3466 enum pipe pipe;
3467 int wm_lp;
3468
Damien Lespiau055e3932014-08-18 13:49:10 +01003469 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003470 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3471 dirty |= WM_DIRTY_PIPE(pipe);
3472 /* Must disable LP1+ watermarks too */
3473 dirty |= WM_DIRTY_LP_ALL;
3474 }
3475 }
3476
3477 if (old->enable_fbc_wm != new->enable_fbc_wm) {
3478 dirty |= WM_DIRTY_FBC;
3479 /* Must disable LP1+ watermarks too */
3480 dirty |= WM_DIRTY_LP_ALL;
3481 }
3482
3483 if (old->partitioning != new->partitioning) {
3484 dirty |= WM_DIRTY_DDB;
3485 /* Must disable LP1+ watermarks too */
3486 dirty |= WM_DIRTY_LP_ALL;
3487 }
3488
3489 /* LP1+ watermarks already deemed dirty, no need to continue */
3490 if (dirty & WM_DIRTY_LP_ALL)
3491 return dirty;
3492
3493 /* Find the lowest numbered LP1+ watermark in need of an update... */
3494 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3495 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3496 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3497 break;
3498 }
3499
3500 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3501 for (; wm_lp <= 3; wm_lp++)
3502 dirty |= WM_DIRTY_LP(wm_lp);
3503
3504 return dirty;
3505}
3506
Ville Syrjälä8553c182013-12-05 15:51:39 +02003507static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3508 unsigned int dirty)
3509{
Imre Deak820c1982013-12-17 14:46:36 +02003510 struct ilk_wm_values *previous = &dev_priv->wm.hw;
Ville Syrjälä8553c182013-12-05 15:51:39 +02003511 bool changed = false;
3512
3513 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3514 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3515 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3516 changed = true;
3517 }
3518 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3519 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3520 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3521 changed = true;
3522 }
3523 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3524 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3525 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3526 changed = true;
3527 }
3528
3529 /*
3530 * Don't touch WM1S_LP_EN here.
3531 * Doing so could cause underruns.
3532 */
3533
3534 return changed;
3535}
3536
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003537/*
3538 * The spec says we shouldn't write when we don't need, because every write
3539 * causes WMs to be re-evaluated, expending some power.
3540 */
Imre Deak820c1982013-12-17 14:46:36 +02003541static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3542 struct ilk_wm_values *results)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003543{
Imre Deak820c1982013-12-17 14:46:36 +02003544 struct ilk_wm_values *previous = &dev_priv->wm.hw;
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003545 unsigned int dirty;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02003546 u32 val;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003547
Damien Lespiau055e3932014-08-18 13:49:10 +01003548 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003549 if (!dirty)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003550 return;
3551
Ville Syrjälä8553c182013-12-05 15:51:39 +02003552 _ilk_disable_lp_wm(dev_priv, dirty);
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02003553
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003554 if (dirty & WM_DIRTY_PIPE(PIPE_A))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003555 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003556 if (dirty & WM_DIRTY_PIPE(PIPE_B))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003557 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003558 if (dirty & WM_DIRTY_PIPE(PIPE_C))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003559 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3560
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003561 if (dirty & WM_DIRTY_DDB) {
Tvrtko Ursulin86527442016-10-13 11:03:00 +01003562 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Ville Syrjäläac9545f2013-12-05 15:51:28 +02003563 val = I915_READ(WM_MISC);
3564 if (results->partitioning == INTEL_DDB_PART_1_2)
3565 val &= ~WM_MISC_DATA_PARTITION_5_6;
3566 else
3567 val |= WM_MISC_DATA_PARTITION_5_6;
3568 I915_WRITE(WM_MISC, val);
3569 } else {
3570 val = I915_READ(DISP_ARB_CTL2);
3571 if (results->partitioning == INTEL_DDB_PART_1_2)
3572 val &= ~DISP_DATA_PARTITION_5_6;
3573 else
3574 val |= DISP_DATA_PARTITION_5_6;
3575 I915_WRITE(DISP_ARB_CTL2, val);
3576 }
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03003577 }
3578
Ville Syrjälä49a687c2013-10-11 19:39:52 +03003579 if (dirty & WM_DIRTY_FBC) {
Paulo Zanonicca32e92013-05-31 11:45:06 -03003580 val = I915_READ(DISP_ARB_CTL);
3581 if (results->enable_fbc_wm)
3582 val &= ~DISP_FBC_WM_DIS;
3583 else
3584 val |= DISP_FBC_WM_DIS;
3585 I915_WRITE(DISP_ARB_CTL, val);
3586 }
3587
Imre Deak954911e2013-12-17 14:46:34 +02003588 if (dirty & WM_DIRTY_LP(1) &&
3589 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3590 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3591
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00003592 if (INTEL_GEN(dev_priv) >= 7) {
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02003593 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3594 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3595 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3596 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3597 }
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003598
Ville Syrjäläfacd619b2013-12-05 15:51:33 +02003599 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003600 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
Ville Syrjäläfacd619b2013-12-05 15:51:33 +02003601 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003602 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
Ville Syrjäläfacd619b2013-12-05 15:51:33 +02003603 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003604 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
Ville Syrjälä609cede2013-10-09 19:18:03 +03003605
3606 dev_priv->wm.hw = *results;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03003607}
3608
Ville Syrjälä60aca572019-11-27 21:05:51 +02003609bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
Ville Syrjälä8553c182013-12-05 15:51:39 +02003610{
Ville Syrjälä8553c182013-12-05 15:51:39 +02003611 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3612}
3613
Stanislav Lisovskiy0f0f9ae2020-02-03 01:06:29 +02003614u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
Mahesh Kumar74bd8002018-04-26 19:55:15 +05303615{
Stanislav Lisovskiy0f0f9ae2020-02-03 01:06:29 +02003616 int i;
3617 int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
3618 u8 enabled_slices_mask = 0;
Mahesh Kumar74bd8002018-04-26 19:55:15 +05303619
Stanislav Lisovskiy0f0f9ae2020-02-03 01:06:29 +02003620 for (i = 0; i < max_slices; i++) {
3621 if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
3622 enabled_slices_mask |= BIT(i);
3623 }
Mahesh Kumar74bd8002018-04-26 19:55:15 +05303624
Stanislav Lisovskiy0f0f9ae2020-02-03 01:06:29 +02003625 return enabled_slices_mask;
Mahesh Kumar74bd8002018-04-26 19:55:15 +05303626}
3627
Matt Roper024c9042015-09-24 15:53:11 -07003628/*
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003629 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3630 * so assume we'll always need it in order to avoid underruns.
3631 */
Ville Syrjälä60e983f2018-12-21 19:14:33 +02003632static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003633{
Ville Syrjälä60e983f2018-12-21 19:14:33 +02003634 return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003635}
3636
Paulo Zanoni56feca92016-09-22 18:00:28 -03003637static bool
3638intel_has_sagv(struct drm_i915_private *dev_priv)
3639{
Lucas De Marchi8ffa4392019-09-04 14:34:18 -07003640 /* HACK! */
3641 if (IS_GEN(dev_priv, 12))
3642 return false;
3643
Rodrigo Vivi1ca2b062018-10-26 13:03:17 -07003644 return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
3645 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
Paulo Zanoni56feca92016-09-22 18:00:28 -03003646}
3647
James Ausmusb068a862019-10-09 10:23:14 -07003648static void
3649skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
3650{
James Ausmusda80f042019-10-09 10:23:15 -07003651 if (INTEL_GEN(dev_priv) >= 12) {
3652 u32 val = 0;
3653 int ret;
3654
3655 ret = sandybridge_pcode_read(dev_priv,
3656 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3657 &val, NULL);
3658 if (!ret) {
3659 dev_priv->sagv_block_time_us = val;
3660 return;
3661 }
3662
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003663 drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
James Ausmusda80f042019-10-09 10:23:15 -07003664 } else if (IS_GEN(dev_priv, 11)) {
James Ausmusb068a862019-10-09 10:23:14 -07003665 dev_priv->sagv_block_time_us = 10;
3666 return;
3667 } else if (IS_GEN(dev_priv, 10)) {
3668 dev_priv->sagv_block_time_us = 20;
3669 return;
3670 } else if (IS_GEN(dev_priv, 9)) {
3671 dev_priv->sagv_block_time_us = 30;
3672 return;
3673 } else {
3674 MISSING_CASE(INTEL_GEN(dev_priv));
3675 }
3676
3677 /* Default to an unusable block time */
3678 dev_priv->sagv_block_time_us = -1;
3679}
3680
Lyude656d1b82016-08-17 15:55:54 -04003681/*
3682 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3683 * depending on power and performance requirements. The display engine access
3684 * to system memory is blocked during the adjustment time. Because of the
3685 * blocking time, having this enabled can cause full system hangs and/or pipe
3686 * underruns if we don't meet all of the following requirements:
3687 *
3688 * - <= 1 pipe enabled
3689 * - All planes can enable watermarks for latencies >= SAGV engine block time
3690 * - We're not using an interlaced display configuration
3691 */
3692int
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03003693intel_enable_sagv(struct drm_i915_private *dev_priv)
Lyude656d1b82016-08-17 15:55:54 -04003694{
3695 int ret;
3696
Paulo Zanoni56feca92016-09-22 18:00:28 -03003697 if (!intel_has_sagv(dev_priv))
3698 return 0;
3699
3700 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
Lyude656d1b82016-08-17 15:55:54 -04003701 return 0;
3702
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003703 drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
Lyude656d1b82016-08-17 15:55:54 -04003704 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3705 GEN9_SAGV_ENABLE);
3706
Ville Syrjäläff61a972018-12-21 19:14:34 +02003707 /* We don't need to wait for SAGV when enabling */
Lyude656d1b82016-08-17 15:55:54 -04003708
3709 /*
3710 * Some skl systems, pre-release machines in particular,
Ville Syrjäläff61a972018-12-21 19:14:34 +02003711 * don't actually have SAGV.
Lyude656d1b82016-08-17 15:55:54 -04003712 */
Paulo Zanoni6e3100e2016-09-22 18:00:29 -03003713 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003714 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03003715 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
Lyude656d1b82016-08-17 15:55:54 -04003716 return 0;
3717 } else if (ret < 0) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003718 drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
Lyude656d1b82016-08-17 15:55:54 -04003719 return ret;
3720 }
3721
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03003722 dev_priv->sagv_status = I915_SAGV_ENABLED;
Lyude656d1b82016-08-17 15:55:54 -04003723 return 0;
3724}
3725
Lyude656d1b82016-08-17 15:55:54 -04003726int
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03003727intel_disable_sagv(struct drm_i915_private *dev_priv)
Lyude656d1b82016-08-17 15:55:54 -04003728{
Imre Deakb3b8e992016-12-05 18:27:38 +02003729 int ret;
Lyude656d1b82016-08-17 15:55:54 -04003730
Paulo Zanoni56feca92016-09-22 18:00:28 -03003731 if (!intel_has_sagv(dev_priv))
3732 return 0;
3733
3734 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
Lyude656d1b82016-08-17 15:55:54 -04003735 return 0;
3736
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003737 drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
Lyude656d1b82016-08-17 15:55:54 -04003738 /* bspec says to keep retrying for at least 1 ms */
Imre Deakb3b8e992016-12-05 18:27:38 +02003739 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3740 GEN9_SAGV_DISABLE,
3741 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3742 1);
Lyude656d1b82016-08-17 15:55:54 -04003743 /*
3744 * Some skl systems, pre-release machines in particular,
Ville Syrjäläff61a972018-12-21 19:14:34 +02003745 * don't actually have SAGV.
Lyude656d1b82016-08-17 15:55:54 -04003746 */
Imre Deakb3b8e992016-12-05 18:27:38 +02003747 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003748 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03003749 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
Lyude656d1b82016-08-17 15:55:54 -04003750 return 0;
Imre Deakb3b8e992016-12-05 18:27:38 +02003751 } else if (ret < 0) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03003752 drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
Imre Deakb3b8e992016-12-05 18:27:38 +02003753 return ret;
Lyude656d1b82016-08-17 15:55:54 -04003754 }
3755
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03003756 dev_priv->sagv_status = I915_SAGV_DISABLED;
Lyude656d1b82016-08-17 15:55:54 -04003757 return 0;
3758}
3759
Stanislav Lisovskiy680e1af2020-04-15 17:39:04 +03003760void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
3761{
3762 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3763
3764 if (!intel_can_enable_sagv(state))
3765 intel_disable_sagv(dev_priv);
3766}
3767
3768void intel_sagv_post_plane_update(struct intel_atomic_state *state)
3769{
3770 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3771
3772 if (intel_can_enable_sagv(state))
3773 intel_enable_sagv(dev_priv);
3774}
3775
Stanislav Lisovskiya389c492020-04-15 17:57:40 +03003776static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
Lyude656d1b82016-08-17 15:55:54 -04003777{
Stanislav Lisovskiya389c492020-04-15 17:57:40 +03003778 struct drm_device *dev = crtc_state->uapi.crtc->dev;
Lyude656d1b82016-08-17 15:55:54 -04003779 struct drm_i915_private *dev_priv = to_i915(dev);
Stanislav Lisovskiya389c492020-04-15 17:57:40 +03003780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003781 struct intel_plane *plane;
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02003782 int level, latency;
Lyude656d1b82016-08-17 15:55:54 -04003783
Stanislav Lisovskiya389c492020-04-15 17:57:40 +03003784 if (!crtc_state->hw.active)
Lyude656d1b82016-08-17 15:55:54 -04003785 return true;
Lucas De Marchida172232019-04-04 16:04:26 -07003786
Maarten Lankhorst1326a922019-10-31 12:26:02 +01003787 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Lyude656d1b82016-08-17 15:55:54 -04003788 return false;
3789
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003790 for_each_intel_plane_on_crtc(dev, crtc, plane) {
Stanislav Lisovskiya389c492020-04-15 17:57:40 +03003791 const struct skl_plane_wm *wm =
Maarten Lankhorstec193642019-06-28 10:55:17 +02003792 &crtc_state->wm.skl.optimal.planes[plane->id];
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003793
Lyude656d1b82016-08-17 15:55:54 -04003794 /* Skip this plane if it's not enabled */
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02003795 if (!wm->wm[0].plane_en)
Lyude656d1b82016-08-17 15:55:54 -04003796 continue;
3797
3798 /* Find the highest enabled wm level for this plane */
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003799 for (level = ilk_wm_max_level(dev_priv);
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02003800 !wm->wm[level].plane_en; --level)
Lyude656d1b82016-08-17 15:55:54 -04003801 { }
3802
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003803 latency = dev_priv->wm.skl_latency[level];
3804
Ville Syrjälä60e983f2018-12-21 19:14:33 +02003805 if (skl_needs_memory_bw_wa(dev_priv) &&
Ville Syrjäläbae781b2016-11-16 13:33:16 +02003806 plane->base.state->fb->modifier ==
Paulo Zanoniee3d5322016-10-11 15:25:38 -03003807 I915_FORMAT_MOD_X_TILED)
3808 latency += 15;
3809
Lyude656d1b82016-08-17 15:55:54 -04003810 /*
Paulo Zanonifdd11c22017-08-09 13:52:45 -07003811 * If any of the planes on this pipe don't enable wm levels that
3812 * incur memory latencies higher than sagv_block_time_us we
Ville Syrjäläff61a972018-12-21 19:14:34 +02003813 * can't enable SAGV.
Lyude656d1b82016-08-17 15:55:54 -04003814 */
James Ausmusb068a862019-10-09 10:23:14 -07003815 if (latency < dev_priv->sagv_block_time_us)
Lyude656d1b82016-08-17 15:55:54 -04003816 return false;
3817 }
3818
3819 return true;
3820}
3821
Stanislav Lisovskiya389c492020-04-15 17:57:40 +03003822bool intel_can_enable_sagv(struct intel_atomic_state *state)
3823{
3824 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3825 struct intel_crtc *crtc;
3826 const struct intel_crtc_state *crtc_state;
3827 enum pipe pipe;
3828
3829 if (!intel_has_sagv(dev_priv))
3830 return false;
3831
3832 /*
3833 * If there are no active CRTCs, no additional checks need be performed
3834 */
3835 if (hweight8(state->active_pipes) == 0)
3836 return true;
3837
3838 /*
3839 * SKL+ workaround: bspec recommends we disable SAGV when we have
3840 * more then one pipe enabled
3841 */
3842 if (hweight8(state->active_pipes) > 1)
3843 return false;
3844
3845 /* Since we're now guaranteed to only have one active CRTC... */
3846 pipe = ffs(state->active_pipes) - 1;
3847 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3848 crtc_state = to_intel_crtc_state(crtc->base.state);
3849
3850 return intel_crtc_can_enable_sagv(crtc_state);
3851}
3852
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003853/*
3854 * Calculate initial DBuf slice offset, based on slice size
3855 * and mask(i.e if slice size is 1024 and second slice is enabled
3856 * offset would be 1024)
3857 */
3858static unsigned int
3859icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
3860 u32 slice_size,
3861 u32 ddb_size)
Mahesh Kumaraa9664f2018-04-26 19:55:16 +05303862{
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003863 unsigned int offset = 0;
3864
3865 if (!dbuf_slice_mask)
3866 return 0;
3867
3868 offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
3869
3870 WARN_ON(offset >= ddb_size);
3871 return offset;
3872}
3873
3874static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
3875{
Mahesh Kumaraa9664f2018-04-26 19:55:16 +05303876 u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3877
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05303878 drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
Mahesh Kumaraa9664f2018-04-26 19:55:16 +05303879
3880 if (INTEL_GEN(dev_priv) < 11)
3881 return ddb_size - 4; /* 4 blocks for bypass path allocation */
3882
Mahesh Kumaraa9664f2018-04-26 19:55:16 +05303883 return ddb_size;
3884}
3885
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003886static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
Ville Syrjälä05e81552020-02-25 19:11:09 +02003887 u8 active_pipes);
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003888
Damien Lespiaub9cec072014-11-04 17:06:43 +00003889static void
Maarten Lankhorstb048a002018-10-18 13:51:30 +02003890skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
Maarten Lankhorstec193642019-06-28 10:55:17 +02003891 const struct intel_crtc_state *crtc_state,
Maarten Lankhorst24719e92018-10-22 12:20:00 +02003892 const u64 total_data_rate,
Matt Roperc107acf2016-05-12 07:06:01 -07003893 struct skl_ddb_entry *alloc, /* out */
3894 int *num_active /* out */)
Damien Lespiaub9cec072014-11-04 17:06:43 +00003895{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01003896 struct drm_atomic_state *state = crtc_state->uapi.state;
Matt Roperc107acf2016-05-12 07:06:01 -07003897 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01003898 struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
Maarten Lankhorstec193642019-06-28 10:55:17 +02003899 const struct intel_crtc *crtc;
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003900 u32 pipe_width = 0, total_width_in_range = 0, width_before_pipe_in_range = 0;
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303901 enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
3902 u16 ddb_size;
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003903 u32 ddb_range_size;
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303904 u32 i;
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003905 u32 dbuf_slice_mask;
3906 u32 active_pipes;
3907 u32 offset;
3908 u32 slice_size;
3909 u32 total_slice_mask;
3910 u32 start, end;
Matt Roperc107acf2016-05-12 07:06:01 -07003911
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05303912 if (drm_WARN_ON(&dev_priv->drm, !state) || !crtc_state->hw.active) {
Damien Lespiaub9cec072014-11-04 17:06:43 +00003913 alloc->start = 0;
3914 alloc->end = 0;
Ville Syrjälä0b14d962019-08-21 20:30:33 +03003915 *num_active = hweight8(dev_priv->active_pipes);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003916 return;
3917 }
3918
Matt Ropera6d3460e2016-05-12 07:06:04 -07003919 if (intel_state->active_pipe_changes)
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003920 active_pipes = intel_state->active_pipes;
Matt Ropera6d3460e2016-05-12 07:06:04 -07003921 else
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003922 active_pipes = dev_priv->active_pipes;
Matt Ropera6d3460e2016-05-12 07:06:04 -07003923
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003924 *num_active = hweight8(active_pipes);
3925
3926 ddb_size = intel_get_ddb_size(dev_priv);
3927
3928 slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003929
Matt Roperc107acf2016-05-12 07:06:01 -07003930 /*
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303931 * If the state doesn't change the active CRTC's or there is no
3932 * modeset request, then there's no need to recalculate;
3933 * the existing pipe allocation limits should remain unchanged.
3934 * Note that we're safe from racing commits since any racing commit
3935 * that changes the active CRTC list or do modeset would need to
3936 * grab _all_ crtc locks, including the one we currently hold.
Matt Roperc107acf2016-05-12 07:06:01 -07003937 */
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303938 if (!intel_state->active_pipe_changes && !intel_state->modeset) {
Maarten Lankhorst512b5522016-11-08 13:55:34 +01003939 /*
3940 * alloc may be cleared by clear_intel_crtc_state,
3941 * copy from old state to be sure
3942 */
3943 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
Matt Ropera6d3460e2016-05-12 07:06:04 -07003944 return;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003945 }
Matt Ropera6d3460e2016-05-12 07:06:04 -07003946
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303947 /*
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003948 * Get allowed DBuf slices for correspondent pipe and platform.
3949 */
3950 dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, active_pipes);
3951
3952 DRM_DEBUG_KMS("DBuf slice mask %x pipe %c active pipes %x\n",
3953 dbuf_slice_mask,
3954 pipe_name(for_pipe), active_pipes);
3955
3956 /*
3957 * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
3958 * and slice size is 1024, the offset would be 1024
3959 */
3960 offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
3961 slice_size, ddb_size);
3962
3963 /*
3964 * Figure out total size of allowed DBuf slices, which is basically
3965 * a number of allowed slices for that pipe multiplied by slice size.
3966 * Inside of this
3967 * range ddb entries are still allocated in proportion to display width.
3968 */
3969 ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
3970
3971 /*
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303972 * Watermark/ddb requirement highly depends upon width of the
3973 * framebuffer, So instead of allocating DDB equally among pipes
3974 * distribute DDB based on resolution/width of the display.
3975 */
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003976 total_slice_mask = dbuf_slice_mask;
Maarten Lankhorstec193642019-06-28 10:55:17 +02003977 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
3978 const struct drm_display_mode *adjusted_mode =
Maarten Lankhorst1326a922019-10-31 12:26:02 +01003979 &crtc_state->hw.adjusted_mode;
Maarten Lankhorstec193642019-06-28 10:55:17 +02003980 enum pipe pipe = crtc->pipe;
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303981 int hdisplay, vdisplay;
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003982 u32 pipe_dbuf_slice_mask;
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05303983
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02003984 if (!crtc_state->hw.active)
3985 continue;
3986
3987 pipe_dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state,
3988 active_pipes);
3989
3990 /*
3991 * According to BSpec pipe can share one dbuf slice with another
3992 * pipes or pipe can use multiple dbufs, in both cases we
3993 * account for other pipes only if they have exactly same mask.
3994 * However we need to account how many slices we should enable
3995 * in total.
3996 */
3997 total_slice_mask |= pipe_dbuf_slice_mask;
3998
3999 /*
4000 * Do not account pipes using other slice sets
4001 * luckily as of current BSpec slice sets do not partially
4002 * intersect(pipes share either same one slice or same slice set
4003 * i.e no partial intersection), so it is enough to check for
4004 * equality for now.
4005 */
4006 if (dbuf_slice_mask != pipe_dbuf_slice_mask)
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05304007 continue;
4008
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05304009 drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004010
4011 total_width_in_range += hdisplay;
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05304012
4013 if (pipe < for_pipe)
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004014 width_before_pipe_in_range += hdisplay;
Mahesh Kumarcf1f6972018-08-01 20:41:13 +05304015 else if (pipe == for_pipe)
4016 pipe_width = hdisplay;
4017 }
4018
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004019 /*
4020 * FIXME: For now we always enable slice S1 as per
4021 * the Bspec display initialization sequence.
4022 */
4023 intel_state->enabled_dbuf_slices_mask = total_slice_mask | BIT(DBUF_S1);
4024
4025 start = ddb_range_size * width_before_pipe_in_range / total_width_in_range;
4026 end = ddb_range_size *
4027 (width_before_pipe_in_range + pipe_width) / total_width_in_range;
4028
4029 alloc->start = offset + start;
4030 alloc->end = offset + end;
4031
4032 DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe,
4033 alloc->start, alloc->end);
4034 DRM_DEBUG_KMS("Enabled ddb slices mask %x num supported %d\n",
4035 intel_state->enabled_dbuf_slices_mask,
4036 INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
Damien Lespiaub9cec072014-11-04 17:06:43 +00004037}
4038
Ville Syrjälädf331de2019-03-19 18:03:11 +02004039static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4040 int width, const struct drm_format_info *format,
4041 u64 modifier, unsigned int rotation,
4042 u32 plane_pixel_rate, struct skl_wm_params *wp,
4043 int color_plane);
Maarten Lankhorstec193642019-06-28 10:55:17 +02004044static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
Ville Syrjälädf331de2019-03-19 18:03:11 +02004045 int level,
Stanislav Lisovskiy7b994752020-04-09 18:47:18 +03004046 unsigned int latency,
Ville Syrjälädf331de2019-03-19 18:03:11 +02004047 const struct skl_wm_params *wp,
4048 const struct skl_wm_level *result_prev,
4049 struct skl_wm_level *result /* out */);
Damien Lespiaub9cec072014-11-04 17:06:43 +00004050
Ville Syrjälädf331de2019-03-19 18:03:11 +02004051static unsigned int
4052skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
4053 int num_active)
4054{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01004055 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Ville Syrjälädf331de2019-03-19 18:03:11 +02004056 int level, max_level = ilk_wm_max_level(dev_priv);
4057 struct skl_wm_level wm = {};
4058 int ret, min_ddb_alloc = 0;
4059 struct skl_wm_params wp;
4060
4061 ret = skl_compute_wm_params(crtc_state, 256,
4062 drm_format_info(DRM_FORMAT_ARGB8888),
4063 DRM_FORMAT_MOD_LINEAR,
4064 DRM_MODE_ROTATE_0,
4065 crtc_state->pixel_rate, &wp, 0);
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05304066 drm_WARN_ON(&dev_priv->drm, ret);
Ville Syrjälädf331de2019-03-19 18:03:11 +02004067
4068 for (level = 0; level <= max_level; level++) {
Stanislav Lisovskiy7b994752020-04-09 18:47:18 +03004069 unsigned int latency = dev_priv->wm.skl_latency[level];
4070
4071 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
Ville Syrjälädf331de2019-03-19 18:03:11 +02004072 if (wm.min_ddb_alloc == U16_MAX)
4073 break;
4074
4075 min_ddb_alloc = wm.min_ddb_alloc;
4076 }
4077
4078 return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
Damien Lespiaub9cec072014-11-04 17:06:43 +00004079}
4080
Mahesh Kumar37cde112018-04-26 19:55:17 +05304081static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
4082 struct skl_ddb_entry *entry, u32 reg)
Damien Lespiaua269c582014-11-04 17:06:49 +00004083{
Mahesh Kumar37cde112018-04-26 19:55:17 +05304084
Ville Syrjäläd7e449a2019-02-05 22:50:56 +02004085 entry->start = reg & DDB_ENTRY_MASK;
4086 entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
Mahesh Kumar37cde112018-04-26 19:55:17 +05304087
Damien Lespiau16160e32014-11-04 17:06:53 +00004088 if (entry->end)
4089 entry->end += 1;
Damien Lespiaua269c582014-11-04 17:06:49 +00004090}
4091
Mahesh Kumarddf34312018-04-09 09:11:03 +05304092static void
4093skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
4094 const enum pipe pipe,
4095 const enum plane_id plane_id,
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004096 struct skl_ddb_entry *ddb_y,
4097 struct skl_ddb_entry *ddb_uv)
Mahesh Kumarddf34312018-04-09 09:11:03 +05304098{
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004099 u32 val, val2;
4100 u32 fourcc = 0;
Mahesh Kumarddf34312018-04-09 09:11:03 +05304101
4102 /* Cursor doesn't support NV12/planar, so no extra calculation needed */
4103 if (plane_id == PLANE_CURSOR) {
4104 val = I915_READ(CUR_BUF_CFG(pipe));
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004105 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
Mahesh Kumarddf34312018-04-09 09:11:03 +05304106 return;
4107 }
4108
4109 val = I915_READ(PLANE_CTL(pipe, plane_id));
4110
4111 /* No DDB allocated for disabled planes */
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004112 if (val & PLANE_CTL_ENABLE)
4113 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4114 val & PLANE_CTL_ORDER_RGBX,
4115 val & PLANE_CTL_ALPHA_MASK);
Mahesh Kumarddf34312018-04-09 09:11:03 +05304116
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004117 if (INTEL_GEN(dev_priv) >= 11) {
4118 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4119 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4120 } else {
4121 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
Paulo Zanoni12a6c932018-07-31 17:46:14 -07004122 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
Mahesh Kumarddf34312018-04-09 09:11:03 +05304123
Ville Syrjäläd1d23d72019-09-13 22:31:54 +03004124 if (fourcc &&
4125 drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004126 swap(val, val2);
4127
4128 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4129 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
Mahesh Kumarddf34312018-04-09 09:11:03 +05304130 }
4131}
4132
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004133void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4134 struct skl_ddb_entry *ddb_y,
4135 struct skl_ddb_entry *ddb_uv)
4136{
4137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4138 enum intel_display_power_domain power_domain;
4139 enum pipe pipe = crtc->pipe;
Chris Wilson0e6e0be2019-01-14 14:21:24 +00004140 intel_wakeref_t wakeref;
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004141 enum plane_id plane_id;
4142
4143 power_domain = POWER_DOMAIN_PIPE(pipe);
Chris Wilson0e6e0be2019-01-14 14:21:24 +00004144 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4145 if (!wakeref)
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004146 return;
4147
4148 for_each_plane_id_on_crtc(crtc, plane_id)
4149 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4150 plane_id,
4151 &ddb_y[plane_id],
4152 &ddb_uv[plane_id]);
4153
Chris Wilson0e6e0be2019-01-14 14:21:24 +00004154 intel_display_power_put(dev_priv, power_domain, wakeref);
Ville Syrjäläff43bc32018-11-27 18:59:00 +02004155}
4156
Stanislav Lisovskiy072fcc32020-02-03 01:06:25 +02004157void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
Damien Lespiaua269c582014-11-04 17:06:49 +00004158{
Stanislav Lisovskiy0f0f9ae2020-02-03 01:06:29 +02004159 dev_priv->enabled_dbuf_slices_mask =
4160 intel_enabled_dbuf_slices_mask(dev_priv);
Damien Lespiaua269c582014-11-04 17:06:49 +00004161}
4162
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004163/*
4164 * Determines the downscale amount of a plane for the purposes of watermark calculations.
4165 * The bspec defines downscale amount as:
4166 *
4167 * """
4168 * Horizontal down scale amount = maximum[1, Horizontal source size /
4169 * Horizontal destination size]
4170 * Vertical down scale amount = maximum[1, Vertical source size /
4171 * Vertical destination size]
4172 * Total down scale amount = Horizontal down scale amount *
4173 * Vertical down scale amount
4174 * """
4175 *
4176 * Return value is provided in 16.16 fixed point form to retain fractional part.
4177 * Caller should take care of dividing & rounding off the value.
4178 */
Kumar, Mahesh7084b502017-05-17 17:28:23 +05304179static uint_fixed_16_16_t
Maarten Lankhorstec193642019-06-28 10:55:17 +02004180skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4181 const struct intel_plane_state *plane_state)
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004182{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004183 u32 src_w, src_h, dst_w, dst_h;
Kumar, Mahesh7084b502017-05-17 17:28:23 +05304184 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4185 uint_fixed_16_16_t downscale_h, downscale_w;
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004186
Maarten Lankhorstec193642019-06-28 10:55:17 +02004187 if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05304188 return u32_to_fixed16(0);
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004189
Maarten Lankhorst3a612762019-10-04 13:34:54 +02004190 /*
4191 * Src coordinates are already rotated by 270 degrees for
4192 * the 90/270 degree plane rotation cases (to match the
4193 * GTT mapping), hence no need to account for rotation here.
4194 *
4195 * n.b., src is 16.16 fixed point, dst is whole integer.
4196 */
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01004197 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4198 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4199 dst_w = drm_rect_width(&plane_state->uapi.dst);
4200 dst_h = drm_rect_height(&plane_state->uapi.dst);
Ville Syrjälä93aa2a12017-03-14 17:10:50 +02004201
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05304202 fp_w_ratio = div_fixed16(src_w, dst_w);
4203 fp_h_ratio = div_fixed16(src_h, dst_h);
4204 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4205 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004206
Kumar, Mahesh7084b502017-05-17 17:28:23 +05304207 return mul_fixed16(downscale_w, downscale_h);
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004208}
4209
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004210struct dbuf_slice_conf_entry {
4211 u8 active_pipes;
4212 u8 dbuf_mask[I915_MAX_PIPES];
4213};
4214
4215/*
4216 * Table taken from Bspec 12716
4217 * Pipes do have some preferred DBuf slice affinity,
4218 * plus there are some hardcoded requirements on how
4219 * those should be distributed for multipipe scenarios.
4220 * For more DBuf slices algorithm can get even more messy
4221 * and less readable, so decided to use a table almost
4222 * as is from BSpec itself - that way it is at least easier
4223 * to compare, change and check.
4224 */
Jani Nikulaf8226d02020-02-19 17:45:42 +02004225static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004226/* Autogenerated with igt/tools/intel_dbuf_map tool: */
4227{
4228 {
4229 .active_pipes = BIT(PIPE_A),
4230 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004231 [PIPE_A] = BIT(DBUF_S1),
4232 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004233 },
4234 {
4235 .active_pipes = BIT(PIPE_B),
4236 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004237 [PIPE_B] = BIT(DBUF_S1),
4238 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004239 },
4240 {
4241 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4242 .dbuf_mask = {
4243 [PIPE_A] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004244 [PIPE_B] = BIT(DBUF_S2),
4245 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004246 },
4247 {
4248 .active_pipes = BIT(PIPE_C),
4249 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004250 [PIPE_C] = BIT(DBUF_S2),
4251 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004252 },
4253 {
4254 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4255 .dbuf_mask = {
4256 [PIPE_A] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004257 [PIPE_C] = BIT(DBUF_S2),
4258 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004259 },
4260 {
4261 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4262 .dbuf_mask = {
4263 [PIPE_B] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004264 [PIPE_C] = BIT(DBUF_S2),
4265 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004266 },
4267 {
4268 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4269 .dbuf_mask = {
4270 [PIPE_A] = BIT(DBUF_S1),
4271 [PIPE_B] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004272 [PIPE_C] = BIT(DBUF_S2),
4273 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004274 },
Ville Syrjälä05e81552020-02-25 19:11:09 +02004275 {}
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004276};
4277
4278/*
4279 * Table taken from Bspec 49255
4280 * Pipes do have some preferred DBuf slice affinity,
4281 * plus there are some hardcoded requirements on how
4282 * those should be distributed for multipipe scenarios.
4283 * For more DBuf slices algorithm can get even more messy
4284 * and less readable, so decided to use a table almost
4285 * as is from BSpec itself - that way it is at least easier
4286 * to compare, change and check.
4287 */
Jani Nikulaf8226d02020-02-19 17:45:42 +02004288static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004289/* Autogenerated with igt/tools/intel_dbuf_map tool: */
4290{
4291 {
4292 .active_pipes = BIT(PIPE_A),
4293 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004294 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4295 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004296 },
4297 {
4298 .active_pipes = BIT(PIPE_B),
4299 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004300 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4301 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004302 },
4303 {
4304 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4305 .dbuf_mask = {
4306 [PIPE_A] = BIT(DBUF_S2),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004307 [PIPE_B] = BIT(DBUF_S1),
4308 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004309 },
4310 {
4311 .active_pipes = BIT(PIPE_C),
4312 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004313 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
4314 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004315 },
4316 {
4317 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4318 .dbuf_mask = {
4319 [PIPE_A] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004320 [PIPE_C] = BIT(DBUF_S2),
4321 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004322 },
4323 {
4324 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4325 .dbuf_mask = {
4326 [PIPE_B] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004327 [PIPE_C] = BIT(DBUF_S2),
4328 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004329 },
4330 {
4331 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4332 .dbuf_mask = {
4333 [PIPE_A] = BIT(DBUF_S1),
4334 [PIPE_B] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004335 [PIPE_C] = BIT(DBUF_S2),
4336 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004337 },
4338 {
4339 .active_pipes = BIT(PIPE_D),
4340 .dbuf_mask = {
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004341 [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
4342 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004343 },
4344 {
4345 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4346 .dbuf_mask = {
4347 [PIPE_A] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004348 [PIPE_D] = BIT(DBUF_S2),
4349 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004350 },
4351 {
4352 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4353 .dbuf_mask = {
4354 [PIPE_B] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004355 [PIPE_D] = BIT(DBUF_S2),
4356 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004357 },
4358 {
4359 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4360 .dbuf_mask = {
4361 [PIPE_A] = BIT(DBUF_S1),
4362 [PIPE_B] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004363 [PIPE_D] = BIT(DBUF_S2),
4364 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004365 },
4366 {
4367 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4368 .dbuf_mask = {
4369 [PIPE_C] = BIT(DBUF_S1),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004370 [PIPE_D] = BIT(DBUF_S2),
4371 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004372 },
4373 {
4374 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4375 .dbuf_mask = {
4376 [PIPE_A] = BIT(DBUF_S1),
4377 [PIPE_C] = BIT(DBUF_S2),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004378 [PIPE_D] = BIT(DBUF_S2),
4379 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004380 },
4381 {
4382 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4383 .dbuf_mask = {
4384 [PIPE_B] = BIT(DBUF_S1),
4385 [PIPE_C] = BIT(DBUF_S2),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004386 [PIPE_D] = BIT(DBUF_S2),
4387 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004388 },
4389 {
4390 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4391 .dbuf_mask = {
4392 [PIPE_A] = BIT(DBUF_S1),
4393 [PIPE_B] = BIT(DBUF_S1),
4394 [PIPE_C] = BIT(DBUF_S2),
Ville Syrjälä06812bd2020-02-25 19:11:08 +02004395 [PIPE_D] = BIT(DBUF_S2),
4396 },
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004397 },
Ville Syrjälä05e81552020-02-25 19:11:09 +02004398 {}
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004399};
4400
Ville Syrjälä05e81552020-02-25 19:11:09 +02004401static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4402 const struct dbuf_slice_conf_entry *dbuf_slices)
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004403{
4404 int i;
4405
Ville Syrjälä05e81552020-02-25 19:11:09 +02004406 for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004407 if (dbuf_slices[i].active_pipes == active_pipes)
4408 return dbuf_slices[i].dbuf_mask[pipe];
4409 }
4410 return 0;
4411}
4412
4413/*
4414 * This function finds an entry with same enabled pipe configuration and
4415 * returns correspondent DBuf slice mask as stated in BSpec for particular
4416 * platform.
4417 */
Ville Syrjälä05e81552020-02-25 19:11:09 +02004418static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004419{
4420 /*
4421 * FIXME: For ICL this is still a bit unclear as prev BSpec revision
4422 * required calculating "pipe ratio" in order to determine
4423 * if one or two slices can be used for single pipe configurations
4424 * as additional constraint to the existing table.
4425 * However based on recent info, it should be not "pipe ratio"
4426 * but rather ratio between pixel_rate and cdclk with additional
4427 * constants, so for now we are using only table until this is
4428 * clarified. Also this is the reason why crtc_state param is
4429 * still here - we will need it once those additional constraints
4430 * pop up.
4431 */
Ville Syrjälä05e81552020-02-25 19:11:09 +02004432 return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004433}
4434
Ville Syrjälä05e81552020-02-25 19:11:09 +02004435static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004436{
Ville Syrjälä05e81552020-02-25 19:11:09 +02004437 return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004438}
4439
4440static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
Ville Syrjälä05e81552020-02-25 19:11:09 +02004441 u8 active_pipes)
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004442{
4443 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4445 enum pipe pipe = crtc->pipe;
4446
4447 if (IS_GEN(dev_priv, 12))
Ville Syrjälä05e81552020-02-25 19:11:09 +02004448 return tgl_compute_dbuf_slices(pipe, active_pipes);
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004449 else if (IS_GEN(dev_priv, 11))
Ville Syrjälä05e81552020-02-25 19:11:09 +02004450 return icl_compute_dbuf_slices(pipe, active_pipes);
Stanislav Lisovskiyff2cd862020-02-03 01:06:30 +02004451 /*
4452 * For anything else just return one slice yet.
4453 * Should be extended for other platforms.
4454 */
4455 return BIT(DBUF_S1);
4456}
4457
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004458static u64
Maarten Lankhorstec193642019-06-28 10:55:17 +02004459skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4460 const struct intel_plane_state *plane_state,
Ville Syrjäläd1d23d72019-09-13 22:31:54 +03004461 int color_plane)
Damien Lespiaub9cec072014-11-04 17:06:43 +00004462{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01004463 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01004464 const struct drm_framebuffer *fb = plane_state->hw.fb;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004465 u32 data_rate;
4466 u32 width = 0, height = 0;
Kumar, Mahesh7084b502017-05-17 17:28:23 +05304467 uint_fixed_16_16_t down_scale_amount;
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004468 u64 rate;
Matt Ropera1de91e2016-05-12 07:05:57 -07004469
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01004470 if (!plane_state->uapi.visible)
Matt Ropera1de91e2016-05-12 07:05:57 -07004471 return 0;
Ville Syrjälä83054942016-11-18 21:53:00 +02004472
Ville Syrjäläd1d23d72019-09-13 22:31:54 +03004473 if (plane->id == PLANE_CURSOR)
Matt Ropera1de91e2016-05-12 07:05:57 -07004474 return 0;
Ville Syrjäläd1d23d72019-09-13 22:31:54 +03004475
4476 if (color_plane == 1 &&
Imre Deak4941f352019-12-21 14:05:43 +02004477 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
Matt Ropera1de91e2016-05-12 07:05:57 -07004478 return 0;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07004479
Ville Syrjäläfce5adf2017-03-31 21:00:55 +03004480 /*
4481 * Src coordinates are already rotated by 270 degrees for
4482 * the 90/270 degree plane rotation cases (to match the
4483 * GTT mapping), hence no need to account for rotation here.
4484 */
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01004485 width = drm_rect_width(&plane_state->uapi.src) >> 16;
4486 height = drm_rect_height(&plane_state->uapi.src) >> 16;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07004487
Mahesh Kumarb879d582018-04-09 09:11:01 +05304488 /* UV plane does 1/2 pixel sub-sampling */
Ville Syrjäläd1d23d72019-09-13 22:31:54 +03004489 if (color_plane == 1) {
Mahesh Kumarb879d582018-04-09 09:11:01 +05304490 width /= 2;
4491 height /= 2;
Chandra Konduru2cd601c2015-04-27 15:47:37 -07004492 }
4493
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004494 data_rate = width * height;
Mahesh Kumarb879d582018-04-09 09:11:01 +05304495
Maarten Lankhorstec193642019-06-28 10:55:17 +02004496 down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
Kumar, Mahesh8d19d7d2016-05-19 15:03:01 -07004497
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004498 rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4499
Ville Syrjäläd1d23d72019-09-13 22:31:54 +03004500 rate *= fb->format->cpp[color_plane];
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004501 return rate;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004502}
4503
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004504static u64
Maarten Lankhorstec193642019-06-28 10:55:17 +02004505skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004506 u64 *plane_data_rate,
4507 u64 *uv_plane_data_rate)
Damien Lespiaub9cec072014-11-04 17:06:43 +00004508{
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02004509 struct intel_plane *plane;
4510 const struct intel_plane_state *plane_state;
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004511 u64 total_data_rate = 0;
Matt Ropera6d3460e2016-05-12 07:06:04 -07004512
Matt Ropera1de91e2016-05-12 07:05:57 -07004513 /* Calculate and cache data rate for each plane */
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02004514 intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
4515 enum plane_id plane_id = plane->id;
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004516 u64 rate;
Matt Roper024c9042015-09-24 15:53:11 -07004517
Mahesh Kumarb879d582018-04-09 09:11:01 +05304518 /* packed/y */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004519 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02004520 plane_data_rate[plane_id] = rate;
Maarten Lankhorst1e6ee542016-10-26 15:41:32 +02004521 total_data_rate += rate;
Matt Roper9c74d822016-05-12 07:05:58 -07004522
Mahesh Kumarb879d582018-04-09 09:11:01 +05304523 /* uv-plane */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004524 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
Mahesh Kumarb879d582018-04-09 09:11:01 +05304525 uv_plane_data_rate[plane_id] = rate;
Maarten Lankhorst1e6ee542016-10-26 15:41:32 +02004526 total_data_rate += rate;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004527 }
4528
4529 return total_data_rate;
4530}
4531
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004532static u64
Maarten Lankhorstec193642019-06-28 10:55:17 +02004533icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004534 u64 *plane_data_rate)
4535{
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02004536 struct intel_plane *plane;
4537 const struct intel_plane_state *plane_state;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004538 u64 total_data_rate = 0;
4539
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004540 /* Calculate and cache data rate for each plane */
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02004541 intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
4542 enum plane_id plane_id = plane->id;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004543 u64 rate;
4544
Maarten Lankhorstc47b7dd2019-09-20 13:42:20 +02004545 if (!plane_state->planar_linked_plane) {
Maarten Lankhorstec193642019-06-28 10:55:17 +02004546 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004547 plane_data_rate[plane_id] = rate;
4548 total_data_rate += rate;
4549 } else {
4550 enum plane_id y_plane_id;
4551
4552 /*
4553 * The slave plane might not iterate in
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02004554 * intel_atomic_crtc_state_for_each_plane_state(),
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004555 * and needs the master plane state which may be
4556 * NULL if we try get_new_plane_state(), so we
4557 * always calculate from the master.
4558 */
Maarten Lankhorstc47b7dd2019-09-20 13:42:20 +02004559 if (plane_state->planar_slave)
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004560 continue;
4561
4562 /* Y plane rate is calculated on the slave */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004563 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
Maarten Lankhorstc47b7dd2019-09-20 13:42:20 +02004564 y_plane_id = plane_state->planar_linked_plane->id;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004565 plane_data_rate[y_plane_id] = rate;
4566 total_data_rate += rate;
4567
Maarten Lankhorstec193642019-06-28 10:55:17 +02004568 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004569 plane_data_rate[plane_id] = rate;
4570 total_data_rate += rate;
4571 }
4572 }
4573
4574 return total_data_rate;
4575}
4576
Matt Roperc107acf2016-05-12 07:06:01 -07004577static int
Stanislav Lisovskiy072fcc32020-02-03 01:06:25 +02004578skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
Damien Lespiaub9cec072014-11-04 17:06:43 +00004579{
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02004580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Maarten Lankhorstec193642019-06-28 10:55:17 +02004582 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004583 u16 alloc_size, start = 0;
4584 u16 total[I915_MAX_PLANES] = {};
4585 u16 uv_total[I915_MAX_PLANES] = {};
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004586 u64 total_data_rate;
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02004587 enum plane_id plane_id;
Matt Roperc107acf2016-05-12 07:06:01 -07004588 int num_active;
Maarten Lankhorst24719e92018-10-22 12:20:00 +02004589 u64 plane_data_rate[I915_MAX_PLANES] = {};
4590 u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
Ville Syrjälä0aded172019-02-05 17:50:53 +02004591 u32 blocks;
Matt Roperd8e87492018-12-11 09:31:07 -08004592 int level;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004593
Paulo Zanoni5a920b82016-10-04 14:37:32 -03004594 /* Clear the partitioning for disabled planes. */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004595 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4596 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
Paulo Zanoni5a920b82016-10-04 14:37:32 -03004597
Maarten Lankhorst1326a922019-10-31 12:26:02 +01004598 if (!crtc_state->hw.active) {
Lyudece0ba282016-09-15 10:46:35 -04004599 alloc->start = alloc->end = 0;
Matt Roperc107acf2016-05-12 07:06:01 -07004600 return 0;
4601 }
4602
Lucas De Marchi323b0a82019-04-04 16:04:25 -07004603 if (INTEL_GEN(dev_priv) >= 11)
4604 total_data_rate =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004605 icl_get_total_relative_data_rate(crtc_state,
Lucas De Marchi323b0a82019-04-04 16:04:25 -07004606 plane_data_rate);
4607 else
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004608 total_data_rate =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004609 skl_get_total_relative_data_rate(crtc_state,
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004610 plane_data_rate,
4611 uv_plane_data_rate);
Lucas De Marchi323b0a82019-04-04 16:04:25 -07004612
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004613
Maarten Lankhorstec193642019-06-28 10:55:17 +02004614 skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
Stanislav Lisovskiy072fcc32020-02-03 01:06:25 +02004615 alloc, &num_active);
Damien Lespiau34bb56a2014-11-04 17:07:01 +00004616 alloc_size = skl_ddb_entry_size(alloc);
Kumar, Mahesh336031e2017-05-17 17:28:25 +05304617 if (alloc_size == 0)
Matt Roperc107acf2016-05-12 07:06:01 -07004618 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004619
Matt Roperd8e87492018-12-11 09:31:07 -08004620 /* Allocate fixed number of blocks for cursor. */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004621 total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
Matt Roperd8e87492018-12-11 09:31:07 -08004622 alloc_size -= total[PLANE_CURSOR];
Maarten Lankhorstec193642019-06-28 10:55:17 +02004623 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
Matt Roperd8e87492018-12-11 09:31:07 -08004624 alloc->end - total[PLANE_CURSOR];
Maarten Lankhorstec193642019-06-28 10:55:17 +02004625 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
Maarten Lankhorst49845a72016-10-26 15:41:34 +02004626
Matt Ropera1de91e2016-05-12 07:05:57 -07004627 if (total_data_rate == 0)
Matt Roperc107acf2016-05-12 07:06:01 -07004628 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004629
Matt Roperd8e87492018-12-11 09:31:07 -08004630 /*
4631 * Find the highest watermark level for which we can satisfy the block
4632 * requirement of active planes.
4633 */
4634 for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
Matt Roper25db2ea2018-12-12 11:17:20 -08004635 blocks = 0;
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02004636 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004637 const struct skl_plane_wm *wm =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004638 &crtc_state->wm.skl.optimal.planes[plane_id];
Ville Syrjälä10a7e072019-03-12 22:58:40 +02004639
4640 if (plane_id == PLANE_CURSOR) {
Vandita Kulkarni4ba48702019-12-16 13:36:19 +05304641 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05304642 drm_WARN_ON(&dev_priv->drm,
4643 wm->wm[level].min_ddb_alloc != U16_MAX);
Ville Syrjälä10a7e072019-03-12 22:58:40 +02004644 blocks = U32_MAX;
4645 break;
4646 }
4647 continue;
4648 }
4649
Ville Syrjälä961d95e2018-12-21 19:14:32 +02004650 blocks += wm->wm[level].min_ddb_alloc;
4651 blocks += wm->uv_wm[level].min_ddb_alloc;
Matt Roperd8e87492018-12-11 09:31:07 -08004652 }
4653
Ville Syrjälä3cf963c2019-03-12 22:58:36 +02004654 if (blocks <= alloc_size) {
Matt Roperd8e87492018-12-11 09:31:07 -08004655 alloc_size -= blocks;
4656 break;
4657 }
4658 }
4659
4660 if (level < 0) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03004661 drm_dbg_kms(&dev_priv->drm,
4662 "Requested display configuration exceeds system DDB limitations");
4663 drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
4664 blocks, alloc_size);
Matt Roperd8e87492018-12-11 09:31:07 -08004665 return -EINVAL;
4666 }
4667
4668 /*
4669 * Grant each plane the blocks it requires at the highest achievable
4670 * watermark level, plus an extra share of the leftover blocks
4671 * proportional to its relative data rate.
4672 */
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02004673 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004674 const struct skl_plane_wm *wm =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004675 &crtc_state->wm.skl.optimal.planes[plane_id];
Matt Roperd8e87492018-12-11 09:31:07 -08004676 u64 rate;
4677 u16 extra;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004678
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02004679 if (plane_id == PLANE_CURSOR)
Maarten Lankhorst49845a72016-10-26 15:41:34 +02004680 continue;
4681
Damien Lespiaub9cec072014-11-04 17:06:43 +00004682 /*
Matt Roperd8e87492018-12-11 09:31:07 -08004683 * We've accounted for all active planes; remaining planes are
4684 * all disabled.
Damien Lespiaub9cec072014-11-04 17:06:43 +00004685 */
Matt Roperd8e87492018-12-11 09:31:07 -08004686 if (total_data_rate == 0)
4687 break;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004688
Matt Roperd8e87492018-12-11 09:31:07 -08004689 rate = plane_data_rate[plane_id];
4690 extra = min_t(u16, alloc_size,
4691 DIV64_U64_ROUND_UP(alloc_size * rate,
4692 total_data_rate));
Ville Syrjälä961d95e2018-12-21 19:14:32 +02004693 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
Matt Roperd8e87492018-12-11 09:31:07 -08004694 alloc_size -= extra;
4695 total_data_rate -= rate;
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07004696
Matt Roperd8e87492018-12-11 09:31:07 -08004697 if (total_data_rate == 0)
4698 break;
Chandra Konduru2cd601c2015-04-27 15:47:37 -07004699
Matt Roperd8e87492018-12-11 09:31:07 -08004700 rate = uv_plane_data_rate[plane_id];
4701 extra = min_t(u16, alloc_size,
4702 DIV64_U64_ROUND_UP(alloc_size * rate,
4703 total_data_rate));
Ville Syrjälä961d95e2018-12-21 19:14:32 +02004704 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
Matt Roperd8e87492018-12-11 09:31:07 -08004705 alloc_size -= extra;
4706 total_data_rate -= rate;
4707 }
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05304708 drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
Matt Roperd8e87492018-12-11 09:31:07 -08004709
4710 /* Set the actual DDB start/end points for each plane */
4711 start = alloc->start;
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02004712 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004713 struct skl_ddb_entry *plane_alloc =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004714 &crtc_state->wm.skl.plane_ddb_y[plane_id];
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004715 struct skl_ddb_entry *uv_plane_alloc =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004716 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
Matt Roperd8e87492018-12-11 09:31:07 -08004717
4718 if (plane_id == PLANE_CURSOR)
4719 continue;
4720
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004721 /* Gen11+ uses a separate plane for UV watermarks */
Pankaj Bharadiya48a1b8d2020-01-15 09:14:53 +05304722 drm_WARN_ON(&dev_priv->drm,
4723 INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02004724
Matt Roperd8e87492018-12-11 09:31:07 -08004725 /* Leave disabled planes at (0,0) */
4726 if (total[plane_id]) {
4727 plane_alloc->start = start;
4728 start += total[plane_id];
4729 plane_alloc->end = start;
Matt Roperc107acf2016-05-12 07:06:01 -07004730 }
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07004731
Matt Roperd8e87492018-12-11 09:31:07 -08004732 if (uv_total[plane_id]) {
4733 uv_plane_alloc->start = start;
4734 start += uv_total[plane_id];
4735 uv_plane_alloc->end = start;
4736 }
4737 }
4738
4739 /*
4740 * When we calculated watermark values we didn't know how high
4741 * of a level we'd actually be able to hit, so we just marked
4742 * all levels as "enabled." Go back now and disable the ones
4743 * that aren't actually possible.
4744 */
4745 for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02004746 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004747 struct skl_plane_wm *wm =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004748 &crtc_state->wm.skl.optimal.planes[plane_id];
Ville Syrjäläa301cb02019-03-12 22:58:41 +02004749
4750 /*
4751 * We only disable the watermarks for each plane if
4752 * they exceed the ddb allocation of said plane. This
4753 * is done so that we don't end up touching cursor
4754 * watermarks needlessly when some other plane reduces
4755 * our max possible watermark level.
4756 *
4757 * Bspec has this to say about the PLANE_WM enable bit:
4758 * "All the watermarks at this level for all enabled
4759 * planes must be enabled before the level will be used."
4760 * So this is actually safe to do.
4761 */
4762 if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
4763 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
4764 memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
Ville Syrjälä290248c2019-02-13 18:54:24 +02004765
Ville Syrjäläc384afe2019-02-28 19:36:39 +02004766 /*
Bob Paauwe39564ae2019-04-12 11:09:20 -07004767 * Wa_1408961008:icl, ehl
Ville Syrjäläc384afe2019-02-28 19:36:39 +02004768 * Underruns with WM1+ disabled
4769 */
Bob Paauwe39564ae2019-04-12 11:09:20 -07004770 if (IS_GEN(dev_priv, 11) &&
Ville Syrjälä290248c2019-02-13 18:54:24 +02004771 level == 1 && wm->wm[0].plane_en) {
4772 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
Ville Syrjäläc384afe2019-02-28 19:36:39 +02004773 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
4774 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
Ville Syrjälä290248c2019-02-13 18:54:24 +02004775 }
Matt Roperd8e87492018-12-11 09:31:07 -08004776 }
4777 }
4778
4779 /*
4780 * Go back and disable the transition watermark if it turns out we
4781 * don't have enough DDB blocks for it.
4782 */
Ville Syrjälä2a67054b2020-02-25 19:11:06 +02004783 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004784 struct skl_plane_wm *wm =
Maarten Lankhorstec193642019-06-28 10:55:17 +02004785 &crtc_state->wm.skl.optimal.planes[plane_id];
Ville Syrjälä5e6037c2019-03-12 22:58:42 +02004786
Ville Syrjäläb19c9bc2018-12-21 19:14:31 +02004787 if (wm->trans_wm.plane_res_b >= total[plane_id])
Matt Roperd8e87492018-12-11 09:31:07 -08004788 memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
Damien Lespiaub9cec072014-11-04 17:06:43 +00004789 }
4790
Matt Roperc107acf2016-05-12 07:06:01 -07004791 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00004792}
4793
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004794/*
4795 * The max latency should be 257 (max the punit can code is 255 and we add 2us
Ville Syrjäläac484962016-01-20 21:05:26 +02004796 * for the read latency) and cpp should always be <= 8, so that
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004797 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4798 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4799*/
Paulo Zanoni6c64dd32017-08-11 16:38:25 -07004800static uint_fixed_16_16_t
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004801skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
4802 u8 cpp, u32 latency, u32 dbuf_block_size)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004803{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004804 u32 wm_intermediate_val;
Mahesh Kumarb95320b2016-12-01 21:19:37 +05304805 uint_fixed_16_16_t ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004806
4807 if (latency == 0)
Mahesh Kumarb95320b2016-12-01 21:19:37 +05304808 return FP_16_16_MAX;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004809
Mahesh Kumarb95320b2016-12-01 21:19:37 +05304810 wm_intermediate_val = latency * pixel_rate * cpp;
Mahesh Kumardf8ee192018-01-30 11:49:11 -02004811 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
Paulo Zanoni6c64dd32017-08-11 16:38:25 -07004812
4813 if (INTEL_GEN(dev_priv) >= 10)
4814 ret = add_fixed16_u32(ret, 1);
4815
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004816 return ret;
4817}
4818
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004819static uint_fixed_16_16_t
4820skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
4821 uint_fixed_16_16_t plane_blocks_per_line)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004822{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004823 u32 wm_intermediate_val;
Mahesh Kumarb95320b2016-12-01 21:19:37 +05304824 uint_fixed_16_16_t ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004825
4826 if (latency == 0)
Mahesh Kumarb95320b2016-12-01 21:19:37 +05304827 return FP_16_16_MAX;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004828
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004829 wm_intermediate_val = latency * pixel_rate;
Mahesh Kumarb95320b2016-12-01 21:19:37 +05304830 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4831 pipe_htotal * 1000);
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05304832 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004833 return ret;
4834}
4835
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304836static uint_fixed_16_16_t
Maarten Lankhorstec193642019-06-28 10:55:17 +02004837intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304838{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004839 u32 pixel_rate;
4840 u32 crtc_htotal;
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304841 uint_fixed_16_16_t linetime_us;
4842
Maarten Lankhorst1326a922019-10-31 12:26:02 +01004843 if (!crtc_state->hw.active)
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05304844 return u32_to_fixed16(0);
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304845
Maarten Lankhorstec193642019-06-28 10:55:17 +02004846 pixel_rate = crtc_state->pixel_rate;
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304847
4848 if (WARN_ON(pixel_rate == 0))
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05304849 return u32_to_fixed16(0);
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304850
Maarten Lankhorst1326a922019-10-31 12:26:02 +01004851 crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05304852 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
Kumar, Maheshd555cb52017-05-17 17:28:29 +05304853
4854 return linetime_us;
4855}
4856
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004857static u32
Maarten Lankhorstec193642019-06-28 10:55:17 +02004858skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
4859 const struct intel_plane_state *plane_state)
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004860{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004861 u64 adjusted_pixel_rate;
Kumar, Mahesh7084b502017-05-17 17:28:23 +05304862 uint_fixed_16_16_t downscale_amount;
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004863
4864 /* Shouldn't reach here on disabled planes... */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004865 if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004866 return 0;
4867
4868 /*
4869 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4870 * with additional adjustments for plane-specific scaling.
4871 */
Maarten Lankhorstec193642019-06-28 10:55:17 +02004872 adjusted_pixel_rate = crtc_state->pixel_rate;
4873 downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004874
Kumar, Mahesh7084b502017-05-17 17:28:23 +05304875 return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4876 downscale_amount);
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07004877}
4878
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304879static int
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004880skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4881 int width, const struct drm_format_info *format,
4882 u64 modifier, unsigned int rotation,
4883 u32 plane_pixel_rate, struct skl_wm_params *wp,
4884 int color_plane)
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304885{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01004886 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004887 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Jani Nikula5ce9a6492019-01-18 14:01:20 +02004888 u32 interm_pbpl;
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304889
Juha-Pekka Heikkiladf7d4152019-03-04 17:26:31 +05304890 /* only planar format has two planes */
Imre Deak4941f352019-12-21 14:05:43 +02004891 if (color_plane == 1 &&
4892 !intel_format_info_is_yuv_semiplanar(format, modifier)) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03004893 drm_dbg_kms(&dev_priv->drm,
4894 "Non planar format have single plane\n");
Mahesh Kumar942aa2d2018-04-09 09:11:04 +05304895 return -EINVAL;
4896 }
4897
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004898 wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
4899 modifier == I915_FORMAT_MOD_Yf_TILED ||
4900 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4901 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4902 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
4903 wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4904 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
Imre Deak4941f352019-12-21 14:05:43 +02004905 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304906
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004907 wp->width = width;
Ville Syrjälä45bee432018-11-14 23:07:28 +02004908 if (color_plane == 1 && wp->is_planar)
Mahesh Kumar942aa2d2018-04-09 09:11:04 +05304909 wp->width /= 2;
4910
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004911 wp->cpp = format->cpp[color_plane];
4912 wp->plane_pixel_rate = plane_pixel_rate;
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304913
Mahesh Kumardf8ee192018-01-30 11:49:11 -02004914 if (INTEL_GEN(dev_priv) >= 11 &&
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004915 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
Mahesh Kumardf8ee192018-01-30 11:49:11 -02004916 wp->dbuf_block_size = 256;
4917 else
4918 wp->dbuf_block_size = 512;
4919
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004920 if (drm_rotation_90_or_270(rotation)) {
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304921 switch (wp->cpp) {
4922 case 1:
4923 wp->y_min_scanlines = 16;
4924 break;
4925 case 2:
4926 wp->y_min_scanlines = 8;
4927 break;
4928 case 4:
4929 wp->y_min_scanlines = 4;
4930 break;
4931 default:
4932 MISSING_CASE(wp->cpp);
4933 return -EINVAL;
4934 }
4935 } else {
4936 wp->y_min_scanlines = 4;
4937 }
4938
Ville Syrjälä60e983f2018-12-21 19:14:33 +02004939 if (skl_needs_memory_bw_wa(dev_priv))
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304940 wp->y_min_scanlines *= 2;
4941
4942 wp->plane_bytes_per_line = wp->width * wp->cpp;
4943 if (wp->y_tiled) {
4944 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
Mahesh Kumardf8ee192018-01-30 11:49:11 -02004945 wp->y_min_scanlines,
4946 wp->dbuf_block_size);
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304947
4948 if (INTEL_GEN(dev_priv) >= 10)
4949 interm_pbpl++;
4950
4951 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4952 wp->y_min_scanlines);
Lucas De Marchicf819ef2018-12-12 10:10:43 -08004953 } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) {
Mahesh Kumardf8ee192018-01-30 11:49:11 -02004954 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4955 wp->dbuf_block_size);
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304956 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4957 } else {
Mahesh Kumardf8ee192018-01-30 11:49:11 -02004958 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4959 wp->dbuf_block_size) + 1;
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304960 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4961 }
4962
4963 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
4964 wp->plane_blocks_per_line);
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004965
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304966 wp->linetime_us = fixed16_to_u32_round_up(
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004967 intel_get_linetime_us(crtc_state));
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05304968
4969 return 0;
4970}
4971
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004972static int
4973skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
4974 const struct intel_plane_state *plane_state,
4975 struct skl_wm_params *wp, int color_plane)
4976{
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01004977 const struct drm_framebuffer *fb = plane_state->hw.fb;
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004978 int width;
4979
Maarten Lankhorst3a612762019-10-04 13:34:54 +02004980 /*
4981 * Src coordinates are already rotated by 270 degrees for
4982 * the 90/270 degree plane rotation cases (to match the
4983 * GTT mapping), hence no need to account for rotation here.
4984 */
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01004985 width = drm_rect_width(&plane_state->uapi.src) >> 16;
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004986
4987 return skl_compute_wm_params(crtc_state, width,
4988 fb->format, fb->modifier,
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01004989 plane_state->hw.rotation,
Ville Syrjäläc92558a2019-03-12 22:58:38 +02004990 skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
4991 wp, color_plane);
4992}
4993
Ville Syrjäläb52c2732018-12-21 19:14:28 +02004994static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
4995{
4996 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4997 return true;
4998
4999 /* The number of lines are ignored for the level 0 watermark. */
5000 return level > 0;
5001}
5002
Maarten Lankhorstec193642019-06-28 10:55:17 +02005003static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
Matt Roperd8e87492018-12-11 09:31:07 -08005004 int level,
Stanislav Lisovskiy7b994752020-04-09 18:47:18 +03005005 unsigned int latency,
Matt Roperd8e87492018-12-11 09:31:07 -08005006 const struct skl_wm_params *wp,
5007 const struct skl_wm_level *result_prev,
5008 struct skl_wm_level *result /* out */)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005009{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01005010 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Mahesh Kumarb95320b2016-12-01 21:19:37 +05305011 uint_fixed_16_16_t method1, method2;
Mahesh Kumarb95320b2016-12-01 21:19:37 +05305012 uint_fixed_16_16_t selected_result;
Ville Syrjälä961d95e2018-12-21 19:14:32 +02005013 u32 res_blocks, res_lines, min_ddb_alloc = 0;
Ville Syrjäläce110ec2018-11-14 23:07:21 +02005014
Ville Syrjälä0aded172019-02-05 17:50:53 +02005015 if (latency == 0) {
5016 /* reject it */
5017 result->min_ddb_alloc = U16_MAX;
Ville Syrjälä692927f2018-12-21 19:14:29 +02005018 return;
Ville Syrjälä0aded172019-02-05 17:50:53 +02005019 }
Ville Syrjälä692927f2018-12-21 19:14:29 +02005020
Ville Syrjälä25312ef2019-05-03 20:38:05 +03005021 /*
5022 * WaIncreaseLatencyIPCEnabled: kbl,cfl
5023 * Display WA #1141: kbl,cfl
5024 */
Ville Syrjälä5a7d2022019-05-03 20:38:06 +03005025 if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) ||
Rodrigo Vivi82525c12017-06-08 08:50:00 -07005026 dev_priv->ipc_enabled)
Mahesh Kumar4b7b2332016-12-01 21:19:35 +05305027 latency += 4;
5028
Ville Syrjälä60e983f2018-12-21 19:14:33 +02005029 if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
Paulo Zanoniee3d5322016-10-11 15:25:38 -03005030 latency += 15;
5031
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305032 method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
Mahesh Kumardf8ee192018-01-30 11:49:11 -02005033 wp->cpp, latency, wp->dbuf_block_size);
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305034 method2 = skl_wm_method2(wp->plane_pixel_rate,
Maarten Lankhorst1326a922019-10-31 12:26:02 +01005035 crtc_state->hw.adjusted_mode.crtc_htotal,
Paulo Zanoni1186fa82016-09-22 18:00:31 -03005036 latency,
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305037 wp->plane_blocks_per_line);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005038
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305039 if (wp->y_tiled) {
5040 selected_result = max_fixed16(method2, wp->y_tile_minimum);
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00005041 } else {
Maarten Lankhorst1326a922019-10-31 12:26:02 +01005042 if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
Mahesh Kumardf8ee192018-01-30 11:49:11 -02005043 wp->dbuf_block_size < 1) &&
Paulo Zanoni077b5822018-10-04 16:15:57 -07005044 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
Paulo Zanonif1db3ea2016-09-22 18:00:34 -03005045 selected_result = method2;
Paulo Zanoni077b5822018-10-04 16:15:57 -07005046 } else if (latency >= wp->linetime_us) {
Lucas De Marchicf819ef2018-12-12 10:10:43 -08005047 if (IS_GEN(dev_priv, 9) &&
Paulo Zanoni077b5822018-10-04 16:15:57 -07005048 !IS_GEMINILAKE(dev_priv))
5049 selected_result = min_fixed16(method1, method2);
5050 else
5051 selected_result = method2;
5052 } else {
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00005053 selected_result = method1;
Paulo Zanoni077b5822018-10-04 16:15:57 -07005054 }
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00005055 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005056
Kumar, Mahesheac2cb82017-07-05 20:01:46 +05305057 res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
Kumar, Maheshd273ecc2017-05-17 17:28:22 +05305058 res_lines = div_round_up_fixed16(selected_result,
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305059 wp->plane_blocks_per_line);
Damien Lespiaue6d66172014-11-04 17:06:55 +00005060
Paulo Zanonia5b79d32018-11-13 17:24:32 -08005061 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
5062 /* Display WA #1125: skl,bxt,kbl */
5063 if (level == 0 && wp->rc_surface)
5064 res_blocks +=
5065 fixed16_to_u32_round_up(wp->y_tile_minimum);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -07005066
Paulo Zanonia5b79d32018-11-13 17:24:32 -08005067 /* Display WA #1126: skl,bxt,kbl */
5068 if (level >= 1 && level <= 7) {
5069 if (wp->y_tiled) {
5070 res_blocks +=
5071 fixed16_to_u32_round_up(wp->y_tile_minimum);
5072 res_lines += wp->y_min_scanlines;
5073 } else {
5074 res_blocks++;
5075 }
5076
5077 /*
5078 * Make sure result blocks for higher latency levels are
5079 * atleast as high as level below the current level.
5080 * Assumption in DDB algorithm optimization for special
5081 * cases. Also covers Display WA #1125 for RC.
5082 */
5083 if (result_prev->plane_res_b > res_blocks)
5084 res_blocks = result_prev->plane_res_b;
Paulo Zanoni75676ed2016-09-22 18:00:33 -03005085 }
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00005086 }
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00005087
Ville Syrjälä961d95e2018-12-21 19:14:32 +02005088 if (INTEL_GEN(dev_priv) >= 11) {
5089 if (wp->y_tiled) {
5090 int extra_lines;
5091
5092 if (res_lines % wp->y_min_scanlines == 0)
5093 extra_lines = wp->y_min_scanlines;
5094 else
5095 extra_lines = wp->y_min_scanlines * 2 -
5096 res_lines % wp->y_min_scanlines;
5097
5098 min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
5099 wp->plane_blocks_per_line);
5100 } else {
5101 min_ddb_alloc = res_blocks +
5102 DIV_ROUND_UP(res_blocks, 10);
5103 }
5104 }
5105
Ville Syrjäläb52c2732018-12-21 19:14:28 +02005106 if (!skl_wm_has_lines(dev_priv, level))
5107 res_lines = 0;
5108
Ville Syrjälä0aded172019-02-05 17:50:53 +02005109 if (res_lines > 31) {
5110 /* reject it */
5111 result->min_ddb_alloc = U16_MAX;
Matt Roperd8e87492018-12-11 09:31:07 -08005112 return;
Ville Syrjälä0aded172019-02-05 17:50:53 +02005113 }
Matt Roperd8e87492018-12-11 09:31:07 -08005114
5115 /*
5116 * If res_lines is valid, assume we can use this watermark level
5117 * for now. We'll come back and disable it after we calculate the
5118 * DDB allocation if it turns out we don't actually have enough
5119 * blocks to satisfy it.
5120 */
Mahesh Kumar62027b72018-04-09 09:11:05 +05305121 result->plane_res_b = res_blocks;
5122 result->plane_res_l = res_lines;
Ville Syrjälä961d95e2018-12-21 19:14:32 +02005123 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
5124 result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
Mahesh Kumar62027b72018-04-09 09:11:05 +05305125 result->plane_en = true;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005126}
5127
Matt Roperd8e87492018-12-11 09:31:07 -08005128static void
Maarten Lankhorstec193642019-06-28 10:55:17 +02005129skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305130 const struct skl_wm_params *wm_params,
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005131 struct skl_wm_level *levels)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005132{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01005133 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Kumar, Maheshd2f5e362017-05-17 17:28:28 +05305134 int level, max_level = ilk_wm_max_level(dev_priv);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005135 struct skl_wm_level *result_prev = &levels[0];
Lyudea62163e2016-10-04 14:28:20 -04005136
Kumar, Maheshd2f5e362017-05-17 17:28:28 +05305137 for (level = 0; level <= max_level; level++) {
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005138 struct skl_wm_level *result = &levels[level];
Stanislav Lisovskiy7b994752020-04-09 18:47:18 +03005139 unsigned int latency = dev_priv->wm.skl_latency[level];
Kumar, Maheshd2f5e362017-05-17 17:28:28 +05305140
Stanislav Lisovskiy7b994752020-04-09 18:47:18 +03005141 skl_compute_plane_wm(crtc_state, level, latency,
5142 wm_params, result_prev, result);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005143
5144 result_prev = result;
Kumar, Maheshd2f5e362017-05-17 17:28:28 +05305145 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005146}
5147
Maarten Lankhorstec193642019-06-28 10:55:17 +02005148static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
Ville Syrjälä6a3c910b2018-11-14 23:07:23 +02005149 const struct skl_wm_params *wp,
Matt Roperd8e87492018-12-11 09:31:07 -08005150 struct skl_plane_wm *wm)
Damien Lespiau407b50f2014-11-04 17:06:57 +00005151{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01005152 struct drm_device *dev = crtc_state->uapi.crtc->dev;
Kumar, Maheshca476672017-08-17 19:15:24 +05305153 const struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläc834d032020-02-28 22:35:52 +02005154 u16 trans_min, trans_amount, trans_y_tile_min;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02005155 u16 wm0_sel_res_b, trans_offset_b, res_blocks;
Damien Lespiau9414f562014-11-04 17:06:58 +00005156
Kumar, Maheshca476672017-08-17 19:15:24 +05305157 /* Transition WM don't make any sense if ipc is disabled */
5158 if (!dev_priv->ipc_enabled)
Ville Syrjälä14a43062018-11-14 23:07:22 +02005159 return;
Kumar, Maheshca476672017-08-17 19:15:24 +05305160
Ville Syrjäläa7f1e8e2020-02-28 22:35:51 +02005161 /*
5162 * WaDisableTWM:skl,kbl,cfl,bxt
5163 * Transition WM are not recommended by HW team for GEN9
5164 */
5165 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
5166 return;
5167
Paulo Zanoni91961a82018-10-04 16:15:56 -07005168 if (INTEL_GEN(dev_priv) >= 11)
Kumar, Maheshca476672017-08-17 19:15:24 +05305169 trans_min = 4;
Ville Syrjäläc834d032020-02-28 22:35:52 +02005170 else
5171 trans_min = 14;
5172
5173 /* Display WA #1140: glk,cnl */
5174 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
5175 trans_amount = 0;
5176 else
5177 trans_amount = 10; /* This is configurable amount */
Kumar, Maheshca476672017-08-17 19:15:24 +05305178
5179 trans_offset_b = trans_min + trans_amount;
5180
Paulo Zanonicbacc792018-10-04 16:15:58 -07005181 /*
5182 * The spec asks for Selected Result Blocks for wm0 (the real value),
5183 * not Result Blocks (the integer value). Pay attention to the capital
5184 * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
5185 * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
5186 * and since we later will have to get the ceiling of the sum in the
5187 * transition watermarks calculation, we can just pretend Selected
5188 * Result Blocks is Result Blocks minus 1 and it should work for the
5189 * current platforms.
5190 */
Ville Syrjälä6a3c910b2018-11-14 23:07:23 +02005191 wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
Paulo Zanonicbacc792018-10-04 16:15:58 -07005192
Kumar, Maheshca476672017-08-17 19:15:24 +05305193 if (wp->y_tiled) {
Jani Nikula5ce9a6492019-01-18 14:01:20 +02005194 trans_y_tile_min =
5195 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
Paulo Zanonicbacc792018-10-04 16:15:58 -07005196 res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
Kumar, Maheshca476672017-08-17 19:15:24 +05305197 trans_offset_b;
5198 } else {
Paulo Zanonicbacc792018-10-04 16:15:58 -07005199 res_blocks = wm0_sel_res_b + trans_offset_b;
Kumar, Maheshca476672017-08-17 19:15:24 +05305200
5201 /* WA BUG:1938466 add one block for non y-tile planes */
5202 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
5203 res_blocks += 1;
Kumar, Maheshca476672017-08-17 19:15:24 +05305204 }
5205
Matt Roperd8e87492018-12-11 09:31:07 -08005206 /*
5207 * Just assume we can enable the transition watermark. After
5208 * computing the DDB we'll come back and disable it if that
5209 * assumption turns out to be false.
5210 */
5211 wm->trans_wm.plane_res_b = res_blocks + 1;
5212 wm->trans_wm.plane_en = true;
Damien Lespiau407b50f2014-11-04 17:06:57 +00005213}
5214
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005215static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005216 const struct intel_plane_state *plane_state,
5217 enum plane_id plane_id, int color_plane)
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005218{
Ville Syrjälä83158472018-11-27 18:57:26 +02005219 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005220 struct skl_wm_params wm_params;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005221 int ret;
5222
Ville Syrjälä51de9c62018-11-14 23:07:25 +02005223 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005224 &wm_params, color_plane);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005225 if (ret)
5226 return ret;
5227
Ville Syrjälä67155a62019-03-12 22:58:37 +02005228 skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
Matt Roperd8e87492018-12-11 09:31:07 -08005229 skl_compute_transition_wm(crtc_state, &wm_params, wm);
Ville Syrjälä83158472018-11-27 18:57:26 +02005230
5231 return 0;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005232}
5233
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005234static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005235 const struct intel_plane_state *plane_state,
5236 enum plane_id plane_id)
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005237{
Ville Syrjälä83158472018-11-27 18:57:26 +02005238 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5239 struct skl_wm_params wm_params;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005240 int ret;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005241
Ville Syrjälä83158472018-11-27 18:57:26 +02005242 wm->is_planar = true;
5243
5244 /* uv plane watermarks must also be validated for NV12/Planar */
Ville Syrjälä51de9c62018-11-14 23:07:25 +02005245 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005246 &wm_params, 1);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005247 if (ret)
5248 return ret;
5249
Ville Syrjälä67155a62019-03-12 22:58:37 +02005250 skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
Ville Syrjälä83158472018-11-27 18:57:26 +02005251
5252 return 0;
5253}
5254
Ville Syrjälä96cb7cd2019-03-12 22:58:43 +02005255static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005256 const struct intel_plane_state *plane_state)
5257{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01005258 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01005259 const struct drm_framebuffer *fb = plane_state->hw.fb;
Ville Syrjälä83158472018-11-27 18:57:26 +02005260 enum plane_id plane_id = plane->id;
5261 int ret;
5262
5263 if (!intel_wm_plane_visible(crtc_state, plane_state))
5264 return 0;
5265
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005266 ret = skl_build_plane_wm_single(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005267 plane_id, 0);
5268 if (ret)
5269 return ret;
5270
5271 if (fb->format->is_yuv && fb->format->num_planes > 1) {
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005272 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005273 plane_id);
5274 if (ret)
5275 return ret;
5276 }
5277
5278 return 0;
5279}
5280
Ville Syrjälä96cb7cd2019-03-12 22:58:43 +02005281static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005282 const struct intel_plane_state *plane_state)
5283{
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01005284 enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
Ville Syrjälä83158472018-11-27 18:57:26 +02005285 int ret;
5286
5287 /* Watermarks calculated in master */
Maarten Lankhorstc47b7dd2019-09-20 13:42:20 +02005288 if (plane_state->planar_slave)
Ville Syrjälä83158472018-11-27 18:57:26 +02005289 return 0;
5290
Maarten Lankhorstc47b7dd2019-09-20 13:42:20 +02005291 if (plane_state->planar_linked_plane) {
Maarten Lankhorst7b3cb172019-10-31 12:26:07 +01005292 const struct drm_framebuffer *fb = plane_state->hw.fb;
Maarten Lankhorstc47b7dd2019-09-20 13:42:20 +02005293 enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
Ville Syrjälä83158472018-11-27 18:57:26 +02005294
5295 WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
5296 WARN_ON(!fb->format->is_yuv ||
5297 fb->format->num_planes == 1);
5298
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005299 ret = skl_build_plane_wm_single(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005300 y_plane_id, 0);
5301 if (ret)
5302 return ret;
5303
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005304 ret = skl_build_plane_wm_single(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005305 plane_id, 1);
5306 if (ret)
5307 return ret;
5308 } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005309 ret = skl_build_plane_wm_single(crtc_state, plane_state,
Ville Syrjälä83158472018-11-27 18:57:26 +02005310 plane_id, 0);
5311 if (ret)
5312 return ret;
5313 }
5314
5315 return 0;
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005316}
5317
Maarten Lankhorstec193642019-06-28 10:55:17 +02005318static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005319{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01005320 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
Maarten Lankhorstec193642019-06-28 10:55:17 +02005321 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02005322 struct intel_plane *plane;
5323 const struct intel_plane_state *plane_state;
Matt Roper55994c22016-05-12 07:06:08 -07005324 int ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005325
Lyudea62163e2016-10-04 14:28:20 -04005326 /*
5327 * We'll only calculate watermarks for planes that are actually
5328 * enabled, so make sure all other planes are set as disabled.
5329 */
5330 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
5331
Maarten Lankhorstaf9fbfa2019-10-04 13:34:53 +02005332 intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
5333 crtc_state) {
Kumar, Mahesheb2fdcd2017-05-17 17:28:27 +05305334
Ville Syrjälä83158472018-11-27 18:57:26 +02005335 if (INTEL_GEN(dev_priv) >= 11)
Maarten Lankhorstec193642019-06-28 10:55:17 +02005336 ret = icl_build_plane_wm(crtc_state, plane_state);
Maarten Lankhorstb048a002018-10-18 13:51:30 +02005337 else
Maarten Lankhorstec193642019-06-28 10:55:17 +02005338 ret = skl_build_plane_wm(crtc_state, plane_state);
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05305339 if (ret)
5340 return ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005341 }
Mahesh Kumar942aa2d2018-04-09 09:11:04 +05305342
Matt Roper55994c22016-05-12 07:06:08 -07005343 return 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00005344}
5345
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005346static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5347 i915_reg_t reg,
Damien Lespiau16160e32014-11-04 17:06:53 +00005348 const struct skl_ddb_entry *entry)
5349{
5350 if (entry->end)
Jani Nikula9b6320a2020-01-23 16:00:04 +02005351 intel_de_write_fw(dev_priv, reg,
5352 (entry->end - 1) << 16 | entry->start);
Damien Lespiau16160e32014-11-04 17:06:53 +00005353 else
Jani Nikula9b6320a2020-01-23 16:00:04 +02005354 intel_de_write_fw(dev_priv, reg, 0);
Damien Lespiau16160e32014-11-04 17:06:53 +00005355}
5356
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005357static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5358 i915_reg_t reg,
5359 const struct skl_wm_level *level)
5360{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02005361 u32 val = 0;
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005362
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02005363 if (level->plane_en)
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005364 val |= PLANE_WM_EN;
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02005365 if (level->ignore_lines)
5366 val |= PLANE_WM_IGNORE_LINES;
5367 val |= level->plane_res_b;
5368 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005369
Jani Nikula9b6320a2020-01-23 16:00:04 +02005370 intel_de_write_fw(dev_priv, reg, val);
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005371}
5372
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005373void skl_write_plane_wm(struct intel_plane *plane,
5374 const struct intel_crtc_state *crtc_state)
Lyude62e0fb82016-08-22 12:50:08 -04005375{
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005376 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01005377 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005378 enum plane_id plane_id = plane->id;
5379 enum pipe pipe = plane->pipe;
5380 const struct skl_plane_wm *wm =
5381 &crtc_state->wm.skl.optimal.planes[plane_id];
5382 const struct skl_ddb_entry *ddb_y =
5383 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5384 const struct skl_ddb_entry *ddb_uv =
5385 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
Lyude62e0fb82016-08-22 12:50:08 -04005386
5387 for (level = 0; level <= max_level; level++) {
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02005388 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005389 &wm->wm[level]);
Lyude62e0fb82016-08-22 12:50:08 -04005390 }
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02005391 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005392 &wm->trans_wm);
Lyude27082492016-08-24 07:48:10 +02005393
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005394 if (INTEL_GEN(dev_priv) >= 11) {
Mahesh Kumar234059d2018-01-30 11:49:13 -02005395 skl_ddb_entry_write(dev_priv,
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005396 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5397 return;
Mahesh Kumarb879d582018-04-09 09:11:01 +05305398 }
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005399
5400 if (wm->is_planar)
5401 swap(ddb_y, ddb_uv);
5402
5403 skl_ddb_entry_write(dev_priv,
5404 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5405 skl_ddb_entry_write(dev_priv,
5406 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
Lyude62e0fb82016-08-22 12:50:08 -04005407}
5408
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005409void skl_write_cursor_wm(struct intel_plane *plane,
5410 const struct intel_crtc_state *crtc_state)
Lyude62e0fb82016-08-22 12:50:08 -04005411{
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005412 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01005413 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005414 enum plane_id plane_id = plane->id;
5415 enum pipe pipe = plane->pipe;
5416 const struct skl_plane_wm *wm =
5417 &crtc_state->wm.skl.optimal.planes[plane_id];
5418 const struct skl_ddb_entry *ddb =
5419 &crtc_state->wm.skl.plane_ddb_y[plane_id];
Lyude62e0fb82016-08-22 12:50:08 -04005420
5421 for (level = 0; level <= max_level; level++) {
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005422 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5423 &wm->wm[level]);
Lyude62e0fb82016-08-22 12:50:08 -04005424 }
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005425 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
Lyude27082492016-08-24 07:48:10 +02005426
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005427 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
Lyude62e0fb82016-08-22 12:50:08 -04005428}
5429
cpaul@redhat.com45ece232016-10-14 17:31:56 -04005430bool skl_wm_level_equals(const struct skl_wm_level *l1,
5431 const struct skl_wm_level *l2)
5432{
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005433 return l1->plane_en == l2->plane_en &&
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02005434 l1->ignore_lines == l2->ignore_lines &&
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005435 l1->plane_res_l == l2->plane_res_l &&
5436 l1->plane_res_b == l2->plane_res_b;
5437}
cpaul@redhat.com45ece232016-10-14 17:31:56 -04005438
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005439static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5440 const struct skl_plane_wm *wm1,
5441 const struct skl_plane_wm *wm2)
5442{
5443 int level, max_level = ilk_wm_max_level(dev_priv);
cpaul@redhat.com45ece232016-10-14 17:31:56 -04005444
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005445 for (level = 0; level <= max_level; level++) {
Ville Syrjäläe7f54e62020-02-28 22:35:49 +02005446 /*
5447 * We don't check uv_wm as the hardware doesn't actually
5448 * use it. It only gets used for calculating the required
5449 * ddb allocation.
5450 */
5451 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005452 return false;
5453 }
5454
5455 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
cpaul@redhat.com45ece232016-10-14 17:31:56 -04005456}
5457
Jani Nikula81b55ef2020-04-20 17:04:38 +03005458static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5459 const struct skl_ddb_entry *b)
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00005460{
Lyude27082492016-08-24 07:48:10 +02005461 return a->start < b->end && b->start < a->end;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00005462}
5463
Ville Syrjälä53cc68802018-11-01 17:05:59 +02005464bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
Jani Nikula696173b2019-04-05 14:00:15 +03005465 const struct skl_ddb_entry *entries,
Ville Syrjälä53cc68802018-11-01 17:05:59 +02005466 int num_entries, int ignore_idx)
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00005467{
Ville Syrjälä53cc68802018-11-01 17:05:59 +02005468 int i;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00005469
Ville Syrjälä53cc68802018-11-01 17:05:59 +02005470 for (i = 0; i < num_entries; i++) {
5471 if (i != ignore_idx &&
5472 skl_ddb_entries_overlap(ddb, &entries[i]))
Lyude27082492016-08-24 07:48:10 +02005473 return true;
Mika Kahola2b685042017-10-10 13:17:03 +03005474 }
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00005475
Lyude27082492016-08-24 07:48:10 +02005476 return false;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00005477}
5478
Jani Nikulabb7791b2016-10-04 12:29:17 +03005479static int
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005480skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
5481 struct intel_crtc_state *new_crtc_state)
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005482{
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01005483 struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
5484 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5486 struct intel_plane *plane;
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005487
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005488 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5489 struct intel_plane_state *plane_state;
5490 enum plane_id plane_id = plane->id;
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005491
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005492 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5493 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5494 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5495 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005496 continue;
5497
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005498 plane_state = intel_atomic_get_plane_state(state, plane);
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005499 if (IS_ERR(plane_state))
5500 return PTR_ERR(plane_state);
Maarten Lankhorst1ab554b2018-10-22 15:51:52 +02005501
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005502 new_crtc_state->update_planes |= BIT(plane_id);
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005503 }
5504
5505 return 0;
5506}
5507
5508static int
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005509skl_compute_ddb(struct intel_atomic_state *state)
Matt Roper98d39492016-05-12 07:06:03 -07005510{
Stanislav Lisovskiy072fcc32020-02-03 01:06:25 +02005511 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005512 struct intel_crtc_state *old_crtc_state;
5513 struct intel_crtc_state *new_crtc_state;
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305514 struct intel_crtc *crtc;
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305515 int ret, i;
Matt Roper98d39492016-05-12 07:06:03 -07005516
Stanislav Lisovskiy0f0f9ae2020-02-03 01:06:29 +02005517 state->enabled_dbuf_slices_mask = dev_priv->enabled_dbuf_slices_mask;
Paulo Zanoni5a920b82016-10-04 14:37:32 -03005518
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005519 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005520 new_crtc_state, i) {
Stanislav Lisovskiy072fcc32020-02-03 01:06:25 +02005521 ret = skl_allocate_pipe_ddb(new_crtc_state);
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005522 if (ret)
5523 return ret;
5524
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005525 ret = skl_ddb_add_affected_planes(old_crtc_state,
5526 new_crtc_state);
Rodrigo Vivi9a30a262017-06-13 10:52:30 -07005527 if (ret)
5528 return ret;
Matt Roper98d39492016-05-12 07:06:03 -07005529 }
5530
5531 return 0;
5532}
5533
Ville Syrjäläab98e942019-02-08 22:05:27 +02005534static char enast(bool enable)
5535{
5536 return enable ? '*' : ' ';
5537}
5538
Matt Roper2722efb2016-08-17 15:55:55 -04005539static void
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005540skl_print_wm_changes(struct intel_atomic_state *state)
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005541{
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005542 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5543 const struct intel_crtc_state *old_crtc_state;
5544 const struct intel_crtc_state *new_crtc_state;
5545 struct intel_plane *plane;
5546 struct intel_crtc *crtc;
Maarten Lankhorst75704982016-11-01 12:04:10 +01005547 int i;
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005548
Jani Nikulabdbf43d2019-10-28 12:38:15 +02005549 if (!drm_debug_enabled(DRM_UT_KMS))
Ville Syrjäläab98e942019-02-08 22:05:27 +02005550 return;
5551
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005552 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5553 new_crtc_state, i) {
Ville Syrjäläab98e942019-02-08 22:05:27 +02005554 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
5555
5556 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
5557 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
5558
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005559 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5560 enum plane_id plane_id = plane->id;
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005561 const struct skl_ddb_entry *old, *new;
5562
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005563 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5564 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005565
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005566 if (skl_ddb_entry_equal(old, new))
5567 continue;
5568
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005569 drm_dbg_kms(&dev_priv->drm,
5570 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
5571 plane->base.base.id, plane->base.name,
5572 old->start, old->end, new->start, new->end,
5573 skl_ddb_entry_size(old), skl_ddb_entry_size(new));
Ville Syrjäläab98e942019-02-08 22:05:27 +02005574 }
5575
5576 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5577 enum plane_id plane_id = plane->id;
5578 const struct skl_plane_wm *old_wm, *new_wm;
5579
5580 old_wm = &old_pipe_wm->planes[plane_id];
5581 new_wm = &new_pipe_wm->planes[plane_id];
5582
5583 if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
5584 continue;
5585
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005586 drm_dbg_kms(&dev_priv->drm,
5587 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
5588 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
5589 plane->base.base.id, plane->base.name,
5590 enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
5591 enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
5592 enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
5593 enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
5594 enast(old_wm->trans_wm.plane_en),
5595 enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
5596 enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
5597 enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
5598 enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5599 enast(new_wm->trans_wm.plane_en));
Ville Syrjäläab98e942019-02-08 22:05:27 +02005600
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005601 drm_dbg_kms(&dev_priv->drm,
5602 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02005603 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005604 plane->base.base.id, plane->base.name,
5605 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
5606 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
5607 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
5608 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
5609 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
5610 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
5611 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
5612 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
5613 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02005614
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005615 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
5616 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
5617 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
5618 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
5619 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
5620 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
5621 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
5622 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5623 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
Ville Syrjäläab98e942019-02-08 22:05:27 +02005624
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005625 drm_dbg_kms(&dev_priv->drm,
5626 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5627 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5628 plane->base.base.id, plane->base.name,
5629 old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
5630 old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
5631 old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
5632 old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
5633 old_wm->trans_wm.plane_res_b,
5634 new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
5635 new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
5636 new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
5637 new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5638 new_wm->trans_wm.plane_res_b);
Ville Syrjäläab98e942019-02-08 22:05:27 +02005639
Wambui Karugaf8d18d52020-01-07 18:13:30 +03005640 drm_dbg_kms(&dev_priv->drm,
5641 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5642 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5643 plane->base.base.id, plane->base.name,
5644 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
5645 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
5646 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
5647 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
5648 old_wm->trans_wm.min_ddb_alloc,
5649 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
5650 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
5651 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
5652 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5653 new_wm->trans_wm.min_ddb_alloc);
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005654 }
5655 }
5656}
5657
Ville Syrjälä49e0ed32019-10-11 23:09:43 +03005658static int intel_add_all_pipes(struct intel_atomic_state *state)
5659{
5660 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5661 struct intel_crtc *crtc;
5662
5663 for_each_intel_crtc(&dev_priv->drm, crtc) {
5664 struct intel_crtc_state *crtc_state;
5665
5666 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5667 if (IS_ERR(crtc_state))
5668 return PTR_ERR(crtc_state);
5669 }
5670
5671 return 0;
5672}
5673
Matt Roper98d39492016-05-12 07:06:03 -07005674static int
Ville Syrjäläd7a14582019-10-11 23:09:42 +03005675skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
Matt Roper98d39492016-05-12 07:06:03 -07005676{
Ville Syrjälä49e0ed32019-10-11 23:09:43 +03005677 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
Ville Syrjäläd7a14582019-10-11 23:09:42 +03005678 int ret;
Matt Roper98d39492016-05-12 07:06:03 -07005679
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305680 /*
5681 * If this is our first atomic update following hardware readout,
5682 * we can't trust the DDB that the BIOS programmed for us. Let's
5683 * pretend that all pipes switched active status so that we'll
5684 * ensure a full DDB recompute.
5685 */
5686 if (dev_priv->wm.distrust_bios_wm) {
Ville Syrjälä49e0ed32019-10-11 23:09:43 +03005687 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005688 state->base.acquire_ctx);
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305689 if (ret)
5690 return ret;
5691
Ville Syrjälä8d9875b2019-10-11 23:09:45 +03005692 state->active_pipe_changes = INTEL_INFO(dev_priv)->pipe_mask;
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305693
5694 /*
Ville Syrjäläd06a79d2019-08-21 20:30:29 +03005695 * We usually only initialize state->active_pipes if we
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305696 * we're doing a modeset; make sure this field is always
5697 * initialized during the sanitization process that happens
5698 * on the first commit too.
5699 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005700 if (!state->modeset)
Ville Syrjäläd06a79d2019-08-21 20:30:29 +03005701 state->active_pipes = dev_priv->active_pipes;
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305702 }
5703
5704 /*
5705 * If the modeset changes which CRTC's are active, we need to
5706 * recompute the DDB allocation for *all* active pipes, even
5707 * those that weren't otherwise being modified in any way by this
5708 * atomic commit. Due to the shrinking of the per-pipe allocations
5709 * when new active CRTC's are added, it's possible for a pipe that
5710 * we were already using and aren't changing at all here to suddenly
5711 * become invalid if its DDB needs exceeds its new allocation.
5712 *
5713 * Note that if we wind up doing a full DDB recompute, we can't let
5714 * any other display updates race with this transaction, so we need
5715 * to grab the lock on *all* CRTC's.
5716 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005717 if (state->active_pipe_changes || state->modeset) {
Ville Syrjälä49e0ed32019-10-11 23:09:43 +03005718 ret = intel_add_all_pipes(state);
5719 if (ret)
5720 return ret;
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305721 }
5722
5723 return 0;
5724}
5725
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005726/*
5727 * To make sure the cursor watermark registers are always consistent
5728 * with our computed state the following scenario needs special
5729 * treatment:
5730 *
5731 * 1. enable cursor
5732 * 2. move cursor entirely offscreen
5733 * 3. disable cursor
5734 *
5735 * Step 2. does call .disable_plane() but does not zero the watermarks
5736 * (since we consider an offscreen cursor still active for the purposes
5737 * of watermarks). Step 3. would not normally call .disable_plane()
5738 * because the actual plane visibility isn't changing, and we don't
5739 * deallocate the cursor ddb until the pipe gets disabled. So we must
5740 * force step 3. to call .disable_plane() to update the watermark
5741 * registers properly.
5742 *
5743 * Other planes do not suffer from this issues as their watermarks are
5744 * calculated based on the actual plane visibility. The only time this
5745 * can trigger for the other planes is during the initial readout as the
5746 * default value of the watermarks registers is not zero.
5747 */
5748static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
5749 struct intel_crtc *crtc)
5750{
5751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5752 const struct intel_crtc_state *old_crtc_state =
5753 intel_atomic_get_old_crtc_state(state, crtc);
5754 struct intel_crtc_state *new_crtc_state =
5755 intel_atomic_get_new_crtc_state(state, crtc);
5756 struct intel_plane *plane;
5757
5758 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5759 struct intel_plane_state *plane_state;
5760 enum plane_id plane_id = plane->id;
5761
5762 /*
5763 * Force a full wm update for every plane on modeset.
5764 * Required because the reset value of the wm registers
5765 * is non-zero, whereas we want all disabled planes to
5766 * have zero watermarks. So if we turn off the relevant
5767 * power well the hardware state will go out of sync
5768 * with the software state.
5769 */
Maarten Lankhorst2225f3c2019-10-31 12:26:03 +01005770 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005771 skl_plane_wm_equals(dev_priv,
5772 &old_crtc_state->wm.skl.optimal.planes[plane_id],
5773 &new_crtc_state->wm.skl.optimal.planes[plane_id]))
5774 continue;
5775
5776 plane_state = intel_atomic_get_plane_state(state, plane);
5777 if (IS_ERR(plane_state))
5778 return PTR_ERR(plane_state);
5779
5780 new_crtc_state->update_planes |= BIT(plane_id);
5781 }
5782
5783 return 0;
5784}
5785
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305786static int
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005787skl_compute_wm(struct intel_atomic_state *state)
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305788{
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005789 struct intel_crtc *crtc;
Ville Syrjälä8cac9fd2019-03-12 22:58:44 +02005790 struct intel_crtc_state *new_crtc_state;
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005791 struct intel_crtc_state *old_crtc_state;
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305792 int ret, i;
5793
Ville Syrjäläd7a14582019-10-11 23:09:42 +03005794 ret = skl_ddb_add_affected_pipes(state);
5795 if (ret)
Mahesh Kumare1f96a62018-04-09 09:11:08 +05305796 return ret;
5797
Matt Roper734fa012016-05-12 15:11:40 -07005798 /*
5799 * Calculate WM's for all pipes that are part of this transaction.
Matt Roperd8e87492018-12-11 09:31:07 -08005800 * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
Ville Syrjäläf119a5e2020-01-20 19:47:13 +02005801 * weren't otherwise being modified if pipe allocations had to change.
Matt Roper734fa012016-05-12 15:11:40 -07005802 */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005803 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
Ville Syrjälä8cac9fd2019-03-12 22:58:44 +02005804 new_crtc_state, i) {
5805 ret = skl_build_pipe_wm(new_crtc_state);
Ville Syrjäläff43bc32018-11-27 18:59:00 +02005806 if (ret)
5807 return ret;
Matt Roper734fa012016-05-12 15:11:40 -07005808 }
5809
Matt Roperd8e87492018-12-11 09:31:07 -08005810 ret = skl_compute_ddb(state);
5811 if (ret)
5812 return ret;
5813
Ville Syrjälä23baedd2020-02-28 22:35:50 +02005814 /*
5815 * skl_compute_ddb() will have adjusted the final watermarks
5816 * based on how much ddb is available. Now we can actually
5817 * check if the final watermarks changed.
5818 */
5819 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5820 new_crtc_state, i) {
5821 ret = skl_wm_add_affected_planes(state, crtc);
5822 if (ret)
5823 return ret;
5824 }
5825
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005826 skl_print_wm_changes(state);
cpaul@redhat.com413fc532016-10-14 17:31:54 -04005827
Matt Roper98d39492016-05-12 07:06:03 -07005828 return 0;
5829}
5830
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005831static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
Ville Syrjäläd8905652016-01-14 14:53:35 +02005832 struct intel_wm_config *config)
5833{
5834 struct intel_crtc *crtc;
5835
5836 /* Compute the currently _active_ config */
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005837 for_each_intel_crtc(&dev_priv->drm, crtc) {
Ville Syrjäläd8905652016-01-14 14:53:35 +02005838 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5839
5840 if (!wm->pipe_enabled)
5841 continue;
5842
5843 config->sprites_enabled |= wm->sprites_enabled;
5844 config->sprites_scaled |= wm->sprites_scaled;
5845 config->num_pipes_active++;
5846 }
5847}
5848
Matt Ropered4a6a72016-02-23 17:20:13 -08005849static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03005850{
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07005851 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
Imre Deak820c1982013-12-17 14:46:36 +02005852 struct ilk_wm_maximums max;
Ville Syrjäläd8905652016-01-14 14:53:35 +02005853 struct intel_wm_config config = {};
Imre Deak820c1982013-12-17 14:46:36 +02005854 struct ilk_wm_values results = {};
Ville Syrjälä77c122b2013-08-06 22:24:04 +03005855 enum intel_ddb_partitioning partitioning;
Matt Roper261a27d2015-10-08 15:28:25 -07005856
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005857 ilk_compute_wm_config(dev_priv, &config);
Ville Syrjäläd8905652016-01-14 14:53:35 +02005858
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005859 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
5860 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
Ville Syrjälä0362c782013-10-09 19:17:57 +03005861
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03005862 /* 5/6 split only in single pipe config on IVB+ */
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00005863 if (INTEL_GEN(dev_priv) >= 7 &&
Ville Syrjäläd8905652016-01-14 14:53:35 +02005864 config.num_pipes_active == 1 && config.sprites_enabled) {
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005865 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
5866 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03005867
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005868 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
Paulo Zanoni861f3382013-05-31 10:19:21 -03005869 } else {
Ville Syrjälä198a1e92013-10-09 19:17:58 +03005870 best_lp_wm = &lp_wm_1_2;
Paulo Zanoni861f3382013-05-31 10:19:21 -03005871 }
5872
Ville Syrjälä198a1e92013-10-09 19:17:58 +03005873 partitioning = (best_lp_wm == &lp_wm_1_2) ?
Ville Syrjälä77c122b2013-08-06 22:24:04 +03005874 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
Paulo Zanoni861f3382013-05-31 10:19:21 -03005875
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005876 ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
Ville Syrjälä609cede2013-10-09 19:18:03 +03005877
Imre Deak820c1982013-12-17 14:46:36 +02005878 ilk_write_wm_values(dev_priv, &results);
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03005879}
5880
Maarten Lankhorstccf010f2016-11-08 13:55:32 +01005881static void ilk_initial_watermarks(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02005882 struct intel_crtc *crtc)
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07005883{
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02005884 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5885 const struct intel_crtc_state *crtc_state =
5886 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07005887
Matt Ropered4a6a72016-02-23 17:20:13 -08005888 mutex_lock(&dev_priv->wm.wm_mutex);
Ville Syrjälä88016a92019-07-01 19:05:45 +03005889 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
Matt Ropered4a6a72016-02-23 17:20:13 -08005890 ilk_program_watermarks(dev_priv);
5891 mutex_unlock(&dev_priv->wm.wm_mutex);
5892}
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07005893
Maarten Lankhorstccf010f2016-11-08 13:55:32 +01005894static void ilk_optimize_watermarks(struct intel_atomic_state *state,
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02005895 struct intel_crtc *crtc)
Matt Ropered4a6a72016-02-23 17:20:13 -08005896{
Ville Syrjälä7a8fdb1f2019-11-18 18:44:26 +02005897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5898 const struct intel_crtc_state *crtc_state =
5899 intel_atomic_get_new_crtc_state(state, crtc);
Ville Syrjälä88016a92019-07-01 19:05:45 +03005900
5901 if (!crtc_state->wm.need_postvbl_update)
5902 return;
Matt Ropered4a6a72016-02-23 17:20:13 -08005903
5904 mutex_lock(&dev_priv->wm.wm_mutex);
Ville Syrjälä88016a92019-07-01 19:05:45 +03005905 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
5906 ilk_program_watermarks(dev_priv);
Matt Ropered4a6a72016-02-23 17:20:13 -08005907 mutex_unlock(&dev_priv->wm.wm_mutex);
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07005908}
5909
Jani Nikula81b55ef2020-04-20 17:04:38 +03005910static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
Pradeep Bhat30789992014-11-04 17:06:45 +00005911{
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005912 level->plane_en = val & PLANE_WM_EN;
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02005913 level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005914 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5915 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5916 PLANE_WM_LINES_MASK;
Pradeep Bhat30789992014-11-04 17:06:45 +00005917}
5918
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005919void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
cpaul@redhat.combf9d99a2016-10-14 17:31:55 -04005920 struct skl_pipe_wm *out)
Pradeep Bhat30789992014-11-04 17:06:45 +00005921{
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5923 enum pipe pipe = crtc->pipe;
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02005924 int level, max_level;
5925 enum plane_id plane_id;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02005926 u32 val;
Pradeep Bhat30789992014-11-04 17:06:45 +00005927
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01005928 max_level = ilk_wm_max_level(dev_priv);
Pradeep Bhat30789992014-11-04 17:06:45 +00005929
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005930 for_each_plane_id_on_crtc(crtc, plane_id) {
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02005931 struct skl_plane_wm *wm = &out->planes[plane_id];
Pradeep Bhat30789992014-11-04 17:06:45 +00005932
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005933 for (level = 0; level <= max_level; level++) {
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02005934 if (plane_id != PLANE_CURSOR)
5935 val = I915_READ(PLANE_WM(pipe, plane_id, level));
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005936 else
5937 val = I915_READ(CUR_WM(pipe, level));
5938
5939 skl_wm_level_from_reg_val(val, &wm->wm[level]);
5940 }
5941
Ville Syrjäläd5cdfdf52016-11-22 18:01:58 +02005942 if (plane_id != PLANE_CURSOR)
5943 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
cpaul@redhat.comd8c0faf2016-10-18 16:09:49 -02005944 else
5945 val = I915_READ(CUR_WM_TRANS(pipe));
5946
5947 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5948 }
Pradeep Bhat30789992014-11-04 17:06:45 +00005949
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005950 if (!crtc->active)
Pradeep Bhat30789992014-11-04 17:06:45 +00005951 return;
Pradeep Bhat30789992014-11-04 17:06:45 +00005952}
5953
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005954void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
Pradeep Bhat30789992014-11-04 17:06:45 +00005955{
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005956 struct intel_crtc *crtc;
Maarten Lankhorstec193642019-06-28 10:55:17 +02005957 struct intel_crtc_state *crtc_state;
Pradeep Bhat30789992014-11-04 17:06:45 +00005958
Stanislav Lisovskiy072fcc32020-02-03 01:06:25 +02005959 skl_ddb_get_hw_state(dev_priv);
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005960 for_each_intel_crtc(&dev_priv->drm, crtc) {
Maarten Lankhorstec193642019-06-28 10:55:17 +02005961 crtc_state = to_intel_crtc_state(crtc->base.state);
cpaul@redhat.combf9d99a2016-10-14 17:31:55 -04005962
Maarten Lankhorstec193642019-06-28 10:55:17 +02005963 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
cpaul@redhat.combf9d99a2016-10-14 17:31:55 -04005964 }
Matt Ropera1de91e2016-05-12 07:05:57 -07005965
Ville Syrjäläd06a79d2019-08-21 20:30:29 +03005966 if (dev_priv->active_pipes) {
Matt Roper279e99d2016-05-12 07:06:02 -07005967 /* Fully recompute DDB on first atomic commit */
5968 dev_priv->wm.distrust_bios_wm = true;
Matt Roper279e99d2016-05-12 07:06:02 -07005969 }
Pradeep Bhat30789992014-11-04 17:06:45 +00005970}
5971
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005972static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
Ville Syrjälä243e6a42013-10-14 14:55:24 +03005973{
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005974 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005975 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak820c1982013-12-17 14:46:36 +02005976 struct ilk_wm_values *hw = &dev_priv->wm.hw;
Maarten Lankhorstec193642019-06-28 10:55:17 +02005977 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
5978 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005979 enum pipe pipe = crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005980 static const i915_reg_t wm0_pipe_reg[] = {
Ville Syrjälä243e6a42013-10-14 14:55:24 +03005981 [PIPE_A] = WM0_PIPEA_ILK,
5982 [PIPE_B] = WM0_PIPEB_ILK,
5983 [PIPE_C] = WM0_PIPEC_IVB,
5984 };
5985
5986 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
Ville Syrjälä243e6a42013-10-14 14:55:24 +03005987
Ville Syrjälä15606532016-05-13 17:55:17 +03005988 memset(active, 0, sizeof(*active));
5989
Matt Ropercd1d3ee2018-12-10 13:54:14 -08005990 active->pipe_enabled = crtc->active;
Ville Syrjälä2a44b762014-03-07 18:32:09 +02005991
5992 if (active->pipe_enabled) {
Ville Syrjälä243e6a42013-10-14 14:55:24 +03005993 u32 tmp = hw->wm_pipe[pipe];
5994
5995 /*
5996 * For active pipes LP0 watermark is marked as
5997 * enabled, and LP1+ watermaks as disabled since
5998 * we can't really reverse compute them in case
5999 * multiple pipes are active.
6000 */
6001 active->wm[0].enable = true;
6002 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
6003 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
6004 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006005 } else {
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01006006 int level, max_level = ilk_wm_max_level(dev_priv);
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006007
6008 /*
6009 * For inactive pipes, all watermark levels
6010 * should be marked as enabled but zeroed,
6011 * which is what we'd compute them to.
6012 */
6013 for (level = 0; level <= max_level; level++)
6014 active->wm[level].enable = true;
6015 }
Matt Roper4e0963c2015-09-24 15:53:15 -07006016
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006017 crtc->wm.active.ilk = *active;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006018}
6019
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006020#define _FW_WM(value, plane) \
6021 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
6022#define _FW_WM_VLV(value, plane) \
6023 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
6024
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006025static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
6026 struct g4x_wm_values *wm)
6027{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006028 u32 tmp;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006029
6030 tmp = I915_READ(DSPFW1);
6031 wm->sr.plane = _FW_WM(tmp, SR);
6032 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6033 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6034 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6035
6036 tmp = I915_READ(DSPFW2);
6037 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
6038 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
6039 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
6040 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6041 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6042 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6043
6044 tmp = I915_READ(DSPFW3);
6045 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
6046 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6047 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
6048 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
6049}
6050
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006051static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
6052 struct vlv_wm_values *wm)
6053{
6054 enum pipe pipe;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006055 u32 tmp;
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006056
6057 for_each_pipe(dev_priv, pipe) {
6058 tmp = I915_READ(VLV_DDL(pipe));
6059
Ville Syrjälä1b313892016-11-28 19:37:08 +02006060 wm->ddl[pipe].plane[PLANE_PRIMARY] =
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006061 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006062 wm->ddl[pipe].plane[PLANE_CURSOR] =
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006063 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006064 wm->ddl[pipe].plane[PLANE_SPRITE0] =
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006065 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006066 wm->ddl[pipe].plane[PLANE_SPRITE1] =
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006067 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6068 }
6069
6070 tmp = I915_READ(DSPFW1);
6071 wm->sr.plane = _FW_WM(tmp, SR);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006072 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6073 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6074 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006075
6076 tmp = I915_READ(DSPFW2);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006077 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6078 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6079 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006080
6081 tmp = I915_READ(DSPFW3);
6082 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6083
6084 if (IS_CHERRYVIEW(dev_priv)) {
6085 tmp = I915_READ(DSPFW7_CHV);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006086 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6087 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006088
6089 tmp = I915_READ(DSPFW8_CHV);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006090 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6091 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006092
6093 tmp = I915_READ(DSPFW9_CHV);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006094 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6095 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006096
6097 tmp = I915_READ(DSPHOWM);
6098 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
Ville Syrjälä1b313892016-11-28 19:37:08 +02006099 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6100 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6101 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6102 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6103 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6104 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6105 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6106 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6107 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006108 } else {
6109 tmp = I915_READ(DSPFW7);
Ville Syrjälä1b313892016-11-28 19:37:08 +02006110 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6111 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006112
6113 tmp = I915_READ(DSPHOWM);
6114 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
Ville Syrjälä1b313892016-11-28 19:37:08 +02006115 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6116 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6117 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6118 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6119 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6120 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006121 }
6122}
6123
6124#undef _FW_WM
6125#undef _FW_WM_VLV
6126
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006127void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006128{
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006129 struct g4x_wm_values *wm = &dev_priv->wm.g4x;
6130 struct intel_crtc *crtc;
6131
6132 g4x_read_wm_values(dev_priv, wm);
6133
6134 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
6135
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006136 for_each_intel_crtc(&dev_priv->drm, crtc) {
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006137 struct intel_crtc_state *crtc_state =
6138 to_intel_crtc_state(crtc->base.state);
6139 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6140 struct g4x_pipe_wm *raw;
6141 enum pipe pipe = crtc->pipe;
6142 enum plane_id plane_id;
6143 int level, max_level;
6144
6145 active->cxsr = wm->cxsr;
6146 active->hpll_en = wm->hpll_en;
6147 active->fbc_en = wm->fbc_en;
6148
6149 active->sr = wm->sr;
6150 active->hpll = wm->hpll;
6151
6152 for_each_plane_id_on_crtc(crtc, plane_id) {
6153 active->wm.plane[plane_id] =
6154 wm->pipe[pipe].plane[plane_id];
6155 }
6156
6157 if (wm->cxsr && wm->hpll_en)
6158 max_level = G4X_WM_LEVEL_HPLL;
6159 else if (wm->cxsr)
6160 max_level = G4X_WM_LEVEL_SR;
6161 else
6162 max_level = G4X_WM_LEVEL_NORMAL;
6163
6164 level = G4X_WM_LEVEL_NORMAL;
6165 raw = &crtc_state->wm.g4x.raw[level];
6166 for_each_plane_id_on_crtc(crtc, plane_id)
6167 raw->plane[plane_id] = active->wm.plane[plane_id];
6168
6169 if (++level > max_level)
6170 goto out;
6171
6172 raw = &crtc_state->wm.g4x.raw[level];
6173 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6174 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6175 raw->plane[PLANE_SPRITE0] = 0;
6176 raw->fbc = active->sr.fbc;
6177
6178 if (++level > max_level)
6179 goto out;
6180
6181 raw = &crtc_state->wm.g4x.raw[level];
6182 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6183 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6184 raw->plane[PLANE_SPRITE0] = 0;
6185 raw->fbc = active->hpll.fbc;
6186
6187 out:
6188 for_each_plane_id_on_crtc(crtc, plane_id)
6189 g4x_raw_plane_wm_set(crtc_state, level,
6190 plane_id, USHRT_MAX);
6191 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6192
6193 crtc_state->wm.g4x.optimal = *active;
6194 crtc_state->wm.g4x.intermediate = *active;
6195
Wambui Karugaf8d18d52020-01-07 18:13:30 +03006196 drm_dbg_kms(&dev_priv->drm,
6197 "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6198 pipe_name(pipe),
6199 wm->pipe[pipe].plane[PLANE_PRIMARY],
6200 wm->pipe[pipe].plane[PLANE_CURSOR],
6201 wm->pipe[pipe].plane[PLANE_SPRITE0]);
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006202 }
6203
Wambui Karugaf8d18d52020-01-07 18:13:30 +03006204 drm_dbg_kms(&dev_priv->drm,
6205 "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6206 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6207 drm_dbg_kms(&dev_priv->drm,
6208 "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6209 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6210 drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6211 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006212}
6213
6214void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6215{
6216 struct intel_plane *plane;
6217 struct intel_crtc *crtc;
6218
6219 mutex_lock(&dev_priv->wm.wm_mutex);
6220
6221 for_each_intel_plane(&dev_priv->drm, plane) {
6222 struct intel_crtc *crtc =
6223 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6224 struct intel_crtc_state *crtc_state =
6225 to_intel_crtc_state(crtc->base.state);
6226 struct intel_plane_state *plane_state =
6227 to_intel_plane_state(plane->base.state);
6228 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6229 enum plane_id plane_id = plane->id;
6230 int level;
6231
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01006232 if (plane_state->uapi.visible)
Ville Syrjälä04548cb2017-04-21 21:14:29 +03006233 continue;
6234
6235 for (level = 0; level < 3; level++) {
6236 struct g4x_pipe_wm *raw =
6237 &crtc_state->wm.g4x.raw[level];
6238
6239 raw->plane[plane_id] = 0;
6240 wm_state->wm.plane[plane_id] = 0;
6241 }
6242
6243 if (plane_id == PLANE_PRIMARY) {
6244 for (level = 0; level < 3; level++) {
6245 struct g4x_pipe_wm *raw =
6246 &crtc_state->wm.g4x.raw[level];
6247 raw->fbc = 0;
6248 }
6249
6250 wm_state->sr.fbc = 0;
6251 wm_state->hpll.fbc = 0;
6252 wm_state->fbc_en = false;
6253 }
6254 }
6255
6256 for_each_intel_crtc(&dev_priv->drm, crtc) {
6257 struct intel_crtc_state *crtc_state =
6258 to_intel_crtc_state(crtc->base.state);
6259
6260 crtc_state->wm.g4x.intermediate =
6261 crtc_state->wm.g4x.optimal;
6262 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6263 }
6264
6265 g4x_program_watermarks(dev_priv);
6266
6267 mutex_unlock(&dev_priv->wm.wm_mutex);
6268}
6269
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006270void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006271{
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006272 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
Ville Syrjäläf07d43d2017-03-02 19:14:52 +02006273 struct intel_crtc *crtc;
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006274 u32 val;
6275
6276 vlv_read_wm_values(dev_priv, wm);
6277
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006278 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6279 wm->level = VLV_WM_LEVEL_PM2;
6280
6281 if (IS_CHERRYVIEW(dev_priv)) {
Chris Wilson337fa6e2019-04-26 09:17:20 +01006282 vlv_punit_get(dev_priv);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006283
Ville Syrjäläc11b8132018-11-29 19:55:03 +02006284 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006285 if (val & DSP_MAXFIFO_PM5_ENABLE)
6286 wm->level = VLV_WM_LEVEL_PM5;
6287
Ville Syrjälä58590c12015-09-08 21:05:12 +03006288 /*
6289 * If DDR DVFS is disabled in the BIOS, Punit
6290 * will never ack the request. So if that happens
6291 * assume we don't have to enable/disable DDR DVFS
6292 * dynamically. To test that just set the REQ_ACK
6293 * bit to poke the Punit, but don't change the
6294 * HIGH/LOW bits so that we don't actually change
6295 * the current state.
6296 */
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006297 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
Ville Syrjälä58590c12015-09-08 21:05:12 +03006298 val |= FORCE_DDR_FREQ_REQ_ACK;
6299 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6300
6301 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6302 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03006303 drm_dbg_kms(&dev_priv->drm,
6304 "Punit not acking DDR DVFS request, "
6305 "assuming DDR DVFS is disabled\n");
Ville Syrjälä58590c12015-09-08 21:05:12 +03006306 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6307 } else {
6308 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6309 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6310 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6311 }
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006312
Chris Wilson337fa6e2019-04-26 09:17:20 +01006313 vlv_punit_put(dev_priv);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006314 }
6315
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006316 for_each_intel_crtc(&dev_priv->drm, crtc) {
Ville Syrjäläff32c542017-03-02 19:14:57 +02006317 struct intel_crtc_state *crtc_state =
6318 to_intel_crtc_state(crtc->base.state);
6319 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6320 const struct vlv_fifo_state *fifo_state =
6321 &crtc_state->wm.vlv.fifo_state;
6322 enum pipe pipe = crtc->pipe;
6323 enum plane_id plane_id;
6324 int level;
6325
6326 vlv_get_fifo_size(crtc_state);
6327
6328 active->num_levels = wm->level + 1;
6329 active->cxsr = wm->cxsr;
6330
Ville Syrjäläff32c542017-03-02 19:14:57 +02006331 for (level = 0; level < active->num_levels; level++) {
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03006332 struct g4x_pipe_wm *raw =
Ville Syrjäläff32c542017-03-02 19:14:57 +02006333 &crtc_state->wm.vlv.raw[level];
6334
6335 active->sr[level].plane = wm->sr.plane;
6336 active->sr[level].cursor = wm->sr.cursor;
6337
6338 for_each_plane_id_on_crtc(crtc, plane_id) {
6339 active->wm[level].plane[plane_id] =
6340 wm->pipe[pipe].plane[plane_id];
6341
6342 raw->plane[plane_id] =
6343 vlv_invert_wm_value(active->wm[level].plane[plane_id],
6344 fifo_state->plane[plane_id]);
6345 }
6346 }
6347
6348 for_each_plane_id_on_crtc(crtc, plane_id)
6349 vlv_raw_plane_wm_set(crtc_state, level,
6350 plane_id, USHRT_MAX);
6351 vlv_invalidate_wms(crtc, active, level);
6352
6353 crtc_state->wm.vlv.optimal = *active;
Ville Syrjälä4841da52017-03-02 19:14:59 +02006354 crtc_state->wm.vlv.intermediate = *active;
Ville Syrjäläff32c542017-03-02 19:14:57 +02006355
Wambui Karugaf8d18d52020-01-07 18:13:30 +03006356 drm_dbg_kms(&dev_priv->drm,
6357 "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6358 pipe_name(pipe),
6359 wm->pipe[pipe].plane[PLANE_PRIMARY],
6360 wm->pipe[pipe].plane[PLANE_CURSOR],
6361 wm->pipe[pipe].plane[PLANE_SPRITE0],
6362 wm->pipe[pipe].plane[PLANE_SPRITE1]);
Ville Syrjäläff32c542017-03-02 19:14:57 +02006363 }
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006364
Wambui Karugaf8d18d52020-01-07 18:13:30 +03006365 drm_dbg_kms(&dev_priv->drm,
6366 "Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
6367 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03006368}
6369
Ville Syrjälä602ae832017-03-02 19:15:02 +02006370void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
6371{
6372 struct intel_plane *plane;
6373 struct intel_crtc *crtc;
6374
6375 mutex_lock(&dev_priv->wm.wm_mutex);
6376
6377 for_each_intel_plane(&dev_priv->drm, plane) {
6378 struct intel_crtc *crtc =
6379 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6380 struct intel_crtc_state *crtc_state =
6381 to_intel_crtc_state(crtc->base.state);
6382 struct intel_plane_state *plane_state =
6383 to_intel_plane_state(plane->base.state);
6384 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6385 const struct vlv_fifo_state *fifo_state =
6386 &crtc_state->wm.vlv.fifo_state;
6387 enum plane_id plane_id = plane->id;
6388 int level;
6389
Maarten Lankhorstf90a85e2019-10-31 12:26:08 +01006390 if (plane_state->uapi.visible)
Ville Syrjälä602ae832017-03-02 19:15:02 +02006391 continue;
6392
6393 for (level = 0; level < wm_state->num_levels; level++) {
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03006394 struct g4x_pipe_wm *raw =
Ville Syrjälä602ae832017-03-02 19:15:02 +02006395 &crtc_state->wm.vlv.raw[level];
6396
6397 raw->plane[plane_id] = 0;
6398
6399 wm_state->wm[level].plane[plane_id] =
6400 vlv_invert_wm_value(raw->plane[plane_id],
6401 fifo_state->plane[plane_id]);
6402 }
6403 }
6404
6405 for_each_intel_crtc(&dev_priv->drm, crtc) {
6406 struct intel_crtc_state *crtc_state =
6407 to_intel_crtc_state(crtc->base.state);
6408
6409 crtc_state->wm.vlv.intermediate =
6410 crtc_state->wm.vlv.optimal;
6411 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6412 }
6413
6414 vlv_program_watermarks(dev_priv);
6415
6416 mutex_unlock(&dev_priv->wm.wm_mutex);
6417}
6418
Ville Syrjäläf72b84c2017-11-08 15:35:55 +02006419/*
6420 * FIXME should probably kill this and improve
6421 * the real watermark readout/sanitation instead
6422 */
6423static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6424{
6425 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6426 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6427 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6428
6429 /*
6430 * Don't touch WM1S_LP_EN here.
6431 * Doing so could cause underruns.
6432 */
6433}
6434
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006435void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006436{
Imre Deak820c1982013-12-17 14:46:36 +02006437 struct ilk_wm_values *hw = &dev_priv->wm.hw;
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006438 struct intel_crtc *crtc;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006439
Ville Syrjäläf72b84c2017-11-08 15:35:55 +02006440 ilk_init_lp_watermarks(dev_priv);
6441
Matt Ropercd1d3ee2018-12-10 13:54:14 -08006442 for_each_intel_crtc(&dev_priv->drm, crtc)
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006443 ilk_pipe_wm_get_hw_state(crtc);
6444
6445 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
6446 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
6447 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
6448
6449 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
Tvrtko Ursulin175fded2016-11-16 08:55:42 +00006450 if (INTEL_GEN(dev_priv) >= 7) {
Ville Syrjäläcfa76982014-03-07 18:32:08 +02006451 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
6452 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
6453 }
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006454
Tvrtko Ursulin86527442016-10-13 11:03:00 +01006455 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjäläac9545f2013-12-05 15:51:28 +02006456 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
6457 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +01006458 else if (IS_IVYBRIDGE(dev_priv))
Ville Syrjäläac9545f2013-12-05 15:51:28 +02006459 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
6460 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03006461
6462 hw->enable_fbc_wm =
6463 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
6464}
6465
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03006466/**
6467 * intel_update_watermarks - update FIFO watermark values based on current modes
Chris Wilson31383412018-02-14 14:03:03 +00006468 * @crtc: the #intel_crtc on which to compute the WM
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03006469 *
6470 * Calculate watermark values for the various WM regs based on current mode
6471 * and plane configuration.
6472 *
6473 * There are several cases to deal with here:
6474 * - normal (i.e. non-self-refresh)
6475 * - self-refresh (SR) mode
6476 * - lines are large relative to FIFO size (buffer can hold up to 2)
6477 * - lines are small relative to FIFO size (buffer can hold more than 2
6478 * lines), so need to account for TLB latency
6479 *
6480 * The normal calculation is:
6481 * watermark = dotclock * bytes per pixel * latency
6482 * where latency is platform & configuration dependent (we assume pessimal
6483 * values here).
6484 *
6485 * The SR calculation is:
6486 * watermark = (trunc(latency/line time)+1) * surface width *
6487 * bytes per pixel
6488 * where
6489 * line time = htotal / dotclock
6490 * surface width = hdisplay for normal plane and 64 for cursor
6491 * and latency is assumed to be high, as above.
6492 *
6493 * The final value programmed to the register should always be rounded up,
6494 * and include an extra 2 entries to account for clock crossings.
6495 *
6496 * We don't use the sprite, so we can ignore that. And on Crestline we have
6497 * to set the non-SR watermarks to 8.
6498 */
Ville Syrjälä432081b2016-10-31 22:37:03 +02006499void intel_update_watermarks(struct intel_crtc *crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03006500{
Ville Syrjälä432081b2016-10-31 22:37:03 +02006501 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03006502
6503 if (dev_priv->display.update_wm)
Ville Syrjälä46ba6142013-09-10 11:40:40 +03006504 dev_priv->display.update_wm(crtc);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03006505}
6506
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05306507void intel_enable_ipc(struct drm_i915_private *dev_priv)
6508{
6509 u32 val;
6510
José Roberto de Souzafd847b82018-09-18 13:47:11 -07006511 if (!HAS_IPC(dev_priv))
6512 return;
6513
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05306514 val = I915_READ(DISP_ARB_CTL2);
6515
6516 if (dev_priv->ipc_enabled)
6517 val |= DISP_IPC_ENABLE;
6518 else
6519 val &= ~DISP_IPC_ENABLE;
6520
6521 I915_WRITE(DISP_ARB_CTL2, val);
6522}
6523
Ville Syrjäläc91a45f2019-05-03 20:38:07 +03006524static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
6525{
6526 /* Display WA #0477 WaDisableIPC: skl */
6527 if (IS_SKYLAKE(dev_priv))
6528 return false;
6529
6530 /* Display WA #1141: SKL:all KBL:all CFL */
6531 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
6532 return dev_priv->dram_info.symmetric_memory;
6533
6534 return true;
6535}
6536
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05306537void intel_init_ipc(struct drm_i915_private *dev_priv)
6538{
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05306539 if (!HAS_IPC(dev_priv))
6540 return;
6541
Ville Syrjäläc91a45f2019-05-03 20:38:07 +03006542 dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
José Roberto de Souzac9b818d2018-09-18 13:47:13 -07006543
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05306544 intel_enable_ipc(dev_priv);
6545}
6546
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006547static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
Daniel Vetter3107bd42012-10-31 22:52:31 +01006548{
Daniel Vetter3107bd42012-10-31 22:52:31 +01006549 /*
6550 * On Ibex Peak and Cougar Point, we need to disable clock
6551 * gating for the panel power sequencer or it will fail to
6552 * start up when no ports are active.
6553 */
6554 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6555}
6556
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006557static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006558{
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +03006559 enum pipe pipe;
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006560
Damien Lespiau055e3932014-08-18 13:49:10 +01006561 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006562 I915_WRITE(DSPCNTR(pipe),
6563 I915_READ(DSPCNTR(pipe)) |
6564 DISPPLANE_TRICKLE_FEED_DISABLE);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +03006565
6566 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6567 POSTING_READ(DSPSURF(pipe));
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006568 }
6569}
6570
Rodrigo Vivi91200c02017-08-28 22:20:26 -07006571static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006572{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006573 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006574
Damien Lespiauf1e8fa52013-06-07 17:41:09 +01006575 /*
6576 * Required for FBC
6577 * WaFbcDisableDpfcClockGating:ilk
6578 */
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01006579 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6580 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6581 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006582
6583 I915_WRITE(PCH_3DCGDIS0,
6584 MARIUNIT_CLOCK_GATE_DISABLE |
6585 SVSMUNIT_CLOCK_GATE_DISABLE);
6586 I915_WRITE(PCH_3DCGDIS1,
6587 VFMUNIT_CLOCK_GATE_DISABLE);
6588
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006589 /*
6590 * According to the spec the following bits should be set in
6591 * order to enable memory self-refresh
6592 * The bit 22/21 of 0x42004
6593 * The bit 5 of 0x42020
6594 * The bit 15 of 0x45000
6595 */
6596 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6597 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6598 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01006599 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006600 I915_WRITE(DISP_ARB_CTL,
6601 (I915_READ(DISP_ARB_CTL) |
6602 DISP_FBC_WM_DIS));
Ville Syrjälä017636c2013-12-05 15:51:37 +02006603
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006604 /*
6605 * Based on the document from hardware guys the following bits
6606 * should be set unconditionally in order to enable FBC.
6607 * The bit 22 of 0x42000
6608 * The bit 22 of 0x42004
6609 * The bit 7,8,9 of 0x42020.
6610 */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01006611 if (IS_IRONLAKE_M(dev_priv)) {
Damien Lespiau4bb35332013-06-14 15:23:24 +01006612 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006613 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6614 I915_READ(ILK_DISPLAY_CHICKEN1) |
6615 ILK_FBCQ_DIS);
6616 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6617 I915_READ(ILK_DISPLAY_CHICKEN2) |
6618 ILK_DPARB_GATE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006619 }
6620
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01006621 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6622
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006623 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6624 I915_READ(ILK_DISPLAY_CHICKEN2) |
6625 ILK_ELPIN_409_SELECT);
6626 I915_WRITE(_3D_CHICKEN2,
6627 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6628 _3D_CHICKEN2_WM_READ_PIPELINED);
Daniel Vetter4358a372012-10-18 11:49:51 +02006629
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006630 /* WaDisableRenderCachePipelinedFlush:ilk */
Daniel Vetter4358a372012-10-18 11:49:51 +02006631 I915_WRITE(CACHE_MODE_0,
6632 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
Daniel Vetter3107bd42012-10-31 22:52:31 +01006633
Akash Goel4e046322014-04-04 17:14:38 +05306634 /* WaDisable_RenderCache_OperationalFlush:ilk */
6635 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6636
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006637 g4x_disable_trickle_feed(dev_priv);
Ville Syrjäläbdad2b22013-06-07 10:47:03 +03006638
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006639 ibx_init_clock_gating(dev_priv);
Daniel Vetter3107bd42012-10-31 22:52:31 +01006640}
6641
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006642static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
Daniel Vetter3107bd42012-10-31 22:52:31 +01006643{
Ville Syrjäläd048a262019-08-21 20:30:31 +03006644 enum pipe pipe;
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006645 u32 val;
Daniel Vetter3107bd42012-10-31 22:52:31 +01006646
6647 /*
6648 * On Ibex Peak and Cougar Point, we need to disable clock
6649 * gating for the panel power sequencer or it will fail to
6650 * start up when no ports are active.
6651 */
Jesse Barnescd664072013-10-02 10:34:19 -07006652 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6653 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6654 PCH_CPUNIT_CLOCK_GATE_DISABLE);
Daniel Vetter3107bd42012-10-31 22:52:31 +01006655 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6656 DPLS_EDP_PPS_FIX_DIS);
Takashi Iwai335c07b2012-12-11 11:46:29 +01006657 /* The below fixes the weird display corruption, a few pixels shifted
6658 * downward, on (only) LVDS of some HP laptops with IVY.
6659 */
Damien Lespiau055e3932014-08-18 13:49:10 +01006660 for_each_pipe(dev_priv, pipe) {
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03006661 val = I915_READ(TRANS_CHICKEN2(pipe));
6662 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6663 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006664 if (dev_priv->vbt.fdi_rx_polarity_inverted)
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03006665 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03006666 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6667 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03006668 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6669 }
Daniel Vetter3107bd42012-10-31 22:52:31 +01006670 /* WADP0ClockGatingDisable */
Damien Lespiau055e3932014-08-18 13:49:10 +01006671 for_each_pipe(dev_priv, pipe) {
Daniel Vetter3107bd42012-10-31 22:52:31 +01006672 I915_WRITE(TRANS_CHICKEN1(pipe),
6673 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6674 }
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006675}
6676
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006677static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006678{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006679 u32 tmp;
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006680
6681 tmp = I915_READ(MCH_SSKPD);
Daniel Vetterdf662a22014-08-04 11:17:25 +02006682 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
Wambui Karugaf8d18d52020-01-07 18:13:30 +03006683 drm_dbg_kms(&dev_priv->drm,
6684 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6685 tmp);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006686}
6687
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006688static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006689{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006690 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006691
Damien Lespiau231e54f2012-10-19 17:55:41 +01006692 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006693
6694 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6695 I915_READ(ILK_DISPLAY_CHICKEN2) |
6696 ILK_ELPIN_409_SELECT);
6697
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006698 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
Daniel Vetter42839082012-12-14 23:38:28 +01006699 I915_WRITE(_3D_CHICKEN,
6700 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6701
Akash Goel4e046322014-04-04 17:14:38 +05306702 /* WaDisable_RenderCache_OperationalFlush:snb */
6703 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6704
Ville Syrjälä8d85d272014-02-04 21:59:15 +02006705 /*
6706 * BSpec recoomends 8x4 when MSAA is used,
6707 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02006708 *
6709 * Note that PS/WM thread counts depend on the WIZ hashing
6710 * disable bit, which we don't touch here, but it's good
6711 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjälä8d85d272014-02-04 21:59:15 +02006712 */
6713 I915_WRITE(GEN6_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00006714 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjälä8d85d272014-02-04 21:59:15 +02006715
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006716 I915_WRITE(CACHE_MODE_0,
Daniel Vetter50743292012-04-26 22:02:54 +02006717 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006718
6719 I915_WRITE(GEN6_UCGCTL1,
6720 I915_READ(GEN6_UCGCTL1) |
6721 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6722 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6723
6724 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6725 * gating disable must be set. Failure to set it results in
6726 * flickering pixels due to Z write ordering failures after
6727 * some amount of runtime in the Mesa "fire" demo, and Unigine
6728 * Sanctuary and Tropics, and apparently anything else with
6729 * alpha test or pixel discard.
6730 *
6731 * According to the spec, bit 11 (RCCUNIT) must also be set,
6732 * but we didn't debug actual testcases to find it out.
Jesse Barnes0f846f82012-06-14 11:04:47 -07006733 *
Ville Syrjäläef593182014-01-22 21:32:47 +02006734 * WaDisableRCCUnitClockGating:snb
6735 * WaDisableRCPBUnitClockGating:snb
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006736 */
6737 I915_WRITE(GEN6_UCGCTL2,
6738 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6739 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6740
Ville Syrjälä5eb146d2014-02-04 21:59:16 +02006741 /* WaStripsFansDisableFastClipPerformanceFix:snb */
Ville Syrjälä743b57d2014-02-04 21:59:17 +02006742 I915_WRITE(_3D_CHICKEN3,
6743 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006744
6745 /*
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02006746 * Bspec says:
6747 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6748 * 3DSTATE_SF number of SF output attributes is more than 16."
6749 */
6750 I915_WRITE(_3D_CHICKEN3,
6751 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6752
6753 /*
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006754 * According to the spec the following bits should be
6755 * set in order to enable memory self-refresh and fbc:
6756 * The bit21 and bit22 of 0x42000
6757 * The bit21 and bit22 of 0x42004
6758 * The bit5 and bit7 of 0x42020
6759 * The bit14 of 0x70180
6760 * The bit14 of 0x71180
Damien Lespiau4bb35332013-06-14 15:23:24 +01006761 *
6762 * WaFbcAsynchFlipDisableFbcQueue:snb
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006763 */
6764 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6765 I915_READ(ILK_DISPLAY_CHICKEN1) |
6766 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6767 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6768 I915_READ(ILK_DISPLAY_CHICKEN2) |
6769 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
Damien Lespiau231e54f2012-10-19 17:55:41 +01006770 I915_WRITE(ILK_DSPCLK_GATE_D,
6771 I915_READ(ILK_DSPCLK_GATE_D) |
6772 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6773 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006774
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006775 g4x_disable_trickle_feed(dev_priv);
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07006776
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006777 cpt_init_clock_gating(dev_priv);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006778
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006779 gen6_check_mch_setup(dev_priv);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006780}
6781
6782static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6783{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006784 u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006785
Ville Syrjälä3aad9052014-01-22 21:32:59 +02006786 /*
Ville Syrjälä46680e02014-01-22 21:33:01 +02006787 * WaVSThreadDispatchOverride:ivb,vlv
Ville Syrjälä3aad9052014-01-22 21:32:59 +02006788 *
6789 * This actually overrides the dispatch
6790 * mode for all thread types.
6791 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006792 reg &= ~GEN7_FF_SCHED_MASK;
6793 reg |= GEN7_FF_TS_SCHED_HW;
6794 reg |= GEN7_FF_VS_SCHED_HW;
6795 reg |= GEN7_FF_DS_SCHED_HW;
6796
6797 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6798}
6799
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006800static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006801{
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006802 /*
6803 * TODO: this bit should only be enabled when really needed, then
6804 * disabled when not needed anymore in order to save power.
6805 */
Tvrtko Ursulin4f8036a2016-10-13 11:02:52 +01006806 if (HAS_PCH_LPT_LP(dev_priv))
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006807 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6808 I915_READ(SOUTH_DSPCLK_GATE_D) |
6809 PCH_LP_PARTITION_LEVEL_DISABLE);
Paulo Zanoni0a790cd2013-04-17 18:15:49 -03006810
6811 /* WADPOClockGatingDisable:hsw */
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03006812 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6813 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
Paulo Zanoni0a790cd2013-04-17 18:15:49 -03006814 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006815}
6816
Ville Syrjälä712bf362016-10-31 22:37:23 +02006817static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
Imre Deak7d708ee2013-04-17 14:04:50 +03006818{
Tvrtko Ursulin4f8036a2016-10-13 11:02:52 +01006819 if (HAS_PCH_LPT_LP(dev_priv)) {
Jani Nikula5ce9a6492019-01-18 14:01:20 +02006820 u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
Imre Deak7d708ee2013-04-17 14:04:50 +03006821
6822 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6823 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6824 }
6825}
6826
Imre Deak450174f2016-05-03 15:54:21 +03006827static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6828 int general_prio_credits,
6829 int high_prio_credits)
6830{
6831 u32 misccpctl;
Oscar Mateo930a7842017-10-17 13:25:45 -07006832 u32 val;
Imre Deak450174f2016-05-03 15:54:21 +03006833
6834 /* WaTempDisableDOPClkGating:bdw */
6835 misccpctl = I915_READ(GEN7_MISCCPCTL);
6836 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6837
Oscar Mateo930a7842017-10-17 13:25:45 -07006838 val = I915_READ(GEN8_L3SQCREG1);
6839 val &= ~L3_PRIO_CREDITS_MASK;
6840 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
6841 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
6842 I915_WRITE(GEN8_L3SQCREG1, val);
Imre Deak450174f2016-05-03 15:54:21 +03006843
6844 /*
6845 * Wait at least 100 clocks before re-enabling clock gating.
6846 * See the definition of L3SQCREG1 in BSpec.
6847 */
6848 POSTING_READ(GEN8_L3SQCREG1);
6849 udelay(1);
6850 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6851}
6852
Oscar Mateod65dc3e2018-05-08 14:29:24 -07006853static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
6854{
6855 /* This is not an Wa. Enable to reduce Sampler power */
6856 I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
6857 I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
Radhakrishna Sripada622b3f62018-10-30 01:45:01 -07006858
Matt Atwood6f4194c2020-01-13 23:11:28 -05006859 /*Wa_14010594013:icl, ehl */
6860 intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
6861 0, CNL_DELAY_PMRSP);
Oscar Mateod65dc3e2018-05-08 14:29:24 -07006862}
6863
Michel Thierry5d869232019-08-23 01:20:34 -07006864static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
6865{
6866 u32 vd_pg_enable = 0;
6867 unsigned int i;
6868
6869 /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
6870 for (i = 0; i < I915_MAX_VCS; i++) {
6871 if (HAS_ENGINE(dev_priv, _VCS(i)))
6872 vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
6873 VDN_MFX_POWERGATE_ENABLE(i);
6874 }
6875
6876 I915_WRITE(POWERGATE_ENABLE,
6877 I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
Radhakrishna Sripadaf78d5da2020-01-09 14:37:27 -08006878
6879 /* Wa_1409825376:tgl (pre-prod)*/
6880 if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
6881 I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
6882 TGL_VRH_GATING_DIS);
Michel Thierry5d869232019-08-23 01:20:34 -07006883}
6884
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07006885static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
6886{
6887 if (!HAS_PCH_CNP(dev_priv))
6888 return;
6889
Rodrigo Vivi470e7c62018-03-05 17:28:12 -08006890 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
Rodrigo Vivi4cc6feb2017-09-08 16:45:33 -07006891 I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
6892 CNP_PWM_CGE_GATING_DISABLE);
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07006893}
6894
Rodrigo Vivi91200c02017-08-28 22:20:26 -07006895static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07006896{
Rodrigo Vivi8f067832017-09-05 12:30:13 -07006897 u32 val;
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07006898 cnp_init_clock_gating(dev_priv);
6899
Rodrigo Vivi1a25db62017-08-15 16:16:51 -07006900 /* This is not an Wa. Enable for better image quality */
6901 I915_WRITE(_3D_CHICKEN3,
6902 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
6903
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07006904 /* WaEnableChickenDCPR:cnl */
6905 I915_WRITE(GEN8_CHICKEN_DCPR_1,
6906 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
6907
6908 /* WaFbcWakeMemOn:cnl */
6909 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
6910 DISP_FBC_MEMORY_WAKE);
6911
Chris Wilson34991bd2017-11-11 10:03:36 +00006912 val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
6913 /* ReadHitWriteOnlyDisable:cnl */
6914 val |= RCCUNIT_CLKGATE_DIS;
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07006915 /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
6916 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
Chris Wilson34991bd2017-11-11 10:03:36 +00006917 val |= SARBUNIT_CLKGATE_DIS;
6918 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
Rafael Antognolli01ab0f92017-12-15 16:11:16 -08006919
Rodrigo Vivia4713c52018-03-07 14:09:12 -08006920 /* Wa_2201832410:cnl */
6921 val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
6922 val |= GWUNIT_CLKGATE_DIS;
6923 I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
6924
Rafael Antognolli01ab0f92017-12-15 16:11:16 -08006925 /* WaDisableVFclkgate:cnl */
Rodrigo Vivi14941b62018-03-05 17:20:00 -08006926 /* WaVFUnitClockGatingDisable:cnl */
Rafael Antognolli01ab0f92017-12-15 16:11:16 -08006927 val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
6928 val |= VFUNIT_CLKGATE_DIS;
6929 I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07006930}
6931
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07006932static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
6933{
6934 cnp_init_clock_gating(dev_priv);
6935 gen9_init_clock_gating(dev_priv);
6936
6937 /* WaFbcNukeOnHostModify:cfl */
6938 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
6939 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
6940}
6941
Rodrigo Vivi91200c02017-08-28 22:20:26 -07006942static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
Mika Kuoppala9498dba2016-06-07 17:19:01 +03006943{
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006944 gen9_init_clock_gating(dev_priv);
Mika Kuoppala9498dba2016-06-07 17:19:01 +03006945
6946 /* WaDisableSDEUnitClockGating:kbl */
6947 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6948 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6949 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Mika Kuoppala8aeb7f62016-06-07 17:19:05 +03006950
6951 /* WaDisableGamClockGating:kbl */
6952 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6953 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6954 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03006955
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07006956 /* WaFbcNukeOnHostModify:kbl */
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03006957 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
6958 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
Mika Kuoppala9498dba2016-06-07 17:19:01 +03006959}
6960
Rodrigo Vivi91200c02017-08-28 22:20:26 -07006961static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02006962{
Ville Syrjälä46f16e62016-10-31 22:37:22 +02006963 gen9_init_clock_gating(dev_priv);
Mika Kuoppala44fff992016-06-07 17:19:09 +03006964
6965 /* WAC6entrylatency:skl */
6966 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
6967 FBC_LLC_FULLY_OPEN);
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03006968
6969 /* WaFbcNukeOnHostModify:skl */
6970 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
6971 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02006972}
6973
Rodrigo Vivi91200c02017-08-28 22:20:26 -07006974static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
Ben Widawsky1020a5c2013-11-02 21:07:06 -07006975{
Damien Lespiau07d27e22014-03-03 17:31:46 +00006976 enum pipe pipe;
Ben Widawsky1020a5c2013-11-02 21:07:06 -07006977
Ben Widawskyab57fff2013-12-12 15:28:04 -08006978 /* WaSwitchSolVfFArbitrationPriority:bdw */
Ben Widawsky50ed5fb2013-11-02 21:07:40 -07006979 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006980
Ben Widawskyab57fff2013-12-12 15:28:04 -08006981 /* WaPsrDPAMaskVBlankInSRD:bdw */
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006982 I915_WRITE(CHICKEN_PAR1_1,
6983 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6984
Ben Widawskyab57fff2013-12-12 15:28:04 -08006985 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
Damien Lespiau055e3932014-08-18 13:49:10 +01006986 for_each_pipe(dev_priv, pipe) {
Damien Lespiau07d27e22014-03-03 17:31:46 +00006987 I915_WRITE(CHICKEN_PIPESL_1(pipe),
Ville Syrjäläc7c65622014-03-05 13:05:45 +02006988 I915_READ(CHICKEN_PIPESL_1(pipe)) |
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02006989 BDW_DPRS_MASK_VBLANK_SRD);
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006990 }
Ben Widawsky63801f22013-12-12 17:26:03 -08006991
Ben Widawskyab57fff2013-12-12 15:28:04 -08006992 /* WaVSRefCountFullforceMissDisable:bdw */
6993 /* WaDSRefCountFullforceMissDisable:bdw */
6994 I915_WRITE(GEN7_FF_THREAD_MODE,
6995 I915_READ(GEN7_FF_THREAD_MODE) &
6996 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Ville Syrjälä36075a42014-02-04 21:59:21 +02006997
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02006998 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6999 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02007000
7001 /* WaDisableSDEUnitClockGating:bdw */
7002 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7003 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Damien Lespiau5d708682014-03-26 18:41:51 +00007004
Imre Deak450174f2016-05-03 15:54:21 +03007005 /* WaProgramL3SqcReg1Default:bdw */
7006 gen8_set_l3sqc_credits(dev_priv, 30, 2);
Ville Syrjälä4d487cf2015-05-19 20:32:56 +03007007
Mika Kuoppala17e0adf2016-06-07 17:19:02 +03007008 /* WaKVMNotificationOnConfigChange:bdw */
7009 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7010 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7011
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007012 lpt_init_clock_gating(dev_priv);
Robert Bragg9cc19732017-02-12 13:32:52 +00007013
7014 /* WaDisableDopClockGating:bdw
7015 *
7016 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7017 * clock gating.
7018 */
7019 I915_WRITE(GEN6_UCGCTL1,
7020 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
Ben Widawsky1020a5c2013-11-02 21:07:06 -07007021}
7022
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007023static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007024{
Francisco Jerezf3fc4882013-10-02 15:53:16 -07007025 /* L3 caching of data atomics doesn't work -- disable it. */
7026 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7027 I915_WRITE(HSW_ROW_CHICKEN3,
7028 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7029
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007030 /* This is required by WaCatErrorRejectionIssue:hsw */
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007031 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7032 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7033 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7034
Ville Syrjäläe36ea7f2014-01-22 21:33:00 +02007035 /* WaVSRefCountFullforceMissDisable:hsw */
7036 I915_WRITE(GEN7_FF_THREAD_MODE,
7037 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007038
Akash Goel4e046322014-04-04 17:14:38 +05307039 /* WaDisable_RenderCache_OperationalFlush:hsw */
7040 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7041
Chia-I Wufe27c602014-01-28 13:29:33 +08007042 /* enable HiZ Raw Stall Optimization */
7043 I915_WRITE(CACHE_MODE_0_GEN7,
7044 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7045
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007046 /* WaDisable4x2SubspanOptimization:hsw */
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007047 I915_WRITE(CACHE_MODE_1,
7048 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03007049
Ville Syrjäläa12c4962014-02-04 21:59:20 +02007050 /*
7051 * BSpec recommends 8x4 when MSAA is used,
7052 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02007053 *
7054 * Note that PS/WM thread counts depend on the WIZ hashing
7055 * disable bit, which we don't touch here, but it's good
7056 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjäläa12c4962014-02-04 21:59:20 +02007057 */
7058 I915_WRITE(GEN7_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00007059 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjäläa12c4962014-02-04 21:59:20 +02007060
Kenneth Graunke94411592014-12-31 16:23:00 -08007061 /* WaSampleCChickenBitEnable:hsw */
7062 I915_WRITE(HALF_SLICE_CHICKEN3,
7063 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7064
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007065 /* WaSwitchSolVfFArbitrationPriority:hsw */
Ben Widawskye3dff582013-03-20 14:49:14 -07007066 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7067
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007068 lpt_init_clock_gating(dev_priv);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007069}
7070
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007071static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007072{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02007073 u32 snpcr;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007074
Damien Lespiau231e54f2012-10-19 17:55:41 +01007075 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007076
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007077 /* WaDisableEarlyCull:ivb */
Jesse Barnes87f80202012-10-02 17:43:41 -05007078 I915_WRITE(_3D_CHICKEN3,
7079 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7080
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007081 /* WaDisableBackToBackFlipFix:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007082 I915_WRITE(IVB_CHICKEN3,
7083 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7084 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7085
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007086 /* WaDisablePSDDualDispatchEnable:ivb */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01007087 if (IS_IVB_GT1(dev_priv))
Jesse Barnes12f33822012-10-25 12:15:45 -07007088 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7089 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
Jesse Barnes12f33822012-10-25 12:15:45 -07007090
Akash Goel4e046322014-04-04 17:14:38 +05307091 /* WaDisable_RenderCache_OperationalFlush:ivb */
7092 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7093
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007094 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007095 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7096 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7097
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007098 /* WaApplyL3ControlAndL3ChickenMode:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007099 I915_WRITE(GEN7_L3CNTLREG1,
7100 GEN7_WA_FOR_GEN7_L3_CONTROL);
7101 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
Jesse Barnes8ab43972012-10-25 12:15:42 -07007102 GEN7_WA_L3_CHICKEN_MODE);
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01007103 if (IS_IVB_GT1(dev_priv))
Jesse Barnes8ab43972012-10-25 12:15:42 -07007104 I915_WRITE(GEN7_ROW_CHICKEN2,
7105 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Ville Syrjälä412236c2014-01-22 21:32:44 +02007106 else {
7107 /* must write both registers */
7108 I915_WRITE(GEN7_ROW_CHICKEN2,
7109 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Jesse Barnes8ab43972012-10-25 12:15:42 -07007110 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7111 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Ville Syrjälä412236c2014-01-22 21:32:44 +02007112 }
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007113
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007114 /* WaForceL3Serialization:ivb */
Jesse Barnes61939d92012-10-02 17:43:38 -05007115 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7116 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7117
Ville Syrjälä1b80a19a2014-01-22 21:32:53 +02007118 /*
Jesse Barnes0f846f82012-06-14 11:04:47 -07007119 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007120 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
Jesse Barnes0f846f82012-06-14 11:04:47 -07007121 */
7122 I915_WRITE(GEN6_UCGCTL2,
Ville Syrjälä28acf3b2014-01-22 21:32:48 +02007123 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes0f846f82012-06-14 11:04:47 -07007124
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007125 /* This is required by WaCatErrorRejectionIssue:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007126 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7127 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7128 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7129
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007130 g4x_disable_trickle_feed(dev_priv);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007131
7132 gen7_setup_fixed_func_scheduler(dev_priv);
Daniel Vetter97e19302012-04-24 16:00:21 +02007133
Chris Wilson22721342014-03-04 09:41:43 +00007134 if (0) { /* causes HiZ corruption on ivb:gt1 */
7135 /* enable HiZ Raw Stall Optimization */
7136 I915_WRITE(CACHE_MODE_0_GEN7,
7137 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7138 }
Chia-I Wu116f2b62014-01-28 13:29:34 +08007139
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007140 /* WaDisable4x2SubspanOptimization:ivb */
Daniel Vetter97e19302012-04-24 16:00:21 +02007141 I915_WRITE(CACHE_MODE_1,
7142 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Ben Widawsky20848222012-05-04 18:58:59 -07007143
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02007144 /*
7145 * BSpec recommends 8x4 when MSAA is used,
7146 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02007147 *
7148 * Note that PS/WM thread counts depend on the WIZ hashing
7149 * disable bit, which we don't touch here, but it's good
7150 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02007151 */
7152 I915_WRITE(GEN7_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00007153 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02007154
Ben Widawsky20848222012-05-04 18:58:59 -07007155 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7156 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7157 snpcr |= GEN6_MBC_SNPCR_MED;
7158 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
Daniel Vetter3107bd42012-10-31 22:52:31 +01007159
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01007160 if (!HAS_PCH_NOP(dev_priv))
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007161 cpt_init_clock_gating(dev_priv);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01007162
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007163 gen6_check_mch_setup(dev_priv);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007164}
7165
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007166static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007167{
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007168 /* WaDisableEarlyCull:vlv */
Jesse Barnes87f80202012-10-02 17:43:41 -05007169 I915_WRITE(_3D_CHICKEN3,
7170 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7171
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007172 /* WaDisableBackToBackFlipFix:vlv */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007173 I915_WRITE(IVB_CHICKEN3,
7174 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7175 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7176
Ville Syrjäläfad7d362014-01-22 21:32:39 +02007177 /* WaPsdDispatchEnable:vlv */
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007178 /* WaDisablePSDDualDispatchEnable:vlv */
Jesse Barnes12f33822012-10-25 12:15:45 -07007179 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
Jesse Barnesd3bc0302013-03-08 10:45:51 -08007180 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7181 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
Jesse Barnes12f33822012-10-25 12:15:45 -07007182
Akash Goel4e046322014-04-04 17:14:38 +05307183 /* WaDisable_RenderCache_OperationalFlush:vlv */
7184 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7185
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007186 /* WaForceL3Serialization:vlv */
Jesse Barnes61939d92012-10-02 17:43:38 -05007187 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7188 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7189
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007190 /* WaDisableDopClockGating:vlv */
Jesse Barnes8ab43972012-10-25 12:15:42 -07007191 I915_WRITE(GEN7_ROW_CHICKEN2,
7192 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7193
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007194 /* This is required by WaCatErrorRejectionIssue:vlv */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007195 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7196 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7197 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7198
Ville Syrjälä46680e02014-01-22 21:33:01 +02007199 gen7_setup_fixed_func_scheduler(dev_priv);
7200
Ville Syrjälä3c0edae2014-01-22 21:32:56 +02007201 /*
Jesse Barnes0f846f82012-06-14 11:04:47 -07007202 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007203 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
Jesse Barnes0f846f82012-06-14 11:04:47 -07007204 */
7205 I915_WRITE(GEN6_UCGCTL2,
Ville Syrjälä3c0edae2014-01-22 21:32:56 +02007206 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes0f846f82012-06-14 11:04:47 -07007207
Akash Goelc98f5062014-03-24 23:00:07 +05307208 /* WaDisableL3Bank2xClockGate:vlv
7209 * Disabling L3 clock gating- MMIO 940c[25] = 1
7210 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7211 I915_WRITE(GEN7_UCGCTL4,
7212 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
Jesse Barnese3f33d42012-06-14 11:04:50 -07007213
Ville Syrjäläafd58e72014-01-22 21:33:03 +02007214 /*
7215 * BSpec says this must be set, even though
7216 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7217 */
Daniel Vetter6b26c862012-04-24 14:04:12 +02007218 I915_WRITE(CACHE_MODE_1,
7219 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Jesse Barnes79831172012-06-20 10:53:12 -07007220
7221 /*
Ville Syrjäläda2518f2015-01-21 19:38:01 +02007222 * BSpec recommends 8x4 when MSAA is used,
7223 * however in practice 16x4 seems fastest.
7224 *
7225 * Note that PS/WM thread counts depend on the WIZ hashing
7226 * disable bit, which we don't touch here, but it's good
7227 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7228 */
7229 I915_WRITE(GEN7_GT_MODE,
7230 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7231
7232 /*
Ville Syrjälä031994e2014-01-22 21:32:46 +02007233 * WaIncreaseL3CreditsForVLVB0:vlv
7234 * This is the hardware default actually.
7235 */
7236 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7237
7238 /*
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007239 * WaDisableVLVClockGating_VBIIssue:vlv
Jesse Barnes2d809572012-10-25 12:15:44 -07007240 * Disable clock gating on th GCFG unit to prevent a delay
7241 * in the reporting of vblank events.
7242 */
Ville Syrjälä7a0d1ee2014-01-22 21:33:04 +02007243 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007244}
7245
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007246static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
Ville Syrjäläa4565da2014-04-09 13:28:10 +03007247{
Ville Syrjälä232ce332014-04-09 13:28:35 +03007248 /* WaVSRefCountFullforceMissDisable:chv */
7249 /* WaDSRefCountFullforceMissDisable:chv */
7250 I915_WRITE(GEN7_FF_THREAD_MODE,
7251 I915_READ(GEN7_FF_THREAD_MODE) &
7252 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Ville Syrjäläacea6f92014-04-09 13:28:36 +03007253
7254 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7255 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7256 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
Ville Syrjälä08466972014-04-09 13:28:37 +03007257
7258 /* WaDisableCSUnitClockGating:chv */
7259 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7260 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
Ville Syrjäläc6317802014-04-09 13:28:38 +03007261
7262 /* WaDisableSDEUnitClockGating:chv */
7263 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7264 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Ville Syrjälä6d50b062015-05-19 20:32:57 +03007265
7266 /*
Imre Deak450174f2016-05-03 15:54:21 +03007267 * WaProgramL3SqcReg1Default:chv
7268 * See gfxspecs/Related Documents/Performance Guide/
7269 * LSQC Setting Recommendations.
7270 */
7271 gen8_set_l3sqc_credits(dev_priv, 38, 2);
Ville Syrjäläa4565da2014-04-09 13:28:10 +03007272}
7273
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007274static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007275{
Jani Nikula5ce9a6492019-01-18 14:01:20 +02007276 u32 dspclk_gate;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007277
7278 I915_WRITE(RENCLK_GATE_D1, 0);
7279 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7280 GS_UNIT_CLOCK_GATE_DISABLE |
7281 CL_UNIT_CLOCK_GATE_DISABLE);
7282 I915_WRITE(RAMCLK_GATE_D, 0);
7283 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7284 OVRUNIT_CLOCK_GATE_DISABLE |
7285 OVCUNIT_CLOCK_GATE_DISABLE;
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01007286 if (IS_GM45(dev_priv))
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007287 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7288 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
Daniel Vetter4358a372012-10-18 11:49:51 +02007289
7290 /* WaDisableRenderCachePipelinedFlush */
7291 I915_WRITE(CACHE_MODE_0,
7292 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
Ville Syrjäläde1aa622013-06-07 10:47:01 +03007293
Akash Goel4e046322014-04-04 17:14:38 +05307294 /* WaDisable_RenderCache_OperationalFlush:g4x */
7295 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7296
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007297 g4x_disable_trickle_feed(dev_priv);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007298}
7299
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007300static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007301{
Tvrtko Ursulin4f5fd912019-06-11 11:45:48 +01007302 struct intel_uncore *uncore = &dev_priv->uncore;
7303
7304 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7305 intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
7306 intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
7307 intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
7308 intel_uncore_write16(uncore, DEUC, 0);
7309 intel_uncore_write(uncore,
7310 MI_ARB_STATE,
7311 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Akash Goel4e046322014-04-04 17:14:38 +05307312
7313 /* WaDisable_RenderCache_OperationalFlush:gen4 */
Tvrtko Ursulin4f5fd912019-06-11 11:45:48 +01007314 intel_uncore_write(uncore,
7315 CACHE_MODE_0,
7316 _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007317}
7318
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007319static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007320{
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007321 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7322 I965_RCC_CLOCK_GATE_DISABLE |
7323 I965_RCPB_CLOCK_GATE_DISABLE |
7324 I965_ISC_CLOCK_GATE_DISABLE |
7325 I965_FBC_CLOCK_GATE_DISABLE);
7326 I915_WRITE(RENCLK_GATE_D2, 0);
Ville Syrjälä20f94962013-06-07 10:47:02 +03007327 I915_WRITE(MI_ARB_STATE,
7328 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Akash Goel4e046322014-04-04 17:14:38 +05307329
7330 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7331 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007332}
7333
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007334static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007335{
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007336 u32 dstate = I915_READ(D_STATE);
7337
7338 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7339 DSTATE_DOT_CLOCK_GATING;
7340 I915_WRITE(D_STATE, dstate);
Chris Wilson13a86b82012-04-24 14:51:43 +01007341
Ville Syrjälä9b1e14f2016-10-31 22:37:15 +02007342 if (IS_PINEVIEW(dev_priv))
Chris Wilson13a86b82012-04-24 14:51:43 +01007343 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
Daniel Vetter974a3b02012-09-09 11:54:16 +02007344
7345 /* IIR "flip pending" means done if this bit is set */
7346 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
Ville Syrjälä12fabbcb92014-02-25 15:13:38 +02007347
7348 /* interrupts should cause a wake up from C3 */
Ville Syrjälä32992542014-02-25 15:13:39 +02007349 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
Ville Syrjälädbb42742014-02-25 15:13:41 +02007350
7351 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7352 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
Ville Syrjälä10383922014-08-15 01:21:54 +03007353
7354 I915_WRITE(MI_ARB_STATE,
7355 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007356}
7357
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007358static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007359{
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007360 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
Ville Syrjälä54e472a2014-02-25 15:13:40 +02007361
7362 /* interrupts should cause a wake up from C3 */
7363 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7364 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
Ville Syrjälä10383922014-08-15 01:21:54 +03007365
7366 I915_WRITE(MEM_MODE,
7367 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007368}
7369
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007370static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007371{
Ville Syrjälä10383922014-08-15 01:21:54 +03007372 I915_WRITE(MEM_MODE,
7373 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7374 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007375}
7376
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007377void intel_init_clock_gating(struct drm_i915_private *dev_priv)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007378{
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007379 dev_priv->display.init_clock_gating(dev_priv);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007380}
7381
Ville Syrjälä712bf362016-10-31 22:37:23 +02007382void intel_suspend_hw(struct drm_i915_private *dev_priv)
Imre Deak7d708ee2013-04-17 14:04:50 +03007383{
Ville Syrjälä712bf362016-10-31 22:37:23 +02007384 if (HAS_PCH_LPT(dev_priv))
7385 lpt_suspend_hw(dev_priv);
Imre Deak7d708ee2013-04-17 14:04:50 +03007386}
7387
Ville Syrjälä46f16e62016-10-31 22:37:22 +02007388static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
Imre Deakbb400da2016-03-16 13:38:54 +02007389{
Wambui Karugaf8d18d52020-01-07 18:13:30 +03007390 drm_dbg_kms(&dev_priv->drm,
7391 "No clock gating settings or workarounds applied.\n");
Imre Deakbb400da2016-03-16 13:38:54 +02007392}
7393
7394/**
7395 * intel_init_clock_gating_hooks - setup the clock gating hooks
7396 * @dev_priv: device private
7397 *
7398 * Setup the hooks that configure which clocks of a given platform can be
7399 * gated and also apply various GT and display specific workarounds for these
7400 * platforms. Note that some GT specific workarounds are applied separately
7401 * when GPU contexts or batchbuffers start their execution.
7402 */
7403void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7404{
Lucas De Marchi13e53c52019-08-17 02:38:42 -07007405 if (IS_GEN(dev_priv, 12))
Michel Thierry5d869232019-08-23 01:20:34 -07007406 dev_priv->display.init_clock_gating = tgl_init_clock_gating;
Lucas De Marchi13e53c52019-08-17 02:38:42 -07007407 else if (IS_GEN(dev_priv, 11))
Oscar Mateod65dc3e2018-05-08 14:29:24 -07007408 dev_priv->display.init_clock_gating = icl_init_clock_gating;
Oscar Mateocc38cae2018-05-08 14:29:23 -07007409 else if (IS_CANNONLAKE(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007410 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07007411 else if (IS_COFFEELAKE(dev_priv))
7412 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07007413 else if (IS_SKYLAKE(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007414 dev_priv->display.init_clock_gating = skl_init_clock_gating;
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07007415 else if (IS_KABYLAKE(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007416 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
Ander Conselvan de Oliveira9fb50262017-01-26 11:16:58 +02007417 else if (IS_BROXTON(dev_priv))
Imre Deakbb400da2016-03-16 13:38:54 +02007418 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
Ander Conselvan de Oliveira9fb50262017-01-26 11:16:58 +02007419 else if (IS_GEMINILAKE(dev_priv))
7420 dev_priv->display.init_clock_gating = glk_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007421 else if (IS_BROADWELL(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007422 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007423 else if (IS_CHERRYVIEW(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007424 dev_priv->display.init_clock_gating = chv_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007425 else if (IS_HASWELL(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007426 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007427 else if (IS_IVYBRIDGE(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007428 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007429 else if (IS_VALLEYVIEW(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007430 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007431 else if (IS_GEN(dev_priv, 6))
Imre Deakbb400da2016-03-16 13:38:54 +02007432 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007433 else if (IS_GEN(dev_priv, 5))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007434 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007435 else if (IS_G4X(dev_priv))
7436 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
Jani Nikulac0f86832016-12-07 12:13:04 +02007437 else if (IS_I965GM(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007438 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
Jani Nikulac0f86832016-12-07 12:13:04 +02007439 else if (IS_I965G(dev_priv))
Rodrigo Vivi91200c02017-08-28 22:20:26 -07007440 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007441 else if (IS_GEN(dev_priv, 3))
Imre Deakbb400da2016-03-16 13:38:54 +02007442 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7443 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7444 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007445 else if (IS_GEN(dev_priv, 2))
Imre Deakbb400da2016-03-16 13:38:54 +02007446 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7447 else {
7448 MISSING_CASE(INTEL_DEVID(dev_priv));
7449 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7450 }
7451}
7452
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007453/* Set up chip specific power management-related functions */
Ville Syrjälä62d75df2016-10-31 22:37:25 +02007454void intel_init_pm(struct drm_i915_private *dev_priv)
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007455{
Daniel Vetterc921aba2012-04-26 23:28:17 +02007456 /* For cxsr */
Ville Syrjälä9b1e14f2016-10-31 22:37:15 +02007457 if (IS_PINEVIEW(dev_priv))
Lucas De Marchi1d218222019-12-24 00:40:04 -08007458 pnv_get_mem_freq(dev_priv);
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007459 else if (IS_GEN(dev_priv, 5))
Lucas De Marchi9eae5e22019-12-24 00:40:09 -08007460 ilk_get_mem_freq(dev_priv);
Daniel Vetterc921aba2012-04-26 23:28:17 +02007461
James Ausmusb068a862019-10-09 10:23:14 -07007462 if (intel_has_sagv(dev_priv))
7463 skl_setup_sagv_block_time(dev_priv);
7464
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007465 /* For FIFO watermark updates */
Ville Syrjälä62d75df2016-10-31 22:37:25 +02007466 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjäläbb726512016-10-31 22:37:24 +02007467 skl_setup_wm_latency(dev_priv);
Matt Roper98d39492016-05-12 07:06:03 -07007468 dev_priv->display.compute_global_watermarks = skl_compute_wm;
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01007469 } else if (HAS_PCH_SPLIT(dev_priv)) {
Ville Syrjäläbb726512016-10-31 22:37:24 +02007470 ilk_setup_wm_latency(dev_priv);
Ville Syrjälä53615a52013-08-01 16:18:50 +03007471
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007472 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
Ville Syrjäläbd602542014-01-07 16:14:10 +02007473 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007474 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
Ville Syrjäläbd602542014-01-07 16:14:10 +02007475 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
Matt Roper86c8bbb2015-09-24 15:53:16 -07007476 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
Matt Ropered4a6a72016-02-23 17:20:13 -08007477 dev_priv->display.compute_intermediate_wm =
7478 ilk_compute_intermediate_wm;
7479 dev_priv->display.initial_watermarks =
7480 ilk_initial_watermarks;
7481 dev_priv->display.optimize_watermarks =
7482 ilk_optimize_watermarks;
Ville Syrjäläbd602542014-01-07 16:14:10 +02007483 } else {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03007484 drm_dbg_kms(&dev_priv->drm,
7485 "Failed to read display plane latency. "
7486 "Disable CxSR\n");
Ville Syrjäläbd602542014-01-07 16:14:10 +02007487 }
Ville Syrjälä6b6b3ee2016-11-28 19:37:07 +02007488 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Ville Syrjäläbb726512016-10-31 22:37:24 +02007489 vlv_setup_wm_latency(dev_priv);
Ville Syrjäläff32c542017-03-02 19:14:57 +02007490 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
Ville Syrjälä4841da52017-03-02 19:14:59 +02007491 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
Ville Syrjäläff32c542017-03-02 19:14:57 +02007492 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
Ville Syrjälä4841da52017-03-02 19:14:59 +02007493 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
Ville Syrjäläff32c542017-03-02 19:14:57 +02007494 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03007495 } else if (IS_G4X(dev_priv)) {
7496 g4x_setup_wm_latency(dev_priv);
7497 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
7498 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
7499 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
7500 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
Ville Syrjälä9b1e14f2016-10-31 22:37:15 +02007501 } else if (IS_PINEVIEW(dev_priv)) {
Tvrtko Ursulin86d35d42019-03-26 07:40:54 +00007502 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007503 dev_priv->is_ddr3,
7504 dev_priv->fsb_freq,
7505 dev_priv->mem_freq)) {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03007506 drm_info(&dev_priv->drm,
7507 "failed to find known CxSR latency "
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007508 "(found ddr%s fsb freq %d, mem freq %d), "
7509 "disabling CxSR\n",
7510 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7511 dev_priv->fsb_freq, dev_priv->mem_freq);
7512 /* Disable CxSR and never update its watermark again */
Imre Deak5209b1f2014-07-01 12:36:17 +03007513 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007514 dev_priv->display.update_wm = NULL;
7515 } else
Lucas De Marchi1d218222019-12-24 00:40:04 -08007516 dev_priv->display.update_wm = pnv_update_wm;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007517 } else if (IS_GEN(dev_priv, 4)) {
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007518 dev_priv->display.update_wm = i965_update_wm;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007519 } else if (IS_GEN(dev_priv, 3)) {
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007520 dev_priv->display.update_wm = i9xx_update_wm;
7521 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Lucas De Marchicf819ef2018-12-12 10:10:43 -08007522 } else if (IS_GEN(dev_priv, 2)) {
Jani Nikula24977872019-09-11 12:26:08 +03007523 if (INTEL_NUM_PIPES(dev_priv) == 1) {
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007524 dev_priv->display.update_wm = i845_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007525 dev_priv->display.get_fifo_size = i845_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007526 } else {
7527 dev_priv->display.update_wm = i9xx_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007528 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007529 }
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007530 } else {
Wambui Karugaf8d18d52020-01-07 18:13:30 +03007531 drm_err(&dev_priv->drm,
7532 "unexpected fall-through in %s\n", __func__);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007533 }
7534}
7535
Tvrtko Ursulin192aa182016-12-01 14:16:45 +00007536void intel_pm_setup(struct drm_i915_private *dev_priv)
Chris Wilson907b28c2013-07-19 20:36:52 +01007537{
Sagar Arun Kamblead1443f2017-10-10 22:30:04 +01007538 dev_priv->runtime_pm.suspended = false;
7539 atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
Chris Wilson907b28c2013-07-19 20:36:52 +01007540}