blob: 93fce737402c9ac5b304fde1d3cd79c0970b786a [file] [log] [blame]
Eugeni Dodonov85208be2012-04-16 22:20:34 -03001/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -030028#include <linux/cpufreq.h>
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -070029#include <drm/drm_plane_helper.h>
Eugeni Dodonov85208be2012-04-16 22:20:34 -030030#include "i915_drv.h"
31#include "intel_drv.h"
Daniel Vettereb48eb02012-04-26 23:28:12 +020032#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
Eugeni Dodonov85208be2012-04-16 22:20:34 -030034
Ben Widawskydc39fff2013-10-18 12:32:07 -070035/**
Jani Nikula18afd442016-01-18 09:19:48 +020036 * DOC: RC6
37 *
Ben Widawskydc39fff2013-10-18 12:32:07 -070038 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
Mika Kuoppalab033bb62016-06-07 17:19:04 +030058static void gen9_init_clock_gating(struct drm_device *dev)
59{
Mika Kuoppala11b28342016-06-07 17:19:04 +030060 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppalab033bb62016-06-07 17:19:04 +030061
62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
Mika Kuoppala590e8ff2016-06-07 17:19:13 +030068
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
Mika Kuoppala0f78dee2016-06-07 17:19:16 +030072
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
Mika Kuoppala303d4ea2016-06-07 17:19:17 +030074 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
Mika Kuoppalad1b4eef2016-06-07 17:19:19 +030078
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
Mika Kuoppalab033bb62016-06-07 17:19:04 +030082}
83
Imre Deaka82abe42015-03-27 14:00:04 +020084static void bxt_init_clock_gating(struct drm_device *dev)
85{
Chris Wilsonfac5e232016-07-04 11:34:36 +010086 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak32608ca2015-03-11 11:10:27 +020087
Mika Kuoppalab033bb62016-06-07 17:19:04 +030088 gen9_init_clock_gating(dev);
Daniel Vetterdc00b6a2016-05-19 09:14:20 +020089
Nick Hoatha7546152015-06-29 14:07:32 +010090 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
Imre Deak32608ca2015-03-11 11:10:27 +020094 /*
95 * FIXME:
Ben Widawsky868434c2015-03-11 10:49:32 +020096 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
Imre Deak32608ca2015-03-11 11:10:27 +020097 */
Imre Deak32608ca2015-03-11 11:10:27 +020098 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
Ben Widawsky868434c2015-03-11 10:49:32 +020099 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
Imre Deakd965e7ac2015-12-01 10:23:52 +0200100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
Imre Deaka82abe42015-03-27 14:00:04 +0200108}
109
Daniel Vetterc921aba2012-04-26 23:28:17 +0200110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100112 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetterc921aba2012-04-26 23:28:17 +0200113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100151 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetterc921aba2012-04-26 23:28:17 +0200152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
Daniel Vetter20e4d402012-08-08 23:35:39 +0200177 dev_priv->ips.r_t = dev_priv->mem_freq;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200209 dev_priv->ips.c_m = 0;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200211 dev_priv->ips.c_m = 1;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200212 } else {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200213 dev_priv->ips.c_m = 2;
Daniel Vetterc921aba2012-04-26 23:28:17 +0200214 }
215}
216
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
Daniel Vetter63c62272012-04-21 23:17:55 +0200255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
Ville Syrjäläf4998962015-03-10 17:02:21 +0200317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
Imre Deak5209b1f2014-07-01 12:36:17 +0300320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300321{
Chris Wilson91c8a322016-07-05 10:40:23 +0100322 struct drm_device *dev = &dev_priv->drm;
Imre Deak5209b1f2014-07-01 12:36:17 +0300323 u32 val;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300324
Wayne Boyer666a4532015-12-09 12:29:35 -0800325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Imre Deak5209b1f2014-07-01 12:36:17 +0300326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300327 POSTING_READ(FW_BLC_SELF_VLV);
Ville Syrjälä852eb002015-06-24 22:00:07 +0300328 dev_priv->wm.vlv.cxsr = enable;
Imre Deak5209b1f2014-07-01 12:36:17 +0300329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300331 POSTING_READ(FW_BLC_SELF);
Imre Deak5209b1f2014-07-01 12:36:17 +0300332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300336 POSTING_READ(DSPFW3);
Imre Deak5209b1f2014-07-01 12:36:17 +0300337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300341 POSTING_READ(FW_BLC_SELF);
Imre Deak5209b1f2014-07-01 12:36:17 +0300342 } else if (IS_I915GM(dev)) {
Ville Syrjäläacb91352016-07-29 17:57:02 +0300343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
Imre Deak5209b1f2014-07-01 12:36:17 +0300348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
Ville Syrjäläa7a6c492015-06-24 22:00:01 +0300351 POSTING_READ(INSTPM);
Imre Deak5209b1f2014-07-01 12:36:17 +0300352 } else {
353 return;
354 }
355
356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300358}
359
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200360
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
Chris Wilson5aef6002014-09-03 11:56:07 +0100375static const int pessimal_latency_ns = 5000;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300376
Ville Syrjäläb5004722015-03-05 21:19:47 +0200377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100383 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläb5004722015-03-05 21:19:47 +0200384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
Eugeni Dodonov1fa61102012-04-18 15:29:26 -0300432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300433{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100434 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
Daniel Vetterfeb56b92013-12-14 20:38:30 -0200448static int i830_get_fifo_size(struct drm_device *dev, int plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300449{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100450 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
Eugeni Dodonov1fa61102012-04-18 15:29:26 -0300465static int i845_get_fifo_size(struct drm_device *dev, int plane)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300466{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100467 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300495};
496static const struct intel_watermark_params pineview_cursor_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300509};
510static const struct intel_watermark_params g4x_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300523};
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300524static const struct intel_watermark_params i965_cursor_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300530};
531static const struct intel_watermark_params i945_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300537};
538static const struct intel_watermark_params i915_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300544};
Ville Syrjälä9d539102014-08-15 01:21:53 +0300545static const struct intel_watermark_params i830_a_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300551};
Ville Syrjälä9d539102014-08-15 01:21:53 +0300552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
Daniel Vetterfeb56b92013-12-14 20:38:30 -0200559static const struct intel_watermark_params i845_wm_info = {
Ville Syrjäläe0f02732014-06-05 19:15:50 +0300560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300565};
566
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
Ville Syrjäläac484962016-01-20 21:05:26 +0200571 * @cpp: bytes per pixel
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
Ville Syrjäläac484962016-01-20 21:05:26 +0200587 int fifo_size, int cpp,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
Ville Syrjäläac484962016-01-20 21:05:26 +0200598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
Ville Syrjäläd6feb192014-09-05 21:54:13 +0300613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
Damien Lespiau70e1e0e2014-05-13 23:32:24 +0100631 for_each_crtc(dev, crtc) {
Chris Wilson3490ea52013-01-07 10:11:40 +0000632 if (intel_crtc_active(crtc)) {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300642static void pineview_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300643{
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300644 struct drm_device *dev = unused_crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100645 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Imre Deak5209b1f2014-07-01 12:36:17 +0300655 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Ville Syrjäläac484962016-01-20 21:05:26 +0200662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300663 int clock = adjusted_mode->crtc_clock;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
Ville Syrjäläac484962016-01-20 21:05:26 +0200668 cpp, latency->display_sr);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200671 reg |= FW_WM(wm, SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
Ville Syrjäläac484962016-01-20 21:05:26 +0200678 cpp, latency->cursor_sr);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200681 reg |= FW_WM(wm, CURSOR_SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
Ville Syrjäläac484962016-01-20 21:05:26 +0200687 cpp, latency->display_hpll_disable);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200690 reg |= FW_WM(wm, HPLL_SR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
Ville Syrjäläac484962016-01-20 21:05:26 +0200696 cpp, latency->cursor_hpll_disable);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
Ville Syrjäläf4998962015-03-10 17:02:21 +0200699 reg |= FW_WM(wm, HPLL_CURSOR);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
Imre Deak5209b1f2014-07-01 12:36:17 +0300703 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300704 } else {
Imre Deak5209b1f2014-07-01 12:36:17 +0300705 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
Ville Syrjälä4fe85902013-09-04 18:25:22 +0300719 const struct drm_display_mode *adjusted_mode;
Ville Syrjäläac484962016-01-20 21:05:26 +0200720 int htotal, hdisplay, clock, cpp;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
Chris Wilson3490ea52013-01-07 10:11:40 +0000725 if (!intel_crtc_active(crtc)) {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100732 clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -0800733 htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
Ville Syrjäläac484962016-01-20 21:05:26 +0200735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300736
737 /* Use the small buffer method to calculate plane watermark */
Ville Syrjäläac484962016-01-20 21:05:26 +0200738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
Ville Syrjälä922044c2014-02-14 14:18:57 +0200748 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
Ville Syrjäläac484962016-01-20 21:05:26 +0200750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
Ville Syrjälä4fe85902013-09-04 18:25:22 +0300805 const struct drm_display_mode *adjusted_mode;
Ville Syrjäläac484962016-01-20 21:05:26 +0200806 int hdisplay, htotal, cpp, clock;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100819 clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -0800820 htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
Ville Syrjäläac484962016-01-20 21:05:26 +0200822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300823
Ville Syrjälä922044c2014-02-14 14:18:57 +0200824 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300825 line_count = (latency_ns / line_time_us + 1000) / 1000;
Ville Syrjäläac484962016-01-20 21:05:26 +0200826 line_size = hdisplay * cpp;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300827
828 /* Use the minimum of the small and large buffer method for primary */
Ville Syrjäläac484962016-01-20 21:05:26 +0200829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
Ville Syrjäläac484962016-01-20 21:05:26 +0200836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
Ville Syrjälä15665972015-03-10 16:16:28 +0200845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
Ville Syrjälä0018fda2015-03-05 21:19:45 +0200848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
Ville Syrjäläae801522015-03-05 21:19:49 +0200860 I915_WRITE(DSPFW1,
Ville Syrjälä15665972015-03-10 16:16:28 +0200861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
Ville Syrjäläae801522015-03-05 21:19:49 +0200865 I915_WRITE(DSPFW2,
Ville Syrjälä15665972015-03-10 16:16:28 +0200866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
Ville Syrjäläae801522015-03-05 21:19:49 +0200869 I915_WRITE(DSPFW3,
Ville Syrjälä15665972015-03-10 16:16:28 +0200870 FW_WM(wm->sr.cursor, CURSOR_SR));
Ville Syrjäläae801522015-03-05 21:19:49 +0200871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
Ville Syrjälä15665972015-03-10 16:16:28 +0200874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
Ville Syrjäläae801522015-03-05 21:19:49 +0200876 I915_WRITE(DSPFW8_CHV,
Ville Syrjälä15665972015-03-10 16:16:28 +0200877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
Ville Syrjäläae801522015-03-05 21:19:49 +0200879 I915_WRITE(DSPFW9_CHV,
Ville Syrjälä15665972015-03-10 16:16:28 +0200880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
Ville Syrjäläae801522015-03-05 21:19:49 +0200882 I915_WRITE(DSPHOWM,
Ville Syrjälä15665972015-03-10 16:16:28 +0200883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
Ville Syrjäläae801522015-03-05 21:19:49 +0200893 } else {
894 I915_WRITE(DSPFW7,
Ville Syrjälä15665972015-03-10 16:16:28 +0200895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
Ville Syrjäläae801522015-03-05 21:19:49 +0200897 I915_WRITE(DSPHOWM,
Ville Syrjälä15665972015-03-10 16:16:28 +0200898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
Ville Syrjäläae801522015-03-05 21:19:49 +0200905 }
906
Ville Syrjälä2cb389b2015-06-24 22:00:10 +0300907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
Ville Syrjäläae801522015-03-05 21:19:49 +0200913 POSTING_READ(DSPFW1);
Ville Syrjälä0018fda2015-03-05 21:19:45 +0200914}
915
Ville Syrjälä15665972015-03-10 16:16:28 +0200916#undef FW_WM_VLV
917
Ville Syrjälä6eb1a682015-06-24 22:00:03 +0300918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
Ville Syrjälä6eb1a682015-06-24 22:00:03 +0300922};
923
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
Ville Syrjäläac484962016-01-20 21:05:26 +0200928 unsigned int cpp,
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
Ville Syrjäläac484962016-01-20 21:05:26 +0200934 ret = (ret + 1) * horiz_pixels * cpp;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100942 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
Ville Syrjälä58590c12015-09-08 21:05:12 +0300947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
Ville Syrjälä58590c12015-09-08 21:05:12 +0300952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjäläac484962016-01-20 21:05:26 +0200963 int clock, htotal, cpp, width, wm;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300968 if (!state->base.visible)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300969 return 0;
970
Ville Syrjäläac484962016-01-20 21:05:26 +0200971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
Ville Syrjäläac484962016-01-20 21:05:26 +0200987 wm = vlv_wm_method2(clock, htotal, width, cpp,
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +0300994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001010 if (state->base.visible) {
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001026 if (!state->base.visible) {
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
Ville Syrjälä26e1fe42015-06-24 22:00:06 +03001095static void vlv_compute_wm(struct intel_crtc *crtc)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
Ville Syrjälä852eb002015-06-24 22:00:07 +03001105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
Ville Syrjälä58590c12015-09-08 21:05:12 +03001106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001107
1108 wm_state->num_active_planes = 0;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001109
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001110 vlv_compute_fifo(crtc);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001126 if (!state->base.visible)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
Thomas Daniel5a37ed02015-10-23 14:55:38 +01001167 wm_state->wm[level].cursor;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
Ville Syrjälä58590c12015-09-08 21:05:12 +03001186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
Ville Syrjälä58590c12015-09-08 21:05:12 +03001290 wm->level = to_i915(dev)->wm.max_level;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
Ville Syrjälä6f9c7842015-06-24 22:00:08 +03001309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001333 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
Ville Syrjälä26e1fe42015-06-24 22:00:06 +03001338 vlv_compute_wm(intel_crtc);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001339 vlv_merge_wm(dev, &wm);
1340
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001344 return;
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001345 }
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
Ville Syrjälä852eb002015-06-24 22:00:07 +03001355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001356 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001357
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03001358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
Ville Syrjälä852eb002015-06-24 22:00:07 +03001369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001370 intel_set_memory_cxsr(dev_priv, true);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
Ville Syrjälä3c2777f2014-06-26 17:03:06 +03001381}
1382
Ville Syrjäläae801522015-03-05 21:19:49 +02001383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001385static void g4x_update_wm(struct drm_crtc *crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001386{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001387 struct drm_device *dev = crtc->dev;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001388 static const int sr_latency_ns = 12000;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001389 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
Imre Deak98584252014-06-13 14:54:20 +03001393 bool cxsr_enabled;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001394
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001395 if (g4x_compute_wm0(dev, PIPE_A,
Chris Wilson5aef6002014-09-03 11:56:07 +01001396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001398 &planea_wm, &cursora_wm))
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001399 enabled |= 1 << PIPE_A;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001400
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001401 if (g4x_compute_wm0(dev, PIPE_B,
Chris Wilson5aef6002014-09-03 11:56:07 +01001402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001404 &planeb_wm, &cursorb_wm))
Ville Syrjälä51cea1f2013-03-21 13:10:44 +02001405 enabled |= 1 << PIPE_B;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001406
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
Chris Wilson52bd02d2012-12-07 10:43:24 +00001412 &plane_sr, &cursor_sr)) {
Imre Deak98584252014-06-13 14:54:20 +03001413 cxsr_enabled = true;
Chris Wilson52bd02d2012-12-07 10:43:24 +00001414 } else {
Imre Deak98584252014-06-13 14:54:20 +03001415 cxsr_enabled = false;
Imre Deak5209b1f2014-07-01 12:36:17 +03001416 intel_set_memory_cxsr(dev_priv, false);
Chris Wilson52bd02d2012-12-07 10:43:24 +00001417 plane_sr = cursor_sr = 0;
1418 }
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001419
Ville Syrjäläa5043452014-06-28 02:04:18 +03001420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
Ville Syrjäläf4998962015-03-10 17:02:21 +02001427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001431 I915_WRITE(DSPFW2,
Chris Wilson8c919b22012-12-04 16:33:19 +00001432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
Ville Syrjäläf4998962015-03-10 17:02:21 +02001433 FW_WM(cursora_wm, CURSORA));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
Chris Wilson8c919b22012-12-04 16:33:19 +00001436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
Ville Syrjäläf4998962015-03-10 17:02:21 +02001437 FW_WM(cursor_sr, CURSOR_SR));
Imre Deak98584252014-06-13 14:54:20 +03001438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001441}
1442
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001443static void i965_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001444{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001445 struct drm_device *dev = unused_crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001446 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
Imre Deak98584252014-06-13 14:54:20 +03001450 bool cxsr_enabled;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
Ville Syrjälä124abe02015-09-08 13:40:45 +03001457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001458 int clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -08001459 int htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
Ville Syrjäläac484962016-01-20 21:05:26 +02001461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001462 unsigned long line_time_us;
1463 int entries;
1464
Ville Syrjälä922044c2014-02-14 14:18:57 +02001465 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Ville Syrjäläac484962016-01-20 21:05:26 +02001469 cpp * hdisplay;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Ville Syrjäläac484962016-01-20 21:05:26 +02001479 cpp * crtc->cursor->state->crtc_w;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
Imre Deak98584252014-06-13 14:54:20 +03001491 cxsr_enabled = true;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001492 } else {
Imre Deak98584252014-06-13 14:54:20 +03001493 cxsr_enabled = false;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001494 /* Turn off self refresh if both pipes are enabled */
Imre Deak5209b1f2014-07-01 12:36:17 +03001495 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
Ville Syrjäläf4998962015-03-10 17:02:21 +02001502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001508 /* update cursor SR watermark */
Ville Syrjäläf4998962015-03-10 17:02:21 +02001509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
Imre Deak98584252014-06-13 14:54:20 +03001510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001513}
1514
Ville Syrjäläf4998962015-03-10 17:02:21 +02001515#undef FW_WM
1516
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001518{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001519 struct drm_device *dev = unused_crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001520 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
Ville Syrjälä9d539102014-08-15 01:21:53 +03001534 wm_info = &i830_a_wm_info;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
Chris Wilson3490ea52013-01-07 10:11:40 +00001538 if (intel_crtc_active(crtc)) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01001539 const struct drm_display_mode *adjusted_mode;
Ville Syrjäläac484962016-01-20 21:05:26 +02001540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001546 wm_info, fifo_size, cpp,
Chris Wilson5aef6002014-09-03 11:56:07 +01001547 pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001548 enabled = crtc;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001549 } else {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001550 planea_wm = fifo_size - wm_info->guard_size;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
Chris Wilson3490ea52013-01-07 10:11:40 +00001560 if (intel_crtc_active(crtc)) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01001561 const struct drm_display_mode *adjusted_mode;
Ville Syrjäläac484962016-01-20 21:05:26 +02001562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Chris Wilsonb9e0bda2012-10-22 12:32:15 +01001568 wm_info, fifo_size, cpp,
Chris Wilson5aef6002014-09-03 11:56:07 +01001569 pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001574 } else {
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001575 planeb_wm = fifo_size - wm_info->guard_size;
Ville Syrjälä9d539102014-08-15 01:21:53 +03001576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001582 if (IS_I915GM(dev) && enabled) {
Matt Roper2ff8fde2014-07-08 07:50:07 -07001583 struct drm_i915_gem_object *obj;
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001584
Matt Roper59bea882015-02-27 10:12:01 -08001585 obj = intel_fb_obj(enabled->primary->state->fb);
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001586
1587 /* self-refresh seems busted with untiled */
Chris Wilson3e510a82016-08-05 10:14:23 +01001588 if (!i915_gem_object_is_tiled(obj))
Daniel Vetter2ab1bc92014-04-07 08:54:21 +02001589 enabled = NULL;
1590 }
1591
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
Imre Deak5209b1f2014-07-01 12:36:17 +03001598 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
Ville Syrjälä124abe02015-09-08 13:40:45 +03001604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001605 int clock = adjusted_mode->crtc_clock;
Jesse Barnesfec8cba2013-11-27 11:10:26 -08001606 int htotal = adjusted_mode->crtc_htotal;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
Ville Syrjäläac484962016-01-20 21:05:26 +02001608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001609 unsigned long line_time_us;
1610 int entries;
1611
Ville Syrjälä2d1b5052016-07-29 17:57:01 +03001612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
Ville Syrjälä922044c2014-02-14 14:18:57 +02001615 line_time_us = max(htotal * 1000 / clock, 1);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Ville Syrjäläac484962016-01-20 21:05:26 +02001619 cpp * hdisplay;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
Ville Syrjäläacb91352016-07-29 17:57:02 +03001629 else
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
Imre Deak5209b1f2014-07-01 12:36:17 +03001646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001648}
1649
Daniel Vetterfeb56b92013-12-14 20:38:30 -02001650static void i845_update_wm(struct drm_crtc *unused_crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001651{
Ville Syrjälä46ba6142013-09-10 11:40:40 +03001652 struct drm_device *dev = unused_crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001653 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001654 struct drm_crtc *crtc;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001655 const struct drm_display_mode *adjusted_mode;
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +01001664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
Daniel Vetterfeb56b92013-12-14 20:38:30 -02001665 &i845_wm_info,
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001666 dev_priv->display.get_fifo_size(dev, 0),
Chris Wilson5aef6002014-09-03 11:56:07 +01001667 4, pessimal_latency_ns);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03001668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03001676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001677{
Chris Wilsonfd4daa92013-08-27 17:04:17 +01001678 uint32_t pixel_rate;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001679
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03001680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03001685 if (pipe_config->pch_pfit.enabled) {
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03001687 uint32_t pfit_size = pipe_config->pch_pfit.size;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001688
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03001689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
1691
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
Matt Roper15126882015-12-03 11:37:40 -08001699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
Ville Syrjälä37126462013-08-01 16:18:55 +03001709/* latency must be in 0.1us units. */
Ville Syrjäläac484962016-01-20 21:05:26 +02001710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001711{
1712 uint64_t ret;
1713
Ville Syrjälä3312ba62013-08-01 16:18:53 +03001714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
Ville Syrjäläac484962016-01-20 21:05:26 +02001717 ret = (uint64_t) pixel_rate * cpp * latency;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
Ville Syrjälä37126462013-08-01 16:18:55 +03001723/* latency must be in 0.1us units. */
Ville Syrjälä23297042013-07-05 11:57:17 +03001724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
Ville Syrjäläac484962016-01-20 21:05:26 +02001725 uint32_t horiz_pixels, uint8_t cpp,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
Ville Syrjälä3312ba62013-08-01 16:18:53 +03001730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
Matt Roper15126882015-12-03 11:37:40 -08001732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
Ville Syrjälä3312ba62013-08-01 16:18:53 +03001734
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
Ville Syrjäläac484962016-01-20 21:05:26 +02001736 ret = (ret + 1) * horiz_pixels * cpp;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
Ville Syrjälä23297042013-07-05 11:57:17 +03001741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
Ville Syrjäläac484962016-01-20 21:05:26 +02001742 uint8_t cpp)
Paulo Zanonicca32e92013-05-31 11:45:06 -03001743{
Matt Roper15126882015-12-03 11:37:40 -08001744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
Ville Syrjäläac484962016-01-20 21:05:26 +02001750 if (WARN_ON(!cpp))
Matt Roper15126882015-12-03 11:37:40 -08001751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
Ville Syrjäläac484962016-01-20 21:05:26 +02001755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
Paulo Zanonicca32e92013-05-31 11:45:06 -03001756}
1757
Imre Deak820c1982013-12-17 14:46:36 +02001758struct ilk_wm_maximums {
Paulo Zanonicca32e92013-05-31 11:45:06 -03001759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
Ville Syrjälä37126462013-08-01 16:18:55 +03001765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
Matt Roper7221fc32015-09-24 15:53:08 -07001769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
Matt Roper43d59ed2015-09-24 15:53:07 -07001770 const struct intel_plane_state *pstate,
Paulo Zanonicca32e92013-05-31 11:45:06 -03001771 uint32_t mem_value,
1772 bool is_lp)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001773{
Ville Syrjäläac484962016-01-20 21:05:26 +02001774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
Paulo Zanonicca32e92013-05-31 11:45:06 -03001776 uint32_t method1, method2;
1777
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001778 if (!cstate->base.active || !pstate->base.visible)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001779 return 0;
1780
Ville Syrjäläac484962016-01-20 21:05:26 +02001781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
Paulo Zanonicca32e92013-05-31 11:45:06 -03001782
1783 if (!is_lp)
1784 return method1;
1785
Matt Roper7221fc32015-09-24 15:53:08 -07001786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001788 drm_rect_width(&pstate->base.dst),
Ville Syrjäläac484962016-01-20 21:05:26 +02001789 cpp, mem_value);
Paulo Zanonicca32e92013-05-31 11:45:06 -03001790
1791 return min(method1, method2);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001792}
1793
Ville Syrjälä37126462013-08-01 16:18:55 +03001794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
Matt Roper7221fc32015-09-24 15:53:08 -07001798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
Matt Roper43d59ed2015-09-24 15:53:07 -07001799 const struct intel_plane_state *pstate,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001800 uint32_t mem_value)
1801{
Ville Syrjäläac484962016-01-20 21:05:26 +02001802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001804 uint32_t method1, method2;
1805
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001806 if (!cstate->base.active || !pstate->base.visible)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001807 return 0;
1808
Ville Syrjäläac484962016-01-20 21:05:26 +02001809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
Matt Roper7221fc32015-09-24 15:53:08 -07001810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001812 drm_rect_width(&pstate->base.dst),
Ville Syrjäläac484962016-01-20 21:05:26 +02001813 cpp, mem_value);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001814 return min(method1, method2);
1815}
1816
Ville Syrjälä37126462013-08-01 16:18:55 +03001817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
Matt Roper7221fc32015-09-24 15:53:08 -07001821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
Matt Roper43d59ed2015-09-24 15:53:07 -07001822 const struct intel_plane_state *pstate,
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001823 uint32_t mem_value)
1824{
Matt Roperb2435692016-02-02 22:06:51 -08001825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
Matt Roper43d59ed2015-09-24 15:53:07 -07001832
Matt Roperb2435692016-02-02 22:06:51 -08001833 if (!cstate->base.active)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001834 return 0;
1835
Matt Roper7221fc32015-09-24 15:53:08 -07001836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
Matt Roperb2435692016-02-02 22:06:51 -08001838 width, cpp, mem_value);
Paulo Zanoni801bcff2013-05-31 10:08:35 -03001839}
1840
Paulo Zanonicca32e92013-05-31 11:45:06 -03001841/* Only for WM_LP. */
Matt Roper7221fc32015-09-24 15:53:08 -07001842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
Matt Roper43d59ed2015-09-24 15:53:07 -07001843 const struct intel_plane_state *pstate,
Ville Syrjälä1fda9882013-07-05 11:57:19 +03001844 uint32_t pri_val)
Paulo Zanonicca32e92013-05-31 11:45:06 -03001845{
Ville Syrjäläac484962016-01-20 21:05:26 +02001846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
Matt Roper43d59ed2015-09-24 15:53:07 -07001848
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001849 if (!cstate->base.active || !pstate->base.visible)
Paulo Zanonicca32e92013-05-31 11:45:06 -03001850 return 0;
1851
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
Paulo Zanonicca32e92013-05-31 11:45:06 -03001853}
1854
Ville Syrjälä158ae642013-08-07 13:28:19 +03001855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
Ville Syrjälä416f4722013-11-02 21:07:46 -07001857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001860 return 768;
1861 else
1862 return 512;
1863}
1864
Ville Syrjälä4e975082014-03-07 18:32:11 +02001865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
Ville Syrjälä158ae642013-08-07 13:28:19 +03001899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
Ville Syrjälä240264f2013-08-07 13:29:12 +03001902 const struct intel_wm_config *config,
Ville Syrjälä158ae642013-08-07 13:28:19 +03001903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
Ville Syrjälä158ae642013-08-07 13:28:19 +03001907
1908 /* if sprites aren't enabled, sprites get nothing */
Ville Syrjälä240264f2013-08-07 13:29:12 +03001909 if (is_sprite && !config->sprites_enabled)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
Ville Syrjälä240264f2013-08-07 13:29:12 +03001913 if (level == 0 || config->num_pipes_active > 1) {
Ville Syrjälä158ae642013-08-07 13:28:19 +03001914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
Ville Syrjälä240264f2013-08-07 13:29:12 +03001925 if (config->sprites_enabled) {
Ville Syrjälä158ae642013-08-07 13:28:19 +03001926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
Ville Syrjälä4e975082014-03-07 18:32:11 +02001937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
Ville Syrjälä158ae642013-08-07 13:28:19 +03001938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
Ville Syrjälä240264f2013-08-07 13:29:12 +03001942 int level,
1943 const struct intel_wm_config *config)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
Ville Syrjälä240264f2013-08-07 13:29:12 +03001946 if (level > 0 && config->num_pipes_active > 1)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
Ville Syrjälä4e975082014-03-07 18:32:11 +02001950 return ilk_cursor_wm_reg_max(dev, level);
Ville Syrjälä158ae642013-08-07 13:28:19 +03001951}
1952
Damien Lespiaud34ff9c2014-01-06 19:17:23 +00001953static void ilk_compute_wm_maximums(const struct drm_device *dev,
Ville Syrjälä34982fe2013-10-09 19:18:09 +03001954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
Imre Deak820c1982013-12-17 14:46:36 +02001957 struct ilk_wm_maximums *max)
Ville Syrjälä158ae642013-08-07 13:28:19 +03001958{
Ville Syrjälä240264f2013-08-07 13:29:12 +03001959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
Ville Syrjälä4e975082014-03-07 18:32:11 +02001962 max->fbc = ilk_fbc_wm_reg_max(dev);
Ville Syrjälä158ae642013-08-07 13:28:19 +03001963}
1964
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03001965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
Ville Syrjäläd9395652013-10-09 19:18:10 +03001975static bool ilk_validate_wm_level(int level,
Imre Deak820c1982013-12-17 14:46:36 +02001976 const struct ilk_wm_maximums *max,
Ville Syrjäläd9395652013-10-09 19:18:10 +03001977 struct intel_wm_level *result)
Ville Syrjäläa9786a12013-08-07 13:24:47 +03001978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
Ville Syrjäläa9786a12013-08-07 13:24:47 +03002013 return ret;
2014}
2015
Damien Lespiaud34ff9c2014-01-06 19:17:23 +00002016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
Matt Roper43d59ed2015-09-24 15:53:07 -07002017 const struct intel_crtc *intel_crtc,
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002018 int level,
Matt Roper7221fc32015-09-24 15:53:08 -07002019 struct intel_crtc_state *cstate,
Matt Roper86c8bbb2015-09-24 15:53:16 -07002020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03002023 struct intel_wm_level *result)
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
Ville Syrjälä6f5ddd12013-08-06 22:24:02 +03002048 result->enable = true;
2049}
2050
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002051static uint32_t
Ville Syrjälä532f7a72016-04-29 17:31:17 +03002052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03002053{
Ville Syrjälä532f7a72016-04-29 17:31:17 +03002054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
Matt Roperee91a152015-12-03 11:37:39 -08002056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
Paulo Zanoni85a02de2013-05-03 17:23:43 -03002058 u32 linetime, ips_linetime;
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03002059
Matt Roperee91a152015-12-03 11:37:39 -08002060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
Ville Syrjälä532f7a72016-04-29 17:31:17 +03002064 if (WARN_ON(intel_state->cdclk == 0))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002065 return 0;
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002066
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03002067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
Ville Syrjälä124abe02015-09-08 13:40:45 +03002070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
Ville Syrjälä532f7a72016-04-29 17:31:17 +03002073 intel_state->cdclk);
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03002074
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03002077}
2078
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002080{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002081 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002082
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002083 if (IS_GEN9(dev)) {
2084 uint32_t val;
Vandana Kannan4f947382014-11-04 17:06:47 +00002085 int ret, i;
Vandana Kannan367294b2014-11-04 17:06:46 +00002086 int level, max_level = ilk_wm_max_level(dev);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
Vandana Kannan367294b2014-11-04 17:06:46 +00002129 /*
Paulo Zanoni0727e402016-09-22 18:00:30 -03002130 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131 * need to be disabled. We make sure to sanitize the values out
2132 * of the punit to satisfy this requirement.
2133 */
2134 for (level = 1; level <= max_level; level++) {
2135 if (wm[level] == 0) {
2136 for (i = level + 1; i <= max_level; i++)
2137 wm[i] = 0;
2138 break;
2139 }
2140 }
2141
2142 /*
Damien Lespiau6f972352015-02-09 19:33:07 +00002143 * WaWmMemoryReadLatency:skl
2144 *
Vandana Kannan367294b2014-11-04 17:06:46 +00002145 * punit doesn't take into account the read latency so we need
Paulo Zanoni0727e402016-09-22 18:00:30 -03002146 * to add 2us to the various latency levels we retrieve from the
2147 * punit when level 0 response data us 0us.
Vandana Kannan367294b2014-11-04 17:06:46 +00002148 */
Paulo Zanoni0727e402016-09-22 18:00:30 -03002149 if (wm[0] == 0) {
2150 wm[0] += 2;
2151 for (level = 1; level <= max_level; level++) {
2152 if (wm[level] == 0)
2153 break;
Vandana Kannan367294b2014-11-04 17:06:46 +00002154 wm[level] += 2;
Vandana Kannan4f947382014-11-04 17:06:47 +00002155 }
Paulo Zanoni0727e402016-09-22 18:00:30 -03002156 }
2157
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002158 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002159 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161 wm[0] = (sskpd >> 56) & 0xFF;
2162 if (wm[0] == 0)
2163 wm[0] = sskpd & 0xF;
Ville Syrjäläe5d50192013-07-05 11:57:22 +03002164 wm[1] = (sskpd >> 4) & 0xFF;
2165 wm[2] = (sskpd >> 12) & 0xFF;
2166 wm[3] = (sskpd >> 20) & 0x1FF;
2167 wm[4] = (sskpd >> 32) & 0x1FF;
Ville Syrjälä63cf9a12013-07-05 11:57:23 +03002168 } else if (INTEL_INFO(dev)->gen >= 6) {
2169 uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
Ville Syrjälä3a88d0a2013-08-01 16:18:49 +03002175 } else if (INTEL_INFO(dev)->gen >= 5) {
2176 uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178 /* ILK primary LP0 latency is 700 ns */
2179 wm[0] = 7;
2180 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
Ville Syrjälä12b134d2013-07-05 11:57:21 +03002182 }
2183}
2184
Ville Syrjälä53615a52013-08-01 16:18:50 +03002185static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186{
2187 /* ILK sprite LP0 latency is 1300 ns */
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01002188 if (IS_GEN5(dev))
Ville Syrjälä53615a52013-08-01 16:18:50 +03002189 wm[0] = 13;
2190}
2191
2192static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 /* ILK cursor LP0 latency is 1300 ns */
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01002195 if (IS_GEN5(dev))
Ville Syrjälä53615a52013-08-01 16:18:50 +03002196 wm[0] = 13;
2197
2198 /* WaDoubleCursorLP3Latency:ivb */
2199 if (IS_IVYBRIDGE(dev))
2200 wm[3] *= 2;
2201}
2202
Damien Lespiau546c81f2014-05-13 15:30:26 +01002203int ilk_wm_max_level(const struct drm_device *dev)
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03002204{
2205 /* how many WM levels are we expecting */
Damien Lespiaub6e742f2015-05-09 02:05:55 +01002206 if (INTEL_INFO(dev)->gen >= 9)
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002207 return 7;
2208 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03002209 return 4;
2210 else if (INTEL_INFO(dev)->gen >= 6)
2211 return 3;
2212 else
2213 return 2;
2214}
Daniel Vetter7526ed72014-09-29 15:07:19 +02002215
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002216static void intel_print_wm_latency(struct drm_device *dev,
2217 const char *name,
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002218 const uint16_t wm[8])
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002219{
Ville Syrjäläad0d6dc2013-08-30 14:30:25 +03002220 int level, max_level = ilk_wm_max_level(dev);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002221
2222 for (level = 0; level <= max_level; level++) {
2223 unsigned int latency = wm[level];
2224
2225 if (latency == 0) {
2226 DRM_ERROR("%s WM%d latency not provided\n",
2227 name, level);
2228 continue;
2229 }
2230
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002231 /*
2232 * - latencies are in us on gen9.
2233 * - before then, WM1+ latency values are in 0.5us units
2234 */
2235 if (IS_GEN9(dev))
2236 latency *= 10;
2237 else if (level > 0)
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002238 latency *= 5;
2239
2240 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241 name, level, wm[level],
2242 latency / 10, latency % 10);
2243 }
2244}
2245
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03002246static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247 uint16_t wm[5], uint16_t min)
2248{
Chris Wilson91c8a322016-07-05 10:40:23 +01002249 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03002250
2251 if (wm[0] >= min)
2252 return false;
2253
2254 wm[0] = max(wm[0], min);
2255 for (level = 1; level <= max_level; level++)
2256 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258 return true;
2259}
2260
2261static void snb_wm_latency_quirk(struct drm_device *dev)
2262{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002263 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03002264 bool changed;
2265
2266 /*
2267 * The BIOS provided WM memory latency values are often
2268 * inadequate for high resolution displays. Adjust them.
2269 */
2270 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274 if (!changed)
2275 return;
2276
2277 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281}
2282
Damien Lespiaufa50ad62014-03-17 18:01:16 +00002283static void ilk_setup_wm_latency(struct drm_device *dev)
Ville Syrjälä53615a52013-08-01 16:18:50 +03002284{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002285 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä53615a52013-08-01 16:18:50 +03002286
2287 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292 sizeof(dev_priv->wm.pri_latency));
2293
2294 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
Ville Syrjälä26ec9712013-08-01 16:18:52 +03002296
2297 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
Ville Syrjäläe95a2f72014-05-08 15:09:19 +03002300
2301 if (IS_GEN6(dev))
2302 snb_wm_latency_quirk(dev);
Ville Syrjälä53615a52013-08-01 16:18:50 +03002303}
2304
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002305static void skl_setup_wm_latency(struct drm_device *dev)
2306{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002307 struct drm_i915_private *dev_priv = to_i915(dev);
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002308
2309 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311}
2312
Matt Ropered4a6a72016-02-23 17:20:13 -08002313static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314 struct intel_pipe_wm *pipe_wm)
2315{
2316 /* LP0 watermark maximums depend on this pipe alone */
2317 const struct intel_wm_config config = {
2318 .num_pipes_active = 1,
2319 .sprites_enabled = pipe_wm->sprites_enabled,
2320 .sprites_scaled = pipe_wm->sprites_scaled,
2321 };
2322 struct ilk_wm_maximums max;
2323
2324 /* LP0 watermarks always use 1/2 DDB partitioning */
2325 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327 /* At least LP0 must be valid */
2328 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330 return false;
2331 }
2332
2333 return true;
2334}
2335
Matt Roper261a27d2015-10-08 15:28:25 -07002336/* Compute new watermarks for the pipe */
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002337static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
Matt Roper261a27d2015-10-08 15:28:25 -07002338{
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002339 struct drm_atomic_state *state = cstate->base.state;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
Matt Roper86c8bbb2015-09-24 15:53:16 -07002341 struct intel_pipe_wm *pipe_wm;
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002342 struct drm_device *dev = state->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01002343 const struct drm_i915_private *dev_priv = to_i915(dev);
Matt Roper43d59ed2015-09-24 15:53:07 -07002344 struct intel_plane *intel_plane;
Matt Roper86c8bbb2015-09-24 15:53:16 -07002345 struct intel_plane_state *pristate = NULL;
Matt Roper43d59ed2015-09-24 15:53:07 -07002346 struct intel_plane_state *sprstate = NULL;
Matt Roper86c8bbb2015-09-24 15:53:16 -07002347 struct intel_plane_state *curstate = NULL;
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01002348 int level, max_level = ilk_wm_max_level(dev), usable_level;
Imre Deak820c1982013-12-17 14:46:36 +02002349 struct ilk_wm_maximums max;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002350
Matt Ropere8f1f022016-05-12 07:05:55 -07002351 pipe_wm = &cstate->wm.ilk.optimal;
Matt Roper86c8bbb2015-09-24 15:53:16 -07002352
Matt Roper43d59ed2015-09-24 15:53:07 -07002353 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002354 struct intel_plane_state *ps;
2355
2356 ps = intel_atomic_get_existing_plane_state(state,
2357 intel_plane);
2358 if (!ps)
2359 continue;
Matt Roper86c8bbb2015-09-24 15:53:16 -07002360
2361 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002362 pristate = ps;
Matt Roper86c8bbb2015-09-24 15:53:16 -07002363 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002364 sprstate = ps;
Matt Roper86c8bbb2015-09-24 15:53:16 -07002365 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002366 curstate = ps;
Matt Roper43d59ed2015-09-24 15:53:07 -07002367 }
2368
Matt Ropered4a6a72016-02-23 17:20:13 -08002369 pipe_wm->pipe_enabled = cstate->base.active;
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002370 if (sprstate) {
Ville Syrjälä936e71e2016-07-26 19:06:59 +03002371 pipe_wm->sprites_enabled = sprstate->base.visible;
2372 pipe_wm->sprites_scaled = sprstate->base.visible &&
2373 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002375 }
2376
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01002377 usable_level = max_level;
2378
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02002379 /* ILK/SNB: LP2+ watermarks only w/o sprites */
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01002380 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01002381 usable_level = 1;
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02002382
2383 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
Matt Ropered4a6a72016-02-23 17:20:13 -08002384 if (pipe_wm->sprites_scaled)
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01002385 usable_level = 0;
Ville Syrjälä7b39a0b2013-12-05 15:51:30 +02002386
Matt Roper86c8bbb2015-09-24 15:53:16 -07002387 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
Maarten Lankhorst71f0a622016-03-08 10:57:16 +01002388 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002392
Ville Syrjäläa42a5712014-01-07 16:14:08 +02002393 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjälä532f7a72016-04-29 17:31:17 +03002394 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002395
Matt Ropered4a6a72016-02-23 17:20:13 -08002396 if (!ilk_validate_pipe_wm(dev, pipe_wm))
Maarten Lankhorst1a426d62016-03-02 12:36:03 +01002397 return -EINVAL;
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002398
2399 ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401 for (level = 1; level <= max_level; level++) {
Maarten Lankhorst71f0a622016-03-08 10:57:16 +01002402 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002403
Matt Roper86c8bbb2015-09-24 15:53:16 -07002404 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01002405 pristate, sprstate, curstate, wm);
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002406
2407 /*
2408 * Disable any watermark level that exceeds the
2409 * register maximums since such watermarks are
2410 * always invalid.
2411 */
Maarten Lankhorst71f0a622016-03-08 10:57:16 +01002412 if (level > usable_level)
2413 continue;
2414
2415 if (ilk_validate_wm_level(level, &max, wm))
2416 pipe_wm->wm[level] = *wm;
2417 else
Maarten Lankhorstd81f04c2016-03-02 12:38:06 +01002418 usable_level = level;
Ville Syrjäläa3cb4042014-04-28 15:44:56 +03002419 }
2420
Matt Roper86c8bbb2015-09-24 15:53:16 -07002421 return 0;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002422}
2423
2424/*
Matt Ropered4a6a72016-02-23 17:20:13 -08002425 * Build a set of 'intermediate' watermark values that satisfy both the old
2426 * state and the new state. These can be programmed to the hardware
2427 * immediately.
2428 */
2429static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430 struct intel_crtc *intel_crtc,
2431 struct intel_crtc_state *newstate)
2432{
Matt Ropere8f1f022016-05-12 07:05:55 -07002433 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
Matt Ropered4a6a72016-02-23 17:20:13 -08002434 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435 int level, max_level = ilk_wm_max_level(dev);
2436
2437 /*
2438 * Start with the final, target watermarks, then combine with the
2439 * currently active watermarks to get values that are safe both before
2440 * and after the vblank.
2441 */
Matt Ropere8f1f022016-05-12 07:05:55 -07002442 *a = newstate->wm.ilk.optimal;
Matt Ropered4a6a72016-02-23 17:20:13 -08002443 a->pipe_enabled |= b->pipe_enabled;
2444 a->sprites_enabled |= b->sprites_enabled;
2445 a->sprites_scaled |= b->sprites_scaled;
2446
2447 for (level = 0; level <= max_level; level++) {
2448 struct intel_wm_level *a_wm = &a->wm[level];
2449 const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451 a_wm->enable &= b_wm->enable;
2452 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456 }
2457
2458 /*
2459 * We need to make sure that these merged watermark values are
2460 * actually a valid configuration themselves. If they're not,
2461 * there's no safe way to transition from the old state to
2462 * the new state, so we need to fail the atomic transaction.
2463 */
2464 if (!ilk_validate_pipe_wm(dev, a))
2465 return -EINVAL;
2466
2467 /*
2468 * If our intermediate WM are identical to the final WM, then we can
2469 * omit the post-vblank programming; only update if it's different.
2470 */
Matt Ropere8f1f022016-05-12 07:05:55 -07002471 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
Matt Ropered4a6a72016-02-23 17:20:13 -08002472 newstate->wm.need_postvbl_update = false;
2473
2474 return 0;
2475}
2476
2477/*
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002478 * Merge the watermarks from all active pipes for a specific level.
2479 */
2480static void ilk_merge_wm_level(struct drm_device *dev,
2481 int level,
2482 struct intel_wm_level *ret_wm)
2483{
2484 const struct intel_crtc *intel_crtc;
2485
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002486 ret_wm->enable = true;
2487
Damien Lespiaud3fcc802014-05-13 23:32:22 +01002488 for_each_intel_crtc(dev, intel_crtc) {
Matt Ropered4a6a72016-02-23 17:20:13 -08002489 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
Ville Syrjäläfe392ef2014-03-07 18:32:10 +02002490 const struct intel_wm_level *wm = &active->wm[level];
2491
2492 if (!active->pipe_enabled)
2493 continue;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002494
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002495 /*
2496 * The watermark values may have been used in the past,
2497 * so we must maintain them in the registers for some
2498 * time even if the level is now disabled.
2499 */
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002500 if (!wm->enable)
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002501 ret_wm->enable = false;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002502
2503 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507 }
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002508}
2509
2510/*
2511 * Merge all low power watermarks for all active pipes.
2512 */
2513static void ilk_wm_merge(struct drm_device *dev,
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02002514 const struct intel_wm_config *config,
Imre Deak820c1982013-12-17 14:46:36 +02002515 const struct ilk_wm_maximums *max,
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002516 struct intel_pipe_wm *merged)
2517{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002518 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002519 int level, max_level = ilk_wm_max_level(dev);
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002520 int last_enabled_level = max_level;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002521
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02002522 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524 config->num_pipes_active > 1)
Ville Syrjälä1204d5b2016-04-01 21:53:18 +03002525 last_enabled_level = 0;
Ville Syrjälä0ba22e22013-12-05 15:51:34 +02002526
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02002527 /* ILK: FBC WM must be disabled always */
2528 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002529
2530 /* merge each WM1+ level */
2531 for (level = 1; level <= max_level; level++) {
2532 struct intel_wm_level *wm = &merged->wm[level];
2533
2534 ilk_merge_wm_level(dev, level, wm);
2535
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002536 if (level > last_enabled_level)
2537 wm->enable = false;
2538 else if (!ilk_validate_wm_level(level, max, wm))
2539 /* make sure all following levels get disabled */
2540 last_enabled_level = level - 1;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002541
2542 /*
2543 * The spec says it is preferred to disable
2544 * FBC WMs instead of disabling a WM level.
2545 */
2546 if (wm->fbc_val > max->fbc) {
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002547 if (wm->enable)
2548 merged->fbc_wm_enabled = false;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002549 wm->fbc_val = 0;
2550 }
2551 }
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02002552
2553 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554 /*
2555 * FIXME this is racy. FBC might get enabled later.
2556 * What we should check here is whether FBC can be
2557 * enabled sometime later.
2558 */
Paulo Zanoni7733b492015-07-07 15:26:04 -03002559 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03002560 intel_fbc_is_active(dev_priv)) {
Ville Syrjälä6c8b6c22013-12-05 15:51:35 +02002561 for (level = 2; level <= max_level; level++) {
2562 struct intel_wm_level *wm = &merged->wm[level];
2563
2564 wm->enable = false;
2565 }
2566 }
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002567}
2568
Ville Syrjäläb380ca32013-10-09 19:18:01 +03002569static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570{
2571 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573}
2574
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002575/* The value we need to program into the WM_LPx latency field */
2576static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002578 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002579
Ville Syrjäläa42a5712014-01-07 16:14:08 +02002580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002581 return 2 * level;
2582 else
2583 return dev_priv->wm.pri_latency[level];
2584}
2585
Imre Deak820c1982013-12-17 14:46:36 +02002586static void ilk_compute_wm_results(struct drm_device *dev,
Ville Syrjälä0362c782013-10-09 19:17:57 +03002587 const struct intel_pipe_wm *merged,
Ville Syrjälä609cede2013-10-09 19:18:03 +03002588 enum intel_ddb_partitioning partitioning,
Imre Deak820c1982013-12-17 14:46:36 +02002589 struct ilk_wm_values *results)
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002590{
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002591 struct intel_crtc *intel_crtc;
2592 int level, wm_lp;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002593
Ville Syrjälä0362c782013-10-09 19:17:57 +03002594 results->enable_fbc_wm = merged->fbc_wm_enabled;
Ville Syrjälä609cede2013-10-09 19:18:03 +03002595 results->partitioning = partitioning;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002596
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002597 /* LP1+ register values */
Paulo Zanonicca32e92013-05-31 11:45:06 -03002598 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03002599 const struct intel_wm_level *r;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002600
Ville Syrjäläb380ca32013-10-09 19:18:01 +03002601 level = ilk_wm_lp_to_level(wm_lp, merged);
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002602
Ville Syrjälä0362c782013-10-09 19:17:57 +03002603 r = &merged->wm[level];
Paulo Zanonicca32e92013-05-31 11:45:06 -03002604
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002605 /*
2606 * Maintain the watermark values even if the level is
2607 * disabled. Doing otherwise could cause underruns.
2608 */
2609 results->wm_lp[wm_lp - 1] =
Ville Syrjäläa68d68e2013-12-05 15:51:29 +02002610 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
Ville Syrjälä416f4722013-11-02 21:07:46 -07002611 (r->pri_val << WM1_LP_SR_SHIFT) |
2612 r->cur_val;
2613
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002614 if (r->enable)
2615 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
Ville Syrjälä416f4722013-11-02 21:07:46 -07002617 if (INTEL_INFO(dev)->gen >= 8)
2618 results->wm_lp[wm_lp - 1] |=
2619 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620 else
2621 results->wm_lp[wm_lp - 1] |=
2622 r->fbc_val << WM1_LP_FBC_SHIFT;
2623
Ville Syrjäläd52fea52014-04-28 15:44:57 +03002624 /*
2625 * Always set WM1S_LP_EN when spr_val != 0, even if the
2626 * level is disabled. Doing otherwise could cause underruns.
2627 */
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02002628 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629 WARN_ON(wm_lp != 1);
2630 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631 } else
2632 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
Paulo Zanonicca32e92013-05-31 11:45:06 -03002633 }
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002634
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002635 /* LP0 register values */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01002636 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002637 enum pipe pipe = intel_crtc->pipe;
Matt Ropered4a6a72016-02-23 17:20:13 -08002638 const struct intel_wm_level *r =
2639 &intel_crtc->wm.active.ilk.wm[0];
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002640
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002641 if (WARN_ON(!r->enable))
2642 continue;
2643
Matt Ropered4a6a72016-02-23 17:20:13 -08002644 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +03002645
2646 results->wm_pipe[pipe] =
2647 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649 r->cur_val;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002650 }
2651}
2652
Paulo Zanoni861f3382013-05-31 10:19:21 -03002653/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654 * case both are at the same level. Prefer r1 in case they're the same. */
Imre Deak820c1982013-12-17 14:46:36 +02002655static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002656 struct intel_pipe_wm *r1,
2657 struct intel_pipe_wm *r2)
Paulo Zanoni861f3382013-05-31 10:19:21 -03002658{
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002659 int level, max_level = ilk_wm_max_level(dev);
2660 int level1 = 0, level2 = 0;
Paulo Zanoni861f3382013-05-31 10:19:21 -03002661
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002662 for (level = 1; level <= max_level; level++) {
2663 if (r1->wm[level].enable)
2664 level1 = level;
2665 if (r2->wm[level].enable)
2666 level2 = level;
Paulo Zanoni861f3382013-05-31 10:19:21 -03002667 }
2668
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002669 if (level1 == level2) {
2670 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
Paulo Zanoni861f3382013-05-31 10:19:21 -03002671 return r2;
2672 else
2673 return r1;
Ville Syrjälä198a1e92013-10-09 19:17:58 +03002674 } else if (level1 > level2) {
Paulo Zanoni861f3382013-05-31 10:19:21 -03002675 return r1;
2676 } else {
2677 return r2;
2678 }
2679}
2680
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002681/* dirty bits used to track which watermarks need changes */
2682#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686#define WM_DIRTY_FBC (1 << 24)
2687#define WM_DIRTY_DDB (1 << 25)
2688
Damien Lespiau055e3932014-08-18 13:49:10 +01002689static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
Imre Deak820c1982013-12-17 14:46:36 +02002690 const struct ilk_wm_values *old,
2691 const struct ilk_wm_values *new)
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002692{
2693 unsigned int dirty = 0;
2694 enum pipe pipe;
2695 int wm_lp;
2696
Damien Lespiau055e3932014-08-18 13:49:10 +01002697 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002698 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699 dirty |= WM_DIRTY_LINETIME(pipe);
2700 /* Must disable LP1+ watermarks too */
2701 dirty |= WM_DIRTY_LP_ALL;
2702 }
2703
2704 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705 dirty |= WM_DIRTY_PIPE(pipe);
2706 /* Must disable LP1+ watermarks too */
2707 dirty |= WM_DIRTY_LP_ALL;
2708 }
2709 }
2710
2711 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712 dirty |= WM_DIRTY_FBC;
2713 /* Must disable LP1+ watermarks too */
2714 dirty |= WM_DIRTY_LP_ALL;
2715 }
2716
2717 if (old->partitioning != new->partitioning) {
2718 dirty |= WM_DIRTY_DDB;
2719 /* Must disable LP1+ watermarks too */
2720 dirty |= WM_DIRTY_LP_ALL;
2721 }
2722
2723 /* LP1+ watermarks already deemed dirty, no need to continue */
2724 if (dirty & WM_DIRTY_LP_ALL)
2725 return dirty;
2726
2727 /* Find the lowest numbered LP1+ watermark in need of an update... */
2728 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731 break;
2732 }
2733
2734 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735 for (; wm_lp <= 3; wm_lp++)
2736 dirty |= WM_DIRTY_LP(wm_lp);
2737
2738 return dirty;
2739}
2740
Ville Syrjälä8553c182013-12-05 15:51:39 +02002741static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742 unsigned int dirty)
2743{
Imre Deak820c1982013-12-17 14:46:36 +02002744 struct ilk_wm_values *previous = &dev_priv->wm.hw;
Ville Syrjälä8553c182013-12-05 15:51:39 +02002745 bool changed = false;
2746
2747 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2750 changed = true;
2751 }
2752 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2755 changed = true;
2756 }
2757 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2760 changed = true;
2761 }
2762
2763 /*
2764 * Don't touch WM1S_LP_EN here.
2765 * Doing so could cause underruns.
2766 */
2767
2768 return changed;
2769}
2770
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
Imre Deak820c1982013-12-17 14:46:36 +02002775static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct ilk_wm_values *results)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002777{
Chris Wilson91c8a322016-07-05 10:40:23 +01002778 struct drm_device *dev = &dev_priv->drm;
Imre Deak820c1982013-12-17 14:46:36 +02002779 struct ilk_wm_values *previous = &dev_priv->wm.hw;
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002780 unsigned int dirty;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002781 uint32_t val;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002782
Damien Lespiau055e3932014-08-18 13:49:10 +01002783 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002784 if (!dirty)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002785 return;
2786
Ville Syrjälä8553c182013-12-05 15:51:39 +02002787 _ilk_disable_lp_wm(dev_priv, dirty);
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02002788
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002789 if (dirty & WM_DIRTY_PIPE(PIPE_A))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002790 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002791 if (dirty & WM_DIRTY_PIPE(PIPE_B))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002792 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002793 if (dirty & WM_DIRTY_PIPE(PIPE_C))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002794 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002796 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002797 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002798 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002799 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002800 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002801 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002803 if (dirty & WM_DIRTY_DDB) {
Ville Syrjäläa42a5712014-01-07 16:14:08 +02002804 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjäläac9545f2013-12-05 15:51:28 +02002805 val = I915_READ(WM_MISC);
2806 if (results->partitioning == INTEL_DDB_PART_1_2)
2807 val &= ~WM_MISC_DATA_PARTITION_5_6;
2808 else
2809 val |= WM_MISC_DATA_PARTITION_5_6;
2810 I915_WRITE(WM_MISC, val);
2811 } else {
2812 val = I915_READ(DISP_ARB_CTL2);
2813 if (results->partitioning == INTEL_DDB_PART_1_2)
2814 val &= ~DISP_DATA_PARTITION_5_6;
2815 else
2816 val |= DISP_DATA_PARTITION_5_6;
2817 I915_WRITE(DISP_ARB_CTL2, val);
2818 }
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03002819 }
2820
Ville Syrjälä49a687c2013-10-11 19:39:52 +03002821 if (dirty & WM_DIRTY_FBC) {
Paulo Zanonicca32e92013-05-31 11:45:06 -03002822 val = I915_READ(DISP_ARB_CTL);
2823 if (results->enable_fbc_wm)
2824 val &= ~DISP_FBC_WM_DIS;
2825 else
2826 val |= DISP_FBC_WM_DIS;
2827 I915_WRITE(DISP_ARB_CTL, val);
2828 }
2829
Imre Deak954911e2013-12-17 14:46:34 +02002830 if (dirty & WM_DIRTY_LP(1) &&
2831 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834 if (INTEL_INFO(dev)->gen >= 7) {
Ville Syrjälä6cef2b8a2013-12-05 15:51:32 +02002835 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839 }
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002840
Ville Syrjäläfacd619b2013-12-05 15:51:33 +02002841 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002842 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
Ville Syrjäläfacd619b2013-12-05 15:51:33 +02002843 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002844 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
Ville Syrjäläfacd619b2013-12-05 15:51:33 +02002845 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002846 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
Ville Syrjälä609cede2013-10-09 19:18:03 +03002847
2848 dev_priv->wm.hw = *results;
Paulo Zanoni801bcff2013-05-31 10:08:35 -03002849}
2850
Matt Ropered4a6a72016-02-23 17:20:13 -08002851bool ilk_disable_lp_wm(struct drm_device *dev)
Ville Syrjälä8553c182013-12-05 15:51:39 +02002852{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002853 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä8553c182013-12-05 15:51:39 +02002854
2855 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856}
2857
Lyude656d1b82016-08-17 15:55:54 -04002858#define SKL_SAGV_BLOCK_TIME 30 /* µs */
Damien Lespiaub9cec072014-11-04 17:06:43 +00002859
Matt Roper024c9042015-09-24 15:53:11 -07002860/*
2861 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2862 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863 * other universal planes are in indices 1..n. Note that this may leave unused
2864 * indices between the top "sprite" plane and the cursor.
2865 */
2866static int
2867skl_wm_plane_id(const struct intel_plane *plane)
2868{
2869 switch (plane->base.type) {
2870 case DRM_PLANE_TYPE_PRIMARY:
2871 return 0;
2872 case DRM_PLANE_TYPE_CURSOR:
2873 return PLANE_CURSOR;
2874 case DRM_PLANE_TYPE_OVERLAY:
2875 return plane->plane + 1;
2876 default:
2877 MISSING_CASE(plane->base.type);
2878 return plane->plane;
2879 }
2880}
2881
Paulo Zanoni56feca92016-09-22 18:00:28 -03002882static bool
2883intel_has_sagv(struct drm_i915_private *dev_priv)
2884{
Paulo Zanoni6e3100e2016-09-22 18:00:29 -03002885 if (IS_KABYLAKE(dev_priv))
2886 return true;
2887
2888 if (IS_SKYLAKE(dev_priv) &&
2889 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890 return true;
2891
2892 return false;
Paulo Zanoni56feca92016-09-22 18:00:28 -03002893}
2894
Lyude656d1b82016-08-17 15:55:54 -04002895/*
2896 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897 * depending on power and performance requirements. The display engine access
2898 * to system memory is blocked during the adjustment time. Because of the
2899 * blocking time, having this enabled can cause full system hangs and/or pipe
2900 * underruns if we don't meet all of the following requirements:
2901 *
2902 * - <= 1 pipe enabled
2903 * - All planes can enable watermarks for latencies >= SAGV engine block time
2904 * - We're not using an interlaced display configuration
2905 */
2906int
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002907intel_enable_sagv(struct drm_i915_private *dev_priv)
Lyude656d1b82016-08-17 15:55:54 -04002908{
2909 int ret;
2910
Paulo Zanoni56feca92016-09-22 18:00:28 -03002911 if (!intel_has_sagv(dev_priv))
2912 return 0;
2913
2914 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
Lyude656d1b82016-08-17 15:55:54 -04002915 return 0;
2916
2917 DRM_DEBUG_KMS("Enabling the SAGV\n");
2918 mutex_lock(&dev_priv->rps.hw_lock);
2919
2920 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921 GEN9_SAGV_ENABLE);
2922
2923 /* We don't need to wait for the SAGV when enabling */
2924 mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926 /*
2927 * Some skl systems, pre-release machines in particular,
2928 * don't actually have an SAGV.
2929 */
Paulo Zanoni6e3100e2016-09-22 18:00:29 -03002930 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
Lyude656d1b82016-08-17 15:55:54 -04002931 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002932 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
Lyude656d1b82016-08-17 15:55:54 -04002933 return 0;
2934 } else if (ret < 0) {
2935 DRM_ERROR("Failed to enable the SAGV\n");
2936 return ret;
2937 }
2938
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002939 dev_priv->sagv_status = I915_SAGV_ENABLED;
Lyude656d1b82016-08-17 15:55:54 -04002940 return 0;
2941}
2942
2943static int
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002944intel_do_sagv_disable(struct drm_i915_private *dev_priv)
Lyude656d1b82016-08-17 15:55:54 -04002945{
2946 int ret;
2947 uint32_t temp = GEN9_SAGV_DISABLE;
2948
2949 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2950 &temp);
2951 if (ret)
2952 return ret;
2953 else
2954 return temp & GEN9_SAGV_IS_DISABLED;
2955}
2956
2957int
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002958intel_disable_sagv(struct drm_i915_private *dev_priv)
Lyude656d1b82016-08-17 15:55:54 -04002959{
2960 int ret, result;
2961
Paulo Zanoni56feca92016-09-22 18:00:28 -03002962 if (!intel_has_sagv(dev_priv))
2963 return 0;
2964
2965 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
Lyude656d1b82016-08-17 15:55:54 -04002966 return 0;
2967
2968 DRM_DEBUG_KMS("Disabling the SAGV\n");
2969 mutex_lock(&dev_priv->rps.hw_lock);
2970
2971 /* bspec says to keep retrying for at least 1 ms */
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002972 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
Lyude656d1b82016-08-17 15:55:54 -04002973 mutex_unlock(&dev_priv->rps.hw_lock);
2974
2975 if (ret == -ETIMEDOUT) {
2976 DRM_ERROR("Request to disable SAGV timed out\n");
2977 return -ETIMEDOUT;
2978 }
2979
2980 /*
2981 * Some skl systems, pre-release machines in particular,
2982 * don't actually have an SAGV.
2983 */
Paulo Zanoni6e3100e2016-09-22 18:00:29 -03002984 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
Lyude656d1b82016-08-17 15:55:54 -04002985 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002986 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
Lyude656d1b82016-08-17 15:55:54 -04002987 return 0;
2988 } else if (result < 0) {
2989 DRM_ERROR("Failed to disable the SAGV\n");
2990 return result;
2991 }
2992
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002993 dev_priv->sagv_status = I915_SAGV_DISABLED;
Lyude656d1b82016-08-17 15:55:54 -04002994 return 0;
2995}
2996
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002997bool intel_can_enable_sagv(struct drm_atomic_state *state)
Lyude656d1b82016-08-17 15:55:54 -04002998{
2999 struct drm_device *dev = state->dev;
3000 struct drm_i915_private *dev_priv = to_i915(dev);
3001 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3002 struct drm_crtc *crtc;
3003 enum pipe pipe;
3004 int level, plane;
3005
Paulo Zanoni56feca92016-09-22 18:00:28 -03003006 if (!intel_has_sagv(dev_priv))
3007 return false;
3008
Lyude656d1b82016-08-17 15:55:54 -04003009 /*
3010 * SKL workaround: bspec recommends we disable the SAGV when we have
3011 * more then one pipe enabled
3012 *
3013 * If there are no active CRTCs, no additional checks need be performed
3014 */
3015 if (hweight32(intel_state->active_crtcs) == 0)
3016 return true;
3017 else if (hweight32(intel_state->active_crtcs) > 1)
3018 return false;
3019
3020 /* Since we're now guaranteed to only have one active CRTC... */
3021 pipe = ffs(intel_state->active_crtcs) - 1;
3022 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3023
3024 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025 return false;
3026
3027 for_each_plane(dev_priv, pipe, plane) {
3028 /* Skip this plane if it's not enabled */
3029 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3030 continue;
3031
3032 /* Find the highest enabled wm level for this plane */
3033 for (level = ilk_wm_max_level(dev);
3034 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3035 { }
3036
3037 /*
3038 * If any of the planes on this pipe don't enable wm levels
3039 * that incur memory latencies higher then 30µs we can't enable
3040 * the SAGV
3041 */
3042 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3043 return false;
3044 }
3045
3046 return true;
3047}
3048
Damien Lespiaub9cec072014-11-04 17:06:43 +00003049static void
3050skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
Matt Roper024c9042015-09-24 15:53:11 -07003051 const struct intel_crtc_state *cstate,
Matt Roperc107acf2016-05-12 07:06:01 -07003052 struct skl_ddb_entry *alloc, /* out */
3053 int *num_active /* out */)
Damien Lespiaub9cec072014-11-04 17:06:43 +00003054{
Matt Roperc107acf2016-05-12 07:06:01 -07003055 struct drm_atomic_state *state = cstate->base.state;
3056 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3057 struct drm_i915_private *dev_priv = to_i915(dev);
Matt Roper024c9042015-09-24 15:53:11 -07003058 struct drm_crtc *for_crtc = cstate->base.crtc;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003059 unsigned int pipe_size, ddb_size;
3060 int nth_active_pipe;
Matt Roperc107acf2016-05-12 07:06:01 -07003061 int pipe = to_intel_crtc(for_crtc)->pipe;
3062
Matt Ropera6d3460e2016-05-12 07:06:04 -07003063 if (WARN_ON(!state) || !cstate->base.active) {
Damien Lespiaub9cec072014-11-04 17:06:43 +00003064 alloc->start = 0;
3065 alloc->end = 0;
Matt Ropera6d3460e2016-05-12 07:06:04 -07003066 *num_active = hweight32(dev_priv->active_crtcs);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003067 return;
3068 }
3069
Matt Ropera6d3460e2016-05-12 07:06:04 -07003070 if (intel_state->active_pipe_changes)
3071 *num_active = hweight32(intel_state->active_crtcs);
3072 else
3073 *num_active = hweight32(dev_priv->active_crtcs);
3074
Deepak M6f3fff62016-09-15 15:01:10 +05303075 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3076 WARN_ON(ddb_size == 0);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003077
3078 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3079
Matt Roperc107acf2016-05-12 07:06:01 -07003080 /*
Matt Ropera6d3460e2016-05-12 07:06:04 -07003081 * If the state doesn't change the active CRTC's, then there's
3082 * no need to recalculate; the existing pipe allocation limits
3083 * should remain unchanged. Note that we're safe from racing
3084 * commits since any racing commit that changes the active CRTC
3085 * list would need to grab _all_ crtc locks, including the one
3086 * we currently hold.
Matt Roperc107acf2016-05-12 07:06:01 -07003087 */
Matt Ropera6d3460e2016-05-12 07:06:04 -07003088 if (!intel_state->active_pipe_changes) {
3089 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3090 return;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003091 }
Matt Ropera6d3460e2016-05-12 07:06:04 -07003092
3093 nth_active_pipe = hweight32(intel_state->active_crtcs &
3094 (drm_crtc_mask(for_crtc) - 1));
3095 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096 alloc->start = nth_active_pipe * ddb_size / *num_active;
3097 alloc->end = alloc->start + pipe_size;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003098}
3099
Matt Roperc107acf2016-05-12 07:06:01 -07003100static unsigned int skl_cursor_allocation(int num_active)
Damien Lespiaub9cec072014-11-04 17:06:43 +00003101{
Matt Roperc107acf2016-05-12 07:06:01 -07003102 if (num_active == 1)
Damien Lespiaub9cec072014-11-04 17:06:43 +00003103 return 32;
3104
3105 return 8;
3106}
3107
Damien Lespiaua269c582014-11-04 17:06:49 +00003108static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109{
3110 entry->start = reg & 0x3ff;
3111 entry->end = (reg >> 16) & 0x3ff;
Damien Lespiau16160e32014-11-04 17:06:53 +00003112 if (entry->end)
3113 entry->end += 1;
Damien Lespiaua269c582014-11-04 17:06:49 +00003114}
3115
Damien Lespiau08db6652014-11-04 17:06:52 +00003116void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117 struct skl_ddb_allocation *ddb /* out */)
Damien Lespiaua269c582014-11-04 17:06:49 +00003118{
Damien Lespiaua269c582014-11-04 17:06:49 +00003119 enum pipe pipe;
3120 int plane;
3121 u32 val;
3122
Maarten Lankhorstb10f1b22015-10-22 13:56:34 +02003123 memset(ddb, 0, sizeof(*ddb));
3124
Damien Lespiaua269c582014-11-04 17:06:49 +00003125 for_each_pipe(dev_priv, pipe) {
Imre Deak4d800032016-02-17 16:31:29 +02003126 enum intel_display_power_domain power_domain;
3127
3128 power_domain = POWER_DOMAIN_PIPE(pipe);
3129 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Maarten Lankhorstb10f1b22015-10-22 13:56:34 +02003130 continue;
3131
Damien Lespiaudd740782015-02-28 14:54:08 +00003132 for_each_plane(dev_priv, pipe, plane) {
Damien Lespiaua269c582014-11-04 17:06:49 +00003133 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3134 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3135 val);
3136 }
3137
3138 val = I915_READ(CUR_BUF_CFG(pipe));
Matt Roper4969d332015-09-24 15:53:10 -07003139 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3140 val);
Imre Deak4d800032016-02-17 16:31:29 +02003141
3142 intel_display_power_put(dev_priv, power_domain);
Damien Lespiaua269c582014-11-04 17:06:49 +00003143 }
3144}
3145
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003146/*
3147 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3148 * The bspec defines downscale amount as:
3149 *
3150 * """
3151 * Horizontal down scale amount = maximum[1, Horizontal source size /
3152 * Horizontal destination size]
3153 * Vertical down scale amount = maximum[1, Vertical source size /
3154 * Vertical destination size]
3155 * Total down scale amount = Horizontal down scale amount *
3156 * Vertical down scale amount
3157 * """
3158 *
3159 * Return value is provided in 16.16 fixed point form to retain fractional part.
3160 * Caller should take care of dividing & rounding off the value.
3161 */
3162static uint32_t
3163skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3164{
3165 uint32_t downscale_h, downscale_w;
3166 uint32_t src_w, src_h, dst_w, dst_h;
3167
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003168 if (WARN_ON(!pstate->base.visible))
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003169 return DRM_PLANE_HELPER_NO_SCALING;
3170
3171 /* n.b., src is 16.16 fixed point, dst is whole integer */
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003172 src_w = drm_rect_width(&pstate->base.src);
3173 src_h = drm_rect_height(&pstate->base.src);
3174 dst_w = drm_rect_width(&pstate->base.dst);
3175 dst_h = drm_rect_height(&pstate->base.dst);
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003176 if (intel_rotation_90_or_270(pstate->base.rotation))
3177 swap(dst_w, dst_h);
3178
3179 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3180 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181
3182 /* Provide result in 16.16 fixed point */
3183 return (uint64_t)downscale_w * downscale_h >> 16;
3184}
3185
Damien Lespiaub9cec072014-11-04 17:06:43 +00003186static unsigned int
Matt Roper024c9042015-09-24 15:53:11 -07003187skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3188 const struct drm_plane_state *pstate,
3189 int y)
Damien Lespiaub9cec072014-11-04 17:06:43 +00003190{
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003191 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
Matt Roper024c9042015-09-24 15:53:11 -07003192 struct drm_framebuffer *fb = pstate->fb;
Kumar, Mahesh8d19d7d2016-05-19 15:03:01 -07003193 uint32_t down_scale_amount, data_rate;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003194 uint32_t width = 0, height = 0;
Matt Ropera1de91e2016-05-12 07:05:57 -07003195 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3196
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003197 if (!intel_pstate->base.visible)
Matt Ropera1de91e2016-05-12 07:05:57 -07003198 return 0;
3199 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3200 return 0;
3201 if (y && format != DRM_FORMAT_NV12)
3202 return 0;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003203
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003204 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3205 height = drm_rect_height(&intel_pstate->base.src) >> 16;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003206
3207 if (intel_rotation_90_or_270(pstate->rotation))
3208 swap(width, height);
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003209
3210 /* for planar format */
Matt Ropera1de91e2016-05-12 07:05:57 -07003211 if (format == DRM_FORMAT_NV12) {
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003212 if (y) /* y-plane data rate */
Kumar, Mahesh8d19d7d2016-05-19 15:03:01 -07003213 data_rate = width * height *
Matt Ropera1de91e2016-05-12 07:05:57 -07003214 drm_format_plane_cpp(format, 0);
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003215 else /* uv-plane data rate */
Kumar, Mahesh8d19d7d2016-05-19 15:03:01 -07003216 data_rate = (width / 2) * (height / 2) *
Matt Ropera1de91e2016-05-12 07:05:57 -07003217 drm_format_plane_cpp(format, 1);
Kumar, Mahesh8d19d7d2016-05-19 15:03:01 -07003218 } else {
3219 /* for packed formats */
3220 data_rate = width * height * drm_format_plane_cpp(format, 0);
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003221 }
3222
Kumar, Mahesh8d19d7d2016-05-19 15:03:01 -07003223 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3224
3225 return (uint64_t)data_rate * down_scale_amount >> 16;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003226}
3227
3228/*
3229 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3230 * a 8192x4096@32bpp framebuffer:
3231 * 3 * 4096 * 8192 * 4 < 2^32
3232 */
3233static unsigned int
Matt Roper9c74d822016-05-12 07:05:58 -07003234skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
Damien Lespiaub9cec072014-11-04 17:06:43 +00003235{
Matt Roper9c74d822016-05-12 07:05:58 -07003236 struct drm_crtc_state *cstate = &intel_cstate->base;
3237 struct drm_atomic_state *state = cstate->state;
3238 struct drm_crtc *crtc = cstate->crtc;
3239 struct drm_device *dev = crtc->dev;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Ropera6d3460e2016-05-12 07:06:04 -07003241 const struct drm_plane *plane;
Matt Roper024c9042015-09-24 15:53:11 -07003242 const struct intel_plane *intel_plane;
Matt Ropera6d3460e2016-05-12 07:06:04 -07003243 struct drm_plane_state *pstate;
Matt Ropera1de91e2016-05-12 07:05:57 -07003244 unsigned int rate, total_data_rate = 0;
Matt Roper9c74d822016-05-12 07:05:58 -07003245 int id;
Matt Ropera6d3460e2016-05-12 07:06:04 -07003246 int i;
3247
3248 if (WARN_ON(!state))
3249 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003250
Matt Ropera1de91e2016-05-12 07:05:57 -07003251 /* Calculate and cache data rate for each plane */
Matt Ropera6d3460e2016-05-12 07:06:04 -07003252 for_each_plane_in_state(state, plane, pstate, i) {
3253 id = skl_wm_plane_id(to_intel_plane(plane));
3254 intel_plane = to_intel_plane(plane);
Matt Roper024c9042015-09-24 15:53:11 -07003255
Matt Ropera6d3460e2016-05-12 07:06:04 -07003256 if (intel_plane->pipe != intel_crtc->pipe)
3257 continue;
Matt Roper024c9042015-09-24 15:53:11 -07003258
Matt Ropera6d3460e2016-05-12 07:06:04 -07003259 /* packed/uv */
3260 rate = skl_plane_relative_data_rate(intel_cstate,
3261 pstate, 0);
3262 intel_cstate->wm.skl.plane_data_rate[id] = rate;
Matt Roper9c74d822016-05-12 07:05:58 -07003263
Matt Ropera6d3460e2016-05-12 07:06:04 -07003264 /* y-plane */
3265 rate = skl_plane_relative_data_rate(intel_cstate,
3266 pstate, 1);
3267 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
Matt Ropera1de91e2016-05-12 07:05:57 -07003268 }
3269
3270 /* Calculate CRTC's total data rate from cached values */
3271 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272 int id = skl_wm_plane_id(intel_plane);
3273
3274 /* packed/uv */
Matt Roper9c74d822016-05-12 07:05:58 -07003275 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3276 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
Damien Lespiaub9cec072014-11-04 17:06:43 +00003277 }
3278
3279 return total_data_rate;
3280}
3281
Kumar, Maheshcbcfd142016-05-31 09:58:59 -07003282static uint16_t
3283skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3284 const int y)
3285{
3286 struct drm_framebuffer *fb = pstate->fb;
3287 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3288 uint32_t src_w, src_h;
3289 uint32_t min_scanlines = 8;
3290 uint8_t plane_bpp;
3291
3292 if (WARN_ON(!fb))
3293 return 0;
3294
3295 /* For packed formats, no y-plane, return 0 */
3296 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3297 return 0;
3298
3299 /* For Non Y-tile return 8-blocks */
3300 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3301 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3302 return 8;
3303
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003304 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3305 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
Kumar, Maheshcbcfd142016-05-31 09:58:59 -07003306
3307 if (intel_rotation_90_or_270(pstate->rotation))
3308 swap(src_w, src_h);
3309
3310 /* Halve UV plane width and height for NV12 */
3311 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3312 src_w /= 2;
3313 src_h /= 2;
3314 }
3315
3316 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3317 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3318 else
3319 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3320
3321 if (intel_rotation_90_or_270(pstate->rotation)) {
3322 switch (plane_bpp) {
3323 case 1:
3324 min_scanlines = 32;
3325 break;
3326 case 2:
3327 min_scanlines = 16;
3328 break;
3329 case 4:
3330 min_scanlines = 8;
3331 break;
3332 case 8:
3333 min_scanlines = 4;
3334 break;
3335 default:
3336 WARN(1, "Unsupported pixel depth %u for rotation",
3337 plane_bpp);
3338 min_scanlines = 32;
3339 }
3340 }
3341
3342 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3343}
3344
Matt Roperc107acf2016-05-12 07:06:01 -07003345static int
Matt Roper024c9042015-09-24 15:53:11 -07003346skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
Damien Lespiaub9cec072014-11-04 17:06:43 +00003347 struct skl_ddb_allocation *ddb /* out */)
3348{
Matt Roperc107acf2016-05-12 07:06:01 -07003349 struct drm_atomic_state *state = cstate->base.state;
Matt Roper024c9042015-09-24 15:53:11 -07003350 struct drm_crtc *crtc = cstate->base.crtc;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003351 struct drm_device *dev = crtc->dev;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper024c9042015-09-24 15:53:11 -07003353 struct intel_plane *intel_plane;
Matt Roperc107acf2016-05-12 07:06:01 -07003354 struct drm_plane *plane;
3355 struct drm_plane_state *pstate;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003356 enum pipe pipe = intel_crtc->pipe;
Damien Lespiau34bb56a2014-11-04 17:07:01 +00003357 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
Damien Lespiaub9cec072014-11-04 17:06:43 +00003358 uint16_t alloc_size, start, cursor_blocks;
Matt Roper86a2100a2016-05-12 07:05:59 -07003359 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3360 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003361 unsigned int total_data_rate;
Matt Roperc107acf2016-05-12 07:06:01 -07003362 int num_active;
3363 int id, i;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003364
Matt Ropera6d3460e2016-05-12 07:06:04 -07003365 if (WARN_ON(!state))
3366 return 0;
3367
Matt Roperc107acf2016-05-12 07:06:01 -07003368 if (!cstate->base.active) {
3369 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3370 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3371 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3372 return 0;
3373 }
3374
Matt Ropera6d3460e2016-05-12 07:06:04 -07003375 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
Damien Lespiau34bb56a2014-11-04 17:07:01 +00003376 alloc_size = skl_ddb_entry_size(alloc);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003377 if (alloc_size == 0) {
3378 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
Matt Roperc107acf2016-05-12 07:06:01 -07003379 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003380 }
3381
Matt Roperc107acf2016-05-12 07:06:01 -07003382 cursor_blocks = skl_cursor_allocation(num_active);
Matt Roper4969d332015-09-24 15:53:10 -07003383 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3384 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003385
3386 alloc_size -= cursor_blocks;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003387
Damien Lespiau80958152015-02-09 13:35:10 +00003388 /* 1. Allocate the mininum required blocks for each active plane */
Matt Ropera6d3460e2016-05-12 07:06:04 -07003389 for_each_plane_in_state(state, plane, pstate, i) {
3390 intel_plane = to_intel_plane(plane);
3391 id = skl_wm_plane_id(intel_plane);
Damien Lespiau80958152015-02-09 13:35:10 +00003392
Matt Ropera6d3460e2016-05-12 07:06:04 -07003393 if (intel_plane->pipe != pipe)
3394 continue;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003395
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003396 if (!to_intel_plane_state(pstate)->base.visible) {
Matt Ropera6d3460e2016-05-12 07:06:04 -07003397 minimum[id] = 0;
3398 y_minimum[id] = 0;
3399 continue;
Matt Roperc107acf2016-05-12 07:06:01 -07003400 }
Matt Ropera6d3460e2016-05-12 07:06:04 -07003401 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3402 minimum[id] = 0;
3403 y_minimum[id] = 0;
3404 continue;
Matt Roperc107acf2016-05-12 07:06:01 -07003405 }
Matt Ropera6d3460e2016-05-12 07:06:04 -07003406
Kumar, Maheshcbcfd142016-05-31 09:58:59 -07003407 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3408 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
Matt Roperc107acf2016-05-12 07:06:01 -07003409 }
3410
3411 for (i = 0; i < PLANE_CURSOR; i++) {
3412 alloc_size -= minimum[i];
3413 alloc_size -= y_minimum[i];
Damien Lespiau80958152015-02-09 13:35:10 +00003414 }
3415
Damien Lespiaub9cec072014-11-04 17:06:43 +00003416 /*
Damien Lespiau80958152015-02-09 13:35:10 +00003417 * 2. Distribute the remaining space in proportion to the amount of
3418 * data each plane needs to fetch from memory.
Damien Lespiaub9cec072014-11-04 17:06:43 +00003419 *
3420 * FIXME: we may not allocate every single block here.
3421 */
Matt Roper024c9042015-09-24 15:53:11 -07003422 total_data_rate = skl_get_total_relative_data_rate(cstate);
Matt Ropera1de91e2016-05-12 07:05:57 -07003423 if (total_data_rate == 0)
Matt Roperc107acf2016-05-12 07:06:01 -07003424 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003425
Damien Lespiau34bb56a2014-11-04 17:07:01 +00003426 start = alloc->start;
Matt Roper024c9042015-09-24 15:53:11 -07003427 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003428 unsigned int data_rate, y_data_rate;
3429 uint16_t plane_blocks, y_plane_blocks = 0;
Matt Roper024c9042015-09-24 15:53:11 -07003430 int id = skl_wm_plane_id(intel_plane);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003431
Matt Ropera1de91e2016-05-12 07:05:57 -07003432 data_rate = cstate->wm.skl.plane_data_rate[id];
Damien Lespiaub9cec072014-11-04 17:06:43 +00003433
3434 /*
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003435 * allocation for (packed formats) or (uv-plane part of planar format):
Damien Lespiaub9cec072014-11-04 17:06:43 +00003436 * promote the expression to 64 bits to avoid overflowing, the
3437 * result is < available as data_rate / total_data_rate < 1
3438 */
Matt Roper024c9042015-09-24 15:53:11 -07003439 plane_blocks = minimum[id];
Damien Lespiau80958152015-02-09 13:35:10 +00003440 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3441 total_data_rate);
Damien Lespiaub9cec072014-11-04 17:06:43 +00003442
Matt Roperc107acf2016-05-12 07:06:01 -07003443 /* Leave disabled planes at (0,0) */
3444 if (data_rate) {
3445 ddb->plane[pipe][id].start = start;
3446 ddb->plane[pipe][id].end = start + plane_blocks;
3447 }
Damien Lespiaub9cec072014-11-04 17:06:43 +00003448
3449 start += plane_blocks;
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003450
3451 /*
3452 * allocation for y_plane part of planar format:
3453 */
Matt Ropera1de91e2016-05-12 07:05:57 -07003454 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003455
Matt Ropera1de91e2016-05-12 07:05:57 -07003456 y_plane_blocks = y_minimum[id];
3457 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3458 total_data_rate);
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003459
Matt Roperc107acf2016-05-12 07:06:01 -07003460 if (y_data_rate) {
3461 ddb->y_plane[pipe][id].start = start;
3462 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3463 }
Chandra Konduru2cd601c2015-04-27 15:47:37 -07003464
Matt Ropera1de91e2016-05-12 07:05:57 -07003465 start += y_plane_blocks;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003466 }
3467
Matt Roperc107acf2016-05-12 07:06:01 -07003468 return 0;
Damien Lespiaub9cec072014-11-04 17:06:43 +00003469}
3470
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02003471static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003472{
3473 /* TODO: Take into account the scalers once we support them */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02003474 return config->base.adjusted_mode.crtc_clock;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003475}
3476
3477/*
3478 * The max latency should be 257 (max the punit can code is 255 and we add 2us
Ville Syrjäläac484962016-01-20 21:05:26 +02003479 * for the read latency) and cpp should always be <= 8, so that
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003480 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3481 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3482*/
Ville Syrjäläac484962016-01-20 21:05:26 +02003483static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003484{
3485 uint32_t wm_intermediate_val, ret;
3486
3487 if (latency == 0)
3488 return UINT_MAX;
3489
Ville Syrjäläac484962016-01-20 21:05:26 +02003490 wm_intermediate_val = latency * pixel_rate * cpp / 512;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003491 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3492
3493 return ret;
3494}
3495
3496static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
Ville Syrjäläac484962016-01-20 21:05:26 +02003497 uint32_t horiz_pixels, uint8_t cpp,
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003498 uint64_t tiling, uint32_t latency)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003499{
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003500 uint32_t ret;
3501 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3502 uint32_t wm_intermediate_val;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003503
3504 if (latency == 0)
3505 return UINT_MAX;
3506
Ville Syrjäläac484962016-01-20 21:05:26 +02003507 plane_bytes_per_line = horiz_pixels * cpp;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003508
3509 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3510 tiling == I915_FORMAT_MOD_Yf_TILED) {
3511 plane_bytes_per_line *= 4;
3512 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3513 plane_blocks_per_line /= 4;
Matt Roper055c3ff2016-08-04 14:08:00 -07003514 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3515 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003516 } else {
3517 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3518 }
3519
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003520 wm_intermediate_val = latency * pixel_rate;
3521 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003522 plane_blocks_per_line;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003523
3524 return ret;
3525}
3526
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003527static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3528 struct intel_plane_state *pstate)
3529{
3530 uint64_t adjusted_pixel_rate;
3531 uint64_t downscale_amount;
3532 uint64_t pixel_rate;
3533
3534 /* Shouldn't reach here on disabled planes... */
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003535 if (WARN_ON(!pstate->base.visible))
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003536 return 0;
3537
3538 /*
3539 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3540 * with additional adjustments for plane-specific scaling.
3541 */
3542 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3543 downscale_amount = skl_plane_downscale_amount(pstate);
3544
3545 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3546 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3547
3548 return pixel_rate;
3549}
3550
Matt Roper55994c22016-05-12 07:06:08 -07003551static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3552 struct intel_crtc_state *cstate,
3553 struct intel_plane_state *intel_pstate,
3554 uint16_t ddb_allocation,
3555 int level,
3556 uint16_t *out_blocks, /* out */
3557 uint8_t *out_lines, /* out */
3558 bool *enabled /* out */)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003559{
Matt Roper33815fa2016-05-12 07:06:05 -07003560 struct drm_plane_state *pstate = &intel_pstate->base;
3561 struct drm_framebuffer *fb = pstate->fb;
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003562 uint32_t latency = dev_priv->wm.skl_latency[level];
3563 uint32_t method1, method2;
3564 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3565 uint32_t res_blocks, res_lines;
3566 uint32_t selected_result;
Ville Syrjäläac484962016-01-20 21:05:26 +02003567 uint8_t cpp;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003568 uint32_t width = 0, height = 0;
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003569 uint32_t plane_pixel_rate;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003570
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003571 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
Matt Roper55994c22016-05-12 07:06:08 -07003572 *enabled = false;
3573 return 0;
3574 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003575
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003576 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3577 height = drm_rect_height(&intel_pstate->base.src) >> 16;
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003578
Matt Roper33815fa2016-05-12 07:06:05 -07003579 if (intel_rotation_90_or_270(pstate->rotation))
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003580 swap(width, height);
3581
Ville Syrjäläac484962016-01-20 21:05:26 +02003582 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
Kumar, Mahesh9c2f7a92016-05-16 15:52:00 -07003583 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3584
3585 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3586 method2 = skl_wm_method2(plane_pixel_rate,
Matt Roper024c9042015-09-24 15:53:11 -07003587 cstate->base.adjusted_mode.crtc_htotal,
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003588 width,
3589 cpp,
3590 fb->modifier[0],
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003591 latency);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003592
Kumar, Mahesha280f7d2016-04-06 08:26:39 -07003593 plane_bytes_per_line = width * cpp;
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003594 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003595
Matt Roper024c9042015-09-24 15:53:11 -07003596 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3597 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00003598 uint32_t min_scanlines = 4;
3599 uint32_t y_tile_minimum;
Matt Roper33815fa2016-05-12 07:06:05 -07003600 if (intel_rotation_90_or_270(pstate->rotation)) {
Ville Syrjäläac484962016-01-20 21:05:26 +02003601 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
Matt Roper024c9042015-09-24 15:53:11 -07003602 drm_format_plane_cpp(fb->pixel_format, 1) :
3603 drm_format_plane_cpp(fb->pixel_format, 0);
3604
Ville Syrjäläac484962016-01-20 21:05:26 +02003605 switch (cpp) {
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00003606 case 1:
3607 min_scanlines = 16;
3608 break;
3609 case 2:
3610 min_scanlines = 8;
3611 break;
3612 case 8:
3613 WARN(1, "Unsupported pixel depth for rotation");
kbuild test robot2f0b5792015-03-26 22:30:21 +08003614 }
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00003615 }
3616 y_tile_minimum = plane_blocks_per_line * min_scanlines;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003617 selected_result = max(method2, y_tile_minimum);
3618 } else {
3619 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3620 selected_result = min(method1, method2);
3621 else
3622 selected_result = method1;
3623 }
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003624
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003625 res_blocks = selected_result + 1;
3626 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
Damien Lespiaue6d66172014-11-04 17:06:55 +00003627
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003628 if (level >= 1 && level <= 7) {
Matt Roper024c9042015-09-24 15:53:11 -07003629 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3630 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +00003631 res_lines += 4;
3632 else
3633 res_blocks++;
3634 }
Tvrtko Ursulind4c2aa62015-02-27 11:15:22 +00003635
Matt Roper55994c22016-05-12 07:06:08 -07003636 if (res_blocks >= ddb_allocation || res_lines > 31) {
3637 *enabled = false;
Matt Roper6b6bada2016-05-12 07:06:10 -07003638
3639 /*
3640 * If there are no valid level 0 watermarks, then we can't
3641 * support this display configuration.
3642 */
3643 if (level) {
3644 return 0;
3645 } else {
3646 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3647 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3648 to_intel_crtc(cstate->base.crtc)->pipe,
3649 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3650 res_blocks, ddb_allocation, res_lines);
3651
3652 return -EINVAL;
3653 }
Matt Roper55994c22016-05-12 07:06:08 -07003654 }
Damien Lespiaue6d66172014-11-04 17:06:55 +00003655
3656 *out_blocks = res_blocks;
3657 *out_lines = res_lines;
Matt Roper55994c22016-05-12 07:06:08 -07003658 *enabled = true;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003659
Matt Roper55994c22016-05-12 07:06:08 -07003660 return 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003661}
3662
Matt Roperf4a96752016-05-12 07:06:06 -07003663static int
3664skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3665 struct skl_ddb_allocation *ddb,
3666 struct intel_crtc_state *cstate,
3667 int level,
3668 struct skl_wm_level *result)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003669{
Matt Roperf4a96752016-05-12 07:06:06 -07003670 struct drm_atomic_state *state = cstate->base.state;
Matt Roper024c9042015-09-24 15:53:11 -07003671 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
Matt Roperf4a96752016-05-12 07:06:06 -07003672 struct drm_plane *plane;
Matt Roper024c9042015-09-24 15:53:11 -07003673 struct intel_plane *intel_plane;
Matt Roper33815fa2016-05-12 07:06:05 -07003674 struct intel_plane_state *intel_pstate;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003675 uint16_t ddb_blocks;
Matt Roper024c9042015-09-24 15:53:11 -07003676 enum pipe pipe = intel_crtc->pipe;
Matt Roper55994c22016-05-12 07:06:08 -07003677 int ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003678
Matt Roperf4a96752016-05-12 07:06:06 -07003679 /*
3680 * We'll only calculate watermarks for planes that are actually
3681 * enabled, so make sure all other planes are set as disabled.
3682 */
3683 memset(result, 0, sizeof(*result));
3684
Chris Wilson91c8a322016-07-05 10:40:23 +01003685 for_each_intel_plane_mask(&dev_priv->drm,
3686 intel_plane,
3687 cstate->base.plane_mask) {
Matt Roper024c9042015-09-24 15:53:11 -07003688 int i = skl_wm_plane_id(intel_plane);
3689
Matt Roperf4a96752016-05-12 07:06:06 -07003690 plane = &intel_plane->base;
3691 intel_pstate = NULL;
3692 if (state)
3693 intel_pstate =
3694 intel_atomic_get_existing_plane_state(state,
3695 intel_plane);
3696
3697 /*
3698 * Note: If we start supporting multiple pending atomic commits
3699 * against the same planes/CRTC's in the future, plane->state
3700 * will no longer be the correct pre-state to use for the
3701 * calculations here and we'll need to change where we get the
3702 * 'unchanged' plane data from.
3703 *
3704 * For now this is fine because we only allow one queued commit
3705 * against a CRTC. Even if the plane isn't modified by this
3706 * transaction and we don't have a plane lock, we still have
3707 * the CRTC's lock, so we know that no other transactions are
3708 * racing with us to update it.
3709 */
3710 if (!intel_pstate)
3711 intel_pstate = to_intel_plane_state(plane->state);
3712
3713 WARN_ON(!intel_pstate->base.fb);
3714
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003715 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3716
Matt Roper55994c22016-05-12 07:06:08 -07003717 ret = skl_compute_plane_wm(dev_priv,
3718 cstate,
3719 intel_pstate,
3720 ddb_blocks,
3721 level,
3722 &result->plane_res_b[i],
3723 &result->plane_res_l[i],
3724 &result->plane_en[i]);
3725 if (ret)
3726 return ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003727 }
Matt Roperf4a96752016-05-12 07:06:06 -07003728
3729 return 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003730}
3731
Damien Lespiau407b50f2014-11-04 17:06:57 +00003732static uint32_t
Matt Roper024c9042015-09-24 15:53:11 -07003733skl_compute_linetime_wm(struct intel_crtc_state *cstate)
Damien Lespiau407b50f2014-11-04 17:06:57 +00003734{
Matt Roper024c9042015-09-24 15:53:11 -07003735 if (!cstate->base.active)
Damien Lespiau407b50f2014-11-04 17:06:57 +00003736 return 0;
3737
Matt Roper024c9042015-09-24 15:53:11 -07003738 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
Mika Kuoppala661abfc2015-07-16 19:36:51 +03003739 return 0;
Damien Lespiau407b50f2014-11-04 17:06:57 +00003740
Matt Roper024c9042015-09-24 15:53:11 -07003741 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3742 skl_pipe_pixel_rate(cstate));
Damien Lespiau407b50f2014-11-04 17:06:57 +00003743}
3744
Matt Roper024c9042015-09-24 15:53:11 -07003745static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
Damien Lespiau9414f562014-11-04 17:06:58 +00003746 struct skl_wm_level *trans_wm /* out */)
Damien Lespiau407b50f2014-11-04 17:06:57 +00003747{
Matt Roper024c9042015-09-24 15:53:11 -07003748 struct drm_crtc *crtc = cstate->base.crtc;
Damien Lespiau9414f562014-11-04 17:06:58 +00003749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper024c9042015-09-24 15:53:11 -07003750 struct intel_plane *intel_plane;
Damien Lespiau9414f562014-11-04 17:06:58 +00003751
Matt Roper024c9042015-09-24 15:53:11 -07003752 if (!cstate->base.active)
Damien Lespiau407b50f2014-11-04 17:06:57 +00003753 return;
Damien Lespiau9414f562014-11-04 17:06:58 +00003754
3755 /* Until we know more, just disable transition WMs */
Matt Roper024c9042015-09-24 15:53:11 -07003756 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3757 int i = skl_wm_plane_id(intel_plane);
3758
Damien Lespiau9414f562014-11-04 17:06:58 +00003759 trans_wm->plane_en[i] = false;
Matt Roper024c9042015-09-24 15:53:11 -07003760 }
Damien Lespiau407b50f2014-11-04 17:06:57 +00003761}
3762
Matt Roper55994c22016-05-12 07:06:08 -07003763static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3764 struct skl_ddb_allocation *ddb,
3765 struct skl_pipe_wm *pipe_wm)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003766{
Matt Roper024c9042015-09-24 15:53:11 -07003767 struct drm_device *dev = cstate->base.crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003768 const struct drm_i915_private *dev_priv = to_i915(dev);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003769 int level, max_level = ilk_wm_max_level(dev);
Matt Roper55994c22016-05-12 07:06:08 -07003770 int ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003771
3772 for (level = 0; level <= max_level; level++) {
Matt Roper55994c22016-05-12 07:06:08 -07003773 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3774 level, &pipe_wm->wm[level]);
3775 if (ret)
3776 return ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003777 }
Matt Roper024c9042015-09-24 15:53:11 -07003778 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003779
Matt Roper024c9042015-09-24 15:53:11 -07003780 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
Matt Roper55994c22016-05-12 07:06:08 -07003781
3782 return 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003783}
3784
3785static void skl_compute_wm_results(struct drm_device *dev,
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003786 struct skl_pipe_wm *p_wm,
3787 struct skl_wm_values *r,
3788 struct intel_crtc *intel_crtc)
3789{
3790 int level, max_level = ilk_wm_max_level(dev);
3791 enum pipe pipe = intel_crtc->pipe;
Damien Lespiau9414f562014-11-04 17:06:58 +00003792 uint32_t temp;
3793 int i;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003794
3795 for (level = 0; level <= max_level; level++) {
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003796 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3797 temp = 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003798
3799 temp |= p_wm->wm[level].plane_res_l[i] <<
3800 PLANE_WM_LINES_SHIFT;
3801 temp |= p_wm->wm[level].plane_res_b[i];
3802 if (p_wm->wm[level].plane_en[i])
3803 temp |= PLANE_WM_EN;
3804
3805 r->plane[pipe][i][level] = temp;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003806 }
3807
3808 temp = 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003809
Matt Roper4969d332015-09-24 15:53:10 -07003810 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3811 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003812
Matt Roper4969d332015-09-24 15:53:10 -07003813 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003814 temp |= PLANE_WM_EN;
3815
Matt Roper4969d332015-09-24 15:53:10 -07003816 r->plane[pipe][PLANE_CURSOR][level] = temp;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003817
3818 }
3819
Damien Lespiau9414f562014-11-04 17:06:58 +00003820 /* transition WMs */
3821 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3822 temp = 0;
3823 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3824 temp |= p_wm->trans_wm.plane_res_b[i];
3825 if (p_wm->trans_wm.plane_en[i])
3826 temp |= PLANE_WM_EN;
3827
3828 r->plane_trans[pipe][i] = temp;
3829 }
3830
3831 temp = 0;
Matt Roper4969d332015-09-24 15:53:10 -07003832 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3833 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3834 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
Damien Lespiau9414f562014-11-04 17:06:58 +00003835 temp |= PLANE_WM_EN;
3836
Matt Roper4969d332015-09-24 15:53:10 -07003837 r->plane_trans[pipe][PLANE_CURSOR] = temp;
Damien Lespiau9414f562014-11-04 17:06:58 +00003838
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003839 r->wm_linetime[pipe] = p_wm->linetime;
3840}
3841
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003842static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3843 i915_reg_t reg,
Damien Lespiau16160e32014-11-04 17:06:53 +00003844 const struct skl_ddb_entry *entry)
3845{
3846 if (entry->end)
3847 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3848 else
3849 I915_WRITE(reg, 0);
3850}
3851
Lyude62e0fb82016-08-22 12:50:08 -04003852void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3853 const struct skl_wm_values *wm,
3854 int plane)
3855{
3856 struct drm_crtc *crtc = &intel_crtc->base;
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = to_i915(dev);
3859 int level, max_level = ilk_wm_max_level(dev);
3860 enum pipe pipe = intel_crtc->pipe;
3861
3862 for (level = 0; level <= max_level; level++) {
3863 I915_WRITE(PLANE_WM(pipe, plane, level),
3864 wm->plane[pipe][plane][level]);
3865 }
3866 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
Lyude27082492016-08-24 07:48:10 +02003867
3868 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3869 &wm->ddb.plane[pipe][plane]);
3870 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3871 &wm->ddb.y_plane[pipe][plane]);
Lyude62e0fb82016-08-22 12:50:08 -04003872}
3873
3874void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3875 const struct skl_wm_values *wm)
3876{
3877 struct drm_crtc *crtc = &intel_crtc->base;
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = to_i915(dev);
3880 int level, max_level = ilk_wm_max_level(dev);
3881 enum pipe pipe = intel_crtc->pipe;
3882
3883 for (level = 0; level <= max_level; level++) {
3884 I915_WRITE(CUR_WM(pipe, level),
3885 wm->plane[pipe][PLANE_CURSOR][level]);
3886 }
3887 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
Lyude27082492016-08-24 07:48:10 +02003888
3889 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3890 &wm->ddb.plane[pipe][PLANE_CURSOR]);
Lyude62e0fb82016-08-22 12:50:08 -04003891}
3892
Lyude27082492016-08-24 07:48:10 +02003893bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3894 const struct skl_ddb_allocation *new,
3895 enum pipe pipe)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003896{
Lyude27082492016-08-24 07:48:10 +02003897 return new->pipe[pipe].start == old->pipe[pipe].start &&
3898 new->pipe[pipe].end == old->pipe[pipe].end;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003899}
3900
Lyude27082492016-08-24 07:48:10 +02003901static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3902 const struct skl_ddb_entry *b)
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003903{
Lyude27082492016-08-24 07:48:10 +02003904 return a->start < b->end && b->start < a->end;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003905}
3906
Lyude27082492016-08-24 07:48:10 +02003907bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3908 const struct skl_ddb_allocation *old,
3909 const struct skl_ddb_allocation *new,
3910 enum pipe pipe)
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003911{
Lyude27082492016-08-24 07:48:10 +02003912 struct drm_device *dev = state->dev;
3913 struct intel_crtc *intel_crtc;
3914 enum pipe otherp;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003915
Lyude27082492016-08-24 07:48:10 +02003916 for_each_intel_crtc(dev, intel_crtc) {
3917 otherp = intel_crtc->pipe;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003918
Lyude27082492016-08-24 07:48:10 +02003919 if (otherp == pipe)
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003920 continue;
3921
Lyude27082492016-08-24 07:48:10 +02003922 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3923 &old->pipe[otherp]))
3924 return true;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003925 }
3926
Lyude27082492016-08-24 07:48:10 +02003927 return false;
Damien Lespiau0e8fb7b2014-11-04 17:07:02 +00003928}
3929
Matt Roper55994c22016-05-12 07:06:08 -07003930static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3931 struct skl_ddb_allocation *ddb, /* out */
3932 struct skl_pipe_wm *pipe_wm, /* out */
3933 bool *changed /* out */)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003934{
Matt Roperf4a96752016-05-12 07:06:06 -07003935 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3936 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
Matt Roper55994c22016-05-12 07:06:08 -07003937 int ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003938
Matt Roper55994c22016-05-12 07:06:08 -07003939 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3940 if (ret)
3941 return ret;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003942
Matt Roper4e0963c2015-09-24 15:53:15 -07003943 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
Matt Roper55994c22016-05-12 07:06:08 -07003944 *changed = false;
3945 else
3946 *changed = true;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003947
Matt Roper55994c22016-05-12 07:06:08 -07003948 return 0;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00003949}
3950
Matt Roper9b613022016-06-27 16:42:44 -07003951static uint32_t
3952pipes_modified(struct drm_atomic_state *state)
3953{
3954 struct drm_crtc *crtc;
3955 struct drm_crtc_state *cstate;
3956 uint32_t i, ret = 0;
3957
3958 for_each_crtc_in_state(state, crtc, cstate, i)
3959 ret |= drm_crtc_mask(crtc);
3960
3961 return ret;
3962}
3963
Matt Roper98d39492016-05-12 07:06:03 -07003964static int
3965skl_compute_ddb(struct drm_atomic_state *state)
3966{
3967 struct drm_device *dev = state->dev;
3968 struct drm_i915_private *dev_priv = to_i915(dev);
3969 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3970 struct intel_crtc *intel_crtc;
Matt Roper734fa012016-05-12 15:11:40 -07003971 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
Matt Roper9b613022016-06-27 16:42:44 -07003972 uint32_t realloc_pipes = pipes_modified(state);
Matt Roper98d39492016-05-12 07:06:03 -07003973 int ret;
3974
3975 /*
3976 * If this is our first atomic update following hardware readout,
3977 * we can't trust the DDB that the BIOS programmed for us. Let's
3978 * pretend that all pipes switched active status so that we'll
3979 * ensure a full DDB recompute.
3980 */
Matt Roper1b54a882016-06-17 13:42:18 -07003981 if (dev_priv->wm.distrust_bios_wm) {
3982 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3983 state->acquire_ctx);
3984 if (ret)
3985 return ret;
3986
Matt Roper98d39492016-05-12 07:06:03 -07003987 intel_state->active_pipe_changes = ~0;
3988
Matt Roper1b54a882016-06-17 13:42:18 -07003989 /*
3990 * We usually only initialize intel_state->active_crtcs if we
3991 * we're doing a modeset; make sure this field is always
3992 * initialized during the sanitization process that happens
3993 * on the first commit too.
3994 */
3995 if (!intel_state->modeset)
3996 intel_state->active_crtcs = dev_priv->active_crtcs;
3997 }
3998
Matt Roper98d39492016-05-12 07:06:03 -07003999 /*
4000 * If the modeset changes which CRTC's are active, we need to
4001 * recompute the DDB allocation for *all* active pipes, even
4002 * those that weren't otherwise being modified in any way by this
4003 * atomic commit. Due to the shrinking of the per-pipe allocations
4004 * when new active CRTC's are added, it's possible for a pipe that
4005 * we were already using and aren't changing at all here to suddenly
4006 * become invalid if its DDB needs exceeds its new allocation.
4007 *
4008 * Note that if we wind up doing a full DDB recompute, we can't let
4009 * any other display updates race with this transaction, so we need
4010 * to grab the lock on *all* CRTC's.
4011 */
Matt Roper734fa012016-05-12 15:11:40 -07004012 if (intel_state->active_pipe_changes) {
Matt Roper98d39492016-05-12 07:06:03 -07004013 realloc_pipes = ~0;
Matt Roper734fa012016-05-12 15:11:40 -07004014 intel_state->wm_results.dirty_pipes = ~0;
4015 }
Matt Roper98d39492016-05-12 07:06:03 -07004016
4017 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4018 struct intel_crtc_state *cstate;
4019
4020 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4021 if (IS_ERR(cstate))
4022 return PTR_ERR(cstate);
4023
Matt Roper734fa012016-05-12 15:11:40 -07004024 ret = skl_allocate_pipe_ddb(cstate, ddb);
Matt Roper98d39492016-05-12 07:06:03 -07004025 if (ret)
4026 return ret;
Lyude05a76d32016-08-17 15:55:57 -04004027
4028 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4029 if (ret)
4030 return ret;
Matt Roper98d39492016-05-12 07:06:03 -07004031 }
4032
4033 return 0;
4034}
4035
Matt Roper2722efb2016-08-17 15:55:55 -04004036static void
4037skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4038 struct skl_wm_values *src,
4039 enum pipe pipe)
4040{
4041 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4042 memcpy(dst->plane[pipe], src->plane[pipe],
4043 sizeof(dst->plane[pipe]));
4044 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4045 sizeof(dst->plane_trans[pipe]));
4046
4047 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4048 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4049 sizeof(dst->ddb.y_plane[pipe]));
4050 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4051 sizeof(dst->ddb.plane[pipe]));
4052}
4053
Matt Roper98d39492016-05-12 07:06:03 -07004054static int
4055skl_compute_wm(struct drm_atomic_state *state)
4056{
4057 struct drm_crtc *crtc;
4058 struct drm_crtc_state *cstate;
Matt Roper734fa012016-05-12 15:11:40 -07004059 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4060 struct skl_wm_values *results = &intel_state->wm_results;
4061 struct skl_pipe_wm *pipe_wm;
Matt Roper98d39492016-05-12 07:06:03 -07004062 bool changed = false;
Matt Roper734fa012016-05-12 15:11:40 -07004063 int ret, i;
Matt Roper98d39492016-05-12 07:06:03 -07004064
4065 /*
4066 * If this transaction isn't actually touching any CRTC's, don't
4067 * bother with watermark calculation. Note that if we pass this
4068 * test, we're guaranteed to hold at least one CRTC state mutex,
4069 * which means we can safely use values like dev_priv->active_crtcs
4070 * since any racing commits that want to update them would need to
4071 * hold _all_ CRTC state mutexes.
4072 */
4073 for_each_crtc_in_state(state, crtc, cstate, i)
4074 changed = true;
4075 if (!changed)
4076 return 0;
4077
Matt Roper734fa012016-05-12 15:11:40 -07004078 /* Clear all dirty flags */
4079 results->dirty_pipes = 0;
4080
Matt Roper98d39492016-05-12 07:06:03 -07004081 ret = skl_compute_ddb(state);
4082 if (ret)
4083 return ret;
4084
Matt Roper734fa012016-05-12 15:11:40 -07004085 /*
4086 * Calculate WM's for all pipes that are part of this transaction.
4087 * Note that the DDB allocation above may have added more CRTC's that
4088 * weren't otherwise being modified (and set bits in dirty_pipes) if
4089 * pipe allocations had to change.
4090 *
4091 * FIXME: Now that we're doing this in the atomic check phase, we
4092 * should allow skl_update_pipe_wm() to return failure in cases where
4093 * no suitable watermark values can be found.
4094 */
4095 for_each_crtc_in_state(state, crtc, cstate, i) {
4096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097 struct intel_crtc_state *intel_cstate =
4098 to_intel_crtc_state(cstate);
4099
4100 pipe_wm = &intel_cstate->wm.skl.optimal;
4101 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4102 &changed);
4103 if (ret)
4104 return ret;
4105
4106 if (changed)
4107 results->dirty_pipes |= drm_crtc_mask(crtc);
4108
4109 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4110 /* This pipe's WM's did not change */
4111 continue;
4112
4113 intel_cstate->update_wm_pre = true;
4114 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4115 }
4116
Matt Roper98d39492016-05-12 07:06:03 -07004117 return 0;
4118}
4119
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004120static void skl_update_wm(struct drm_crtc *crtc)
4121{
4122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4123 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004124 struct drm_i915_private *dev_priv = to_i915(dev);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004125 struct skl_wm_values *results = &dev_priv->wm.skl_results;
Matt Roper2722efb2016-08-17 15:55:55 -04004126 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
Matt Roper4e0963c2015-09-24 15:53:15 -07004127 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
Matt Ropere8f1f022016-05-12 07:05:55 -07004128 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
Lyude27082492016-08-24 07:48:10 +02004129 enum pipe pipe = intel_crtc->pipe;
Bob Paauweadda50b2015-07-21 10:42:53 -07004130
Matt Roper734fa012016-05-12 15:11:40 -07004131 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004132 return;
4133
Matt Roper734fa012016-05-12 15:11:40 -07004134 intel_crtc->wm.active.skl = *pipe_wm;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004135
Matt Roper734fa012016-05-12 15:11:40 -07004136 mutex_lock(&dev_priv->wm.wm_mutex);
4137
Matt Roper2722efb2016-08-17 15:55:55 -04004138 /*
Lyude27082492016-08-24 07:48:10 +02004139 * If this pipe isn't active already, we're going to be enabling it
4140 * very soon. Since it's safe to update a pipe's ddb allocation while
4141 * the pipe's shut off, just do so here. Already active pipes will have
4142 * their watermarks updated once we update their planes.
Matt Roper2722efb2016-08-17 15:55:55 -04004143 */
Lyude27082492016-08-24 07:48:10 +02004144 if (crtc->state->active_changed) {
4145 int plane;
4146
4147 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4148 skl_write_plane_wm(intel_crtc, results, plane);
4149
4150 skl_write_cursor_wm(intel_crtc, results);
4151 }
4152
4153 skl_copy_wm_for_pipe(hw_vals, results, pipe);
Matt Roper734fa012016-05-12 15:11:40 -07004154
4155 mutex_unlock(&dev_priv->wm.wm_mutex);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00004156}
4157
Ville Syrjäläd8905652016-01-14 14:53:35 +02004158static void ilk_compute_wm_config(struct drm_device *dev,
4159 struct intel_wm_config *config)
4160{
4161 struct intel_crtc *crtc;
4162
4163 /* Compute the currently _active_ config */
4164 for_each_intel_crtc(dev, crtc) {
4165 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4166
4167 if (!wm->pipe_enabled)
4168 continue;
4169
4170 config->sprites_enabled |= wm->sprites_enabled;
4171 config->sprites_scaled |= wm->sprites_scaled;
4172 config->num_pipes_active++;
4173 }
4174}
4175
Matt Ropered4a6a72016-02-23 17:20:13 -08004176static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03004177{
Chris Wilson91c8a322016-07-05 10:40:23 +01004178 struct drm_device *dev = &dev_priv->drm;
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07004179 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
Imre Deak820c1982013-12-17 14:46:36 +02004180 struct ilk_wm_maximums max;
Ville Syrjäläd8905652016-01-14 14:53:35 +02004181 struct intel_wm_config config = {};
Imre Deak820c1982013-12-17 14:46:36 +02004182 struct ilk_wm_values results = {};
Ville Syrjälä77c122b2013-08-06 22:24:04 +03004183 enum intel_ddb_partitioning partitioning;
Matt Roper261a27d2015-10-08 15:28:25 -07004184
Ville Syrjäläd8905652016-01-14 14:53:35 +02004185 ilk_compute_wm_config(dev, &config);
4186
4187 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4188 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
Ville Syrjälä0362c782013-10-09 19:17:57 +03004189
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03004190 /* 5/6 split only in single pipe config on IVB+ */
Ville Syrjäläec98c8d2013-10-11 15:26:26 +03004191 if (INTEL_INFO(dev)->gen >= 7 &&
Ville Syrjäläd8905652016-01-14 14:53:35 +02004192 config.num_pipes_active == 1 && config.sprites_enabled) {
4193 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4194 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
Ville Syrjäläa485bfb2013-10-09 19:17:59 +03004195
Imre Deak820c1982013-12-17 14:46:36 +02004196 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
Paulo Zanoni861f3382013-05-31 10:19:21 -03004197 } else {
Ville Syrjälä198a1e92013-10-09 19:17:58 +03004198 best_lp_wm = &lp_wm_1_2;
Paulo Zanoni861f3382013-05-31 10:19:21 -03004199 }
4200
Ville Syrjälä198a1e92013-10-09 19:17:58 +03004201 partitioning = (best_lp_wm == &lp_wm_1_2) ?
Ville Syrjälä77c122b2013-08-06 22:24:04 +03004202 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
Paulo Zanoni861f3382013-05-31 10:19:21 -03004203
Imre Deak820c1982013-12-17 14:46:36 +02004204 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
Ville Syrjälä609cede2013-10-09 19:18:03 +03004205
Imre Deak820c1982013-12-17 14:46:36 +02004206 ilk_write_wm_values(dev_priv, &results);
Paulo Zanoni1011d8c2013-05-09 16:55:50 -03004207}
4208
Matt Ropered4a6a72016-02-23 17:20:13 -08004209static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07004210{
Matt Ropered4a6a72016-02-23 17:20:13 -08004211 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4212 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07004213
Matt Ropered4a6a72016-02-23 17:20:13 -08004214 mutex_lock(&dev_priv->wm.wm_mutex);
Matt Ropere8f1f022016-05-12 07:05:55 -07004215 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
Matt Ropered4a6a72016-02-23 17:20:13 -08004216 ilk_program_watermarks(dev_priv);
4217 mutex_unlock(&dev_priv->wm.wm_mutex);
4218}
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07004219
Matt Ropered4a6a72016-02-23 17:20:13 -08004220static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4221{
4222 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4223 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4224
4225 mutex_lock(&dev_priv->wm.wm_mutex);
4226 if (cstate->wm.need_postvbl_update) {
Matt Ropere8f1f022016-05-12 07:05:55 -07004227 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
Matt Ropered4a6a72016-02-23 17:20:13 -08004228 ilk_program_watermarks(dev_priv);
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07004229 }
Matt Ropered4a6a72016-02-23 17:20:13 -08004230 mutex_unlock(&dev_priv->wm.wm_mutex);
Ville Syrjäläb9d5c832015-09-24 15:53:14 -07004231}
4232
Pradeep Bhat30789992014-11-04 17:06:45 +00004233static void skl_pipe_wm_active_state(uint32_t val,
4234 struct skl_pipe_wm *active,
4235 bool is_transwm,
4236 bool is_cursor,
4237 int i,
4238 int level)
4239{
4240 bool is_enabled = (val & PLANE_WM_EN) != 0;
4241
4242 if (!is_transwm) {
4243 if (!is_cursor) {
4244 active->wm[level].plane_en[i] = is_enabled;
4245 active->wm[level].plane_res_b[i] =
4246 val & PLANE_WM_BLOCKS_MASK;
4247 active->wm[level].plane_res_l[i] =
4248 (val >> PLANE_WM_LINES_SHIFT) &
4249 PLANE_WM_LINES_MASK;
4250 } else {
Matt Roper4969d332015-09-24 15:53:10 -07004251 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4252 active->wm[level].plane_res_b[PLANE_CURSOR] =
Pradeep Bhat30789992014-11-04 17:06:45 +00004253 val & PLANE_WM_BLOCKS_MASK;
Matt Roper4969d332015-09-24 15:53:10 -07004254 active->wm[level].plane_res_l[PLANE_CURSOR] =
Pradeep Bhat30789992014-11-04 17:06:45 +00004255 (val >> PLANE_WM_LINES_SHIFT) &
4256 PLANE_WM_LINES_MASK;
4257 }
4258 } else {
4259 if (!is_cursor) {
4260 active->trans_wm.plane_en[i] = is_enabled;
4261 active->trans_wm.plane_res_b[i] =
4262 val & PLANE_WM_BLOCKS_MASK;
4263 active->trans_wm.plane_res_l[i] =
4264 (val >> PLANE_WM_LINES_SHIFT) &
4265 PLANE_WM_LINES_MASK;
4266 } else {
Matt Roper4969d332015-09-24 15:53:10 -07004267 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4268 active->trans_wm.plane_res_b[PLANE_CURSOR] =
Pradeep Bhat30789992014-11-04 17:06:45 +00004269 val & PLANE_WM_BLOCKS_MASK;
Matt Roper4969d332015-09-24 15:53:10 -07004270 active->trans_wm.plane_res_l[PLANE_CURSOR] =
Pradeep Bhat30789992014-11-04 17:06:45 +00004271 (val >> PLANE_WM_LINES_SHIFT) &
4272 PLANE_WM_LINES_MASK;
4273 }
4274 }
4275}
4276
4277static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4278{
4279 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004280 struct drm_i915_private *dev_priv = to_i915(dev);
Pradeep Bhat30789992014-11-04 17:06:45 +00004281 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper4e0963c2015-09-24 15:53:15 -07004283 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
Matt Ropere8f1f022016-05-12 07:05:55 -07004284 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
Pradeep Bhat30789992014-11-04 17:06:45 +00004285 enum pipe pipe = intel_crtc->pipe;
4286 int level, i, max_level;
4287 uint32_t temp;
4288
4289 max_level = ilk_wm_max_level(dev);
4290
4291 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4292
4293 for (level = 0; level <= max_level; level++) {
4294 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4295 hw->plane[pipe][i][level] =
4296 I915_READ(PLANE_WM(pipe, i, level));
Matt Roper4969d332015-09-24 15:53:10 -07004297 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
Pradeep Bhat30789992014-11-04 17:06:45 +00004298 }
4299
4300 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4301 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
Matt Roper4969d332015-09-24 15:53:10 -07004302 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
Pradeep Bhat30789992014-11-04 17:06:45 +00004303
Matt Roper3ef00282015-03-09 10:19:24 -07004304 if (!intel_crtc->active)
Pradeep Bhat30789992014-11-04 17:06:45 +00004305 return;
4306
Matt Roper2b4b9f32016-05-12 07:06:07 -07004307 hw->dirty_pipes |= drm_crtc_mask(crtc);
Pradeep Bhat30789992014-11-04 17:06:45 +00004308
4309 active->linetime = hw->wm_linetime[pipe];
4310
4311 for (level = 0; level <= max_level; level++) {
4312 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4313 temp = hw->plane[pipe][i][level];
4314 skl_pipe_wm_active_state(temp, active, false,
4315 false, i, level);
4316 }
Matt Roper4969d332015-09-24 15:53:10 -07004317 temp = hw->plane[pipe][PLANE_CURSOR][level];
Pradeep Bhat30789992014-11-04 17:06:45 +00004318 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4319 }
4320
4321 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4322 temp = hw->plane_trans[pipe][i];
4323 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4324 }
4325
Matt Roper4969d332015-09-24 15:53:10 -07004326 temp = hw->plane_trans[pipe][PLANE_CURSOR];
Pradeep Bhat30789992014-11-04 17:06:45 +00004327 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
Matt Roper4e0963c2015-09-24 15:53:15 -07004328
4329 intel_crtc->wm.active.skl = *active;
Pradeep Bhat30789992014-11-04 17:06:45 +00004330}
4331
4332void skl_wm_get_hw_state(struct drm_device *dev)
4333{
Chris Wilsonfac5e232016-07-04 11:34:36 +01004334 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiaua269c582014-11-04 17:06:49 +00004335 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
Pradeep Bhat30789992014-11-04 17:06:45 +00004336 struct drm_crtc *crtc;
4337
Damien Lespiaua269c582014-11-04 17:06:49 +00004338 skl_ddb_get_hw_state(dev_priv, ddb);
Pradeep Bhat30789992014-11-04 17:06:45 +00004339 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4340 skl_pipe_wm_get_hw_state(crtc);
Matt Ropera1de91e2016-05-12 07:05:57 -07004341
Matt Roper279e99d2016-05-12 07:06:02 -07004342 if (dev_priv->active_crtcs) {
4343 /* Fully recompute DDB on first atomic commit */
4344 dev_priv->wm.distrust_bios_wm = true;
4345 } else {
4346 /* Easy/common case; just sanitize DDB now if everything off */
4347 memset(ddb, 0, sizeof(*ddb));
4348 }
Pradeep Bhat30789992014-11-04 17:06:45 +00004349}
4350
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004351static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4352{
4353 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004354 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak820c1982013-12-17 14:46:36 +02004355 struct ilk_wm_values *hw = &dev_priv->wm.hw;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper4e0963c2015-09-24 15:53:15 -07004357 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
Matt Ropere8f1f022016-05-12 07:05:55 -07004358 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004359 enum pipe pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004360 static const i915_reg_t wm0_pipe_reg[] = {
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004361 [PIPE_A] = WM0_PIPEA_ILK,
4362 [PIPE_B] = WM0_PIPEB_ILK,
4363 [PIPE_C] = WM0_PIPEC_IVB,
4364 };
4365
4366 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
Ville Syrjäläa42a5712014-01-07 16:14:08 +02004367 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläce0e0712013-12-05 15:51:36 +02004368 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004369
Ville Syrjälä15606532016-05-13 17:55:17 +03004370 memset(active, 0, sizeof(*active));
4371
Matt Roper3ef00282015-03-09 10:19:24 -07004372 active->pipe_enabled = intel_crtc->active;
Ville Syrjälä2a44b762014-03-07 18:32:09 +02004373
4374 if (active->pipe_enabled) {
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004375 u32 tmp = hw->wm_pipe[pipe];
4376
4377 /*
4378 * For active pipes LP0 watermark is marked as
4379 * enabled, and LP1+ watermaks as disabled since
4380 * we can't really reverse compute them in case
4381 * multiple pipes are active.
4382 */
4383 active->wm[0].enable = true;
4384 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4385 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4386 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4387 active->linetime = hw->wm_linetime[pipe];
4388 } else {
4389 int level, max_level = ilk_wm_max_level(dev);
4390
4391 /*
4392 * For inactive pipes, all watermark levels
4393 * should be marked as enabled but zeroed,
4394 * which is what we'd compute them to.
4395 */
4396 for (level = 0; level <= max_level; level++)
4397 active->wm[level].enable = true;
4398 }
Matt Roper4e0963c2015-09-24 15:53:15 -07004399
4400 intel_crtc->wm.active.ilk = *active;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004401}
4402
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03004403#define _FW_WM(value, plane) \
4404 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4405#define _FW_WM_VLV(value, plane) \
4406 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4407
4408static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4409 struct vlv_wm_values *wm)
4410{
4411 enum pipe pipe;
4412 uint32_t tmp;
4413
4414 for_each_pipe(dev_priv, pipe) {
4415 tmp = I915_READ(VLV_DDL(pipe));
4416
4417 wm->ddl[pipe].primary =
4418 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4419 wm->ddl[pipe].cursor =
4420 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4421 wm->ddl[pipe].sprite[0] =
4422 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4423 wm->ddl[pipe].sprite[1] =
4424 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4425 }
4426
4427 tmp = I915_READ(DSPFW1);
4428 wm->sr.plane = _FW_WM(tmp, SR);
4429 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4430 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4431 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4432
4433 tmp = I915_READ(DSPFW2);
4434 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4435 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4436 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4437
4438 tmp = I915_READ(DSPFW3);
4439 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4440
4441 if (IS_CHERRYVIEW(dev_priv)) {
4442 tmp = I915_READ(DSPFW7_CHV);
4443 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4444 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4445
4446 tmp = I915_READ(DSPFW8_CHV);
4447 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4448 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4449
4450 tmp = I915_READ(DSPFW9_CHV);
4451 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4452 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4453
4454 tmp = I915_READ(DSPHOWM);
4455 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4456 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4457 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4458 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4459 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4460 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4461 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4462 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4463 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4464 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4465 } else {
4466 tmp = I915_READ(DSPFW7);
4467 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4468 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4469
4470 tmp = I915_READ(DSPHOWM);
4471 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4472 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4473 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4474 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4475 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4476 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4477 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4478 }
4479}
4480
4481#undef _FW_WM
4482#undef _FW_WM_VLV
4483
4484void vlv_wm_get_hw_state(struct drm_device *dev)
4485{
4486 struct drm_i915_private *dev_priv = to_i915(dev);
4487 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4488 struct intel_plane *plane;
4489 enum pipe pipe;
4490 u32 val;
4491
4492 vlv_read_wm_values(dev_priv, wm);
4493
4494 for_each_intel_plane(dev, plane) {
4495 switch (plane->base.type) {
4496 int sprite;
4497 case DRM_PLANE_TYPE_CURSOR:
4498 plane->wm.fifo_size = 63;
4499 break;
4500 case DRM_PLANE_TYPE_PRIMARY:
4501 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4502 break;
4503 case DRM_PLANE_TYPE_OVERLAY:
4504 sprite = plane->plane;
4505 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4506 break;
4507 }
4508 }
4509
4510 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4511 wm->level = VLV_WM_LEVEL_PM2;
4512
4513 if (IS_CHERRYVIEW(dev_priv)) {
4514 mutex_lock(&dev_priv->rps.hw_lock);
4515
4516 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4517 if (val & DSP_MAXFIFO_PM5_ENABLE)
4518 wm->level = VLV_WM_LEVEL_PM5;
4519
Ville Syrjälä58590c12015-09-08 21:05:12 +03004520 /*
4521 * If DDR DVFS is disabled in the BIOS, Punit
4522 * will never ack the request. So if that happens
4523 * assume we don't have to enable/disable DDR DVFS
4524 * dynamically. To test that just set the REQ_ACK
4525 * bit to poke the Punit, but don't change the
4526 * HIGH/LOW bits so that we don't actually change
4527 * the current state.
4528 */
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03004529 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
Ville Syrjälä58590c12015-09-08 21:05:12 +03004530 val |= FORCE_DDR_FREQ_REQ_ACK;
4531 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4532
4533 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4534 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4535 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4536 "assuming DDR DVFS is disabled\n");
4537 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4538 } else {
4539 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4540 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4541 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4542 }
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03004543
4544 mutex_unlock(&dev_priv->rps.hw_lock);
4545 }
4546
4547 for_each_pipe(dev_priv, pipe)
4548 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4549 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4550 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4551
4552 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4553 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4554}
4555
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004556void ilk_wm_get_hw_state(struct drm_device *dev)
4557{
Chris Wilsonfac5e232016-07-04 11:34:36 +01004558 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak820c1982013-12-17 14:46:36 +02004559 struct ilk_wm_values *hw = &dev_priv->wm.hw;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004560 struct drm_crtc *crtc;
4561
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01004562 for_each_crtc(dev, crtc)
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004563 ilk_pipe_wm_get_hw_state(crtc);
4564
4565 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4566 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4567 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4568
4569 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
Ville Syrjäläcfa76982014-03-07 18:32:08 +02004570 if (INTEL_INFO(dev)->gen >= 7) {
4571 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4572 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4573 }
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004574
Ville Syrjäläa42a5712014-01-07 16:14:08 +02004575 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjäläac9545f2013-12-05 15:51:28 +02004576 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4577 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4578 else if (IS_IVYBRIDGE(dev))
4579 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4580 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
Ville Syrjälä243e6a42013-10-14 14:55:24 +03004581
4582 hw->enable_fbc_wm =
4583 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4584}
4585
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03004586/**
4587 * intel_update_watermarks - update FIFO watermark values based on current modes
4588 *
4589 * Calculate watermark values for the various WM regs based on current mode
4590 * and plane configuration.
4591 *
4592 * There are several cases to deal with here:
4593 * - normal (i.e. non-self-refresh)
4594 * - self-refresh (SR) mode
4595 * - lines are large relative to FIFO size (buffer can hold up to 2)
4596 * - lines are small relative to FIFO size (buffer can hold more than 2
4597 * lines), so need to account for TLB latency
4598 *
4599 * The normal calculation is:
4600 * watermark = dotclock * bytes per pixel * latency
4601 * where latency is platform & configuration dependent (we assume pessimal
4602 * values here).
4603 *
4604 * The SR calculation is:
4605 * watermark = (trunc(latency/line time)+1) * surface width *
4606 * bytes per pixel
4607 * where
4608 * line time = htotal / dotclock
4609 * surface width = hdisplay for normal plane and 64 for cursor
4610 * and latency is assumed to be high, as above.
4611 *
4612 * The final value programmed to the register should always be rounded up,
4613 * and include an extra 2 entries to account for clock crossings.
4614 *
4615 * We don't use the sprite, so we can ignore that. And on Crestline we have
4616 * to set the non-SR watermarks to 8.
4617 */
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004618void intel_update_watermarks(struct drm_crtc *crtc)
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03004619{
Chris Wilsonfac5e232016-07-04 11:34:36 +01004620 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03004621
4622 if (dev_priv->display.update_wm)
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004623 dev_priv->display.update_wm(crtc);
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -03004624}
4625
Jani Nikulae2828912016-01-18 09:19:47 +02004626/*
Daniel Vetter92703882012-08-09 16:46:01 +02004627 * Lock protecting IPS related data structures
Daniel Vetter92703882012-08-09 16:46:01 +02004628 */
4629DEFINE_SPINLOCK(mchdev_lock);
4630
4631/* Global for IPS driver to get at the current i915 device. Protected by
4632 * mchdev_lock. */
4633static struct drm_i915_private *i915_mch_dev;
4634
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004635bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004636{
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004637 u16 rgvswctl;
4638
Daniel Vetter92703882012-08-09 16:46:01 +02004639 assert_spin_locked(&mchdev_lock);
4640
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004641 rgvswctl = I915_READ16(MEMSWCTL);
4642 if (rgvswctl & MEMCTL_CMD_STS) {
4643 DRM_DEBUG("gpu busy, RCS change rejected\n");
4644 return false; /* still busy with another command */
4645 }
4646
4647 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4648 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4649 I915_WRITE16(MEMSWCTL, rgvswctl);
4650 POSTING_READ16(MEMSWCTL);
4651
4652 rgvswctl |= MEMCTL_CMD_STS;
4653 I915_WRITE16(MEMSWCTL, rgvswctl);
4654
4655 return true;
4656}
4657
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004658static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004659{
Tvrtko Ursulin84f1b202016-02-11 10:27:32 +00004660 u32 rgvmodectl;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004661 u8 fmax, fmin, fstart, vstart;
4662
Daniel Vetter92703882012-08-09 16:46:01 +02004663 spin_lock_irq(&mchdev_lock);
4664
Tvrtko Ursulin84f1b202016-02-11 10:27:32 +00004665 rgvmodectl = I915_READ(MEMMODECTL);
4666
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004667 /* Enable temp reporting */
4668 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4669 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4670
4671 /* 100ms RC evaluation intervals */
4672 I915_WRITE(RCUPEI, 100000);
4673 I915_WRITE(RCDNEI, 100000);
4674
4675 /* Set max/min thresholds to 90ms and 80ms respectively */
4676 I915_WRITE(RCBMAXAVG, 90000);
4677 I915_WRITE(RCBMINAVG, 80000);
4678
4679 I915_WRITE(MEMIHYST, 1);
4680
4681 /* Set up min, max, and cur for interrupt handling */
4682 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4683 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4684 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4685 MEMMODE_FSTART_SHIFT;
4686
Ville Syrjälä616847e2015-09-18 20:03:19 +03004687 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004688 PXVFREQ_PX_SHIFT;
4689
Daniel Vetter20e4d402012-08-08 23:35:39 +02004690 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4691 dev_priv->ips.fstart = fstart;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004692
Daniel Vetter20e4d402012-08-08 23:35:39 +02004693 dev_priv->ips.max_delay = fstart;
4694 dev_priv->ips.min_delay = fmin;
4695 dev_priv->ips.cur_delay = fstart;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004696
4697 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4698 fmax, fmin, fstart);
4699
4700 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4701
4702 /*
4703 * Interrupts will be enabled in ironlake_irq_postinstall
4704 */
4705
4706 I915_WRITE(VIDSTART, vstart);
4707 POSTING_READ(VIDSTART);
4708
4709 rgvmodectl |= MEMMODE_SWMODE_EN;
4710 I915_WRITE(MEMMODECTL, rgvmodectl);
4711
Daniel Vetter92703882012-08-09 16:46:01 +02004712 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004713 DRM_ERROR("stuck trying to change perf mode\n");
Daniel Vetterdd92d8d2015-07-20 10:58:21 +02004714 mdelay(1);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004715
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004716 ironlake_set_drps(dev_priv, fstart);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004717
Ville Syrjälä7d81c3e2015-09-18 20:03:20 +03004718 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4719 I915_READ(DDREC) + I915_READ(CSIEC);
Daniel Vetter20e4d402012-08-08 23:35:39 +02004720 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
Ville Syrjälä7d81c3e2015-09-18 20:03:20 +03004721 dev_priv->ips.last_count2 = I915_READ(GFXEC);
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00004722 dev_priv->ips.last_time2 = ktime_get_raw_ns();
Daniel Vetter92703882012-08-09 16:46:01 +02004723
4724 spin_unlock_irq(&mchdev_lock);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004725}
4726
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004727static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004728{
Daniel Vetter92703882012-08-09 16:46:01 +02004729 u16 rgvswctl;
4730
4731 spin_lock_irq(&mchdev_lock);
4732
4733 rgvswctl = I915_READ16(MEMSWCTL);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004734
4735 /* Ack interrupts, disable EFC interrupt */
4736 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4737 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4738 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4739 I915_WRITE(DEIIR, DE_PCU_EVENT);
4740 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4741
4742 /* Go back to the starting frequency */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004743 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
Daniel Vetterdd92d8d2015-07-20 10:58:21 +02004744 mdelay(1);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004745 rgvswctl |= MEMCTL_CMD_STS;
4746 I915_WRITE(MEMSWCTL, rgvswctl);
Daniel Vetterdd92d8d2015-07-20 10:58:21 +02004747 mdelay(1);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004748
Daniel Vetter92703882012-08-09 16:46:01 +02004749 spin_unlock_irq(&mchdev_lock);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004750}
4751
Daniel Vetteracbe9472012-07-26 11:50:05 +02004752/* There's a funny hw issue where the hw returns all 0 when reading from
4753 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4754 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4755 * all limits and the gpu stuck at whatever frequency it is at atm).
4756 */
Akash Goel74ef1172015-03-06 11:07:19 +05304757static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004758{
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01004759 u32 limits;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004760
Daniel Vetter20b46e52012-07-26 11:16:14 +02004761 /* Only set the down limit when we've reached the lowest level to avoid
4762 * getting more interrupts, otherwise leave this clear. This prevents a
4763 * race in the hw when coming out of rc6: There's a tiny window where
4764 * the hw runs at the minimal clock before selecting the desired
4765 * frequency, if the down threshold expires in that window we will not
4766 * receive a down interrupt. */
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03004767 if (IS_GEN9(dev_priv)) {
Akash Goel74ef1172015-03-06 11:07:19 +05304768 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4769 if (val <= dev_priv->rps.min_freq_softlimit)
4770 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4771 } else {
4772 limits = dev_priv->rps.max_freq_softlimit << 24;
4773 if (val <= dev_priv->rps.min_freq_softlimit)
4774 limits |= dev_priv->rps.min_freq_softlimit << 16;
4775 }
Daniel Vetter20b46e52012-07-26 11:16:14 +02004776
4777 return limits;
4778}
4779
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004780static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4781{
4782 int new_power;
Akash Goel8a586432015-03-06 11:07:18 +05304783 u32 threshold_up = 0, threshold_down = 0; /* in % */
4784 u32 ei_up = 0, ei_down = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004785
4786 new_power = dev_priv->rps.power;
4787 switch (dev_priv->rps.power) {
4788 case LOW_POWER:
Chris Wilsona72b5622016-07-02 15:35:59 +01004789 if (val > dev_priv->rps.efficient_freq + 1 &&
4790 val > dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004791 new_power = BETWEEN;
4792 break;
4793
4794 case BETWEEN:
Chris Wilsona72b5622016-07-02 15:35:59 +01004795 if (val <= dev_priv->rps.efficient_freq &&
4796 val < dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004797 new_power = LOW_POWER;
Chris Wilsona72b5622016-07-02 15:35:59 +01004798 else if (val >= dev_priv->rps.rp0_freq &&
4799 val > dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004800 new_power = HIGH_POWER;
4801 break;
4802
4803 case HIGH_POWER:
Chris Wilsona72b5622016-07-02 15:35:59 +01004804 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4805 val < dev_priv->rps.cur_freq)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004806 new_power = BETWEEN;
4807 break;
4808 }
4809 /* Max/min bins are special */
Chris Wilsonaed242f2015-03-18 09:48:21 +00004810 if (val <= dev_priv->rps.min_freq_softlimit)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004811 new_power = LOW_POWER;
Chris Wilsonaed242f2015-03-18 09:48:21 +00004812 if (val >= dev_priv->rps.max_freq_softlimit)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004813 new_power = HIGH_POWER;
4814 if (new_power == dev_priv->rps.power)
4815 return;
4816
4817 /* Note the units here are not exactly 1us, but 1280ns. */
4818 switch (new_power) {
4819 case LOW_POWER:
4820 /* Upclock if more than 95% busy over 16ms */
Akash Goel8a586432015-03-06 11:07:18 +05304821 ei_up = 16000;
4822 threshold_up = 95;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004823
4824 /* Downclock if less than 85% busy over 32ms */
Akash Goel8a586432015-03-06 11:07:18 +05304825 ei_down = 32000;
4826 threshold_down = 85;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004827 break;
4828
4829 case BETWEEN:
4830 /* Upclock if more than 90% busy over 13ms */
Akash Goel8a586432015-03-06 11:07:18 +05304831 ei_up = 13000;
4832 threshold_up = 90;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004833
4834 /* Downclock if less than 75% busy over 32ms */
Akash Goel8a586432015-03-06 11:07:18 +05304835 ei_down = 32000;
4836 threshold_down = 75;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004837 break;
4838
4839 case HIGH_POWER:
4840 /* Upclock if more than 85% busy over 10ms */
Akash Goel8a586432015-03-06 11:07:18 +05304841 ei_up = 10000;
4842 threshold_up = 85;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004843
4844 /* Downclock if less than 60% busy over 32ms */
Akash Goel8a586432015-03-06 11:07:18 +05304845 ei_down = 32000;
4846 threshold_down = 60;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004847 break;
4848 }
4849
Akash Goel8a586432015-03-06 11:07:18 +05304850 I915_WRITE(GEN6_RP_UP_EI,
Chris Wilsona72b5622016-07-02 15:35:59 +01004851 GT_INTERVAL_FROM_US(dev_priv, ei_up));
Akash Goel8a586432015-03-06 11:07:18 +05304852 I915_WRITE(GEN6_RP_UP_THRESHOLD,
Chris Wilsona72b5622016-07-02 15:35:59 +01004853 GT_INTERVAL_FROM_US(dev_priv,
4854 ei_up * threshold_up / 100));
Akash Goel8a586432015-03-06 11:07:18 +05304855
4856 I915_WRITE(GEN6_RP_DOWN_EI,
Chris Wilsona72b5622016-07-02 15:35:59 +01004857 GT_INTERVAL_FROM_US(dev_priv, ei_down));
Akash Goel8a586432015-03-06 11:07:18 +05304858 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
Chris Wilsona72b5622016-07-02 15:35:59 +01004859 GT_INTERVAL_FROM_US(dev_priv,
4860 ei_down * threshold_down / 100));
Akash Goel8a586432015-03-06 11:07:18 +05304861
Chris Wilsona72b5622016-07-02 15:35:59 +01004862 I915_WRITE(GEN6_RP_CONTROL,
4863 GEN6_RP_MEDIA_TURBO |
4864 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4865 GEN6_RP_MEDIA_IS_GFX |
4866 GEN6_RP_ENABLE |
4867 GEN6_RP_UP_BUSY_AVG |
4868 GEN6_RP_DOWN_IDLE_AVG);
Akash Goel8a586432015-03-06 11:07:18 +05304869
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004870 dev_priv->rps.power = new_power;
Chris Wilson8fb55192015-04-07 16:20:28 +01004871 dev_priv->rps.up_threshold = threshold_up;
4872 dev_priv->rps.down_threshold = threshold_down;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004873 dev_priv->rps.last_adj = 0;
4874}
4875
Chris Wilson2876ce72014-03-28 08:03:34 +00004876static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4877{
4878 u32 mask = 0;
4879
4880 if (val > dev_priv->rps.min_freq_softlimit)
Chris Wilson6f4b12f82015-03-18 09:48:23 +00004881 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
Chris Wilson2876ce72014-03-28 08:03:34 +00004882 if (val < dev_priv->rps.max_freq_softlimit)
Chris Wilson6f4b12f82015-03-18 09:48:23 +00004883 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
Chris Wilson2876ce72014-03-28 08:03:34 +00004884
Chris Wilson7b3c29f2014-07-10 20:31:19 +01004885 mask &= dev_priv->pm_rps_events;
4886
Imre Deak59d02a12014-12-19 19:33:26 +02004887 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
Chris Wilson2876ce72014-03-28 08:03:34 +00004888}
4889
Jeff McGeeb8a5ff82014-02-04 11:37:01 -06004890/* gen6_set_rps is called to update the frequency request, but should also be
4891 * called when the range (min_delay and max_delay) is modified so that we can
4892 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
Chris Wilsondc979972016-05-10 14:10:04 +01004893static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
Daniel Vetter20b46e52012-07-26 11:16:14 +02004894{
Sagar Arun Kamble23eafea2015-08-23 17:52:48 +05304895 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
Chris Wilsondc979972016-05-10 14:10:04 +01004896 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
Sagar Arun Kamble23eafea2015-08-23 17:52:48 +05304897 return;
4898
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004899 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Chris Wilsonaed242f2015-03-18 09:48:21 +00004900 WARN_ON(val > dev_priv->rps.max_freq);
4901 WARN_ON(val < dev_priv->rps.min_freq);
Daniel Vetter004777c2012-08-09 15:07:01 +02004902
Chris Wilsoneb64cad2014-03-27 08:24:20 +00004903 /* min/max delay may still have been modified so be sure to
4904 * write the limits value.
4905 */
4906 if (val != dev_priv->rps.cur_freq) {
4907 gen6_set_rps_thresholds(dev_priv, val);
Jeff McGeeb8a5ff82014-02-04 11:37:01 -06004908
Chris Wilsondc979972016-05-10 14:10:04 +01004909 if (IS_GEN9(dev_priv))
Akash Goel57041952015-03-06 11:07:17 +05304910 I915_WRITE(GEN6_RPNSWREQ,
4911 GEN9_FREQUENCY(val));
Chris Wilsondc979972016-05-10 14:10:04 +01004912 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Chris Wilsoneb64cad2014-03-27 08:24:20 +00004913 I915_WRITE(GEN6_RPNSWREQ,
4914 HSW_FREQUENCY(val));
4915 else
4916 I915_WRITE(GEN6_RPNSWREQ,
4917 GEN6_FREQUENCY(val) |
4918 GEN6_OFFSET(0) |
4919 GEN6_AGGRESSIVE_TURBO);
Jeff McGeeb8a5ff82014-02-04 11:37:01 -06004920 }
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01004921
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01004922 /* Make sure we continue to get interrupts
4923 * until we hit the minimum or maximum frequencies.
4924 */
Akash Goel74ef1172015-03-06 11:07:19 +05304925 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
Chris Wilson2876ce72014-03-28 08:03:34 +00004926 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01004927
Ben Widawskyd5570a72012-09-07 19:43:41 -07004928 POSTING_READ(GEN6_RPNSWREQ);
4929
Ben Widawskyb39fb292014-03-19 18:31:11 -07004930 dev_priv->rps.cur_freq = val;
Mika Kuoppala0f945922015-11-17 18:14:26 +02004931 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03004932}
4933
Chris Wilsondc979972016-05-10 14:10:04 +01004934static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004935{
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004936 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Chris Wilsonaed242f2015-03-18 09:48:21 +00004937 WARN_ON(val > dev_priv->rps.max_freq);
4938 WARN_ON(val < dev_priv->rps.min_freq);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004939
Chris Wilsondc979972016-05-10 14:10:04 +01004940 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004941 "Odd GPU freq value\n"))
4942 val &= ~1;
4943
Deepak Scd25dd52015-07-10 18:31:40 +05304944 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4945
Chris Wilson8fb55192015-04-07 16:20:28 +01004946 if (val != dev_priv->rps.cur_freq) {
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004947 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
Chris Wilson8fb55192015-04-07 16:20:28 +01004948 if (!IS_CHERRYVIEW(dev_priv))
4949 gen6_set_rps_thresholds(dev_priv, val);
4950 }
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004951
Ville Syrjäläffe02b42015-02-02 19:09:50 +02004952 dev_priv->rps.cur_freq = val;
4953 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4954}
4955
Deepak Sa7f6e232015-05-09 18:04:44 +05304956/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
Deepak S76c3552f2014-01-30 23:08:16 +05304957 *
4958 * * If Gfx is Idle, then
Deepak Sa7f6e232015-05-09 18:04:44 +05304959 * 1. Forcewake Media well.
4960 * 2. Request idle freq.
4961 * 3. Release Forcewake of Media well.
Deepak S76c3552f2014-01-30 23:08:16 +05304962*/
4963static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4964{
Chris Wilsonaed242f2015-03-18 09:48:21 +00004965 u32 val = dev_priv->rps.idle_freq;
Deepak S5549d252014-06-28 11:26:11 +05304966
Chris Wilsonaed242f2015-03-18 09:48:21 +00004967 if (dev_priv->rps.cur_freq <= val)
Deepak S76c3552f2014-01-30 23:08:16 +05304968 return;
4969
Deepak Sa7f6e232015-05-09 18:04:44 +05304970 /* Wake up the media well, as that takes a lot less
4971 * power than the Render well. */
4972 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
Chris Wilsondc979972016-05-10 14:10:04 +01004973 valleyview_set_rps(dev_priv, val);
Deepak Sa7f6e232015-05-09 18:04:44 +05304974 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
Deepak S76c3552f2014-01-30 23:08:16 +05304975}
4976
Chris Wilson43cf3bf2015-03-18 09:48:22 +00004977void gen6_rps_busy(struct drm_i915_private *dev_priv)
4978{
4979 mutex_lock(&dev_priv->rps.hw_lock);
4980 if (dev_priv->rps.enabled) {
4981 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4982 gen6_rps_reset_ei(dev_priv);
4983 I915_WRITE(GEN6_PMINTRMSK,
4984 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
Michał Winiarski2b83c4c2016-06-20 11:58:27 +02004985
Chris Wilsonc33d2472016-07-04 08:08:36 +01004986 gen6_enable_rps_interrupts(dev_priv);
4987
Michał Winiarski2b83c4c2016-06-20 11:58:27 +02004988 /* Ensure we start at the user's desired frequency */
4989 intel_set_rps(dev_priv,
4990 clamp(dev_priv->rps.cur_freq,
4991 dev_priv->rps.min_freq_softlimit,
4992 dev_priv->rps.max_freq_softlimit));
Chris Wilson43cf3bf2015-03-18 09:48:22 +00004993 }
4994 mutex_unlock(&dev_priv->rps.hw_lock);
4995}
4996
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004997void gen6_rps_idle(struct drm_i915_private *dev_priv)
4998{
Chris Wilsonc33d2472016-07-04 08:08:36 +01004999 /* Flush our bottom-half so that it does not race with us
5000 * setting the idle frequency and so that it is bounded by
5001 * our rpm wakeref. And then disable the interrupts to stop any
5002 * futher RPS reclocking whilst we are asleep.
5003 */
5004 gen6_disable_rps_interrupts(dev_priv);
5005
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005006 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilsonc0951f02013-10-10 21:58:50 +01005007 if (dev_priv->rps.enabled) {
Chris Wilsondc979972016-05-10 14:10:04 +01005008 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Deepak S76c3552f2014-01-30 23:08:16 +05305009 vlv_set_rps_idle(dev_priv);
Daniel Vetter7526ed72014-09-29 15:07:19 +02005010 else
Chris Wilsondc979972016-05-10 14:10:04 +01005011 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
Chris Wilsonc0951f02013-10-10 21:58:50 +01005012 dev_priv->rps.last_adj = 0;
Ville Syrjälä12c100b2016-05-23 17:42:48 +03005013 I915_WRITE(GEN6_PMINTRMSK,
5014 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
Chris Wilsonc0951f02013-10-10 21:58:50 +01005015 }
Chris Wilson8d3afd72015-05-21 21:01:47 +01005016 mutex_unlock(&dev_priv->rps.hw_lock);
Chris Wilson1854d5c2015-04-07 16:20:32 +01005017
Chris Wilson8d3afd72015-05-21 21:01:47 +01005018 spin_lock(&dev_priv->rps.client_lock);
Chris Wilson1854d5c2015-04-07 16:20:32 +01005019 while (!list_empty(&dev_priv->rps.clients))
5020 list_del_init(dev_priv->rps.clients.next);
Chris Wilson8d3afd72015-05-21 21:01:47 +01005021 spin_unlock(&dev_priv->rps.client_lock);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005022}
5023
Chris Wilson1854d5c2015-04-07 16:20:32 +01005024void gen6_rps_boost(struct drm_i915_private *dev_priv,
Chris Wilsone61b9952015-04-27 13:41:24 +01005025 struct intel_rps_client *rps,
5026 unsigned long submitted)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005027{
Chris Wilson8d3afd72015-05-21 21:01:47 +01005028 /* This is intentionally racy! We peek at the state here, then
5029 * validate inside the RPS worker.
5030 */
Chris Wilson67d97da2016-07-04 08:08:31 +01005031 if (!(dev_priv->gt.awake &&
Chris Wilson8d3afd72015-05-21 21:01:47 +01005032 dev_priv->rps.enabled &&
Chris Wilson29ecd78d2016-07-13 09:10:35 +01005033 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
Chris Wilson8d3afd72015-05-21 21:01:47 +01005034 return;
Chris Wilson43cf3bf2015-03-18 09:48:22 +00005035
Chris Wilsone61b9952015-04-27 13:41:24 +01005036 /* Force a RPS boost (and don't count it against the client) if
5037 * the GPU is severely congested.
5038 */
Chris Wilsond0bc54f2015-05-21 21:01:48 +01005039 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
Chris Wilsone61b9952015-04-27 13:41:24 +01005040 rps = NULL;
5041
Chris Wilson8d3afd72015-05-21 21:01:47 +01005042 spin_lock(&dev_priv->rps.client_lock);
5043 if (rps == NULL || list_empty(&rps->link)) {
5044 spin_lock_irq(&dev_priv->irq_lock);
5045 if (dev_priv->rps.interrupts_enabled) {
5046 dev_priv->rps.client_boost = true;
Chris Wilsonc33d2472016-07-04 08:08:36 +01005047 schedule_work(&dev_priv->rps.work);
Chris Wilson8d3afd72015-05-21 21:01:47 +01005048 }
5049 spin_unlock_irq(&dev_priv->irq_lock);
Chris Wilson1854d5c2015-04-07 16:20:32 +01005050
Chris Wilson2e1b8732015-04-27 13:41:22 +01005051 if (rps != NULL) {
5052 list_add(&rps->link, &dev_priv->rps.clients);
5053 rps->boosts++;
Chris Wilson1854d5c2015-04-07 16:20:32 +01005054 } else
5055 dev_priv->rps.boosts++;
Chris Wilsonc0951f02013-10-10 21:58:50 +01005056 }
Chris Wilson8d3afd72015-05-21 21:01:47 +01005057 spin_unlock(&dev_priv->rps.client_lock);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005058}
5059
Chris Wilsondc979972016-05-10 14:10:04 +01005060void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
Jesse Barnes0a073b82013-04-17 15:54:58 -07005061{
Chris Wilsondc979972016-05-10 14:10:04 +01005062 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5063 valleyview_set_rps(dev_priv, val);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02005064 else
Chris Wilsondc979972016-05-10 14:10:04 +01005065 gen6_set_rps(dev_priv, val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005066}
5067
Chris Wilsondc979972016-05-10 14:10:04 +01005068static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
Zhe Wang20e49362014-11-04 17:07:05 +00005069{
Zhe Wang20e49362014-11-04 17:07:05 +00005070 I915_WRITE(GEN6_RC_CONTROL, 0);
Zhe Wang38c23522015-01-20 12:23:04 +00005071 I915_WRITE(GEN9_PG_ENABLE, 0);
Zhe Wang20e49362014-11-04 17:07:05 +00005072}
5073
Chris Wilsondc979972016-05-10 14:10:04 +01005074static void gen9_disable_rps(struct drm_i915_private *dev_priv)
Akash Goel2030d682016-04-23 00:05:45 +05305075{
Akash Goel2030d682016-04-23 00:05:45 +05305076 I915_WRITE(GEN6_RP_CONTROL, 0);
5077}
5078
Chris Wilsondc979972016-05-10 14:10:04 +01005079static void gen6_disable_rps(struct drm_i915_private *dev_priv)
Daniel Vetter44fc7d52013-07-12 22:43:27 +02005080{
Daniel Vetter44fc7d52013-07-12 22:43:27 +02005081 I915_WRITE(GEN6_RC_CONTROL, 0);
5082 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
Akash Goel2030d682016-04-23 00:05:45 +05305083 I915_WRITE(GEN6_RP_CONTROL, 0);
Daniel Vetter44fc7d52013-07-12 22:43:27 +02005084}
5085
Chris Wilsondc979972016-05-10 14:10:04 +01005086static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
Deepak S38807742014-05-23 21:00:15 +05305087{
Deepak S38807742014-05-23 21:00:15 +05305088 I915_WRITE(GEN6_RC_CONTROL, 0);
5089}
5090
Chris Wilsondc979972016-05-10 14:10:04 +01005091static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
Jesse Barnesd20d4f02013-04-23 10:09:28 -07005092{
Deepak S98a2e5f2014-08-18 10:35:27 -07005093 /* we're doing forcewake before Disabling RC6,
5094 * This what the BIOS expects when going into suspend */
Mika Kuoppala59bad942015-01-16 11:34:40 +02005095 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Deepak S98a2e5f2014-08-18 10:35:27 -07005096
Jesse Barnesd20d4f02013-04-23 10:09:28 -07005097 I915_WRITE(GEN6_RC_CONTROL, 0);
Jesse Barnesd20d4f02013-04-23 10:09:28 -07005098
Mika Kuoppala59bad942015-01-16 11:34:40 +02005099 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Jesse Barnesd20d4f02013-04-23 10:09:28 -07005100}
5101
Chris Wilsondc979972016-05-10 14:10:04 +01005102static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
Ben Widawskydc39fff2013-10-18 12:32:07 -07005103{
Chris Wilsondc979972016-05-10 14:10:04 +01005104 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Imre Deak91ca6892014-04-14 20:24:25 +03005105 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5106 mode = GEN6_RC_CTL_RC6_ENABLE;
5107 else
5108 mode = 0;
5109 }
Chris Wilsondc979972016-05-10 14:10:04 +01005110 if (HAS_RC6p(dev_priv))
Imre Deakb99d49c2016-06-29 19:13:54 +03005111 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5112 "RC6 %s RC6p %s RC6pp %s\n",
5113 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5114 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5115 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07005116
5117 else
Imre Deakb99d49c2016-06-29 19:13:54 +03005118 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5119 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
Ben Widawskydc39fff2013-10-18 12:32:07 -07005120}
5121
Chris Wilsondc979972016-05-10 14:10:04 +01005122static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305123{
Joonas Lahtinen72e96d62016-03-30 16:57:10 +03005124 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305125 bool enable_rc6 = true;
5126 unsigned long rc6_ctx_base;
Imre Deakfc619842016-06-29 19:13:55 +03005127 u32 rc_ctl;
5128 int rc_sw_target;
5129
5130 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5131 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5132 RC_SW_TARGET_STATE_SHIFT;
5133 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5134 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5135 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5136 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5137 rc_sw_target);
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305138
5139 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
Imre Deakb99d49c2016-06-29 19:13:54 +03005140 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305141 enable_rc6 = false;
5142 }
5143
5144 /*
5145 * The exact context size is not known for BXT, so assume a page size
5146 * for this check.
5147 */
5148 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
Joonas Lahtinen72e96d62016-03-30 16:57:10 +03005149 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5150 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5151 ggtt->stolen_reserved_size))) {
Imre Deakb99d49c2016-06-29 19:13:54 +03005152 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305153 enable_rc6 = false;
5154 }
5155
5156 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5157 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5158 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5159 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
Imre Deakb99d49c2016-06-29 19:13:54 +03005160 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305161 enable_rc6 = false;
5162 }
5163
Imre Deakfc619842016-06-29 19:13:55 +03005164 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5165 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5166 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5167 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5168 enable_rc6 = false;
5169 }
5170
5171 if (!I915_READ(GEN6_GFXPAUSE)) {
5172 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5173 enable_rc6 = false;
5174 }
5175
5176 if (!I915_READ(GEN8_MISC_CTRL0)) {
5177 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305178 enable_rc6 = false;
5179 }
5180
5181 return enable_rc6;
5182}
5183
Chris Wilsondc979972016-05-10 14:10:04 +01005184int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005185{
Daniel Vettere7d66d82015-06-15 23:23:54 +02005186 /* No RC6 before Ironlake and code is gone for ilk. */
Chris Wilsondc979972016-05-10 14:10:04 +01005187 if (INTEL_INFO(dev_priv)->gen < 6)
Imre Deake6069ca2014-04-18 16:01:02 +03005188 return 0;
5189
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305190 if (!enable_rc6)
5191 return 0;
5192
Chris Wilsondc979972016-05-10 14:10:04 +01005193 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05305194 DRM_INFO("RC6 disabled by BIOS\n");
5195 return 0;
5196 }
5197
Daniel Vetter456470e2012-08-08 23:35:40 +02005198 /* Respect the kernel parameter if it is set */
Imre Deake6069ca2014-04-18 16:01:02 +03005199 if (enable_rc6 >= 0) {
5200 int mask;
5201
Chris Wilsondc979972016-05-10 14:10:04 +01005202 if (HAS_RC6p(dev_priv))
Imre Deake6069ca2014-04-18 16:01:02 +03005203 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5204 INTEL_RC6pp_ENABLE;
5205 else
5206 mask = INTEL_RC6_ENABLE;
5207
5208 if ((enable_rc6 & mask) != enable_rc6)
Imre Deakb99d49c2016-06-29 19:13:54 +03005209 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5210 "(requested %d, valid %d)\n",
5211 enable_rc6 & mask, enable_rc6, mask);
Imre Deake6069ca2014-04-18 16:01:02 +03005212
5213 return enable_rc6 & mask;
5214 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005215
Chris Wilsondc979972016-05-10 14:10:04 +01005216 if (IS_IVYBRIDGE(dev_priv))
Ben Widawskycca84a12014-01-28 20:25:38 -08005217 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
Ben Widawsky8bade1a2014-01-28 20:25:39 -08005218
5219 return INTEL_RC6_ENABLE;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005220}
5221
Chris Wilsondc979972016-05-10 14:10:04 +01005222static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
Imre Deake6069ca2014-04-18 16:01:02 +03005223{
Ben Widawsky3280e8b2014-03-31 17:16:42 -07005224 /* All of these values are in units of 50MHz */
Chris Wilson773ea9a2016-07-13 09:10:33 +01005225
Tom O'Rourke93ee2922014-11-19 14:21:52 -08005226 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
Chris Wilsondc979972016-05-10 14:10:04 +01005227 if (IS_BROXTON(dev_priv)) {
Chris Wilson773ea9a2016-07-13 09:10:33 +01005228 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
Bob Paauwe35040562015-06-25 14:54:07 -07005229 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5230 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5231 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5232 } else {
Chris Wilson773ea9a2016-07-13 09:10:33 +01005233 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Bob Paauwe35040562015-06-25 14:54:07 -07005234 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5235 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5236 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5237 }
Ben Widawsky3280e8b2014-03-31 17:16:42 -07005238 /* hw_max = RP0 until we check for overclocking */
Chris Wilson773ea9a2016-07-13 09:10:33 +01005239 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
Ben Widawsky3280e8b2014-03-31 17:16:42 -07005240
Tom O'Rourke93ee2922014-11-19 14:21:52 -08005241 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
Chris Wilsondc979972016-05-10 14:10:04 +01005242 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5243 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Chris Wilson773ea9a2016-07-13 09:10:33 +01005244 u32 ddcc_status = 0;
5245
5246 if (sandybridge_pcode_read(dev_priv,
5247 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5248 &ddcc_status) == 0)
Tom O'Rourke93ee2922014-11-19 14:21:52 -08005249 dev_priv->rps.efficient_freq =
Tom O'Rourke46efa4a2015-02-10 23:06:46 -08005250 clamp_t(u8,
5251 ((ddcc_status >> 8) & 0xff),
5252 dev_priv->rps.min_freq,
5253 dev_priv->rps.max_freq);
Tom O'Rourke93ee2922014-11-19 14:21:52 -08005254 }
5255
Chris Wilsondc979972016-05-10 14:10:04 +01005256 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Akash Goelc5e06882015-06-29 14:50:19 +05305257 /* Store the frequency values in 16.66 MHZ units, which is
Chris Wilson773ea9a2016-07-13 09:10:33 +01005258 * the natural hardware unit for SKL
5259 */
Akash Goelc5e06882015-06-29 14:50:19 +05305260 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5261 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5262 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5263 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5264 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5265 }
Ben Widawsky3280e8b2014-03-31 17:16:42 -07005266}
5267
Chris Wilson3a45b052016-07-13 09:10:32 +01005268static void reset_rps(struct drm_i915_private *dev_priv,
5269 void (*set)(struct drm_i915_private *, u8))
5270{
5271 u8 freq = dev_priv->rps.cur_freq;
5272
5273 /* force a reset */
5274 dev_priv->rps.power = -1;
5275 dev_priv->rps.cur_freq = -1;
5276
5277 set(dev_priv, freq);
5278}
5279
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005280/* See the Gen9_GT_PM_Programming_Guide doc for the below */
Chris Wilsondc979972016-05-10 14:10:04 +01005281static void gen9_enable_rps(struct drm_i915_private *dev_priv)
Zhe Wang20e49362014-11-04 17:07:05 +00005282{
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005283 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5284
Sagar Arun Kamble23eafea2015-08-23 17:52:48 +05305285 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
Chris Wilsondc979972016-05-10 14:10:04 +01005286 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
Akash Goel2030d682016-04-23 00:05:45 +05305287 /*
5288 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5289 * clear out the Control register just to avoid inconsitency
5290 * with debugfs interface, which will show Turbo as enabled
5291 * only and that is not expected by the User after adding the
5292 * WaGsvDisableTurbo. Apart from this there is no problem even
5293 * if the Turbo is left enabled in the Control register, as the
5294 * Up/Down interrupts would remain masked.
5295 */
Chris Wilsondc979972016-05-10 14:10:04 +01005296 gen9_disable_rps(dev_priv);
Sagar Arun Kamble23eafea2015-08-23 17:52:48 +05305297 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5298 return;
5299 }
5300
Akash Goel0beb0592015-03-06 11:07:20 +05305301 /* Program defaults and thresholds for RPS*/
5302 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5303 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005304
Akash Goel0beb0592015-03-06 11:07:20 +05305305 /* 1 second timeout*/
5306 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5307 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5308
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005309 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005310
Akash Goel0beb0592015-03-06 11:07:20 +05305311 /* Leaning on the below call to gen6_set_rps to program/setup the
5312 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5313 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
Chris Wilson3a45b052016-07-13 09:10:32 +01005314 reset_rps(dev_priv, gen6_set_rps);
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005315
5316 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5317}
5318
Chris Wilsondc979972016-05-10 14:10:04 +01005319static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
Jesse Barnesb6fef0e2015-01-16 18:07:25 +00005320{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005321 struct intel_engine_cs *engine;
Zhe Wang20e49362014-11-04 17:07:05 +00005322 uint32_t rc6_mask = 0;
Zhe Wang20e49362014-11-04 17:07:05 +00005323
5324 /* 1a: Software RC state - RC0 */
5325 I915_WRITE(GEN6_RC_STATE, 0);
5326
5327 /* 1b: Get forcewake during program sequence. Although the driver
5328 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
Mika Kuoppala59bad942015-01-16 11:34:40 +02005329 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Zhe Wang20e49362014-11-04 17:07:05 +00005330
5331 /* 2a: Disable RC states. */
5332 I915_WRITE(GEN6_RC_CONTROL, 0);
5333
5334 /* 2b: Program RC6 thresholds.*/
Sagar Arun Kamble63a4dec2015-09-12 10:17:53 +05305335
5336 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
Chris Wilsondc979972016-05-10 14:10:04 +01005337 if (IS_SKYLAKE(dev_priv))
Sagar Arun Kamble63a4dec2015-09-12 10:17:53 +05305338 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5339 else
5340 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
Zhe Wang20e49362014-11-04 17:07:05 +00005341 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5342 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
Dave Gordonb4ac5af2016-03-24 11:20:38 +00005343 for_each_engine(engine, dev_priv)
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005344 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
Sagar Arun Kamble97c322e2015-09-12 10:17:54 +05305345
Dave Gordon1a3d1892016-05-13 15:36:30 +01005346 if (HAS_GUC(dev_priv))
Sagar Arun Kamble97c322e2015-09-12 10:17:54 +05305347 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5348
Zhe Wang20e49362014-11-04 17:07:05 +00005349 I915_WRITE(GEN6_RC_SLEEP, 0);
Zhe Wang20e49362014-11-04 17:07:05 +00005350
Zhe Wang38c23522015-01-20 12:23:04 +00005351 /* 2c: Program Coarse Power Gating Policies. */
5352 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5353 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5354
Zhe Wang20e49362014-11-04 17:07:05 +00005355 /* 3a: Enable RC6 */
Chris Wilsondc979972016-05-10 14:10:04 +01005356 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
Zhe Wang20e49362014-11-04 17:07:05 +00005357 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
Jani Nikula87ad3212016-01-14 12:53:34 +02005358 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
Sagar Arun Kamble3e7732a2015-10-01 20:29:27 +05305359 /* WaRsUseTimeoutMode */
Jani Nikula9fc736e2016-09-16 16:59:46 +03005360 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
Sagar Arun Kamble3e7732a2015-10-01 20:29:27 +05305361 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
Sagar Arun Kamblee3429cd2015-09-12 10:17:52 +05305362 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5363 GEN7_RC_CTL_TO_MODE |
5364 rc6_mask);
Sagar Arun Kamble3e7732a2015-10-01 20:29:27 +05305365 } else {
5366 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
Sagar Arun Kamblee3429cd2015-09-12 10:17:52 +05305367 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5368 GEN6_RC_CTL_EI_MODE(1) |
5369 rc6_mask);
Sagar Arun Kamble3e7732a2015-10-01 20:29:27 +05305370 }
Zhe Wang20e49362014-11-04 17:07:05 +00005371
Sagar Kamblecb07bae2015-04-12 11:28:14 +05305372 /*
5373 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
Sagar Arun Kamblef2d2fe92015-09-12 10:17:51 +05305374 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
Sagar Kamblecb07bae2015-04-12 11:28:14 +05305375 */
Chris Wilsondc979972016-05-10 14:10:04 +01005376 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
Sagar Arun Kamblef2d2fe92015-09-12 10:17:51 +05305377 I915_WRITE(GEN9_PG_ENABLE, 0);
5378 else
5379 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5380 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
Zhe Wang38c23522015-01-20 12:23:04 +00005381
Mika Kuoppala59bad942015-01-16 11:34:40 +02005382 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Zhe Wang20e49362014-11-04 17:07:05 +00005383}
5384
Chris Wilsondc979972016-05-10 14:10:04 +01005385static void gen8_enable_rps(struct drm_i915_private *dev_priv)
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005386{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005387 struct intel_engine_cs *engine;
Tom O'Rourke93ee2922014-11-19 14:21:52 -08005388 uint32_t rc6_mask = 0;
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005389
5390 /* 1a: Software RC state - RC0 */
5391 I915_WRITE(GEN6_RC_STATE, 0);
5392
5393 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5394 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
Mika Kuoppala59bad942015-01-16 11:34:40 +02005395 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005396
5397 /* 2a: Disable RC states. */
5398 I915_WRITE(GEN6_RC_CONTROL, 0);
5399
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005400 /* 2b: Program RC6 thresholds.*/
5401 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5402 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5403 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
Dave Gordonb4ac5af2016-03-24 11:20:38 +00005404 for_each_engine(engine, dev_priv)
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005405 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005406 I915_WRITE(GEN6_RC_SLEEP, 0);
Chris Wilsondc979972016-05-10 14:10:04 +01005407 if (IS_BROADWELL(dev_priv))
Tom O'Rourke0d68b252014-04-09 11:44:06 -07005408 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5409 else
5410 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005411
5412 /* 3: Enable RC6 */
Chris Wilsondc979972016-05-10 14:10:04 +01005413 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005414 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
Chris Wilsondc979972016-05-10 14:10:04 +01005415 intel_print_rc6_info(dev_priv, rc6_mask);
5416 if (IS_BROADWELL(dev_priv))
Tom O'Rourke0d68b252014-04-09 11:44:06 -07005417 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5418 GEN7_RC_CTL_TO_MODE |
5419 rc6_mask);
5420 else
5421 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5422 GEN6_RC_CTL_EI_MODE(1) |
5423 rc6_mask);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005424
5425 /* 4 Program defaults and thresholds for RPS*/
Ben Widawskyf9bdc582014-03-31 17:16:41 -07005426 I915_WRITE(GEN6_RPNSWREQ,
5427 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5428 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5429 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
Daniel Vetter7526ed72014-09-29 15:07:19 +02005430 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5431 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005432
Daniel Vetter7526ed72014-09-29 15:07:19 +02005433 /* Docs recommend 900MHz, and 300 MHz respectively */
5434 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5435 dev_priv->rps.max_freq_softlimit << 24 |
5436 dev_priv->rps.min_freq_softlimit << 16);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005437
Daniel Vetter7526ed72014-09-29 15:07:19 +02005438 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5439 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5440 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5441 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005442
Daniel Vetter7526ed72014-09-29 15:07:19 +02005443 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005444
5445 /* 5: Enable RPS */
Daniel Vetter7526ed72014-09-29 15:07:19 +02005446 I915_WRITE(GEN6_RP_CONTROL,
5447 GEN6_RP_MEDIA_TURBO |
5448 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5449 GEN6_RP_MEDIA_IS_GFX |
5450 GEN6_RP_ENABLE |
5451 GEN6_RP_UP_BUSY_AVG |
5452 GEN6_RP_DOWN_IDLE_AVG);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005453
Daniel Vetter7526ed72014-09-29 15:07:19 +02005454 /* 6: Ring frequency + overclocking (our driver does this later */
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005455
Chris Wilson3a45b052016-07-13 09:10:32 +01005456 reset_rps(dev_priv, gen6_set_rps);
Daniel Vetter7526ed72014-09-29 15:07:19 +02005457
Mika Kuoppala59bad942015-01-16 11:34:40 +02005458 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6edee7f2013-11-02 21:07:52 -07005459}
5460
Chris Wilsondc979972016-05-10 14:10:04 +01005461static void gen6_enable_rps(struct drm_i915_private *dev_priv)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005462{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005463 struct intel_engine_cs *engine;
Chris Wilson99ac9612016-07-13 09:10:34 +01005464 u32 rc6vids, rc6_mask = 0;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005465 u32 gtfifodbg;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005466 int rc6_mode;
Dave Gordonb4ac5af2016-03-24 11:20:38 +00005467 int ret;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005468
Jesse Barnes4fc688c2012-11-02 11:14:01 -07005469 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02005470
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005471 /* Here begins a magic sequence of register writes to enable
5472 * auto-downclocking.
5473 *
5474 * Perhaps there might be some value in exposing these to
5475 * userspace...
5476 */
5477 I915_WRITE(GEN6_RC_STATE, 0);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005478
5479 /* Clear the DBG now so we don't confuse earlier errors */
Ville Syrjälä297b32e2016-04-13 21:09:30 +03005480 gtfifodbg = I915_READ(GTFIFODBG);
5481 if (gtfifodbg) {
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005482 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5483 I915_WRITE(GTFIFODBG, gtfifodbg);
5484 }
5485
Mika Kuoppala59bad942015-01-16 11:34:40 +02005486 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005487
5488 /* disable the counters and set deterministic thresholds */
5489 I915_WRITE(GEN6_RC_CONTROL, 0);
5490
5491 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5492 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5493 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5494 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5495 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5496
Dave Gordonb4ac5af2016-03-24 11:20:38 +00005497 for_each_engine(engine, dev_priv)
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005498 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005499
5500 I915_WRITE(GEN6_RC_SLEEP, 0);
5501 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
Chris Wilsondc979972016-05-10 14:10:04 +01005502 if (IS_IVYBRIDGE(dev_priv))
Stéphane Marchesin351aa562013-08-13 11:55:17 -07005503 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5504 else
5505 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
Stéphane Marchesin0920a482013-01-29 19:41:59 -08005506 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005507 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5508
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03005509 /* Check if we are enabling RC6 */
Chris Wilsondc979972016-05-10 14:10:04 +01005510 rc6_mode = intel_enable_rc6();
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005511 if (rc6_mode & INTEL_RC6_ENABLE)
5512 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5513
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03005514 /* We don't use those on Haswell */
Chris Wilsondc979972016-05-10 14:10:04 +01005515 if (!IS_HASWELL(dev_priv)) {
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03005516 if (rc6_mode & INTEL_RC6p_ENABLE)
5517 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005518
Eugeni Dodonov5a7dc922012-07-02 11:51:05 -03005519 if (rc6_mode & INTEL_RC6pp_ENABLE)
5520 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5521 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005522
Chris Wilsondc979972016-05-10 14:10:04 +01005523 intel_print_rc6_info(dev_priv, rc6_mask);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005524
5525 I915_WRITE(GEN6_RC_CONTROL,
5526 rc6_mask |
5527 GEN6_RC_CTL_EI_MODE(1) |
5528 GEN6_RC_CTL_HW_ENABLE);
5529
Chris Wilsondd75fdc2013-09-25 17:34:57 +01005530 /* Power down if completely idle for over 50ms */
5531 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005532 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005533
Ben Widawsky42c05262012-09-26 10:34:00 -07005534 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
Ben Widawskyd060c162014-03-19 18:31:08 -07005535 if (ret)
Ben Widawsky42c05262012-09-26 10:34:00 -07005536 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
Ben Widawskyd060c162014-03-19 18:31:08 -07005537
Chris Wilson3a45b052016-07-13 09:10:32 +01005538 reset_rps(dev_priv, gen6_set_rps);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005539
Ben Widawsky31643d52012-09-26 10:34:01 -07005540 rc6vids = 0;
5541 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
Chris Wilsondc979972016-05-10 14:10:04 +01005542 if (IS_GEN6(dev_priv) && ret) {
Ben Widawsky31643d52012-09-26 10:34:01 -07005543 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
Chris Wilsondc979972016-05-10 14:10:04 +01005544 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
Ben Widawsky31643d52012-09-26 10:34:01 -07005545 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5546 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5547 rc6vids &= 0xffff00;
5548 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5549 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5550 if (ret)
5551 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5552 }
5553
Mika Kuoppala59bad942015-01-16 11:34:40 +02005554 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005555}
5556
Chris Wilsonfb7404e2016-07-13 09:10:38 +01005557static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005558{
5559 int min_freq = 15;
Chris Wilson3ebecd02013-04-12 19:10:13 +01005560 unsigned int gpu_freq;
5561 unsigned int max_ia_freq, min_ring_freq;
Akash Goel4c8c7742015-06-29 14:50:20 +05305562 unsigned int max_gpu_freq, min_gpu_freq;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005563 int scaling_factor = 180;
Ben Widawskyeda79642013-10-07 17:15:48 -03005564 struct cpufreq_policy *policy;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005565
Jesse Barnes4fc688c2012-11-02 11:14:01 -07005566 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02005567
Ben Widawskyeda79642013-10-07 17:15:48 -03005568 policy = cpufreq_cpu_get(0);
5569 if (policy) {
5570 max_ia_freq = policy->cpuinfo.max_freq;
5571 cpufreq_cpu_put(policy);
5572 } else {
5573 /*
5574 * Default to measured freq if none found, PCU will ensure we
5575 * don't go over
5576 */
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005577 max_ia_freq = tsc_khz;
Ben Widawskyeda79642013-10-07 17:15:48 -03005578 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005579
5580 /* Convert from kHz to MHz */
5581 max_ia_freq /= 1000;
5582
Ben Widawsky153b4b952013-10-22 22:05:09 -07005583 min_ring_freq = I915_READ(DCLK) & 0xf;
Ben Widawskyf6aca452013-10-02 09:25:02 -07005584 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5585 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
Chris Wilson3ebecd02013-04-12 19:10:13 +01005586
Chris Wilsondc979972016-05-10 14:10:04 +01005587 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Akash Goel4c8c7742015-06-29 14:50:20 +05305588 /* Convert GT frequency to 50 HZ units */
5589 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5590 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5591 } else {
5592 min_gpu_freq = dev_priv->rps.min_freq;
5593 max_gpu_freq = dev_priv->rps.max_freq;
5594 }
5595
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005596 /*
5597 * For each potential GPU frequency, load a ring frequency we'd like
5598 * to use for memory access. We do this by specifying the IA frequency
5599 * the PCU should use as a reference to determine the ring frequency.
5600 */
Akash Goel4c8c7742015-06-29 14:50:20 +05305601 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5602 int diff = max_gpu_freq - gpu_freq;
Chris Wilson3ebecd02013-04-12 19:10:13 +01005603 unsigned int ia_freq = 0, ring_freq = 0;
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005604
Chris Wilsondc979972016-05-10 14:10:04 +01005605 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Akash Goel4c8c7742015-06-29 14:50:20 +05305606 /*
5607 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5608 * No floor required for ring frequency on SKL.
5609 */
5610 ring_freq = gpu_freq;
Chris Wilsondc979972016-05-10 14:10:04 +01005611 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
Ben Widawsky46c764d2013-11-02 21:07:49 -07005612 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5613 ring_freq = max(min_ring_freq, gpu_freq);
Chris Wilsondc979972016-05-10 14:10:04 +01005614 } else if (IS_HASWELL(dev_priv)) {
Ben Widawskyf6aca452013-10-02 09:25:02 -07005615 ring_freq = mult_frac(gpu_freq, 5, 4);
Chris Wilson3ebecd02013-04-12 19:10:13 +01005616 ring_freq = max(min_ring_freq, ring_freq);
5617 /* leave ia_freq as the default, chosen by cpufreq */
5618 } else {
5619 /* On older processors, there is no separate ring
5620 * clock domain, so in order to boost the bandwidth
5621 * of the ring, we need to upclock the CPU (ia_freq).
5622 *
5623 * For GPU frequencies less than 750MHz,
5624 * just use the lowest ring freq.
5625 */
5626 if (gpu_freq < min_freq)
5627 ia_freq = 800;
5628 else
5629 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5630 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5631 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005632
Ben Widawsky42c05262012-09-26 10:34:00 -07005633 sandybridge_pcode_write(dev_priv,
5634 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
Chris Wilson3ebecd02013-04-12 19:10:13 +01005635 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5636 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5637 gpu_freq);
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005638 }
Eugeni Dodonov2b4e57b2012-04-18 15:29:23 -03005639}
5640
Ville Syrjälä03af2042014-06-28 02:03:53 +03005641static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
Deepak S2b6b3a02014-05-27 15:59:30 +05305642{
5643 u32 val, rp0;
5644
Jani Nikula5b5929c2015-10-07 11:17:46 +03005645 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
Deepak S2b6b3a02014-05-27 15:59:30 +05305646
Imre Deak43b67992016-08-31 19:13:02 +03005647 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
Jani Nikula5b5929c2015-10-07 11:17:46 +03005648 case 8:
5649 /* (2 * 4) config */
5650 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5651 break;
5652 case 12:
5653 /* (2 * 6) config */
5654 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5655 break;
5656 case 16:
5657 /* (2 * 8) config */
5658 default:
5659 /* Setting (2 * 8) Min RP0 for any other combination */
5660 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5661 break;
Deepak S095acd52015-01-17 11:05:59 +05305662 }
Jani Nikula5b5929c2015-10-07 11:17:46 +03005663
5664 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5665
Deepak S2b6b3a02014-05-27 15:59:30 +05305666 return rp0;
5667}
5668
5669static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5670{
5671 u32 val, rpe;
5672
5673 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5674 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5675
5676 return rpe;
5677}
5678
Deepak S7707df42014-07-12 18:46:14 +05305679static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5680{
5681 u32 val, rp1;
5682
Jani Nikula5b5929c2015-10-07 11:17:46 +03005683 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5684 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5685
Deepak S7707df42014-07-12 18:46:14 +05305686 return rp1;
5687}
5688
Deepak Sf8f2b002014-07-10 13:16:21 +05305689static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5690{
5691 u32 val, rp1;
5692
5693 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5694
5695 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5696
5697 return rp1;
5698}
5699
Ville Syrjälä03af2042014-06-28 02:03:53 +03005700static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
Jesse Barnes0a073b82013-04-17 15:54:58 -07005701{
5702 u32 val, rp0;
5703
Jani Nikula64936252013-05-22 15:36:20 +03005704 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005705
5706 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5707 /* Clamp to max */
5708 rp0 = min_t(u32, rp0, 0xea);
5709
5710 return rp0;
5711}
5712
5713static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5714{
5715 u32 val, rpe;
5716
Jani Nikula64936252013-05-22 15:36:20 +03005717 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005718 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
Jani Nikula64936252013-05-22 15:36:20 +03005719 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005720 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5721
5722 return rpe;
5723}
5724
Ville Syrjälä03af2042014-06-28 02:03:53 +03005725static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
Jesse Barnes0a073b82013-04-17 15:54:58 -07005726{
Imre Deak36146032014-12-04 18:39:35 +02005727 u32 val;
5728
5729 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5730 /*
5731 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5732 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5733 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5734 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5735 * to make sure it matches what Punit accepts.
5736 */
5737 return max_t(u32, val, 0xc0);
Jesse Barnes0a073b82013-04-17 15:54:58 -07005738}
5739
Imre Deakae484342014-03-31 15:10:44 +03005740/* Check that the pctx buffer wasn't move under us. */
5741static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5742{
5743 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5744
5745 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5746 dev_priv->vlv_pctx->stolen->start);
5747}
5748
Deepak S38807742014-05-23 21:00:15 +05305749
5750/* Check that the pcbr address is not empty. */
5751static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5752{
5753 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5754
5755 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5756}
5757
Chris Wilsondc979972016-05-10 14:10:04 +01005758static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
Deepak S38807742014-05-23 21:00:15 +05305759{
Joonas Lahtinen62106b42016-03-18 10:42:57 +02005760 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Joonas Lahtinen72e96d62016-03-30 16:57:10 +03005761 unsigned long pctx_paddr, paddr;
Deepak S38807742014-05-23 21:00:15 +05305762 u32 pcbr;
5763 int pctx_size = 32*1024;
5764
Deepak S38807742014-05-23 21:00:15 +05305765 pcbr = I915_READ(VLV_PCBR);
5766 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
Ville Syrjäläce611ef2014-11-07 21:33:46 +02005767 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
Deepak S38807742014-05-23 21:00:15 +05305768 paddr = (dev_priv->mm.stolen_base +
Joonas Lahtinen62106b42016-03-18 10:42:57 +02005769 (ggtt->stolen_size - pctx_size));
Deepak S38807742014-05-23 21:00:15 +05305770
5771 pctx_paddr = (paddr & (~4095));
5772 I915_WRITE(VLV_PCBR, pctx_paddr);
5773 }
Ville Syrjäläce611ef2014-11-07 21:33:46 +02005774
5775 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
Deepak S38807742014-05-23 21:00:15 +05305776}
5777
Chris Wilsondc979972016-05-10 14:10:04 +01005778static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005779{
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005780 struct drm_i915_gem_object *pctx;
5781 unsigned long pctx_paddr;
5782 u32 pcbr;
5783 int pctx_size = 24*1024;
5784
5785 pcbr = I915_READ(VLV_PCBR);
5786 if (pcbr) {
5787 /* BIOS set it up already, grab the pre-alloc'd space */
5788 int pcbr_offset;
5789
5790 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
Chris Wilson91c8a322016-07-05 10:40:23 +01005791 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005792 pcbr_offset,
Daniel Vetter190d6cd2013-07-04 13:06:28 +02005793 I915_GTT_OFFSET_NONE,
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005794 pctx_size);
5795 goto out;
5796 }
5797
Ville Syrjäläce611ef2014-11-07 21:33:46 +02005798 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5799
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005800 /*
5801 * From the Gunit register HAS:
5802 * The Gfx driver is expected to program this register and ensure
5803 * proper allocation within Gfx stolen memory. For example, this
5804 * register should be programmed such than the PCBR range does not
5805 * overlap with other ranges, such as the frame buffer, protected
5806 * memory, or any other relevant ranges.
5807 */
Chris Wilson91c8a322016-07-05 10:40:23 +01005808 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005809 if (!pctx) {
5810 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
Tvrtko Ursulinee504892016-02-11 10:27:30 +00005811 goto out;
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005812 }
5813
5814 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5815 I915_WRITE(VLV_PCBR, pctx_paddr);
5816
5817out:
Ville Syrjäläce611ef2014-11-07 21:33:46 +02005818 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
Jesse Barnesc9cddff2013-05-08 10:45:13 -07005819 dev_priv->vlv_pctx = pctx;
5820}
5821
Chris Wilsondc979972016-05-10 14:10:04 +01005822static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
Imre Deakae484342014-03-31 15:10:44 +03005823{
Imre Deakae484342014-03-31 15:10:44 +03005824 if (WARN_ON(!dev_priv->vlv_pctx))
5825 return;
5826
Chris Wilson34911fd2016-07-20 13:31:54 +01005827 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
Imre Deakae484342014-03-31 15:10:44 +03005828 dev_priv->vlv_pctx = NULL;
5829}
5830
Ville Syrjäläc30fec62016-03-04 21:43:02 +02005831static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5832{
5833 dev_priv->rps.gpll_ref_freq =
5834 vlv_get_cck_clock(dev_priv, "GPLL ref",
5835 CCK_GPLL_CLOCK_CONTROL,
5836 dev_priv->czclk_freq);
5837
5838 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5839 dev_priv->rps.gpll_ref_freq);
5840}
5841
Chris Wilsondc979972016-05-10 14:10:04 +01005842static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
Imre Deak4e805192014-04-14 20:24:41 +03005843{
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005844 u32 val;
Imre Deak4e805192014-04-14 20:24:41 +03005845
Chris Wilsondc979972016-05-10 14:10:04 +01005846 valleyview_setup_pctx(dev_priv);
Imre Deak4e805192014-04-14 20:24:41 +03005847
Ville Syrjäläc30fec62016-03-04 21:43:02 +02005848 vlv_init_gpll_ref_freq(dev_priv);
5849
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005850 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5851 switch ((val >> 6) & 3) {
5852 case 0:
5853 case 1:
5854 dev_priv->mem_freq = 800;
5855 break;
5856 case 2:
5857 dev_priv->mem_freq = 1066;
5858 break;
5859 case 3:
5860 dev_priv->mem_freq = 1333;
5861 break;
5862 }
Ville Syrjälä80b83b62014-11-10 22:55:14 +02005863 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005864
Imre Deak4e805192014-04-14 20:24:41 +03005865 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5866 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5867 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005868 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
Imre Deak4e805192014-04-14 20:24:41 +03005869 dev_priv->rps.max_freq);
5870
5871 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5872 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005873 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
Imre Deak4e805192014-04-14 20:24:41 +03005874 dev_priv->rps.efficient_freq);
5875
Deepak Sf8f2b002014-07-10 13:16:21 +05305876 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5877 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005878 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
Deepak Sf8f2b002014-07-10 13:16:21 +05305879 dev_priv->rps.rp1_freq);
5880
Imre Deak4e805192014-04-14 20:24:41 +03005881 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5882 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005883 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
Imre Deak4e805192014-04-14 20:24:41 +03005884 dev_priv->rps.min_freq);
Imre Deak4e805192014-04-14 20:24:41 +03005885}
5886
Chris Wilsondc979972016-05-10 14:10:04 +01005887static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
Deepak S38807742014-05-23 21:00:15 +05305888{
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005889 u32 val;
Deepak S2b6b3a02014-05-27 15:59:30 +05305890
Chris Wilsondc979972016-05-10 14:10:04 +01005891 cherryview_setup_pctx(dev_priv);
Deepak S2b6b3a02014-05-27 15:59:30 +05305892
Ville Syrjäläc30fec62016-03-04 21:43:02 +02005893 vlv_init_gpll_ref_freq(dev_priv);
5894
Ville Syrjäläa5805162015-05-26 20:42:30 +03005895 mutex_lock(&dev_priv->sb_lock);
Ville Syrjäläc6e8f392014-11-07 21:33:43 +02005896 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
Ville Syrjäläa5805162015-05-26 20:42:30 +03005897 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjäläc6e8f392014-11-07 21:33:43 +02005898
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005899 switch ((val >> 2) & 0x7) {
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005900 case 3:
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005901 dev_priv->mem_freq = 2000;
5902 break;
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03005903 default:
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005904 dev_priv->mem_freq = 1600;
5905 break;
5906 }
Ville Syrjälä80b83b62014-11-10 22:55:14 +02005907 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
Ville Syrjälä2bb25c12014-08-18 14:42:44 +03005908
Deepak S2b6b3a02014-05-27 15:59:30 +05305909 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5910 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5911 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005912 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05305913 dev_priv->rps.max_freq);
5914
5915 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5916 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005917 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05305918 dev_priv->rps.efficient_freq);
5919
Deepak S7707df42014-07-12 18:46:14 +05305920 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5921 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005922 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
Deepak S7707df42014-07-12 18:46:14 +05305923 dev_priv->rps.rp1_freq);
5924
Deepak S5b7c91b2015-05-09 18:15:46 +05305925 /* PUnit validated range is only [RPe, RP0] */
5926 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
Deepak S2b6b3a02014-05-27 15:59:30 +05305927 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02005928 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
Deepak S2b6b3a02014-05-27 15:59:30 +05305929 dev_priv->rps.min_freq);
5930
Ville Syrjälä1c147622014-08-18 14:42:43 +03005931 WARN_ONCE((dev_priv->rps.max_freq |
5932 dev_priv->rps.efficient_freq |
5933 dev_priv->rps.rp1_freq |
5934 dev_priv->rps.min_freq) & 1,
5935 "Odd GPU freq values\n");
Deepak S38807742014-05-23 21:00:15 +05305936}
5937
Chris Wilsondc979972016-05-10 14:10:04 +01005938static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
Imre Deak4e805192014-04-14 20:24:41 +03005939{
Chris Wilsondc979972016-05-10 14:10:04 +01005940 valleyview_cleanup_pctx(dev_priv);
Imre Deak4e805192014-04-14 20:24:41 +03005941}
5942
Chris Wilsondc979972016-05-10 14:10:04 +01005943static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
Deepak S38807742014-05-23 21:00:15 +05305944{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005945 struct intel_engine_cs *engine;
Deepak S2b6b3a02014-05-27 15:59:30 +05305946 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
Deepak S38807742014-05-23 21:00:15 +05305947
5948 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5949
Ville Syrjälä297b32e2016-04-13 21:09:30 +03005950 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5951 GT_FIFO_FREE_ENTRIES_CHV);
Deepak S38807742014-05-23 21:00:15 +05305952 if (gtfifodbg) {
5953 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5954 gtfifodbg);
5955 I915_WRITE(GTFIFODBG, gtfifodbg);
5956 }
5957
5958 cherryview_check_pctx(dev_priv);
5959
5960 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5961 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
Mika Kuoppala59bad942015-01-16 11:34:40 +02005962 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Deepak S38807742014-05-23 21:00:15 +05305963
Ville Syrjälä160614a2015-01-19 13:50:47 +02005964 /* Disable RC states. */
5965 I915_WRITE(GEN6_RC_CONTROL, 0);
5966
Deepak S38807742014-05-23 21:00:15 +05305967 /* 2a: Program RC6 thresholds.*/
5968 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5969 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5970 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5971
Dave Gordonb4ac5af2016-03-24 11:20:38 +00005972 for_each_engine(engine, dev_priv)
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00005973 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
Deepak S38807742014-05-23 21:00:15 +05305974 I915_WRITE(GEN6_RC_SLEEP, 0);
5975
Deepak Sf4f71c72015-03-28 15:23:35 +05305976 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5977 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
Deepak S38807742014-05-23 21:00:15 +05305978
5979 /* allows RC6 residency counter to work */
5980 I915_WRITE(VLV_COUNTER_CONTROL,
5981 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5982 VLV_MEDIA_RC6_COUNT_EN |
5983 VLV_RENDER_RC6_COUNT_EN));
5984
5985 /* For now we assume BIOS is allocating and populating the PCBR */
5986 pcbr = I915_READ(VLV_PCBR);
5987
Deepak S38807742014-05-23 21:00:15 +05305988 /* 3: Enable RC6 */
Chris Wilsondc979972016-05-10 14:10:04 +01005989 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5990 (pcbr >> VLV_PCBR_ADDR_SHIFT))
Ville Syrjäläaf5a75a2015-01-19 13:50:50 +02005991 rc6_mode = GEN7_RC_CTL_TO_MODE;
Deepak S38807742014-05-23 21:00:15 +05305992
5993 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5994
Deepak S2b6b3a02014-05-27 15:59:30 +05305995 /* 4 Program defaults and thresholds for RPS*/
Ville Syrjälä3cbdb482015-01-19 13:50:49 +02005996 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
Deepak S2b6b3a02014-05-27 15:59:30 +05305997 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5998 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5999 I915_WRITE(GEN6_RP_UP_EI, 66000);
6000 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6001
6002 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6003
6004 /* 5: Enable RPS */
6005 I915_WRITE(GEN6_RP_CONTROL,
6006 GEN6_RP_MEDIA_HW_NORMAL_MODE |
Ville Syrjäläeb973a52015-01-21 19:37:59 +02006007 GEN6_RP_MEDIA_IS_GFX |
Deepak S2b6b3a02014-05-27 15:59:30 +05306008 GEN6_RP_ENABLE |
6009 GEN6_RP_UP_BUSY_AVG |
6010 GEN6_RP_DOWN_IDLE_AVG);
6011
Deepak S3ef62342015-04-29 08:36:24 +05306012 /* Setting Fixed Bias */
6013 val = VLV_OVERRIDE_EN |
6014 VLV_SOC_TDP_EN |
6015 CHV_BIAS_CPU_50_SOC_50;
6016 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6017
Deepak S2b6b3a02014-05-27 15:59:30 +05306018 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6019
Ville Syrjälä8d40c3a2014-11-07 21:33:45 +02006020 /* RPS code assumes GPLL is used */
6021 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6022
Jani Nikula742f4912015-09-03 11:16:09 +03006023 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
Deepak S2b6b3a02014-05-27 15:59:30 +05306024 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6025
Chris Wilson3a45b052016-07-13 09:10:32 +01006026 reset_rps(dev_priv, valleyview_set_rps);
Deepak S2b6b3a02014-05-27 15:59:30 +05306027
Mika Kuoppala59bad942015-01-16 11:34:40 +02006028 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Deepak S38807742014-05-23 21:00:15 +05306029}
6030
Chris Wilsondc979972016-05-10 14:10:04 +01006031static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
Jesse Barnes0a073b82013-04-17 15:54:58 -07006032{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00006033 struct intel_engine_cs *engine;
Ben Widawsky2a5913a2014-03-19 18:31:13 -07006034 u32 gtfifodbg, val, rc6_mode = 0;
Jesse Barnes0a073b82013-04-17 15:54:58 -07006035
6036 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6037
Imre Deakae484342014-03-31 15:10:44 +03006038 valleyview_check_pctx(dev_priv);
6039
Ville Syrjälä297b32e2016-04-13 21:09:30 +03006040 gtfifodbg = I915_READ(GTFIFODBG);
6041 if (gtfifodbg) {
Jesse Barnesf7d85c12013-09-27 10:40:54 -07006042 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6043 gtfifodbg);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006044 I915_WRITE(GTFIFODBG, gtfifodbg);
6045 }
6046
Deepak Sc8d9a592013-11-23 14:55:42 +05306047 /* If VLV, Forcewake all wells, else re-direct to regular path */
Mika Kuoppala59bad942015-01-16 11:34:40 +02006048 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006049
Ville Syrjälä160614a2015-01-19 13:50:47 +02006050 /* Disable RC states. */
6051 I915_WRITE(GEN6_RC_CONTROL, 0);
6052
Ville Syrjäläcad725f2015-01-19 13:50:48 +02006053 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006054 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6055 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6056 I915_WRITE(GEN6_RP_UP_EI, 66000);
6057 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6058
6059 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6060
6061 I915_WRITE(GEN6_RP_CONTROL,
6062 GEN6_RP_MEDIA_TURBO |
6063 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6064 GEN6_RP_MEDIA_IS_GFX |
6065 GEN6_RP_ENABLE |
6066 GEN6_RP_UP_BUSY_AVG |
6067 GEN6_RP_DOWN_IDLE_CONT);
6068
6069 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6070 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6071 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6072
Dave Gordonb4ac5af2016-03-24 11:20:38 +00006073 for_each_engine(engine, dev_priv)
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00006074 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006075
Jesse Barnes2f0aa3042013-11-15 09:32:11 -08006076 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006077
6078 /* allows RC6 residency counter to work */
Jesse Barnes49798eb2013-09-26 17:55:57 -07006079 I915_WRITE(VLV_COUNTER_CONTROL,
Deepak S31685c22014-07-03 17:33:01 -04006080 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6081 VLV_RENDER_RC0_COUNT_EN |
Jesse Barnes49798eb2013-09-26 17:55:57 -07006082 VLV_MEDIA_RC6_COUNT_EN |
6083 VLV_RENDER_RC6_COUNT_EN));
Deepak S31685c22014-07-03 17:33:01 -04006084
Chris Wilsondc979972016-05-10 14:10:04 +01006085 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
Jesse Barnes6b88f292013-11-15 09:32:12 -08006086 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
Ben Widawskydc39fff2013-10-18 12:32:07 -07006087
Chris Wilsondc979972016-05-10 14:10:04 +01006088 intel_print_rc6_info(dev_priv, rc6_mode);
Ben Widawskydc39fff2013-10-18 12:32:07 -07006089
Jesse Barnesa2b23fe2013-09-19 09:33:13 -07006090 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006091
Deepak S3ef62342015-04-29 08:36:24 +05306092 /* Setting Fixed Bias */
6093 val = VLV_OVERRIDE_EN |
6094 VLV_SOC_TDP_EN |
6095 VLV_BIAS_CPU_125_SOC_875;
6096 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6097
Jani Nikula64936252013-05-22 15:36:20 +03006098 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006099
Ville Syrjälä8d40c3a2014-11-07 21:33:45 +02006100 /* RPS code assumes GPLL is used */
6101 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6102
Jani Nikula742f4912015-09-03 11:16:09 +03006103 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
Jesse Barnes0a073b82013-04-17 15:54:58 -07006104 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6105
Chris Wilson3a45b052016-07-13 09:10:32 +01006106 reset_rps(dev_priv, valleyview_set_rps);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006107
Mika Kuoppala59bad942015-01-16 11:34:40 +02006108 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006109}
6110
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006111static unsigned long intel_pxfreq(u32 vidfreq)
6112{
6113 unsigned long freq;
6114 int div = (vidfreq & 0x3f0000) >> 16;
6115 int post = (vidfreq & 0x3000) >> 12;
6116 int pre = (vidfreq & 0x7);
6117
6118 if (!pre)
6119 return 0;
6120
6121 freq = ((div * 133333) / ((1<<post) * pre));
6122
6123 return freq;
6124}
6125
Daniel Vettereb48eb02012-04-26 23:28:12 +02006126static const struct cparams {
6127 u16 i;
6128 u16 t;
6129 u16 m;
6130 u16 c;
6131} cparams[] = {
6132 { 1, 1333, 301, 28664 },
6133 { 1, 1066, 294, 24460 },
6134 { 1, 800, 294, 25192 },
6135 { 0, 1333, 276, 27605 },
6136 { 0, 1066, 276, 27605 },
6137 { 0, 800, 231, 23784 },
6138};
6139
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006140static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
Daniel Vettereb48eb02012-04-26 23:28:12 +02006141{
6142 u64 total_count, diff, ret;
6143 u32 count1, count2, count3, m = 0, c = 0;
6144 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6145 int i;
6146
Daniel Vetter02d71952012-08-09 16:44:54 +02006147 assert_spin_locked(&mchdev_lock);
6148
Daniel Vetter20e4d402012-08-08 23:35:39 +02006149 diff1 = now - dev_priv->ips.last_time1;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006150
6151 /* Prevent division-by-zero if we are asking too fast.
6152 * Also, we don't get interesting results if we are polling
6153 * faster than once in 10ms, so just return the saved value
6154 * in such cases.
6155 */
6156 if (diff1 <= 10)
Daniel Vetter20e4d402012-08-08 23:35:39 +02006157 return dev_priv->ips.chipset_power;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006158
6159 count1 = I915_READ(DMIEC);
6160 count2 = I915_READ(DDREC);
6161 count3 = I915_READ(CSIEC);
6162
6163 total_count = count1 + count2 + count3;
6164
6165 /* FIXME: handle per-counter overflow */
Daniel Vetter20e4d402012-08-08 23:35:39 +02006166 if (total_count < dev_priv->ips.last_count1) {
6167 diff = ~0UL - dev_priv->ips.last_count1;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006168 diff += total_count;
6169 } else {
Daniel Vetter20e4d402012-08-08 23:35:39 +02006170 diff = total_count - dev_priv->ips.last_count1;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006171 }
6172
6173 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
Daniel Vetter20e4d402012-08-08 23:35:39 +02006174 if (cparams[i].i == dev_priv->ips.c_m &&
6175 cparams[i].t == dev_priv->ips.r_t) {
Daniel Vettereb48eb02012-04-26 23:28:12 +02006176 m = cparams[i].m;
6177 c = cparams[i].c;
6178 break;
6179 }
6180 }
6181
6182 diff = div_u64(diff, diff1);
6183 ret = ((m * diff) + c);
6184 ret = div_u64(ret, 10);
6185
Daniel Vetter20e4d402012-08-08 23:35:39 +02006186 dev_priv->ips.last_count1 = total_count;
6187 dev_priv->ips.last_time1 = now;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006188
Daniel Vetter20e4d402012-08-08 23:35:39 +02006189 dev_priv->ips.chipset_power = ret;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006190
6191 return ret;
6192}
6193
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006194unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6195{
6196 unsigned long val;
6197
Chris Wilsondc979972016-05-10 14:10:04 +01006198 if (INTEL_INFO(dev_priv)->gen != 5)
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006199 return 0;
6200
6201 spin_lock_irq(&mchdev_lock);
6202
6203 val = __i915_chipset_val(dev_priv);
6204
6205 spin_unlock_irq(&mchdev_lock);
6206
6207 return val;
6208}
6209
Daniel Vettereb48eb02012-04-26 23:28:12 +02006210unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6211{
6212 unsigned long m, x, b;
6213 u32 tsfs;
6214
6215 tsfs = I915_READ(TSFS);
6216
6217 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6218 x = I915_READ8(TR1);
6219
6220 b = tsfs & TSFS_INTR_MASK;
6221
6222 return ((m * x) / 127) - b;
6223}
6224
Mika Kuoppalad972d6e2014-12-01 18:01:05 +02006225static int _pxvid_to_vd(u8 pxvid)
6226{
6227 if (pxvid == 0)
6228 return 0;
6229
6230 if (pxvid >= 8 && pxvid < 31)
6231 pxvid = 31;
6232
6233 return (pxvid + 2) * 125;
6234}
6235
6236static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
Daniel Vettereb48eb02012-04-26 23:28:12 +02006237{
Mika Kuoppalad972d6e2014-12-01 18:01:05 +02006238 const int vd = _pxvid_to_vd(pxvid);
6239 const int vm = vd - 1125;
6240
Chris Wilsondc979972016-05-10 14:10:04 +01006241 if (INTEL_INFO(dev_priv)->is_mobile)
Mika Kuoppalad972d6e2014-12-01 18:01:05 +02006242 return vm > 0 ? vm : 0;
6243
6244 return vd;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006245}
6246
Daniel Vetter02d71952012-08-09 16:44:54 +02006247static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
Daniel Vettereb48eb02012-04-26 23:28:12 +02006248{
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00006249 u64 now, diff, diffms;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006250 u32 count;
6251
Daniel Vetter02d71952012-08-09 16:44:54 +02006252 assert_spin_locked(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006253
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00006254 now = ktime_get_raw_ns();
6255 diffms = now - dev_priv->ips.last_time2;
6256 do_div(diffms, NSEC_PER_MSEC);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006257
6258 /* Don't divide by 0 */
Daniel Vettereb48eb02012-04-26 23:28:12 +02006259 if (!diffms)
6260 return;
6261
6262 count = I915_READ(GFXEC);
6263
Daniel Vetter20e4d402012-08-08 23:35:39 +02006264 if (count < dev_priv->ips.last_count2) {
6265 diff = ~0UL - dev_priv->ips.last_count2;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006266 diff += count;
6267 } else {
Daniel Vetter20e4d402012-08-08 23:35:39 +02006268 diff = count - dev_priv->ips.last_count2;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006269 }
6270
Daniel Vetter20e4d402012-08-08 23:35:39 +02006271 dev_priv->ips.last_count2 = count;
6272 dev_priv->ips.last_time2 = now;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006273
6274 /* More magic constants... */
6275 diff = diff * 1181;
6276 diff = div_u64(diff, diffms * 10);
Daniel Vetter20e4d402012-08-08 23:35:39 +02006277 dev_priv->ips.gfx_power = diff;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006278}
6279
Daniel Vetter02d71952012-08-09 16:44:54 +02006280void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6281{
Chris Wilsondc979972016-05-10 14:10:04 +01006282 if (INTEL_INFO(dev_priv)->gen != 5)
Daniel Vetter02d71952012-08-09 16:44:54 +02006283 return;
6284
Daniel Vetter92703882012-08-09 16:46:01 +02006285 spin_lock_irq(&mchdev_lock);
Daniel Vetter02d71952012-08-09 16:44:54 +02006286
6287 __i915_update_gfx_val(dev_priv);
6288
Daniel Vetter92703882012-08-09 16:46:01 +02006289 spin_unlock_irq(&mchdev_lock);
Daniel Vetter02d71952012-08-09 16:44:54 +02006290}
6291
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006292static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
Daniel Vettereb48eb02012-04-26 23:28:12 +02006293{
6294 unsigned long t, corr, state1, corr2, state2;
6295 u32 pxvid, ext_v;
6296
Daniel Vetter02d71952012-08-09 16:44:54 +02006297 assert_spin_locked(&mchdev_lock);
6298
Ville Syrjälä616847e2015-09-18 20:03:19 +03006299 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
Daniel Vettereb48eb02012-04-26 23:28:12 +02006300 pxvid = (pxvid >> 24) & 0x7f;
6301 ext_v = pvid_to_extvid(dev_priv, pxvid);
6302
6303 state1 = ext_v;
6304
6305 t = i915_mch_val(dev_priv);
6306
6307 /* Revel in the empirically derived constants */
6308
6309 /* Correction factor in 1/100000 units */
6310 if (t > 80)
6311 corr = ((t * 2349) + 135940);
6312 else if (t >= 50)
6313 corr = ((t * 964) + 29317);
6314 else /* < 50 */
6315 corr = ((t * 301) + 1004);
6316
6317 corr = corr * ((150142 * state1) / 10000 - 78642);
6318 corr /= 100000;
Daniel Vetter20e4d402012-08-08 23:35:39 +02006319 corr2 = (corr * dev_priv->ips.corr);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006320
6321 state2 = (corr2 * state1) / 10000;
6322 state2 /= 100; /* convert to mW */
6323
Daniel Vetter02d71952012-08-09 16:44:54 +02006324 __i915_update_gfx_val(dev_priv);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006325
Daniel Vetter20e4d402012-08-08 23:35:39 +02006326 return dev_priv->ips.gfx_power + state2;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006327}
6328
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006329unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6330{
6331 unsigned long val;
6332
Chris Wilsondc979972016-05-10 14:10:04 +01006333 if (INTEL_INFO(dev_priv)->gen != 5)
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006334 return 0;
6335
6336 spin_lock_irq(&mchdev_lock);
6337
6338 val = __i915_gfx_val(dev_priv);
6339
6340 spin_unlock_irq(&mchdev_lock);
6341
6342 return val;
6343}
6344
Daniel Vettereb48eb02012-04-26 23:28:12 +02006345/**
6346 * i915_read_mch_val - return value for IPS use
6347 *
6348 * Calculate and return a value for the IPS driver to use when deciding whether
6349 * we have thermal and power headroom to increase CPU or GPU power budget.
6350 */
6351unsigned long i915_read_mch_val(void)
6352{
6353 struct drm_i915_private *dev_priv;
6354 unsigned long chipset_val, graphics_val, ret = 0;
6355
Daniel Vetter92703882012-08-09 16:46:01 +02006356 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006357 if (!i915_mch_dev)
6358 goto out_unlock;
6359 dev_priv = i915_mch_dev;
6360
Chris Wilsonf531dcb22012-09-25 10:16:12 +01006361 chipset_val = __i915_chipset_val(dev_priv);
6362 graphics_val = __i915_gfx_val(dev_priv);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006363
6364 ret = chipset_val + graphics_val;
6365
6366out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02006367 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006368
6369 return ret;
6370}
6371EXPORT_SYMBOL_GPL(i915_read_mch_val);
6372
6373/**
6374 * i915_gpu_raise - raise GPU frequency limit
6375 *
6376 * Raise the limit; IPS indicates we have thermal headroom.
6377 */
6378bool i915_gpu_raise(void)
6379{
6380 struct drm_i915_private *dev_priv;
6381 bool ret = true;
6382
Daniel Vetter92703882012-08-09 16:46:01 +02006383 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006384 if (!i915_mch_dev) {
6385 ret = false;
6386 goto out_unlock;
6387 }
6388 dev_priv = i915_mch_dev;
6389
Daniel Vetter20e4d402012-08-08 23:35:39 +02006390 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6391 dev_priv->ips.max_delay--;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006392
6393out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02006394 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006395
6396 return ret;
6397}
6398EXPORT_SYMBOL_GPL(i915_gpu_raise);
6399
6400/**
6401 * i915_gpu_lower - lower GPU frequency limit
6402 *
6403 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6404 * frequency maximum.
6405 */
6406bool i915_gpu_lower(void)
6407{
6408 struct drm_i915_private *dev_priv;
6409 bool ret = true;
6410
Daniel Vetter92703882012-08-09 16:46:01 +02006411 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006412 if (!i915_mch_dev) {
6413 ret = false;
6414 goto out_unlock;
6415 }
6416 dev_priv = i915_mch_dev;
6417
Daniel Vetter20e4d402012-08-08 23:35:39 +02006418 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6419 dev_priv->ips.max_delay++;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006420
6421out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02006422 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006423
6424 return ret;
6425}
6426EXPORT_SYMBOL_GPL(i915_gpu_lower);
6427
6428/**
6429 * i915_gpu_busy - indicate GPU business to IPS
6430 *
6431 * Tell the IPS driver whether or not the GPU is busy.
6432 */
6433bool i915_gpu_busy(void)
6434{
Daniel Vettereb48eb02012-04-26 23:28:12 +02006435 bool ret = false;
6436
Daniel Vetter92703882012-08-09 16:46:01 +02006437 spin_lock_irq(&mchdev_lock);
Chris Wilsondcff85c2016-08-05 10:14:11 +01006438 if (i915_mch_dev)
6439 ret = i915_mch_dev->gt.awake;
Daniel Vetter92703882012-08-09 16:46:01 +02006440 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006441
6442 return ret;
6443}
6444EXPORT_SYMBOL_GPL(i915_gpu_busy);
6445
6446/**
6447 * i915_gpu_turbo_disable - disable graphics turbo
6448 *
6449 * Disable graphics turbo by resetting the max frequency and setting the
6450 * current frequency to the default.
6451 */
6452bool i915_gpu_turbo_disable(void)
6453{
6454 struct drm_i915_private *dev_priv;
6455 bool ret = true;
6456
Daniel Vetter92703882012-08-09 16:46:01 +02006457 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006458 if (!i915_mch_dev) {
6459 ret = false;
6460 goto out_unlock;
6461 }
6462 dev_priv = i915_mch_dev;
6463
Daniel Vetter20e4d402012-08-08 23:35:39 +02006464 dev_priv->ips.max_delay = dev_priv->ips.fstart;
Daniel Vettereb48eb02012-04-26 23:28:12 +02006465
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01006466 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
Daniel Vettereb48eb02012-04-26 23:28:12 +02006467 ret = false;
6468
6469out_unlock:
Daniel Vetter92703882012-08-09 16:46:01 +02006470 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006471
6472 return ret;
6473}
6474EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6475
6476/**
6477 * Tells the intel_ips driver that the i915 driver is now loaded, if
6478 * IPS got loaded first.
6479 *
6480 * This awkward dance is so that neither module has to depend on the
6481 * other in order for IPS to do the appropriate communication of
6482 * GPU turbo limits to i915.
6483 */
6484static void
6485ips_ping_for_i915_load(void)
6486{
6487 void (*link)(void);
6488
6489 link = symbol_get(ips_link_to_i915_driver);
6490 if (link) {
6491 link();
6492 symbol_put(ips_link_to_i915_driver);
6493 }
6494}
6495
6496void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6497{
Daniel Vetter02d71952012-08-09 16:44:54 +02006498 /* We only register the i915 ips part with intel-ips once everything is
6499 * set up, to avoid intel-ips sneaking in and reading bogus values. */
Daniel Vetter92703882012-08-09 16:46:01 +02006500 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006501 i915_mch_dev = dev_priv;
Daniel Vetter92703882012-08-09 16:46:01 +02006502 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006503
6504 ips_ping_for_i915_load();
6505}
6506
6507void intel_gpu_ips_teardown(void)
6508{
Daniel Vetter92703882012-08-09 16:46:01 +02006509 spin_lock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006510 i915_mch_dev = NULL;
Daniel Vetter92703882012-08-09 16:46:01 +02006511 spin_unlock_irq(&mchdev_lock);
Daniel Vettereb48eb02012-04-26 23:28:12 +02006512}
Deepak S76c3552f2014-01-30 23:08:16 +05306513
Chris Wilsondc979972016-05-10 14:10:04 +01006514static void intel_init_emon(struct drm_i915_private *dev_priv)
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006515{
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006516 u32 lcfuse;
6517 u8 pxw[16];
6518 int i;
6519
6520 /* Disable to program */
6521 I915_WRITE(ECR, 0);
6522 POSTING_READ(ECR);
6523
6524 /* Program energy weights for various events */
6525 I915_WRITE(SDEW, 0x15040d00);
6526 I915_WRITE(CSIEW0, 0x007f0000);
6527 I915_WRITE(CSIEW1, 0x1e220004);
6528 I915_WRITE(CSIEW2, 0x04000004);
6529
6530 for (i = 0; i < 5; i++)
Ville Syrjälä616847e2015-09-18 20:03:19 +03006531 I915_WRITE(PEW(i), 0);
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006532 for (i = 0; i < 3; i++)
Ville Syrjälä616847e2015-09-18 20:03:19 +03006533 I915_WRITE(DEW(i), 0);
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006534
6535 /* Program P-state weights to account for frequency power adjustment */
6536 for (i = 0; i < 16; i++) {
Ville Syrjälä616847e2015-09-18 20:03:19 +03006537 u32 pxvidfreq = I915_READ(PXVFREQ(i));
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006538 unsigned long freq = intel_pxfreq(pxvidfreq);
6539 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6540 PXVFREQ_PX_SHIFT;
6541 unsigned long val;
6542
6543 val = vid * vid;
6544 val *= (freq / 1000);
6545 val *= 255;
6546 val /= (127*127*900);
6547 if (val > 0xff)
6548 DRM_ERROR("bad pxval: %ld\n", val);
6549 pxw[i] = val;
6550 }
6551 /* Render standby states get 0 weight */
6552 pxw[14] = 0;
6553 pxw[15] = 0;
6554
6555 for (i = 0; i < 4; i++) {
6556 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6557 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
Ville Syrjälä616847e2015-09-18 20:03:19 +03006558 I915_WRITE(PXW(i), val);
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006559 }
6560
6561 /* Adjust magic regs to magic values (more experimental results) */
6562 I915_WRITE(OGW0, 0);
6563 I915_WRITE(OGW1, 0);
6564 I915_WRITE(EG0, 0x00007f00);
6565 I915_WRITE(EG1, 0x0000000e);
6566 I915_WRITE(EG2, 0x000e0000);
6567 I915_WRITE(EG3, 0x68000300);
6568 I915_WRITE(EG4, 0x42000000);
6569 I915_WRITE(EG5, 0x00140031);
6570 I915_WRITE(EG6, 0);
6571 I915_WRITE(EG7, 0);
6572
6573 for (i = 0; i < 8; i++)
Ville Syrjälä616847e2015-09-18 20:03:19 +03006574 I915_WRITE(PXWL(i), 0);
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006575
6576 /* Enable PMON + select events */
6577 I915_WRITE(ECR, 0x80000019);
6578
6579 lcfuse = I915_READ(LCFUSE02);
6580
Daniel Vetter20e4d402012-08-08 23:35:39 +02006581 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
Eugeni Dodonovdde18882012-04-18 15:29:24 -03006582}
6583
Chris Wilsondc979972016-05-10 14:10:04 +01006584void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
Imre Deakae484342014-03-31 15:10:44 +03006585{
Imre Deakb268c692015-12-15 20:10:31 +02006586 /*
6587 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6588 * requirement.
6589 */
6590 if (!i915.enable_rc6) {
6591 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6592 intel_runtime_pm_get(dev_priv);
6593 }
Imre Deake6069ca2014-04-18 16:01:02 +03006594
Chris Wilsonb5163db2016-08-10 13:58:24 +01006595 mutex_lock(&dev_priv->drm.struct_mutex);
Chris Wilson773ea9a2016-07-13 09:10:33 +01006596 mutex_lock(&dev_priv->rps.hw_lock);
6597
6598 /* Initialize RPS limits (for userspace) */
Chris Wilsondc979972016-05-10 14:10:04 +01006599 if (IS_CHERRYVIEW(dev_priv))
6600 cherryview_init_gt_powersave(dev_priv);
6601 else if (IS_VALLEYVIEW(dev_priv))
6602 valleyview_init_gt_powersave(dev_priv);
Chris Wilson2a13ae72016-08-02 11:15:27 +01006603 else if (INTEL_GEN(dev_priv) >= 6)
Chris Wilson773ea9a2016-07-13 09:10:33 +01006604 gen6_init_rps_frequencies(dev_priv);
6605
6606 /* Derive initial user preferences/limits from the hardware limits */
6607 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6608 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6609
6610 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6611 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6612
6613 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6614 dev_priv->rps.min_freq_softlimit =
6615 max_t(int,
6616 dev_priv->rps.efficient_freq,
6617 intel_freq_opcode(dev_priv, 450));
6618
Chris Wilson99ac9612016-07-13 09:10:34 +01006619 /* After setting max-softlimit, find the overclock max freq */
6620 if (IS_GEN6(dev_priv) ||
6621 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6622 u32 params = 0;
6623
6624 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6625 if (params & BIT(31)) { /* OC supported */
6626 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6627 (dev_priv->rps.max_freq & 0xff) * 50,
6628 (params & 0xff) * 50);
6629 dev_priv->rps.max_freq = params & 0xff;
6630 }
6631 }
6632
Chris Wilson29ecd78d2016-07-13 09:10:35 +01006633 /* Finally allow us to boost to max by default */
6634 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6635
Chris Wilson773ea9a2016-07-13 09:10:33 +01006636 mutex_unlock(&dev_priv->rps.hw_lock);
Chris Wilsonb5163db2016-08-10 13:58:24 +01006637 mutex_unlock(&dev_priv->drm.struct_mutex);
Chris Wilson54b4f682016-07-21 21:16:19 +01006638
6639 intel_autoenable_gt_powersave(dev_priv);
Imre Deakae484342014-03-31 15:10:44 +03006640}
6641
Chris Wilsondc979972016-05-10 14:10:04 +01006642void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
Imre Deakae484342014-03-31 15:10:44 +03006643{
Ville Syrjälä8dac1e12016-08-02 14:07:33 +03006644 if (IS_VALLEYVIEW(dev_priv))
Chris Wilsondc979972016-05-10 14:10:04 +01006645 valleyview_cleanup_gt_powersave(dev_priv);
Imre Deakb268c692015-12-15 20:10:31 +02006646
6647 if (!i915.enable_rc6)
6648 intel_runtime_pm_put(dev_priv);
Imre Deakae484342014-03-31 15:10:44 +03006649}
6650
Chris Wilson54b4f682016-07-21 21:16:19 +01006651/**
6652 * intel_suspend_gt_powersave - suspend PM work and helper threads
6653 * @dev_priv: i915 device
6654 *
6655 * We don't want to disable RC6 or other features here, we just want
6656 * to make sure any work we've queued has finished and won't bother
6657 * us while we're suspended.
6658 */
6659void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6660{
6661 if (INTEL_GEN(dev_priv) < 6)
6662 return;
6663
6664 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6665 intel_runtime_pm_put(dev_priv);
6666
6667 /* gen6_rps_idle() will be called later to disable interrupts */
6668}
6669
Chris Wilsonb7137e02016-07-13 09:10:37 +01006670void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6671{
6672 dev_priv->rps.enabled = true; /* force disabling */
6673 intel_disable_gt_powersave(dev_priv);
Chris Wilson54b4f682016-07-21 21:16:19 +01006674
6675 gen6_reset_rps_interrupts(dev_priv);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07006676}
6677
Chris Wilsondc979972016-05-10 14:10:04 +01006678void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
Daniel Vetter8090c6b2012-06-24 16:42:32 +02006679{
Chris Wilsonb7137e02016-07-13 09:10:37 +01006680 if (!READ_ONCE(dev_priv->rps.enabled))
6681 return;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07006682
Jesse Barnes4fc688c2012-11-02 11:14:01 -07006683 mutex_lock(&dev_priv->rps.hw_lock);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006684
Chris Wilsonb7137e02016-07-13 09:10:37 +01006685 if (INTEL_GEN(dev_priv) >= 9) {
6686 gen9_disable_rc6(dev_priv);
6687 gen9_disable_rps(dev_priv);
6688 } else if (IS_CHERRYVIEW(dev_priv)) {
6689 cherryview_disable_rps(dev_priv);
6690 } else if (IS_VALLEYVIEW(dev_priv)) {
6691 valleyview_disable_rps(dev_priv);
6692 } else if (INTEL_GEN(dev_priv) >= 6) {
6693 gen6_disable_rps(dev_priv);
6694 } else if (IS_IRONLAKE_M(dev_priv)) {
6695 ironlake_disable_drps(dev_priv);
6696 }
6697
6698 dev_priv->rps.enabled = false;
6699 mutex_unlock(&dev_priv->rps.hw_lock);
6700}
6701
6702void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6703{
Chris Wilson54b4f682016-07-21 21:16:19 +01006704 /* We shouldn't be disabling as we submit, so this should be less
6705 * racy than it appears!
6706 */
Chris Wilsonb7137e02016-07-13 09:10:37 +01006707 if (READ_ONCE(dev_priv->rps.enabled))
6708 return;
6709
6710 /* Powersaving is controlled by the host when inside a VM */
6711 if (intel_vgpu_active(dev_priv))
6712 return;
6713
6714 mutex_lock(&dev_priv->rps.hw_lock);
Imre Deak3cc134e2014-11-19 15:30:03 +02006715
Chris Wilsondc979972016-05-10 14:10:04 +01006716 if (IS_CHERRYVIEW(dev_priv)) {
6717 cherryview_enable_rps(dev_priv);
6718 } else if (IS_VALLEYVIEW(dev_priv)) {
6719 valleyview_enable_rps(dev_priv);
Chris Wilsonb7137e02016-07-13 09:10:37 +01006720 } else if (INTEL_GEN(dev_priv) >= 9) {
Chris Wilsondc979972016-05-10 14:10:04 +01006721 gen9_enable_rc6(dev_priv);
6722 gen9_enable_rps(dev_priv);
6723 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
Chris Wilsonfb7404e2016-07-13 09:10:38 +01006724 gen6_update_ring_freq(dev_priv);
Chris Wilsondc979972016-05-10 14:10:04 +01006725 } else if (IS_BROADWELL(dev_priv)) {
6726 gen8_enable_rps(dev_priv);
Chris Wilsonfb7404e2016-07-13 09:10:38 +01006727 gen6_update_ring_freq(dev_priv);
Chris Wilsonb7137e02016-07-13 09:10:37 +01006728 } else if (INTEL_GEN(dev_priv) >= 6) {
Chris Wilsondc979972016-05-10 14:10:04 +01006729 gen6_enable_rps(dev_priv);
Chris Wilsonfb7404e2016-07-13 09:10:38 +01006730 gen6_update_ring_freq(dev_priv);
Chris Wilsonb7137e02016-07-13 09:10:37 +01006731 } else if (IS_IRONLAKE_M(dev_priv)) {
6732 ironlake_enable_drps(dev_priv);
6733 intel_init_emon(dev_priv);
Jesse Barnes0a073b82013-04-17 15:54:58 -07006734 }
Chris Wilsonaed242f2015-03-18 09:48:21 +00006735
6736 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6737 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6738
6739 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6740 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6741
Chris Wilson54b4f682016-07-21 21:16:19 +01006742 dev_priv->rps.enabled = true;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07006743 mutex_unlock(&dev_priv->rps.hw_lock);
Chris Wilsonb7137e02016-07-13 09:10:37 +01006744}
Imre Deakc6df39b2014-04-14 20:24:29 +03006745
Chris Wilson54b4f682016-07-21 21:16:19 +01006746static void __intel_autoenable_gt_powersave(struct work_struct *work)
6747{
6748 struct drm_i915_private *dev_priv =
6749 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6750 struct intel_engine_cs *rcs;
6751 struct drm_i915_gem_request *req;
6752
6753 if (READ_ONCE(dev_priv->rps.enabled))
6754 goto out;
6755
6756 rcs = &dev_priv->engine[RCS];
6757 if (rcs->last_context)
6758 goto out;
6759
6760 if (!rcs->init_context)
6761 goto out;
6762
6763 mutex_lock(&dev_priv->drm.struct_mutex);
6764
6765 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6766 if (IS_ERR(req))
6767 goto unlock;
6768
6769 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6770 rcs->init_context(req);
6771
6772 /* Mark the device busy, calling intel_enable_gt_powersave() */
6773 i915_add_request_no_flush(req);
6774
6775unlock:
6776 mutex_unlock(&dev_priv->drm.struct_mutex);
6777out:
6778 intel_runtime_pm_put(dev_priv);
6779}
6780
6781void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6782{
6783 if (READ_ONCE(dev_priv->rps.enabled))
6784 return;
6785
6786 if (IS_IRONLAKE_M(dev_priv)) {
6787 ironlake_enable_drps(dev_priv);
Chris Wilson54b4f682016-07-21 21:16:19 +01006788 intel_init_emon(dev_priv);
Chris Wilson54b4f682016-07-21 21:16:19 +01006789 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6790 /*
6791 * PCU communication is slow and this doesn't need to be
6792 * done at any specific time, so do this out of our fast path
6793 * to make resume and init faster.
6794 *
6795 * We depend on the HW RC6 power context save/restore
6796 * mechanism when entering D3 through runtime PM suspend. So
6797 * disable RPM until RPS/RC6 is properly setup. We can only
6798 * get here via the driver load/system resume/runtime resume
6799 * paths, so the _noresume version is enough (and in case of
6800 * runtime resume it's necessary).
6801 */
6802 if (queue_delayed_work(dev_priv->wq,
6803 &dev_priv->rps.autoenable_work,
6804 round_jiffies_up_relative(HZ)))
6805 intel_runtime_pm_get_noresume(dev_priv);
6806 }
6807}
6808
Daniel Vetter3107bd42012-10-31 22:52:31 +01006809static void ibx_init_clock_gating(struct drm_device *dev)
6810{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006811 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter3107bd42012-10-31 22:52:31 +01006812
6813 /*
6814 * On Ibex Peak and Cougar Point, we need to disable clock
6815 * gating for the panel power sequencer or it will fail to
6816 * start up when no ports are active.
6817 */
6818 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6819}
6820
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006821static void g4x_disable_trickle_feed(struct drm_device *dev)
6822{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006823 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +03006824 enum pipe pipe;
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006825
Damien Lespiau055e3932014-08-18 13:49:10 +01006826 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006827 I915_WRITE(DSPCNTR(pipe),
6828 I915_READ(DSPCNTR(pipe)) |
6829 DISPPLANE_TRICKLE_FEED_DISABLE);
Ville Syrjäläb12ce1d2015-05-26 20:27:23 +03006830
6831 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6832 POSTING_READ(DSPSURF(pipe));
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006833 }
6834}
6835
Ville Syrjälä017636c2013-12-05 15:51:37 +02006836static void ilk_init_lp_watermarks(struct drm_device *dev)
6837{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006838 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä017636c2013-12-05 15:51:37 +02006839
6840 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6841 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6842 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6843
6844 /*
6845 * Don't touch WM1S_LP_EN here.
6846 * Doing so could cause underruns.
6847 */
6848}
6849
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006850static void ironlake_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006851{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006852 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau231e54f2012-10-19 17:55:41 +01006853 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006854
Damien Lespiauf1e8fa52013-06-07 17:41:09 +01006855 /*
6856 * Required for FBC
6857 * WaFbcDisableDpfcClockGating:ilk
6858 */
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01006859 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6860 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6861 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006862
6863 I915_WRITE(PCH_3DCGDIS0,
6864 MARIUNIT_CLOCK_GATE_DISABLE |
6865 SVSMUNIT_CLOCK_GATE_DISABLE);
6866 I915_WRITE(PCH_3DCGDIS1,
6867 VFMUNIT_CLOCK_GATE_DISABLE);
6868
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006869 /*
6870 * According to the spec the following bits should be set in
6871 * order to enable memory self-refresh
6872 * The bit 22/21 of 0x42004
6873 * The bit 5 of 0x42020
6874 * The bit 15 of 0x45000
6875 */
6876 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6877 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6878 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01006879 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006880 I915_WRITE(DISP_ARB_CTL,
6881 (I915_READ(DISP_ARB_CTL) |
6882 DISP_FBC_WM_DIS));
Ville Syrjälä017636c2013-12-05 15:51:37 +02006883
6884 ilk_init_lp_watermarks(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006885
6886 /*
6887 * Based on the document from hardware guys the following bits
6888 * should be set unconditionally in order to enable FBC.
6889 * The bit 22 of 0x42000
6890 * The bit 22 of 0x42004
6891 * The bit 7,8,9 of 0x42020.
6892 */
6893 if (IS_IRONLAKE_M(dev)) {
Damien Lespiau4bb35332013-06-14 15:23:24 +01006894 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006895 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6896 I915_READ(ILK_DISPLAY_CHICKEN1) |
6897 ILK_FBCQ_DIS);
6898 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6899 I915_READ(ILK_DISPLAY_CHICKEN2) |
6900 ILK_DPARB_GATE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006901 }
6902
Damien Lespiau4d47e4f2012-10-19 17:55:42 +01006903 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6904
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006905 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6906 I915_READ(ILK_DISPLAY_CHICKEN2) |
6907 ILK_ELPIN_409_SELECT);
6908 I915_WRITE(_3D_CHICKEN2,
6909 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6910 _3D_CHICKEN2_WM_READ_PIPELINED);
Daniel Vetter4358a372012-10-18 11:49:51 +02006911
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006912 /* WaDisableRenderCachePipelinedFlush:ilk */
Daniel Vetter4358a372012-10-18 11:49:51 +02006913 I915_WRITE(CACHE_MODE_0,
6914 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
Daniel Vetter3107bd42012-10-31 22:52:31 +01006915
Akash Goel4e046322014-04-04 17:14:38 +05306916 /* WaDisable_RenderCache_OperationalFlush:ilk */
6917 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6918
Ville Syrjälä0e088b82013-06-07 10:47:04 +03006919 g4x_disable_trickle_feed(dev);
Ville Syrjäläbdad2b22013-06-07 10:47:03 +03006920
Daniel Vetter3107bd42012-10-31 22:52:31 +01006921 ibx_init_clock_gating(dev);
6922}
6923
6924static void cpt_init_clock_gating(struct drm_device *dev)
6925{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006926 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter3107bd42012-10-31 22:52:31 +01006927 int pipe;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03006928 uint32_t val;
Daniel Vetter3107bd42012-10-31 22:52:31 +01006929
6930 /*
6931 * On Ibex Peak and Cougar Point, we need to disable clock
6932 * gating for the panel power sequencer or it will fail to
6933 * start up when no ports are active.
6934 */
Jesse Barnescd664072013-10-02 10:34:19 -07006935 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6936 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6937 PCH_CPUNIT_CLOCK_GATE_DISABLE);
Daniel Vetter3107bd42012-10-31 22:52:31 +01006938 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6939 DPLS_EDP_PPS_FIX_DIS);
Takashi Iwai335c07b2012-12-11 11:46:29 +01006940 /* The below fixes the weird display corruption, a few pixels shifted
6941 * downward, on (only) LVDS of some HP laptops with IVY.
6942 */
Damien Lespiau055e3932014-08-18 13:49:10 +01006943 for_each_pipe(dev_priv, pipe) {
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03006944 val = I915_READ(TRANS_CHICKEN2(pipe));
6945 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6946 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006947 if (dev_priv->vbt.fdi_rx_polarity_inverted)
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03006948 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03006949 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6950 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6951 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -03006952 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6953 }
Daniel Vetter3107bd42012-10-31 22:52:31 +01006954 /* WADP0ClockGatingDisable */
Damien Lespiau055e3932014-08-18 13:49:10 +01006955 for_each_pipe(dev_priv, pipe) {
Daniel Vetter3107bd42012-10-31 22:52:31 +01006956 I915_WRITE(TRANS_CHICKEN1(pipe),
6957 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6958 }
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006959}
6960
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006961static void gen6_check_mch_setup(struct drm_device *dev)
6962{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006963 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006964 uint32_t tmp;
6965
6966 tmp = I915_READ(MCH_SSKPD);
Daniel Vetterdf662a22014-08-04 11:17:25 +02006967 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6968 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6969 tmp);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01006970}
6971
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03006972static void gen6_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006973{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006974 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau231e54f2012-10-19 17:55:41 +01006975 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006976
Damien Lespiau231e54f2012-10-19 17:55:41 +01006977 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03006978
6979 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6980 I915_READ(ILK_DISPLAY_CHICKEN2) |
6981 ILK_ELPIN_409_SELECT);
6982
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01006983 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
Daniel Vetter42839082012-12-14 23:38:28 +01006984 I915_WRITE(_3D_CHICKEN,
6985 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6986
Akash Goel4e046322014-04-04 17:14:38 +05306987 /* WaDisable_RenderCache_OperationalFlush:snb */
6988 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6989
Ville Syrjälä8d85d272014-02-04 21:59:15 +02006990 /*
6991 * BSpec recoomends 8x4 when MSAA is used,
6992 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02006993 *
6994 * Note that PS/WM thread counts depend on the WIZ hashing
6995 * disable bit, which we don't touch here, but it's good
6996 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjälä8d85d272014-02-04 21:59:15 +02006997 */
6998 I915_WRITE(GEN6_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00006999 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjälä8d85d272014-02-04 21:59:15 +02007000
Ville Syrjälä017636c2013-12-05 15:51:37 +02007001 ilk_init_lp_watermarks(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007002
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007003 I915_WRITE(CACHE_MODE_0,
Daniel Vetter50743292012-04-26 22:02:54 +02007004 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007005
7006 I915_WRITE(GEN6_UCGCTL1,
7007 I915_READ(GEN6_UCGCTL1) |
7008 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7009 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7010
7011 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7012 * gating disable must be set. Failure to set it results in
7013 * flickering pixels due to Z write ordering failures after
7014 * some amount of runtime in the Mesa "fire" demo, and Unigine
7015 * Sanctuary and Tropics, and apparently anything else with
7016 * alpha test or pixel discard.
7017 *
7018 * According to the spec, bit 11 (RCCUNIT) must also be set,
7019 * but we didn't debug actual testcases to find it out.
Jesse Barnes0f846f82012-06-14 11:04:47 -07007020 *
Ville Syrjäläef593182014-01-22 21:32:47 +02007021 * WaDisableRCCUnitClockGating:snb
7022 * WaDisableRCPBUnitClockGating:snb
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007023 */
7024 I915_WRITE(GEN6_UCGCTL2,
7025 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7026 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7027
Ville Syrjälä5eb146d2014-02-04 21:59:16 +02007028 /* WaStripsFansDisableFastClipPerformanceFix:snb */
Ville Syrjälä743b57d2014-02-04 21:59:17 +02007029 I915_WRITE(_3D_CHICKEN3,
7030 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007031
7032 /*
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02007033 * Bspec says:
7034 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7035 * 3DSTATE_SF number of SF output attributes is more than 16."
7036 */
7037 I915_WRITE(_3D_CHICKEN3,
7038 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7039
7040 /*
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007041 * According to the spec the following bits should be
7042 * set in order to enable memory self-refresh and fbc:
7043 * The bit21 and bit22 of 0x42000
7044 * The bit21 and bit22 of 0x42004
7045 * The bit5 and bit7 of 0x42020
7046 * The bit14 of 0x70180
7047 * The bit14 of 0x71180
Damien Lespiau4bb35332013-06-14 15:23:24 +01007048 *
7049 * WaFbcAsynchFlipDisableFbcQueue:snb
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007050 */
7051 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7052 I915_READ(ILK_DISPLAY_CHICKEN1) |
7053 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7054 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7055 I915_READ(ILK_DISPLAY_CHICKEN2) |
7056 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
Damien Lespiau231e54f2012-10-19 17:55:41 +01007057 I915_WRITE(ILK_DSPCLK_GATE_D,
7058 I915_READ(ILK_DSPCLK_GATE_D) |
7059 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7060 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007061
Ville Syrjälä0e088b82013-06-07 10:47:04 +03007062 g4x_disable_trickle_feed(dev);
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07007063
Daniel Vetter3107bd42012-10-31 22:52:31 +01007064 cpt_init_clock_gating(dev);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01007065
7066 gen6_check_mch_setup(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007067}
7068
7069static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7070{
7071 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7072
Ville Syrjälä3aad9052014-01-22 21:32:59 +02007073 /*
Ville Syrjälä46680e02014-01-22 21:33:01 +02007074 * WaVSThreadDispatchOverride:ivb,vlv
Ville Syrjälä3aad9052014-01-22 21:32:59 +02007075 *
7076 * This actually overrides the dispatch
7077 * mode for all thread types.
7078 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007079 reg &= ~GEN7_FF_SCHED_MASK;
7080 reg |= GEN7_FF_TS_SCHED_HW;
7081 reg |= GEN7_FF_VS_SCHED_HW;
7082 reg |= GEN7_FF_DS_SCHED_HW;
7083
7084 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7085}
7086
Paulo Zanoni17a303e2012-11-20 15:12:07 -02007087static void lpt_init_clock_gating(struct drm_device *dev)
7088{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007089 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni17a303e2012-11-20 15:12:07 -02007090
7091 /*
7092 * TODO: this bit should only be enabled when really needed, then
7093 * disabled when not needed anymore in order to save power.
7094 */
Ville Syrjäläc2699522015-08-27 23:55:59 +03007095 if (HAS_PCH_LPT_LP(dev))
Paulo Zanoni17a303e2012-11-20 15:12:07 -02007096 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7097 I915_READ(SOUTH_DSPCLK_GATE_D) |
7098 PCH_LP_PARTITION_LEVEL_DISABLE);
Paulo Zanoni0a790cd2013-04-17 18:15:49 -03007099
7100 /* WADPOClockGatingDisable:hsw */
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03007101 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7102 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
Paulo Zanoni0a790cd2013-04-17 18:15:49 -03007103 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
Paulo Zanoni17a303e2012-11-20 15:12:07 -02007104}
7105
Imre Deak7d708ee2013-04-17 14:04:50 +03007106static void lpt_suspend_hw(struct drm_device *dev)
7107{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007108 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak7d708ee2013-04-17 14:04:50 +03007109
Ville Syrjäläc2699522015-08-27 23:55:59 +03007110 if (HAS_PCH_LPT_LP(dev)) {
Imre Deak7d708ee2013-04-17 14:04:50 +03007111 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7112
7113 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7114 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7115 }
7116}
7117
Imre Deak450174f2016-05-03 15:54:21 +03007118static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7119 int general_prio_credits,
7120 int high_prio_credits)
7121{
7122 u32 misccpctl;
7123
7124 /* WaTempDisableDOPClkGating:bdw */
7125 misccpctl = I915_READ(GEN7_MISCCPCTL);
7126 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7127
7128 I915_WRITE(GEN8_L3SQCREG1,
7129 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7130 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7131
7132 /*
7133 * Wait at least 100 clocks before re-enabling clock gating.
7134 * See the definition of L3SQCREG1 in BSpec.
7135 */
7136 POSTING_READ(GEN8_L3SQCREG1);
7137 udelay(1);
7138 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7139}
7140
Mika Kuoppala9498dba2016-06-07 17:19:01 +03007141static void kabylake_init_clock_gating(struct drm_device *dev)
7142{
Mika Kuoppala9146f302016-06-07 17:19:01 +03007143 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala9498dba2016-06-07 17:19:01 +03007144
Mika Kuoppalab033bb62016-06-07 17:19:04 +03007145 gen9_init_clock_gating(dev);
Mika Kuoppala9498dba2016-06-07 17:19:01 +03007146
7147 /* WaDisableSDEUnitClockGating:kbl */
7148 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7149 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7150 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Mika Kuoppala8aeb7f62016-06-07 17:19:05 +03007151
7152 /* WaDisableGamClockGating:kbl */
7153 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7154 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7155 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03007156
7157 /* WaFbcNukeOnHostModify:kbl */
7158 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7159 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
Mika Kuoppala9498dba2016-06-07 17:19:01 +03007160}
7161
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02007162static void skylake_init_clock_gating(struct drm_device *dev)
7163{
Mika Kuoppalac584e2d2016-06-07 17:19:18 +03007164 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala44fff992016-06-07 17:19:09 +03007165
Mika Kuoppalab033bb62016-06-07 17:19:04 +03007166 gen9_init_clock_gating(dev);
Mika Kuoppala44fff992016-06-07 17:19:09 +03007167
7168 /* WAC6entrylatency:skl */
7169 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7170 FBC_LLC_FULLY_OPEN);
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03007171
7172 /* WaFbcNukeOnHostModify:skl */
7173 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7174 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02007175}
7176
Paulo Zanoni47c2bd92014-08-21 17:09:37 -03007177static void broadwell_init_clock_gating(struct drm_device *dev)
Ben Widawsky1020a5c2013-11-02 21:07:06 -07007178{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007179 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau07d27e22014-03-03 17:31:46 +00007180 enum pipe pipe;
Ben Widawsky1020a5c2013-11-02 21:07:06 -07007181
Ville Syrjälä7ad0dba2015-05-19 20:32:55 +03007182 ilk_init_lp_watermarks(dev);
Ben Widawsky50ed5fb2013-11-02 21:07:40 -07007183
Ben Widawskyab57fff2013-12-12 15:28:04 -08007184 /* WaSwitchSolVfFArbitrationPriority:bdw */
Ben Widawsky50ed5fb2013-11-02 21:07:40 -07007185 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07007186
Ben Widawskyab57fff2013-12-12 15:28:04 -08007187 /* WaPsrDPAMaskVBlankInSRD:bdw */
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07007188 I915_WRITE(CHICKEN_PAR1_1,
7189 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7190
Ben Widawskyab57fff2013-12-12 15:28:04 -08007191 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
Damien Lespiau055e3932014-08-18 13:49:10 +01007192 for_each_pipe(dev_priv, pipe) {
Damien Lespiau07d27e22014-03-03 17:31:46 +00007193 I915_WRITE(CHICKEN_PIPESL_1(pipe),
Ville Syrjäläc7c65622014-03-05 13:05:45 +02007194 I915_READ(CHICKEN_PIPESL_1(pipe)) |
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02007195 BDW_DPRS_MASK_VBLANK_SRD);
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07007196 }
Ben Widawsky63801f22013-12-12 17:26:03 -08007197
Ben Widawskyab57fff2013-12-12 15:28:04 -08007198 /* WaVSRefCountFullforceMissDisable:bdw */
7199 /* WaDSRefCountFullforceMissDisable:bdw */
7200 I915_WRITE(GEN7_FF_THREAD_MODE,
7201 I915_READ(GEN7_FF_THREAD_MODE) &
7202 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Ville Syrjälä36075a42014-02-04 21:59:21 +02007203
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02007204 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7205 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02007206
7207 /* WaDisableSDEUnitClockGating:bdw */
7208 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7209 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Damien Lespiau5d708682014-03-26 18:41:51 +00007210
Imre Deak450174f2016-05-03 15:54:21 +03007211 /* WaProgramL3SqcReg1Default:bdw */
7212 gen8_set_l3sqc_credits(dev_priv, 30, 2);
Ville Syrjälä4d487cf2015-05-19 20:32:56 +03007213
Ville Syrjälä6d50b062015-05-19 20:32:57 +03007214 /*
7215 * WaGttCachingOffByDefault:bdw
7216 * GTT cache may not work with big pages, so if those
7217 * are ever enabled GTT cache may need to be disabled.
7218 */
7219 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7220
Mika Kuoppala17e0adf2016-06-07 17:19:02 +03007221 /* WaKVMNotificationOnConfigChange:bdw */
7222 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7223 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7224
Paulo Zanoni89d6b2b2014-08-21 17:09:36 -03007225 lpt_init_clock_gating(dev);
Ben Widawsky1020a5c2013-11-02 21:07:06 -07007226}
7227
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007228static void haswell_init_clock_gating(struct drm_device *dev)
7229{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007230 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007231
Ville Syrjälä017636c2013-12-05 15:51:37 +02007232 ilk_init_lp_watermarks(dev);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007233
Francisco Jerezf3fc4882013-10-02 15:53:16 -07007234 /* L3 caching of data atomics doesn't work -- disable it. */
7235 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7236 I915_WRITE(HSW_ROW_CHICKEN3,
7237 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7238
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007239 /* This is required by WaCatErrorRejectionIssue:hsw */
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007240 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7241 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7242 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7243
Ville Syrjäläe36ea7f2014-01-22 21:33:00 +02007244 /* WaVSRefCountFullforceMissDisable:hsw */
7245 I915_WRITE(GEN7_FF_THREAD_MODE,
7246 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007247
Akash Goel4e046322014-04-04 17:14:38 +05307248 /* WaDisable_RenderCache_OperationalFlush:hsw */
7249 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7250
Chia-I Wufe27c602014-01-28 13:29:33 +08007251 /* enable HiZ Raw Stall Optimization */
7252 I915_WRITE(CACHE_MODE_0_GEN7,
7253 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7254
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007255 /* WaDisable4x2SubspanOptimization:hsw */
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007256 I915_WRITE(CACHE_MODE_1,
7257 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03007258
Ville Syrjäläa12c4962014-02-04 21:59:20 +02007259 /*
7260 * BSpec recommends 8x4 when MSAA is used,
7261 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02007262 *
7263 * Note that PS/WM thread counts depend on the WIZ hashing
7264 * disable bit, which we don't touch here, but it's good
7265 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjäläa12c4962014-02-04 21:59:20 +02007266 */
7267 I915_WRITE(GEN7_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00007268 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjäläa12c4962014-02-04 21:59:20 +02007269
Kenneth Graunke94411592014-12-31 16:23:00 -08007270 /* WaSampleCChickenBitEnable:hsw */
7271 I915_WRITE(HALF_SLICE_CHICKEN3,
7272 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7273
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007274 /* WaSwitchSolVfFArbitrationPriority:hsw */
Ben Widawskye3dff582013-03-20 14:49:14 -07007275 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7276
Paulo Zanoni90a88642013-05-03 17:23:45 -03007277 /* WaRsPkgCStateDisplayPMReq:hsw */
7278 I915_WRITE(CHICKEN_PAR1_1,
7279 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03007280
Paulo Zanoni17a303e2012-11-20 15:12:07 -02007281 lpt_init_clock_gating(dev);
Eugeni Dodonovcad2a2d2012-07-02 11:51:09 -03007282}
7283
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007284static void ivybridge_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007285{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007286 struct drm_i915_private *dev_priv = to_i915(dev);
Ben Widawsky20848222012-05-04 18:58:59 -07007287 uint32_t snpcr;
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007288
Ville Syrjälä017636c2013-12-05 15:51:37 +02007289 ilk_init_lp_watermarks(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007290
Damien Lespiau231e54f2012-10-19 17:55:41 +01007291 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007292
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007293 /* WaDisableEarlyCull:ivb */
Jesse Barnes87f80202012-10-02 17:43:41 -05007294 I915_WRITE(_3D_CHICKEN3,
7295 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7296
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007297 /* WaDisableBackToBackFlipFix:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007298 I915_WRITE(IVB_CHICKEN3,
7299 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7300 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7301
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007302 /* WaDisablePSDDualDispatchEnable:ivb */
Jesse Barnes12f33822012-10-25 12:15:45 -07007303 if (IS_IVB_GT1(dev))
7304 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7305 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
Jesse Barnes12f33822012-10-25 12:15:45 -07007306
Akash Goel4e046322014-04-04 17:14:38 +05307307 /* WaDisable_RenderCache_OperationalFlush:ivb */
7308 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7309
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007310 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007311 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7312 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7313
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007314 /* WaApplyL3ControlAndL3ChickenMode:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007315 I915_WRITE(GEN7_L3CNTLREG1,
7316 GEN7_WA_FOR_GEN7_L3_CONTROL);
7317 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
Jesse Barnes8ab43972012-10-25 12:15:42 -07007318 GEN7_WA_L3_CHICKEN_MODE);
7319 if (IS_IVB_GT1(dev))
7320 I915_WRITE(GEN7_ROW_CHICKEN2,
7321 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Ville Syrjälä412236c2014-01-22 21:32:44 +02007322 else {
7323 /* must write both registers */
7324 I915_WRITE(GEN7_ROW_CHICKEN2,
7325 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Jesse Barnes8ab43972012-10-25 12:15:42 -07007326 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7327 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
Ville Syrjälä412236c2014-01-22 21:32:44 +02007328 }
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007329
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007330 /* WaForceL3Serialization:ivb */
Jesse Barnes61939d92012-10-02 17:43:38 -05007331 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7332 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7333
Ville Syrjälä1b80a19a2014-01-22 21:32:53 +02007334 /*
Jesse Barnes0f846f82012-06-14 11:04:47 -07007335 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007336 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
Jesse Barnes0f846f82012-06-14 11:04:47 -07007337 */
7338 I915_WRITE(GEN6_UCGCTL2,
Ville Syrjälä28acf3b2014-01-22 21:32:48 +02007339 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes0f846f82012-06-14 11:04:47 -07007340
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007341 /* This is required by WaCatErrorRejectionIssue:ivb */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007342 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7343 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7344 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7345
Ville Syrjälä0e088b82013-06-07 10:47:04 +03007346 g4x_disable_trickle_feed(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007347
7348 gen7_setup_fixed_func_scheduler(dev_priv);
Daniel Vetter97e19302012-04-24 16:00:21 +02007349
Chris Wilson22721342014-03-04 09:41:43 +00007350 if (0) { /* causes HiZ corruption on ivb:gt1 */
7351 /* enable HiZ Raw Stall Optimization */
7352 I915_WRITE(CACHE_MODE_0_GEN7,
7353 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7354 }
Chia-I Wu116f2b62014-01-28 13:29:34 +08007355
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007356 /* WaDisable4x2SubspanOptimization:ivb */
Daniel Vetter97e19302012-04-24 16:00:21 +02007357 I915_WRITE(CACHE_MODE_1,
7358 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Ben Widawsky20848222012-05-04 18:58:59 -07007359
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02007360 /*
7361 * BSpec recommends 8x4 when MSAA is used,
7362 * however in practice 16x4 seems fastest.
Ville Syrjäläc5c98a52014-02-05 12:43:47 +02007363 *
7364 * Note that PS/WM thread counts depend on the WIZ hashing
7365 * disable bit, which we don't touch here, but it's good
7366 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02007367 */
7368 I915_WRITE(GEN7_GT_MODE,
Damien Lespiau98533252014-12-08 17:33:51 +00007369 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02007370
Ben Widawsky20848222012-05-04 18:58:59 -07007371 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7372 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7373 snpcr |= GEN6_MBC_SNPCR_MED;
7374 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
Daniel Vetter3107bd42012-10-31 22:52:31 +01007375
Ben Widawskyab5c6082013-04-05 13:12:41 -07007376 if (!HAS_PCH_NOP(dev))
7377 cpt_init_clock_gating(dev);
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01007378
7379 gen6_check_mch_setup(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007380}
7381
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007382static void valleyview_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007383{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007384 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007385
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007386 /* WaDisableEarlyCull:vlv */
Jesse Barnes87f80202012-10-02 17:43:41 -05007387 I915_WRITE(_3D_CHICKEN3,
7388 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7389
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007390 /* WaDisableBackToBackFlipFix:vlv */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007391 I915_WRITE(IVB_CHICKEN3,
7392 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7393 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7394
Ville Syrjäläfad7d362014-01-22 21:32:39 +02007395 /* WaPsdDispatchEnable:vlv */
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007396 /* WaDisablePSDDualDispatchEnable:vlv */
Jesse Barnes12f33822012-10-25 12:15:45 -07007397 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
Jesse Barnesd3bc0302013-03-08 10:45:51 -08007398 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7399 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
Jesse Barnes12f33822012-10-25 12:15:45 -07007400
Akash Goel4e046322014-04-04 17:14:38 +05307401 /* WaDisable_RenderCache_OperationalFlush:vlv */
7402 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7403
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007404 /* WaForceL3Serialization:vlv */
Jesse Barnes61939d92012-10-02 17:43:38 -05007405 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7406 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7407
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007408 /* WaDisableDopClockGating:vlv */
Jesse Barnes8ab43972012-10-25 12:15:42 -07007409 I915_WRITE(GEN7_ROW_CHICKEN2,
7410 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7411
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007412 /* This is required by WaCatErrorRejectionIssue:vlv */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007413 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7414 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7415 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7416
Ville Syrjälä46680e02014-01-22 21:33:01 +02007417 gen7_setup_fixed_func_scheduler(dev_priv);
7418
Ville Syrjälä3c0edae2014-01-22 21:32:56 +02007419 /*
Jesse Barnes0f846f82012-06-14 11:04:47 -07007420 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007421 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
Jesse Barnes0f846f82012-06-14 11:04:47 -07007422 */
7423 I915_WRITE(GEN6_UCGCTL2,
Ville Syrjälä3c0edae2014-01-22 21:32:56 +02007424 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes0f846f82012-06-14 11:04:47 -07007425
Akash Goelc98f5062014-03-24 23:00:07 +05307426 /* WaDisableL3Bank2xClockGate:vlv
7427 * Disabling L3 clock gating- MMIO 940c[25] = 1
7428 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7429 I915_WRITE(GEN7_UCGCTL4,
7430 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
Jesse Barnese3f33d42012-06-14 11:04:50 -07007431
Ville Syrjäläafd58e72014-01-22 21:33:03 +02007432 /*
7433 * BSpec says this must be set, even though
7434 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7435 */
Daniel Vetter6b26c862012-04-24 14:04:12 +02007436 I915_WRITE(CACHE_MODE_1,
7437 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Jesse Barnes79831172012-06-20 10:53:12 -07007438
7439 /*
Ville Syrjäläda2518f2015-01-21 19:38:01 +02007440 * BSpec recommends 8x4 when MSAA is used,
7441 * however in practice 16x4 seems fastest.
7442 *
7443 * Note that PS/WM thread counts depend on the WIZ hashing
7444 * disable bit, which we don't touch here, but it's good
7445 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7446 */
7447 I915_WRITE(GEN7_GT_MODE,
7448 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7449
7450 /*
Ville Syrjälä031994e2014-01-22 21:32:46 +02007451 * WaIncreaseL3CreditsForVLVB0:vlv
7452 * This is the hardware default actually.
7453 */
7454 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7455
7456 /*
Damien Lespiauecdb4eb72013-05-03 18:48:10 +01007457 * WaDisableVLVClockGating_VBIIssue:vlv
Jesse Barnes2d809572012-10-25 12:15:44 -07007458 * Disable clock gating on th GCFG unit to prevent a delay
7459 * in the reporting of vblank events.
7460 */
Ville Syrjälä7a0d1ee2014-01-22 21:33:04 +02007461 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007462}
7463
Ville Syrjäläa4565da2014-04-09 13:28:10 +03007464static void cherryview_init_clock_gating(struct drm_device *dev)
7465{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007466 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläa4565da2014-04-09 13:28:10 +03007467
Ville Syrjälä232ce332014-04-09 13:28:35 +03007468 /* WaVSRefCountFullforceMissDisable:chv */
7469 /* WaDSRefCountFullforceMissDisable:chv */
7470 I915_WRITE(GEN7_FF_THREAD_MODE,
7471 I915_READ(GEN7_FF_THREAD_MODE) &
7472 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Ville Syrjäläacea6f92014-04-09 13:28:36 +03007473
7474 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7475 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7476 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
Ville Syrjälä08466972014-04-09 13:28:37 +03007477
7478 /* WaDisableCSUnitClockGating:chv */
7479 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7480 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
Ville Syrjäläc6317802014-04-09 13:28:38 +03007481
7482 /* WaDisableSDEUnitClockGating:chv */
7483 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7484 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
Ville Syrjälä6d50b062015-05-19 20:32:57 +03007485
7486 /*
Imre Deak450174f2016-05-03 15:54:21 +03007487 * WaProgramL3SqcReg1Default:chv
7488 * See gfxspecs/Related Documents/Performance Guide/
7489 * LSQC Setting Recommendations.
7490 */
7491 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7492
7493 /*
Ville Syrjälä6d50b062015-05-19 20:32:57 +03007494 * GTT cache may not work with big pages, so if those
7495 * are ever enabled GTT cache may need to be disabled.
7496 */
7497 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
Ville Syrjäläa4565da2014-04-09 13:28:10 +03007498}
7499
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007500static void g4x_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007501{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007502 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007503 uint32_t dspclk_gate;
7504
7505 I915_WRITE(RENCLK_GATE_D1, 0);
7506 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7507 GS_UNIT_CLOCK_GATE_DISABLE |
7508 CL_UNIT_CLOCK_GATE_DISABLE);
7509 I915_WRITE(RAMCLK_GATE_D, 0);
7510 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7511 OVRUNIT_CLOCK_GATE_DISABLE |
7512 OVCUNIT_CLOCK_GATE_DISABLE;
7513 if (IS_GM45(dev))
7514 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7515 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
Daniel Vetter4358a372012-10-18 11:49:51 +02007516
7517 /* WaDisableRenderCachePipelinedFlush */
7518 I915_WRITE(CACHE_MODE_0,
7519 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
Ville Syrjäläde1aa622013-06-07 10:47:01 +03007520
Akash Goel4e046322014-04-04 17:14:38 +05307521 /* WaDisable_RenderCache_OperationalFlush:g4x */
7522 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7523
Ville Syrjälä0e088b82013-06-07 10:47:04 +03007524 g4x_disable_trickle_feed(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007525}
7526
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007527static void crestline_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007528{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007529 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007530
7531 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7532 I915_WRITE(RENCLK_GATE_D2, 0);
7533 I915_WRITE(DSPCLK_GATE_D, 0);
7534 I915_WRITE(RAMCLK_GATE_D, 0);
7535 I915_WRITE16(DEUC, 0);
Ville Syrjälä20f94962013-06-07 10:47:02 +03007536 I915_WRITE(MI_ARB_STATE,
7537 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Akash Goel4e046322014-04-04 17:14:38 +05307538
7539 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7540 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007541}
7542
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007543static void broadwater_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007544{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007545 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007546
7547 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7548 I965_RCC_CLOCK_GATE_DISABLE |
7549 I965_RCPB_CLOCK_GATE_DISABLE |
7550 I965_ISC_CLOCK_GATE_DISABLE |
7551 I965_FBC_CLOCK_GATE_DISABLE);
7552 I915_WRITE(RENCLK_GATE_D2, 0);
Ville Syrjälä20f94962013-06-07 10:47:02 +03007553 I915_WRITE(MI_ARB_STATE,
7554 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Akash Goel4e046322014-04-04 17:14:38 +05307555
7556 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7557 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007558}
7559
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007560static void gen3_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007561{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007562 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007563 u32 dstate = I915_READ(D_STATE);
7564
7565 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7566 DSTATE_DOT_CLOCK_GATING;
7567 I915_WRITE(D_STATE, dstate);
Chris Wilson13a86b82012-04-24 14:51:43 +01007568
7569 if (IS_PINEVIEW(dev))
7570 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
Daniel Vetter974a3b02012-09-09 11:54:16 +02007571
7572 /* IIR "flip pending" means done if this bit is set */
7573 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
Ville Syrjälä12fabbcb92014-02-25 15:13:38 +02007574
7575 /* interrupts should cause a wake up from C3 */
Ville Syrjälä32992542014-02-25 15:13:39 +02007576 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
Ville Syrjälädbb42742014-02-25 15:13:41 +02007577
7578 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7579 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
Ville Syrjälä10383922014-08-15 01:21:54 +03007580
7581 I915_WRITE(MI_ARB_STATE,
7582 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007583}
7584
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007585static void i85x_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007586{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007587 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007588
7589 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
Ville Syrjälä54e472a2014-02-25 15:13:40 +02007590
7591 /* interrupts should cause a wake up from C3 */
7592 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7593 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
Ville Syrjälä10383922014-08-15 01:21:54 +03007594
7595 I915_WRITE(MEM_MODE,
7596 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007597}
7598
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007599static void i830_init_clock_gating(struct drm_device *dev)
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007600{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007601 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007602
7603 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
Ville Syrjälä10383922014-08-15 01:21:54 +03007604
7605 I915_WRITE(MEM_MODE,
7606 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7607 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007608}
7609
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007610void intel_init_clock_gating(struct drm_device *dev)
7611{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007612 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007613
Imre Deakbb400da2016-03-16 13:38:54 +02007614 dev_priv->display.init_clock_gating(dev);
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03007615}
7616
Imre Deak7d708ee2013-04-17 14:04:50 +03007617void intel_suspend_hw(struct drm_device *dev)
7618{
7619 if (HAS_PCH_LPT(dev))
7620 lpt_suspend_hw(dev);
7621}
7622
Imre Deakbb400da2016-03-16 13:38:54 +02007623static void nop_init_clock_gating(struct drm_device *dev)
7624{
7625 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7626}
7627
7628/**
7629 * intel_init_clock_gating_hooks - setup the clock gating hooks
7630 * @dev_priv: device private
7631 *
7632 * Setup the hooks that configure which clocks of a given platform can be
7633 * gated and also apply various GT and display specific workarounds for these
7634 * platforms. Note that some GT specific workarounds are applied separately
7635 * when GPU contexts or batchbuffers start their execution.
7636 */
7637void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7638{
7639 if (IS_SKYLAKE(dev_priv))
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02007640 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007641 else if (IS_KABYLAKE(dev_priv))
Mika Kuoppala9498dba2016-06-07 17:19:01 +03007642 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
Imre Deakbb400da2016-03-16 13:38:54 +02007643 else if (IS_BROXTON(dev_priv))
7644 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7645 else if (IS_BROADWELL(dev_priv))
7646 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7647 else if (IS_CHERRYVIEW(dev_priv))
7648 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7649 else if (IS_HASWELL(dev_priv))
7650 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7651 else if (IS_IVYBRIDGE(dev_priv))
7652 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7653 else if (IS_VALLEYVIEW(dev_priv))
7654 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7655 else if (IS_GEN6(dev_priv))
7656 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7657 else if (IS_GEN5(dev_priv))
7658 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7659 else if (IS_G4X(dev_priv))
7660 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7661 else if (IS_CRESTLINE(dev_priv))
7662 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7663 else if (IS_BROADWATER(dev_priv))
7664 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7665 else if (IS_GEN3(dev_priv))
7666 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7667 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7668 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7669 else if (IS_GEN2(dev_priv))
7670 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7671 else {
7672 MISSING_CASE(INTEL_DEVID(dev_priv));
7673 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7674 }
7675}
7676
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007677/* Set up chip specific power management-related functions */
7678void intel_init_pm(struct drm_device *dev)
7679{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007680 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007681
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02007682 intel_fbc_init(dev_priv);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007683
Daniel Vetterc921aba2012-04-26 23:28:17 +02007684 /* For cxsr */
7685 if (IS_PINEVIEW(dev))
7686 i915_pineview_get_mem_freq(dev);
7687 else if (IS_GEN5(dev))
7688 i915_ironlake_get_mem_freq(dev);
7689
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007690 /* For FIFO watermark updates */
Damien Lespiauf5ed50c2014-11-13 17:51:52 +00007691 if (INTEL_INFO(dev)->gen >= 9) {
Pradeep Bhat2af30a52014-11-04 17:06:38 +00007692 skl_setup_wm_latency(dev);
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00007693 dev_priv->display.update_wm = skl_update_wm;
Matt Roper98d39492016-05-12 07:06:03 -07007694 dev_priv->display.compute_global_watermarks = skl_compute_wm;
Damien Lespiauc83155a2014-03-28 00:18:35 +05307695 } else if (HAS_PCH_SPLIT(dev)) {
Damien Lespiaufa50ad62014-03-17 18:01:16 +00007696 ilk_setup_wm_latency(dev);
Ville Syrjälä53615a52013-08-01 16:18:50 +03007697
Ville Syrjäläbd602542014-01-07 16:14:10 +02007698 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7699 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7700 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7701 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
Matt Roper86c8bbb2015-09-24 15:53:16 -07007702 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
Matt Ropered4a6a72016-02-23 17:20:13 -08007703 dev_priv->display.compute_intermediate_wm =
7704 ilk_compute_intermediate_wm;
7705 dev_priv->display.initial_watermarks =
7706 ilk_initial_watermarks;
7707 dev_priv->display.optimize_watermarks =
7708 ilk_optimize_watermarks;
Ville Syrjäläbd602542014-01-07 16:14:10 +02007709 } else {
7710 DRM_DEBUG_KMS("Failed to read display plane latency. "
7711 "Disable CxSR\n");
7712 }
Ville Syrjäläa4565da2014-04-09 13:28:10 +03007713 } else if (IS_CHERRYVIEW(dev)) {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03007714 vlv_setup_wm_latency(dev);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03007715 dev_priv->display.update_wm = vlv_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007716 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä26e1fe42015-06-24 22:00:06 +03007717 vlv_setup_wm_latency(dev);
Ville Syrjälä26e1fe42015-06-24 22:00:06 +03007718 dev_priv->display.update_wm = vlv_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007719 } else if (IS_PINEVIEW(dev)) {
7720 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7721 dev_priv->is_ddr3,
7722 dev_priv->fsb_freq,
7723 dev_priv->mem_freq)) {
7724 DRM_INFO("failed to find known CxSR latency "
7725 "(found ddr%s fsb freq %d, mem freq %d), "
7726 "disabling CxSR\n",
7727 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7728 dev_priv->fsb_freq, dev_priv->mem_freq);
7729 /* Disable CxSR and never update its watermark again */
Imre Deak5209b1f2014-07-01 12:36:17 +03007730 intel_set_memory_cxsr(dev_priv, false);
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007731 dev_priv->display.update_wm = NULL;
7732 } else
7733 dev_priv->display.update_wm = pineview_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007734 } else if (IS_G4X(dev)) {
7735 dev_priv->display.update_wm = g4x_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007736 } else if (IS_GEN4(dev)) {
7737 dev_priv->display.update_wm = i965_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007738 } else if (IS_GEN3(dev)) {
7739 dev_priv->display.update_wm = i9xx_update_wm;
7740 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007741 } else if (IS_GEN2(dev)) {
7742 if (INTEL_INFO(dev)->num_pipes == 1) {
7743 dev_priv->display.update_wm = i845_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007744 dev_priv->display.get_fifo_size = i845_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007745 } else {
7746 dev_priv->display.update_wm = i9xx_update_wm;
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007747 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007748 }
Daniel Vetterfeb56b92013-12-14 20:38:30 -02007749 } else {
7750 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007751 }
7752}
7753
Lyude87660502016-08-17 15:55:53 -04007754static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7755{
7756 uint32_t flags =
7757 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7758
7759 switch (flags) {
7760 case GEN6_PCODE_SUCCESS:
7761 return 0;
7762 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7763 case GEN6_PCODE_ILLEGAL_CMD:
7764 return -ENXIO;
7765 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
Chris Wilson7850d1c2016-08-26 11:59:26 +01007766 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
Lyude87660502016-08-17 15:55:53 -04007767 return -EOVERFLOW;
7768 case GEN6_PCODE_TIMEOUT:
7769 return -ETIMEDOUT;
7770 default:
7771 MISSING_CASE(flags)
7772 return 0;
7773 }
7774}
7775
7776static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7777{
7778 uint32_t flags =
7779 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7780
7781 switch (flags) {
7782 case GEN6_PCODE_SUCCESS:
7783 return 0;
7784 case GEN6_PCODE_ILLEGAL_CMD:
7785 return -ENXIO;
7786 case GEN7_PCODE_TIMEOUT:
7787 return -ETIMEDOUT;
7788 case GEN7_PCODE_ILLEGAL_DATA:
7789 return -EINVAL;
7790 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7791 return -EOVERFLOW;
7792 default:
7793 MISSING_CASE(flags);
7794 return 0;
7795 }
7796}
7797
Tom O'Rourke151a49d2014-11-13 18:50:10 -08007798int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
Ben Widawsky42c05262012-09-26 10:34:00 -07007799{
Lyude87660502016-08-17 15:55:53 -04007800 int status;
7801
Jesse Barnes4fc688c2012-11-02 11:14:01 -07007802 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Ben Widawsky42c05262012-09-26 10:34:00 -07007803
Chris Wilson3f5582d2016-06-30 15:32:45 +01007804 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7805 * use te fw I915_READ variants to reduce the amount of work
7806 * required when reading/writing.
7807 */
7808
7809 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
Ben Widawsky42c05262012-09-26 10:34:00 -07007810 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7811 return -EAGAIN;
7812 }
7813
Chris Wilson3f5582d2016-06-30 15:32:45 +01007814 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7815 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7816 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
Ben Widawsky42c05262012-09-26 10:34:00 -07007817
Chris Wilson3f5582d2016-06-30 15:32:45 +01007818 if (intel_wait_for_register_fw(dev_priv,
7819 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7820 500)) {
Ben Widawsky42c05262012-09-26 10:34:00 -07007821 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7822 return -ETIMEDOUT;
7823 }
7824
Chris Wilson3f5582d2016-06-30 15:32:45 +01007825 *val = I915_READ_FW(GEN6_PCODE_DATA);
7826 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
Ben Widawsky42c05262012-09-26 10:34:00 -07007827
Lyude87660502016-08-17 15:55:53 -04007828 if (INTEL_GEN(dev_priv) > 6)
7829 status = gen7_check_mailbox_status(dev_priv);
7830 else
7831 status = gen6_check_mailbox_status(dev_priv);
7832
7833 if (status) {
7834 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7835 status);
7836 return status;
7837 }
7838
Ben Widawsky42c05262012-09-26 10:34:00 -07007839 return 0;
7840}
7841
Chris Wilson3f5582d2016-06-30 15:32:45 +01007842int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
Lyude87660502016-08-17 15:55:53 -04007843 u32 mbox, u32 val)
Ben Widawsky42c05262012-09-26 10:34:00 -07007844{
Lyude87660502016-08-17 15:55:53 -04007845 int status;
7846
Jesse Barnes4fc688c2012-11-02 11:14:01 -07007847 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Ben Widawsky42c05262012-09-26 10:34:00 -07007848
Chris Wilson3f5582d2016-06-30 15:32:45 +01007849 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7850 * use te fw I915_READ variants to reduce the amount of work
7851 * required when reading/writing.
7852 */
7853
7854 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
Ben Widawsky42c05262012-09-26 10:34:00 -07007855 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7856 return -EAGAIN;
7857 }
7858
Chris Wilson3f5582d2016-06-30 15:32:45 +01007859 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7860 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
Ben Widawsky42c05262012-09-26 10:34:00 -07007861
Chris Wilson3f5582d2016-06-30 15:32:45 +01007862 if (intel_wait_for_register_fw(dev_priv,
7863 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7864 500)) {
Ben Widawsky42c05262012-09-26 10:34:00 -07007865 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7866 return -ETIMEDOUT;
7867 }
7868
Chris Wilson3f5582d2016-06-30 15:32:45 +01007869 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
Ben Widawsky42c05262012-09-26 10:34:00 -07007870
Lyude87660502016-08-17 15:55:53 -04007871 if (INTEL_GEN(dev_priv) > 6)
7872 status = gen7_check_mailbox_status(dev_priv);
7873 else
7874 status = gen6_check_mailbox_status(dev_priv);
7875
7876 if (status) {
7877 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7878 status);
7879 return status;
7880 }
7881
Ben Widawsky42c05262012-09-26 10:34:00 -07007882 return 0;
7883}
Jesse Barnesa0e4e192013-04-02 11:23:05 -07007884
Ville Syrjälädd06f882014-11-10 22:55:12 +02007885static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7886{
Ville Syrjäläc30fec62016-03-04 21:43:02 +02007887 /*
7888 * N = val - 0xb7
7889 * Slow = Fast = GPLL ref * N
7890 */
7891 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
Jesse Barnes855ba3b2013-04-17 15:54:57 -07007892}
7893
Fengguang Wub55dd642014-07-12 11:21:39 +02007894static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
Jesse Barnes855ba3b2013-04-17 15:54:57 -07007895{
Ville Syrjäläc30fec62016-03-04 21:43:02 +02007896 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
Jesse Barnes855ba3b2013-04-17 15:54:57 -07007897}
7898
Fengguang Wub55dd642014-07-12 11:21:39 +02007899static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
Deepak S22b1b2f2014-07-12 14:54:33 +05307900{
Ville Syrjäläc30fec62016-03-04 21:43:02 +02007901 /*
7902 * N = val / 2
7903 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7904 */
7905 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
Deepak S22b1b2f2014-07-12 14:54:33 +05307906}
7907
Fengguang Wub55dd642014-07-12 11:21:39 +02007908static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
Deepak S22b1b2f2014-07-12 14:54:33 +05307909{
Ville Syrjälä1c147622014-08-18 14:42:43 +03007910 /* CHV needs even values */
Ville Syrjäläc30fec62016-03-04 21:43:02 +02007911 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
Deepak S22b1b2f2014-07-12 14:54:33 +05307912}
7913
Ville Syrjälä616bc822015-01-23 21:04:25 +02007914int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7915{
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007916 if (IS_GEN9(dev_priv))
Mika Kuoppala500a3d22015-11-13 19:29:41 +02007917 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7918 GEN9_FREQ_SCALER);
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007919 else if (IS_CHERRYVIEW(dev_priv))
Ville Syrjälä616bc822015-01-23 21:04:25 +02007920 return chv_gpu_freq(dev_priv, val);
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007921 else if (IS_VALLEYVIEW(dev_priv))
Ville Syrjälä616bc822015-01-23 21:04:25 +02007922 return byt_gpu_freq(dev_priv, val);
7923 else
7924 return val * GT_FREQUENCY_MULTIPLIER;
7925}
7926
Ville Syrjälä616bc822015-01-23 21:04:25 +02007927int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7928{
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007929 if (IS_GEN9(dev_priv))
Mika Kuoppala500a3d22015-11-13 19:29:41 +02007930 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7931 GT_FREQUENCY_MULTIPLIER);
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007932 else if (IS_CHERRYVIEW(dev_priv))
Ville Syrjälä616bc822015-01-23 21:04:25 +02007933 return chv_freq_opcode(dev_priv, val);
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007934 else if (IS_VALLEYVIEW(dev_priv))
Ville Syrjälä616bc822015-01-23 21:04:25 +02007935 return byt_freq_opcode(dev_priv, val);
7936 else
Mika Kuoppala500a3d22015-11-13 19:29:41 +02007937 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
Deepak S22b1b2f2014-07-12 14:54:33 +05307938}
7939
Chris Wilson6ad790c2015-04-07 16:20:31 +01007940struct request_boost {
7941 struct work_struct work;
Daniel Vettereed29a52015-05-21 14:21:25 +02007942 struct drm_i915_gem_request *req;
Chris Wilson6ad790c2015-04-07 16:20:31 +01007943};
7944
7945static void __intel_rps_boost_work(struct work_struct *work)
7946{
7947 struct request_boost *boost = container_of(work, struct request_boost, work);
Chris Wilsone61b9952015-04-27 13:41:24 +01007948 struct drm_i915_gem_request *req = boost->req;
Chris Wilson6ad790c2015-04-07 16:20:31 +01007949
Chris Wilsonf69a02c2016-07-01 17:23:16 +01007950 if (!i915_gem_request_completed(req))
Chris Wilsonc0336662016-05-06 15:40:21 +01007951 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
Chris Wilson6ad790c2015-04-07 16:20:31 +01007952
Chris Wilsone8a261e2016-07-20 13:31:49 +01007953 i915_gem_request_put(req);
Chris Wilson6ad790c2015-04-07 16:20:31 +01007954 kfree(boost);
7955}
7956
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01007957void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
Chris Wilson6ad790c2015-04-07 16:20:31 +01007958{
7959 struct request_boost *boost;
7960
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01007961 if (req == NULL || INTEL_GEN(req->i915) < 6)
Chris Wilson6ad790c2015-04-07 16:20:31 +01007962 return;
7963
Chris Wilsonf69a02c2016-07-01 17:23:16 +01007964 if (i915_gem_request_completed(req))
Chris Wilsone61b9952015-04-27 13:41:24 +01007965 return;
7966
Chris Wilson6ad790c2015-04-07 16:20:31 +01007967 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7968 if (boost == NULL)
7969 return;
7970
Chris Wilsone8a261e2016-07-20 13:31:49 +01007971 boost->req = i915_gem_request_get(req);
Chris Wilson6ad790c2015-04-07 16:20:31 +01007972
7973 INIT_WORK(&boost->work, __intel_rps_boost_work);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01007974 queue_work(req->i915->wq, &boost->work);
Chris Wilson6ad790c2015-04-07 16:20:31 +01007975}
7976
Daniel Vetterf742a552013-12-06 10:17:53 +01007977void intel_pm_setup(struct drm_device *dev)
Chris Wilson907b28c2013-07-19 20:36:52 +01007978{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007979 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01007980
Daniel Vetterf742a552013-12-06 10:17:53 +01007981 mutex_init(&dev_priv->rps.hw_lock);
Chris Wilson8d3afd72015-05-21 21:01:47 +01007982 spin_lock_init(&dev_priv->rps.client_lock);
Daniel Vetterf742a552013-12-06 10:17:53 +01007983
Chris Wilson54b4f682016-07-21 21:16:19 +01007984 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7985 __intel_autoenable_gt_powersave);
Chris Wilson1854d5c2015-04-07 16:20:32 +01007986 INIT_LIST_HEAD(&dev_priv->rps.clients);
Paulo Zanoni5d584b22014-03-07 20:08:15 -03007987
Paulo Zanoni33688d92014-03-07 20:08:19 -03007988 dev_priv->pm.suspended = false;
Imre Deak1f814da2015-12-16 02:52:19 +02007989 atomic_set(&dev_priv->pm.wakeref_count, 0);
Imre Deak2b19efe2015-12-15 20:10:37 +02007990 atomic_set(&dev_priv->pm.atomic_seq, 0);
Chris Wilson907b28c2013-07-19 20:36:52 +01007991}