blob: 1e3b5eebd2a2daf8d7b6b237e480ea1080be94fe [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
Chris Wilson5d723d72016-08-04 16:32:35 +010037#include "intel_frontbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010038#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080039#include "i915_drv.h"
Chris Wilsonc37efb92016-06-17 08:28:47 +010040#include "i915_gem_dmabuf.h"
Imre Deakdb18b6a2016-03-24 12:41:40 +020041#include "intel_dsi.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070042#include "i915_trace.h"
Xi Ruoyao319c1d42015-03-12 20:16:32 +080043#include <drm/drm_atomic.h>
Matt Roperc196e1d2015-01-21 16:35:48 -080044#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010045#include <drm/drm_dp_helper.h>
46#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070047#include <drm/drm_plane_helper.h>
48#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080049#include <linux/dma_remapping.h>
Alex Goinsfd8e0582015-11-25 18:43:38 -080050#include <linux/reservation.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080051
Daniel Vetter5a21b662016-05-24 17:13:53 +020052static bool is_mmio_work(struct intel_flip_work *work)
53{
54 return work->mmio_work.func;
55}
56
Matt Roper465c1202014-05-29 08:06:54 -070057/* Primary plane formats for gen <= 3 */
Damien Lespiau568db4f2015-05-12 16:13:18 +010058static const uint32_t i8xx_primary_formats[] = {
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010059 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
Matt Roper465c1202014-05-29 08:06:54 -070061 DRM_FORMAT_XRGB1555,
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010062 DRM_FORMAT_XRGB8888,
Matt Roper465c1202014-05-29 08:06:54 -070063};
64
65/* Primary plane formats for gen >= 4 */
Damien Lespiau568db4f2015-05-12 16:13:18 +010066static const uint32_t i965_primary_formats[] = {
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010067 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
Matt Roper465c1202014-05-29 08:06:54 -070070 DRM_FORMAT_XBGR8888,
Damien Lespiau6c0fd452015-05-19 12:29:16 +010071 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73};
74
75static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010080 DRM_FORMAT_ARGB8888,
Matt Roper465c1202014-05-29 08:06:54 -070081 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
Matt Roper465c1202014-05-29 08:06:54 -070083 DRM_FORMAT_XBGR2101010,
Kumar, Maheshea916ea2015-09-03 16:17:09 +053084 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
Matt Roper465c1202014-05-29 08:06:54 -070088};
89
Matt Roper3d7d6512014-06-10 08:28:13 -070090/* Cursor formats */
91static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93};
94
Jesse Barnesf1f644d2013-06-27 00:39:25 +030095static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020096 struct intel_crtc_state *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030097static void ironlake_pch_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020098 struct intel_crtc_state *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030099
Jesse Barneseb1bfe82014-02-12 12:26:25 -0800100static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +0200104static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Jani Nikulabc58be62016-03-18 17:05:39 +0200106static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +0200107static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -0700108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +0200110static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +0200111static void haswell_set_pipeconf(struct drm_crtc *crtc);
Jani Nikula391bf042016-03-18 17:05:40 +0200112static void haswell_set_pipemisc(struct drm_crtc *crtc);
Ville Syrjäläd288f652014-10-28 13:20:22 +0200113static void vlv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200114 const struct intel_crtc_state *pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +0200115static void chv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200116 const struct intel_crtc_state *pipe_config);
Daniel Vetter5a21b662016-05-24 17:13:53 +0200117static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
Chandra Konduru549e2bf2015-04-07 15:28:38 -0700119static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +0200121static void skylake_pfit_enable(struct intel_crtc *crtc);
122static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123static void ironlake_pfit_enable(struct intel_crtc *crtc);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +0200124static void intel_modeset_setup_hw_state(struct drm_device *dev);
Ville Syrjälä2622a082016-03-09 19:07:26 +0200125static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
Ville Syrjälä4e5ca602016-05-11 22:44:44 +0300126static int ilk_max_pixel_rate(struct drm_atomic_state *state);
Imre Deak324513c2016-06-13 16:44:36 +0300127static int bxt_calc_cdclk(int max_pixclk);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100128
Ma Lingd4906092009-03-18 20:13:27 +0800129struct intel_limit {
Ander Conselvan de Oliveira4c5def92016-05-04 12:11:58 +0300130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
Ma Lingd4906092009-03-18 20:13:27 +0800138};
Jesse Barnes79e53942008-11-07 14:24:08 -0800139
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300140/* returns HPLL frequency in kHz */
141static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142{
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152}
153
Ville Syrjäläc30fec62016-03-04 21:43:02 +0200154int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300156{
157 u32 val;
158 int divider;
159
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
Ville Syrjäläc30fec62016-03-04 21:43:02 +0200170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171}
172
173static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175{
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300181}
182
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200183static int
184intel_pch_rawclk(struct drm_i915_private *dev_priv)
Daniel Vetterd2acd212012-10-20 20:57:43 +0200185{
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
Daniel Vetterd2acd212012-10-20 20:57:43 +0200187}
188
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200189static int
190intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
Jani Nikula79e50a42015-08-26 10:58:20 +0300191{
Ville Syrjälä19ab4ed2016-04-27 17:43:22 +0300192 /* RAWCLK_FREQ_VLV register updated from power well code */
Ville Syrjälä35d38d12016-03-02 17:22:16 +0200193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200195}
196
197static int
198intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199{
Jani Nikula79e50a42015-08-26 10:58:20 +0300200 uint32_t clkcfg;
201
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200202 /* hrawclock is 1/4 the FSB frequency */
Jani Nikula79e50a42015-08-26 10:58:20 +0300203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200206 return 100000;
Jani Nikula79e50a42015-08-26 10:58:20 +0300207 case CLKCFG_FSB_533:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200208 return 133333;
Jani Nikula79e50a42015-08-26 10:58:20 +0300209 case CLKCFG_FSB_667:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200210 return 166667;
Jani Nikula79e50a42015-08-26 10:58:20 +0300211 case CLKCFG_FSB_800:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200212 return 200000;
Jani Nikula79e50a42015-08-26 10:58:20 +0300213 case CLKCFG_FSB_1067:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200214 return 266667;
Jani Nikula79e50a42015-08-26 10:58:20 +0300215 case CLKCFG_FSB_1333:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200216 return 333333;
Jani Nikula79e50a42015-08-26 10:58:20 +0300217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200220 return 400000;
Jani Nikula79e50a42015-08-26 10:58:20 +0300221 default:
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200222 return 133333;
Jani Nikula79e50a42015-08-26 10:58:20 +0300223 }
224}
225
Ville Syrjälä19ab4ed2016-04-27 17:43:22 +0300226void intel_update_rawclk(struct drm_i915_private *dev_priv)
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +0200227{
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238}
239
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300240static void intel_update_czclk(struct drm_i915_private *dev_priv)
241{
Wayne Boyer666a4532015-12-09 12:29:35 -0800242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249}
250
Chris Wilson021357a2010-09-07 20:54:59 +0100251static inline u32 /* units of 100MHz */
Ville Syrjälä21a727b2016-02-17 21:41:10 +0200252intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
Chris Wilson021357a2010-09-07 20:54:59 +0100254{
Ville Syrjälä21a727b2016-02-17 21:41:10 +0200255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
Ville Syrjäläe3b247d2016-02-17 21:41:09 +0200259 else
Ville Syrjälä21a727b2016-02-17 21:41:10 +0200260 return 270000;
Chris Wilson021357a2010-09-07 20:54:59 +0100261}
262
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300263static const struct intel_limit intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400264 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200265 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200266 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700274};
275
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300276static const struct intel_limit intel_limits_i8xx_dvo = {
Daniel Vetter5d536e22013-07-06 12:52:06 +0200277 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200278 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200279 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287};
288
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300289static const struct intel_limit intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400290 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200291 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200292 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700300};
Eric Anholt273e27c2011-03-30 13:01:10 -0700301
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300302static const struct intel_limit intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700313};
314
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300315static const struct intel_limit intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700326};
327
Eric Anholt273e27c2011-03-30 13:01:10 -0700328
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300329static const struct intel_limit intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800341 },
Keith Packarde4b36692009-06-05 19:22:17 -0700342};
343
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300344static const struct intel_limit intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700355};
356
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300357static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800368 },
Keith Packarde4b36692009-06-05 19:22:17 -0700369};
370
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300371static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800382 },
Keith Packarde4b36692009-06-05 19:22:17 -0700383};
384
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300385static const struct intel_limit intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700388 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700391 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700398};
399
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300400static const struct intel_limit intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700411};
412
Eric Anholt273e27c2011-03-30 13:01:10 -0700413/* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300418static const struct intel_limit intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700429};
430
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300431static const struct intel_limit intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800442};
443
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300444static const struct intel_limit intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800455};
456
Eric Anholt273e27c2011-03-30 13:01:10 -0700457/* LVDS 100mhz refclk limits. */
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300458static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400466 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800469};
470
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300471static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400479 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800482};
483
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300484static const struct intel_limit intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200492 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700493 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300496 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700498};
499
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300500static const struct intel_limit intel_limits_chv = {
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
Ville Syrjälä17fe1022015-02-26 21:01:52 +0200508 .vco = { .min = 4800000, .max = 6480000 },
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514};
515
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300516static const struct intel_limit intel_limits_bxt = {
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
Vandana Kannane6292552015-07-01 17:02:57 +0530519 .vco = { .min = 4800000, .max = 6700000 },
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526};
527
Ander Conselvan de Oliveiracdba9542015-06-01 12:49:51 +0200528static bool
529needs_modeset(struct drm_crtc_state *state)
530{
Maarten Lankhorstfc596662015-07-21 13:28:57 +0200531 return drm_atomic_crtc_needs_modeset(state);
Ander Conselvan de Oliveiracdba9542015-06-01 12:49:51 +0200532}
533
Imre Deakdccbea32015-06-22 23:35:51 +0300534/*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500542/* m1 is reserved as 0 in Pineview, n is a ring counter */
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300543static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800544{
Shaohua Li21778322009-02-23 15:19:16 +0800545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200547 if (WARN_ON(clock->n == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300548 return 0;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300551
552 return clock->dot;
Shaohua Li21778322009-02-23 15:19:16 +0800553}
554
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200555static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556{
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558}
559
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300560static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800561{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200562 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800563 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300565 return 0;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300568
569 return clock->dot;
Jesse Barnes79e53942008-11-07 14:24:08 -0800570}
571
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300572static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
Imre Deak589eca62015-06-22 23:35:50 +0300573{
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300577 return 0;
Imre Deak589eca62015-06-22 23:35:50 +0300578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300580
581 return clock->dot / 5;
Imre Deak589eca62015-06-22 23:35:50 +0300582}
583
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300584int chv_calc_dpll_params(int refclk, struct dpll *clock)
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300585{
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300589 return 0;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300593
594 return clock->dot / 5;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300595}
596
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800597#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800598/**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
Chris Wilson1b894b52010-12-14 20:04:54 +0000603static bool intel_PLL_is_valid(struct drm_device *dev,
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300604 const struct intel_limit *limit,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300605 const struct dpll *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800606{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400610 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400612 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400614 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300615
Wayne Boyer666a4532015-12-09 12:29:35 -0800616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
Wayne Boyer666a4532015-12-09 12:29:35 -0800621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
Jesse Barnes79e53942008-11-07 14:24:08 -0800628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400629 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400634 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800635
636 return true;
637}
638
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300639static int
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300640i9xx_select_p2_div(const struct intel_limit *limit,
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300641 const struct intel_crtc_state *crtc_state,
642 int target)
Jesse Barnes79e53942008-11-07 14:24:08 -0800643{
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300644 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +0300646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800647 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800651 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100652 if (intel_is_dual_link_lvds(dev))
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300653 return limit->p2.p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800654 else
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300655 return limit->p2.p2_slow;
Jesse Barnes79e53942008-11-07 14:24:08 -0800656 } else {
657 if (target < limit->p2.dot_limit)
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300658 return limit->p2.p2_slow;
Jesse Barnes79e53942008-11-07 14:24:08 -0800659 else
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300660 return limit->p2.p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800661 }
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300662}
663
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +0200664/*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300674static bool
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300675i9xx_find_best_dpll(const struct intel_limit *limit,
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300676 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300679{
680 struct drm_device *dev = crtc_state->base.crtc->dev;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300681 struct dpll clock;
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300682 int err = target;
Jesse Barnes79e53942008-11-07 14:24:08 -0800683
Akshay Joshi0206e352011-08-16 15:34:10 -0400684 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800685
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
Zhao Yakui42158662009-11-20 11:24:18 +0800688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200692 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800693 break;
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800698 int this_err;
699
Imre Deakdccbea32015-06-22 23:35:51 +0300700 i9xx_calc_dpll_params(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800703 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719}
720
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +0200721/*
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 *
726 * Target and reference clocks are specified in kHz.
727 *
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
730 */
Ma Lingd4906092009-03-18 20:13:27 +0800731static bool
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300732pnv_find_best_dpll(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200733 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200736{
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300737 struct drm_device *dev = crtc_state->base.crtc->dev;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300738 struct dpll clock;
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200739 int err = target;
740
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200741 memset(best_clock, 0, sizeof(*best_clock));
742
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
746 clock.m1++) {
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
753 int this_err;
754
Imre Deakdccbea32015-06-22 23:35:51 +0300755 pnv_calc_dpll_params(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800756 if (!intel_PLL_is_valid(dev, limit,
757 &clock))
758 continue;
759 if (match_clock &&
760 clock.p != match_clock->p)
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
765 *best_clock = clock;
766 err = this_err;
767 }
768 }
769 }
770 }
771 }
772
773 return (err != target);
774}
775
Ander Conselvan de Oliveira997c0302016-03-21 18:00:12 +0200776/*
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +0200780 *
781 * Target and reference clocks are specified in kHz.
782 *
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
Ander Conselvan de Oliveira997c0302016-03-21 18:00:12 +0200785 */
Ma Lingd4906092009-03-18 20:13:27 +0800786static bool
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300787g4x_find_best_dpll(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200788 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800791{
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300792 struct drm_device *dev = crtc_state->base.crtc->dev;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300793 struct dpll clock;
Ma Lingd4906092009-03-18 20:13:27 +0800794 int max_n;
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300795 bool found = false;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800798
799 memset(best_clock, 0, sizeof(*best_clock));
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300800
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
802
Ma Lingd4906092009-03-18 20:13:27 +0800803 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200804 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200806 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
813 int this_err;
814
Imre Deakdccbea32015-06-22 23:35:51 +0300815 i9xx_calc_dpll_params(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000816 if (!intel_PLL_is_valid(dev, limit,
817 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800818 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000819
820 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800821 if (this_err < err_most) {
822 *best_clock = clock;
823 err_most = this_err;
824 max_n = clock.n;
825 found = true;
826 }
827 }
828 }
829 }
830 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800831 return found;
832}
Ma Lingd4906092009-03-18 20:13:27 +0800833
Imre Deakd5dd62b2015-03-17 11:40:03 +0200834/*
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
837 */
838static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
Imre Deakd5dd62b2015-03-17 11:40:03 +0200841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
843{
Imre Deak9ca3ba02015-03-17 11:40:05 +0200844 /*
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
847 */
848 if (IS_CHERRYVIEW(dev)) {
849 *error_ppm = 0;
850
851 return calculated_clock->p > best_clock->p;
852 }
853
Imre Deak24be4e42015-03-17 11:40:04 +0200854 if (WARN_ON_ONCE(!target_freq))
855 return false;
856
Imre Deakd5dd62b2015-03-17 11:40:03 +0200857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
859 target_freq);
860 /*
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
864 */
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866 *error_ppm = 0;
867
868 return true;
869 }
870
871 return *error_ppm + 10 < best_error_ppm;
872}
873
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +0200874/*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800879static bool
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300880vlv_find_best_dpll(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200881 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700884{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300886 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300887 struct dpll clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300888 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300891 bool found = false;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700892
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300893 target *= 5; /* fast clock */
894
895 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700896
897 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300902 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700903 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Imre Deakd5dd62b2015-03-17 11:40:03 +0200905 unsigned int ppm;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300906
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
908 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300909
Imre Deakdccbea32015-06-22 23:35:51 +0300910 vlv_calc_dpll_params(refclk, &clock);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300911
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300912 if (!intel_PLL_is_valid(dev, limit,
913 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300914 continue;
915
Imre Deakd5dd62b2015-03-17 11:40:03 +0200916 if (!vlv_PLL_is_optimal(dev, target,
917 &clock,
918 best_clock,
919 bestppm, &ppm))
920 continue;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300921
Imre Deakd5dd62b2015-03-17 11:40:03 +0200922 *best_clock = clock;
923 bestppm = ppm;
924 found = true;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700925 }
926 }
927 }
928 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700929
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300930 return found;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700931}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700932
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +0200933/*
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
937 */
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300938static bool
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +0300939chv_find_best_dpll(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200940 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300943{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300945 struct drm_device *dev = crtc->base.dev;
Imre Deak9ca3ba02015-03-17 11:40:05 +0200946 unsigned int best_error_ppm;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300947 struct dpll clock;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300948 uint64_t m2;
949 int found = false;
950
951 memset(best_clock, 0, sizeof(*best_clock));
Imre Deak9ca3ba02015-03-17 11:40:05 +0200952 best_error_ppm = 1000000;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300953
954 /*
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
958 */
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
961
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Imre Deak9ca3ba02015-03-17 11:40:05 +0200966 unsigned int error_ppm;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300967
968 clock.p = clock.p1 * clock.p2;
969
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
972
973 if (m2 > INT_MAX/clock.m1)
974 continue;
975
976 clock.m2 = m2;
977
Imre Deakdccbea32015-06-22 23:35:51 +0300978 chv_calc_dpll_params(refclk, &clock);
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300979
980 if (!intel_PLL_is_valid(dev, limit, &clock))
981 continue;
982
Imre Deak9ca3ba02015-03-17 11:40:05 +0200983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
985 continue;
986
987 *best_clock = clock;
988 best_error_ppm = error_ppm;
989 found = true;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300990 }
991 }
992
993 return found;
994}
995
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200996bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300997 struct dpll *best_clock)
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200998{
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +0200999 int refclk = 100000;
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03001000 const struct intel_limit *limit = &intel_limits_bxt;
Imre Deak5ab7b0b2015-03-06 03:29:25 +02001001
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +02001002 return chv_find_best_dpll(limit, crtc_state,
Imre Deak5ab7b0b2015-03-06 03:29:25 +02001003 target_clock, refclk, NULL, best_clock);
1004}
1005
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001006bool intel_crtc_active(struct drm_crtc *crtc)
1007{
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1012 *
Damien Lespiau241bfc32013-09-25 16:45:37 +01001013 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001014 * as Haswell has gained clock readout/fastboot support.
1015 *
Dave Airlie66e514c2014-04-03 07:51:54 +10001016 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001017 * properly reconstruct framebuffers.
Matt Roperc3d1f432015-03-09 10:19:23 -07001018 *
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1021 * for atomic.
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001022 */
Matt Roperc3d1f432015-03-09 10:19:23 -07001023 return intel_crtc->active && crtc->primary->state->fb &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001024 intel_crtc->config->base.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001025}
1026
Paulo Zanonia5c961d2012-10-24 15:59:34 -02001027enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029{
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001033 return intel_crtc->config->cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -02001034}
1035
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001036static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001038 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001039 i915_reg_t reg = PIPEDSL(pipe);
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001040 u32 line1, line2;
1041 u32 line_mask;
1042
1043 if (IS_GEN2(dev))
1044 line_mask = DSL_LINEMASK_GEN2;
1045 else
1046 line_mask = DSL_LINEMASK_GEN3;
1047
1048 line1 = I915_READ(reg) & line_mask;
Daniel Vetter6adfb1e2015-07-07 09:10:40 +02001049 msleep(5);
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001050 line2 = I915_READ(reg) & line_mask;
1051
1052 return line1 == line2;
1053}
1054
Keith Packardab7ad7f2010-10-03 00:33:06 -07001055/*
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001057 * @crtc: crtc whose pipe to wait for
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001058 *
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1062 *
Keith Packardab7ad7f2010-10-03 00:33:06 -07001063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1065 *
1066 * Otherwise:
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +01001069 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001070 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001071static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001072{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001073 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001074 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001076 enum pipe pipe = crtc->pipe;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001077
Keith Packardab7ad7f2010-10-03 00:33:06 -07001078 if (INTEL_INFO(dev)->gen >= 4) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001079 i915_reg_t reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001080
Keith Packardab7ad7f2010-10-03 00:33:06 -07001081 /* Wait for the Pipe State to go off */
Chris Wilsonb8511f52016-06-30 15:32:53 +01001082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001085 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001086 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -07001087 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001089 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001090 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001091}
1092
Jesse Barnesb24e7172011-01-04 15:09:30 -08001093/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001094void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001096{
Jesse Barnesb24e7172011-01-04 15:09:30 -08001097 u32 val;
1098 bool cur_state;
1099
Ville Syrjälä649636e2015-09-22 19:50:01 +03001100 val = I915_READ(DPLL(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001101 cur_state = !!(val & DPLL_VCO_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001102 I915_STATE_WARN(cur_state != state,
Jesse Barnesb24e7172011-01-04 15:09:30 -08001103 "PLL state assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001104 onoff(state), onoff(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001105}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001106
Jani Nikula23538ef2013-08-27 15:12:22 +03001107/* XXX: the dsi pll is shared between MIPI DSI ports */
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +00001108void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
Jani Nikula23538ef2013-08-27 15:12:22 +03001109{
1110 u32 val;
1111 bool cur_state;
1112
Ville Syrjäläa5805162015-05-26 20:42:30 +03001113 mutex_lock(&dev_priv->sb_lock);
Jani Nikula23538ef2013-08-27 15:12:22 +03001114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
Ville Syrjäläa5805162015-05-26 20:42:30 +03001115 mutex_unlock(&dev_priv->sb_lock);
Jani Nikula23538ef2013-08-27 15:12:22 +03001116
1117 cur_state = val & DSI_PLL_VCO_EN;
Rob Clarke2c719b2014-12-15 13:56:32 -05001118 I915_STATE_WARN(cur_state != state,
Jani Nikula23538ef2013-08-27 15:12:22 +03001119 "DSI PLL state assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001120 onoff(state), onoff(cur_state));
Jani Nikula23538ef2013-08-27 15:12:22 +03001121}
Jani Nikula23538ef2013-08-27 15:12:22 +03001122
Jesse Barnes040484a2011-01-03 12:14:26 -08001123static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125{
Jesse Barnes040484a2011-01-03 12:14:26 -08001126 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001129
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001130 if (HAS_DDI(dev_priv)) {
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001131 /* DDI does not have a specific FDI_TX register */
Ville Syrjälä649636e2015-09-22 19:50:01 +03001132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
Paulo Zanoniad80a812012-10-24 16:06:19 -02001133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 } else {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001135 u32 val = I915_READ(FDI_TX_CTL(pipe));
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
Rob Clarke2c719b2014-12-15 13:56:32 -05001138 I915_STATE_WARN(cur_state != state,
Jesse Barnes040484a2011-01-03 12:14:26 -08001139 "FDI TX state assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001140 onoff(state), onoff(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001141}
1142#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147{
Jesse Barnes040484a2011-01-03 12:14:26 -08001148 u32 val;
1149 bool cur_state;
1150
Ville Syrjälä649636e2015-09-22 19:50:01 +03001151 val = I915_READ(FDI_RX_CTL(pipe));
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001152 cur_state = !!(val & FDI_RX_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001153 I915_STATE_WARN(cur_state != state,
Jesse Barnes040484a2011-01-03 12:14:26 -08001154 "FDI RX state assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001155 onoff(state), onoff(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001156}
1157#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162{
Jesse Barnes040484a2011-01-03 12:14:26 -08001163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01001166 if (IS_GEN5(dev_priv))
Jesse Barnes040484a2011-01-03 12:14:26 -08001167 return;
1168
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001170 if (HAS_DDI(dev_priv))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001171 return;
1172
Ville Syrjälä649636e2015-09-22 19:50:01 +03001173 val = I915_READ(FDI_TX_CTL(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
Jesse Barnes040484a2011-01-03 12:14:26 -08001175}
1176
Daniel Vetter55607e82013-06-16 21:42:39 +02001177void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001179{
Jesse Barnes040484a2011-01-03 12:14:26 -08001180 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001181 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001182
Ville Syrjälä649636e2015-09-22 19:50:01 +03001183 val = I915_READ(FDI_RX_CTL(pipe));
Daniel Vetter55607e82013-06-16 21:42:39 +02001184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001185 I915_STATE_WARN(cur_state != state,
Daniel Vetter55607e82013-06-16 21:42:39 +02001186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001187 onoff(state), onoff(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001188}
1189
Daniel Vetterb680c372014-09-19 18:27:27 +02001190void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 enum pipe pipe)
Jesse Barnesea0760c2011-01-04 15:09:32 -08001192{
Chris Wilson91c8a322016-07-05 10:40:23 +01001193 struct drm_device *dev = &dev_priv->drm;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001194 i915_reg_t pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001195 u32 val;
1196 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001197 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001198
Jani Nikulabedd4db2014-08-22 15:04:13 +03001199 if (WARN_ON(HAS_DDI(dev)))
1200 return;
1201
1202 if (HAS_PCH_SPLIT(dev)) {
1203 u32 port_sel;
1204
Imre Deak44cb7342016-08-10 14:07:29 +03001205 pp_reg = PP_CONTROL(0);
1206 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001207
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
Wayne Boyer666a4532015-12-09 12:29:35 -08001212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Jani Nikulabedd4db2014-08-22 15:04:13 +03001213 /* presumably write lock depends on pipe, not port select */
Imre Deak44cb7342016-08-10 14:07:29 +03001214 pp_reg = PP_CONTROL(pipe);
Jani Nikulabedd4db2014-08-22 15:04:13 +03001215 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001216 } else {
Imre Deak44cb7342016-08-10 14:07:29 +03001217 pp_reg = PP_CONTROL(0);
Jani Nikulabedd4db2014-08-22 15:04:13 +03001218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001220 }
1221
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001225 locked = false;
1226
Rob Clarke2c719b2014-12-15 13:56:32 -05001227 I915_STATE_WARN(panel_pipe == pipe && locked,
Jesse Barnesea0760c2011-01-04 15:09:32 -08001228 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001229 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001230}
1231
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001232static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234{
Chris Wilson91c8a322016-07-05 10:40:23 +01001235 struct drm_device *dev = &dev_priv->drm;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001236 bool cur_state;
1237
Paulo Zanonid9d82082014-02-27 16:30:56 -03001238 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä0b87c242015-09-22 19:47:51 +03001239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001240 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001242
Rob Clarke2c719b2014-12-15 13:56:32 -05001243 I915_STATE_WARN(cur_state != state,
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001245 pipe_name(pipe), onoff(state), onoff(cur_state));
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001246}
1247#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001250void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001252{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001253 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255 pipe);
Imre Deak4feed0e2016-02-12 18:55:14 +02001256 enum intel_display_power_domain power_domain;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001257
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetter8e636782012-01-22 01:36:48 +01001261 state = true;
1262
Imre Deak4feed0e2016-02-12 18:55:14 +02001263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni69310162013-01-29 16:35:19 -02001266 cur_state = !!(val & PIPECONF_ENABLE);
Imre Deak4feed0e2016-02-12 18:55:14 +02001267
1268 intel_display_power_put(dev_priv, power_domain);
1269 } else {
1270 cur_state = false;
Paulo Zanoni69310162013-01-29 16:35:19 -02001271 }
1272
Rob Clarke2c719b2014-12-15 13:56:32 -05001273 I915_STATE_WARN(cur_state != state,
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001274 "pipe %c assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001275 pipe_name(pipe), onoff(state), onoff(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001276}
1277
Chris Wilson931872f2012-01-16 23:01:13 +00001278static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280{
Jesse Barnesb24e7172011-01-04 15:09:30 -08001281 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001282 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001283
Ville Syrjälä649636e2015-09-22 19:50:01 +03001284 val = I915_READ(DSPCNTR(plane));
Chris Wilson931872f2012-01-16 23:01:13 +00001285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001286 I915_STATE_WARN(cur_state != state,
Chris Wilson931872f2012-01-16 23:01:13 +00001287 "plane %c assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001288 plane_name(plane), onoff(state), onoff(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001289}
1290
Chris Wilson931872f2012-01-16 23:01:13 +00001291#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
Jesse Barnesb24e7172011-01-04 15:09:30 -08001294static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296{
Chris Wilson91c8a322016-07-05 10:40:23 +01001297 struct drm_device *dev = &dev_priv->drm;
Ville Syrjälä649636e2015-09-22 19:50:01 +03001298 int i;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001299
Ville Syrjälä653e1022013-06-04 13:49:05 +03001300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001302 u32 val = I915_READ(DSPCNTR(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001304 "plane %c assertion failure, should be disabled but not\n",
1305 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001306 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001307 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001308
Jesse Barnesb24e7172011-01-04 15:09:30 -08001309 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001310 for_each_pipe(dev_priv, i) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
Jesse Barnesb24e7172011-01-04 15:09:30 -08001313 DISPPLANE_SEL_PIPE_SHIFT;
Rob Clarke2c719b2014-12-15 13:56:32 -05001314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001317 }
1318}
1319
Jesse Barnes19332d72013-03-28 09:55:38 -07001320static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322{
Chris Wilson91c8a322016-07-05 10:40:23 +01001323 struct drm_device *dev = &dev_priv->drm;
Ville Syrjälä649636e2015-09-22 19:50:01 +03001324 int sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001325
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001326 if (INTEL_INFO(dev)->gen >= 9) {
Damien Lespiau3bdcfc02015-02-28 14:54:09 +00001327 for_each_sprite(dev_priv, pipe, sprite) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
Rob Clarke2c719b2014-12-15 13:56:32 -05001329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1332 }
Wayne Boyer666a4532015-12-09 12:29:35 -08001333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Damien Lespiau3bdcfc02015-02-28 14:54:09 +00001334 for_each_sprite(dev_priv, pipe, sprite) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001335 u32 val = I915_READ(SPCNTR(pipe, sprite));
Rob Clarke2c719b2014-12-15 13:56:32 -05001336 I915_STATE_WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001338 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001339 }
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001341 u32 val = I915_READ(SPRCTL(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001342 I915_STATE_WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001346 u32 val = I915_READ(DVSCNTR(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001347 I915_STATE_WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001350 }
1351}
1352
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001353static void assert_vblank_disabled(struct drm_crtc *crtc)
1354{
Rob Clarke2c719b2014-12-15 13:56:32 -05001355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001356 drm_crtc_vblank_put(crtc);
1357}
1358
Ander Conselvan de Oliveira7abd4b32016-03-08 17:46:15 +02001359void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001361{
Jesse Barnes92f25842011-01-04 15:09:34 -08001362 u32 val;
1363 bool enabled;
1364
Ville Syrjälä649636e2015-09-22 19:50:01 +03001365 val = I915_READ(PCH_TRANSCONF(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001366 enabled = !!(val & TRANS_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001367 I915_STATE_WARN(enabled,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001370}
1371
Keith Packard4e634382011-08-06 10:39:45 -07001372static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001374{
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001378 if (HAS_PCH_CPT(dev_priv)) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
Keith Packardf0575e92011-07-25 22:12:43 -07001380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381 return false;
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001382 } else if (IS_CHERRYVIEW(dev_priv)) {
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001385 } else {
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 return false;
1388 }
1389 return true;
1390}
1391
Keith Packard1519b992011-08-06 10:35:34 -07001392static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001395 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001396 return false;
1397
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001398 if (HAS_PCH_CPT(dev_priv)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001400 return false;
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001401 } else if (IS_CHERRYVIEW(dev_priv)) {
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001404 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001406 return false;
1407 }
1408 return true;
1409}
1410
1411static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1413{
1414 if ((val & LVDS_PORT_EN) == 0)
1415 return false;
1416
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001417 if (HAS_PCH_CPT(dev_priv)) {
Keith Packard1519b992011-08-06 10:35:34 -07001418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419 return false;
1420 } else {
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 return false;
1423 }
1424 return true;
1425}
1426
1427static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1429{
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1431 return false;
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001432 if (HAS_PCH_CPT(dev_priv)) {
Keith Packard1519b992011-08-06 10:35:34 -07001433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434 return false;
1435 } else {
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 return false;
1438 }
1439 return true;
1440}
1441
Jesse Barnes291906f2011-02-02 12:28:03 -08001442static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001443 enum pipe pipe, i915_reg_t reg,
1444 u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001445{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001446 u32 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001449 i915_mmio_reg_offset(reg), pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001450
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001452 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001453 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001454}
1455
1456static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001457 enum pipe pipe, i915_reg_t reg)
Jesse Barnes291906f2011-02-02 12:28:03 -08001458{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001459 u32 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001462 i915_mmio_reg_offset(reg), pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001463
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001465 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001466 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001467}
1468
1469static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471{
Jesse Barnes291906f2011-02-02 12:28:03 -08001472 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001473
Keith Packardf0575e92011-07-25 22:12:43 -07001474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001477
Ville Syrjälä649636e2015-09-22 19:50:01 +03001478 val = I915_READ(PCH_ADPA);
Rob Clarke2c719b2014-12-15 13:56:32 -05001479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001480 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001481 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001482
Ville Syrjälä649636e2015-09-22 19:50:01 +03001483 val = I915_READ(PCH_LVDS);
Rob Clarke2c719b2014-12-15 13:56:32 -05001484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001486 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001487
Paulo Zanonie2debe92013-02-18 19:00:27 -03001488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001491}
1492
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001493static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1495{
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1498
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1501 udelay(150);
1502
Chris Wilson2c30b432016-06-30 15:32:54 +01001503 if (intel_wait_for_register(dev_priv,
1504 DPLL(pipe),
1505 DPLL_LOCK_VLV,
1506 DPLL_LOCK_VLV,
1507 1))
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509}
1510
Ville Syrjäläd288f652014-10-28 13:20:22 +02001511static void vlv_enable_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001512 const struct intel_crtc_state *pipe_config)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001513{
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä8bd3f302016-03-15 16:39:57 +02001515 enum pipe pipe = crtc->pipe;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001516
Ville Syrjälä8bd3f302016-03-15 16:39:57 +02001517 assert_pipe_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001518
Daniel Vetter87442f72013-06-06 00:52:17 +02001519 /* PLL is protected by panel, make sure we can write it */
Ville Syrjälä7d1a83c2016-03-15 16:39:58 +02001520 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001521
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
Daniel Vetter426115c2013-07-11 22:13:42 +02001524
Ville Syrjälä8bd3f302016-03-15 16:39:57 +02001525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001527}
1528
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001529
1530static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001532{
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä8bd3f302016-03-15 16:39:57 +02001534 enum pipe pipe = crtc->pipe;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001536 u32 tmp;
1537
Ville Syrjäläa5805162015-05-26 20:42:30 +03001538 mutex_lock(&dev_priv->sb_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001539
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
Ville Syrjälä54433e92015-05-26 20:42:31 +03001545 mutex_unlock(&dev_priv->sb_lock);
1546
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001547 /*
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549 */
1550 udelay(1);
1551
1552 /* Enable PLL */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001554
1555 /* Check PLL is locked */
Chris Wilson6b188262016-06-30 15:32:55 +01001556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001559 DRM_ERROR("PLL %d failed to lock\n", pipe);
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03001560}
1561
1562static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1564{
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1567
1568 assert_pipe_disabled(dev_priv, pipe);
1569
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1572
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001575
Ville Syrjäläc2317752016-03-15 16:39:56 +02001576 if (pipe != PIPE_A) {
1577 /*
1578 * WaPixelRepeatModeFixForC0:chv
1579 *
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1582 */
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588 /*
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1591 */
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593 } else {
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1596 }
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001597}
1598
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001599static int intel_num_dvo_pipes(struct drm_device *dev)
1600{
1601 struct intel_crtc *crtc;
1602 int count = 0;
1603
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03001604 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorst3538b9d2015-06-01 12:50:10 +02001605 count += crtc->base.state->active &&
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03001606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607 }
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001608
1609 return count;
1610}
1611
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001612static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001613{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001614 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001615 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001616 i915_reg_t reg = DPLL(crtc->pipe);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001617 u32 dpll = crtc->config->dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001618
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001619 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001620
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001621 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001624
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627 /*
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1632 */
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001637
Ville Syrjäläc2b63372015-10-07 22:08:25 +03001638 /*
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1642 */
1643 I915_WRITE(reg, 0);
1644
Ville Syrjälä8e7a65a2015-10-07 22:08:24 +03001645 I915_WRITE(reg, dpll);
1646
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001647 /* Wait for the clocks to stabilize. */
1648 POSTING_READ(reg);
1649 udelay(150);
1650
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001653 crtc->config->dpll_hw_state.dpll_md);
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001654 } else {
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1657 *
1658 * So write it again.
1659 */
1660 I915_WRITE(reg, dpll);
1661 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001662
1663 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001664 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001667 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001668 POSTING_READ(reg);
1669 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001670 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001671 POSTING_READ(reg);
1672 udelay(150); /* wait for warmup */
1673}
1674
1675/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001676 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1679 *
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 *
1682 * Note! This is for pre-ILK only.
1683 */
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001684static void i9xx_disable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001685{
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001686 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001687 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001688 enum pipe pipe = crtc->pipe;
1689
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1691 if (IS_I830(dev) &&
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03001692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
Maarten Lankhorst3538b9d2015-06-01 12:50:10 +02001693 !intel_num_dvo_pipes(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698 }
1699
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001703 return;
1704
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1707
Ville Syrjäläb8afb912015-06-29 15:25:48 +03001708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
Daniel Vetter50b44a42013-06-05 13:34:33 +02001709 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001710}
1711
Jesse Barnesf6071162013-10-01 10:41:38 -07001712static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713{
Ville Syrjäläb8afb912015-06-29 15:25:48 +03001714 u32 val;
Jesse Barnesf6071162013-10-01 10:41:38 -07001715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02001719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
Jesse Barnesf6071162013-10-01 10:41:38 -07001724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001726}
1727
1728static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001731 u32 val;
1732
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001735
Ville Syrjälä60bfe442015-06-29 15:25:49 +03001736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001738 if (pipe != PIPE_A)
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02001740
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001743
Ville Syrjäläa5805162015-05-26 20:42:30 +03001744 mutex_lock(&dev_priv->sb_lock);
Ville Syrjäläd7520482014-04-09 13:28:59 +03001745
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
Ville Syrjäläa5805162015-05-26 20:42:30 +03001751 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001752}
1753
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001754void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001757{
1758 u32 port_mask;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001759 i915_reg_t dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001760
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001761 switch (dport->port) {
1762 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001763 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001764 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001765 break;
1766 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001767 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001768 dpll_reg = DPLL(0);
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001769 expected_mask <<= 4;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001770 break;
1771 case PORT_D:
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001774 break;
1775 default:
1776 BUG();
1777 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001778
Chris Wilson370004d2016-06-30 15:32:56 +01001779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1781 1000))
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001784}
1785
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001786static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001788{
Chris Wilson91c8a322016-07-05 10:40:23 +01001789 struct drm_device *dev = &dev_priv->drm;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001792 i915_reg_t reg;
1793 uint32_t val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001794
Jesse Barnes040484a2011-01-03 12:14:26 -08001795 /* Make sure PCH DPLL is enabled */
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02001796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
Jesse Barnes040484a2011-01-03 12:14:26 -08001797
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1801
Daniel Vetter23670b322012-11-01 09:15:30 +01001802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001809 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001810
Daniel Vetterab9412b2013-05-03 11:49:46 +02001811 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001812 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001813 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001814
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001815 if (HAS_PCH_IBX(dev_priv)) {
Jesse Barnese9bcff52011-06-24 12:19:20 -07001816 /*
Ville Syrjäläc5de7c62015-05-05 17:06:22 +03001817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
Jesse Barnese9bcff52011-06-24 12:19:20 -07001820 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001821 val &= ~PIPECONF_BPC_MASK;
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03001822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
Ville Syrjäläc5de7c62015-05-05 17:06:22 +03001823 val |= PIPECONF_8BPC;
1824 else
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001826 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001827
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001830 if (HAS_PCH_IBX(dev_priv) &&
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03001831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001832 val |= TRANS_LEGACY_INTERLACED_ILK;
1833 else
1834 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001835 else
1836 val |= TRANS_PROGRESSIVE;
1837
Jesse Barnes040484a2011-01-03 12:14:26 -08001838 I915_WRITE(reg, val | TRANS_ENABLE);
Chris Wilson650fbd82016-06-30 15:32:57 +01001839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001843}
1844
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001845static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001846 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001847{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001848 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001849
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001850 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001852 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001853
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001854 /* Workaround: set timing override bit. */
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03001855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
Daniel Vetter23670b322012-11-01 09:15:30 +01001856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03001857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001858
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001859 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001861
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001864 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001865 else
1866 val |= TRANS_PROGRESSIVE;
1867
Daniel Vetterab9412b2013-05-03 11:49:46 +02001868 I915_WRITE(LPT_TRANSCONF, val);
Chris Wilsond9f96242016-06-30 15:32:58 +01001869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF,
1871 TRANS_STATE_ENABLE,
1872 TRANS_STATE_ENABLE,
1873 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001874 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001875}
1876
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001877static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001879{
Chris Wilson91c8a322016-07-05 10:40:23 +01001880 struct drm_device *dev = &dev_priv->drm;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001881 i915_reg_t reg;
1882 uint32_t val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001883
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1887
Jesse Barnes291906f2011-02-02 12:28:03 -08001888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1890
Daniel Vetterab9412b2013-05-03 11:49:46 +02001891 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
Chris Wilsona7d04662016-06-30 15:32:59 +01001896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1898 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001900
Ville Syrjäläc4656132015-10-29 21:25:56 +02001901 if (HAS_PCH_CPT(dev)) {
Daniel Vetter23670b322012-11-01 09:15:30 +01001902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1907 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001908}
1909
Maarten Lankhorstb7076542016-08-23 16:18:08 +02001910void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001911{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001912 u32 val;
1913
Daniel Vetterab9412b2013-05-03 11:49:46 +02001914 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001915 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001916 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001917 /* wait for PCH transcoder off, transcoder state */
Chris Wilsondfdb4742016-06-30 15:33:00 +01001918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001921 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001922
1923 /* Workaround: clear timing override bit. */
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03001924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
Daniel Vetter23670b322012-11-01 09:15:30 +01001925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03001926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001927}
1928
1929/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001930 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001931 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001932 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001933 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001935 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001936static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001937{
Paulo Zanoni03722642014-01-17 13:51:09 -02001938 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001939 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni03722642014-01-17 13:51:09 -02001940 enum pipe pipe = crtc->pipe;
Ville Syrjälä1a70a7282015-10-29 21:25:50 +02001941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Daniel Vetter1a240d42012-11-29 22:18:51 +01001942 enum pipe pch_transcoder;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001943 i915_reg_t reg;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001944 u32 val;
1945
Ville Syrjälä9e2ee2d2015-06-24 21:59:35 +03001946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001948 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001949 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001950 assert_sprites_disabled(dev_priv, pipe);
1951
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001952 if (HAS_PCH_LPT(dev_priv))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001953 pch_transcoder = TRANSCODER_A;
1954 else
1955 pch_transcoder = pipe;
1956
Jesse Barnesb24e7172011-01-04 15:09:30 -08001957 /*
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 * need the check.
1961 */
Ville Syrjälä09fa8bb2016-08-05 20:41:34 +03001962 if (HAS_GMCH_DISPLAY(dev_priv)) {
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03001963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03001964 assert_dsi_pll_enabled(dev_priv);
1965 else
1966 assert_pll_enabled(dev_priv, pipe);
Ville Syrjälä09fa8bb2016-08-05 20:41:34 +03001967 } else {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001968 if (crtc->config->has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08001969 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001973 }
1974 /* FIXME: assert CPU port conditions for SNB+ */
1975 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001976
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001977 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001978 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02001979 if (val & PIPECONF_ENABLE) {
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
Chris Wilson00d70b12011-03-17 07:18:29 +00001982 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02001983 }
Chris Wilson00d70b12011-03-17 07:18:29 +00001984
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02001986 POSTING_READ(reg);
Ville Syrjäläb7792d82015-12-14 18:23:43 +02001987
1988 /*
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1994 */
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001998}
1999
2000/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002001 * intel_disable_pipe - disable a pipe, asserting requirements
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002002 * @crtc: crtc whose pipes is to be disabled
Jesse Barnesb24e7172011-01-04 15:09:30 -08002003 *
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002007 *
2008 * Will wait until the pipe has shut down before returning.
2009 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002010static void intel_disable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002011{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002014 enum pipe pipe = crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002015 i915_reg_t reg;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002016 u32 val;
2017
Ville Syrjälä9e2ee2d2015-06-24 21:59:35 +03002018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
Jesse Barnesb24e7172011-01-04 15:09:30 -08002020 /*
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2023 */
2024 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002025 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002026 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002027
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002028 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002029 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002030 if ((val & PIPECONF_ENABLE) == 0)
2031 return;
2032
Ville Syrjälä67adc642014-08-15 01:21:57 +03002033 /*
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2036 */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002037 if (crtc->config->double_wide)
Ville Syrjälä67adc642014-08-15 01:21:57 +03002038 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040 /* Don't disable pipe or pipe PLLs if needed */
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Ville Syrjälä67adc642014-08-15 01:21:57 +03002043 val &= ~PIPECONF_ENABLE;
2044
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002048}
2049
Ville Syrjälä832be822016-01-12 21:08:33 +02002050static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051{
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2053}
2054
Ville Syrjälä27ba3912016-02-15 22:54:40 +02002055static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
Ville Syrjälä7b49f942016-01-12 21:08:32 +02002057{
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2060 return cpp;
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2063 return 128;
2064 else
2065 return 512;
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068 return 128;
2069 else
2070 return 512;
2071 case I915_FORMAT_MOD_Yf_TILED:
2072 switch (cpp) {
2073 case 1:
2074 return 64;
2075 case 2:
2076 case 4:
2077 return 128;
2078 case 8:
2079 case 16:
2080 return 256;
2081 default:
2082 MISSING_CASE(cpp);
2083 return cpp;
2084 }
2085 break;
2086 default:
2087 MISSING_CASE(fb_modifier);
2088 return cpp;
2089 }
2090}
2091
Ville Syrjälä832be822016-01-12 21:08:33 +02002092unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002094{
Ville Syrjälä832be822016-01-12 21:08:33 +02002095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096 return 1;
2097 else
2098 return intel_tile_size(dev_priv) /
Ville Syrjälä27ba3912016-02-15 22:54:40 +02002099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002100}
2101
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002102/* Return the tile dimensions in pixel units */
2103static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2107 unsigned int cpp)
2108{
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114}
2115
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002116unsigned int
2117intel_fb_align_height(struct drm_device *dev, unsigned int height,
Ville Syrjälä832be822016-01-12 21:08:33 +02002118 uint32_t pixel_format, uint64_t fb_modifier)
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002119{
Ville Syrjälä832be822016-01-12 21:08:33 +02002120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123 return ALIGN(height, tile_height);
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002124}
2125
Ville Syrjälä1663b9d2016-02-15 22:54:45 +02002126unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127{
2128 unsigned int size = 0;
2129 int i;
2130
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134 return size;
2135}
2136
Daniel Vetter75c82a52015-10-14 16:51:04 +02002137static void
Ville Syrjälä3465c582016-02-15 22:54:43 +02002138intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002141{
Ville Syrjälä2d7a2152016-02-15 22:54:47 +02002142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145 } else {
2146 *view = i915_ggtt_view_normal;
2147 }
2148}
2149
Ville Syrjälä603525d2016-01-12 21:08:37 +02002150static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002151{
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2153 return 256 * 1024;
Ville Syrjälä985b8bb2015-06-11 16:31:15 +03002154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
Wayne Boyer666a4532015-12-09 12:29:35 -08002155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002156 return 128 * 1024;
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2158 return 4 * 1024;
2159 else
Ville Syrjälä44c59052015-06-11 16:31:16 +03002160 return 0;
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002161}
2162
Ville Syrjälä603525d2016-01-12 21:08:37 +02002163static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2165{
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2171 return 256 * 1024;
2172 return 0;
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2176 default:
2177 MISSING_CASE(fb_modifier);
2178 return 0;
2179 }
2180}
2181
Chris Wilson058d88c2016-08-15 10:49:06 +01002182struct i915_vma *
2183intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002184{
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002185 struct drm_device *dev = fb->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01002186 struct drm_i915_private *dev_priv = to_i915(dev);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002188 struct i915_ggtt_view view;
Chris Wilson058d88c2016-08-15 10:49:06 +01002189 struct i915_vma *vma;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002190 u32 alignment;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002191
Matt Roperebcdd392014-07-09 16:22:11 -07002192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
Ville Syrjälä603525d2016-01-12 21:08:37 +02002194 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002195
Ville Syrjälä3465c582016-02-15 22:54:43 +02002196 intel_fill_fb_ggtt_view(&view, fb, rotation);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002197
Chris Wilson693db182013-03-05 14:52:39 +00002198 /* Note that the w/a also requires 64 PTE of padding following the
2199 * bo. We currently fill all unused PTE with the shadow page and so
2200 * we should always have valid PTE following the scanout preventing
2201 * the VT-d warning.
2202 */
Chris Wilson48f112f2016-06-24 14:07:14 +01002203 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
Chris Wilson693db182013-03-05 14:52:39 +00002204 alignment = 256 * 1024;
2205
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002206 /*
2207 * Global gtt pte registers are special registers which actually forward
2208 * writes to a chunk of system memory. Which means that there is no risk
2209 * that the register values disappear as soon as we call
2210 * intel_runtime_pm_put(), so it is correct to wrap only the
2211 * pin/unpin/fence and not more.
2212 */
2213 intel_runtime_pm_get(dev_priv);
2214
Chris Wilson058d88c2016-08-15 10:49:06 +01002215 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
Chris Wilson49ef5292016-08-18 17:17:00 +01002216 if (IS_ERR(vma))
2217 goto err;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002218
Chris Wilson05a20d02016-08-18 17:16:55 +01002219 if (i915_vma_is_map_and_fenceable(vma)) {
Chris Wilson49ef5292016-08-18 17:17:00 +01002220 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221 * fence, whereas 965+ only requires a fence if using
2222 * framebuffer compression. For simplicity, we always, when
2223 * possible, install a fence as the cost is not that onerous.
2224 *
2225 * If we fail to fence the tiled scanout, then either the
2226 * modeset will reject the change (which is highly unlikely as
2227 * the affected systems, all but one, do not have unmappable
2228 * space) or we will not be able to enable full powersaving
2229 * techniques (also likely not to apply due to various limits
2230 * FBC and the like impose on the size of the buffer, which
2231 * presumably we violated anyway with this unmappable buffer).
2232 * Anyway, it is presumably better to stumble onwards with
2233 * something and try to run the system in a "less than optimal"
2234 * mode that matches the user configuration.
2235 */
2236 if (i915_vma_get_fence(vma) == 0)
2237 i915_vma_pin_fence(vma);
Vivek Kasireddy98072162015-10-29 18:54:38 -07002238 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002239
Chris Wilson49ef5292016-08-18 17:17:00 +01002240err:
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002241 intel_runtime_pm_put(dev_priv);
Chris Wilson058d88c2016-08-15 10:49:06 +01002242 return vma;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002243}
2244
Chris Wilsonfb4b8ce2016-04-28 09:56:35 +01002245void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
Chris Wilson1690e1e2011-12-14 13:57:08 +01002246{
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002248 struct i915_ggtt_view view;
Chris Wilson058d88c2016-08-15 10:49:06 +01002249 struct i915_vma *vma;
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002250
Matt Roperebcdd392014-07-09 16:22:11 -07002251 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
Ville Syrjälä3465c582016-02-15 22:54:43 +02002253 intel_fill_fb_ggtt_view(&view, fb, rotation);
Chris Wilson05a20d02016-08-18 17:16:55 +01002254 vma = i915_gem_object_to_ggtt(obj, &view);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002255
Chris Wilson49ef5292016-08-18 17:17:00 +01002256 i915_vma_unpin_fence(vma);
Chris Wilson058d88c2016-08-15 10:49:06 +01002257 i915_gem_object_unpin_from_display_plane(vma);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002258}
Chris Wilsonbc752862013-02-21 20:04:31 +00002259
Ville Syrjäläef78ec92015-10-13 22:48:39 +03002260static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation)
2262{
2263 if (intel_rotation_90_or_270(rotation))
2264 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265 else
2266 return fb->pitches[plane];
Chris Wilson1690e1e2011-12-14 13:57:08 +01002267}
2268
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002269/*
Ville Syrjälä6687c902015-09-15 13:16:41 +03002270 * Convert the x/y offsets into a linear offset.
2271 * Only valid with 0/180 degree rotation, which is fine since linear
2272 * offset is only used with linear buffers on pre-hsw and tiled buffers
2273 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274 */
2275u32 intel_fb_xy_to_linear(int x, int y,
Ville Syrjälä29490562016-01-20 18:02:50 +02002276 const struct intel_plane_state *state,
2277 int plane)
Ville Syrjälä6687c902015-09-15 13:16:41 +03002278{
Ville Syrjälä29490562016-01-20 18:02:50 +02002279 const struct drm_framebuffer *fb = state->base.fb;
Ville Syrjälä6687c902015-09-15 13:16:41 +03002280 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281 unsigned int pitch = fb->pitches[plane];
2282
2283 return y * pitch + x * cpp;
2284}
2285
2286/*
2287 * Add the x/y offsets derived from fb->offsets[] to the user
2288 * specified plane src x/y offsets. The resulting x/y offsets
2289 * specify the start of scanout from the beginning of the gtt mapping.
2290 */
2291void intel_add_fb_offsets(int *x, int *y,
Ville Syrjälä29490562016-01-20 18:02:50 +02002292 const struct intel_plane_state *state,
2293 int plane)
Ville Syrjälä6687c902015-09-15 13:16:41 +03002294
2295{
Ville Syrjälä29490562016-01-20 18:02:50 +02002296 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297 unsigned int rotation = state->base.rotation;
Ville Syrjälä6687c902015-09-15 13:16:41 +03002298
2299 if (intel_rotation_90_or_270(rotation)) {
2300 *x += intel_fb->rotated[plane].x;
2301 *y += intel_fb->rotated[plane].y;
2302 } else {
2303 *x += intel_fb->normal[plane].x;
2304 *y += intel_fb->normal[plane].y;
2305 }
2306}
2307
2308/*
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002309 * Input tile dimensions and pitch must already be
2310 * rotated to match x and y, and in pixel units.
2311 */
Ville Syrjälä66a2d922016-02-05 18:44:05 +02002312static u32 _intel_adjust_tile_offset(int *x, int *y,
2313 unsigned int tile_width,
2314 unsigned int tile_height,
2315 unsigned int tile_size,
2316 unsigned int pitch_tiles,
2317 u32 old_offset,
2318 u32 new_offset)
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002319{
Ville Syrjäläb9b24032016-02-08 18:28:00 +02002320 unsigned int pitch_pixels = pitch_tiles * tile_width;
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002321 unsigned int tiles;
2322
2323 WARN_ON(old_offset & (tile_size - 1));
2324 WARN_ON(new_offset & (tile_size - 1));
2325 WARN_ON(new_offset > old_offset);
2326
2327 tiles = (old_offset - new_offset) / tile_size;
2328
2329 *y += tiles / pitch_tiles * tile_height;
2330 *x += tiles % pitch_tiles * tile_width;
2331
Ville Syrjäläb9b24032016-02-08 18:28:00 +02002332 /* minimize x in case it got needlessly big */
2333 *y += *x / pitch_pixels * tile_height;
2334 *x %= pitch_pixels;
2335
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002336 return new_offset;
2337}
2338
2339/*
Ville Syrjälä66a2d922016-02-05 18:44:05 +02002340 * Adjust the tile offset by moving the difference into
2341 * the x/y offsets.
2342 */
2343static u32 intel_adjust_tile_offset(int *x, int *y,
2344 const struct intel_plane_state *state, int plane,
2345 u32 old_offset, u32 new_offset)
2346{
2347 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348 const struct drm_framebuffer *fb = state->base.fb;
2349 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350 unsigned int rotation = state->base.rotation;
2351 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353 WARN_ON(new_offset > old_offset);
2354
2355 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361 fb->modifier[plane], cpp);
2362
2363 if (intel_rotation_90_or_270(rotation)) {
2364 pitch_tiles = pitch / tile_height;
2365 swap(tile_width, tile_height);
2366 } else {
2367 pitch_tiles = pitch / (tile_width * cpp);
2368 }
2369
2370 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371 tile_size, pitch_tiles,
2372 old_offset, new_offset);
2373 } else {
2374 old_offset += *y * pitch + *x * cpp;
2375
2376 *y = (old_offset - new_offset) / pitch;
2377 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378 }
2379
Chris Wilsonbc752862013-02-21 20:04:31 +00002380 return new_offset;
2381}
2382
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002383/*
2384 * Computes the linear offset to the base tile and adjusts
2385 * x, y. bytes per pixel is assumed to be a power-of-two.
2386 *
2387 * In the 90/270 rotated case, x and y are assumed
2388 * to be already rotated to match the rotated GTT view, and
2389 * pitch is the tile_height aligned framebuffer height.
Ville Syrjälä6687c902015-09-15 13:16:41 +03002390 *
2391 * This function is used when computing the derived information
2392 * under intel_framebuffer, so using any of that information
2393 * here is not allowed. Anything under drm_framebuffer can be
2394 * used. This is why the user has to pass in the pitch since it
2395 * is specified in the rotated orientation.
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002396 */
Ville Syrjälä6687c902015-09-15 13:16:41 +03002397static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398 int *x, int *y,
2399 const struct drm_framebuffer *fb, int plane,
2400 unsigned int pitch,
2401 unsigned int rotation,
2402 u32 alignment)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002403{
Ville Syrjälä4f2d9932016-02-15 22:54:44 +02002404 uint64_t fb_modifier = fb->modifier[plane];
2405 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
Ville Syrjälä6687c902015-09-15 13:16:41 +03002406 u32 offset, offset_aligned;
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002407
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002408 if (alignment)
2409 alignment--;
2410
Ville Syrjäläb5c65332016-01-12 21:08:31 +02002411 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002412 unsigned int tile_size, tile_width, tile_height;
2413 unsigned int tile_rows, tiles, pitch_tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002414
Ville Syrjäläd8433102016-01-12 21:08:35 +02002415 tile_size = intel_tile_size(dev_priv);
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002416 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417 fb_modifier, cpp);
2418
2419 if (intel_rotation_90_or_270(rotation)) {
2420 pitch_tiles = pitch / tile_height;
2421 swap(tile_width, tile_height);
2422 } else {
2423 pitch_tiles = pitch / (tile_width * cpp);
2424 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002425
Ville Syrjäläd8433102016-01-12 21:08:35 +02002426 tile_rows = *y / tile_height;
2427 *y %= tile_height;
Chris Wilsonbc752862013-02-21 20:04:31 +00002428
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02002429 tiles = *x / tile_width;
2430 *x %= tile_width;
Ville Syrjäläd8433102016-01-12 21:08:35 +02002431
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002432 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433 offset_aligned = offset & ~alignment;
Chris Wilsonbc752862013-02-21 20:04:31 +00002434
Ville Syrjälä66a2d922016-02-05 18:44:05 +02002435 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436 tile_size, pitch_tiles,
2437 offset, offset_aligned);
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002438 } else {
Chris Wilsonbc752862013-02-21 20:04:31 +00002439 offset = *y * pitch + *x * cpp;
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002440 offset_aligned = offset & ~alignment;
2441
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002442 *y = (offset & alignment) / pitch;
2443 *x = ((offset & alignment) - *y * pitch) / cpp;
Chris Wilsonbc752862013-02-21 20:04:31 +00002444 }
Ville Syrjälä29cf9492016-02-15 22:54:42 +02002445
2446 return offset_aligned;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002447}
2448
Ville Syrjälä6687c902015-09-15 13:16:41 +03002449u32 intel_compute_tile_offset(int *x, int *y,
Ville Syrjälä29490562016-01-20 18:02:50 +02002450 const struct intel_plane_state *state,
2451 int plane)
Ville Syrjälä6687c902015-09-15 13:16:41 +03002452{
Ville Syrjälä29490562016-01-20 18:02:50 +02002453 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454 const struct drm_framebuffer *fb = state->base.fb;
2455 unsigned int rotation = state->base.rotation;
Ville Syrjäläef78ec92015-10-13 22:48:39 +03002456 int pitch = intel_fb_pitch(fb, plane, rotation);
Ville Syrjälä8d970652016-01-28 16:30:28 +02002457 u32 alignment;
2458
2459 /* AUX_DIST needs only 4K alignment */
2460 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461 alignment = 4096;
2462 else
2463 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
Ville Syrjälä6687c902015-09-15 13:16:41 +03002464
2465 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466 rotation, alignment);
2467}
2468
2469/* Convert the fb->offset[] linear offset into x/y offsets */
2470static void intel_fb_offset_to_xy(int *x, int *y,
2471 const struct drm_framebuffer *fb, int plane)
2472{
2473 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474 unsigned int pitch = fb->pitches[plane];
2475 u32 linear_offset = fb->offsets[plane];
2476
2477 *y = linear_offset / pitch;
2478 *x = linear_offset % pitch / cpp;
2479}
2480
Ville Syrjälä72618eb2016-02-04 20:38:20 +02002481static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482{
2483 switch (fb_modifier) {
2484 case I915_FORMAT_MOD_X_TILED:
2485 return I915_TILING_X;
2486 case I915_FORMAT_MOD_Y_TILED:
2487 return I915_TILING_Y;
2488 default:
2489 return I915_TILING_NONE;
2490 }
2491}
2492
Ville Syrjälä6687c902015-09-15 13:16:41 +03002493static int
2494intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495 struct drm_framebuffer *fb)
2496{
2497 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499 u32 gtt_offset_rotated = 0;
2500 unsigned int max_size = 0;
2501 uint32_t format = fb->pixel_format;
2502 int i, num_planes = drm_format_num_planes(format);
2503 unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505 for (i = 0; i < num_planes; i++) {
2506 unsigned int width, height;
2507 unsigned int cpp, size;
2508 u32 offset;
2509 int x, y;
2510
2511 cpp = drm_format_plane_cpp(format, i);
2512 width = drm_format_plane_width(fb->width, format, i);
2513 height = drm_format_plane_height(fb->height, format, i);
2514
2515 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517 /*
Ville Syrjälä60d5f2a2016-01-22 18:41:24 +02002518 * The fence (if used) is aligned to the start of the object
2519 * so having the framebuffer wrap around across the edge of the
2520 * fenced region doesn't really work. We have no API to configure
2521 * the fence start offset within the object (nor could we probably
2522 * on gen2/3). So it's just easier if we just require that the
2523 * fb layout agrees with the fence layout. We already check that the
2524 * fb stride matches the fence stride elsewhere.
2525 */
2526 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527 (x + width) * cpp > fb->pitches[i]) {
2528 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529 i, fb->offsets[i]);
2530 return -EINVAL;
2531 }
2532
2533 /*
Ville Syrjälä6687c902015-09-15 13:16:41 +03002534 * First pixel of the framebuffer from
2535 * the start of the normal gtt mapping.
2536 */
2537 intel_fb->normal[i].x = x;
2538 intel_fb->normal[i].y = y;
2539
2540 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541 fb, 0, fb->pitches[i],
Daniel Vettercc926382016-08-15 10:41:47 +02002542 DRM_ROTATE_0, tile_size);
Ville Syrjälä6687c902015-09-15 13:16:41 +03002543 offset /= tile_size;
2544
2545 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546 unsigned int tile_width, tile_height;
2547 unsigned int pitch_tiles;
2548 struct drm_rect r;
2549
2550 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551 fb->modifier[i], cpp);
2552
2553 rot_info->plane[i].offset = offset;
2554 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558 intel_fb->rotated[i].pitch =
2559 rot_info->plane[i].height * tile_height;
2560
2561 /* how many tiles does this plane need */
2562 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563 /*
2564 * If the plane isn't horizontally tile aligned,
2565 * we need one more tile.
2566 */
2567 if (x != 0)
2568 size++;
2569
2570 /* rotate the x/y offsets to match the GTT view */
2571 r.x1 = x;
2572 r.y1 = y;
2573 r.x2 = x + width;
2574 r.y2 = y + height;
2575 drm_rect_rotate(&r,
2576 rot_info->plane[i].width * tile_width,
2577 rot_info->plane[i].height * tile_height,
Daniel Vettercc926382016-08-15 10:41:47 +02002578 DRM_ROTATE_270);
Ville Syrjälä6687c902015-09-15 13:16:41 +03002579 x = r.x1;
2580 y = r.y1;
2581
2582 /* rotate the tile dimensions to match the GTT view */
2583 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584 swap(tile_width, tile_height);
2585
2586 /*
2587 * We only keep the x/y offsets, so push all of the
2588 * gtt offset into the x/y offsets.
2589 */
Ville Syrjälä66a2d922016-02-05 18:44:05 +02002590 _intel_adjust_tile_offset(&x, &y, tile_size,
2591 tile_width, tile_height, pitch_tiles,
2592 gtt_offset_rotated * tile_size, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +03002593
2594 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596 /*
2597 * First pixel of the framebuffer from
2598 * the start of the rotated gtt mapping.
2599 */
2600 intel_fb->rotated[i].x = x;
2601 intel_fb->rotated[i].y = y;
2602 } else {
2603 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604 x * cpp, tile_size);
2605 }
2606
2607 /* how many tiles in total needed in the bo */
2608 max_size = max(max_size, offset + size);
2609 }
2610
2611 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614 return -EINVAL;
2615 }
2616
2617 return 0;
2618}
2619
Damien Lespiaub35d63f2015-01-20 12:51:50 +00002620static int i9xx_format_to_fourcc(int format)
Jesse Barnes46f297f2014-03-07 08:57:48 -08002621{
2622 switch (format) {
2623 case DISPPLANE_8BPP:
2624 return DRM_FORMAT_C8;
2625 case DISPPLANE_BGRX555:
2626 return DRM_FORMAT_XRGB1555;
2627 case DISPPLANE_BGRX565:
2628 return DRM_FORMAT_RGB565;
2629 default:
2630 case DISPPLANE_BGRX888:
2631 return DRM_FORMAT_XRGB8888;
2632 case DISPPLANE_RGBX888:
2633 return DRM_FORMAT_XBGR8888;
2634 case DISPPLANE_BGRX101010:
2635 return DRM_FORMAT_XRGB2101010;
2636 case DISPPLANE_RGBX101010:
2637 return DRM_FORMAT_XBGR2101010;
2638 }
2639}
2640
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00002641static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642{
2643 switch (format) {
2644 case PLANE_CTL_FORMAT_RGB_565:
2645 return DRM_FORMAT_RGB565;
2646 default:
2647 case PLANE_CTL_FORMAT_XRGB_8888:
2648 if (rgb_order) {
2649 if (alpha)
2650 return DRM_FORMAT_ABGR8888;
2651 else
2652 return DRM_FORMAT_XBGR8888;
2653 } else {
2654 if (alpha)
2655 return DRM_FORMAT_ARGB8888;
2656 else
2657 return DRM_FORMAT_XRGB8888;
2658 }
2659 case PLANE_CTL_FORMAT_XRGB_2101010:
2660 if (rgb_order)
2661 return DRM_FORMAT_XBGR2101010;
2662 else
2663 return DRM_FORMAT_XRGB2101010;
2664 }
2665}
2666
Damien Lespiau5724dbd2015-01-20 12:51:52 +00002667static bool
Daniel Vetterf6936e22015-03-26 12:17:05 +01002668intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669 struct intel_initial_plane_config *plane_config)
Jesse Barnes46f297f2014-03-07 08:57:48 -08002670{
2671 struct drm_device *dev = crtc->base.dev;
Paulo Zanoni3badb492015-09-23 12:52:23 -03002672 struct drm_i915_private *dev_priv = to_i915(dev);
Joonas Lahtinen72e96d62016-03-30 16:57:10 +03002673 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002674 struct drm_i915_gem_object *obj = NULL;
2675 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Damien Lespiau2d140302015-02-05 17:22:18 +00002676 struct drm_framebuffer *fb = &plane_config->fb->base;
Daniel Vetterf37b5c22015-02-10 23:12:27 +01002677 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679 PAGE_SIZE);
2680
2681 size_aligned -= base_aligned;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002682
Chris Wilsonff2652e2014-03-10 08:07:02 +00002683 if (plane_config->size == 0)
2684 return false;
2685
Paulo Zanoni3badb492015-09-23 12:52:23 -03002686 /* If the FB is too big, just don't use it since fbdev is not very
2687 * important and we should probably use that space with FBC or other
2688 * features. */
Joonas Lahtinen72e96d62016-03-30 16:57:10 +03002689 if (size_aligned * 2 > ggtt->stolen_usable_size)
Paulo Zanoni3badb492015-09-23 12:52:23 -03002690 return false;
2691
Tvrtko Ursulin12c83d92016-02-11 10:27:29 +00002692 mutex_lock(&dev->struct_mutex);
2693
Daniel Vetterf37b5c22015-02-10 23:12:27 +01002694 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695 base_aligned,
2696 base_aligned,
2697 size_aligned);
Tvrtko Ursulin12c83d92016-02-11 10:27:29 +00002698 if (!obj) {
2699 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002700 return false;
Tvrtko Ursulin12c83d92016-02-11 10:27:29 +00002701 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002702
Chris Wilson3e510a82016-08-05 10:14:23 +01002703 if (plane_config->tiling == I915_TILING_X)
2704 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002705
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002706 mode_cmd.pixel_format = fb->pixel_format;
2707 mode_cmd.width = fb->width;
2708 mode_cmd.height = fb->height;
2709 mode_cmd.pitches[0] = fb->pitches[0];
Daniel Vetter18c52472015-02-10 17:16:09 +00002710 mode_cmd.modifier[0] = fb->modifier[0];
2711 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002712
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002713 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002714 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002715 DRM_DEBUG_KMS("intel fb init failed\n");
2716 goto out_unref_obj;
2717 }
Tvrtko Ursulin12c83d92016-02-11 10:27:29 +00002718
Jesse Barnes46f297f2014-03-07 08:57:48 -08002719 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002720
Daniel Vetterf6936e22015-03-26 12:17:05 +01002721 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002722 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002723
2724out_unref_obj:
Chris Wilsonf8c417c2016-07-20 13:31:53 +01002725 i915_gem_object_put(obj);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002726 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002727 return false;
2728}
2729
Daniel Vetter5a21b662016-05-24 17:13:53 +02002730/* Update plane->state->fb to match plane->fb after driver-internal updates */
2731static void
2732update_state_fb(struct drm_plane *plane)
2733{
2734 if (plane->fb == plane->state->fb)
2735 return;
2736
2737 if (plane->state->fb)
2738 drm_framebuffer_unreference(plane->state->fb);
2739 plane->state->fb = plane->fb;
2740 if (plane->state->fb)
2741 drm_framebuffer_reference(plane->state->fb);
2742}
2743
Damien Lespiau5724dbd2015-01-20 12:51:52 +00002744static void
Daniel Vetterf6936e22015-03-26 12:17:05 +01002745intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746 struct intel_initial_plane_config *plane_config)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002747{
2748 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01002749 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002750 struct drm_crtc *c;
2751 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002752 struct drm_i915_gem_object *obj;
Daniel Vetter88595ac2015-03-26 12:42:24 +01002753 struct drm_plane *primary = intel_crtc->base.primary;
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002754 struct drm_plane_state *plane_state = primary->state;
Matt Roper200757f2015-12-03 11:37:36 -08002755 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756 struct intel_plane *intel_plane = to_intel_plane(primary);
Matt Roper0a8d8a82015-12-03 11:37:38 -08002757 struct intel_plane_state *intel_state =
2758 to_intel_plane_state(plane_state);
Daniel Vetter88595ac2015-03-26 12:42:24 +01002759 struct drm_framebuffer *fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002760
Damien Lespiau2d140302015-02-05 17:22:18 +00002761 if (!plane_config->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002762 return;
2763
Daniel Vetterf6936e22015-03-26 12:17:05 +01002764 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
Daniel Vetter88595ac2015-03-26 12:42:24 +01002765 fb = &plane_config->fb->base;
2766 goto valid_fb;
Damien Lespiauf55548b2015-02-05 18:30:20 +00002767 }
Jesse Barnes484b41d2014-03-07 08:57:55 -08002768
Damien Lespiau2d140302015-02-05 17:22:18 +00002769 kfree(plane_config->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002770
2771 /*
2772 * Failed to alloc the obj, check to see if we should share
2773 * an fb with another CRTC instead
2774 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002775 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002776 i = to_intel_crtc(c);
2777
2778 if (c == &intel_crtc->base)
2779 continue;
2780
Matt Roper2ff8fde2014-07-08 07:50:07 -07002781 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002782 continue;
2783
Daniel Vetter88595ac2015-03-26 12:42:24 +01002784 fb = c->primary->fb;
2785 if (!fb)
Matt Roper2ff8fde2014-07-08 07:50:07 -07002786 continue;
2787
Daniel Vetter88595ac2015-03-26 12:42:24 +01002788 obj = intel_fb_obj(fb);
Chris Wilson058d88c2016-08-15 10:49:06 +01002789 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
Daniel Vetter88595ac2015-03-26 12:42:24 +01002790 drm_framebuffer_reference(fb);
2791 goto valid_fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002792 }
2793 }
Daniel Vetter88595ac2015-03-26 12:42:24 +01002794
Matt Roper200757f2015-12-03 11:37:36 -08002795 /*
2796 * We've failed to reconstruct the BIOS FB. Current display state
2797 * indicates that the primary plane is visible, but has a NULL FB,
2798 * which will lead to problems later if we don't fix it up. The
2799 * simplest solution is to just disable the primary plane now and
2800 * pretend the BIOS never had it enabled.
2801 */
Ville Syrjälä936e71e2016-07-26 19:06:59 +03002802 to_intel_plane_state(plane_state)->base.visible = false;
Matt Roper200757f2015-12-03 11:37:36 -08002803 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
Ville Syrjälä2622a082016-03-09 19:07:26 +02002804 intel_pre_disable_primary_noatomic(&intel_crtc->base);
Matt Roper200757f2015-12-03 11:37:36 -08002805 intel_plane->disable_plane(primary, &intel_crtc->base);
2806
Daniel Vetter88595ac2015-03-26 12:42:24 +01002807 return;
2808
2809valid_fb:
Ville Syrjäläf44e2652015-11-13 19:16:13 +02002810 plane_state->src_x = 0;
2811 plane_state->src_y = 0;
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002812 plane_state->src_w = fb->width << 16;
2813 plane_state->src_h = fb->height << 16;
2814
Ville Syrjäläf44e2652015-11-13 19:16:13 +02002815 plane_state->crtc_x = 0;
2816 plane_state->crtc_y = 0;
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002817 plane_state->crtc_w = fb->width;
2818 plane_state->crtc_h = fb->height;
2819
Ville Syrjälä936e71e2016-07-26 19:06:59 +03002820 intel_state->base.src.x1 = plane_state->src_x;
2821 intel_state->base.src.y1 = plane_state->src_y;
2822 intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823 intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824 intel_state->base.dst.x1 = plane_state->crtc_x;
2825 intel_state->base.dst.y1 = plane_state->crtc_y;
2826 intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827 intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
Matt Roper0a8d8a82015-12-03 11:37:38 -08002828
Daniel Vetter88595ac2015-03-26 12:42:24 +01002829 obj = intel_fb_obj(fb);
Chris Wilson3e510a82016-08-05 10:14:23 +01002830 if (i915_gem_object_is_tiled(obj))
Daniel Vetter88595ac2015-03-26 12:42:24 +01002831 dev_priv->preserve_bios_swizzle = true;
2832
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002833 drm_framebuffer_reference(fb);
2834 primary->fb = primary->state->fb = fb;
Maarten Lankhorst36750f22015-06-01 12:49:54 +02002835 primary->crtc = primary->state->crtc = &intel_crtc->base;
Maarten Lankhorst36750f22015-06-01 12:49:54 +02002836 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
Chris Wilsonfaf5bf02016-08-04 16:32:37 +01002837 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838 &obj->frontbuffer_bits);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002839}
2840
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002841static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842 unsigned int rotation)
2843{
2844 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846 switch (fb->modifier[plane]) {
2847 case DRM_FORMAT_MOD_NONE:
2848 case I915_FORMAT_MOD_X_TILED:
2849 switch (cpp) {
2850 case 8:
2851 return 4096;
2852 case 4:
2853 case 2:
2854 case 1:
2855 return 8192;
2856 default:
2857 MISSING_CASE(cpp);
2858 break;
2859 }
2860 break;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 case I915_FORMAT_MOD_Yf_TILED:
2863 switch (cpp) {
2864 case 8:
2865 return 2048;
2866 case 4:
2867 return 4096;
2868 case 2:
2869 case 1:
2870 return 8192;
2871 default:
2872 MISSING_CASE(cpp);
2873 break;
2874 }
2875 break;
2876 default:
2877 MISSING_CASE(fb->modifier[plane]);
2878 }
2879
2880 return 2048;
2881}
2882
2883static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884{
2885 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886 const struct drm_framebuffer *fb = plane_state->base.fb;
2887 unsigned int rotation = plane_state->base.rotation;
Daniel Vettercc926382016-08-15 10:41:47 +02002888 int x = plane_state->base.src.x1 >> 16;
2889 int y = plane_state->base.src.y1 >> 16;
2890 int w = drm_rect_width(&plane_state->base.src) >> 16;
2891 int h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002892 int max_width = skl_max_plane_width(fb, 0, rotation);
2893 int max_height = 4096;
Ville Syrjälä8d970652016-01-28 16:30:28 +02002894 u32 alignment, offset, aux_offset = plane_state->aux.offset;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002895
2896 if (w > max_width || h > max_height) {
2897 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898 w, h, max_width, max_height);
2899 return -EINVAL;
2900 }
2901
2902 intel_add_fb_offsets(&x, &y, plane_state, 0);
2903 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907 /*
Ville Syrjälä8d970652016-01-28 16:30:28 +02002908 * AUX surface offset is specified as the distance from the
2909 * main surface offset, and it must be non-negative. Make
2910 * sure that is what we will get.
2911 */
2912 if (offset > aux_offset)
2913 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914 offset, aux_offset & ~(alignment - 1));
2915
2916 /*
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002917 * When using an X-tiled surface, the plane blows up
2918 * if the x offset + width exceed the stride.
2919 *
2920 * TODO: linear and Y-tiled seem fine, Yf untested,
2921 */
2922 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925 while ((x + w) * cpp > fb->pitches[0]) {
2926 if (offset == 0) {
2927 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928 return -EINVAL;
2929 }
2930
2931 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932 offset, offset - alignment);
2933 }
2934 }
2935
2936 plane_state->main.offset = offset;
2937 plane_state->main.x = x;
2938 plane_state->main.y = y;
2939
2940 return 0;
2941}
2942
Ville Syrjälä8d970652016-01-28 16:30:28 +02002943static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944{
2945 const struct drm_framebuffer *fb = plane_state->base.fb;
2946 unsigned int rotation = plane_state->base.rotation;
2947 int max_width = skl_max_plane_width(fb, 1, rotation);
2948 int max_height = 4096;
Daniel Vettercc926382016-08-15 10:41:47 +02002949 int x = plane_state->base.src.x1 >> 17;
2950 int y = plane_state->base.src.y1 >> 17;
2951 int w = drm_rect_width(&plane_state->base.src) >> 17;
2952 int h = drm_rect_height(&plane_state->base.src) >> 17;
Ville Syrjälä8d970652016-01-28 16:30:28 +02002953 u32 offset;
2954
2955 intel_add_fb_offsets(&x, &y, plane_state, 1);
2956 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958 /* FIXME not quite sure how/if these apply to the chroma plane */
2959 if (w > max_width || h > max_height) {
2960 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961 w, h, max_width, max_height);
2962 return -EINVAL;
2963 }
2964
2965 plane_state->aux.offset = offset;
2966 plane_state->aux.x = x;
2967 plane_state->aux.y = y;
2968
2969 return 0;
2970}
2971
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002972int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973{
2974 const struct drm_framebuffer *fb = plane_state->base.fb;
2975 unsigned int rotation = plane_state->base.rotation;
2976 int ret;
2977
2978 /* Rotate src coordinates to match rotated GTT view */
2979 if (intel_rotation_90_or_270(rotation))
Daniel Vettercc926382016-08-15 10:41:47 +02002980 drm_rect_rotate(&plane_state->base.src,
2981 fb->width, fb->height, DRM_ROTATE_270);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002982
Ville Syrjälä8d970652016-01-28 16:30:28 +02002983 /*
2984 * Handle the AUX surface first since
2985 * the main surface setup depends on it.
2986 */
2987 if (fb->pixel_format == DRM_FORMAT_NV12) {
2988 ret = skl_check_nv12_aux_surface(plane_state);
2989 if (ret)
2990 return ret;
2991 } else {
2992 plane_state->aux.offset = ~0xfff;
2993 plane_state->aux.x = 0;
2994 plane_state->aux.y = 0;
2995 }
2996
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02002997 ret = skl_check_main_surface(plane_state);
2998 if (ret)
2999 return ret;
3000
3001 return 0;
3002}
3003
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003004static void i9xx_update_primary_plane(struct drm_plane *primary,
3005 const struct intel_crtc_state *crtc_state,
3006 const struct intel_plane_state *plane_state)
Jesse Barnes81255562010-08-02 12:07:50 -07003007{
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003008 struct drm_device *dev = primary->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003009 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011 struct drm_framebuffer *fb = plane_state->base.fb;
3012 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes81255562010-08-02 12:07:50 -07003013 int plane = intel_crtc->plane;
Ville Syrjälä54ea9da2016-01-20 21:05:25 +02003014 u32 linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07003015 u32 dspcntr;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003016 i915_reg_t reg = DSPCNTR(plane);
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02003017 unsigned int rotation = plane_state->base.rotation;
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003018 int x = plane_state->base.src.x1 >> 16;
3019 int y = plane_state->base.src.y1 >> 16;
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03003020
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003021 dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03003023 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003024
3025 if (INTEL_INFO(dev)->gen < 4) {
3026 if (intel_crtc->pipe == PIPE_B)
3027 dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029 /* pipesrc and dspsize control the size that is scaled from,
3030 * which should always be the user's requested size.
3031 */
3032 I915_WRITE(DSPSIZE(plane),
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003033 ((crtc_state->pipe_src_h - 1) << 16) |
3034 (crtc_state->pipe_src_w - 1));
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003035 I915_WRITE(DSPPOS(plane), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03003036 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037 I915_WRITE(PRIMSIZE(plane),
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003038 ((crtc_state->pipe_src_h - 1) << 16) |
3039 (crtc_state->pipe_src_w - 1));
Ville Syrjäläc14b0482014-10-16 20:52:34 +03003040 I915_WRITE(PRIMPOS(plane), 0);
3041 I915_WRITE(PRIMCNSTALPHA(plane), 0);
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003042 }
3043
Ville Syrjälä57779d02012-10-31 17:50:14 +02003044 switch (fb->pixel_format) {
3045 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07003046 dspcntr |= DISPPLANE_8BPP;
3047 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02003048 case DRM_FORMAT_XRGB1555:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003049 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07003050 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02003051 case DRM_FORMAT_RGB565:
3052 dspcntr |= DISPPLANE_BGRX565;
3053 break;
3054 case DRM_FORMAT_XRGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003055 dspcntr |= DISPPLANE_BGRX888;
3056 break;
3057 case DRM_FORMAT_XBGR8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003058 dspcntr |= DISPPLANE_RGBX888;
3059 break;
3060 case DRM_FORMAT_XRGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003061 dspcntr |= DISPPLANE_BGRX101010;
3062 break;
3063 case DRM_FORMAT_XBGR2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003064 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07003065 break;
3066 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01003067 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07003068 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02003069
Ville Syrjälä72618eb2016-02-04 20:38:20 +02003070 if (INTEL_GEN(dev_priv) >= 4 &&
3071 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003072 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07003073
Ville Syrjäläde1aa622013-06-07 10:47:01 +03003074 if (IS_G4X(dev))
3075 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
Ville Syrjälä29490562016-01-20 18:02:50 +02003077 intel_add_fb_offsets(&x, &y, plane_state, 0);
Jesse Barnes81255562010-08-02 12:07:50 -07003078
Ville Syrjälä6687c902015-09-15 13:16:41 +03003079 if (INTEL_INFO(dev)->gen >= 4)
Daniel Vetterc2c75132012-07-05 12:17:30 +02003080 intel_crtc->dspaddr_offset =
Ville Syrjälä29490562016-01-20 18:02:50 +02003081 intel_compute_tile_offset(&x, &y, plane_state, 0);
Daniel Vettere506a0c2012-07-05 12:17:29 +02003082
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03003083 if (rotation == DRM_ROTATE_180) {
Sonika Jindal48404c12014-08-22 14:06:04 +05303084 dspcntr |= DISPPLANE_ROTATE_180;
3085
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003086 x += (crtc_state->pipe_src_w - 1);
3087 y += (crtc_state->pipe_src_h - 1);
Sonika Jindal48404c12014-08-22 14:06:04 +05303088 }
3089
Ville Syrjälä29490562016-01-20 18:02:50 +02003090 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +03003091
3092 if (INTEL_INFO(dev)->gen < 4)
3093 intel_crtc->dspaddr_offset = linear_offset;
3094
Paulo Zanoni2db33662015-09-14 15:20:03 -03003095 intel_crtc->adjusted_x = x;
3096 intel_crtc->adjusted_y = y;
3097
Sonika Jindal48404c12014-08-22 14:06:04 +05303098 I915_WRITE(reg, dspcntr);
3099
Ville Syrjälä01f2c772011-12-20 00:06:49 +02003100 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003101 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01003102 I915_WRITE(DSPSURF(plane),
Ville Syrjälä6687c902015-09-15 13:16:41 +03003103 intel_fb_gtt_offset(fb, rotation) +
3104 intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01003105 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02003106 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01003107 } else
Chris Wilson058d88c2016-08-15 10:49:06 +01003108 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01003109 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07003110}
3111
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003112static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113 struct drm_crtc *crtc)
Jesse Barnes17638cd2011-06-24 12:19:23 -07003114{
3115 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003116 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes17638cd2011-06-24 12:19:23 -07003117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003118 int plane = intel_crtc->plane;
3119
3120 I915_WRITE(DSPCNTR(plane), 0);
3121 if (INTEL_INFO(dev_priv)->gen >= 4)
3122 I915_WRITE(DSPSURF(plane), 0);
3123 else
3124 I915_WRITE(DSPADDR(plane), 0);
3125 POSTING_READ(DSPCNTR(plane));
3126}
3127
3128static void ironlake_update_primary_plane(struct drm_plane *primary,
3129 const struct intel_crtc_state *crtc_state,
3130 const struct intel_plane_state *plane_state)
3131{
3132 struct drm_device *dev = primary->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003133 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135 struct drm_framebuffer *fb = plane_state->base.fb;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003136 int plane = intel_crtc->plane;
Ville Syrjälä54ea9da2016-01-20 21:05:25 +02003137 u32 linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003138 u32 dspcntr;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003139 i915_reg_t reg = DSPCNTR(plane);
Ville Syrjälä8d0deca2016-02-15 22:54:41 +02003140 unsigned int rotation = plane_state->base.rotation;
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003141 int x = plane_state->base.src.x1 >> 16;
3142 int y = plane_state->base.src.y1 >> 16;
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03003143
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003144 dspcntr = DISPPLANE_GAMMA_ENABLE;
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03003145 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003146
3147 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
Ville Syrjälä57779d02012-10-31 17:50:14 +02003150 switch (fb->pixel_format) {
3151 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07003152 dspcntr |= DISPPLANE_8BPP;
3153 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02003154 case DRM_FORMAT_RGB565:
3155 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003156 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02003157 case DRM_FORMAT_XRGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003158 dspcntr |= DISPPLANE_BGRX888;
3159 break;
3160 case DRM_FORMAT_XBGR8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003161 dspcntr |= DISPPLANE_RGBX888;
3162 break;
3163 case DRM_FORMAT_XRGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003164 dspcntr |= DISPPLANE_BGRX101010;
3165 break;
3166 case DRM_FORMAT_XBGR2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02003167 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003168 break;
3169 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01003170 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07003171 }
3172
Ville Syrjälä72618eb2016-02-04 20:38:20 +02003173 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
Jesse Barnes17638cd2011-06-24 12:19:23 -07003174 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003175
Ville Syrjäläf45651b2014-08-08 21:51:10 +03003176 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03003177 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003178
Ville Syrjälä29490562016-01-20 18:02:50 +02003179 intel_add_fb_offsets(&x, &y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +03003180
Daniel Vetterc2c75132012-07-05 12:17:30 +02003181 intel_crtc->dspaddr_offset =
Ville Syrjälä29490562016-01-20 18:02:50 +02003182 intel_compute_tile_offset(&x, &y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +03003183
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03003184 if (rotation == DRM_ROTATE_180) {
Sonika Jindal48404c12014-08-22 14:06:04 +05303185 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003188 x += (crtc_state->pipe_src_w - 1);
3189 y += (crtc_state->pipe_src_h - 1);
Sonika Jindal48404c12014-08-22 14:06:04 +05303190 }
3191 }
3192
Ville Syrjälä29490562016-01-20 18:02:50 +02003193 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +03003194
Paulo Zanoni2db33662015-09-14 15:20:03 -03003195 intel_crtc->adjusted_x = x;
3196 intel_crtc->adjusted_y = y;
3197
Sonika Jindal48404c12014-08-22 14:06:04 +05303198 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07003199
Ville Syrjälä01f2c772011-12-20 00:06:49 +02003200 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01003201 I915_WRITE(DSPSURF(plane),
Ville Syrjälä6687c902015-09-15 13:16:41 +03003202 intel_fb_gtt_offset(fb, rotation) +
3203 intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07003204 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00003205 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206 } else {
3207 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07003210 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07003211}
3212
Ville Syrjälä7b49f942016-01-12 21:08:32 +02003213u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214 uint64_t fb_modifier, uint32_t pixel_format)
Damien Lespiaub3218032015-02-27 11:15:18 +00003215{
Ville Syrjälä7b49f942016-01-12 21:08:32 +02003216 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217 return 64;
3218 } else {
3219 int cpp = drm_format_plane_cpp(pixel_format, 0);
Damien Lespiaub3218032015-02-27 11:15:18 +00003220
Ville Syrjälä27ba3912016-02-15 22:54:40 +02003221 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
Damien Lespiaub3218032015-02-27 11:15:18 +00003222 }
3223}
3224
Ville Syrjälä6687c902015-09-15 13:16:41 +03003225u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226 unsigned int rotation)
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003227{
Ville Syrjälä6687c902015-09-15 13:16:41 +03003228 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetterce7f1722015-10-14 16:51:06 +02003229 struct i915_ggtt_view view;
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01003230 struct i915_vma *vma;
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003231
Ville Syrjälä6687c902015-09-15 13:16:41 +03003232 intel_fill_fb_ggtt_view(&view, fb, rotation);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003233
Chris Wilson058d88c2016-08-15 10:49:06 +01003234 vma = i915_gem_object_to_ggtt(obj, &view);
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01003235 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
Chris Wilson058d88c2016-08-15 10:49:06 +01003236 view.type))
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01003237 return -1;
3238
Chris Wilsonbde13eb2016-08-15 10:49:07 +01003239 return i915_ggtt_offset(vma);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003240}
3241
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02003242static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243{
3244 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003245 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02003246
3247 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02003250}
3251
Chandra Kondurua1b22782015-04-07 15:28:45 -07003252/*
3253 * This function detaches (aka. unbinds) unused scalers in hardware
3254 */
Maarten Lankhorst05832362015-06-15 12:33:48 +02003255static void skl_detach_scalers(struct intel_crtc *intel_crtc)
Chandra Kondurua1b22782015-04-07 15:28:45 -07003256{
Chandra Kondurua1b22782015-04-07 15:28:45 -07003257 struct intel_crtc_scaler_state *scaler_state;
3258 int i;
3259
Chandra Kondurua1b22782015-04-07 15:28:45 -07003260 scaler_state = &intel_crtc->config->scaler_state;
3261
3262 /* loop through and disable scalers that aren't in use */
3263 for (i = 0; i < intel_crtc->num_scalers; i++) {
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02003264 if (!scaler_state->scalers[i].in_use)
3265 skl_detach_scaler(intel_crtc, i);
Chandra Kondurua1b22782015-04-07 15:28:45 -07003266 }
3267}
3268
Ville Syrjäläd2196772016-01-28 18:33:11 +02003269u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270 unsigned int rotation)
3271{
3272 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273 u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275 /*
3276 * The stride is either expressed as a multiple of 64 bytes chunks for
3277 * linear buffers or in number of tiles for tiled buffers.
3278 */
3279 if (intel_rotation_90_or_270(rotation)) {
3280 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283 } else {
3284 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285 fb->pixel_format);
3286 }
3287
3288 return stride;
3289}
3290
Chandra Konduru6156a452015-04-27 13:48:39 -07003291u32 skl_plane_ctl_format(uint32_t pixel_format)
3292{
Chandra Konduru6156a452015-04-27 13:48:39 -07003293 switch (pixel_format) {
Damien Lespiaud161cf72015-05-12 16:13:17 +01003294 case DRM_FORMAT_C8:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003295 return PLANE_CTL_FORMAT_INDEXED;
Chandra Konduru6156a452015-04-27 13:48:39 -07003296 case DRM_FORMAT_RGB565:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003297 return PLANE_CTL_FORMAT_RGB_565;
Chandra Konduru6156a452015-04-27 13:48:39 -07003298 case DRM_FORMAT_XBGR8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003299 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
Chandra Konduru6156a452015-04-27 13:48:39 -07003300 case DRM_FORMAT_XRGB8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003301 return PLANE_CTL_FORMAT_XRGB_8888;
Chandra Konduru6156a452015-04-27 13:48:39 -07003302 /*
3303 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304 * to be already pre-multiplied. We need to add a knob (or a different
3305 * DRM_FORMAT) for user-space to configure that.
3306 */
3307 case DRM_FORMAT_ABGR8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003308 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
Chandra Konduru6156a452015-04-27 13:48:39 -07003309 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003310 case DRM_FORMAT_ARGB8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003311 return PLANE_CTL_FORMAT_XRGB_8888 |
Chandra Konduru6156a452015-04-27 13:48:39 -07003312 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003313 case DRM_FORMAT_XRGB2101010:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003314 return PLANE_CTL_FORMAT_XRGB_2101010;
Chandra Konduru6156a452015-04-27 13:48:39 -07003315 case DRM_FORMAT_XBGR2101010:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003316 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
Chandra Konduru6156a452015-04-27 13:48:39 -07003317 case DRM_FORMAT_YUYV:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003318 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
Chandra Konduru6156a452015-04-27 13:48:39 -07003319 case DRM_FORMAT_YVYU:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003320 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
Chandra Konduru6156a452015-04-27 13:48:39 -07003321 case DRM_FORMAT_UYVY:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003322 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003323 case DRM_FORMAT_VYUY:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003324 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003325 default:
Damien Lespiau4249eee2015-05-12 16:13:16 +01003326 MISSING_CASE(pixel_format);
Chandra Konduru6156a452015-04-27 13:48:39 -07003327 }
Damien Lespiau8cfcba42015-05-12 16:13:14 +01003328
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003329 return 0;
Chandra Konduru6156a452015-04-27 13:48:39 -07003330}
3331
3332u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333{
Chandra Konduru6156a452015-04-27 13:48:39 -07003334 switch (fb_modifier) {
3335 case DRM_FORMAT_MOD_NONE:
3336 break;
3337 case I915_FORMAT_MOD_X_TILED:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003338 return PLANE_CTL_TILED_X;
Chandra Konduru6156a452015-04-27 13:48:39 -07003339 case I915_FORMAT_MOD_Y_TILED:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003340 return PLANE_CTL_TILED_Y;
Chandra Konduru6156a452015-04-27 13:48:39 -07003341 case I915_FORMAT_MOD_Yf_TILED:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003342 return PLANE_CTL_TILED_YF;
Chandra Konduru6156a452015-04-27 13:48:39 -07003343 default:
3344 MISSING_CASE(fb_modifier);
3345 }
Damien Lespiau8cfcba42015-05-12 16:13:14 +01003346
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003347 return 0;
Chandra Konduru6156a452015-04-27 13:48:39 -07003348}
3349
3350u32 skl_plane_ctl_rotation(unsigned int rotation)
3351{
Chandra Konduru6156a452015-04-27 13:48:39 -07003352 switch (rotation) {
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03003353 case DRM_ROTATE_0:
Chandra Konduru6156a452015-04-27 13:48:39 -07003354 break;
Sonika Jindal1e8df162015-05-20 13:40:48 +05303355 /*
3356 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357 * while i915 HW rotation is clockwise, thats why this swapping.
3358 */
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03003359 case DRM_ROTATE_90:
Sonika Jindal1e8df162015-05-20 13:40:48 +05303360 return PLANE_CTL_ROTATE_270;
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03003361 case DRM_ROTATE_180:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003362 return PLANE_CTL_ROTATE_180;
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03003363 case DRM_ROTATE_270:
Sonika Jindal1e8df162015-05-20 13:40:48 +05303364 return PLANE_CTL_ROTATE_90;
Chandra Konduru6156a452015-04-27 13:48:39 -07003365 default:
3366 MISSING_CASE(rotation);
3367 }
3368
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003369 return 0;
Chandra Konduru6156a452015-04-27 13:48:39 -07003370}
3371
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003372static void skylake_update_primary_plane(struct drm_plane *plane,
3373 const struct intel_crtc_state *crtc_state,
3374 const struct intel_plane_state *plane_state)
Damien Lespiau70d21f02013-07-03 21:06:04 +01003375{
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003376 struct drm_device *dev = plane->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003377 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379 struct drm_framebuffer *fb = plane_state->base.fb;
Lyude62e0fb82016-08-22 12:50:08 -04003380 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
Damien Lespiau70d21f02013-07-03 21:06:04 +01003381 int pipe = intel_crtc->pipe;
Ville Syrjäläd2196772016-01-28 18:33:11 +02003382 u32 plane_ctl;
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003383 unsigned int rotation = plane_state->base.rotation;
Ville Syrjäläd2196772016-01-28 18:33:11 +02003384 u32 stride = skl_plane_stride(fb, 0, rotation);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02003385 u32 surf_addr = plane_state->main.offset;
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003386 int scaler_id = plane_state->scaler_id;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02003387 int src_x = plane_state->main.x;
3388 int src_y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003389 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391 int dst_x = plane_state->base.dst.x1;
3392 int dst_y = plane_state->base.dst.y1;
3393 int dst_w = drm_rect_width(&plane_state->base.dst);
3394 int dst_h = drm_rect_height(&plane_state->base.dst);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003395
3396 plane_ctl = PLANE_CTL_ENABLE |
3397 PLANE_CTL_PIPE_GAMMA_ENABLE |
3398 PLANE_CTL_PIPE_CSC_ENABLE;
3399
Chandra Konduru6156a452015-04-27 13:48:39 -07003400 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003402 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
Chandra Konduru6156a452015-04-27 13:48:39 -07003403 plane_ctl |= skl_plane_ctl_rotation(rotation);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003404
Ville Syrjälä6687c902015-09-15 13:16:41 +03003405 /* Sizes are 0 based */
3406 src_w--;
3407 src_h--;
3408 dst_w--;
3409 dst_h--;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303410
Ville Syrjälä6687c902015-09-15 13:16:41 +03003411 intel_crtc->adjusted_x = src_x;
3412 intel_crtc->adjusted_y = src_y;
Paulo Zanoni2db33662015-09-14 15:20:03 -03003413
Lyude62e0fb82016-08-22 12:50:08 -04003414 if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3415 skl_write_plane_wm(intel_crtc, wm, 0);
3416
Damien Lespiau70d21f02013-07-03 21:06:04 +01003417 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
Ville Syrjälä6687c902015-09-15 13:16:41 +03003418 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303419 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
Ville Syrjälä6687c902015-09-15 13:16:41 +03003420 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
Chandra Konduru6156a452015-04-27 13:48:39 -07003421
3422 if (scaler_id >= 0) {
3423 uint32_t ps_ctrl = 0;
3424
3425 WARN_ON(!dst_w || !dst_h);
3426 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3427 crtc_state->scaler_state.scalers[scaler_id].mode;
3428 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3429 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3430 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3431 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3432 I915_WRITE(PLANE_POS(pipe, 0), 0);
3433 } else {
3434 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3435 }
3436
Ville Syrjälä6687c902015-09-15 13:16:41 +03003437 I915_WRITE(PLANE_SURF(pipe, 0),
3438 intel_fb_gtt_offset(fb, rotation) + surf_addr);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003439
3440 POSTING_READ(PLANE_SURF(pipe, 0));
3441}
3442
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003443static void skylake_disable_primary_plane(struct drm_plane *primary,
3444 struct drm_crtc *crtc)
3445{
3446 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003447 struct drm_i915_private *dev_priv = to_i915(dev);
Lyude62e0fb82016-08-22 12:50:08 -04003448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449 int pipe = intel_crtc->pipe;
3450
Lyudeccebc232016-08-29 12:31:27 -04003451 /*
3452 * We only populate skl_results on watermark updates, and if the
3453 * plane's visiblity isn't actually changing neither is its watermarks.
3454 */
3455 if (!crtc->primary->state->visible)
3456 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003457
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003458 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3459 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3460 POSTING_READ(PLANE_SURF(pipe, 0));
3461}
3462
Jesse Barnes17638cd2011-06-24 12:19:23 -07003463/* Assume fb object is pinned & idle & fenced and just update base pointers */
3464static int
3465intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3466 int x, int y, enum mode_set_atomic state)
3467{
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003468 /* Support for kgdboc is disabled, this needs a major rework. */
3469 DRM_ERROR("legacy panic handler not supported any more.\n");
Jesse Barnes17638cd2011-06-24 12:19:23 -07003470
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003471 return -ENODEV;
Jesse Barnes81255562010-08-02 12:07:50 -07003472}
3473
Daniel Vetter5a21b662016-05-24 17:13:53 +02003474static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3475{
3476 struct intel_crtc *crtc;
3477
Chris Wilson91c8a322016-07-05 10:40:23 +01003478 for_each_intel_crtc(&dev_priv->drm, crtc)
Daniel Vetter5a21b662016-05-24 17:13:53 +02003479 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3480}
3481
Ville Syrjälä75147472014-11-24 18:28:11 +02003482static void intel_update_primary_planes(struct drm_device *dev)
3483{
Ville Syrjälä75147472014-11-24 18:28:11 +02003484 struct drm_crtc *crtc;
Ville Syrjälä96a02912013-02-18 19:08:49 +02003485
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01003486 for_each_crtc(dev, crtc) {
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003487 struct intel_plane *plane = to_intel_plane(crtc->primary);
Maarten Lankhorst73974892016-08-05 23:28:27 +03003488 struct intel_plane_state *plane_state =
3489 to_intel_plane_state(plane->base.state);
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003490
Ville Syrjälä936e71e2016-07-26 19:06:59 +03003491 if (plane_state->base.visible)
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +01003492 plane->update_plane(&plane->base,
3493 to_intel_crtc_state(crtc->state),
3494 plane_state);
Ville Syrjälä96a02912013-02-18 19:08:49 +02003495 }
3496}
3497
Maarten Lankhorst73974892016-08-05 23:28:27 +03003498static int
3499__intel_display_resume(struct drm_device *dev,
3500 struct drm_atomic_state *state)
3501{
3502 struct drm_crtc_state *crtc_state;
3503 struct drm_crtc *crtc;
3504 int i, ret;
3505
3506 intel_modeset_setup_hw_state(dev);
3507 i915_redisable_vga(dev);
3508
3509 if (!state)
3510 return 0;
3511
3512 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3513 /*
3514 * Force recalculation even if we restore
3515 * current state. With fast modeset this may not result
3516 * in a modeset when the state is compatible.
3517 */
3518 crtc_state->mode_changed = true;
3519 }
3520
3521 /* ignore any reset values/BIOS leftovers in the WM registers */
3522 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3523
3524 ret = drm_atomic_commit(state);
3525
3526 WARN_ON(ret == -EDEADLK);
3527 return ret;
3528}
3529
Ville Syrjälä4ac2ba22016-08-05 23:28:29 +03003530static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3531{
Ville Syrjäläae981042016-08-05 23:28:30 +03003532 return intel_has_gpu_reset(dev_priv) &&
3533 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
Ville Syrjälä4ac2ba22016-08-05 23:28:29 +03003534}
3535
Chris Wilsonc0336662016-05-06 15:40:21 +01003536void intel_prepare_reset(struct drm_i915_private *dev_priv)
Ville Syrjälä75147472014-11-24 18:28:11 +02003537{
Maarten Lankhorst73974892016-08-05 23:28:27 +03003538 struct drm_device *dev = &dev_priv->drm;
3539 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540 struct drm_atomic_state *state;
3541 int ret;
3542
Maarten Lankhorst73974892016-08-05 23:28:27 +03003543 /*
3544 * Need mode_config.mutex so that we don't
3545 * trample ongoing ->detect() and whatnot.
3546 */
3547 mutex_lock(&dev->mode_config.mutex);
3548 drm_modeset_acquire_init(ctx, 0);
3549 while (1) {
3550 ret = drm_modeset_lock_all_ctx(dev, ctx);
3551 if (ret != -EDEADLK)
3552 break;
3553
3554 drm_modeset_backoff(ctx);
3555 }
3556
3557 /* reset doesn't touch the display, but flips might get nuked anyway, */
Maarten Lankhorst522a63d2016-08-05 23:28:28 +03003558 if (!i915.force_reset_modeset_test &&
Ville Syrjälä4ac2ba22016-08-05 23:28:29 +03003559 !gpu_reset_clobbers_display(dev_priv))
Ville Syrjälä75147472014-11-24 18:28:11 +02003560 return;
3561
Ville Syrjäläf98ce922014-11-21 21:54:30 +02003562 /*
3563 * Disabling the crtcs gracefully seems nicer. Also the
3564 * g33 docs say we should at least disable all the planes.
3565 */
Maarten Lankhorst73974892016-08-05 23:28:27 +03003566 state = drm_atomic_helper_duplicate_state(dev, ctx);
3567 if (IS_ERR(state)) {
3568 ret = PTR_ERR(state);
3569 state = NULL;
3570 DRM_ERROR("Duplicating state failed with %i\n", ret);
3571 goto err;
3572 }
3573
3574 ret = drm_atomic_helper_disable_all(dev, ctx);
3575 if (ret) {
3576 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3577 goto err;
3578 }
3579
3580 dev_priv->modeset_restore_state = state;
3581 state->acquire_ctx = ctx;
3582 return;
3583
3584err:
Chris Wilson08536952016-10-14 13:18:18 +01003585 drm_atomic_state_put(state);
Ville Syrjälä75147472014-11-24 18:28:11 +02003586}
3587
Chris Wilsonc0336662016-05-06 15:40:21 +01003588void intel_finish_reset(struct drm_i915_private *dev_priv)
Ville Syrjälä75147472014-11-24 18:28:11 +02003589{
Maarten Lankhorst73974892016-08-05 23:28:27 +03003590 struct drm_device *dev = &dev_priv->drm;
3591 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3592 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3593 int ret;
3594
Daniel Vetter5a21b662016-05-24 17:13:53 +02003595 /*
3596 * Flips in the rings will be nuked by the reset,
3597 * so complete all pending flips so that user space
3598 * will get its events and not get stuck.
3599 */
3600 intel_complete_page_flips(dev_priv);
3601
Maarten Lankhorst73974892016-08-05 23:28:27 +03003602 dev_priv->modeset_restore_state = NULL;
Ville Syrjälä75147472014-11-24 18:28:11 +02003603
Maarten Lankhorstdfa29972016-08-05 23:28:27 +03003604 dev_priv->modeset_restore_state = NULL;
3605
Ville Syrjälä75147472014-11-24 18:28:11 +02003606 /* reset doesn't touch the display */
Ville Syrjälä4ac2ba22016-08-05 23:28:29 +03003607 if (!gpu_reset_clobbers_display(dev_priv)) {
Maarten Lankhorst522a63d2016-08-05 23:28:28 +03003608 if (!state) {
3609 /*
3610 * Flips in the rings have been nuked by the reset,
3611 * so update the base address of all primary
3612 * planes to the the last fb to make sure we're
3613 * showing the correct fb after a reset.
3614 *
3615 * FIXME: Atomic will make this obsolete since we won't schedule
3616 * CS-based flips (which might get lost in gpu resets) any more.
3617 */
3618 intel_update_primary_planes(dev);
3619 } else {
3620 ret = __intel_display_resume(dev, state);
3621 if (ret)
3622 DRM_ERROR("Restoring old state failed with %i\n", ret);
3623 }
Maarten Lankhorst73974892016-08-05 23:28:27 +03003624 } else {
Ville Syrjälä75147472014-11-24 18:28:11 +02003625 /*
Maarten Lankhorst73974892016-08-05 23:28:27 +03003626 * The display has been reset as well,
3627 * so need a full re-initialization.
Ville Syrjälä75147472014-11-24 18:28:11 +02003628 */
Maarten Lankhorst73974892016-08-05 23:28:27 +03003629 intel_runtime_pm_disable_interrupts(dev_priv);
3630 intel_runtime_pm_enable_interrupts(dev_priv);
3631
3632 intel_modeset_init_hw(dev);
3633
3634 spin_lock_irq(&dev_priv->irq_lock);
3635 if (dev_priv->display.hpd_irq_setup)
3636 dev_priv->display.hpd_irq_setup(dev_priv);
3637 spin_unlock_irq(&dev_priv->irq_lock);
3638
3639 ret = __intel_display_resume(dev, state);
3640 if (ret)
3641 DRM_ERROR("Restoring old state failed with %i\n", ret);
3642
3643 intel_hpd_init(dev_priv);
Ville Syrjälä75147472014-11-24 18:28:11 +02003644 }
3645
Chris Wilson08536952016-10-14 13:18:18 +01003646 if (state)
3647 drm_atomic_state_put(state);
Maarten Lankhorst73974892016-08-05 23:28:27 +03003648 drm_modeset_drop_locks(ctx);
3649 drm_modeset_acquire_fini(ctx);
3650 mutex_unlock(&dev->mode_config.mutex);
Ville Syrjälä75147472014-11-24 18:28:11 +02003651}
3652
Chris Wilson8af29b02016-09-09 14:11:47 +01003653static bool abort_flip_on_reset(struct intel_crtc *crtc)
3654{
3655 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3656
3657 if (i915_reset_in_progress(error))
3658 return true;
3659
3660 if (crtc->reset_count != i915_reset_count(error))
3661 return true;
3662
3663 return false;
3664}
3665
Chris Wilson7d5e3792014-03-04 13:15:08 +00003666static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3667{
Daniel Vetter5a21b662016-05-24 17:13:53 +02003668 struct drm_device *dev = crtc->dev;
3669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter5a21b662016-05-24 17:13:53 +02003670 bool pending;
3671
Chris Wilson8af29b02016-09-09 14:11:47 +01003672 if (abort_flip_on_reset(intel_crtc))
Daniel Vetter5a21b662016-05-24 17:13:53 +02003673 return false;
3674
3675 spin_lock_irq(&dev->event_lock);
3676 pending = to_intel_crtc(crtc)->flip_work != NULL;
3677 spin_unlock_irq(&dev->event_lock);
3678
3679 return pending;
Chris Wilson7d5e3792014-03-04 13:15:08 +00003680}
3681
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003682static void intel_update_pipe_config(struct intel_crtc *crtc,
3683 struct intel_crtc_state *old_crtc_state)
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003684{
3685 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003686 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003687 struct intel_crtc_state *pipe_config =
3688 to_intel_crtc_state(crtc->base.state);
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003689
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003690 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3691 crtc->base.mode = crtc->base.state->mode;
3692
3693 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3694 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3695 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003696
3697 /*
3698 * Update pipe size and adjust fitter if needed: the reason for this is
3699 * that in compute_mode_changes we check the native mode (not the pfit
3700 * mode) to see if we can flip rather than do a full mode set. In the
3701 * fastboot case, we'll flip, but if we don't update the pipesrc and
3702 * pfit state, we'll end up with a big fb scanned out into the wrong
3703 * sized surface.
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003704 */
3705
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003706 I915_WRITE(PIPESRC(crtc->pipe),
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003707 ((pipe_config->pipe_src_w - 1) << 16) |
3708 (pipe_config->pipe_src_h - 1));
3709
3710 /* on skylake this is done by detaching scalers */
3711 if (INTEL_INFO(dev)->gen >= 9) {
3712 skl_detach_scalers(crtc);
3713
3714 if (pipe_config->pch_pfit.enabled)
3715 skylake_pfit_enable(crtc);
3716 } else if (HAS_PCH_SPLIT(dev)) {
3717 if (pipe_config->pch_pfit.enabled)
3718 ironlake_pfit_enable(crtc);
3719 else if (old_crtc_state->pch_pfit.enabled)
3720 ironlake_pfit_disable(crtc, true);
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003721 }
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003722}
3723
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003724static void intel_fdi_normal_train(struct drm_crtc *crtc)
3725{
3726 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003727 struct drm_i915_private *dev_priv = to_i915(dev);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3729 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003730 i915_reg_t reg;
3731 u32 temp;
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003732
3733 /* enable normal train */
3734 reg = FDI_TX_CTL(pipe);
3735 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07003736 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07003737 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3738 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07003739 } else {
3740 temp &= ~FDI_LINK_TRAIN_NONE;
3741 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07003742 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003743 I915_WRITE(reg, temp);
3744
3745 reg = FDI_RX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 if (HAS_PCH_CPT(dev)) {
3748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3749 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3750 } else {
3751 temp &= ~FDI_LINK_TRAIN_NONE;
3752 temp |= FDI_LINK_TRAIN_NONE;
3753 }
3754 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3755
3756 /* wait one idle pattern time */
3757 POSTING_READ(reg);
3758 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07003759
3760 /* IVB wants error correction enabled */
3761 if (IS_IVYBRIDGE(dev))
3762 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3763 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003764}
3765
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003766/* The FDI link training functions for ILK/Ibexpeak. */
3767static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3768{
3769 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003770 struct drm_i915_private *dev_priv = to_i915(dev);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3772 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003773 i915_reg_t reg;
3774 u32 temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003775
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03003776 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003777 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003778
Adam Jacksone1a44742010-06-25 15:32:14 -04003779 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3780 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003781 reg = FDI_RX_IMR(pipe);
3782 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003783 temp &= ~FDI_RX_SYMBOL_LOCK;
3784 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003785 I915_WRITE(reg, temp);
3786 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003787 udelay(150);
3788
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003789 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003790 reg = FDI_TX_CTL(pipe);
3791 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003792 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003793 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003794 temp &= ~FDI_LINK_TRAIN_NONE;
3795 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003796 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003797
Chris Wilson5eddb702010-09-11 13:48:45 +01003798 reg = FDI_RX_CTL(pipe);
3799 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003800 temp &= ~FDI_LINK_TRAIN_NONE;
3801 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003802 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3803
3804 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003805 udelay(150);
3806
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003807 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01003808 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3809 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3810 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003811
Chris Wilson5eddb702010-09-11 13:48:45 +01003812 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003813 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003814 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003815 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3816
3817 if ((temp & FDI_RX_BIT_LOCK)) {
3818 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003819 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003820 break;
3821 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003822 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003823 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003824 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003825
3826 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003827 reg = FDI_TX_CTL(pipe);
3828 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003829 temp &= ~FDI_LINK_TRAIN_NONE;
3830 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003831 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003832
Chris Wilson5eddb702010-09-11 13:48:45 +01003833 reg = FDI_RX_CTL(pipe);
3834 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003835 temp &= ~FDI_LINK_TRAIN_NONE;
3836 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003837 I915_WRITE(reg, temp);
3838
3839 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003840 udelay(150);
3841
Chris Wilson5eddb702010-09-11 13:48:45 +01003842 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003843 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003844 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003845 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3846
3847 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003848 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003849 DRM_DEBUG_KMS("FDI train 2 done.\n");
3850 break;
3851 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003852 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003853 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003854 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003855
3856 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07003857
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003858}
3859
Akshay Joshi0206e352011-08-16 15:34:10 -04003860static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003861 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3862 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3863 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3864 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3865};
3866
3867/* The FDI link training functions for SNB/Cougarpoint. */
3868static void gen6_fdi_link_train(struct drm_crtc *crtc)
3869{
3870 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003871 struct drm_i915_private *dev_priv = to_i915(dev);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3873 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003874 i915_reg_t reg;
3875 u32 temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003876
Adam Jacksone1a44742010-06-25 15:32:14 -04003877 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3878 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003879 reg = FDI_RX_IMR(pipe);
3880 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003881 temp &= ~FDI_RX_SYMBOL_LOCK;
3882 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003883 I915_WRITE(reg, temp);
3884
3885 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003886 udelay(150);
3887
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003888 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003889 reg = FDI_TX_CTL(pipe);
3890 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003891 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003892 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003893 temp &= ~FDI_LINK_TRAIN_NONE;
3894 temp |= FDI_LINK_TRAIN_PATTERN_1;
3895 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3896 /* SNB-B */
3897 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003898 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003899
Daniel Vetterd74cf322012-10-26 10:58:13 +02003900 I915_WRITE(FDI_RX_MISC(pipe),
3901 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3902
Chris Wilson5eddb702010-09-11 13:48:45 +01003903 reg = FDI_RX_CTL(pipe);
3904 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003905 if (HAS_PCH_CPT(dev)) {
3906 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3907 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3908 } else {
3909 temp &= ~FDI_LINK_TRAIN_NONE;
3910 temp |= FDI_LINK_TRAIN_PATTERN_1;
3911 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003912 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3913
3914 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003915 udelay(150);
3916
Akshay Joshi0206e352011-08-16 15:34:10 -04003917 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003918 reg = FDI_TX_CTL(pipe);
3919 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003920 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3921 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003922 I915_WRITE(reg, temp);
3923
3924 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003925 udelay(500);
3926
Sean Paulfa37d392012-03-02 12:53:39 -05003927 for (retry = 0; retry < 5; retry++) {
3928 reg = FDI_RX_IIR(pipe);
3929 temp = I915_READ(reg);
3930 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3931 if (temp & FDI_RX_BIT_LOCK) {
3932 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3933 DRM_DEBUG_KMS("FDI train 1 done.\n");
3934 break;
3935 }
3936 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003937 }
Sean Paulfa37d392012-03-02 12:53:39 -05003938 if (retry < 5)
3939 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003940 }
3941 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003942 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003943
3944 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003945 reg = FDI_TX_CTL(pipe);
3946 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003947 temp &= ~FDI_LINK_TRAIN_NONE;
3948 temp |= FDI_LINK_TRAIN_PATTERN_2;
3949 if (IS_GEN6(dev)) {
3950 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3951 /* SNB-B */
3952 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3953 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003954 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003955
Chris Wilson5eddb702010-09-11 13:48:45 +01003956 reg = FDI_RX_CTL(pipe);
3957 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003958 if (HAS_PCH_CPT(dev)) {
3959 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3960 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3961 } else {
3962 temp &= ~FDI_LINK_TRAIN_NONE;
3963 temp |= FDI_LINK_TRAIN_PATTERN_2;
3964 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003965 I915_WRITE(reg, temp);
3966
3967 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003968 udelay(150);
3969
Akshay Joshi0206e352011-08-16 15:34:10 -04003970 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003971 reg = FDI_TX_CTL(pipe);
3972 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003973 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3974 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003975 I915_WRITE(reg, temp);
3976
3977 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003978 udelay(500);
3979
Sean Paulfa37d392012-03-02 12:53:39 -05003980 for (retry = 0; retry < 5; retry++) {
3981 reg = FDI_RX_IIR(pipe);
3982 temp = I915_READ(reg);
3983 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3984 if (temp & FDI_RX_SYMBOL_LOCK) {
3985 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3986 DRM_DEBUG_KMS("FDI train 2 done.\n");
3987 break;
3988 }
3989 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003990 }
Sean Paulfa37d392012-03-02 12:53:39 -05003991 if (retry < 5)
3992 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003993 }
3994 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003995 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003996
3997 DRM_DEBUG_KMS("FDI train done.\n");
3998}
3999
Jesse Barnes357555c2011-04-28 15:09:55 -07004000/* Manual link training for Ivy Bridge A0 parts */
4001static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4002{
4003 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004004 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes357555c2011-04-28 15:09:55 -07004005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4006 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004007 i915_reg_t reg;
4008 u32 temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07004009
4010 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4011 for train result */
4012 reg = FDI_RX_IMR(pipe);
4013 temp = I915_READ(reg);
4014 temp &= ~FDI_RX_SYMBOL_LOCK;
4015 temp &= ~FDI_RX_BIT_LOCK;
4016 I915_WRITE(reg, temp);
4017
4018 POSTING_READ(reg);
4019 udelay(150);
4020
Daniel Vetter01a415f2012-10-27 15:58:40 +02004021 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4022 I915_READ(FDI_RX_IIR(pipe)));
4023
Jesse Barnes139ccd32013-08-19 11:04:55 -07004024 /* Try each vswing and preemphasis setting twice before moving on */
4025 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4026 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07004027 reg = FDI_TX_CTL(pipe);
4028 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07004029 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4030 temp &= ~FDI_TX_ENABLE;
4031 I915_WRITE(reg, temp);
4032
4033 reg = FDI_RX_CTL(pipe);
4034 temp = I915_READ(reg);
4035 temp &= ~FDI_LINK_TRAIN_AUTO;
4036 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4037 temp &= ~FDI_RX_ENABLE;
4038 I915_WRITE(reg, temp);
4039
4040 /* enable CPU FDI TX and PCH FDI RX */
4041 reg = FDI_TX_CTL(pipe);
4042 temp = I915_READ(reg);
4043 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004044 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Jesse Barnes139ccd32013-08-19 11:04:55 -07004045 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07004046 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07004047 temp |= snb_b_fdi_train_param[j/2];
4048 temp |= FDI_COMPOSITE_SYNC;
4049 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4050
4051 I915_WRITE(FDI_RX_MISC(pipe),
4052 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4053
4054 reg = FDI_RX_CTL(pipe);
4055 temp = I915_READ(reg);
4056 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4057 temp |= FDI_COMPOSITE_SYNC;
4058 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4059
4060 POSTING_READ(reg);
4061 udelay(1); /* should be 0.5us */
4062
4063 for (i = 0; i < 4; i++) {
4064 reg = FDI_RX_IIR(pipe);
4065 temp = I915_READ(reg);
4066 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4067
4068 if (temp & FDI_RX_BIT_LOCK ||
4069 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4070 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4071 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4072 i);
4073 break;
4074 }
4075 udelay(1); /* should be 0.5us */
4076 }
4077 if (i == 4) {
4078 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4079 continue;
4080 }
4081
4082 /* Train 2 */
4083 reg = FDI_TX_CTL(pipe);
4084 temp = I915_READ(reg);
4085 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4086 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4087 I915_WRITE(reg, temp);
4088
4089 reg = FDI_RX_CTL(pipe);
4090 temp = I915_READ(reg);
4091 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4092 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07004093 I915_WRITE(reg, temp);
4094
4095 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07004096 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07004097
Jesse Barnes139ccd32013-08-19 11:04:55 -07004098 for (i = 0; i < 4; i++) {
4099 reg = FDI_RX_IIR(pipe);
4100 temp = I915_READ(reg);
4101 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07004102
Jesse Barnes139ccd32013-08-19 11:04:55 -07004103 if (temp & FDI_RX_SYMBOL_LOCK ||
4104 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4105 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4106 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4107 i);
4108 goto train_done;
4109 }
4110 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07004111 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07004112 if (i == 4)
4113 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07004114 }
Jesse Barnes357555c2011-04-28 15:09:55 -07004115
Jesse Barnes139ccd32013-08-19 11:04:55 -07004116train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07004117 DRM_DEBUG_KMS("FDI train done.\n");
4118}
4119
Daniel Vetter88cefb62012-08-12 19:27:14 +02004120static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07004121{
Daniel Vetter88cefb62012-08-12 19:27:14 +02004122 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004123 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes0e23b992010-09-10 11:10:00 -07004124 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004125 i915_reg_t reg;
4126 u32 temp;
Jesse Barnesc64e3112010-09-10 11:27:03 -07004127
Jesse Barnes0e23b992010-09-10 11:10:00 -07004128 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01004129 reg = FDI_RX_CTL(pipe);
4130 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02004131 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004132 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004133 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01004134 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4135
4136 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07004137 udelay(200);
4138
4139 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01004140 temp = I915_READ(reg);
4141 I915_WRITE(reg, temp | FDI_PCDCLK);
4142
4143 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07004144 udelay(200);
4145
Paulo Zanoni20749732012-11-23 15:30:38 -02004146 /* Enable CPU FDI TX PLL, always on for Ironlake */
4147 reg = FDI_TX_CTL(pipe);
4148 temp = I915_READ(reg);
4149 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4150 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01004151
Paulo Zanoni20749732012-11-23 15:30:38 -02004152 POSTING_READ(reg);
4153 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07004154 }
4155}
4156
Daniel Vetter88cefb62012-08-12 19:27:14 +02004157static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4158{
4159 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004160 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter88cefb62012-08-12 19:27:14 +02004161 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004162 i915_reg_t reg;
4163 u32 temp;
Daniel Vetter88cefb62012-08-12 19:27:14 +02004164
4165 /* Switch from PCDclk to Rawclk */
4166 reg = FDI_RX_CTL(pipe);
4167 temp = I915_READ(reg);
4168 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4169
4170 /* Disable CPU FDI TX PLL */
4171 reg = FDI_TX_CTL(pipe);
4172 temp = I915_READ(reg);
4173 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4174
4175 POSTING_READ(reg);
4176 udelay(100);
4177
4178 reg = FDI_RX_CTL(pipe);
4179 temp = I915_READ(reg);
4180 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4181
4182 /* Wait for the clocks to turn off. */
4183 POSTING_READ(reg);
4184 udelay(100);
4185}
4186
Jesse Barnes0fc932b2011-01-04 15:09:37 -08004187static void ironlake_fdi_disable(struct drm_crtc *crtc)
4188{
4189 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004190 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08004191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004193 i915_reg_t reg;
4194 u32 temp;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08004195
4196 /* disable CPU FDI tx and PCH FDI rx */
4197 reg = FDI_TX_CTL(pipe);
4198 temp = I915_READ(reg);
4199 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4200 POSTING_READ(reg);
4201
4202 reg = FDI_RX_CTL(pipe);
4203 temp = I915_READ(reg);
4204 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004205 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08004206 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4207
4208 POSTING_READ(reg);
4209 udelay(100);
4210
4211 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02004212 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08004213 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08004214
4215 /* still set train pattern 1 */
4216 reg = FDI_TX_CTL(pipe);
4217 temp = I915_READ(reg);
4218 temp &= ~FDI_LINK_TRAIN_NONE;
4219 temp |= FDI_LINK_TRAIN_PATTERN_1;
4220 I915_WRITE(reg, temp);
4221
4222 reg = FDI_RX_CTL(pipe);
4223 temp = I915_READ(reg);
4224 if (HAS_PCH_CPT(dev)) {
4225 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4226 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4227 } else {
4228 temp &= ~FDI_LINK_TRAIN_NONE;
4229 temp |= FDI_LINK_TRAIN_PATTERN_1;
4230 }
4231 /* BPC in FDI rx is consistent with that in PIPECONF */
4232 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004233 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08004234 I915_WRITE(reg, temp);
4235
4236 POSTING_READ(reg);
4237 udelay(100);
4238}
4239
Chris Wilson5dce5b932014-01-20 10:17:36 +00004240bool intel_has_pending_fb_unpin(struct drm_device *dev)
4241{
4242 struct intel_crtc *crtc;
4243
4244 /* Note that we don't need to be called with mode_config.lock here
4245 * as our list of CRTC objects is static for the lifetime of the
4246 * device and so cannot disappear as we iterate. Similarly, we can
4247 * happily treat the predicates as racy, atomic checks as userspace
4248 * cannot claim and pin a new fb without at least acquring the
4249 * struct_mutex and so serialising with us.
4250 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004251 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00004252 if (atomic_read(&crtc->unpin_work_count) == 0)
4253 continue;
4254
Daniel Vetter5a21b662016-05-24 17:13:53 +02004255 if (crtc->flip_work)
Chris Wilson5dce5b932014-01-20 10:17:36 +00004256 intel_wait_for_vblank(dev, crtc->pipe);
4257
4258 return true;
4259 }
4260
4261 return false;
4262}
4263
Daniel Vetter5a21b662016-05-24 17:13:53 +02004264static void page_flip_completed(struct intel_crtc *intel_crtc)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004265{
4266 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +02004267 struct intel_flip_work *work = intel_crtc->flip_work;
4268
4269 intel_crtc->flip_work = NULL;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004270
4271 if (work->event)
Gustavo Padovan560ce1d2016-04-14 10:48:15 -07004272 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004273
4274 drm_crtc_vblank_put(&intel_crtc->base);
4275
Daniel Vetter5a21b662016-05-24 17:13:53 +02004276 wake_up_all(&dev_priv->pending_flip_queue);
Maarten Lankhorst143f73b32016-05-17 15:07:54 +02004277 queue_work(dev_priv->wq, &work->unpin_work);
Daniel Vetter5a21b662016-05-24 17:13:53 +02004278
4279 trace_i915_flip_complete(intel_crtc->plane,
4280 work->pending_flip_obj);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004281}
4282
Maarten Lankhorst5008e872015-08-18 13:40:05 +02004283static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01004284{
Chris Wilson0f911282012-04-17 10:05:38 +01004285 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004286 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst5008e872015-08-18 13:40:05 +02004287 long ret;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01004288
Daniel Vetter2c10d572012-12-20 21:24:07 +01004289 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Maarten Lankhorst5008e872015-08-18 13:40:05 +02004290
4291 ret = wait_event_interruptible_timeout(
4292 dev_priv->pending_flip_queue,
4293 !intel_crtc_has_pending_flip(crtc),
4294 60*HZ);
4295
4296 if (ret < 0)
4297 return ret;
4298
Daniel Vetter5a21b662016-05-24 17:13:53 +02004299 if (ret == 0) {
4300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301 struct intel_flip_work *work;
4302
4303 spin_lock_irq(&dev->event_lock);
4304 work = intel_crtc->flip_work;
4305 if (work && !is_mmio_work(work)) {
4306 WARN_ONCE(1, "Removing stuck page flip\n");
4307 page_flip_completed(intel_crtc);
4308 }
4309 spin_unlock_irq(&dev->event_lock);
4310 }
Chris Wilson5bb61642012-09-27 21:25:58 +01004311
Maarten Lankhorst5008e872015-08-18 13:40:05 +02004312 return 0;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01004313}
4314
Maarten Lankhorstb7076542016-08-23 16:18:08 +02004315void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
Ville Syrjälä060f02d2015-12-04 22:21:34 +02004316{
4317 u32 temp;
4318
4319 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4320
4321 mutex_lock(&dev_priv->sb_lock);
4322
4323 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4324 temp |= SBI_SSCCTL_DISABLE;
4325 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4326
4327 mutex_unlock(&dev_priv->sb_lock);
4328}
4329
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004330/* Program iCLKIP clock to the desired frequency */
4331static void lpt_program_iclkip(struct drm_crtc *crtc)
4332{
Ville Syrjälä64b46a02016-02-17 21:41:11 +02004333 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004334 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004335 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4336 u32 temp;
4337
Ville Syrjälä060f02d2015-12-04 22:21:34 +02004338 lpt_disable_iclkip(dev_priv);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004339
Ville Syrjälä64b46a02016-02-17 21:41:11 +02004340 /* The iCLK virtual clock root frequency is in MHz,
4341 * but the adjusted_mode->crtc_clock in in KHz. To get the
4342 * divisors, it is necessary to divide one by another, so we
4343 * convert the virtual clock precision to KHz here for higher
4344 * precision.
4345 */
4346 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004347 u32 iclk_virtual_root_freq = 172800 * 1000;
4348 u32 iclk_pi_range = 64;
Ville Syrjälä64b46a02016-02-17 21:41:11 +02004349 u32 desired_divisor;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004350
Ville Syrjälä64b46a02016-02-17 21:41:11 +02004351 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4352 clock << auxdiv);
4353 divsel = (desired_divisor / iclk_pi_range) - 2;
4354 phaseinc = desired_divisor % iclk_pi_range;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004355
Ville Syrjälä64b46a02016-02-17 21:41:11 +02004356 /*
4357 * Near 20MHz is a corner case which is
4358 * out of range for the 7-bit divisor
4359 */
4360 if (divsel <= 0x7f)
4361 break;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004362 }
4363
4364 /* This should not happen with any sane values */
4365 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4366 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4367 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4368 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4369
4370 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03004371 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004372 auxdiv,
4373 divsel,
4374 phasedir,
4375 phaseinc);
4376
Ville Syrjälä060f02d2015-12-04 22:21:34 +02004377 mutex_lock(&dev_priv->sb_lock);
4378
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004379 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004380 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004381 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4382 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4383 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4384 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4385 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4386 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004387 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004388
4389 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004390 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004391 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4392 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004393 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004394
4395 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004396 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004397 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004398 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004399
Ville Syrjälä060f02d2015-12-04 22:21:34 +02004400 mutex_unlock(&dev_priv->sb_lock);
4401
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004402 /* Wait for initialization time */
4403 udelay(24);
4404
4405 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4406}
4407
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02004408int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4409{
4410 u32 divsel, phaseinc, auxdiv;
4411 u32 iclk_virtual_root_freq = 172800 * 1000;
4412 u32 iclk_pi_range = 64;
4413 u32 desired_divisor;
4414 u32 temp;
4415
4416 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4417 return 0;
4418
4419 mutex_lock(&dev_priv->sb_lock);
4420
4421 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4422 if (temp & SBI_SSCCTL_DISABLE) {
4423 mutex_unlock(&dev_priv->sb_lock);
4424 return 0;
4425 }
4426
4427 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4428 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4429 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4430 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4431 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4432
4433 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4434 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4435 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4436
4437 mutex_unlock(&dev_priv->sb_lock);
4438
4439 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4440
4441 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4442 desired_divisor << auxdiv);
4443}
4444
Daniel Vetter275f01b22013-05-03 11:49:47 +02004445static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4446 enum pipe pch_transcoder)
4447{
4448 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004449 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004450 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Daniel Vetter275f01b22013-05-03 11:49:47 +02004451
4452 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4453 I915_READ(HTOTAL(cpu_transcoder)));
4454 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4455 I915_READ(HBLANK(cpu_transcoder)));
4456 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4457 I915_READ(HSYNC(cpu_transcoder)));
4458
4459 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4460 I915_READ(VTOTAL(cpu_transcoder)));
4461 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4462 I915_READ(VBLANK(cpu_transcoder)));
4463 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4464 I915_READ(VSYNC(cpu_transcoder)));
4465 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4466 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4467}
4468
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004469static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004470{
Chris Wilsonfac5e232016-07-04 11:34:36 +01004471 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004472 uint32_t temp;
4473
4474 temp = I915_READ(SOUTH_CHICKEN1);
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004475 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004476 return;
4477
4478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4480
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004481 temp &= ~FDI_BC_BIFURCATION_SELECT;
4482 if (enable)
4483 temp |= FDI_BC_BIFURCATION_SELECT;
4484
4485 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004486 I915_WRITE(SOUTH_CHICKEN1, temp);
4487 POSTING_READ(SOUTH_CHICKEN1);
4488}
4489
4490static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4491{
4492 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004493
4494 switch (intel_crtc->pipe) {
4495 case PIPE_A:
4496 break;
4497 case PIPE_B:
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004498 if (intel_crtc->config->fdi_lanes > 2)
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004499 cpt_set_fdi_bc_bifurcation(dev, false);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004500 else
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004501 cpt_set_fdi_bc_bifurcation(dev, true);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004502
4503 break;
4504 case PIPE_C:
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004505 cpt_set_fdi_bc_bifurcation(dev, true);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004506
4507 break;
4508 default:
4509 BUG();
4510 }
4511}
4512
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004513/* Return which DP Port should be selected for Transcoder DP control */
4514static enum port
4515intel_trans_dp_port_sel(struct drm_crtc *crtc)
4516{
4517 struct drm_device *dev = crtc->dev;
4518 struct intel_encoder *encoder;
4519
4520 for_each_encoder_on_crtc(dev, crtc, encoder) {
Ville Syrjäläcca05022016-06-22 21:57:06 +03004521 if (encoder->type == INTEL_OUTPUT_DP ||
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004522 encoder->type == INTEL_OUTPUT_EDP)
4523 return enc_to_dig_port(&encoder->base)->port;
4524 }
4525
4526 return -1;
4527}
4528
Jesse Barnesf67a5592011-01-05 10:31:48 -08004529/*
4530 * Enable PCH resources required for PCH ports:
4531 * - PCH PLLs
4532 * - FDI training & RX/TX
4533 * - update transcoder timings
4534 * - DP transcoding bits
4535 * - transcoder
4536 */
4537static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004538{
4539 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004540 struct drm_i915_private *dev_priv = to_i915(dev);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004543 u32 temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004544
Daniel Vetterab9412b2013-05-03 11:49:46 +02004545 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01004546
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004547 if (IS_IVYBRIDGE(dev))
4548 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4549
Daniel Vettercd986ab2012-10-26 10:58:12 +02004550 /* Write the TU size bits before fdi link training, so that error
4551 * detection works. */
4552 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4553 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4554
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004555 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07004556 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004557
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004558 /* We need to program the right clock selection before writing the pixel
4559 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02004560 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004561 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004562
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004563 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004564 temp |= TRANS_DPLL_ENABLE(pipe);
4565 sel = TRANS_DPLLB_SEL(pipe);
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02004566 if (intel_crtc->config->shared_dpll ==
4567 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004568 temp |= sel;
4569 else
4570 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004571 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004572 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004573
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004574 /* XXX: pch pll's can be enabled any time before we enable the PCH
4575 * transcoder, and we actually should do this to not upset any PCH
4576 * transcoder that already use the clock when we share it.
4577 *
4578 * Note that enable_shared_dpll tries to do the right thing, but
4579 * get_shared_dpll unconditionally resets the pll - we need that to have
4580 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02004581 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004582
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08004583 /* set transcoder timing, panel must allow it */
4584 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02004585 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004586
Paulo Zanoni303b81e2012-10-31 18:12:23 -02004587 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08004588
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004589 /* For PCH DP, enable TRANS_DP_CTL */
Ville Syrjälä37a56502016-06-22 21:57:04 +03004590 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
Ville Syrjälä9c4edae2015-10-29 21:25:51 +02004591 const struct drm_display_mode *adjusted_mode =
4592 &intel_crtc->config->base.adjusted_mode;
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004593 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004594 i915_reg_t reg = TRANS_DP_CTL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01004595 temp = I915_READ(reg);
4596 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08004597 TRANS_DP_SYNC_MASK |
4598 TRANS_DP_BPC_MASK);
Ville Syrjäläe3ef4472015-05-05 17:17:31 +03004599 temp |= TRANS_DP_OUTPUT_ENABLE;
Jesse Barnes9325c9f2011-06-24 12:19:21 -07004600 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004601
Ville Syrjälä9c4edae2015-10-29 21:25:51 +02004602 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01004603 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Ville Syrjälä9c4edae2015-10-29 21:25:51 +02004604 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01004605 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004606
4607 switch (intel_trans_dp_port_sel(crtc)) {
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004608 case PORT_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01004609 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004610 break;
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004611 case PORT_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01004612 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004613 break;
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004614 case PORT_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01004615 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004616 break;
4617 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02004618 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004619 }
4620
Chris Wilson5eddb702010-09-11 13:48:45 +01004621 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004622 }
4623
Paulo Zanonib8a4f402012-10-31 18:12:42 -02004624 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004625}
4626
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004627static void lpt_pch_enable(struct drm_crtc *crtc)
4628{
4629 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004630 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004632 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004633
Daniel Vetterab9412b2013-05-03 11:49:46 +02004634 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004635
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02004636 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004637
Paulo Zanoni0540e482012-10-31 18:12:40 -02004638 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02004639 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004640
Paulo Zanoni937bb612012-10-31 18:12:47 -02004641 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004642}
4643
Daniel Vettera1520312013-05-03 11:49:50 +02004644static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07004645{
Chris Wilsonfac5e232016-07-04 11:34:36 +01004646 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004647 i915_reg_t dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07004648 u32 temp;
4649
4650 temp = I915_READ(dslreg);
4651 udelay(500);
4652 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07004653 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03004654 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07004655 }
4656}
4657
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004658static int
4659skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4660 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4661 int src_w, int src_h, int dst_w, int dst_h)
Chandra Kondurua1b22782015-04-07 15:28:45 -07004662{
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004663 struct intel_crtc_scaler_state *scaler_state =
4664 &crtc_state->scaler_state;
4665 struct intel_crtc *intel_crtc =
4666 to_intel_crtc(crtc_state->base.crtc);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004667 int need_scaling;
Chandra Konduru6156a452015-04-27 13:48:39 -07004668
4669 need_scaling = intel_rotation_90_or_270(rotation) ?
4670 (src_h != dst_w || src_w != dst_h):
4671 (src_w != dst_w || src_h != dst_h);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004672
4673 /*
4674 * if plane is being disabled or scaler is no more required or force detach
4675 * - free scaler binded to this plane/crtc
4676 * - in order to do this, update crtc->scaler_usage
4677 *
4678 * Here scaler state in crtc_state is set free so that
4679 * scaler can be assigned to other user. Actual register
4680 * update to free the scaler is done in plane/panel-fit programming.
4681 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4682 */
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004683 if (force_detach || !need_scaling) {
Chandra Kondurua1b22782015-04-07 15:28:45 -07004684 if (*scaler_id >= 0) {
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004685 scaler_state->scaler_users &= ~(1 << scaler_user);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004686 scaler_state->scalers[*scaler_id].in_use = 0;
4687
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004688 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4689 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4690 intel_crtc->pipe, scaler_user, *scaler_id,
Chandra Kondurua1b22782015-04-07 15:28:45 -07004691 scaler_state->scaler_users);
4692 *scaler_id = -1;
4693 }
4694 return 0;
4695 }
4696
4697 /* range checks */
4698 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4699 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4700
4701 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4702 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004703 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
Chandra Kondurua1b22782015-04-07 15:28:45 -07004704 "size is out of scaler range\n",
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004705 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004706 return -EINVAL;
4707 }
4708
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004709 /* mark this plane as a scaler user in crtc_state */
4710 scaler_state->scaler_users |= (1 << scaler_user);
4711 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4712 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4713 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4714 scaler_state->scaler_users);
4715
4716 return 0;
4717}
4718
4719/**
4720 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4721 *
4722 * @state: crtc's scaler state
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004723 *
4724 * Return
4725 * 0 - scaler_usage updated successfully
4726 * error - requested scaling cannot be supported or other error condition
4727 */
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02004728int skl_update_scaler_crtc(struct intel_crtc_state *state)
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004729{
4730 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03004731 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004732
Ville Syrjälä78108b72016-05-27 20:59:19 +03004733 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4734 intel_crtc->base.base.id, intel_crtc->base.name,
4735 intel_crtc->pipe, SKL_CRTC_INDEX);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004736
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02004737 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03004738 &state->scaler_state.scaler_id, DRM_ROTATE_0,
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004739 state->pipe_src_w, state->pipe_src_h,
Ville Syrjäläaad941d2015-09-25 16:38:56 +03004740 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004741}
4742
4743/**
4744 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4745 *
4746 * @state: crtc's scaler state
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004747 * @plane_state: atomic plane state to update
4748 *
4749 * Return
4750 * 0 - scaler_usage updated successfully
4751 * error - requested scaling cannot be supported or other error condition
4752 */
Maarten Lankhorstda20eab2015-06-15 12:33:44 +02004753static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4754 struct intel_plane_state *plane_state)
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004755{
4756
4757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +02004758 struct intel_plane *intel_plane =
4759 to_intel_plane(plane_state->base.plane);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004760 struct drm_framebuffer *fb = plane_state->base.fb;
4761 int ret;
4762
Ville Syrjälä936e71e2016-07-26 19:06:59 +03004763 bool force_detach = !fb || !plane_state->base.visible;
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004764
Ville Syrjälä72660ce2016-05-27 20:59:20 +03004765 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4766 intel_plane->base.base.id, intel_plane->base.name,
4767 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004768
4769 ret = skl_update_scaler(crtc_state, force_detach,
4770 drm_plane_index(&intel_plane->base),
4771 &plane_state->scaler_id,
4772 plane_state->base.rotation,
Ville Syrjälä936e71e2016-07-26 19:06:59 +03004773 drm_rect_width(&plane_state->base.src) >> 16,
4774 drm_rect_height(&plane_state->base.src) >> 16,
4775 drm_rect_width(&plane_state->base.dst),
4776 drm_rect_height(&plane_state->base.dst));
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004777
4778 if (ret || plane_state->scaler_id < 0)
4779 return ret;
4780
Chandra Kondurua1b22782015-04-07 15:28:45 -07004781 /* check colorkey */
Maarten Lankhorst818ed962015-06-15 12:33:54 +02004782 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
Ville Syrjälä72660ce2016-05-27 20:59:20 +03004783 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4784 intel_plane->base.base.id,
4785 intel_plane->base.name);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004786 return -EINVAL;
4787 }
4788
4789 /* Check src format */
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004790 switch (fb->pixel_format) {
4791 case DRM_FORMAT_RGB565:
4792 case DRM_FORMAT_XBGR8888:
4793 case DRM_FORMAT_XRGB8888:
4794 case DRM_FORMAT_ABGR8888:
4795 case DRM_FORMAT_ARGB8888:
4796 case DRM_FORMAT_XRGB2101010:
4797 case DRM_FORMAT_XBGR2101010:
4798 case DRM_FORMAT_YUYV:
4799 case DRM_FORMAT_YVYU:
4800 case DRM_FORMAT_UYVY:
4801 case DRM_FORMAT_VYUY:
4802 break;
4803 default:
Ville Syrjälä72660ce2016-05-27 20:59:20 +03004804 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4805 intel_plane->base.base.id, intel_plane->base.name,
4806 fb->base.id, fb->pixel_format);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004807 return -EINVAL;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004808 }
4809
Chandra Kondurua1b22782015-04-07 15:28:45 -07004810 return 0;
4811}
4812
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02004813static void skylake_scaler_disable(struct intel_crtc *crtc)
4814{
4815 int i;
4816
4817 for (i = 0; i < crtc->num_scalers; i++)
4818 skl_detach_scaler(crtc, i);
4819}
4820
4821static void skylake_pfit_enable(struct intel_crtc *crtc)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004822{
4823 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004824 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004825 int pipe = crtc->pipe;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004826 struct intel_crtc_scaler_state *scaler_state =
4827 &crtc->config->scaler_state;
4828
4829 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4830
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004831 if (crtc->config->pch_pfit.enabled) {
Chandra Kondurua1b22782015-04-07 15:28:45 -07004832 int id;
4833
4834 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4835 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4836 return;
4837 }
4838
4839 id = scaler_state->scaler_id;
4840 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4841 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4842 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4843 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4844
4845 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004846 }
4847}
4848
Jesse Barnesb074cec2013-04-25 12:55:02 -07004849static void ironlake_pfit_enable(struct intel_crtc *crtc)
4850{
4851 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004852 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesb074cec2013-04-25 12:55:02 -07004853 int pipe = crtc->pipe;
4854
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004855 if (crtc->config->pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07004856 /* Force use of hard-coded filter coefficients
4857 * as some pre-programmed values are broken,
4858 * e.g. x201.
4859 */
4860 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4861 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4862 PF_PIPE_SEL_IVB(pipe));
4863 else
4864 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004865 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4866 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08004867 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004868}
4869
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004870void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004871{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004872 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004873 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonid77e4532013-09-24 13:52:55 -03004874
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004875 if (!crtc->config->ips_enabled)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004876 return;
4877
Maarten Lankhorst307e4492016-03-23 14:33:28 +01004878 /*
4879 * We can only enable IPS after we enable a plane and wait for a vblank
4880 * This function is called from post_plane_update, which is run after
4881 * a vblank wait.
4882 */
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004883
Paulo Zanonid77e4532013-09-24 13:52:55 -03004884 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004885 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004886 mutex_lock(&dev_priv->rps.hw_lock);
4887 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4888 mutex_unlock(&dev_priv->rps.hw_lock);
4889 /* Quoting Art Runyan: "its not safe to expect any particular
4890 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08004891 * mailbox." Moreover, the mailbox may return a bogus state,
4892 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004893 */
4894 } else {
4895 I915_WRITE(IPS_CTL, IPS_ENABLE);
4896 /* The bit only becomes 1 in the next vblank, so this wait here
4897 * is essentially intel_wait_for_vblank. If we don't have this
4898 * and don't wait for vblanks until the end of crtc_enable, then
4899 * the HW state readout code will complain that the expected
4900 * IPS_CTL value is not the one we read. */
Chris Wilson2ec9ba32016-06-30 15:33:01 +01004901 if (intel_wait_for_register(dev_priv,
4902 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4903 50))
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004904 DRM_ERROR("Timed out waiting for IPS enable\n");
4905 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004906}
4907
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004908void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004909{
4910 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004911 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonid77e4532013-09-24 13:52:55 -03004912
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004913 if (!crtc->config->ips_enabled)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004914 return;
4915
4916 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004917 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004918 mutex_lock(&dev_priv->rps.hw_lock);
4919 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4920 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004921 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
Chris Wilsonb85c1ec2016-06-30 15:33:02 +01004922 if (intel_wait_for_register(dev_priv,
4923 IPS_CTL, IPS_ENABLE, 0,
4924 42))
Ben Widawsky23d0b132014-04-10 14:32:41 -07004925 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08004926 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004927 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08004928 POSTING_READ(IPS_CTL);
4929 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004930
4931 /* We need to wait for a vblank before we can disable the plane. */
4932 intel_wait_for_vblank(dev, crtc->pipe);
4933}
4934
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004935static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004936{
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004937 if (intel_crtc->overlay) {
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004938 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004939 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004940
4941 mutex_lock(&dev->struct_mutex);
4942 dev_priv->mm.interruptible = false;
4943 (void) intel_overlay_switch_off(intel_crtc->overlay);
4944 dev_priv->mm.interruptible = true;
4945 mutex_unlock(&dev->struct_mutex);
4946 }
4947
4948 /* Let userspace switch the overlay on again. In most cases userspace
4949 * has to recompute where to put it anyway.
4950 */
4951}
4952
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004953/**
4954 * intel_post_enable_primary - Perform operations after enabling primary plane
4955 * @crtc: the CRTC whose primary plane was just enabled
4956 *
4957 * Performs potentially sleeping operations that must be done after the primary
4958 * plane is enabled, such as updating FBC and IPS. Note that this may be
4959 * called due to an explicit primary plane update, or due to an implicit
4960 * re-enable that is caused when a sprite plane is updated to no longer
4961 * completely hide the primary plane.
4962 */
4963static void
4964intel_post_enable_primary(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004965{
4966 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004967 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004970
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004971 /*
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004972 * FIXME IPS should be fine as long as one plane is
4973 * enabled, but in practice it seems to have problems
4974 * when going from primary only to sprite only and vice
4975 * versa.
4976 */
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004977 hsw_enable_ips(intel_crtc);
4978
Daniel Vetterf99d7062014-06-19 16:01:59 +02004979 /*
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004980 * Gen2 reports pipe underruns whenever all planes are disabled.
4981 * So don't enable underrun reporting before at least some planes
4982 * are enabled.
4983 * FIXME: Need to fix the logic to work when we turn off all planes
4984 * but leave the pipe running.
Daniel Vetterf99d7062014-06-19 16:01:59 +02004985 */
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004986 if (IS_GEN2(dev))
4987 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
Ville Syrjäläaca7b682015-10-30 19:22:21 +02004989 /* Underruns don't always raise interrupts, so check manually. */
4990 intel_check_cpu_fifo_underruns(dev_priv);
4991 intel_check_pch_fifo_underruns(dev_priv);
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004992}
4993
Ville Syrjälä2622a082016-03-09 19:07:26 +02004994/* FIXME move all this to pre_plane_update() with proper state tracking */
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004995static void
4996intel_pre_disable_primary(struct drm_crtc *crtc)
4997{
4998 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01004999 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst87d43002015-04-21 17:12:54 +03005000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001 int pipe = intel_crtc->pipe;
5002
5003 /*
5004 * Gen2 reports pipe underruns whenever all planes are disabled.
5005 * So diasble underrun reporting before all the planes get disabled.
5006 * FIXME: Need to fix the logic to work when we turn off all planes
5007 * but leave the pipe running.
5008 */
5009 if (IS_GEN2(dev))
5010 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5011
5012 /*
Ville Syrjälä2622a082016-03-09 19:07:26 +02005013 * FIXME IPS should be fine as long as one plane is
5014 * enabled, but in practice it seems to have problems
5015 * when going from primary only to sprite only and vice
5016 * versa.
5017 */
5018 hsw_disable_ips(intel_crtc);
5019}
5020
5021/* FIXME get rid of this and use pre_plane_update */
5022static void
5023intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5024{
5025 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005026 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä2622a082016-03-09 19:07:26 +02005027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 int pipe = intel_crtc->pipe;
5029
5030 intel_pre_disable_primary(crtc);
5031
5032 /*
Maarten Lankhorst87d43002015-04-21 17:12:54 +03005033 * Vblank time updates from the shadow to live plane control register
5034 * are blocked if the memory self-refresh mode is active at that
5035 * moment. So to make sure the plane gets truly disabled, disable
5036 * first the self-refresh mode. The self-refresh enable bit in turn
5037 * will be checked/applied by the HW only at the next frame start
5038 * event which is after the vblank start event, so we need to have a
5039 * wait-for-vblank between disabling the plane and the pipe.
5040 */
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03005041 if (HAS_GMCH_DISPLAY(dev)) {
Maarten Lankhorst87d43002015-04-21 17:12:54 +03005042 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03005043 dev_priv->wm.vlv.cxsr = false;
5044 intel_wait_for_vblank(dev, pipe);
5045 }
Maarten Lankhorst87d43002015-04-21 17:12:54 +03005046}
5047
Daniel Vetter5a21b662016-05-24 17:13:53 +02005048static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5049{
5050 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5051 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5052 struct intel_crtc_state *pipe_config =
5053 to_intel_crtc_state(crtc->base.state);
Daniel Vetter5a21b662016-05-24 17:13:53 +02005054 struct drm_plane *primary = crtc->base.primary;
5055 struct drm_plane_state *old_pri_state =
5056 drm_atomic_get_existing_plane_state(old_state, primary);
5057
Chris Wilson5748b6a2016-08-04 16:32:38 +01005058 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
Daniel Vetter5a21b662016-05-24 17:13:53 +02005059
5060 crtc->wm.cxsr_allowed = true;
5061
5062 if (pipe_config->update_wm_post && pipe_config->base.active)
5063 intel_update_watermarks(&crtc->base);
5064
5065 if (old_pri_state) {
5066 struct intel_plane_state *primary_state =
5067 to_intel_plane_state(primary->state);
5068 struct intel_plane_state *old_primary_state =
5069 to_intel_plane_state(old_pri_state);
5070
5071 intel_fbc_post_update(crtc);
5072
Ville Syrjälä936e71e2016-07-26 19:06:59 +03005073 if (primary_state->base.visible &&
Daniel Vetter5a21b662016-05-24 17:13:53 +02005074 (needs_modeset(&pipe_config->base) ||
Ville Syrjälä936e71e2016-07-26 19:06:59 +03005075 !old_primary_state->base.visible))
Daniel Vetter5a21b662016-05-24 17:13:53 +02005076 intel_post_enable_primary(&crtc->base);
5077 }
5078}
5079
Maarten Lankhorst5c74cd72016-02-03 16:53:24 +01005080static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
Maarten Lankhorstac21b222015-06-15 12:33:49 +02005081{
Maarten Lankhorst5c74cd72016-02-03 16:53:24 +01005082 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02005083 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005084 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +01005085 struct intel_crtc_state *pipe_config =
5086 to_intel_crtc_state(crtc->base.state);
Maarten Lankhorst5c74cd72016-02-03 16:53:24 +01005087 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5088 struct drm_plane *primary = crtc->base.primary;
5089 struct drm_plane_state *old_pri_state =
5090 drm_atomic_get_existing_plane_state(old_state, primary);
5091 bool modeset = needs_modeset(&pipe_config->base);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02005092
Maarten Lankhorst5c74cd72016-02-03 16:53:24 +01005093 if (old_pri_state) {
5094 struct intel_plane_state *primary_state =
5095 to_intel_plane_state(primary->state);
5096 struct intel_plane_state *old_primary_state =
5097 to_intel_plane_state(old_pri_state);
5098
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02005099 intel_fbc_pre_update(crtc, pipe_config, primary_state);
Maarten Lankhorst31ae71f2016-03-09 10:35:45 +01005100
Ville Syrjälä936e71e2016-07-26 19:06:59 +03005101 if (old_primary_state->base.visible &&
5102 (modeset || !primary_state->base.visible))
Maarten Lankhorst5c74cd72016-02-03 16:53:24 +01005103 intel_pre_disable_primary(&crtc->base);
5104 }
Ville Syrjälä852eb002015-06-24 22:00:07 +03005105
David Weinehalla4015f92016-05-19 15:50:36 +03005106 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
Ville Syrjälä852eb002015-06-24 22:00:07 +03005107 crtc->wm.cxsr_allowed = false;
Maarten Lankhorst2dfd1782016-02-03 16:53:25 +01005108
Ville Syrjälä2622a082016-03-09 19:07:26 +02005109 /*
5110 * Vblank time updates from the shadow to live plane control register
5111 * are blocked if the memory self-refresh mode is active at that
5112 * moment. So to make sure the plane gets truly disabled, disable
5113 * first the self-refresh mode. The self-refresh enable bit in turn
5114 * will be checked/applied by the HW only at the next frame start
5115 * event which is after the vblank start event, so we need to have a
5116 * wait-for-vblank between disabling the plane and the pipe.
5117 */
5118 if (old_crtc_state->base.active) {
Maarten Lankhorst2dfd1782016-02-03 16:53:25 +01005119 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä2622a082016-03-09 19:07:26 +02005120 dev_priv->wm.vlv.cxsr = false;
5121 intel_wait_for_vblank(dev, crtc->pipe);
5122 }
Ville Syrjälä852eb002015-06-24 22:00:07 +03005123 }
Maarten Lankhorst92826fc2015-12-03 13:49:13 +01005124
Matt Ropered4a6a72016-02-23 17:20:13 -08005125 /*
5126 * IVB workaround: must disable low power watermarks for at least
5127 * one frame before enabling scaling. LP watermarks can be re-enabled
5128 * when scaling is disabled.
5129 *
5130 * WaCxSRDisabledForSpriteScaling:ivb
5131 */
5132 if (pipe_config->disable_lp_wm) {
5133 ilk_disable_lp_wm(dev);
5134 intel_wait_for_vblank(dev, crtc->pipe);
5135 }
5136
5137 /*
5138 * If we're doing a modeset, we're done. No need to do any pre-vblank
5139 * watermark programming here.
5140 */
5141 if (needs_modeset(&pipe_config->base))
5142 return;
5143
5144 /*
5145 * For platforms that support atomic watermarks, program the
5146 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5147 * will be the intermediate values that are safe for both pre- and
5148 * post- vblank; when vblank happens, the 'active' values will be set
5149 * to the final 'target' values and we'll do this again to get the
5150 * optimal watermarks. For gen9+ platforms, the values we program here
5151 * will be the final target values which will get automatically latched
5152 * at vblank time; no further programming will be necessary.
5153 *
5154 * If a platform hasn't been transitioned to atomic watermarks yet,
5155 * we'll continue to update watermarks the old way, if flags tell
5156 * us to.
5157 */
5158 if (dev_priv->display.initial_watermarks != NULL)
5159 dev_priv->display.initial_watermarks(pipe_config);
Ville Syrjäläcaed3612016-03-09 19:07:25 +02005160 else if (pipe_config->update_wm_pre)
Maarten Lankhorst92826fc2015-12-03 13:49:13 +01005161 intel_update_watermarks(&crtc->base);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02005162}
5163
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +02005164static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02005165{
5166 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02005167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +02005168 struct drm_plane *p;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02005169 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02005170
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03005171 intel_crtc_dpms_overlay_disable(intel_crtc);
Maarten Lankhorst27321ae2015-04-21 17:12:52 +03005172
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +02005173 drm_for_each_plane_mask(p, dev, plane_mask)
5174 to_intel_plane(p)->disable_plane(p, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03005175
Daniel Vetterf99d7062014-06-19 16:01:59 +02005176 /*
5177 * FIXME: Once we grow proper nuclear flip support out of this we need
5178 * to compute the mask of flip planes precisely. For the time being
5179 * consider this a flip to a NULL plane.
5180 */
Chris Wilson5748b6a2016-08-04 16:32:38 +01005181 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02005182}
5183
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005184static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005185 struct intel_crtc_state *crtc_state,
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005186 struct drm_atomic_state *old_state)
Jesse Barnesf67a5592011-01-05 10:31:48 -08005187{
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005188 struct drm_connector_state *old_conn_state;
5189 struct drm_connector *conn;
5190 int i;
5191
5192 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5193 struct drm_connector_state *conn_state = conn->state;
5194 struct intel_encoder *encoder =
5195 to_intel_encoder(conn_state->best_encoder);
5196
5197 if (conn_state->crtc != crtc)
5198 continue;
5199
5200 if (encoder->pre_pll_enable)
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005201 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005202 }
5203}
5204
5205static void intel_encoders_pre_enable(struct drm_crtc *crtc,
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005206 struct intel_crtc_state *crtc_state,
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005207 struct drm_atomic_state *old_state)
5208{
5209 struct drm_connector_state *old_conn_state;
5210 struct drm_connector *conn;
5211 int i;
5212
5213 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5214 struct drm_connector_state *conn_state = conn->state;
5215 struct intel_encoder *encoder =
5216 to_intel_encoder(conn_state->best_encoder);
5217
5218 if (conn_state->crtc != crtc)
5219 continue;
5220
5221 if (encoder->pre_enable)
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005222 encoder->pre_enable(encoder, crtc_state, conn_state);
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005223 }
5224}
5225
5226static void intel_encoders_enable(struct drm_crtc *crtc,
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005227 struct intel_crtc_state *crtc_state,
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005228 struct drm_atomic_state *old_state)
5229{
5230 struct drm_connector_state *old_conn_state;
5231 struct drm_connector *conn;
5232 int i;
5233
5234 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5235 struct drm_connector_state *conn_state = conn->state;
5236 struct intel_encoder *encoder =
5237 to_intel_encoder(conn_state->best_encoder);
5238
5239 if (conn_state->crtc != crtc)
5240 continue;
5241
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005242 encoder->enable(encoder, crtc_state, conn_state);
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005243 intel_opregion_notify_encoder(encoder, true);
5244 }
5245}
5246
5247static void intel_encoders_disable(struct drm_crtc *crtc,
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005248 struct intel_crtc_state *old_crtc_state,
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005249 struct drm_atomic_state *old_state)
5250{
5251 struct drm_connector_state *old_conn_state;
5252 struct drm_connector *conn;
5253 int i;
5254
5255 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5256 struct intel_encoder *encoder =
5257 to_intel_encoder(old_conn_state->best_encoder);
5258
5259 if (old_conn_state->crtc != crtc)
5260 continue;
5261
5262 intel_opregion_notify_encoder(encoder, false);
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005263 encoder->disable(encoder, old_crtc_state, old_conn_state);
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005264 }
5265}
5266
5267static void intel_encoders_post_disable(struct drm_crtc *crtc,
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005268 struct intel_crtc_state *old_crtc_state,
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005269 struct drm_atomic_state *old_state)
5270{
5271 struct drm_connector_state *old_conn_state;
5272 struct drm_connector *conn;
5273 int i;
5274
5275 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5276 struct intel_encoder *encoder =
5277 to_intel_encoder(old_conn_state->best_encoder);
5278
5279 if (old_conn_state->crtc != crtc)
5280 continue;
5281
5282 if (encoder->post_disable)
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005283 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005284 }
5285}
5286
5287static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005288 struct intel_crtc_state *old_crtc_state,
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005289 struct drm_atomic_state *old_state)
5290{
5291 struct drm_connector_state *old_conn_state;
5292 struct drm_connector *conn;
5293 int i;
5294
5295 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5296 struct intel_encoder *encoder =
5297 to_intel_encoder(old_conn_state->best_encoder);
5298
5299 if (old_conn_state->crtc != crtc)
5300 continue;
5301
5302 if (encoder->post_pll_disable)
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005303 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
Maarten Lankhorstfb1c98b2016-08-09 17:04:03 +02005304 }
5305}
5306
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005307static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5308 struct drm_atomic_state *old_state)
Jesse Barnesf67a5592011-01-05 10:31:48 -08005309{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005310 struct drm_crtc *crtc = pipe_config->base.crtc;
Jesse Barnesf67a5592011-01-05 10:31:48 -08005311 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005312 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesf67a5592011-01-05 10:31:48 -08005313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08005315
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02005316 if (WARN_ON(intel_crtc->active))
Jesse Barnesf67a5592011-01-05 10:31:48 -08005317 return;
5318
Ville Syrjäläb2c05932016-04-01 21:53:17 +03005319 /*
5320 * Sometimes spurious CPU pipe underruns happen during FDI
5321 * training, at least with VGA+HDMI cloning. Suppress them.
5322 *
5323 * On ILK we get an occasional spurious CPU pipe underruns
5324 * between eDP port A enable and vdd enable. Also PCH port
5325 * enable seems to result in the occasional CPU pipe underrun.
5326 *
5327 * Spurious PCH underruns also occur during PCH enabling.
5328 */
5329 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5330 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005331 if (intel_crtc->config->has_pch_encoder)
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005332 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5333
5334 if (intel_crtc->config->has_pch_encoder)
Daniel Vetterb14b1052014-04-24 23:55:13 +02005335 intel_prepare_shared_dpll(intel_crtc);
5336
Ville Syrjälä37a56502016-06-22 21:57:04 +03005337 if (intel_crtc_has_dp_encoder(intel_crtc->config))
Ramalingam Cfe3cd482015-02-13 15:32:59 +05305338 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter29407aa2014-04-24 23:55:08 +02005339
5340 intel_set_pipe_timings(intel_crtc);
Jani Nikulabc58be62016-03-18 17:05:39 +02005341 intel_set_pipe_src_size(intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +02005342
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005343 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetter29407aa2014-04-24 23:55:08 +02005344 intel_cpu_transcoder_set_m_n(intel_crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005345 &intel_crtc->config->fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02005346 }
5347
5348 ironlake_set_pipeconf(crtc);
5349
Jesse Barnesf67a5592011-01-05 10:31:48 -08005350 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03005351
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005352 intel_encoders_pre_enable(crtc, pipe_config, old_state);
Jesse Barnesf67a5592011-01-05 10:31:48 -08005353
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005354 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02005355 /* Note: FDI PLL enabling _must_ be done before we enable the
5356 * cpu pipes, hence this is separate from all the other fdi/pch
5357 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02005358 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02005359 } else {
5360 assert_fdi_tx_disabled(dev_priv, pipe);
5361 assert_fdi_rx_disabled(dev_priv, pipe);
5362 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08005363
Jesse Barnesb074cec2013-04-25 12:55:02 -07005364 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08005365
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02005366 /*
5367 * On ILK+ LUT must be loaded before the pipe is running but with
5368 * clocks enabled
5369 */
Maarten Lankhorstb95c5322016-03-30 17:16:34 +02005370 intel_color_load_luts(&pipe_config->base);
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02005371
Imre Deak1d5bf5d2016-02-29 22:10:33 +02005372 if (dev_priv->display.initial_watermarks != NULL)
5373 dev_priv->display.initial_watermarks(intel_crtc->config);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005374 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08005375
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005376 if (intel_crtc->config->has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08005377 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005378
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005379 assert_vblank_disabled(crtc);
5380 drm_crtc_vblank_on(crtc);
5381
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005382 intel_encoders_enable(crtc, pipe_config, old_state);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02005383
5384 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02005385 cpt_verify_modeset(dev, intel_crtc->pipe);
Ville Syrjälä37ca8d42015-10-30 19:20:27 +02005386
5387 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5388 if (intel_crtc->config->has_pch_encoder)
5389 intel_wait_for_vblank(dev, pipe);
Ville Syrjäläb2c05932016-04-01 21:53:17 +03005390 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä37ca8d42015-10-30 19:20:27 +02005391 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005392}
5393
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005394/* IPS only exists on ULT machines and is tied to pipe A. */
5395static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5396{
Damien Lespiauf5adf942013-06-24 18:29:34 +01005397 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005398}
5399
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005400static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5401 struct drm_atomic_state *old_state)
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005402{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005403 struct drm_crtc *crtc = pipe_config->base.crtc;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005404 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005405 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorst99d736a2015-06-01 12:50:09 +02005407 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
Jani Nikula4d1de972016-03-18 17:05:42 +02005408 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005409
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02005410 if (WARN_ON(intel_crtc->active))
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005411 return;
5412
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005413 if (intel_crtc->config->has_pch_encoder)
5414 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5415 false);
5416
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005417 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
Imre Deak95a7a2a2016-06-13 16:44:35 +03005418
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02005419 if (intel_crtc->config->shared_dpll)
Daniel Vetterdf8ad702014-06-25 22:02:03 +03005420 intel_enable_shared_dpll(intel_crtc);
5421
Ville Syrjälä37a56502016-06-22 21:57:04 +03005422 if (intel_crtc_has_dp_encoder(intel_crtc->config))
Ramalingam Cfe3cd482015-02-13 15:32:59 +05305423 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter229fca92014-04-24 23:55:09 +02005424
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005425 if (!transcoder_is_dsi(cpu_transcoder))
Jani Nikula4d1de972016-03-18 17:05:42 +02005426 intel_set_pipe_timings(intel_crtc);
5427
Jani Nikulabc58be62016-03-18 17:05:39 +02005428 intel_set_pipe_src_size(intel_crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +02005429
Jani Nikula4d1de972016-03-18 17:05:42 +02005430 if (cpu_transcoder != TRANSCODER_EDP &&
5431 !transcoder_is_dsi(cpu_transcoder)) {
5432 I915_WRITE(PIPE_MULT(cpu_transcoder),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005433 intel_crtc->config->pixel_multiplier - 1);
Clint Taylorebb69c92014-09-30 10:30:22 -07005434 }
5435
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005436 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetter229fca92014-04-24 23:55:09 +02005437 intel_cpu_transcoder_set_m_n(intel_crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005438 &intel_crtc->config->fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02005439 }
5440
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005441 if (!transcoder_is_dsi(cpu_transcoder))
Jani Nikula4d1de972016-03-18 17:05:42 +02005442 haswell_set_pipeconf(crtc);
5443
Jani Nikula391bf042016-03-18 17:05:40 +02005444 haswell_set_pipemisc(crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +02005445
Maarten Lankhorstb95c5322016-03-30 17:16:34 +02005446 intel_color_set_csc(&pipe_config->base);
Daniel Vetter229fca92014-04-24 23:55:09 +02005447
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005448 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03005449
Daniel Vetter6b698512015-11-28 11:05:39 +01005450 if (intel_crtc->config->has_pch_encoder)
5451 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5452 else
5453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5454
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005455 intel_encoders_pre_enable(crtc, pipe_config, old_state);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005456
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005457 if (intel_crtc->config->has_pch_encoder)
Imre Deak4fe94672014-06-25 22:01:49 +03005458 dev_priv->display.fdi_link_train(crtc);
Imre Deak4fe94672014-06-25 22:01:49 +03005459
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005460 if (!transcoder_is_dsi(cpu_transcoder))
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305461 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005462
Rodrigo Vivi1c132b42015-09-02 15:19:26 -07005463 if (INTEL_INFO(dev)->gen >= 9)
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02005464 skylake_pfit_enable(intel_crtc);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005465 else
Rodrigo Vivi1c132b42015-09-02 15:19:26 -07005466 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005467
5468 /*
5469 * On ILK+ LUT must be loaded before the pipe is running but with
5470 * clocks enabled
5471 */
Maarten Lankhorstb95c5322016-03-30 17:16:34 +02005472 intel_color_load_luts(&pipe_config->base);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005473
Paulo Zanoni1f544382012-10-24 11:32:00 -02005474 intel_ddi_set_pipe_settings(crtc);
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005475 if (!transcoder_is_dsi(cpu_transcoder))
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305476 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005477
Imre Deak1d5bf5d2016-02-29 22:10:33 +02005478 if (dev_priv->display.initial_watermarks != NULL)
5479 dev_priv->display.initial_watermarks(pipe_config);
5480 else
5481 intel_update_watermarks(crtc);
Jani Nikula4d1de972016-03-18 17:05:42 +02005482
5483 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005484 if (!transcoder_is_dsi(cpu_transcoder))
Jani Nikula4d1de972016-03-18 17:05:42 +02005485 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005486
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005487 if (intel_crtc->config->has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02005488 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005489
Jani Nikulaa65347b2015-11-27 12:21:46 +02005490 if (intel_crtc->config->dp_encoder_is_mst)
Dave Airlie0e32b392014-05-02 14:02:48 +10005491 intel_ddi_set_vc_payload_alloc(crtc, true);
5492
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005493 assert_vblank_disabled(crtc);
5494 drm_crtc_vblank_on(crtc);
5495
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005496 intel_encoders_enable(crtc, pipe_config, old_state);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005497
Daniel Vetter6b698512015-11-28 11:05:39 +01005498 if (intel_crtc->config->has_pch_encoder) {
5499 intel_wait_for_vblank(dev, pipe);
5500 intel_wait_for_vblank(dev, pipe);
5501 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005502 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5503 true);
Daniel Vetter6b698512015-11-28 11:05:39 +01005504 }
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005505
Paulo Zanonie4916942013-09-20 16:21:19 -03005506 /* If we change the relative order between pipe/planes enabling, we need
5507 * to change the workaround. */
Maarten Lankhorst99d736a2015-06-01 12:50:09 +02005508 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5509 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5510 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5511 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5512 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005513}
5514
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005515static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005516{
5517 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005518 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005519 int pipe = crtc->pipe;
5520
5521 /* To avoid upsetting the power well on haswell only disable the pfit if
5522 * it's in use. The hw state code will make sure we get this right. */
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005523 if (force || crtc->config->pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005524 I915_WRITE(PF_CTL(pipe), 0);
5525 I915_WRITE(PF_WIN_POS(pipe), 0);
5526 I915_WRITE(PF_WIN_SZ(pipe), 0);
5527 }
5528}
5529
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005530static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5531 struct drm_atomic_state *old_state)
Jesse Barnes6be4a602010-09-10 10:26:01 -07005532{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005533 struct drm_crtc *crtc = old_crtc_state->base.crtc;
Jesse Barnes6be4a602010-09-10 10:26:01 -07005534 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005535 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5537 int pipe = intel_crtc->pipe;
Jesse Barnes6be4a602010-09-10 10:26:01 -07005538
Ville Syrjäläb2c05932016-04-01 21:53:17 +03005539 /*
5540 * Sometimes spurious CPU pipe underruns happen when the
5541 * pipe is already disabled, but FDI RX/TX is still enabled.
5542 * Happens at least with VGA+HDMI cloning. Suppress them.
5543 */
5544 if (intel_crtc->config->has_pch_encoder) {
5545 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä37ca8d42015-10-30 19:20:27 +02005546 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjäläb2c05932016-04-01 21:53:17 +03005547 }
Ville Syrjälä37ca8d42015-10-30 19:20:27 +02005548
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005549 intel_encoders_disable(crtc, old_crtc_state, old_state);
Daniel Vetterea9d7582012-07-10 10:42:52 +02005550
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005551 drm_crtc_vblank_off(crtc);
5552 assert_vblank_disabled(crtc);
5553
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005554 intel_disable_pipe(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005555
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005556 ironlake_pfit_disable(intel_crtc, false);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005557
Ville Syrjäläb2c05932016-04-01 21:53:17 +03005558 if (intel_crtc->config->has_pch_encoder)
Ville Syrjälä5a74f702015-05-05 17:17:38 +03005559 ironlake_fdi_disable(crtc);
5560
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005561 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005562
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005563 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetterd925c592013-06-05 13:34:04 +02005564 ironlake_disable_pch_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005565
Daniel Vetterd925c592013-06-05 13:34:04 +02005566 if (HAS_PCH_CPT(dev)) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005567 i915_reg_t reg;
5568 u32 temp;
5569
Daniel Vetterd925c592013-06-05 13:34:04 +02005570 /* disable TRANS_DP_CTL */
5571 reg = TRANS_DP_CTL(pipe);
5572 temp = I915_READ(reg);
5573 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5574 TRANS_DP_PORT_SEL_MASK);
5575 temp |= TRANS_DP_PORT_SEL_NONE;
5576 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005577
Daniel Vetterd925c592013-06-05 13:34:04 +02005578 /* disable DPLL_SEL */
5579 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02005580 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02005581 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005582 }
Daniel Vetterd925c592013-06-05 13:34:04 +02005583
Daniel Vetterd925c592013-06-05 13:34:04 +02005584 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005585 }
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005586
Ville Syrjäläb2c05932016-04-01 21:53:17 +03005587 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005588 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005589}
5590
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005591static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5592 struct drm_atomic_state *old_state)
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005593{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02005594 struct drm_crtc *crtc = old_crtc_state->base.crtc;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005595 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005596 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005598 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005599
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005600 if (intel_crtc->config->has_pch_encoder)
5601 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5602 false);
5603
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005604 intel_encoders_disable(crtc, old_crtc_state, old_state);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005605
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005606 drm_crtc_vblank_off(crtc);
5607 assert_vblank_disabled(crtc);
5608
Jani Nikula4d1de972016-03-18 17:05:42 +02005609 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005610 if (!transcoder_is_dsi(cpu_transcoder))
Jani Nikula4d1de972016-03-18 17:05:42 +02005611 intel_disable_pipe(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005612
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005613 if (intel_crtc->config->dp_encoder_is_mst)
Ville Syrjäläa4bf2142014-08-18 21:27:34 +03005614 intel_ddi_set_vc_payload_alloc(crtc, false);
5615
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005616 if (!transcoder_is_dsi(cpu_transcoder))
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305617 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005618
Rodrigo Vivi1c132b42015-09-02 15:19:26 -07005619 if (INTEL_INFO(dev)->gen >= 9)
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02005620 skylake_scaler_disable(intel_crtc);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005621 else
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005622 ironlake_pfit_disable(intel_crtc, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005623
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03005624 if (!transcoder_is_dsi(cpu_transcoder))
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305625 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005626
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02005627 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005628
Maarten Lankhorstb7076542016-08-23 16:18:08 +02005629 if (old_crtc_state->has_pch_encoder)
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005630 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5631 true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005632}
5633
Jesse Barnes2dd24552013-04-25 12:55:01 -07005634static void i9xx_pfit_enable(struct intel_crtc *crtc)
5635{
5636 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01005637 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005638 struct intel_crtc_state *pipe_config = crtc->config;
Jesse Barnes2dd24552013-04-25 12:55:01 -07005639
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02005640 if (!pipe_config->gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07005641 return;
5642
Daniel Vetterc0b03412013-05-28 12:05:54 +02005643 /*
5644 * The panel fitter should only be adjusted whilst the pipe is disabled,
5645 * according to register description and PRM.
5646 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07005647 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5648 assert_pipe_disabled(dev_priv, crtc->pipe);
5649
Jesse Barnesb074cec2013-04-25 12:55:02 -07005650 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5651 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02005652
5653 /* Border color in case we don't scale up to the full screen. Black by
5654 * default, change to something else for debugging. */
5655 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07005656}
5657
Dave Airlied05410f2014-06-05 13:22:59 +10005658static enum intel_display_power_domain port_to_power_domain(enum port port)
5659{
5660 switch (port) {
5661 case PORT_A:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005662 return POWER_DOMAIN_PORT_DDI_A_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005663 case PORT_B:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005664 return POWER_DOMAIN_PORT_DDI_B_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005665 case PORT_C:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005666 return POWER_DOMAIN_PORT_DDI_C_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005667 case PORT_D:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005668 return POWER_DOMAIN_PORT_DDI_D_LANES;
Xiong Zhangd8e19f92015-08-13 18:00:12 +08005669 case PORT_E:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005670 return POWER_DOMAIN_PORT_DDI_E_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005671 default:
Imre Deakb9fec162015-11-18 15:57:25 +02005672 MISSING_CASE(port);
Dave Airlied05410f2014-06-05 13:22:59 +10005673 return POWER_DOMAIN_PORT_OTHER;
5674 }
5675}
5676
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005677static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5678{
5679 switch (port) {
5680 case PORT_A:
5681 return POWER_DOMAIN_AUX_A;
5682 case PORT_B:
5683 return POWER_DOMAIN_AUX_B;
5684 case PORT_C:
5685 return POWER_DOMAIN_AUX_C;
5686 case PORT_D:
5687 return POWER_DOMAIN_AUX_D;
5688 case PORT_E:
5689 /* FIXME: Check VBT for actual wiring of PORT E */
5690 return POWER_DOMAIN_AUX_D;
5691 default:
Imre Deakb9fec162015-11-18 15:57:25 +02005692 MISSING_CASE(port);
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005693 return POWER_DOMAIN_AUX_A;
5694 }
5695}
5696
Imre Deak319be8a2014-03-04 19:22:57 +02005697enum intel_display_power_domain
5698intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02005699{
Imre Deak319be8a2014-03-04 19:22:57 +02005700 struct drm_device *dev = intel_encoder->base.dev;
5701 struct intel_digital_port *intel_dig_port;
5702
5703 switch (intel_encoder->type) {
5704 case INTEL_OUTPUT_UNKNOWN:
5705 /* Only DDI platforms should ever use this output type */
5706 WARN_ON_ONCE(!HAS_DDI(dev));
Ville Syrjäläcca05022016-06-22 21:57:06 +03005707 case INTEL_OUTPUT_DP:
Imre Deak319be8a2014-03-04 19:22:57 +02005708 case INTEL_OUTPUT_HDMI:
5709 case INTEL_OUTPUT_EDP:
5710 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10005711 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10005712 case INTEL_OUTPUT_DP_MST:
5713 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5714 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02005715 case INTEL_OUTPUT_ANALOG:
5716 return POWER_DOMAIN_PORT_CRT;
5717 case INTEL_OUTPUT_DSI:
5718 return POWER_DOMAIN_PORT_DSI;
5719 default:
5720 return POWER_DOMAIN_PORT_OTHER;
5721 }
5722}
5723
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005724enum intel_display_power_domain
5725intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5726{
5727 struct drm_device *dev = intel_encoder->base.dev;
5728 struct intel_digital_port *intel_dig_port;
5729
5730 switch (intel_encoder->type) {
5731 case INTEL_OUTPUT_UNKNOWN:
Imre Deak651174a2015-11-18 15:57:24 +02005732 case INTEL_OUTPUT_HDMI:
5733 /*
5734 * Only DDI platforms should ever use these output types.
5735 * We can get here after the HDMI detect code has already set
5736 * the type of the shared encoder. Since we can't be sure
5737 * what's the status of the given connectors, play safe and
5738 * run the DP detection too.
5739 */
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005740 WARN_ON_ONCE(!HAS_DDI(dev));
Ville Syrjäläcca05022016-06-22 21:57:06 +03005741 case INTEL_OUTPUT_DP:
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005742 case INTEL_OUTPUT_EDP:
5743 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5744 return port_to_aux_power_domain(intel_dig_port->port);
5745 case INTEL_OUTPUT_DP_MST:
5746 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5747 return port_to_aux_power_domain(intel_dig_port->port);
5748 default:
Imre Deakb9fec162015-11-18 15:57:25 +02005749 MISSING_CASE(intel_encoder->type);
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005750 return POWER_DOMAIN_AUX_A;
5751 }
5752}
5753
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005754static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5755 struct intel_crtc_state *crtc_state)
Imre Deak319be8a2014-03-04 19:22:57 +02005756{
5757 struct drm_device *dev = crtc->dev;
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005758 struct drm_encoder *encoder;
Imre Deak319be8a2014-03-04 19:22:57 +02005759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02005761 unsigned long mask;
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005762 enum transcoder transcoder = crtc_state->cpu_transcoder;
Imre Deak77d22dc2014-03-05 16:20:52 +02005763
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005764 if (!crtc_state->base.active)
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005765 return 0;
5766
Imre Deak77d22dc2014-03-05 16:20:52 +02005767 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5768 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005769 if (crtc_state->pch_pfit.enabled ||
5770 crtc_state->pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02005771 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5772
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005773 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5774 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5775
Imre Deak319be8a2014-03-04 19:22:57 +02005776 mask |= BIT(intel_display_port_power_domain(intel_encoder));
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005777 }
Imre Deak319be8a2014-03-04 19:22:57 +02005778
Maarten Lankhorst15e7ec22016-03-14 09:27:54 +01005779 if (crtc_state->shared_dpll)
5780 mask |= BIT(POWER_DOMAIN_PLLS);
5781
Imre Deak77d22dc2014-03-05 16:20:52 +02005782 return mask;
5783}
5784
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005785static unsigned long
5786modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5787 struct intel_crtc_state *crtc_state)
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005788{
Chris Wilsonfac5e232016-07-04 11:34:36 +01005789 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791 enum intel_display_power_domain domain;
Daniel Vetter5a21b662016-05-24 17:13:53 +02005792 unsigned long domains, new_domains, old_domains;
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005793
5794 old_domains = intel_crtc->enabled_power_domains;
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +01005795 intel_crtc->enabled_power_domains = new_domains =
5796 get_crtc_power_domains(crtc, crtc_state);
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005797
Daniel Vetter5a21b662016-05-24 17:13:53 +02005798 domains = new_domains & ~old_domains;
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005799
5800 for_each_power_domain(domain, domains)
5801 intel_display_power_get(dev_priv, domain);
5802
Daniel Vetter5a21b662016-05-24 17:13:53 +02005803 return old_domains & ~new_domains;
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005804}
5805
5806static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5807 unsigned long domains)
5808{
5809 enum intel_display_power_domain domain;
5810
5811 for_each_power_domain(domain, domains)
5812 intel_display_power_put(dev_priv, domain);
5813}
5814
Mika Kaholaadafdc62015-08-18 14:36:59 +03005815static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5816{
5817 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5818
5819 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5820 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5821 return max_cdclk_freq;
5822 else if (IS_CHERRYVIEW(dev_priv))
5823 return max_cdclk_freq*95/100;
5824 else if (INTEL_INFO(dev_priv)->gen < 4)
5825 return 2*max_cdclk_freq*90/100;
5826 else
5827 return max_cdclk_freq*90/100;
5828}
5829
Ville Syrjäläb2045352016-05-13 23:41:27 +03005830static int skl_calc_cdclk(int max_pixclk, int vco);
5831
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005832static void intel_update_max_cdclk(struct drm_device *dev)
5833{
Chris Wilsonfac5e232016-07-04 11:34:36 +01005834 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005835
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07005836 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005837 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
Ville Syrjäläb2045352016-05-13 23:41:27 +03005838 int max_cdclk, vco;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005839
Ville Syrjäläb2045352016-05-13 23:41:27 +03005840 vco = dev_priv->skl_preferred_vco_freq;
Ville Syrjälä63911d72016-05-13 23:41:32 +03005841 WARN_ON(vco != 8100000 && vco != 8640000);
Ville Syrjäläb2045352016-05-13 23:41:27 +03005842
5843 /*
5844 * Use the lower (vco 8640) cdclk values as a
5845 * first guess. skl_calc_cdclk() will correct it
5846 * if the preferred vco is 8100 instead.
5847 */
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005848 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03005849 max_cdclk = 617143;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005850 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
Ville Syrjäläb2045352016-05-13 23:41:27 +03005851 max_cdclk = 540000;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005852 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
Ville Syrjäläb2045352016-05-13 23:41:27 +03005853 max_cdclk = 432000;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005854 else
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03005855 max_cdclk = 308571;
Ville Syrjäläb2045352016-05-13 23:41:27 +03005856
5857 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
Matt Roper281c1142016-04-05 14:37:19 -07005858 } else if (IS_BROXTON(dev)) {
5859 dev_priv->max_cdclk_freq = 624000;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005860 } else if (IS_BROADWELL(dev)) {
5861 /*
5862 * FIXME with extra cooling we can allow
5863 * 540 MHz for ULX and 675 Mhz for ULT.
5864 * How can we know if extra cooling is
5865 * available? PCI ID, VTB, something else?
5866 */
5867 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5868 dev_priv->max_cdclk_freq = 450000;
5869 else if (IS_BDW_ULX(dev))
5870 dev_priv->max_cdclk_freq = 450000;
5871 else if (IS_BDW_ULT(dev))
5872 dev_priv->max_cdclk_freq = 540000;
5873 else
5874 dev_priv->max_cdclk_freq = 675000;
Mika Kahola0904dea2015-06-12 10:11:32 +03005875 } else if (IS_CHERRYVIEW(dev)) {
5876 dev_priv->max_cdclk_freq = 320000;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005877 } else if (IS_VALLEYVIEW(dev)) {
5878 dev_priv->max_cdclk_freq = 400000;
5879 } else {
5880 /* otherwise assume cdclk is fixed */
5881 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5882 }
5883
Mika Kaholaadafdc62015-08-18 14:36:59 +03005884 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5885
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005886 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5887 dev_priv->max_cdclk_freq);
Mika Kaholaadafdc62015-08-18 14:36:59 +03005888
5889 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5890 dev_priv->max_dotclk_freq);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005891}
5892
5893static void intel_update_cdclk(struct drm_device *dev)
5894{
Chris Wilsonfac5e232016-07-04 11:34:36 +01005895 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005896
5897 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Ville Syrjälä2f2a1212016-05-13 23:41:25 +03005898
Ville Syrjälä83d7c812016-05-13 23:41:35 +03005899 if (INTEL_GEN(dev_priv) >= 9)
Ville Syrjälä709e05c2016-05-13 23:41:33 +03005900 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5901 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5902 dev_priv->cdclk_pll.ref);
Ville Syrjälä2f2a1212016-05-13 23:41:25 +03005903 else
5904 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5905 dev_priv->cdclk_freq);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005906
5907 /*
Ville Syrjäläb5d99ff2016-04-26 19:46:34 +03005908 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5909 * Programmng [sic] note: bit[9:2] should be programmed to the number
5910 * of cdclk that generates 4MHz reference clock freq which is used to
5911 * generate GMBus clock. This will vary with the cdclk freq.
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005912 */
Ville Syrjäläb5d99ff2016-04-26 19:46:34 +03005913 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005914 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005915}
5916
Ville Syrjälä92891e42016-05-11 22:44:45 +03005917/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5918static int skl_cdclk_decimal(int cdclk)
5919{
5920 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5921}
5922
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005923static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5924{
5925 int ratio;
5926
5927 if (cdclk == dev_priv->cdclk_pll.ref)
5928 return 0;
5929
5930 switch (cdclk) {
5931 default:
5932 MISSING_CASE(cdclk);
5933 case 144000:
5934 case 288000:
5935 case 384000:
5936 case 576000:
5937 ratio = 60;
5938 break;
5939 case 624000:
5940 ratio = 65;
5941 break;
5942 }
5943
5944 return dev_priv->cdclk_pll.ref * ratio;
5945}
5946
Ville Syrjälä2b730012016-05-13 23:41:34 +03005947static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5948{
5949 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5950
5951 /* Timeout 200us */
Chris Wilson95cac282016-06-30 15:33:03 +01005952 if (intel_wait_for_register(dev_priv,
5953 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5954 1))
Ville Syrjälä2b730012016-05-13 23:41:34 +03005955 DRM_ERROR("timeout waiting for DE PLL unlock\n");
Ville Syrjälä83d7c812016-05-13 23:41:35 +03005956
5957 dev_priv->cdclk_pll.vco = 0;
Ville Syrjälä2b730012016-05-13 23:41:34 +03005958}
5959
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005960static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
Ville Syrjälä2b730012016-05-13 23:41:34 +03005961{
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005962 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
Ville Syrjälä2b730012016-05-13 23:41:34 +03005963 u32 val;
5964
5965 val = I915_READ(BXT_DE_PLL_CTL);
5966 val &= ~BXT_DE_PLL_RATIO_MASK;
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005967 val |= BXT_DE_PLL_RATIO(ratio);
Ville Syrjälä2b730012016-05-13 23:41:34 +03005968 I915_WRITE(BXT_DE_PLL_CTL, val);
5969
5970 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5971
5972 /* Timeout 200us */
Chris Wilsone084e1b2016-06-30 15:33:04 +01005973 if (intel_wait_for_register(dev_priv,
5974 BXT_DE_PLL_ENABLE,
5975 BXT_DE_PLL_LOCK,
5976 BXT_DE_PLL_LOCK,
5977 1))
Ville Syrjälä2b730012016-05-13 23:41:34 +03005978 DRM_ERROR("timeout waiting for DE PLL lock\n");
Ville Syrjälä83d7c812016-05-13 23:41:35 +03005979
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005980 dev_priv->cdclk_pll.vco = vco;
Ville Syrjälä2b730012016-05-13 23:41:34 +03005981}
5982
Imre Deak324513c2016-06-13 16:44:36 +03005983static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305984{
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005985 u32 val, divider;
5986 int vco, ret;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305987
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005988 vco = bxt_de_pll_vco(dev_priv, cdclk);
5989
5990 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5991
5992 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5993 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5994 case 8:
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305995 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305996 break;
Ville Syrjälä5f199df2016-05-13 23:41:38 +03005997 case 4:
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305998 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305999 break;
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006000 case 3:
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306001 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306002 break;
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006003 case 2:
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306004 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306005 break;
6006 default:
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006007 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6008 WARN_ON(vco != 0);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306009
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006010 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6011 break;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306012 }
6013
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306014 /* Inform power controller of upcoming frequency change */
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006015 mutex_lock(&dev_priv->rps.hw_lock);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306016 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6017 0x80000000);
6018 mutex_unlock(&dev_priv->rps.hw_lock);
6019
6020 if (ret) {
6021 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
Ville Syrjälä9ef56152016-05-11 22:44:49 +03006022 ret, cdclk);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306023 return;
6024 }
6025
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006026 if (dev_priv->cdclk_pll.vco != 0 &&
6027 dev_priv->cdclk_pll.vco != vco)
Ville Syrjälä2b730012016-05-13 23:41:34 +03006028 bxt_de_pll_disable(dev_priv);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306029
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006030 if (dev_priv->cdclk_pll.vco != vco)
6031 bxt_de_pll_enable(dev_priv, vco);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306032
Ville Syrjälä5f199df2016-05-13 23:41:38 +03006033 val = divider | skl_cdclk_decimal(cdclk);
6034 /*
6035 * FIXME if only the cd2x divider needs changing, it could be done
6036 * without shutting off the pipe (if only one pipe is active).
6037 */
6038 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6039 /*
6040 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6041 * enable otherwise.
6042 */
6043 if (cdclk >= 500000)
6044 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6045 I915_WRITE(CDCLK_CTL, val);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306046
6047 mutex_lock(&dev_priv->rps.hw_lock);
6048 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
Ville Syrjälä9ef56152016-05-11 22:44:49 +03006049 DIV_ROUND_UP(cdclk, 25000));
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306050 mutex_unlock(&dev_priv->rps.hw_lock);
6051
6052 if (ret) {
6053 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
Ville Syrjälä9ef56152016-05-11 22:44:49 +03006054 ret, cdclk);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306055 return;
6056 }
6057
Chris Wilson91c8a322016-07-05 10:40:23 +01006058 intel_update_cdclk(&dev_priv->drm);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306059}
6060
Imre Deakd66a2192016-05-24 15:38:33 +03006061static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306062{
Imre Deakd66a2192016-05-24 15:38:33 +03006063 u32 cdctl, expected;
6064
Chris Wilson91c8a322016-07-05 10:40:23 +01006065 intel_update_cdclk(&dev_priv->drm);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306066
Imre Deakd66a2192016-05-24 15:38:33 +03006067 if (dev_priv->cdclk_pll.vco == 0 ||
6068 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6069 goto sanitize;
6070
6071 /* DPLL okay; verify the cdclock
6072 *
6073 * Some BIOS versions leave an incorrect decimal frequency value and
6074 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6075 * so sanitize this register.
6076 */
6077 cdctl = I915_READ(CDCLK_CTL);
6078 /*
6079 * Let's ignore the pipe field, since BIOS could have configured the
6080 * dividers both synching to an active pipe, or asynchronously
6081 * (PIPE_NONE).
6082 */
6083 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6084
6085 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6086 skl_cdclk_decimal(dev_priv->cdclk_freq);
6087 /*
6088 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6089 * enable otherwise.
6090 */
6091 if (dev_priv->cdclk_freq >= 500000)
6092 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6093
6094 if (cdctl == expected)
6095 /* All well; nothing to sanitize */
6096 return;
6097
6098sanitize:
6099 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6100
6101 /* force cdclk programming */
6102 dev_priv->cdclk_freq = 0;
6103
6104 /* force full PLL disable + enable */
6105 dev_priv->cdclk_pll.vco = -1;
6106}
6107
Imre Deak324513c2016-06-13 16:44:36 +03006108void bxt_init_cdclk(struct drm_i915_private *dev_priv)
Imre Deakd66a2192016-05-24 15:38:33 +03006109{
6110 bxt_sanitize_cdclk(dev_priv);
6111
6112 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
Ville Syrjälä089c6fd2016-05-13 23:41:36 +03006113 return;
Imre Deakc2e001e2016-04-01 16:02:43 +03006114
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306115 /*
6116 * FIXME:
6117 * - The initial CDCLK needs to be read from VBT.
6118 * Need to make this change after VBT has changes for BXT.
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306119 */
Imre Deak324513c2016-06-13 16:44:36 +03006120 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306121}
6122
Imre Deak324513c2016-06-13 16:44:36 +03006123void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306124{
Imre Deak324513c2016-06-13 16:44:36 +03006125 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306126}
6127
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006128static int skl_calc_cdclk(int max_pixclk, int vco)
6129{
Ville Syrjälä63911d72016-05-13 23:41:32 +03006130 if (vco == 8640000) {
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006131 if (max_pixclk > 540000)
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03006132 return 617143;
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006133 else if (max_pixclk > 432000)
6134 return 540000;
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03006135 else if (max_pixclk > 308571)
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006136 return 432000;
6137 else
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03006138 return 308571;
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006139 } else {
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006140 if (max_pixclk > 540000)
6141 return 675000;
6142 else if (max_pixclk > 450000)
6143 return 540000;
6144 else if (max_pixclk > 337500)
6145 return 450000;
6146 else
6147 return 337500;
6148 }
6149}
6150
Ville Syrjäläea617912016-05-13 23:41:24 +03006151static void
6152skl_dpll0_update(struct drm_i915_private *dev_priv)
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006153{
Ville Syrjäläea617912016-05-13 23:41:24 +03006154 u32 val;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006155
Ville Syrjälä709e05c2016-05-13 23:41:33 +03006156 dev_priv->cdclk_pll.ref = 24000;
Imre Deak1c3f7702016-05-24 15:38:32 +03006157 dev_priv->cdclk_pll.vco = 0;
Ville Syrjälä709e05c2016-05-13 23:41:33 +03006158
Ville Syrjäläea617912016-05-13 23:41:24 +03006159 val = I915_READ(LCPLL1_CTL);
Imre Deak1c3f7702016-05-24 15:38:32 +03006160 if ((val & LCPLL_PLL_ENABLE) == 0)
Ville Syrjäläea617912016-05-13 23:41:24 +03006161 return;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006162
Imre Deak1c3f7702016-05-24 15:38:32 +03006163 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6164 return;
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006165
Ville Syrjäläea617912016-05-13 23:41:24 +03006166 val = I915_READ(DPLL_CTRL1);
6167
Imre Deak1c3f7702016-05-24 15:38:32 +03006168 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6169 DPLL_CTRL1_SSC(SKL_DPLL0) |
6170 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6171 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6172 return;
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006173
Ville Syrjäläea617912016-05-13 23:41:24 +03006174 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6175 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6176 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6177 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6178 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
Ville Syrjälä63911d72016-05-13 23:41:32 +03006179 dev_priv->cdclk_pll.vco = 8100000;
Ville Syrjäläea617912016-05-13 23:41:24 +03006180 break;
6181 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6182 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
Ville Syrjälä63911d72016-05-13 23:41:32 +03006183 dev_priv->cdclk_pll.vco = 8640000;
Ville Syrjäläea617912016-05-13 23:41:24 +03006184 break;
6185 default:
6186 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
Ville Syrjäläea617912016-05-13 23:41:24 +03006187 break;
6188 }
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006189}
6190
Ville Syrjäläb2045352016-05-13 23:41:27 +03006191void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6192{
6193 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6194
6195 dev_priv->skl_preferred_vco_freq = vco;
6196
6197 if (changed)
Chris Wilson91c8a322016-07-05 10:40:23 +01006198 intel_update_max_cdclk(&dev_priv->drm);
Ville Syrjäläb2045352016-05-13 23:41:27 +03006199}
6200
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006201static void
Ville Syrjälä3861fc62016-05-11 22:44:50 +03006202skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006203{
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006204 int min_cdclk = skl_calc_cdclk(0, vco);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006205 u32 val;
6206
Ville Syrjälä63911d72016-05-13 23:41:32 +03006207 WARN_ON(vco != 8100000 && vco != 8640000);
Ville Syrjäläb2045352016-05-13 23:41:27 +03006208
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006209 /* select the minimum CDCLK before enabling DPLL 0 */
Ville Syrjälä9ef56152016-05-11 22:44:49 +03006210 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006211 I915_WRITE(CDCLK_CTL, val);
6212 POSTING_READ(CDCLK_CTL);
6213
6214 /*
6215 * We always enable DPLL0 with the lowest link rate possible, but still
6216 * taking into account the VCO required to operate the eDP panel at the
6217 * desired frequency. The usual DP link rates operate with a VCO of
6218 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6219 * The modeset code is responsible for the selection of the exact link
6220 * rate later on, with the constraint of choosing a frequency that
Ville Syrjäläa8ca4932016-05-13 23:41:23 +03006221 * works with vco.
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006222 */
6223 val = I915_READ(DPLL_CTRL1);
6224
6225 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6226 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6227 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
Ville Syrjälä63911d72016-05-13 23:41:32 +03006228 if (vco == 8640000)
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006229 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6230 SKL_DPLL0);
6231 else
6232 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6233 SKL_DPLL0);
6234
6235 I915_WRITE(DPLL_CTRL1, val);
6236 POSTING_READ(DPLL_CTRL1);
6237
6238 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6239
Chris Wilsone24ca052016-06-30 15:33:05 +01006240 if (intel_wait_for_register(dev_priv,
6241 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6242 5))
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006243 DRM_ERROR("DPLL0 not locked\n");
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006244
Ville Syrjälä63911d72016-05-13 23:41:32 +03006245 dev_priv->cdclk_pll.vco = vco;
Ville Syrjäläb2045352016-05-13 23:41:27 +03006246
6247 /* We'll want to keep using the current vco from now on. */
6248 skl_set_preferred_cdclk_vco(dev_priv, vco);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006249}
6250
Ville Syrjälä430e05d2016-05-11 22:44:47 +03006251static void
6252skl_dpll0_disable(struct drm_i915_private *dev_priv)
6253{
6254 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
Chris Wilson8ad32a052016-06-30 15:33:06 +01006255 if (intel_wait_for_register(dev_priv,
6256 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6257 1))
Ville Syrjälä430e05d2016-05-11 22:44:47 +03006258 DRM_ERROR("Couldn't disable DPLL0\n");
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006259
Ville Syrjälä63911d72016-05-13 23:41:32 +03006260 dev_priv->cdclk_pll.vco = 0;
Ville Syrjälä430e05d2016-05-11 22:44:47 +03006261}
6262
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006263static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6264{
6265 int ret;
6266 u32 val;
6267
6268 /* inform PCU we want to change CDCLK */
6269 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6270 mutex_lock(&dev_priv->rps.hw_lock);
6271 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6272 mutex_unlock(&dev_priv->rps.hw_lock);
6273
6274 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6275}
6276
6277static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6278{
Ville Syrjälä3b2c1712016-07-13 16:32:03 +03006279 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006280}
6281
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006282static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006283{
Chris Wilson91c8a322016-07-05 10:40:23 +01006284 struct drm_device *dev = &dev_priv->drm;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006285 u32 freq_select, pcu_ack;
6286
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006287 WARN_ON((cdclk == 24000) != (vco == 0));
6288
Ville Syrjälä63911d72016-05-13 23:41:32 +03006289 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006290
6291 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6292 DRM_ERROR("failed to inform PCU about cdclk change\n");
6293 return;
6294 }
6295
6296 /* set CDCLK_CTL */
Ville Syrjälä9ef56152016-05-11 22:44:49 +03006297 switch (cdclk) {
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006298 case 450000:
6299 case 432000:
6300 freq_select = CDCLK_FREQ_450_432;
6301 pcu_ack = 1;
6302 break;
6303 case 540000:
6304 freq_select = CDCLK_FREQ_540;
6305 pcu_ack = 2;
6306 break;
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03006307 case 308571:
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006308 case 337500:
6309 default:
6310 freq_select = CDCLK_FREQ_337_308;
6311 pcu_ack = 0;
6312 break;
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03006313 case 617143:
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006314 case 675000:
6315 freq_select = CDCLK_FREQ_675_617;
6316 pcu_ack = 3;
6317 break;
6318 }
6319
Ville Syrjälä63911d72016-05-13 23:41:32 +03006320 if (dev_priv->cdclk_pll.vco != 0 &&
6321 dev_priv->cdclk_pll.vco != vco)
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006322 skl_dpll0_disable(dev_priv);
6323
Ville Syrjälä63911d72016-05-13 23:41:32 +03006324 if (dev_priv->cdclk_pll.vco != vco)
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006325 skl_dpll0_enable(dev_priv, vco);
6326
Ville Syrjälä9ef56152016-05-11 22:44:49 +03006327 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006328 POSTING_READ(CDCLK_CTL);
6329
6330 /* inform PCU of the change */
6331 mutex_lock(&dev_priv->rps.hw_lock);
6332 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6333 mutex_unlock(&dev_priv->rps.hw_lock);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01006334
6335 intel_update_cdclk(dev);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006336}
6337
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006338static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6339
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006340void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6341{
Ville Syrjälä709e05c2016-05-13 23:41:33 +03006342 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006343}
6344
6345void skl_init_cdclk(struct drm_i915_private *dev_priv)
6346{
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006347 int cdclk, vco;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006348
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006349 skl_sanitize_cdclk(dev_priv);
6350
Ville Syrjälä63911d72016-05-13 23:41:32 +03006351 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006352 /*
6353 * Use the current vco as our initial
6354 * guess as to what the preferred vco is.
6355 */
6356 if (dev_priv->skl_preferred_vco_freq == 0)
6357 skl_set_preferred_cdclk_vco(dev_priv,
Ville Syrjälä63911d72016-05-13 23:41:32 +03006358 dev_priv->cdclk_pll.vco);
Ville Syrjälä70c2c182016-05-13 23:41:30 +03006359 return;
Ville Syrjälä1cd593e2016-05-13 23:41:26 +03006360 }
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006361
Ville Syrjälä70c2c182016-05-13 23:41:30 +03006362 vco = dev_priv->skl_preferred_vco_freq;
6363 if (vco == 0)
Ville Syrjälä63911d72016-05-13 23:41:32 +03006364 vco = 8100000;
Ville Syrjälä70c2c182016-05-13 23:41:30 +03006365 cdclk = skl_calc_cdclk(0, vco);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006366
Ville Syrjälä70c2c182016-05-13 23:41:30 +03006367 skl_set_cdclk(dev_priv, cdclk, vco);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006368}
6369
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006370static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
Shobhit Kumarc73666f2015-10-20 18:13:12 +05306371{
Ville Syrjälä09492492016-05-13 23:41:28 +03006372 uint32_t cdctl, expected;
Shobhit Kumarc73666f2015-10-20 18:13:12 +05306373
Shobhit Kumarf1b391a2015-11-05 18:05:32 +05306374 /*
6375 * check if the pre-os intialized the display
6376 * There is SWF18 scratchpad register defined which is set by the
6377 * pre-os which can be used by the OS drivers to check the status
6378 */
6379 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6380 goto sanitize;
6381
Chris Wilson91c8a322016-07-05 10:40:23 +01006382 intel_update_cdclk(&dev_priv->drm);
Imre Deak1c3f7702016-05-24 15:38:32 +03006383 /* Is PLL enabled and locked ? */
6384 if (dev_priv->cdclk_pll.vco == 0 ||
6385 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6386 goto sanitize;
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006387
Shobhit Kumarc73666f2015-10-20 18:13:12 +05306388 /* DPLL okay; verify the cdclock
6389 *
6390 * Noticed in some instances that the freq selection is correct but
6391 * decimal part is programmed wrong from BIOS where pre-os does not
6392 * enable display. Verify the same as well.
6393 */
Ville Syrjälä09492492016-05-13 23:41:28 +03006394 cdctl = I915_READ(CDCLK_CTL);
6395 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6396 skl_cdclk_decimal(dev_priv->cdclk_freq);
6397 if (cdctl == expected)
Shobhit Kumarc73666f2015-10-20 18:13:12 +05306398 /* All well; nothing to sanitize */
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006399 return;
6400
Shobhit Kumarc73666f2015-10-20 18:13:12 +05306401sanitize:
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006402 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
Clint Taylorc89e39f2016-05-13 23:41:21 +03006403
Ville Syrjälä9f7eb312016-05-13 23:41:29 +03006404 /* force cdclk programming */
6405 dev_priv->cdclk_freq = 0;
6406 /* force full PLL disable + enable */
Ville Syrjälä63911d72016-05-13 23:41:32 +03006407 dev_priv->cdclk_pll.vco = -1;
Shobhit Kumarc73666f2015-10-20 18:13:12 +05306408}
6409
Jesse Barnes30a970c2013-11-04 13:48:12 -08006410/* Adjust CDclk dividers to allow high res or save power if possible */
6411static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6412{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006413 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006414 u32 val, cmd;
6415
Vandana Kannan164dfd22014-11-24 13:37:41 +05306416 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6417 != dev_priv->cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02006418
Ville Syrjälädfcab172014-06-13 13:37:47 +03006419 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08006420 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03006421 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006422 cmd = 1;
6423 else
6424 cmd = 0;
6425
6426 mutex_lock(&dev_priv->rps.hw_lock);
6427 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6428 val &= ~DSPFREQGUAR_MASK;
6429 val |= (cmd << DSPFREQGUAR_SHIFT);
6430 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6431 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6432 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6433 50)) {
6434 DRM_ERROR("timed out waiting for CDclk change\n");
6435 }
6436 mutex_unlock(&dev_priv->rps.hw_lock);
6437
Ville Syrjälä54433e92015-05-26 20:42:31 +03006438 mutex_lock(&dev_priv->sb_lock);
6439
Ville Syrjälädfcab172014-06-13 13:37:47 +03006440 if (cdclk == 400000) {
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03006441 u32 divider;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006442
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03006443 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006444
Jesse Barnes30a970c2013-11-04 13:48:12 -08006445 /* adjust cdclk divider */
6446 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Vandana Kannan87d5d252015-09-24 23:29:17 +03006447 val &= ~CCK_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006448 val |= divider;
6449 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03006450
6451 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
Vandana Kannan87d5d252015-09-24 23:29:17 +03006452 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
Ville Syrjäläa877e802014-06-13 13:37:52 +03006453 50))
6454 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08006455 }
6456
Jesse Barnes30a970c2013-11-04 13:48:12 -08006457 /* adjust self-refresh exit latency value */
6458 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6459 val &= ~0x7f;
6460
6461 /*
6462 * For high bandwidth configs, we set a higher latency in the bunit
6463 * so that the core display fetch happens in time to avoid underruns.
6464 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03006465 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006466 val |= 4500 / 250; /* 4.5 usec */
6467 else
6468 val |= 3000 / 250; /* 3.0 usec */
6469 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
Ville Syrjälä54433e92015-05-26 20:42:31 +03006470
Ville Syrjäläa5805162015-05-26 20:42:30 +03006471 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006472
Ville Syrjäläb6283052015-06-03 15:45:07 +03006473 intel_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006474}
6475
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006476static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6477{
Chris Wilsonfac5e232016-07-04 11:34:36 +01006478 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006479 u32 val, cmd;
6480
Vandana Kannan164dfd22014-11-24 13:37:41 +05306481 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6482 != dev_priv->cdclk_freq);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006483
6484 switch (cdclk) {
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006485 case 333333:
6486 case 320000:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006487 case 266667:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006488 case 200000:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006489 break;
6490 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +01006491 MISSING_CASE(cdclk);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006492 return;
6493 }
6494
Ville Syrjälä9d0d3fd2015-03-02 20:07:17 +02006495 /*
6496 * Specs are full of misinformation, but testing on actual
6497 * hardware has shown that we just need to write the desired
6498 * CCK divider into the Punit register.
6499 */
6500 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6501
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006502 mutex_lock(&dev_priv->rps.hw_lock);
6503 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6504 val &= ~DSPFREQGUAR_MASK_CHV;
6505 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6506 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6507 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6508 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6509 50)) {
6510 DRM_ERROR("timed out waiting for CDclk change\n");
6511 }
6512 mutex_unlock(&dev_priv->rps.hw_lock);
6513
Ville Syrjäläb6283052015-06-03 15:45:07 +03006514 intel_update_cdclk(dev);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006515}
6516
Jesse Barnes30a970c2013-11-04 13:48:12 -08006517static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6518 int max_pixclk)
6519{
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03006520 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006521 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03006522
Jesse Barnes30a970c2013-11-04 13:48:12 -08006523 /*
6524 * Really only a few cases to deal with, as only 4 CDclks are supported:
6525 * 200MHz
6526 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03006527 * 320/333MHz (depends on HPLL freq)
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006528 * 400MHz (VLV only)
6529 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6530 * of the lower bin and adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03006531 *
6532 * We seem to get an unstable or solid color picture at 200MHz.
6533 * Not sure what's wrong. For now use 200MHz only when all pipes
6534 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08006535 */
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006536 if (!IS_CHERRYVIEW(dev_priv) &&
6537 max_pixclk > freq_320*limit/100)
Ville Syrjälädfcab172014-06-13 13:37:47 +03006538 return 400000;
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006539 else if (max_pixclk > 266667*limit/100)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03006540 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03006541 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03006542 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03006543 else
6544 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006545}
6546
Imre Deak324513c2016-06-13 16:44:36 +03006547static int bxt_calc_cdclk(int max_pixclk)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006548{
Ville Syrjälä760e1472016-05-11 22:44:46 +03006549 if (max_pixclk > 576000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306550 return 624000;
Ville Syrjälä760e1472016-05-11 22:44:46 +03006551 else if (max_pixclk > 384000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306552 return 576000;
Ville Syrjälä760e1472016-05-11 22:44:46 +03006553 else if (max_pixclk > 288000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306554 return 384000;
Ville Syrjälä760e1472016-05-11 22:44:46 +03006555 else if (max_pixclk > 144000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306556 return 288000;
6557 else
6558 return 144000;
6559}
6560
Maarten Lankhorste8788cb2016-02-16 10:25:11 +01006561/* Compute the max pixel clock for new configuration. */
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03006562static int intel_mode_max_pixclk(struct drm_device *dev,
6563 struct drm_atomic_state *state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006564{
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006565 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Chris Wilsonfac5e232016-07-04 11:34:36 +01006566 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006567 struct drm_crtc *crtc;
6568 struct drm_crtc_state *crtc_state;
6569 unsigned max_pixclk = 0, i;
6570 enum pipe pipe;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006571
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006572 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6573 sizeof(intel_state->min_pixclk));
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006574
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006575 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6576 int pixclk = 0;
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006577
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006578 if (crtc_state->enable)
6579 pixclk = crtc_state->adjusted_mode.crtc_clock;
6580
6581 intel_state->min_pixclk[i] = pixclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006582 }
6583
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006584 for_each_pipe(dev_priv, pipe)
6585 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6586
Jesse Barnes30a970c2013-11-04 13:48:12 -08006587 return max_pixclk;
6588}
6589
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006590static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006591{
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006592 struct drm_device *dev = state->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01006593 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006594 int max_pixclk = intel_mode_max_pixclk(dev, state);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006595 struct intel_atomic_state *intel_state =
6596 to_intel_atomic_state(state);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006597
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006598 intel_state->cdclk = intel_state->dev_cdclk =
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006599 valleyview_calc_cdclk(dev_priv, max_pixclk);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306600
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006601 if (!intel_state->active_crtcs)
6602 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6603
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006604 return 0;
6605}
Jesse Barnes30a970c2013-11-04 13:48:12 -08006606
Imre Deak324513c2016-06-13 16:44:36 +03006607static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006608{
Ville Syrjälä4e5ca602016-05-11 22:44:44 +03006609 int max_pixclk = ilk_max_pixel_rate(state);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006610 struct intel_atomic_state *intel_state =
6611 to_intel_atomic_state(state);
Maarten Lankhorst85a96e72015-06-01 12:49:53 +02006612
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006613 intel_state->cdclk = intel_state->dev_cdclk =
Imre Deak324513c2016-06-13 16:44:36 +03006614 bxt_calc_cdclk(max_pixclk);
Maarten Lankhorst85a96e72015-06-01 12:49:53 +02006615
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006616 if (!intel_state->active_crtcs)
Imre Deak324513c2016-06-13 16:44:36 +03006617 intel_state->dev_cdclk = bxt_calc_cdclk(0);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006618
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006619 return 0;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006620}
6621
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02006622static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6623{
6624 unsigned int credits, default_credits;
6625
6626 if (IS_CHERRYVIEW(dev_priv))
6627 default_credits = PFI_CREDIT(12);
6628 else
6629 default_credits = PFI_CREDIT(8);
6630
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03006631 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02006632 /* CHV suggested value is 31 or 63 */
6633 if (IS_CHERRYVIEW(dev_priv))
Ville Syrjäläfcc00082015-05-26 20:22:40 +03006634 credits = PFI_CREDIT_63;
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02006635 else
6636 credits = PFI_CREDIT(15);
6637 } else {
6638 credits = default_credits;
6639 }
6640
6641 /*
6642 * WA - write default credits before re-programming
6643 * FIXME: should we also set the resend bit here?
6644 */
6645 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6646 default_credits);
6647
6648 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6649 credits | PFI_CREDIT_RESEND);
6650
6651 /*
6652 * FIXME is this guaranteed to clear
6653 * immediately or should we poll for it?
6654 */
6655 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6656}
6657
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006658static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006659{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03006660 struct drm_device *dev = old_state->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01006661 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01006662 struct intel_atomic_state *old_intel_state =
6663 to_intel_atomic_state(old_state);
6664 unsigned req_cdclk = old_intel_state->dev_cdclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006665
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006666 /*
6667 * FIXME: We can end up here with all power domains off, yet
6668 * with a CDCLK frequency other than the minimum. To account
6669 * for this take the PIPE-A power domain, which covers the HW
6670 * blocks needed for the following programming. This can be
6671 * removed once it's guaranteed that we get here either with
6672 * the minimum CDCLK set, or the required power domains
6673 * enabled.
6674 */
6675 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006676
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006677 if (IS_CHERRYVIEW(dev))
6678 cherryview_set_cdclk(dev, req_cdclk);
6679 else
6680 valleyview_set_cdclk(dev, req_cdclk);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006681
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006682 vlv_program_pfi_credits(dev_priv);
Imre Deak738c05c2014-11-19 16:25:37 +02006683
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006684 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006685}
6686
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006687static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6688 struct drm_atomic_state *old_state)
Jesse Barnes89b667f2013-04-18 14:51:36 -07006689{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006690 struct drm_crtc *crtc = pipe_config->base.crtc;
Jesse Barnes89b667f2013-04-18 14:51:36 -07006691 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02006692 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006694 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07006695
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02006696 if (WARN_ON(intel_crtc->active))
Jesse Barnes89b667f2013-04-18 14:51:36 -07006697 return;
6698
Ville Syrjälä37a56502016-06-22 21:57:04 +03006699 if (intel_crtc_has_dp_encoder(intel_crtc->config))
Ramalingam Cfe3cd482015-02-13 15:32:59 +05306700 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter5b18e572014-04-24 23:55:06 +02006701
6702 intel_set_pipe_timings(intel_crtc);
Jani Nikulabc58be62016-03-18 17:05:39 +02006703 intel_set_pipe_src_size(intel_crtc);
Daniel Vetter5b18e572014-04-24 23:55:06 +02006704
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006705 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
Chris Wilsonfac5e232016-07-04 11:34:36 +01006706 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006707
6708 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6709 I915_WRITE(CHV_CANVAS(pipe), 0);
6710 }
6711
Daniel Vetter5b18e572014-04-24 23:55:06 +02006712 i9xx_set_pipeconf(intel_crtc);
6713
Jesse Barnes89b667f2013-04-18 14:51:36 -07006714 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07006715
Daniel Vettera72e4c92014-09-30 10:56:47 +02006716 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006717
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006718 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006719
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03006720 if (IS_CHERRYVIEW(dev)) {
6721 chv_prepare_pll(intel_crtc, intel_crtc->config);
6722 chv_enable_pll(intel_crtc, intel_crtc->config);
6723 } else {
6724 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6725 vlv_enable_pll(intel_crtc, intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006726 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07006727
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006728 intel_encoders_pre_enable(crtc, pipe_config, old_state);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006729
Jesse Barnes2dd24552013-04-25 12:55:01 -07006730 i9xx_pfit_enable(intel_crtc);
6731
Maarten Lankhorstb95c5322016-03-30 17:16:34 +02006732 intel_color_load_luts(&pipe_config->base);
Ville Syrjälä63cbb072013-06-04 13:48:59 +03006733
Ville Syrjäläcaed3612016-03-09 19:07:25 +02006734 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02006735 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02006736
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006737 assert_vblank_disabled(crtc);
6738 drm_crtc_vblank_on(crtc);
6739
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006740 intel_encoders_enable(crtc, pipe_config, old_state);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006741}
6742
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006743static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6744{
6745 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01006746 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006747
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006748 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6749 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006750}
6751
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006752static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6753 struct drm_atomic_state *old_state)
Zhenyu Wang2c072452009-06-05 15:38:42 +08006754{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006755 struct drm_crtc *crtc = pipe_config->base.crtc;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006756 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02006757 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03006759 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08006760
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02006761 if (WARN_ON(intel_crtc->active))
Chris Wilsonf7abfe82010-09-13 14:19:16 +01006762 return;
6763
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006764 i9xx_set_pll_dividers(intel_crtc);
6765
Ville Syrjälä37a56502016-06-22 21:57:04 +03006766 if (intel_crtc_has_dp_encoder(intel_crtc->config))
Ramalingam Cfe3cd482015-02-13 15:32:59 +05306767 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter5b18e572014-04-24 23:55:06 +02006768
6769 intel_set_pipe_timings(intel_crtc);
Jani Nikulabc58be62016-03-18 17:05:39 +02006770 intel_set_pipe_src_size(intel_crtc);
Daniel Vetter5b18e572014-04-24 23:55:06 +02006771
Daniel Vetter5b18e572014-04-24 23:55:06 +02006772 i9xx_set_pipeconf(intel_crtc);
6773
Chris Wilsonf7abfe82010-09-13 14:19:16 +01006774 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01006775
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006776 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02006777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006778
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006779 intel_encoders_pre_enable(crtc, pipe_config, old_state);
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02006780
Daniel Vetterf6736a12013-06-05 13:34:30 +02006781 i9xx_enable_pll(intel_crtc);
6782
Jesse Barnes2dd24552013-04-25 12:55:01 -07006783 i9xx_pfit_enable(intel_crtc);
6784
Maarten Lankhorstb95c5322016-03-30 17:16:34 +02006785 intel_color_load_luts(&pipe_config->base);
Ville Syrjälä63cbb072013-06-04 13:48:59 +03006786
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03006787 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02006788 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02006789
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006790 assert_vblank_disabled(crtc);
6791 drm_crtc_vblank_on(crtc);
6792
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006793 intel_encoders_enable(crtc, pipe_config, old_state);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006794}
6795
Daniel Vetter87476d62013-04-11 16:29:06 +02006796static void i9xx_pfit_disable(struct intel_crtc *crtc)
6797{
6798 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01006799 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter328d8e82013-05-08 10:36:31 +02006800
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006801 if (!crtc->config->gmch_pfit.control)
Daniel Vetter328d8e82013-05-08 10:36:31 +02006802 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02006803
6804 assert_pipe_disabled(dev_priv, crtc->pipe);
6805
Daniel Vetter328d8e82013-05-08 10:36:31 +02006806 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6807 I915_READ(PFIT_CONTROL));
6808 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02006809}
6810
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006811static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6812 struct drm_atomic_state *old_state)
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006813{
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006814 struct drm_crtc *crtc = old_crtc_state->base.crtc;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006815 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01006816 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6818 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02006819
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006820 /*
6821 * On gen2 planes are double buffered but the pipe isn't, so we must
6822 * wait for planes to fully turn off before disabling the pipe.
6823 */
Ander Conselvan de Oliveira90e83e52016-03-22 10:11:24 +02006824 if (IS_GEN2(dev))
6825 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006826
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006827 intel_encoders_disable(crtc, old_crtc_state, old_state);
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006828
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01006829 drm_crtc_vblank_off(crtc);
6830 assert_vblank_disabled(crtc);
6831
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03006832 intel_disable_pipe(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02006833
Daniel Vetter87476d62013-04-11 16:29:06 +02006834 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02006835
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006836 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006837
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03006838 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03006839 if (IS_CHERRYVIEW(dev))
6840 chv_disable_pll(dev_priv, pipe);
6841 else if (IS_VALLEYVIEW(dev))
6842 vlv_disable_pll(dev_priv, pipe);
6843 else
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03006844 i9xx_disable_pll(intel_crtc);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03006845 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006846
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02006847 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
Ville Syrjäläd6db9952015-07-08 23:45:49 +03006848
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006849 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02006850 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006851}
6852
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006853static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006854{
Maarten Lankhorst842e0302016-03-02 15:48:01 +01006855 struct intel_encoder *encoder;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006857 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006858 enum intel_display_power_domain domain;
6859 unsigned long domains;
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006860 struct drm_atomic_state *state;
6861 struct intel_crtc_state *crtc_state;
6862 int ret;
Daniel Vetter976f8a22012-07-08 22:34:21 +02006863
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006864 if (!intel_crtc->active)
6865 return;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006866
Ville Syrjälä936e71e2016-07-26 19:06:59 +03006867 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
Daniel Vetter5a21b662016-05-24 17:13:53 +02006868 WARN_ON(intel_crtc->flip_work);
Maarten Lankhorstfc32b1f2015-10-19 17:09:23 +02006869
Ville Syrjälä2622a082016-03-09 19:07:26 +02006870 intel_pre_disable_primary_noatomic(crtc);
Maarten Lankhorst54a419612015-11-23 10:25:28 +01006871
6872 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
Ville Syrjälä936e71e2016-07-26 19:06:59 +03006873 to_intel_plane_state(crtc->primary->state)->base.visible = false;
Maarten Lankhorsta5392052015-06-15 12:33:52 +02006874 }
6875
Maarten Lankhorst4a806552016-08-09 17:04:01 +02006876 state = drm_atomic_state_alloc(crtc->dev);
6877 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6878
6879 /* Everything's already locked, -EDEADLK can't happen. */
6880 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6881 ret = drm_atomic_add_affected_connectors(state, crtc);
6882
6883 WARN_ON(IS_ERR(crtc_state) || ret);
6884
6885 dev_priv->display.crtc_disable(crtc_state, state);
6886
Chris Wilson08536952016-10-14 13:18:18 +01006887 drm_atomic_state_put(state);
Maarten Lankhorst842e0302016-03-02 15:48:01 +01006888
Ville Syrjälä78108b72016-05-27 20:59:19 +03006889 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6890 crtc->base.id, crtc->name);
Maarten Lankhorst842e0302016-03-02 15:48:01 +01006891
6892 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6893 crtc->state->active = false;
Matt Roper37d90782015-09-24 15:53:06 -07006894 intel_crtc->active = false;
Maarten Lankhorst842e0302016-03-02 15:48:01 +01006895 crtc->enabled = false;
6896 crtc->state->connector_mask = 0;
6897 crtc->state->encoder_mask = 0;
6898
6899 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6900 encoder->base.crtc = NULL;
6901
Paulo Zanoni58f9c0b2016-01-19 11:35:51 -02006902 intel_fbc_disable(intel_crtc);
Matt Roper37d90782015-09-24 15:53:06 -07006903 intel_update_watermarks(crtc);
Maarten Lankhorst1f7457b2015-07-13 11:55:05 +02006904 intel_disable_shared_dpll(intel_crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006905
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006906 domains = intel_crtc->enabled_power_domains;
6907 for_each_power_domain(domain, domains)
6908 intel_display_power_put(dev_priv, domain);
6909 intel_crtc->enabled_power_domains = 0;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006910
6911 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6912 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006913}
6914
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006915/*
6916 * turn all crtc's off, but do not adjust state
6917 * This has to be paired with a call to intel_modeset_setup_hw_state.
6918 */
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006919int intel_display_suspend(struct drm_device *dev)
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006920{
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01006921 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006922 struct drm_atomic_state *state;
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01006923 int ret;
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006924
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01006925 state = drm_atomic_helper_suspend(dev);
6926 ret = PTR_ERR_OR_ZERO(state);
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006927 if (ret)
6928 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01006929 else
6930 dev_priv->modeset_restore_state = state;
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006931 return ret;
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006932}
6933
Chris Wilsonea5b2132010-08-04 13:50:23 +01006934void intel_encoder_destroy(struct drm_encoder *encoder)
6935{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006936 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01006937
Chris Wilsonea5b2132010-08-04 13:50:23 +01006938 drm_encoder_cleanup(encoder);
6939 kfree(intel_encoder);
6940}
6941
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006942/* Cross check the actual hw state with our own modeset state tracking (and it's
6943 * internal consistency). */
Daniel Vetter5a21b662016-05-24 17:13:53 +02006944static void intel_connector_verify_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006945{
Daniel Vetter5a21b662016-05-24 17:13:53 +02006946 struct drm_crtc *crtc = connector->base.state->crtc;
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006947
6948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6949 connector->base.base.id,
6950 connector->base.name);
6951
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006952 if (connector->get_hw_state(connector)) {
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006953 struct intel_encoder *encoder = connector->encoder;
Daniel Vetter5a21b662016-05-24 17:13:53 +02006954 struct drm_connector_state *conn_state = connector->base.state;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006955
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006956 I915_STATE_WARN(!crtc,
6957 "connector enabled without attached crtc\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006958
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006959 if (!crtc)
6960 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006961
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006962 I915_STATE_WARN(!crtc->state->active,
6963 "connector is active, but attached crtc isn't\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006964
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006965 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006966 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006967
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006968 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006969 "atomic encoder doesn't match attached encoder\n");
Dave Airlie36cd7442014-05-02 13:44:18 +10006970
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006971 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006972 "attached encoder crtc differs from connector crtc\n");
6973 } else {
Maarten Lankhorst4d688a22015-08-05 12:37:06 +02006974 I915_STATE_WARN(crtc && crtc->state->active,
6975 "attached crtc is active, but connector isn't\n");
Daniel Vetter5a21b662016-05-24 17:13:53 +02006976 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006977 "best encoder set without crtc!\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006978 }
6979}
6980
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006981int intel_connector_init(struct intel_connector *connector)
6982{
Maarten Lankhorst5350a032016-01-04 12:53:15 +01006983 drm_atomic_helper_connector_reset(&connector->base);
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006984
Maarten Lankhorst5350a032016-01-04 12:53:15 +01006985 if (!connector->base.state)
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006986 return -ENOMEM;
6987
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006988 return 0;
6989}
6990
6991struct intel_connector *intel_connector_alloc(void)
6992{
6993 struct intel_connector *connector;
6994
6995 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6996 if (!connector)
6997 return NULL;
6998
6999 if (intel_connector_init(connector) < 0) {
7000 kfree(connector);
7001 return NULL;
7002 }
7003
7004 return connector;
7005}
7006
Daniel Vetterf0947c32012-07-02 13:10:34 +02007007/* Simple connector->get_hw_state implementation for encoders that support only
7008 * one connector and no cloning and hence the encoder state determines the state
7009 * of the connector. */
7010bool intel_connector_get_hw_state(struct intel_connector *connector)
7011{
Daniel Vetter24929352012-07-02 20:28:59 +02007012 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02007013 struct intel_encoder *encoder = connector->encoder;
7014
7015 return encoder->get_hw_state(encoder, &pipe);
7016}
7017
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007018static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
Ville Syrjäläd272ddf2015-03-11 18:52:31 +02007019{
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007020 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7021 return crtc_state->fdi_lanes;
Ville Syrjäläd272ddf2015-03-11 18:52:31 +02007022
7023 return 0;
7024}
7025
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007026static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007027 struct intel_crtc_state *pipe_config)
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007028{
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007029 struct drm_atomic_state *state = pipe_config->base.state;
7030 struct intel_crtc *other_crtc;
7031 struct intel_crtc_state *other_crtc_state;
7032
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007033 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7034 pipe_name(pipe), pipe_config->fdi_lanes);
7035 if (pipe_config->fdi_lanes > 4) {
7036 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7037 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007038 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007039 }
7040
Paulo Zanonibafb6552013-11-02 21:07:44 -07007041 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007042 if (pipe_config->fdi_lanes > 2) {
7043 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7044 pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007045 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007046 } else {
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007047 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007048 }
7049 }
7050
7051 if (INTEL_INFO(dev)->num_pipes == 2)
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007052 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007053
7054 /* Ivybridge 3 pipe is really complicated */
7055 switch (pipe) {
7056 case PIPE_A:
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007057 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007058 case PIPE_B:
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007059 if (pipe_config->fdi_lanes <= 2)
7060 return 0;
7061
7062 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7063 other_crtc_state =
7064 intel_atomic_get_crtc_state(state, other_crtc);
7065 if (IS_ERR(other_crtc_state))
7066 return PTR_ERR(other_crtc_state);
7067
7068 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007069 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7070 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007071 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007072 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007073 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007074 case PIPE_C:
Ville Syrjälä251cc672015-03-11 18:52:30 +02007075 if (pipe_config->fdi_lanes > 2) {
7076 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7077 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007078 return -EINVAL;
Ville Syrjälä251cc672015-03-11 18:52:30 +02007079 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007080
7081 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7082 other_crtc_state =
7083 intel_atomic_get_crtc_state(state, other_crtc);
7084 if (IS_ERR(other_crtc_state))
7085 return PTR_ERR(other_crtc_state);
7086
7087 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007088 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007089 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007090 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007091 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007092 default:
7093 BUG();
7094 }
7095}
7096
Daniel Vettere29c22c2013-02-21 00:00:16 +01007097#define RETRY 1
7098static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007099 struct intel_crtc_state *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02007100{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007101 struct drm_device *dev = intel_crtc->base.dev;
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03007102 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007103 int lane, link_bw, fdi_dotclock, ret;
7104 bool needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02007105
Daniel Vettere29c22c2013-02-21 00:00:16 +01007106retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02007107 /* FDI is a binary signal running at ~2.7GHz, encoding
7108 * each output octet as 10 bits. The actual frequency
7109 * is stored as a divider into a 100MHz clock, and the
7110 * mode pixel clock is stored in units of 1KHz.
7111 * Hence the bw of each lane in terms of the mode signal
7112 * is:
7113 */
Ville Syrjälä21a727b2016-02-17 21:41:10 +02007114 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02007115
Damien Lespiau241bfc32013-09-25 16:45:37 +01007116 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02007117
Daniel Vetter2bd89a02013-06-01 17:16:19 +02007118 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02007119 pipe_config->pipe_bpp);
7120
7121 pipe_config->fdi_lanes = lane;
7122
Daniel Vetter2bd89a02013-06-01 17:16:19 +02007123 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02007124 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02007125
Ville Syrjäläe3b247d2016-02-17 21:41:09 +02007126 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007127 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
Daniel Vettere29c22c2013-02-21 00:00:16 +01007128 pipe_config->pipe_bpp -= 2*3;
7129 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7130 pipe_config->pipe_bpp);
7131 needs_recompute = true;
7132 pipe_config->bw_constrained = true;
7133
7134 goto retry;
7135 }
7136
7137 if (needs_recompute)
7138 return RETRY;
7139
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03007140 return ret;
Daniel Vetter877d48d2013-04-19 11:24:43 +02007141}
7142
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03007143static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7144 struct intel_crtc_state *pipe_config)
7145{
7146 if (pipe_config->pipe_bpp > 24)
7147 return false;
7148
7149 /* HSW can handle pixel rate up to cdclk? */
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03007150 if (IS_HASWELL(dev_priv))
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03007151 return true;
7152
7153 /*
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03007154 * We compare against max which means we must take
7155 * the increased cdclk requirement into account when
7156 * calculating the new cdclk.
7157 *
7158 * Should measure whether using a lower cdclk w/o IPS
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03007159 */
7160 return ilk_pipe_pixel_rate(pipe_config) <=
7161 dev_priv->max_cdclk_freq * 95 / 100;
7162}
7163
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007164static void hsw_compute_ips_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007165 struct intel_crtc_state *pipe_config)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007166{
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03007167 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01007168 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03007169
Jani Nikulad330a952014-01-21 11:24:25 +02007170 pipe_config->ips_enabled = i915.enable_ips &&
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03007171 hsw_crtc_supports_ips(crtc) &&
7172 pipe_config_supports_ips(dev_priv, pipe_config);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007173}
7174
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02007175static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7176{
7177 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7178
7179 /* GDG double wide on either pipe, otherwise pipe A only */
7180 return INTEL_INFO(dev_priv)->gen < 4 &&
7181 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7182}
7183
Daniel Vettera43f6e02013-06-07 23:10:32 +02007184static int intel_crtc_compute_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007185 struct intel_crtc_state *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08007186{
Daniel Vettera43f6e02013-06-07 23:10:32 +02007187 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01007188 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03007189 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Ville Syrjäläf3261152016-05-24 21:34:18 +03007190 int clock_limit = dev_priv->max_dotclk_freq;
Chris Wilson89749352010-09-12 18:25:19 +01007191
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007192 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjäläf3261152016-05-24 21:34:18 +03007193 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007194
7195 /*
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02007196 * Enable double wide mode when the dot clock
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007197 * is > 90% of the (display) core speed.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007198 */
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02007199 if (intel_crtc_supports_double_wide(crtc) &&
7200 adjusted_mode->crtc_clock > clock_limit) {
Ville Syrjäläf3261152016-05-24 21:34:18 +03007201 clock_limit = dev_priv->max_dotclk_freq;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007202 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03007203 }
Ville Syrjäläf3261152016-05-24 21:34:18 +03007204 }
Ville Syrjäläad3a4472013-09-04 18:30:04 +03007205
Ville Syrjäläf3261152016-05-24 21:34:18 +03007206 if (adjusted_mode->crtc_clock > clock_limit) {
7207 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7208 adjusted_mode->crtc_clock, clock_limit,
7209 yesno(pipe_config->double_wide));
7210 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007211 }
Chris Wilson89749352010-09-12 18:25:19 +01007212
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03007213 /*
7214 * Pipe horizontal size must be even in:
7215 * - DVO ganged mode
7216 * - LVDS dual channel mode
7217 * - Double wide pipe
7218 */
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03007219 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03007220 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7221 pipe_config->pipe_src_w &= ~1;
7222
Damien Lespiau8693a822013-05-03 18:48:11 +01007223 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7224 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03007225 */
7226 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
Ville Syrjäläaad941d2015-09-25 16:38:56 +03007227 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01007228 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03007229
Damien Lespiauf5adf942013-06-24 18:29:34 +01007230 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02007231 hsw_compute_ips_config(crtc, pipe_config);
7232
Daniel Vetter877d48d2013-04-19 11:24:43 +02007233 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02007234 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02007235
Maarten Lankhorstcf5a15b2015-06-15 12:33:41 +02007236 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007237}
7238
Ville Syrjälä1652d192015-03-31 14:12:01 +03007239static int skylake_get_display_clock_speed(struct drm_device *dev)
7240{
7241 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläea617912016-05-13 23:41:24 +03007242 uint32_t cdctl;
Ville Syrjälä1652d192015-03-31 14:12:01 +03007243
Ville Syrjäläea617912016-05-13 23:41:24 +03007244 skl_dpll0_update(dev_priv);
7245
Ville Syrjälä63911d72016-05-13 23:41:32 +03007246 if (dev_priv->cdclk_pll.vco == 0)
Ville Syrjälä709e05c2016-05-13 23:41:33 +03007247 return dev_priv->cdclk_pll.ref;
Ville Syrjälä1652d192015-03-31 14:12:01 +03007248
Ville Syrjäläea617912016-05-13 23:41:24 +03007249 cdctl = I915_READ(CDCLK_CTL);
Ville Syrjälä1652d192015-03-31 14:12:01 +03007250
Ville Syrjälä63911d72016-05-13 23:41:32 +03007251 if (dev_priv->cdclk_pll.vco == 8640000) {
Ville Syrjälä1652d192015-03-31 14:12:01 +03007252 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7253 case CDCLK_FREQ_450_432:
7254 return 432000;
7255 case CDCLK_FREQ_337_308:
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03007256 return 308571;
Ville Syrjäläea617912016-05-13 23:41:24 +03007257 case CDCLK_FREQ_540:
7258 return 540000;
Ville Syrjälä1652d192015-03-31 14:12:01 +03007259 case CDCLK_FREQ_675_617:
Ville Syrjälä487ed2e2016-05-13 23:41:31 +03007260 return 617143;
Ville Syrjälä1652d192015-03-31 14:12:01 +03007261 default:
Ville Syrjäläea617912016-05-13 23:41:24 +03007262 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
Ville Syrjälä1652d192015-03-31 14:12:01 +03007263 }
7264 } else {
Ville Syrjälä1652d192015-03-31 14:12:01 +03007265 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7266 case CDCLK_FREQ_450_432:
7267 return 450000;
7268 case CDCLK_FREQ_337_308:
7269 return 337500;
Ville Syrjäläea617912016-05-13 23:41:24 +03007270 case CDCLK_FREQ_540:
7271 return 540000;
Ville Syrjälä1652d192015-03-31 14:12:01 +03007272 case CDCLK_FREQ_675_617:
7273 return 675000;
7274 default:
Ville Syrjäläea617912016-05-13 23:41:24 +03007275 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
Ville Syrjälä1652d192015-03-31 14:12:01 +03007276 }
7277 }
7278
Ville Syrjälä709e05c2016-05-13 23:41:33 +03007279 return dev_priv->cdclk_pll.ref;
Ville Syrjälä1652d192015-03-31 14:12:01 +03007280}
7281
Ville Syrjälä83d7c812016-05-13 23:41:35 +03007282static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7283{
7284 u32 val;
7285
7286 dev_priv->cdclk_pll.ref = 19200;
Imre Deak1c3f7702016-05-24 15:38:32 +03007287 dev_priv->cdclk_pll.vco = 0;
Ville Syrjälä83d7c812016-05-13 23:41:35 +03007288
7289 val = I915_READ(BXT_DE_PLL_ENABLE);
Imre Deak1c3f7702016-05-24 15:38:32 +03007290 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
Ville Syrjälä83d7c812016-05-13 23:41:35 +03007291 return;
Ville Syrjälä83d7c812016-05-13 23:41:35 +03007292
Imre Deak1c3f7702016-05-24 15:38:32 +03007293 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7294 return;
Ville Syrjälä83d7c812016-05-13 23:41:35 +03007295
7296 val = I915_READ(BXT_DE_PLL_CTL);
7297 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7298 dev_priv->cdclk_pll.ref;
7299}
7300
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007301static int broxton_get_display_clock_speed(struct drm_device *dev)
7302{
7303 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläf5986242016-05-13 23:41:37 +03007304 u32 divider;
7305 int div, vco;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007306
Ville Syrjälä83d7c812016-05-13 23:41:35 +03007307 bxt_de_pll_update(dev_priv);
7308
Ville Syrjäläf5986242016-05-13 23:41:37 +03007309 vco = dev_priv->cdclk_pll.vco;
7310 if (vco == 0)
7311 return dev_priv->cdclk_pll.ref;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007312
Ville Syrjäläf5986242016-05-13 23:41:37 +03007313 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007314
Ville Syrjäläf5986242016-05-13 23:41:37 +03007315 switch (divider) {
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007316 case BXT_CDCLK_CD2X_DIV_SEL_1:
Ville Syrjäläf5986242016-05-13 23:41:37 +03007317 div = 2;
7318 break;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007319 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
Ville Syrjäläf5986242016-05-13 23:41:37 +03007320 div = 3;
7321 break;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007322 case BXT_CDCLK_CD2X_DIV_SEL_2:
Ville Syrjäläf5986242016-05-13 23:41:37 +03007323 div = 4;
7324 break;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007325 case BXT_CDCLK_CD2X_DIV_SEL_4:
Ville Syrjäläf5986242016-05-13 23:41:37 +03007326 div = 8;
7327 break;
7328 default:
7329 MISSING_CASE(divider);
7330 return dev_priv->cdclk_pll.ref;
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007331 }
7332
Ville Syrjäläf5986242016-05-13 23:41:37 +03007333 return DIV_ROUND_CLOSEST(vco, div);
Bob Paauweacd3f3d2015-06-23 14:14:26 -07007334}
7335
Ville Syrjälä1652d192015-03-31 14:12:01 +03007336static int broadwell_get_display_clock_speed(struct drm_device *dev)
7337{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007338 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä1652d192015-03-31 14:12:01 +03007339 uint32_t lcpll = I915_READ(LCPLL_CTL);
7340 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7341
7342 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7343 return 800000;
7344 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7345 return 450000;
7346 else if (freq == LCPLL_CLK_FREQ_450)
7347 return 450000;
7348 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7349 return 540000;
7350 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7351 return 337500;
7352 else
7353 return 675000;
7354}
7355
7356static int haswell_get_display_clock_speed(struct drm_device *dev)
7357{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007358 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä1652d192015-03-31 14:12:01 +03007359 uint32_t lcpll = I915_READ(LCPLL_CTL);
7360 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7361
7362 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7363 return 800000;
7364 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7365 return 450000;
7366 else if (freq == LCPLL_CLK_FREQ_450)
7367 return 450000;
7368 else if (IS_HSW_ULT(dev))
7369 return 337500;
7370 else
7371 return 540000;
Jesse Barnes79e53942008-11-07 14:24:08 -08007372}
7373
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07007374static int valleyview_get_display_clock_speed(struct drm_device *dev)
7375{
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03007376 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7377 CCK_DISPLAY_CLOCK_CONTROL);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07007378}
7379
Ville Syrjäläb37a6432015-03-31 14:11:54 +03007380static int ilk_get_display_clock_speed(struct drm_device *dev)
7381{
7382 return 450000;
7383}
7384
Jesse Barnese70236a2009-09-21 10:42:27 -07007385static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08007386{
Jesse Barnese70236a2009-09-21 10:42:27 -07007387 return 400000;
7388}
Jesse Barnes79e53942008-11-07 14:24:08 -08007389
Jesse Barnese70236a2009-09-21 10:42:27 -07007390static int i915_get_display_clock_speed(struct drm_device *dev)
7391{
Ville Syrjäläe907f172015-03-31 14:09:47 +03007392 return 333333;
Jesse Barnese70236a2009-09-21 10:42:27 -07007393}
Jesse Barnes79e53942008-11-07 14:24:08 -08007394
Jesse Barnese70236a2009-09-21 10:42:27 -07007395static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7396{
7397 return 200000;
7398}
Jesse Barnes79e53942008-11-07 14:24:08 -08007399
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007400static int pnv_get_display_clock_speed(struct drm_device *dev)
7401{
David Weinehall52a05c32016-08-22 13:32:44 +03007402 struct pci_dev *pdev = dev->pdev;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007403 u16 gcfgc = 0;
7404
David Weinehall52a05c32016-08-22 13:32:44 +03007405 pci_read_config_word(pdev, GCFGC, &gcfgc);
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007406
7407 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7408 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007409 return 266667;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007410 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007411 return 333333;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007412 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007413 return 444444;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007414 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7415 return 200000;
7416 default:
7417 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7418 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007419 return 133333;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007420 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007421 return 166667;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02007422 }
7423}
7424
Jesse Barnese70236a2009-09-21 10:42:27 -07007425static int i915gm_get_display_clock_speed(struct drm_device *dev)
7426{
David Weinehall52a05c32016-08-22 13:32:44 +03007427 struct pci_dev *pdev = dev->pdev;
Jesse Barnese70236a2009-09-21 10:42:27 -07007428 u16 gcfgc = 0;
7429
David Weinehall52a05c32016-08-22 13:32:44 +03007430 pci_read_config_word(pdev, GCFGC, &gcfgc);
Jesse Barnese70236a2009-09-21 10:42:27 -07007431
7432 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Ville Syrjäläe907f172015-03-31 14:09:47 +03007433 return 133333;
Jesse Barnese70236a2009-09-21 10:42:27 -07007434 else {
7435 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7436 case GC_DISPLAY_CLOCK_333_MHZ:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007437 return 333333;
Jesse Barnese70236a2009-09-21 10:42:27 -07007438 default:
7439 case GC_DISPLAY_CLOCK_190_200_MHZ:
7440 return 190000;
7441 }
7442 }
7443}
Jesse Barnes79e53942008-11-07 14:24:08 -08007444
Jesse Barnese70236a2009-09-21 10:42:27 -07007445static int i865_get_display_clock_speed(struct drm_device *dev)
7446{
Ville Syrjäläe907f172015-03-31 14:09:47 +03007447 return 266667;
Jesse Barnese70236a2009-09-21 10:42:27 -07007448}
7449
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03007450static int i85x_get_display_clock_speed(struct drm_device *dev)
Jesse Barnese70236a2009-09-21 10:42:27 -07007451{
David Weinehall52a05c32016-08-22 13:32:44 +03007452 struct pci_dev *pdev = dev->pdev;
Jesse Barnese70236a2009-09-21 10:42:27 -07007453 u16 hpllcc = 0;
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03007454
Ville Syrjälä65cd2b32015-05-22 11:22:32 +03007455 /*
7456 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7457 * encoding is different :(
7458 * FIXME is this the right way to detect 852GM/852GMV?
7459 */
David Weinehall52a05c32016-08-22 13:32:44 +03007460 if (pdev->revision == 0x1)
Ville Syrjälä65cd2b32015-05-22 11:22:32 +03007461 return 133333;
7462
David Weinehall52a05c32016-08-22 13:32:44 +03007463 pci_bus_read_config_word(pdev->bus,
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03007464 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7465
Jesse Barnese70236a2009-09-21 10:42:27 -07007466 /* Assume that the hardware is in the high speed state. This
7467 * should be the default.
7468 */
7469 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7470 case GC_CLOCK_133_200:
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03007471 case GC_CLOCK_133_200_2:
Jesse Barnese70236a2009-09-21 10:42:27 -07007472 case GC_CLOCK_100_200:
7473 return 200000;
7474 case GC_CLOCK_166_250:
7475 return 250000;
7476 case GC_CLOCK_100_133:
Ville Syrjäläe907f172015-03-31 14:09:47 +03007477 return 133333;
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03007478 case GC_CLOCK_133_266:
7479 case GC_CLOCK_133_266_2:
7480 case GC_CLOCK_166_266:
7481 return 266667;
Jesse Barnese70236a2009-09-21 10:42:27 -07007482 }
7483
7484 /* Shouldn't happen */
7485 return 0;
7486}
7487
7488static int i830_get_display_clock_speed(struct drm_device *dev)
7489{
Ville Syrjäläe907f172015-03-31 14:09:47 +03007490 return 133333;
Jesse Barnes79e53942008-11-07 14:24:08 -08007491}
7492
Ville Syrjälä34edce22015-05-22 11:22:33 +03007493static unsigned int intel_hpll_vco(struct drm_device *dev)
7494{
Chris Wilsonfac5e232016-07-04 11:34:36 +01007495 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä34edce22015-05-22 11:22:33 +03007496 static const unsigned int blb_vco[8] = {
7497 [0] = 3200000,
7498 [1] = 4000000,
7499 [2] = 5333333,
7500 [3] = 4800000,
7501 [4] = 6400000,
7502 };
7503 static const unsigned int pnv_vco[8] = {
7504 [0] = 3200000,
7505 [1] = 4000000,
7506 [2] = 5333333,
7507 [3] = 4800000,
7508 [4] = 2666667,
7509 };
7510 static const unsigned int cl_vco[8] = {
7511 [0] = 3200000,
7512 [1] = 4000000,
7513 [2] = 5333333,
7514 [3] = 6400000,
7515 [4] = 3333333,
7516 [5] = 3566667,
7517 [6] = 4266667,
7518 };
7519 static const unsigned int elk_vco[8] = {
7520 [0] = 3200000,
7521 [1] = 4000000,
7522 [2] = 5333333,
7523 [3] = 4800000,
7524 };
7525 static const unsigned int ctg_vco[8] = {
7526 [0] = 3200000,
7527 [1] = 4000000,
7528 [2] = 5333333,
7529 [3] = 6400000,
7530 [4] = 2666667,
7531 [5] = 4266667,
7532 };
7533 const unsigned int *vco_table;
7534 unsigned int vco;
7535 uint8_t tmp = 0;
7536
7537 /* FIXME other chipsets? */
7538 if (IS_GM45(dev))
7539 vco_table = ctg_vco;
7540 else if (IS_G4X(dev))
7541 vco_table = elk_vco;
7542 else if (IS_CRESTLINE(dev))
7543 vco_table = cl_vco;
7544 else if (IS_PINEVIEW(dev))
7545 vco_table = pnv_vco;
7546 else if (IS_G33(dev))
7547 vco_table = blb_vco;
7548 else
7549 return 0;
7550
7551 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7552
7553 vco = vco_table[tmp & 0x7];
7554 if (vco == 0)
7555 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7556 else
7557 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7558
7559 return vco;
7560}
7561
7562static int gm45_get_display_clock_speed(struct drm_device *dev)
7563{
David Weinehall52a05c32016-08-22 13:32:44 +03007564 struct pci_dev *pdev = dev->pdev;
Ville Syrjälä34edce22015-05-22 11:22:33 +03007565 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7566 uint16_t tmp = 0;
7567
David Weinehall52a05c32016-08-22 13:32:44 +03007568 pci_read_config_word(pdev, GCFGC, &tmp);
Ville Syrjälä34edce22015-05-22 11:22:33 +03007569
7570 cdclk_sel = (tmp >> 12) & 0x1;
7571
7572 switch (vco) {
7573 case 2666667:
7574 case 4000000:
7575 case 5333333:
7576 return cdclk_sel ? 333333 : 222222;
7577 case 3200000:
7578 return cdclk_sel ? 320000 : 228571;
7579 default:
7580 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7581 return 222222;
7582 }
7583}
7584
7585static int i965gm_get_display_clock_speed(struct drm_device *dev)
7586{
David Weinehall52a05c32016-08-22 13:32:44 +03007587 struct pci_dev *pdev = dev->pdev;
Ville Syrjälä34edce22015-05-22 11:22:33 +03007588 static const uint8_t div_3200[] = { 16, 10, 8 };
7589 static const uint8_t div_4000[] = { 20, 12, 10 };
7590 static const uint8_t div_5333[] = { 24, 16, 14 };
7591 const uint8_t *div_table;
7592 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7593 uint16_t tmp = 0;
7594
David Weinehall52a05c32016-08-22 13:32:44 +03007595 pci_read_config_word(pdev, GCFGC, &tmp);
Ville Syrjälä34edce22015-05-22 11:22:33 +03007596
7597 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7598
7599 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7600 goto fail;
7601
7602 switch (vco) {
7603 case 3200000:
7604 div_table = div_3200;
7605 break;
7606 case 4000000:
7607 div_table = div_4000;
7608 break;
7609 case 5333333:
7610 div_table = div_5333;
7611 break;
7612 default:
7613 goto fail;
7614 }
7615
7616 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7617
Damien Lespiaucaf4e252015-06-04 16:56:18 +01007618fail:
Ville Syrjälä34edce22015-05-22 11:22:33 +03007619 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7620 return 200000;
7621}
7622
7623static int g33_get_display_clock_speed(struct drm_device *dev)
7624{
David Weinehall52a05c32016-08-22 13:32:44 +03007625 struct pci_dev *pdev = dev->pdev;
Ville Syrjälä34edce22015-05-22 11:22:33 +03007626 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7627 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7628 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7629 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7630 const uint8_t *div_table;
7631 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7632 uint16_t tmp = 0;
7633
David Weinehall52a05c32016-08-22 13:32:44 +03007634 pci_read_config_word(pdev, GCFGC, &tmp);
Ville Syrjälä34edce22015-05-22 11:22:33 +03007635
7636 cdclk_sel = (tmp >> 4) & 0x7;
7637
7638 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7639 goto fail;
7640
7641 switch (vco) {
7642 case 3200000:
7643 div_table = div_3200;
7644 break;
7645 case 4000000:
7646 div_table = div_4000;
7647 break;
7648 case 4800000:
7649 div_table = div_4800;
7650 break;
7651 case 5333333:
7652 div_table = div_5333;
7653 break;
7654 default:
7655 goto fail;
7656 }
7657
7658 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7659
Damien Lespiaucaf4e252015-06-04 16:56:18 +01007660fail:
Ville Syrjälä34edce22015-05-22 11:22:33 +03007661 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7662 return 190476;
7663}
7664
Zhenyu Wang2c072452009-06-05 15:38:42 +08007665static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007666intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08007667{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007668 while (*num > DATA_LINK_M_N_MASK ||
7669 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08007670 *num >>= 1;
7671 *den >>= 1;
7672 }
7673}
7674
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007675static void compute_m_n(unsigned int m, unsigned int n,
7676 uint32_t *ret_m, uint32_t *ret_n)
7677{
7678 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7679 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7680 intel_reduce_m_n_ratio(ret_m, ret_n);
7681}
7682
Daniel Vettere69d0bc2012-11-29 15:59:36 +01007683void
7684intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7685 int pixel_clock, int link_clock,
7686 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08007687{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01007688 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007689
7690 compute_m_n(bits_per_pixel * pixel_clock,
7691 link_clock * nlanes * 8,
7692 &m_n->gmch_m, &m_n->gmch_n);
7693
7694 compute_m_n(pixel_clock, link_clock,
7695 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08007696}
7697
Chris Wilsona7615032011-01-12 17:04:08 +00007698static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7699{
Jani Nikulad330a952014-01-21 11:24:25 +02007700 if (i915.panel_use_ssc >= 0)
7701 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03007702 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07007703 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00007704}
7705
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007706static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007707{
Daniel Vetter7df00d72013-05-21 21:54:55 +02007708 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007709}
Daniel Vetterf47709a2013-03-28 10:42:02 +01007710
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007711static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7712{
7713 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007714}
7715
Daniel Vetterf47709a2013-03-28 10:42:02 +01007716static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007717 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03007718 struct dpll *reduced_clock)
Jesse Barnesa7516a02011-12-15 12:30:37 -08007719{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007720 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007721 u32 fp, fp2 = 0;
7722
7723 if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007724 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007725 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007726 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007727 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007728 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007729 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007730 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007731 }
7732
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007733 crtc_state->dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007734
Daniel Vetterf47709a2013-03-28 10:42:02 +01007735 crtc->lowfreq_avail = false;
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03007736 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Rodrigo Viviab585de2015-03-24 12:40:09 -07007737 reduced_clock) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007738 crtc_state->dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007739 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007740 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007741 crtc_state->dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007742 }
7743}
7744
Chon Ming Lee5e69f972013-09-05 20:41:49 +08007745static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7746 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07007747{
7748 u32 reg_val;
7749
7750 /*
7751 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7752 * and set it to a reasonable value instead.
7753 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007754 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007755 reg_val &= 0xffffff00;
7756 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007757 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007758
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007759 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007760 reg_val &= 0x8cffffff;
7761 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007762 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007763
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007764 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007765 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007766 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007767
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007768 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007769 reg_val &= 0x00ffffff;
7770 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007771 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007772}
7773
Daniel Vetterb5518422013-05-03 11:49:48 +02007774static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7775 struct intel_link_m_n *m_n)
7776{
7777 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01007778 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetterb5518422013-05-03 11:49:48 +02007779 int pipe = crtc->pipe;
7780
Daniel Vettere3b95f12013-05-03 11:49:49 +02007781 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7782 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7783 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7784 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02007785}
7786
7787static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07007788 struct intel_link_m_n *m_n,
7789 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02007790{
7791 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01007792 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetterb5518422013-05-03 11:49:48 +02007793 int pipe = crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007794 enum transcoder transcoder = crtc->config->cpu_transcoder;
Daniel Vetterb5518422013-05-03 11:49:48 +02007795
7796 if (INTEL_INFO(dev)->gen >= 5) {
7797 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7798 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7799 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7800 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07007801 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7802 * for gen < 8) and if DRRS is supported (to make sure the
7803 * registers are not unnecessarily accessed).
7804 */
Durgadoss R44395bf2015-02-13 15:33:02 +05307805 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007806 crtc->config->has_drrs) {
Vandana Kannanf769cd22014-08-05 07:51:22 -07007807 I915_WRITE(PIPE_DATA_M2(transcoder),
7808 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7809 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7810 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7811 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7812 }
Daniel Vetterb5518422013-05-03 11:49:48 +02007813 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02007814 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7815 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7816 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7817 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02007818 }
7819}
7820
Ramalingam Cfe3cd482015-02-13 15:32:59 +05307821void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02007822{
Ramalingam Cfe3cd482015-02-13 15:32:59 +05307823 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7824
7825 if (m_n == M1_N1) {
7826 dp_m_n = &crtc->config->dp_m_n;
7827 dp_m2_n2 = &crtc->config->dp_m2_n2;
7828 } else if (m_n == M2_N2) {
7829
7830 /*
7831 * M2_N2 registers are not supported. Hence m2_n2 divider value
7832 * needs to be programmed into M1_N1.
7833 */
7834 dp_m_n = &crtc->config->dp_m2_n2;
7835 } else {
7836 DRM_ERROR("Unsupported divider value\n");
7837 return;
7838 }
7839
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007840 if (crtc->config->has_pch_encoder)
7841 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02007842 else
Ramalingam Cfe3cd482015-02-13 15:32:59 +05307843 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02007844}
7845
Daniel Vetter251ac862015-06-18 10:30:24 +02007846static void vlv_compute_dpll(struct intel_crtc *crtc,
7847 struct intel_crtc_state *pipe_config)
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007848{
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02007849 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007850 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02007851 if (crtc->pipe != PIPE_A)
7852 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007853
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007854 /* DPLL not used with DSI, but still need the rest set up */
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03007855 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007856 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7857 DPLL_EXT_BUFFER_ENABLE_VLV;
7858
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02007859 pipe_config->dpll_hw_state.dpll_md =
7860 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7861}
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007862
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02007863static void chv_compute_dpll(struct intel_crtc *crtc,
7864 struct intel_crtc_state *pipe_config)
7865{
7866 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007867 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02007868 if (crtc->pipe != PIPE_A)
7869 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7870
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007871 /* DPLL not used with DSI, but still need the rest set up */
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +03007872 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007873 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7874
Ville Syrjälä03ed5cbf2016-03-15 16:39:55 +02007875 pipe_config->dpll_hw_state.dpll_md =
7876 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007877}
7878
Ville Syrjäläd288f652014-10-28 13:20:22 +02007879static void vlv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007880 const struct intel_crtc_state *pipe_config)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007881{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007882 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01007883 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007884 enum pipe pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007885 u32 mdiv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007886 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007887 u32 coreclk, reg_val;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007888
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007889 /* Enable Refclk */
7890 I915_WRITE(DPLL(pipe),
7891 pipe_config->dpll_hw_state.dpll &
7892 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7893
7894 /* No need to actually set up the DPLL with DSI */
7895 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7896 return;
7897
Ville Syrjäläa5805162015-05-26 20:42:30 +03007898 mutex_lock(&dev_priv->sb_lock);
Daniel Vetter09153002012-12-12 14:06:44 +01007899
Ville Syrjäläd288f652014-10-28 13:20:22 +02007900 bestn = pipe_config->dpll.n;
7901 bestm1 = pipe_config->dpll.m1;
7902 bestm2 = pipe_config->dpll.m2;
7903 bestp1 = pipe_config->dpll.p1;
7904 bestp2 = pipe_config->dpll.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007905
Jesse Barnes89b667f2013-04-18 14:51:36 -07007906 /* See eDP HDMI DPIO driver vbios notes doc */
7907
7908 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007909 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08007910 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007911
7912 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007914
7915 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007916 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007917 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007918 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007919
7920 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007921 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007922
7923 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007924 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7925 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7926 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007927 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07007928
7929 /*
7930 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7931 * but we don't support that).
7932 * Note: don't use the DAC post divider as it seems unstable.
7933 */
7934 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007936
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007937 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007939
Jesse Barnes89b667f2013-04-18 14:51:36 -07007940 /* Set HBR and RBR LPF coefficients */
Ville Syrjäläd288f652014-10-28 13:20:22 +02007941 if (pipe_config->port_clock == 162000 ||
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03007942 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7943 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b01202013-07-05 19:21:38 +03007945 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007946 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007948 0x00d0000f);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007949
Ville Syrjälä37a56502016-06-22 21:57:04 +03007950 if (intel_crtc_has_dp_encoder(pipe_config)) {
Jesse Barnes89b667f2013-04-18 14:51:36 -07007951 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007952 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007954 0x0df40000);
7955 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007957 0x0df70000);
7958 } else { /* HDMI or VGA */
7959 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007960 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007962 0x0df70000);
7963 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007964 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007965 0x0df40000);
7966 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007967
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007968 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007969 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
Ville Syrjälä2210ce72016-06-22 21:57:05 +03007970 if (intel_crtc_has_dp_encoder(crtc->config))
Jesse Barnes89b667f2013-04-18 14:51:36 -07007971 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007973
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Ville Syrjäläa5805162015-05-26 20:42:30 +03007975 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007976}
7977
Ville Syrjäläd288f652014-10-28 13:20:22 +02007978static void chv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007979 const struct intel_crtc_state *pipe_config)
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007980{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007981 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01007982 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007983 enum pipe pipe = crtc->pipe;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007984 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307985 u32 loopfilter, tribuf_calcntr;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007986 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307987 u32 dpio_val;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307988 int vco;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007989
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +03007990 /* Enable Refclk and SSC */
7991 I915_WRITE(DPLL(pipe),
7992 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7993
7994 /* No need to actually set up the DPLL with DSI */
7995 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7996 return;
7997
Ville Syrjäläd288f652014-10-28 13:20:22 +02007998 bestn = pipe_config->dpll.n;
7999 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8000 bestm1 = pipe_config->dpll.m1;
8001 bestm2 = pipe_config->dpll.m2 >> 22;
8002 bestp1 = pipe_config->dpll.p1;
8003 bestp2 = pipe_config->dpll.p2;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05308004 vco = pipe_config->dpll.vco;
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05308005 dpio_val = 0;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05308006 loopfilter = 0;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008007
Ville Syrjäläa5805162015-05-26 20:42:30 +03008008 mutex_lock(&dev_priv->sb_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008009
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008010 /* p1 and p2 divider */
8011 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8012 5 << DPIO_CHV_S1_DIV_SHIFT |
8013 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8014 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8015 1 << DPIO_CHV_K_DIV_SHIFT);
8016
8017 /* Feedback post-divider - m2 */
8018 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8019
8020 /* Feedback refclk divider - n and m1 */
8021 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8022 DPIO_CHV_M1_DIV_BY_2 |
8023 1 << DPIO_CHV_N_DIV_SHIFT);
8024
8025 /* M2 fraction division */
Ville Syrjälä25a25df2015-07-08 23:45:47 +03008026 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008027
8028 /* M2 fraction division enable */
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05308029 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8030 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8031 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8032 if (bestm2_frac)
8033 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8034 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008035
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05308036 /* Program digital lock detect threshold */
8037 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8038 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8039 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8040 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8041 if (!bestm2_frac)
8042 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8043 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8044
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008045 /* Loop filter */
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05308046 if (vco == 5400000) {
8047 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8048 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8049 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8050 tribuf_calcntr = 0x9;
8051 } else if (vco <= 6200000) {
8052 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8053 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8054 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8055 tribuf_calcntr = 0x9;
8056 } else if (vco <= 6480000) {
8057 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8058 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8059 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8060 tribuf_calcntr = 0x8;
8061 } else {
8062 /* Not supported. Apply the same limits as in the max case */
8063 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8064 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8065 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8066 tribuf_calcntr = 0;
8067 }
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008068 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8069
Ville Syrjälä968040b2015-03-11 22:52:08 +02008070 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05308071 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8072 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8073 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8074
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008075 /* AFC Recal */
8076 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8077 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8078 DPIO_AFC_RECAL);
8079
Ville Syrjäläa5805162015-05-26 20:42:30 +03008080 mutex_unlock(&dev_priv->sb_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008081}
8082
Ville Syrjäläd288f652014-10-28 13:20:22 +02008083/**
8084 * vlv_force_pll_on - forcibly enable just the PLL
8085 * @dev_priv: i915 private structure
8086 * @pipe: pipe PLL to enable
8087 * @dpll: PLL configuration
8088 *
8089 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8090 * in cases where we need the PLL enabled even when @pipe is not going to
8091 * be enabled.
8092 */
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +00008093int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8094 const struct dpll *dpll)
Ville Syrjäläd288f652014-10-28 13:20:22 +02008095{
8096 struct intel_crtc *crtc =
8097 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +00008098 struct intel_crtc_state *pipe_config;
8099
8100 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8101 if (!pipe_config)
8102 return -ENOMEM;
8103
8104 pipe_config->base.crtc = &crtc->base;
8105 pipe_config->pixel_multiplier = 1;
8106 pipe_config->dpll = *dpll;
Ville Syrjäläd288f652014-10-28 13:20:22 +02008107
8108 if (IS_CHERRYVIEW(dev)) {
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +00008109 chv_compute_dpll(crtc, pipe_config);
8110 chv_prepare_pll(crtc, pipe_config);
8111 chv_enable_pll(crtc, pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +02008112 } else {
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +00008113 vlv_compute_dpll(crtc, pipe_config);
8114 vlv_prepare_pll(crtc, pipe_config);
8115 vlv_enable_pll(crtc, pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +02008116 }
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +00008117
8118 kfree(pipe_config);
8119
8120 return 0;
Ville Syrjäläd288f652014-10-28 13:20:22 +02008121}
8122
8123/**
8124 * vlv_force_pll_off - forcibly disable just the PLL
8125 * @dev_priv: i915 private structure
8126 * @pipe: pipe PLL to disable
8127 *
8128 * Disable the PLL for @pipe. To be used in cases where we need
8129 * the PLL enabled even when @pipe is not going to be enabled.
8130 */
8131void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8132{
8133 if (IS_CHERRYVIEW(dev))
8134 chv_disable_pll(to_i915(dev), pipe);
8135 else
8136 vlv_disable_pll(to_i915(dev), pipe);
8137}
8138
Daniel Vetter251ac862015-06-18 10:30:24 +02008139static void i9xx_compute_dpll(struct intel_crtc *crtc,
8140 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03008141 struct dpll *reduced_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008142{
Daniel Vetterf47709a2013-03-28 10:42:02 +01008143 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008144 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008145 u32 dpll;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008146 struct dpll *clock = &crtc_state->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008147
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008148 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05308149
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008150 dpll = DPLL_VGA_MODE_DIS;
8151
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008152 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008153 dpll |= DPLLB_MODE_LVDS;
8154 else
8155 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01008156
Daniel Vetteref1b4602013-06-01 17:17:04 +02008157 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008158 dpll |= (crtc_state->pixel_multiplier - 1)
Daniel Vetter198a037f2013-04-19 11:14:37 +02008159 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008160 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02008161
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03008162 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8163 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
Daniel Vetter4a33e482013-07-06 12:52:05 +02008164 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02008165
Ville Syrjälä37a56502016-06-22 21:57:04 +03008166 if (intel_crtc_has_dp_encoder(crtc_state))
Daniel Vetter4a33e482013-07-06 12:52:05 +02008167 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008168
8169 /* compute bitmask from p1 value */
8170 if (IS_PINEVIEW(dev))
8171 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8172 else {
8173 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8174 if (IS_G4X(dev) && reduced_clock)
8175 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8176 }
8177 switch (clock->p2) {
8178 case 5:
8179 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8180 break;
8181 case 7:
8182 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8183 break;
8184 case 10:
8185 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8186 break;
8187 case 14:
8188 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8189 break;
8190 }
8191 if (INTEL_INFO(dev)->gen >= 4)
8192 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8193
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008194 if (crtc_state->sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008195 dpll |= PLL_REF_INPUT_TVCLKINBC;
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008196 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Ander Conselvan de Oliveiraceb41002016-03-21 18:00:02 +02008197 intel_panel_use_ssc(dev_priv))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008198 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8199 else
8200 dpll |= PLL_REF_INPUT_DREFCLK;
8201
8202 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008203 crtc_state->dpll_hw_state.dpll = dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008204
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008205 if (INTEL_INFO(dev)->gen >= 4) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008206 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02008207 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008208 crtc_state->dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008209 }
8210}
8211
Daniel Vetter251ac862015-06-18 10:30:24 +02008212static void i8xx_compute_dpll(struct intel_crtc *crtc,
8213 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03008214 struct dpll *reduced_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008215{
Daniel Vetterf47709a2013-03-28 10:42:02 +01008216 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008217 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008218 u32 dpll;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008219 struct dpll *clock = &crtc_state->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008220
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008221 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05308222
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008223 dpll = DPLL_VGA_MODE_DIS;
8224
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008225 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008226 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8227 } else {
8228 if (clock->p1 == 2)
8229 dpll |= PLL_P1_DIVIDE_BY_TWO;
8230 else
8231 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232 if (clock->p2 == 4)
8233 dpll |= PLL_P2_DIVIDE_BY_4;
8234 }
8235
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008236 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
Daniel Vetter4a33e482013-07-06 12:52:05 +02008237 dpll |= DPLL_DVO_2X_MODE;
8238
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008239 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Ander Conselvan de Oliveiraceb41002016-03-21 18:00:02 +02008240 intel_panel_use_ssc(dev_priv))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008241 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8242 else
8243 dpll |= PLL_REF_INPUT_DREFCLK;
8244
8245 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008246 crtc_state->dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02008247}
8248
Daniel Vetter8a654f32013-06-01 17:16:22 +02008249static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008250{
8251 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008252 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008253 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008254 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03008255 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02008256 uint32_t crtc_vtotal, crtc_vblank_end;
8257 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02008258
8259 /* We need to be careful not to changed the adjusted mode, for otherwise
8260 * the hw state checker will get angry at the mismatch. */
8261 crtc_vtotal = adjusted_mode->crtc_vtotal;
8262 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008263
Ville Syrjälä609aeac2014-03-28 23:29:30 +02008264 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008265 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02008266 crtc_vtotal -= 1;
8267 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02008268
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008269 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
Ville Syrjälä609aeac2014-03-28 23:29:30 +02008270 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8271 else
8272 vsyncshift = adjusted_mode->crtc_hsync_start -
8273 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02008274 if (vsyncshift < 0)
8275 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008276 }
8277
8278 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008279 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008280
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008281 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008282 (adjusted_mode->crtc_hdisplay - 1) |
8283 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008284 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008285 (adjusted_mode->crtc_hblank_start - 1) |
8286 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008287 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008288 (adjusted_mode->crtc_hsync_start - 1) |
8289 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8290
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008291 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008292 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02008293 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008294 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008295 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02008296 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008297 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008298 (adjusted_mode->crtc_vsync_start - 1) |
8299 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8300
Paulo Zanonib5e508d2012-10-24 11:34:43 -02008301 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8302 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8303 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8304 * bits. */
8305 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8306 (pipe == PIPE_B || pipe == PIPE_C))
8307 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8308
Jani Nikulabc58be62016-03-18 17:05:39 +02008309}
8310
8311static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8312{
8313 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008314 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikulabc58be62016-03-18 17:05:39 +02008315 enum pipe pipe = intel_crtc->pipe;
8316
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008317 /* pipesrc controls the size that is scaled from, which should
8318 * always be the user's requested size.
8319 */
8320 I915_WRITE(PIPESRC(pipe),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008321 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8322 (intel_crtc->config->pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03008323}
8324
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008325static void intel_get_pipe_timings(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008326 struct intel_crtc_state *pipe_config)
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008327{
8328 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008329 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008330 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8331 uint32_t tmp;
8332
8333 tmp = I915_READ(HTOTAL(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008334 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8335 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008336 tmp = I915_READ(HBLANK(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008337 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8338 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008339 tmp = I915_READ(HSYNC(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008340 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8341 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008342
8343 tmp = I915_READ(VTOTAL(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008344 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8345 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008346 tmp = I915_READ(VBLANK(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008347 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8348 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008349 tmp = I915_READ(VSYNC(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008350 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8351 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008352
8353 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008354 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8355 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8356 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008357 }
Jani Nikulabc58be62016-03-18 17:05:39 +02008358}
8359
8360static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8361 struct intel_crtc_state *pipe_config)
8362{
8363 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008364 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikulabc58be62016-03-18 17:05:39 +02008365 u32 tmp;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008366
8367 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03008368 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8369 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8370
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008371 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8372 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008373}
8374
Daniel Vetterf6a83282014-02-11 15:28:57 -08008375void intel_mode_from_pipe_config(struct drm_display_mode *mode,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008376 struct intel_crtc_state *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03008377{
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008378 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8379 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8380 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8381 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03008382
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008383 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8384 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8385 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8386 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03008387
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008388 mode->flags = pipe_config->base.adjusted_mode.flags;
Maarten Lankhorstcd13f5a2015-07-14 14:12:02 +02008389 mode->type = DRM_MODE_TYPE_DRIVER;
Jesse Barnesbabea612013-06-26 18:57:38 +03008390
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02008391 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8392 mode->flags |= pipe_config->base.adjusted_mode.flags;
Maarten Lankhorstcd13f5a2015-07-14 14:12:02 +02008393
8394 mode->hsync = drm_mode_hsync(mode);
8395 mode->vrefresh = drm_mode_vrefresh(mode);
8396 drm_mode_set_name(mode);
Jesse Barnesbabea612013-06-26 18:57:38 +03008397}
8398
Daniel Vetter84b046f2013-02-19 18:48:54 +01008399static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8400{
8401 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008402 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter84b046f2013-02-19 18:48:54 +01008403 uint32_t pipeconf;
8404
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02008405 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01008406
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03008407 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8408 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8409 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
Daniel Vetter67c72a12013-09-24 11:46:14 +02008410
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008411 if (intel_crtc->config->double_wide)
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03008412 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01008413
Daniel Vetterff9ce462013-04-24 14:57:17 +02008414 /* only g4x and later have fancy bpc/dither controls */
Wayne Boyer666a4532015-12-09 12:29:35 -08008415 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02008416 /* Bspec claims that we can't use dithering for 30bpp pipes. */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008417 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
Daniel Vetterff9ce462013-04-24 14:57:17 +02008418 pipeconf |= PIPECONF_DITHER_EN |
8419 PIPECONF_DITHER_TYPE_SP;
8420
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008421 switch (intel_crtc->config->pipe_bpp) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02008422 case 18:
8423 pipeconf |= PIPECONF_6BPC;
8424 break;
8425 case 24:
8426 pipeconf |= PIPECONF_8BPC;
8427 break;
8428 case 30:
8429 pipeconf |= PIPECONF_10BPC;
8430 break;
8431 default:
8432 /* Case prevented by intel_choose_pipe_bpp_dither. */
8433 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01008434 }
8435 }
8436
8437 if (HAS_PIPE_CXSR(dev)) {
8438 if (intel_crtc->lowfreq_avail) {
8439 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8440 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8441 } else {
8442 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01008443 }
8444 }
8445
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008446 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02008447 if (INTEL_INFO(dev)->gen < 4 ||
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008448 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02008449 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8450 else
8451 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8452 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01008453 pipeconf |= PIPECONF_PROGRESSIVE;
8454
Wayne Boyer666a4532015-12-09 12:29:35 -08008455 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8456 intel_crtc->config->limited_color_range)
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02008457 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03008458
Daniel Vetter84b046f2013-02-19 18:48:54 +01008459 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8460 POSTING_READ(PIPECONF(intel_crtc->pipe));
8461}
8462
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008463static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8464 struct intel_crtc_state *crtc_state)
8465{
8466 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008467 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03008468 const struct intel_limit *limit;
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008469 int refclk = 48000;
8470
8471 memset(&crtc_state->dpll_hw_state, 0,
8472 sizeof(crtc_state->dpll_hw_state));
8473
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008474 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008475 if (intel_panel_use_ssc(dev_priv)) {
8476 refclk = dev_priv->vbt.lvds_ssc_freq;
8477 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8478 }
8479
8480 limit = &intel_limits_i8xx_lvds;
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008481 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008482 limit = &intel_limits_i8xx_dvo;
8483 } else {
8484 limit = &intel_limits_i8xx_dac;
8485 }
8486
8487 if (!crtc_state->clock_set &&
8488 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8489 refclk, NULL, &crtc_state->dpll)) {
8490 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8491 return -EINVAL;
8492 }
8493
8494 i8xx_compute_dpll(crtc, crtc_state, NULL);
8495
8496 return 0;
8497}
8498
Ander Conselvan de Oliveira19ec6692016-03-21 18:00:15 +02008499static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8500 struct intel_crtc_state *crtc_state)
8501{
8502 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008503 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03008504 const struct intel_limit *limit;
Ander Conselvan de Oliveira19ec6692016-03-21 18:00:15 +02008505 int refclk = 96000;
8506
8507 memset(&crtc_state->dpll_hw_state, 0,
8508 sizeof(crtc_state->dpll_hw_state));
8509
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008510 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Ander Conselvan de Oliveira19ec6692016-03-21 18:00:15 +02008511 if (intel_panel_use_ssc(dev_priv)) {
8512 refclk = dev_priv->vbt.lvds_ssc_freq;
8513 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8514 }
8515
8516 if (intel_is_dual_link_lvds(dev))
8517 limit = &intel_limits_g4x_dual_channel_lvds;
8518 else
8519 limit = &intel_limits_g4x_single_channel_lvds;
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008520 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8521 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
Ander Conselvan de Oliveira19ec6692016-03-21 18:00:15 +02008522 limit = &intel_limits_g4x_hdmi;
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008523 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
Ander Conselvan de Oliveira19ec6692016-03-21 18:00:15 +02008524 limit = &intel_limits_g4x_sdvo;
8525 } else {
8526 /* The option is for other outputs */
8527 limit = &intel_limits_i9xx_sdvo;
8528 }
8529
8530 if (!crtc_state->clock_set &&
8531 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8532 refclk, NULL, &crtc_state->dpll)) {
8533 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8534 return -EINVAL;
8535 }
8536
8537 i9xx_compute_dpll(crtc, crtc_state, NULL);
8538
8539 return 0;
8540}
8541
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008542static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8543 struct intel_crtc_state *crtc_state)
Jesse Barnes79e53942008-11-07 14:24:08 -08008544{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008545 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008546 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03008547 const struct intel_limit *limit;
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008548 int refclk = 96000;
Jesse Barnes79e53942008-11-07 14:24:08 -08008549
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03008550 memset(&crtc_state->dpll_hw_state, 0,
8551 sizeof(crtc_state->dpll_hw_state));
8552
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008553 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008554 if (intel_panel_use_ssc(dev_priv)) {
8555 refclk = dev_priv->vbt.lvds_ssc_freq;
8556 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8557 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008558
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008559 limit = &intel_limits_pineview_lvds;
8560 } else {
8561 limit = &intel_limits_pineview_sdvo;
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008562 }
Jani Nikulaf2335332013-09-13 11:03:09 +03008563
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008564 if (!crtc_state->clock_set &&
8565 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8566 refclk, NULL, &crtc_state->dpll)) {
8567 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8568 return -EINVAL;
8569 }
8570
8571 i9xx_compute_dpll(crtc, crtc_state, NULL);
8572
8573 return 0;
8574}
8575
8576static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8577 struct intel_crtc_state *crtc_state)
8578{
8579 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008580 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03008581 const struct intel_limit *limit;
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008582 int refclk = 96000;
8583
8584 memset(&crtc_state->dpll_hw_state, 0,
8585 sizeof(crtc_state->dpll_hw_state));
8586
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03008587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008588 if (intel_panel_use_ssc(dev_priv)) {
8589 refclk = dev_priv->vbt.lvds_ssc_freq;
8590 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03008591 }
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +02008592
8593 limit = &intel_limits_i9xx_lvds;
8594 } else {
8595 limit = &intel_limits_i9xx_sdvo;
8596 }
8597
8598 if (!crtc_state->clock_set &&
8599 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8600 refclk, NULL, &crtc_state->dpll)) {
8601 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8602 return -EINVAL;
Daniel Vetterf47709a2013-03-28 10:42:02 +01008603 }
Eric Anholtf564048e2011-03-30 13:01:02 -07008604
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +02008605 i9xx_compute_dpll(crtc, crtc_state, NULL);
Eric Anholtf564048e2011-03-30 13:01:02 -07008606
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02008607 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07008608}
8609
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +02008610static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8611 struct intel_crtc_state *crtc_state)
8612{
8613 int refclk = 100000;
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03008614 const struct intel_limit *limit = &intel_limits_chv;
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +02008615
8616 memset(&crtc_state->dpll_hw_state, 0,
8617 sizeof(crtc_state->dpll_hw_state));
8618
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +02008619 if (!crtc_state->clock_set &&
8620 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8621 refclk, NULL, &crtc_state->dpll)) {
8622 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8623 return -EINVAL;
8624 }
8625
8626 chv_compute_dpll(crtc, crtc_state);
8627
8628 return 0;
8629}
8630
8631static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8632 struct intel_crtc_state *crtc_state)
8633{
8634 int refclk = 100000;
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03008635 const struct intel_limit *limit = &intel_limits_vlv;
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +02008636
8637 memset(&crtc_state->dpll_hw_state, 0,
8638 sizeof(crtc_state->dpll_hw_state));
8639
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +02008640 if (!crtc_state->clock_set &&
8641 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8642 refclk, NULL, &crtc_state->dpll)) {
8643 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8644 return -EINVAL;
8645 }
8646
8647 vlv_compute_dpll(crtc, crtc_state);
8648
8649 return 0;
8650}
8651
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008652static void i9xx_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008653 struct intel_crtc_state *pipe_config)
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008654{
8655 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008656 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008657 uint32_t tmp;
8658
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02008659 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8660 return;
8661
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008662 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02008663 if (!(tmp & PFIT_ENABLE))
8664 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008665
Daniel Vetter06922822013-07-11 13:35:40 +02008666 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008667 if (INTEL_INFO(dev)->gen < 4) {
8668 if (crtc->pipe != PIPE_B)
8669 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008670 } else {
8671 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8672 return;
8673 }
8674
Daniel Vetter06922822013-07-11 13:35:40 +02008675 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008676 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008677}
8678
Jesse Barnesacbec812013-09-20 11:29:32 -07008679static void vlv_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008680 struct intel_crtc_state *pipe_config)
Jesse Barnesacbec812013-09-20 11:29:32 -07008681{
8682 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008683 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesacbec812013-09-20 11:29:32 -07008684 int pipe = pipe_config->cpu_transcoder;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03008685 struct dpll clock;
Jesse Barnesacbec812013-09-20 11:29:32 -07008686 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07008687 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07008688
Ville Syrjäläb5219732016-03-15 16:40:01 +02008689 /* In case of DSI, DPLL will not be used */
8690 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
Shobhit Kumarf573de52014-07-30 20:32:37 +05308691 return;
8692
Ville Syrjäläa5805162015-05-26 20:42:30 +03008693 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08008694 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Ville Syrjäläa5805162015-05-26 20:42:30 +03008695 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnesacbec812013-09-20 11:29:32 -07008696
8697 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8698 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8699 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8700 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8701 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8702
Imre Deakdccbea32015-06-22 23:35:51 +03008703 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07008704}
8705
Damien Lespiau5724dbd2015-01-20 12:51:52 +00008706static void
8707i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8708 struct intel_initial_plane_config *plane_config)
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008709{
8710 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008711 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008712 u32 val, base, offset;
8713 int pipe = crtc->pipe, plane = crtc->plane;
8714 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00008715 unsigned int aligned_height;
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008716 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00008717 struct intel_framebuffer *intel_fb;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008718
Damien Lespiau42a7b082015-02-05 19:35:13 +00008719 val = I915_READ(DSPCNTR(plane));
8720 if (!(val & DISPLAY_PLANE_ENABLE))
8721 return;
8722
Damien Lespiaud9806c92015-01-21 14:07:19 +00008723 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00008724 if (!intel_fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008725 DRM_DEBUG_KMS("failed to alloc fb\n");
8726 return;
8727 }
8728
Damien Lespiau1b842c82015-01-21 13:50:54 +00008729 fb = &intel_fb->base;
8730
Daniel Vetter18c52472015-02-10 17:16:09 +00008731 if (INTEL_INFO(dev)->gen >= 4) {
8732 if (val & DISPPLANE_TILED) {
Damien Lespiau49af4492015-01-20 12:51:44 +00008733 plane_config->tiling = I915_TILING_X;
Daniel Vetter18c52472015-02-10 17:16:09 +00008734 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8735 }
8736 }
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008737
8738 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
Damien Lespiaub35d63f2015-01-20 12:51:50 +00008739 fourcc = i9xx_format_to_fourcc(pixel_format);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008740 fb->pixel_format = fourcc;
8741 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008742
8743 if (INTEL_INFO(dev)->gen >= 4) {
Damien Lespiau49af4492015-01-20 12:51:44 +00008744 if (plane_config->tiling)
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008745 offset = I915_READ(DSPTILEOFF(plane));
8746 else
8747 offset = I915_READ(DSPLINOFF(plane));
8748 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8749 } else {
8750 base = I915_READ(DSPADDR(plane));
8751 }
8752 plane_config->base = base;
8753
8754 val = I915_READ(PIPESRC(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008755 fb->width = ((val >> 16) & 0xfff) + 1;
8756 fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008757
8758 val = I915_READ(DSPSTRIDE(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008759 fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008760
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008761 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00008762 fb->pixel_format,
8763 fb->modifier[0]);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008764
Daniel Vetterf37b5c22015-02-10 23:12:27 +01008765 plane_config->size = fb->pitches[0] * aligned_height;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008766
Damien Lespiau2844a922015-01-20 12:51:48 +00008767 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8768 pipe_name(pipe), plane, fb->width, fb->height,
8769 fb->bits_per_pixel, base, fb->pitches[0],
8770 plane_config->size);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008771
Damien Lespiau2d140302015-02-05 17:22:18 +00008772 plane_config->fb = intel_fb;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008773}
8774
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008775static void chv_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008776 struct intel_crtc_state *pipe_config)
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008777{
8778 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008779 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008780 int pipe = pipe_config->cpu_transcoder;
8781 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03008782 struct dpll clock;
Imre Deak0d7b6b12015-07-02 14:29:58 +03008783 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008784 int refclk = 100000;
8785
Ville Syrjäläb5219732016-03-15 16:40:01 +02008786 /* In case of DSI, DPLL will not be used */
8787 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8788 return;
8789
Ville Syrjäläa5805162015-05-26 20:42:30 +03008790 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008791 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8792 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8793 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8794 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
Imre Deak0d7b6b12015-07-02 14:29:58 +03008795 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
Ville Syrjäläa5805162015-05-26 20:42:30 +03008796 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008797
8798 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
Imre Deak0d7b6b12015-07-02 14:29:58 +03008799 clock.m2 = (pll_dw0 & 0xff) << 22;
8800 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8801 clock.m2 |= pll_dw2 & 0x3fffff;
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008802 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8803 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8804 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8805
Imre Deakdccbea32015-06-22 23:35:51 +03008806 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008807}
8808
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008809static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008810 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008811{
8812 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01008813 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak17290502016-02-12 18:55:11 +02008814 enum intel_display_power_domain power_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008815 uint32_t tmp;
Imre Deak17290502016-02-12 18:55:11 +02008816 bool ret;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008817
Imre Deak17290502016-02-12 18:55:11 +02008818 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8819 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Imre Deakb5482bd2014-03-05 16:20:55 +02008820 return false;
8821
Daniel Vettere143a212013-07-04 12:01:15 +02008822 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02008823 pipe_config->shared_dpll = NULL;
Daniel Vettereccb1402013-05-22 00:50:22 +02008824
Imre Deak17290502016-02-12 18:55:11 +02008825 ret = false;
8826
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008827 tmp = I915_READ(PIPECONF(crtc->pipe));
8828 if (!(tmp & PIPECONF_ENABLE))
Imre Deak17290502016-02-12 18:55:11 +02008829 goto out;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008830
Wayne Boyer666a4532015-12-09 12:29:35 -08008831 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjälä42571ae2013-09-06 23:29:00 +03008832 switch (tmp & PIPECONF_BPC_MASK) {
8833 case PIPECONF_6BPC:
8834 pipe_config->pipe_bpp = 18;
8835 break;
8836 case PIPECONF_8BPC:
8837 pipe_config->pipe_bpp = 24;
8838 break;
8839 case PIPECONF_10BPC:
8840 pipe_config->pipe_bpp = 30;
8841 break;
8842 default:
8843 break;
8844 }
8845 }
8846
Wayne Boyer666a4532015-12-09 12:29:35 -08008847 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8848 (tmp & PIPECONF_COLOR_RANGE_SELECT))
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02008849 pipe_config->limited_color_range = true;
8850
Ville Syrjälä282740f2013-09-04 18:30:03 +03008851 if (INTEL_INFO(dev)->gen < 4)
8852 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8853
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008854 intel_get_pipe_timings(crtc, pipe_config);
Jani Nikulabc58be62016-03-18 17:05:39 +02008855 intel_get_pipe_src_size(crtc, pipe_config);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008856
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008857 i9xx_get_pfit_config(crtc, pipe_config);
8858
Daniel Vetter6c49f242013-06-06 12:45:25 +02008859 if (INTEL_INFO(dev)->gen >= 4) {
Ville Syrjäläc2317752016-03-15 16:39:56 +02008860 /* No way to read it out on pipes B and C */
8861 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8862 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8863 else
8864 tmp = I915_READ(DPLL_MD(crtc->pipe));
Daniel Vetter6c49f242013-06-06 12:45:25 +02008865 pipe_config->pixel_multiplier =
8866 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8867 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008868 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02008869 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8870 tmp = I915_READ(DPLL(crtc->pipe));
8871 pipe_config->pixel_multiplier =
8872 ((tmp & SDVO_MULTIPLIER_MASK)
8873 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8874 } else {
8875 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8876 * port and will be fixed up in the encoder->get_config
8877 * function. */
8878 pipe_config->pixel_multiplier = 1;
8879 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008880 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
Wayne Boyer666a4532015-12-09 12:29:35 -08008881 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03008882 /*
8883 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8884 * on 830. Filter it out here so that we don't
8885 * report errors due to that.
8886 */
8887 if (IS_I830(dev))
8888 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8889
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008890 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8891 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03008892 } else {
8893 /* Mask out read-only status bits. */
8894 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8895 DPLL_PORTC_READY_MASK |
8896 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008897 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008898
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008899 if (IS_CHERRYVIEW(dev))
8900 chv_crtc_clock_get(crtc, pipe_config);
8901 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07008902 vlv_crtc_clock_get(crtc, pipe_config);
8903 else
8904 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03008905
Ville Syrjälä0f646142015-08-26 19:39:18 +03008906 /*
8907 * Normally the dotclock is filled in by the encoder .get_config()
8908 * but in case the pipe is enabled w/o any ports we need a sane
8909 * default.
8910 */
8911 pipe_config->base.adjusted_mode.crtc_clock =
8912 pipe_config->port_clock / pipe_config->pixel_multiplier;
8913
Imre Deak17290502016-02-12 18:55:11 +02008914 ret = true;
8915
8916out:
8917 intel_display_power_put(dev_priv, power_domain);
8918
8919 return ret;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008920}
8921
Paulo Zanonidde86e22012-12-01 12:04:25 -02008922static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07008923{
Chris Wilsonfac5e232016-07-04 11:34:36 +01008924 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008925 struct intel_encoder *encoder;
Lyude1c1a24d2016-06-14 11:04:09 -04008926 int i;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008927 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008928 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07008929 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07008930 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07008931 bool has_ck505 = false;
8932 bool can_ssc = false;
Lyude1c1a24d2016-06-14 11:04:09 -04008933 bool using_ssc_source = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008934
8935 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01008936 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07008937 switch (encoder->type) {
8938 case INTEL_OUTPUT_LVDS:
8939 has_panel = true;
8940 has_lvds = true;
8941 break;
8942 case INTEL_OUTPUT_EDP:
8943 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03008944 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07008945 has_cpu_edp = true;
8946 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008947 default:
8948 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008949 }
8950 }
8951
Keith Packard99eb6a02011-09-26 14:29:12 -07008952 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03008953 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07008954 can_ssc = has_ck505;
8955 } else {
8956 has_ck505 = false;
8957 can_ssc = true;
8958 }
8959
Lyude1c1a24d2016-06-14 11:04:09 -04008960 /* Check if any DPLLs are using the SSC source */
8961 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8962 u32 temp = I915_READ(PCH_DPLL(i));
8963
8964 if (!(temp & DPLL_VCO_ENABLE))
8965 continue;
8966
8967 if ((temp & PLL_REF_INPUT_MASK) ==
8968 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8969 using_ssc_source = true;
8970 break;
8971 }
8972 }
8973
8974 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8975 has_panel, has_lvds, has_ck505, using_ssc_source);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008976
8977 /* Ironlake: try to setup display ref clock before DPLL
8978 * enabling. This is only under driver's control after
8979 * PCH B stepping, previous chipset stepping should be
8980 * ignoring this setting.
8981 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008982 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008983
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008984 /* As we must carefully and slowly disable/enable each source in turn,
8985 * compute the final state we want first and check if we need to
8986 * make any changes at all.
8987 */
8988 final = val;
8989 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07008990 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008991 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07008992 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008993 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8994
Daniel Vetter8c07eb62016-06-09 18:39:07 +02008995 final &= ~DREF_SSC_SOURCE_MASK;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008996 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Daniel Vetter8c07eb62016-06-09 18:39:07 +02008997 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008998
Keith Packard199e5d72011-09-22 12:01:57 -07008999 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009000 final |= DREF_SSC_SOURCE_ENABLE;
9001
9002 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9003 final |= DREF_SSC1_ENABLE;
9004
9005 if (has_cpu_edp) {
9006 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9007 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9008 else
9009 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9010 } else
9011 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Lyude1c1a24d2016-06-14 11:04:09 -04009012 } else if (using_ssc_source) {
9013 final |= DREF_SSC_SOURCE_ENABLE;
9014 final |= DREF_SSC1_ENABLE;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009015 }
9016
9017 if (final == val)
9018 return;
9019
9020 /* Always enable nonspread source */
9021 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9022
9023 if (has_ck505)
9024 val |= DREF_NONSPREAD_CK505_ENABLE;
9025 else
9026 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9027
9028 if (has_panel) {
9029 val &= ~DREF_SSC_SOURCE_MASK;
9030 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07009031
Keith Packard199e5d72011-09-22 12:01:57 -07009032 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07009033 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07009034 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009035 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02009036 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009037 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07009038
9039 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009040 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07009041 POSTING_READ(PCH_DREF_CONTROL);
9042 udelay(200);
9043
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009044 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07009045
9046 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07009047 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07009048 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07009049 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009050 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02009051 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009052 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07009053 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009054 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07009055
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009056 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07009057 POSTING_READ(PCH_DREF_CONTROL);
9058 udelay(200);
9059 } else {
Lyude1c1a24d2016-06-14 11:04:09 -04009060 DRM_DEBUG_KMS("Disabling CPU source output\n");
Keith Packard199e5d72011-09-22 12:01:57 -07009061
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009062 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07009063
9064 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009065 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07009066
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009067 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07009068 POSTING_READ(PCH_DREF_CONTROL);
9069 udelay(200);
9070
Lyude1c1a24d2016-06-14 11:04:09 -04009071 if (!using_ssc_source) {
9072 DRM_DEBUG_KMS("Disabling SSC source\n");
Keith Packard199e5d72011-09-22 12:01:57 -07009073
Lyude1c1a24d2016-06-14 11:04:09 -04009074 /* Turn off the SSC source */
9075 val &= ~DREF_SSC_SOURCE_MASK;
9076 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07009077
Lyude1c1a24d2016-06-14 11:04:09 -04009078 /* Turn off SSC1 */
9079 val &= ~DREF_SSC1_ENABLE;
9080
9081 I915_WRITE(PCH_DREF_CONTROL, val);
9082 POSTING_READ(PCH_DREF_CONTROL);
9083 udelay(200);
9084 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07009085 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07009086
9087 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07009088}
9089
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009090static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02009091{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009092 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02009093
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009094 tmp = I915_READ(SOUTH_CHICKEN2);
9095 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9096 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009097
Imre Deakcf3598c2016-06-28 13:37:31 +03009098 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9099 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009100 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02009101
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009102 tmp = I915_READ(SOUTH_CHICKEN2);
9103 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9104 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009105
Imre Deakcf3598c2016-06-28 13:37:31 +03009106 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9107 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009108 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009109}
9110
9111/* WaMPhyProgramming:hsw */
9112static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9113{
9114 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02009115
9116 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9117 tmp &= ~(0xFF << 24);
9118 tmp |= (0x12 << 24);
9119 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9120
Paulo Zanonidde86e22012-12-01 12:04:25 -02009121 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9122 tmp |= (1 << 11);
9123 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9124
9125 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9126 tmp |= (1 << 11);
9127 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9128
Paulo Zanonidde86e22012-12-01 12:04:25 -02009129 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9130 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9131 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9132
9133 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9134 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9135 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9136
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009137 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9138 tmp &= ~(7 << 13);
9139 tmp |= (5 << 13);
9140 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009141
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009142 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9143 tmp &= ~(7 << 13);
9144 tmp |= (5 << 13);
9145 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009146
9147 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9148 tmp &= ~0xFF;
9149 tmp |= 0x1C;
9150 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9151
9152 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9153 tmp &= ~0xFF;
9154 tmp |= 0x1C;
9155 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9156
9157 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9158 tmp &= ~(0xFF << 16);
9159 tmp |= (0x1C << 16);
9160 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9161
9162 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9163 tmp &= ~(0xFF << 16);
9164 tmp |= (0x1C << 16);
9165 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9166
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009167 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9168 tmp |= (1 << 27);
9169 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009170
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009171 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9172 tmp |= (1 << 27);
9173 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009174
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009175 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9176 tmp &= ~(0xF << 28);
9177 tmp |= (4 << 28);
9178 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009179
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03009180 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9181 tmp &= ~(0xF << 28);
9182 tmp |= (4 << 28);
9183 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009184}
9185
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03009186/* Implements 3 different sequences from BSpec chapter "Display iCLK
9187 * Programming" based on the parameters passed:
9188 * - Sequence to enable CLKOUT_DP
9189 * - Sequence to enable CLKOUT_DP without spread
9190 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9191 */
9192static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9193 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009194{
Chris Wilsonfac5e232016-07-04 11:34:36 +01009195 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03009196 uint32_t reg, tmp;
9197
9198 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9199 with_spread = true;
Ville Syrjäläc2699522015-08-27 23:55:59 +03009200 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03009201 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009202
Ville Syrjäläa5805162015-05-26 20:42:30 +03009203 mutex_lock(&dev_priv->sb_lock);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009204
9205 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9206 tmp &= ~SBI_SSCCTL_DISABLE;
9207 tmp |= SBI_SSCCTL_PATHALT;
9208 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9209
9210 udelay(24);
9211
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03009212 if (with_spread) {
9213 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9214 tmp &= ~SBI_SSCCTL_PATHALT;
9215 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03009216
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03009217 if (with_fdi) {
9218 lpt_reset_fdi_mphy(dev_priv);
9219 lpt_program_fdi_mphy(dev_priv);
9220 }
9221 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02009222
Ville Syrjäläc2699522015-08-27 23:55:59 +03009223 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03009224 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9225 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9226 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01009227
Ville Syrjäläa5805162015-05-26 20:42:30 +03009228 mutex_unlock(&dev_priv->sb_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02009229}
9230
Paulo Zanoni47701c32013-07-23 11:19:25 -03009231/* Sequence to disable CLKOUT_DP */
9232static void lpt_disable_clkout_dp(struct drm_device *dev)
9233{
Chris Wilsonfac5e232016-07-04 11:34:36 +01009234 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni47701c32013-07-23 11:19:25 -03009235 uint32_t reg, tmp;
9236
Ville Syrjäläa5805162015-05-26 20:42:30 +03009237 mutex_lock(&dev_priv->sb_lock);
Paulo Zanoni47701c32013-07-23 11:19:25 -03009238
Ville Syrjäläc2699522015-08-27 23:55:59 +03009239 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
Paulo Zanoni47701c32013-07-23 11:19:25 -03009240 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9241 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9242 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9243
9244 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9245 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9246 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9247 tmp |= SBI_SSCCTL_PATHALT;
9248 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9249 udelay(32);
9250 }
9251 tmp |= SBI_SSCCTL_DISABLE;
9252 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9253 }
9254
Ville Syrjäläa5805162015-05-26 20:42:30 +03009255 mutex_unlock(&dev_priv->sb_lock);
Paulo Zanoni47701c32013-07-23 11:19:25 -03009256}
9257
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02009258#define BEND_IDX(steps) ((50 + (steps)) / 5)
9259
9260static const uint16_t sscdivintphase[] = {
9261 [BEND_IDX( 50)] = 0x3B23,
9262 [BEND_IDX( 45)] = 0x3B23,
9263 [BEND_IDX( 40)] = 0x3C23,
9264 [BEND_IDX( 35)] = 0x3C23,
9265 [BEND_IDX( 30)] = 0x3D23,
9266 [BEND_IDX( 25)] = 0x3D23,
9267 [BEND_IDX( 20)] = 0x3E23,
9268 [BEND_IDX( 15)] = 0x3E23,
9269 [BEND_IDX( 10)] = 0x3F23,
9270 [BEND_IDX( 5)] = 0x3F23,
9271 [BEND_IDX( 0)] = 0x0025,
9272 [BEND_IDX( -5)] = 0x0025,
9273 [BEND_IDX(-10)] = 0x0125,
9274 [BEND_IDX(-15)] = 0x0125,
9275 [BEND_IDX(-20)] = 0x0225,
9276 [BEND_IDX(-25)] = 0x0225,
9277 [BEND_IDX(-30)] = 0x0325,
9278 [BEND_IDX(-35)] = 0x0325,
9279 [BEND_IDX(-40)] = 0x0425,
9280 [BEND_IDX(-45)] = 0x0425,
9281 [BEND_IDX(-50)] = 0x0525,
9282};
9283
9284/*
9285 * Bend CLKOUT_DP
9286 * steps -50 to 50 inclusive, in steps of 5
9287 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9288 * change in clock period = -(steps / 10) * 5.787 ps
9289 */
9290static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9291{
9292 uint32_t tmp;
9293 int idx = BEND_IDX(steps);
9294
9295 if (WARN_ON(steps % 5 != 0))
9296 return;
9297
9298 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9299 return;
9300
9301 mutex_lock(&dev_priv->sb_lock);
9302
9303 if (steps % 10 != 0)
9304 tmp = 0xAAAAAAAB;
9305 else
9306 tmp = 0x00000000;
9307 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9308
9309 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9310 tmp &= 0xffff0000;
9311 tmp |= sscdivintphase[idx];
9312 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9313
9314 mutex_unlock(&dev_priv->sb_lock);
9315}
9316
9317#undef BEND_IDX
9318
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03009319static void lpt_init_pch_refclk(struct drm_device *dev)
9320{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03009321 struct intel_encoder *encoder;
9322 bool has_vga = false;
9323
Damien Lespiaub2784e12014-08-05 11:29:37 +01009324 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03009325 switch (encoder->type) {
9326 case INTEL_OUTPUT_ANALOG:
9327 has_vga = true;
9328 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02009329 default:
9330 break;
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03009331 }
9332 }
9333
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02009334 if (has_vga) {
9335 lpt_bend_clkout_dp(to_i915(dev), 0);
Paulo Zanoni47701c32013-07-23 11:19:25 -03009336 lpt_enable_clkout_dp(dev, true, true);
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02009337 } else {
Paulo Zanoni47701c32013-07-23 11:19:25 -03009338 lpt_disable_clkout_dp(dev);
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02009339 }
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03009340}
9341
Paulo Zanonidde86e22012-12-01 12:04:25 -02009342/*
9343 * Initialize reference clocks when the driver loads
9344 */
9345void intel_init_pch_refclk(struct drm_device *dev)
9346{
9347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9348 ironlake_init_pch_refclk(dev);
9349 else if (HAS_PCH_LPT(dev))
9350 lpt_init_pch_refclk(dev);
9351}
9352
Daniel Vetter6ff93602013-04-19 11:24:36 +02009353static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03009354{
Chris Wilsonfac5e232016-07-04 11:34:36 +01009355 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Paulo Zanonic8203562012-09-12 10:06:29 -03009356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9357 int pipe = intel_crtc->pipe;
9358 uint32_t val;
9359
Daniel Vetter78114072013-06-13 00:54:57 +02009360 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03009361
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009362 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03009363 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01009364 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03009365 break;
9366 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01009367 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03009368 break;
9369 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01009370 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03009371 break;
9372 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01009373 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03009374 break;
9375 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03009376 /* Case prevented by intel_choose_pipe_bpp_dither. */
9377 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03009378 }
9379
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009380 if (intel_crtc->config->dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03009381 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9382
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009383 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03009384 val |= PIPECONF_INTERLACED_ILK;
9385 else
9386 val |= PIPECONF_PROGRESSIVE;
9387
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009388 if (intel_crtc->config->limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02009389 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02009390
Paulo Zanonic8203562012-09-12 10:06:29 -03009391 I915_WRITE(PIPECONF(pipe), val);
9392 POSTING_READ(PIPECONF(pipe));
9393}
9394
Daniel Vetter6ff93602013-04-19 11:24:36 +02009395static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03009396{
Chris Wilsonfac5e232016-07-04 11:34:36 +01009397 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03009398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009399 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Jani Nikula391bf042016-03-18 17:05:40 +02009400 u32 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03009401
Jani Nikula391bf042016-03-18 17:05:40 +02009402 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03009403 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9404
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009405 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03009406 val |= PIPECONF_INTERLACED_ILK;
9407 else
9408 val |= PIPECONF_PROGRESSIVE;
9409
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009410 I915_WRITE(PIPECONF(cpu_transcoder), val);
9411 POSTING_READ(PIPECONF(cpu_transcoder));
Jani Nikula391bf042016-03-18 17:05:40 +02009412}
9413
Jani Nikula391bf042016-03-18 17:05:40 +02009414static void haswell_set_pipemisc(struct drm_crtc *crtc)
9415{
Chris Wilsonfac5e232016-07-04 11:34:36 +01009416 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Jani Nikula391bf042016-03-18 17:05:40 +02009417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9418
9419 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9420 u32 val = 0;
Paulo Zanoni756f85c2013-11-02 21:07:38 -07009421
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009422 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07009423 case 18:
9424 val |= PIPEMISC_DITHER_6_BPC;
9425 break;
9426 case 24:
9427 val |= PIPEMISC_DITHER_8_BPC;
9428 break;
9429 case 30:
9430 val |= PIPEMISC_DITHER_10_BPC;
9431 break;
9432 case 36:
9433 val |= PIPEMISC_DITHER_12_BPC;
9434 break;
9435 default:
9436 /* Case prevented by pipe_config_set_bpp. */
9437 BUG();
9438 }
9439
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009440 if (intel_crtc->config->dither)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07009441 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9442
Jani Nikula391bf042016-03-18 17:05:40 +02009443 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07009444 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03009445}
9446
Paulo Zanonid4b19312012-11-29 11:29:32 -02009447int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9448{
9449 /*
9450 * Account for spread spectrum to avoid
9451 * oversubscribing the link. Max center spread
9452 * is 2.5%; use 5% for safety's sake.
9453 */
9454 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02009455 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02009456}
9457
Daniel Vetter7429e9d2013-04-20 17:19:46 +02009458static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02009459{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02009460 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03009461}
9462
Ander Conselvan de Oliveirab75ca6f2016-03-21 18:00:11 +02009463static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9464 struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03009465 struct dpll *reduced_clock)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03009466{
9467 struct drm_crtc *crtc = &intel_crtc->base;
9468 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009469 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveirab75ca6f2016-03-21 18:00:11 +02009470 u32 dpll, fp, fp2;
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03009471 int factor;
Jesse Barnes79e53942008-11-07 14:24:08 -08009472
Chris Wilsonc1858122010-12-03 21:35:48 +00009473 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07009474 factor = 21;
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03009475 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Eric Anholt8febb292011-03-30 13:01:07 -07009476 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02009477 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02009478 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07009479 factor = 25;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009480 } else if (crtc_state->sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07009481 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00009482
Ander Conselvan de Oliveirab75ca6f2016-03-21 18:00:11 +02009483 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
Chris Wilsonc1858122010-12-03 21:35:48 +00009484
Ander Conselvan de Oliveirab75ca6f2016-03-21 18:00:11 +02009485 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9486 fp |= FP_CB_TUNE;
9487
9488 if (reduced_clock) {
9489 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9490
9491 if (reduced_clock->m < factor * reduced_clock->n)
9492 fp2 |= FP_CB_TUNE;
9493 } else {
9494 fp2 = fp;
9495 }
Daniel Vetter9a7c7892013-04-04 22:20:34 +02009496
Chris Wilson5eddb702010-09-11 13:48:45 +01009497 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08009498
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03009499 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
Eric Anholta07d6782011-03-30 13:01:08 -07009500 dpll |= DPLLB_MODE_LVDS;
9501 else
9502 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02009503
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009504 dpll |= (crtc_state->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02009505 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02009506
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03009507 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9508 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
Daniel Vetter4a33e482013-07-06 12:52:05 +02009509 dpll |= DPLL_SDVO_HIGH_SPEED;
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03009510
Ville Syrjälä37a56502016-06-22 21:57:04 +03009511 if (intel_crtc_has_dp_encoder(crtc_state))
Daniel Vetter4a33e482013-07-06 12:52:05 +02009512 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08009513
Eric Anholta07d6782011-03-30 13:01:08 -07009514 /* compute bitmask from p1 value */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009515 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07009516 /* also FPA1 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009517 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07009518
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009519 switch (crtc_state->dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07009520 case 5:
9521 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9522 break;
9523 case 7:
9524 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9525 break;
9526 case 10:
9527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9528 break;
9529 case 14:
9530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9531 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08009532 }
9533
Ville Syrjälä3d6e9ee2016-06-22 21:57:03 +03009534 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9535 intel_panel_use_ssc(dev_priv))
Kristian Høgsberg43565a02009-02-13 20:56:52 -05009536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08009537 else
9538 dpll |= PLL_REF_INPUT_DREFCLK;
9539
Ander Conselvan de Oliveirab75ca6f2016-03-21 18:00:11 +02009540 dpll |= DPLL_VCO_ENABLE;
9541
9542 crtc_state->dpll_hw_state.dpll = dpll;
9543 crtc_state->dpll_hw_state.fp0 = fp;
9544 crtc_state->dpll_hw_state.fp1 = fp2;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03009545}
9546
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009547static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9548 struct intel_crtc_state *crtc_state)
Jesse Barnes79e53942008-11-07 14:24:08 -08009549{
Ander Conselvan de Oliveira997c0302016-03-21 18:00:12 +02009550 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009551 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03009552 struct dpll reduced_clock;
Ander Conselvan de Oliveira7ed9f892016-03-21 18:00:07 +02009553 bool has_reduced_clock = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02009554 struct intel_shared_dpll *pll;
Ander Conselvan de Oliveira1b6f4952016-05-04 12:11:59 +03009555 const struct intel_limit *limit;
Ander Conselvan de Oliveira997c0302016-03-21 18:00:12 +02009556 int refclk = 120000;
Jesse Barnes79e53942008-11-07 14:24:08 -08009557
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03009558 memset(&crtc_state->dpll_hw_state, 0,
9559 sizeof(crtc_state->dpll_hw_state));
9560
Ander Conselvan de Oliveiraded220e2016-03-21 18:00:09 +02009561 crtc->lowfreq_avail = false;
9562
9563 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9564 if (!crtc_state->has_pch_encoder)
9565 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08009566
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03009567 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Ander Conselvan de Oliveira997c0302016-03-21 18:00:12 +02009568 if (intel_panel_use_ssc(dev_priv)) {
9569 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9570 dev_priv->vbt.lvds_ssc_freq);
9571 refclk = dev_priv->vbt.lvds_ssc_freq;
9572 }
9573
9574 if (intel_is_dual_link_lvds(dev)) {
9575 if (refclk == 100000)
9576 limit = &intel_limits_ironlake_dual_lvds_100m;
9577 else
9578 limit = &intel_limits_ironlake_dual_lvds;
9579 } else {
9580 if (refclk == 100000)
9581 limit = &intel_limits_ironlake_single_lvds_100m;
9582 else
9583 limit = &intel_limits_ironlake_single_lvds;
9584 }
9585 } else {
9586 limit = &intel_limits_ironlake_dac;
9587 }
9588
Ander Conselvan de Oliveira364ee292016-03-21 18:00:10 +02009589 if (!crtc_state->clock_set &&
Ander Conselvan de Oliveira997c0302016-03-21 18:00:12 +02009590 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9591 refclk, NULL, &crtc_state->dpll)) {
Ander Conselvan de Oliveira364ee292016-03-21 18:00:10 +02009592 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9593 return -EINVAL;
Daniel Vetterf47709a2013-03-28 10:42:02 +01009594 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009595
Ander Conselvan de Oliveirab75ca6f2016-03-21 18:00:11 +02009596 ironlake_compute_dpll(crtc, crtc_state,
9597 has_reduced_clock ? &reduced_clock : NULL);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009598
Ander Conselvan de Oliveiraded220e2016-03-21 18:00:09 +02009599 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9600 if (pll == NULL) {
9601 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9602 pipe_name(crtc->pipe));
9603 return -EINVAL;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02009604 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009605
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03009606 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Ander Conselvan de Oliveiraded220e2016-03-21 18:00:09 +02009607 has_reduced_clock)
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009608 crtc->lowfreq_avail = true;
Daniel Vettere2b78262013-06-07 23:10:03 +02009609
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02009610 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08009611}
9612
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009613static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9614 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02009615{
9616 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009617 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009618 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02009619
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009620 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9621 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9622 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9623 & ~TU_SIZE_MASK;
9624 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9625 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9626 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9627}
9628
9629static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9630 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009631 struct intel_link_m_n *m_n,
9632 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009633{
9634 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009635 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009636 enum pipe pipe = crtc->pipe;
9637
9638 if (INTEL_INFO(dev)->gen >= 5) {
9639 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9640 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9641 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9642 & ~TU_SIZE_MASK;
9643 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9644 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9645 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009646 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9647 * gen < 8) and if DRRS is supported (to make sure the
9648 * registers are not unnecessarily read).
9649 */
9650 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009651 crtc->config->has_drrs) {
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009652 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9653 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9654 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9655 & ~TU_SIZE_MASK;
9656 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9657 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9658 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9659 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009660 } else {
9661 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9662 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9663 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9664 & ~TU_SIZE_MASK;
9665 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9666 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9667 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9668 }
9669}
9670
9671void intel_dp_get_m_n(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009672 struct intel_crtc_state *pipe_config)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009673{
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02009674 if (pipe_config->has_pch_encoder)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009675 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9676 else
9677 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009678 &pipe_config->dp_m_n,
9679 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009680}
9681
Daniel Vetter72419202013-04-04 13:28:53 +02009682static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009683 struct intel_crtc_state *pipe_config)
Daniel Vetter72419202013-04-04 13:28:53 +02009684{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009685 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009686 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02009687}
9688
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009689static void skylake_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009690 struct intel_crtc_state *pipe_config)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009691{
9692 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009693 struct drm_i915_private *dev_priv = to_i915(dev);
Chandra Kondurua1b22782015-04-07 15:28:45 -07009694 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9695 uint32_t ps_ctrl = 0;
9696 int id = -1;
9697 int i;
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009698
Chandra Kondurua1b22782015-04-07 15:28:45 -07009699 /* find scaler attached to this pipe */
9700 for (i = 0; i < crtc->num_scalers; i++) {
9701 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9702 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9703 id = i;
9704 pipe_config->pch_pfit.enabled = true;
9705 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9706 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9707 break;
9708 }
9709 }
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009710
Chandra Kondurua1b22782015-04-07 15:28:45 -07009711 scaler_state->scaler_id = id;
9712 if (id >= 0) {
9713 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9714 } else {
9715 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009716 }
9717}
9718
Damien Lespiau5724dbd2015-01-20 12:51:52 +00009719static void
9720skylake_get_initial_plane_config(struct intel_crtc *crtc,
9721 struct intel_initial_plane_config *plane_config)
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009722{
9723 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009724 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau40f46282015-02-27 11:15:21 +00009725 u32 val, base, offset, stride_mult, tiling;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009726 int pipe = crtc->pipe;
9727 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00009728 unsigned int aligned_height;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009729 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00009730 struct intel_framebuffer *intel_fb;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009731
Damien Lespiaud9806c92015-01-21 14:07:19 +00009732 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00009733 if (!intel_fb) {
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009734 DRM_DEBUG_KMS("failed to alloc fb\n");
9735 return;
9736 }
9737
Damien Lespiau1b842c82015-01-21 13:50:54 +00009738 fb = &intel_fb->base;
9739
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009740 val = I915_READ(PLANE_CTL(pipe, 0));
Damien Lespiau42a7b082015-02-05 19:35:13 +00009741 if (!(val & PLANE_CTL_ENABLE))
9742 goto error;
9743
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009744 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9745 fourcc = skl_format_to_fourcc(pixel_format,
9746 val & PLANE_CTL_ORDER_RGBX,
9747 val & PLANE_CTL_ALPHA_MASK);
9748 fb->pixel_format = fourcc;
9749 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9750
Damien Lespiau40f46282015-02-27 11:15:21 +00009751 tiling = val & PLANE_CTL_TILED_MASK;
9752 switch (tiling) {
9753 case PLANE_CTL_TILED_LINEAR:
9754 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9755 break;
9756 case PLANE_CTL_TILED_X:
9757 plane_config->tiling = I915_TILING_X;
9758 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9759 break;
9760 case PLANE_CTL_TILED_Y:
9761 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9762 break;
9763 case PLANE_CTL_TILED_YF:
9764 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9765 break;
9766 default:
9767 MISSING_CASE(tiling);
9768 goto error;
9769 }
9770
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009771 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9772 plane_config->base = base;
9773
9774 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9775
9776 val = I915_READ(PLANE_SIZE(pipe, 0));
9777 fb->height = ((val >> 16) & 0xfff) + 1;
9778 fb->width = ((val >> 0) & 0x1fff) + 1;
9779
9780 val = I915_READ(PLANE_STRIDE(pipe, 0));
Ville Syrjälä7b49f942016-01-12 21:08:32 +02009781 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
Damien Lespiau40f46282015-02-27 11:15:21 +00009782 fb->pixel_format);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009783 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9784
9785 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00009786 fb->pixel_format,
9787 fb->modifier[0]);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009788
Daniel Vetterf37b5c22015-02-10 23:12:27 +01009789 plane_config->size = fb->pitches[0] * aligned_height;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009790
9791 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9792 pipe_name(pipe), fb->width, fb->height,
9793 fb->bits_per_pixel, base, fb->pitches[0],
9794 plane_config->size);
9795
Damien Lespiau2d140302015-02-05 17:22:18 +00009796 plane_config->fb = intel_fb;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009797 return;
9798
9799error:
Matthew Auldd1a3a032016-08-23 16:00:44 +01009800 kfree(intel_fb);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009801}
9802
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009803static void ironlake_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009804 struct intel_crtc_state *pipe_config)
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009805{
9806 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009807 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009808 uint32_t tmp;
9809
9810 tmp = I915_READ(PF_CTL(crtc->pipe));
9811
9812 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009813 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009814 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9815 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02009816
9817 /* We currently do not free assignements of panel fitters on
9818 * ivb/hsw (since we don't use the higher upscaling modes which
9819 * differentiates them) so just WARN about this case for now. */
9820 if (IS_GEN7(dev)) {
9821 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9822 PF_PIPE_SEL_IVB(crtc->pipe));
9823 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009824 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009825}
9826
Damien Lespiau5724dbd2015-01-20 12:51:52 +00009827static void
9828ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9829 struct intel_initial_plane_config *plane_config)
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009830{
9831 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009832 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009833 u32 val, base, offset;
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009834 int pipe = crtc->pipe;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009835 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00009836 unsigned int aligned_height;
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009837 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00009838 struct intel_framebuffer *intel_fb;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009839
Damien Lespiau42a7b082015-02-05 19:35:13 +00009840 val = I915_READ(DSPCNTR(pipe));
9841 if (!(val & DISPLAY_PLANE_ENABLE))
9842 return;
9843
Damien Lespiaud9806c92015-01-21 14:07:19 +00009844 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00009845 if (!intel_fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009846 DRM_DEBUG_KMS("failed to alloc fb\n");
9847 return;
9848 }
9849
Damien Lespiau1b842c82015-01-21 13:50:54 +00009850 fb = &intel_fb->base;
9851
Daniel Vetter18c52472015-02-10 17:16:09 +00009852 if (INTEL_INFO(dev)->gen >= 4) {
9853 if (val & DISPPLANE_TILED) {
Damien Lespiau49af4492015-01-20 12:51:44 +00009854 plane_config->tiling = I915_TILING_X;
Daniel Vetter18c52472015-02-10 17:16:09 +00009855 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9856 }
9857 }
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009858
9859 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
Damien Lespiaub35d63f2015-01-20 12:51:50 +00009860 fourcc = i9xx_format_to_fourcc(pixel_format);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009861 fb->pixel_format = fourcc;
9862 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009863
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009864 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009865 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009866 offset = I915_READ(DSPOFFSET(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009867 } else {
Damien Lespiau49af4492015-01-20 12:51:44 +00009868 if (plane_config->tiling)
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009869 offset = I915_READ(DSPTILEOFF(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009870 else
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009871 offset = I915_READ(DSPLINOFF(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009872 }
9873 plane_config->base = base;
9874
9875 val = I915_READ(PIPESRC(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009876 fb->width = ((val >> 16) & 0xfff) + 1;
9877 fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009878
9879 val = I915_READ(DSPSTRIDE(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009880 fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009881
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009882 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00009883 fb->pixel_format,
9884 fb->modifier[0]);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009885
Daniel Vetterf37b5c22015-02-10 23:12:27 +01009886 plane_config->size = fb->pitches[0] * aligned_height;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009887
Damien Lespiau2844a922015-01-20 12:51:48 +00009888 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9889 pipe_name(pipe), fb->width, fb->height,
9890 fb->bits_per_pixel, base, fb->pitches[0],
9891 plane_config->size);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009892
Damien Lespiau2d140302015-02-05 17:22:18 +00009893 plane_config->fb = intel_fb;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009894}
9895
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009896static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009897 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009898{
9899 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01009900 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak17290502016-02-12 18:55:11 +02009901 enum intel_display_power_domain power_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009902 uint32_t tmp;
Imre Deak17290502016-02-12 18:55:11 +02009903 bool ret;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009904
Imre Deak17290502016-02-12 18:55:11 +02009905 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9906 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Paulo Zanoni930e8c92014-07-04 13:38:34 -03009907 return false;
9908
Daniel Vettere143a212013-07-04 12:01:15 +02009909 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02009910 pipe_config->shared_dpll = NULL;
Daniel Vettereccb1402013-05-22 00:50:22 +02009911
Imre Deak17290502016-02-12 18:55:11 +02009912 ret = false;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009913 tmp = I915_READ(PIPECONF(crtc->pipe));
9914 if (!(tmp & PIPECONF_ENABLE))
Imre Deak17290502016-02-12 18:55:11 +02009915 goto out;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009916
Ville Syrjälä42571ae2013-09-06 23:29:00 +03009917 switch (tmp & PIPECONF_BPC_MASK) {
9918 case PIPECONF_6BPC:
9919 pipe_config->pipe_bpp = 18;
9920 break;
9921 case PIPECONF_8BPC:
9922 pipe_config->pipe_bpp = 24;
9923 break;
9924 case PIPECONF_10BPC:
9925 pipe_config->pipe_bpp = 30;
9926 break;
9927 case PIPECONF_12BPC:
9928 pipe_config->pipe_bpp = 36;
9929 break;
9930 default:
9931 break;
9932 }
9933
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02009934 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9935 pipe_config->limited_color_range = true;
9936
Daniel Vetterab9412b2013-05-03 11:49:46 +02009937 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02009938 struct intel_shared_dpll *pll;
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02009939 enum intel_dpll_id pll_id;
Daniel Vetter66e985c2013-06-05 13:34:20 +02009940
Daniel Vetter88adfff2013-03-28 10:42:01 +01009941 pipe_config->has_pch_encoder = true;
9942
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009943 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9944 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9945 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02009946
9947 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009948
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03009949 if (HAS_PCH_IBX(dev_priv)) {
Imre Deakd9a7bc62016-05-12 16:18:50 +03009950 /*
9951 * The pipe->pch transcoder and pch transcoder->pll
9952 * mapping is fixed.
9953 */
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02009954 pll_id = (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009955 } else {
9956 tmp = I915_READ(PCH_DPLL_SEL);
9957 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02009958 pll_id = DPLL_ID_PCH_PLL_B;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009959 else
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02009960 pll_id= DPLL_ID_PCH_PLL_A;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009961 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02009962
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +02009963 pipe_config->shared_dpll =
9964 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9965 pll = pipe_config->shared_dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02009966
Ander Conselvan de Oliveira2edd6442016-03-08 17:46:21 +02009967 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9968 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009969
9970 tmp = pipe_config->dpll_hw_state.dpll;
9971 pipe_config->pixel_multiplier =
9972 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9973 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03009974
9975 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009976 } else {
9977 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009978 }
9979
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009980 intel_get_pipe_timings(crtc, pipe_config);
Jani Nikulabc58be62016-03-18 17:05:39 +02009981 intel_get_pipe_src_size(crtc, pipe_config);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009982
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009983 ironlake_get_pfit_config(crtc, pipe_config);
9984
Imre Deak17290502016-02-12 18:55:11 +02009985 ret = true;
9986
9987out:
9988 intel_display_power_put(dev_priv, power_domain);
9989
9990 return ret;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009991}
9992
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009993static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9994{
Chris Wilson91c8a322016-07-05 10:40:23 +01009995 struct drm_device *dev = &dev_priv->drm;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009996 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009997
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009998 for_each_intel_crtc(dev, crtc)
Rob Clarke2c719b2014-12-15 13:56:32 -05009999 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010000 pipe_name(crtc->pipe));
10001
Rob Clarke2c719b2014-12-15 13:56:32 -050010002 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10003 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
Ville Syrjälä01403de2015-09-18 20:03:33 +030010004 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10005 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Imre Deak44cb7342016-08-10 14:07:29 +030010006 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050010007 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010008 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -030010009 if (IS_HASWELL(dev))
Rob Clarke2c719b2014-12-15 13:56:32 -050010010 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
Paulo Zanonic5107b82014-07-04 11:50:30 -030010011 "CPU PWM2 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050010012 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010013 "PCH PWM1 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050010014 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010015 "Utility pin enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050010016 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010017
Paulo Zanoni9926ada2014-04-01 19:39:47 -030010018 /*
10019 * In theory we can still leave IRQs enabled, as long as only the HPD
10020 * interrupts remain enabled. We used to check for that, but since it's
10021 * gen-specific and since we only disable LCPLL after we fully disable
10022 * the interrupts, the check below should be enough.
10023 */
Rob Clarke2c719b2014-12-15 13:56:32 -050010024 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010025}
10026
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -030010027static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10028{
Chris Wilson91c8a322016-07-05 10:40:23 +010010029 struct drm_device *dev = &dev_priv->drm;
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -030010030
10031 if (IS_HASWELL(dev))
10032 return I915_READ(D_COMP_HSW);
10033 else
10034 return I915_READ(D_COMP_BDW);
10035}
10036
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -030010037static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10038{
Chris Wilson91c8a322016-07-05 10:40:23 +010010039 struct drm_device *dev = &dev_priv->drm;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -030010040
10041 if (IS_HASWELL(dev)) {
10042 mutex_lock(&dev_priv->rps.hw_lock);
10043 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10044 val))
Chris Wilson79cf2192016-08-24 11:16:07 +010010045 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -030010046 mutex_unlock(&dev_priv->rps.hw_lock);
10047 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -030010048 I915_WRITE(D_COMP_BDW, val);
10049 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -030010050 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010051}
10052
10053/*
10054 * This function implements pieces of two sequences from BSpec:
10055 * - Sequence for display software to disable LCPLL
10056 * - Sequence for display software to allow package C8+
10057 * The steps implemented here are just the steps that actually touch the LCPLL
10058 * register. Callers should take care of disabling all the display engine
10059 * functions, doing the mode unset, fixing interrupts, etc.
10060 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -030010061static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10062 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010063{
10064 uint32_t val;
10065
10066 assert_can_disable_lcpll(dev_priv);
10067
10068 val = I915_READ(LCPLL_CTL);
10069
10070 if (switch_to_fclk) {
10071 val |= LCPLL_CD_SOURCE_FCLK;
10072 I915_WRITE(LCPLL_CTL, val);
10073
Imre Deakf53dd632016-06-28 13:37:32 +030010074 if (wait_for_us(I915_READ(LCPLL_CTL) &
10075 LCPLL_CD_SOURCE_FCLK_DONE, 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010076 DRM_ERROR("Switching to FCLK failed\n");
10077
10078 val = I915_READ(LCPLL_CTL);
10079 }
10080
10081 val |= LCPLL_PLL_DISABLE;
10082 I915_WRITE(LCPLL_CTL, val);
10083 POSTING_READ(LCPLL_CTL);
10084
Chris Wilson24d84412016-06-30 15:33:07 +010010085 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010086 DRM_ERROR("LCPLL still locked\n");
10087
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -030010088 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010089 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -030010090 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010091 ndelay(100);
10092
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -030010093 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10094 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010095 DRM_ERROR("D_COMP RCOMP still in progress\n");
10096
10097 if (allow_power_down) {
10098 val = I915_READ(LCPLL_CTL);
10099 val |= LCPLL_POWER_DOWN_ALLOW;
10100 I915_WRITE(LCPLL_CTL, val);
10101 POSTING_READ(LCPLL_CTL);
10102 }
10103}
10104
10105/*
10106 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10107 * source.
10108 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -030010109static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010110{
10111 uint32_t val;
10112
10113 val = I915_READ(LCPLL_CTL);
10114
10115 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10116 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10117 return;
10118
Paulo Zanonia8a8bd52014-03-07 20:08:05 -030010119 /*
10120 * Make sure we're not on PC8 state before disabling PC8, otherwise
10121 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -030010122 */
Mika Kuoppala59bad942015-01-16 11:34:40 +020010123 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Paulo Zanoni215733f2013-08-19 13:18:07 -030010124
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010125 if (val & LCPLL_POWER_DOWN_ALLOW) {
10126 val &= ~LCPLL_POWER_DOWN_ALLOW;
10127 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +020010128 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010129 }
10130
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -030010131 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010132 val |= D_COMP_COMP_FORCE;
10133 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -030010134 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010135
10136 val = I915_READ(LCPLL_CTL);
10137 val &= ~LCPLL_PLL_DISABLE;
10138 I915_WRITE(LCPLL_CTL, val);
10139
Chris Wilson93220c02016-06-30 15:33:08 +010010140 if (intel_wait_for_register(dev_priv,
10141 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10142 5))
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010143 DRM_ERROR("LCPLL not locked yet\n");
10144
10145 if (val & LCPLL_CD_SOURCE_FCLK) {
10146 val = I915_READ(LCPLL_CTL);
10147 val &= ~LCPLL_CD_SOURCE_FCLK;
10148 I915_WRITE(LCPLL_CTL, val);
10149
Imre Deakf53dd632016-06-28 13:37:32 +030010150 if (wait_for_us((I915_READ(LCPLL_CTL) &
10151 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010152 DRM_ERROR("Switching back to LCPLL failed\n");
10153 }
Paulo Zanoni215733f2013-08-19 13:18:07 -030010154
Mika Kuoppala59bad942015-01-16 11:34:40 +020010155 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Chris Wilson91c8a322016-07-05 10:40:23 +010010156 intel_update_cdclk(&dev_priv->drm);
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010157}
10158
Paulo Zanoni765dab672014-03-07 20:08:18 -030010159/*
10160 * Package states C8 and deeper are really deep PC states that can only be
10161 * reached when all the devices on the system allow it, so even if the graphics
10162 * device allows PC8+, it doesn't mean the system will actually get to these
10163 * states. Our driver only allows PC8+ when going into runtime PM.
10164 *
10165 * The requirements for PC8+ are that all the outputs are disabled, the power
10166 * well is disabled and most interrupts are disabled, and these are also
10167 * requirements for runtime PM. When these conditions are met, we manually do
10168 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10169 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10170 * hang the machine.
10171 *
10172 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10173 * the state of some registers, so when we come back from PC8+ we need to
10174 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10175 * need to take care of the registers kept by RC6. Notice that this happens even
10176 * if we don't put the device in PCI D3 state (which is what currently happens
10177 * because of the runtime PM support).
10178 *
10179 * For more, read "Display Sequences for Package C8" on the hardware
10180 * documentation.
10181 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -030010182void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -030010183{
Chris Wilson91c8a322016-07-05 10:40:23 +010010184 struct drm_device *dev = &dev_priv->drm;
Paulo Zanonic67a4702013-08-19 13:18:09 -030010185 uint32_t val;
10186
Paulo Zanonic67a4702013-08-19 13:18:09 -030010187 DRM_DEBUG_KMS("Enabling package C8+\n");
10188
Ville Syrjäläc2699522015-08-27 23:55:59 +030010189 if (HAS_PCH_LPT_LP(dev)) {
Paulo Zanonic67a4702013-08-19 13:18:09 -030010190 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10191 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10192 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10193 }
10194
10195 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -030010196 hsw_disable_lcpll(dev_priv, true, true);
10197}
10198
Paulo Zanonia14cb6f2014-03-07 20:08:17 -030010199void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -030010200{
Chris Wilson91c8a322016-07-05 10:40:23 +010010201 struct drm_device *dev = &dev_priv->drm;
Paulo Zanonic67a4702013-08-19 13:18:09 -030010202 uint32_t val;
10203
Paulo Zanonic67a4702013-08-19 13:18:09 -030010204 DRM_DEBUG_KMS("Disabling package C8+\n");
10205
10206 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -030010207 lpt_init_pch_refclk(dev);
10208
Ville Syrjäläc2699522015-08-27 23:55:59 +030010209 if (HAS_PCH_LPT_LP(dev)) {
Paulo Zanonic67a4702013-08-19 13:18:09 -030010210 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10211 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10212 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10213 }
Paulo Zanonic67a4702013-08-19 13:18:09 -030010214}
10215
Imre Deak324513c2016-06-13 16:44:36 +030010216static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
Vandana Kannanf8437dd12014-11-24 13:37:39 +053010217{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030010218 struct drm_device *dev = old_state->dev;
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010010219 struct intel_atomic_state *old_intel_state =
10220 to_intel_atomic_state(old_state);
10221 unsigned int req_cdclk = old_intel_state->dev_cdclk;
Vandana Kannanf8437dd12014-11-24 13:37:39 +053010222
Imre Deak324513c2016-06-13 16:44:36 +030010223 bxt_set_cdclk(to_i915(dev), req_cdclk);
Vandana Kannanf8437dd12014-11-24 13:37:39 +053010224}
10225
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010226/* compute the max rate for new configuration */
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010227static int ilk_max_pixel_rate(struct drm_atomic_state *state)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010228{
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010229 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Chris Wilsonfac5e232016-07-04 11:34:36 +010010230 struct drm_i915_private *dev_priv = to_i915(state->dev);
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010231 struct drm_crtc *crtc;
10232 struct drm_crtc_state *cstate;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010233 struct intel_crtc_state *crtc_state;
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010234 unsigned max_pixel_rate = 0, i;
10235 enum pipe pipe;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010236
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010237 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10238 sizeof(intel_state->min_pixclk));
10239
10240 for_each_crtc_in_state(state, crtc, cstate, i) {
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010241 int pixel_rate;
10242
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010243 crtc_state = to_intel_crtc_state(cstate);
10244 if (!crtc_state->base.enable) {
10245 intel_state->min_pixclk[i] = 0;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010246 continue;
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010247 }
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010248
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010249 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010250
10251 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010252 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010253 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10254
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010255 intel_state->min_pixclk[i] = pixel_rate;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010256 }
10257
Maarten Lankhorst565602d2015-12-10 12:33:57 +010010258 for_each_pipe(dev_priv, pipe)
10259 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10260
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010261 return max_pixel_rate;
10262}
10263
10264static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10265{
Chris Wilsonfac5e232016-07-04 11:34:36 +010010266 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010267 uint32_t val, data;
10268 int ret;
10269
10270 if (WARN((I915_READ(LCPLL_CTL) &
10271 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10272 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10273 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10274 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10275 "trying to change cdclk frequency with cdclk not enabled\n"))
10276 return;
10277
10278 mutex_lock(&dev_priv->rps.hw_lock);
10279 ret = sandybridge_pcode_write(dev_priv,
10280 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10281 mutex_unlock(&dev_priv->rps.hw_lock);
10282 if (ret) {
10283 DRM_ERROR("failed to inform pcode about cdclk change\n");
10284 return;
10285 }
10286
10287 val = I915_READ(LCPLL_CTL);
10288 val |= LCPLL_CD_SOURCE_FCLK;
10289 I915_WRITE(LCPLL_CTL, val);
10290
Tvrtko Ursulin5ba00172016-03-03 14:36:45 +000010291 if (wait_for_us(I915_READ(LCPLL_CTL) &
10292 LCPLL_CD_SOURCE_FCLK_DONE, 1))
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010293 DRM_ERROR("Switching to FCLK failed\n");
10294
10295 val = I915_READ(LCPLL_CTL);
10296 val &= ~LCPLL_CLK_FREQ_MASK;
10297
10298 switch (cdclk) {
10299 case 450000:
10300 val |= LCPLL_CLK_FREQ_450;
10301 data = 0;
10302 break;
10303 case 540000:
10304 val |= LCPLL_CLK_FREQ_54O_BDW;
10305 data = 1;
10306 break;
10307 case 337500:
10308 val |= LCPLL_CLK_FREQ_337_5_BDW;
10309 data = 2;
10310 break;
10311 case 675000:
10312 val |= LCPLL_CLK_FREQ_675_BDW;
10313 data = 3;
10314 break;
10315 default:
10316 WARN(1, "invalid cdclk frequency\n");
10317 return;
10318 }
10319
10320 I915_WRITE(LCPLL_CTL, val);
10321
10322 val = I915_READ(LCPLL_CTL);
10323 val &= ~LCPLL_CD_SOURCE_FCLK;
10324 I915_WRITE(LCPLL_CTL, val);
10325
Tvrtko Ursulin5ba00172016-03-03 14:36:45 +000010326 if (wait_for_us((I915_READ(LCPLL_CTL) &
10327 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010328 DRM_ERROR("Switching back to LCPLL failed\n");
10329
10330 mutex_lock(&dev_priv->rps.hw_lock);
10331 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10332 mutex_unlock(&dev_priv->rps.hw_lock);
10333
Ville Syrjälä7f1052a2016-04-26 19:46:32 +030010334 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10335
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010336 intel_update_cdclk(dev);
10337
10338 WARN(cdclk != dev_priv->cdclk_freq,
10339 "cdclk requested %d kHz but got %d kHz\n",
10340 cdclk, dev_priv->cdclk_freq);
10341}
10342
Ville Syrjälä587c7912016-05-11 22:44:41 +030010343static int broadwell_calc_cdclk(int max_pixclk)
10344{
10345 if (max_pixclk > 540000)
10346 return 675000;
10347 else if (max_pixclk > 450000)
10348 return 540000;
10349 else if (max_pixclk > 337500)
10350 return 450000;
10351 else
10352 return 337500;
10353}
10354
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010355static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010356{
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010357 struct drm_i915_private *dev_priv = to_i915(state->dev);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010010358 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010359 int max_pixclk = ilk_max_pixel_rate(state);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010360 int cdclk;
10361
10362 /*
10363 * FIXME should also account for plane ratio
10364 * once 64bpp pixel formats are supported.
10365 */
Ville Syrjälä587c7912016-05-11 22:44:41 +030010366 cdclk = broadwell_calc_cdclk(max_pixclk);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010367
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010368 if (cdclk > dev_priv->max_cdclk_freq) {
Maarten Lankhorst63ba5342015-11-24 11:29:03 +010010369 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10370 cdclk, dev_priv->max_cdclk_freq);
10371 return -EINVAL;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010372 }
10373
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010010374 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10375 if (!intel_state->active_crtcs)
Ville Syrjälä587c7912016-05-11 22:44:41 +030010376 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010377
10378 return 0;
10379}
10380
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010381static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010382{
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010383 struct drm_device *dev = old_state->dev;
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010010384 struct intel_atomic_state *old_intel_state =
10385 to_intel_atomic_state(old_state);
10386 unsigned req_cdclk = old_intel_state->dev_cdclk;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010387
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020010388 broadwell_set_cdclk(dev, req_cdclk);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030010389}
10390
Clint Taylorc89e39f2016-05-13 23:41:21 +030010391static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10392{
10393 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10394 struct drm_i915_private *dev_priv = to_i915(state->dev);
10395 const int max_pixclk = ilk_max_pixel_rate(state);
Ville Syrjäläa8ca4932016-05-13 23:41:23 +030010396 int vco = intel_state->cdclk_pll_vco;
Clint Taylorc89e39f2016-05-13 23:41:21 +030010397 int cdclk;
10398
10399 /*
10400 * FIXME should also account for plane ratio
10401 * once 64bpp pixel formats are supported.
10402 */
Ville Syrjäläa8ca4932016-05-13 23:41:23 +030010403 cdclk = skl_calc_cdclk(max_pixclk, vco);
Clint Taylorc89e39f2016-05-13 23:41:21 +030010404
10405 /*
10406 * FIXME move the cdclk caclulation to
10407 * compute_config() so we can fail gracegully.
10408 */
10409 if (cdclk > dev_priv->max_cdclk_freq) {
10410 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10411 cdclk, dev_priv->max_cdclk_freq);
10412 cdclk = dev_priv->max_cdclk_freq;
10413 }
10414
10415 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10416 if (!intel_state->active_crtcs)
Ville Syrjäläa8ca4932016-05-13 23:41:23 +030010417 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
Clint Taylorc89e39f2016-05-13 23:41:21 +030010418
10419 return 0;
10420}
10421
10422static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10423{
Ville Syrjälä1cd593e2016-05-13 23:41:26 +030010424 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10425 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10426 unsigned int req_cdclk = intel_state->dev_cdclk;
10427 unsigned int req_vco = intel_state->cdclk_pll_vco;
Clint Taylorc89e39f2016-05-13 23:41:21 +030010428
Ville Syrjälä1cd593e2016-05-13 23:41:26 +030010429 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
Clint Taylorc89e39f2016-05-13 23:41:21 +030010430}
10431
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +020010432static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10433 struct intel_crtc_state *crtc_state)
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030010434{
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +030010435 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
Mika Kaholaaf3997b2016-02-05 13:29:28 +020010436 if (!intel_ddi_pll_select(crtc, crtc_state))
10437 return -EINVAL;
10438 }
Daniel Vetter716c2e52014-06-25 22:02:02 +030010439
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +030010440 crtc->lowfreq_avail = false;
Daniel Vetter644cef32014-04-24 23:55:07 +020010441
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +020010442 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080010443}
10444
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010445static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10446 enum port port,
10447 struct intel_crtc_state *pipe_config)
10448{
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010449 enum intel_dpll_id id;
10450
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010451 switch (port) {
10452 case PORT_A:
Imre Deak08250c42016-03-14 19:55:34 +020010453 id = DPLL_ID_SKL_DPLL0;
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010454 break;
10455 case PORT_B:
Imre Deak08250c42016-03-14 19:55:34 +020010456 id = DPLL_ID_SKL_DPLL1;
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010457 break;
10458 case PORT_C:
Imre Deak08250c42016-03-14 19:55:34 +020010459 id = DPLL_ID_SKL_DPLL2;
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010460 break;
10461 default:
10462 DRM_ERROR("Incorrect port type\n");
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010463 return;
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010464 }
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010465
10466 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010467}
10468
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010469static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10470 enum port port,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010471 struct intel_crtc_state *pipe_config)
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010472{
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010473 enum intel_dpll_id id;
Ander Conselvan de Oliveiraa3c988e2016-03-08 17:46:27 +020010474 u32 temp;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010475
10476 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070010477 id = temp >> (port * 3 + 1);
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010478
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070010479 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010480 return;
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010481
10482 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010483}
10484
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010485static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10486 enum port port,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010487 struct intel_crtc_state *pipe_config)
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010488{
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010489 enum intel_dpll_id id;
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070010490 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010491
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070010492 switch (ddi_pll_sel) {
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010493 case PORT_CLK_SEL_WRPLL1:
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010494 id = DPLL_ID_WRPLL1;
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010495 break;
10496 case PORT_CLK_SEL_WRPLL2:
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010497 id = DPLL_ID_WRPLL2;
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010498 break;
Maarten Lankhorst00490c22015-11-16 14:42:12 +010010499 case PORT_CLK_SEL_SPLL:
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010500 id = DPLL_ID_SPLL;
Ville Syrjälä79bd23d2015-12-01 23:32:07 +020010501 break;
Ander Conselvan de Oliveira9d16da62016-03-08 17:46:26 +020010502 case PORT_CLK_SEL_LCPLL_810:
10503 id = DPLL_ID_LCPLL_810;
10504 break;
10505 case PORT_CLK_SEL_LCPLL_1350:
10506 id = DPLL_ID_LCPLL_1350;
10507 break;
10508 case PORT_CLK_SEL_LCPLL_2700:
10509 id = DPLL_ID_LCPLL_2700;
10510 break;
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010511 default:
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070010512 MISSING_CASE(ddi_pll_sel);
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010513 /* fall through */
10514 case PORT_CLK_SEL_NONE:
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010515 return;
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010516 }
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010517
10518 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
Damien Lespiau7d2c8172014-07-29 18:06:18 +010010519}
10520
Jani Nikulacf304292016-03-18 17:05:41 +020010521static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10522 struct intel_crtc_state *pipe_config,
10523 unsigned long *power_domain_mask)
10524{
10525 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010526 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikulacf304292016-03-18 17:05:41 +020010527 enum intel_display_power_domain power_domain;
10528 u32 tmp;
10529
Imre Deakd9a7bc62016-05-12 16:18:50 +030010530 /*
10531 * The pipe->transcoder mapping is fixed with the exception of the eDP
10532 * transcoder handled below.
10533 */
Jani Nikulacf304292016-03-18 17:05:41 +020010534 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10535
10536 /*
10537 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10538 * consistency and less surprising code; it's in always on power).
10539 */
10540 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10541 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10542 enum pipe trans_edp_pipe;
10543 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10544 default:
10545 WARN(1, "unknown pipe linked to edp transcoder\n");
10546 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10547 case TRANS_DDI_EDP_INPUT_A_ON:
10548 trans_edp_pipe = PIPE_A;
10549 break;
10550 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10551 trans_edp_pipe = PIPE_B;
10552 break;
10553 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10554 trans_edp_pipe = PIPE_C;
10555 break;
10556 }
10557
10558 if (trans_edp_pipe == crtc->pipe)
10559 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10560 }
10561
10562 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10563 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10564 return false;
10565 *power_domain_mask |= BIT(power_domain);
10566
10567 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10568
10569 return tmp & PIPECONF_ENABLE;
10570}
10571
Jani Nikula4d1de972016-03-18 17:05:42 +020010572static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10573 struct intel_crtc_state *pipe_config,
10574 unsigned long *power_domain_mask)
10575{
10576 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010577 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula4d1de972016-03-18 17:05:42 +020010578 enum intel_display_power_domain power_domain;
10579 enum port port;
10580 enum transcoder cpu_transcoder;
10581 u32 tmp;
10582
Jani Nikula4d1de972016-03-18 17:05:42 +020010583 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10584 if (port == PORT_A)
10585 cpu_transcoder = TRANSCODER_DSI_A;
10586 else
10587 cpu_transcoder = TRANSCODER_DSI_C;
10588
10589 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10590 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10591 continue;
10592 *power_domain_mask |= BIT(power_domain);
10593
Imre Deakdb18b6a2016-03-24 12:41:40 +020010594 /*
10595 * The PLL needs to be enabled with a valid divider
10596 * configuration, otherwise accessing DSI registers will hang
10597 * the machine. See BSpec North Display Engine
10598 * registers/MIPI[BXT]. We can break out here early, since we
10599 * need the same DSI PLL to be enabled for both DSI ports.
10600 */
10601 if (!intel_dsi_pll_is_enabled(dev_priv))
10602 break;
10603
Jani Nikula4d1de972016-03-18 17:05:42 +020010604 /* XXX: this works for video mode only */
10605 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10606 if (!(tmp & DPI_ENABLE))
10607 continue;
10608
10609 tmp = I915_READ(MIPI_CTRL(port));
10610 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10611 continue;
10612
10613 pipe_config->cpu_transcoder = cpu_transcoder;
Jani Nikula4d1de972016-03-18 17:05:42 +020010614 break;
10615 }
10616
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +030010617 return transcoder_is_dsi(pipe_config->cpu_transcoder);
Jani Nikula4d1de972016-03-18 17:05:42 +020010618}
10619
Daniel Vetter26804af2014-06-25 22:01:55 +030010620static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010621 struct intel_crtc_state *pipe_config)
Daniel Vetter26804af2014-06-25 22:01:55 +030010622{
10623 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010624 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010625 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +030010626 enum port port;
10627 uint32_t tmp;
10628
10629 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10630
10631 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10632
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070010633 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010634 skylake_get_ddi_pll(dev_priv, port, pipe_config);
Satheeshakrishna M3760b592014-08-22 09:49:11 +053010635 else if (IS_BROXTON(dev))
10636 bxt_get_ddi_pll(dev_priv, port, pipe_config);
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +000010637 else
10638 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +030010639
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010640 pll = pipe_config->shared_dpll;
10641 if (pll) {
Ander Conselvan de Oliveira2edd6442016-03-08 17:46:21 +020010642 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10643 &pipe_config->dpll_hw_state));
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010644 }
10645
Daniel Vetter26804af2014-06-25 22:01:55 +030010646 /*
10647 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10648 * DDI E. So just check whether this pipe is wired to DDI E and whether
10649 * the PCH transcoder is on.
10650 */
Damien Lespiauca370452013-12-03 13:56:24 +000010651 if (INTEL_INFO(dev)->gen < 9 &&
10652 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter26804af2014-06-25 22:01:55 +030010653 pipe_config->has_pch_encoder = true;
10654
10655 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10656 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10657 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10658
10659 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10660 }
10661}
10662
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010663static bool haswell_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010664 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010665{
10666 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010667 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak17290502016-02-12 18:55:11 +020010668 enum intel_display_power_domain power_domain;
10669 unsigned long power_domain_mask;
Jani Nikulacf304292016-03-18 17:05:41 +020010670 bool active;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010671
Imre Deak17290502016-02-12 18:55:11 +020010672 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10673 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Imre Deakb5482bd2014-03-05 16:20:55 +020010674 return false;
Imre Deak17290502016-02-12 18:55:11 +020010675 power_domain_mask = BIT(power_domain);
10676
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020010677 pipe_config->shared_dpll = NULL;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010678
Jani Nikulacf304292016-03-18 17:05:41 +020010679 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
Daniel Vettereccb1402013-05-22 00:50:22 +020010680
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +030010681 if (IS_BROXTON(dev_priv) &&
10682 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10683 WARN_ON(active);
10684 active = true;
Jani Nikula4d1de972016-03-18 17:05:42 +020010685 }
10686
Jani Nikulacf304292016-03-18 17:05:41 +020010687 if (!active)
Imre Deak17290502016-02-12 18:55:11 +020010688 goto out;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010689
Ville Syrjäläd7edc4e2016-06-22 21:57:07 +030010690 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
Jani Nikula4d1de972016-03-18 17:05:42 +020010691 haswell_get_ddi_port_state(crtc, pipe_config);
10692 intel_get_pipe_timings(crtc, pipe_config);
10693 }
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010694
Jani Nikulabc58be62016-03-18 17:05:39 +020010695 intel_get_pipe_src_size(crtc, pipe_config);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010696
Lionel Landwerlin05dc6982016-03-16 10:57:15 +000010697 pipe_config->gamma_mode =
10698 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10699
Chandra Kondurua1b22782015-04-07 15:28:45 -070010700 if (INTEL_INFO(dev)->gen >= 9) {
10701 skl_init_scalers(dev, crtc, pipe_config);
10702 }
10703
Chandra Konduruaf99ced2015-05-11 14:35:47 -070010704 if (INTEL_INFO(dev)->gen >= 9) {
10705 pipe_config->scaler_state.scaler_id = -1;
10706 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10707 }
10708
Imre Deak17290502016-02-12 18:55:11 +020010709 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10710 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10711 power_domain_mask |= BIT(power_domain);
Rodrigo Vivi1c132b42015-09-02 15:19:26 -070010712 if (INTEL_INFO(dev)->gen >= 9)
Jesse Barnesbd2e2442014-11-13 17:51:47 +000010713 skylake_get_pfit_config(crtc, pipe_config);
Jesse Barnesff6d9f52015-01-21 17:19:54 -080010714 else
Rodrigo Vivi1c132b42015-09-02 15:19:26 -070010715 ironlake_get_pfit_config(crtc, pipe_config);
Jesse Barnesbd2e2442014-11-13 17:51:47 +000010716 }
Daniel Vetter88adfff2013-03-28 10:42:01 +010010717
Jesse Barnese59150d2014-01-07 13:30:45 -080010718 if (IS_HASWELL(dev))
10719 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10720 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010721
Jani Nikula4d1de972016-03-18 17:05:42 +020010722 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10723 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
Clint Taylorebb69c92014-09-30 10:30:22 -070010724 pipe_config->pixel_multiplier =
10725 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10726 } else {
10727 pipe_config->pixel_multiplier = 1;
10728 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010729
Imre Deak17290502016-02-12 18:55:11 +020010730out:
10731 for_each_power_domain(power_domain, power_domain_mask)
10732 intel_display_power_put(dev_priv, power_domain);
10733
Jani Nikulacf304292016-03-18 17:05:41 +020010734 return active;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010735}
10736
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010737static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10738 const struct intel_plane_state *plane_state)
Chris Wilson560b85b2010-08-07 11:01:38 +010010739{
10740 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010741 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson560b85b2010-08-07 11:01:38 +010010742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +030010743 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +010010744
Ville Syrjälä936e71e2016-07-26 19:06:59 +030010745 if (plane_state && plane_state->base.visible) {
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010746 unsigned int width = plane_state->base.crtc_w;
10747 unsigned int height = plane_state->base.crtc_h;
Ville Syrjälädc41c152014-08-13 11:57:05 +030010748 unsigned int stride = roundup_pow_of_two(width) * 4;
10749
10750 switch (stride) {
10751 default:
10752 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10753 width, stride);
10754 stride = 256;
10755 /* fallthrough */
10756 case 256:
10757 case 512:
10758 case 1024:
10759 case 2048:
10760 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +030010761 }
10762
Ville Syrjälädc41c152014-08-13 11:57:05 +030010763 cntl |= CURSOR_ENABLE |
10764 CURSOR_GAMMA_ENABLE |
10765 CURSOR_FORMAT_ARGB |
10766 CURSOR_STRIDE(stride);
10767
10768 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +030010769 }
Chris Wilson560b85b2010-08-07 11:01:38 +010010770
Ville Syrjälädc41c152014-08-13 11:57:05 +030010771 if (intel_crtc->cursor_cntl != 0 &&
10772 (intel_crtc->cursor_base != base ||
10773 intel_crtc->cursor_size != size ||
10774 intel_crtc->cursor_cntl != cntl)) {
10775 /* On these chipsets we can only modify the base/size/stride
10776 * whilst the cursor is disabled.
10777 */
Ville Syrjälä0b87c242015-09-22 19:47:51 +030010778 I915_WRITE(CURCNTR(PIPE_A), 0);
10779 POSTING_READ(CURCNTR(PIPE_A));
Ville Syrjälädc41c152014-08-13 11:57:05 +030010780 intel_crtc->cursor_cntl = 0;
10781 }
10782
Ville Syrjälä99d1f382014-09-12 20:53:32 +030010783 if (intel_crtc->cursor_base != base) {
Ville Syrjälä0b87c242015-09-22 19:47:51 +030010784 I915_WRITE(CURBASE(PIPE_A), base);
Ville Syrjälä99d1f382014-09-12 20:53:32 +030010785 intel_crtc->cursor_base = base;
10786 }
Ville Syrjälädc41c152014-08-13 11:57:05 +030010787
10788 if (intel_crtc->cursor_size != size) {
10789 I915_WRITE(CURSIZE, size);
10790 intel_crtc->cursor_size = size;
10791 }
10792
Chris Wilson4b0e3332014-05-30 16:35:26 +030010793 if (intel_crtc->cursor_cntl != cntl) {
Ville Syrjälä0b87c242015-09-22 19:47:51 +030010794 I915_WRITE(CURCNTR(PIPE_A), cntl);
10795 POSTING_READ(CURCNTR(PIPE_A));
Chris Wilson4b0e3332014-05-30 16:35:26 +030010796 intel_crtc->cursor_cntl = cntl;
10797 }
Chris Wilson560b85b2010-08-07 11:01:38 +010010798}
10799
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010800static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10801 const struct intel_plane_state *plane_state)
Chris Wilson560b85b2010-08-07 11:01:38 +010010802{
10803 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010804 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson560b85b2010-08-07 11:01:38 +010010805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Lyude62e0fb82016-08-22 12:50:08 -040010806 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
Chris Wilson560b85b2010-08-07 11:01:38 +010010807 int pipe = intel_crtc->pipe;
Ville Syrjälä663f3122015-12-14 13:16:48 +020010808 uint32_t cntl = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +010010809
Lyude62e0fb82016-08-22 12:50:08 -040010810 if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10811 skl_write_cursor_wm(intel_crtc, wm);
10812
Ville Syrjälä936e71e2016-07-26 19:06:59 +030010813 if (plane_state && plane_state->base.visible) {
Chris Wilson4b0e3332014-05-30 16:35:26 +030010814 cntl = MCURSOR_GAMMA_ENABLE;
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010815 switch (plane_state->base.crtc_w) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +053010816 case 64:
10817 cntl |= CURSOR_MODE_64_ARGB_AX;
10818 break;
10819 case 128:
10820 cntl |= CURSOR_MODE_128_ARGB_AX;
10821 break;
10822 case 256:
10823 cntl |= CURSOR_MODE_256_ARGB_AX;
10824 break;
10825 default:
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010826 MISSING_CASE(plane_state->base.crtc_w);
Sagar Kamble4726e0b2014-03-10 17:06:23 +053010827 return;
Chris Wilson560b85b2010-08-07 11:01:38 +010010828 }
Chris Wilson4b0e3332014-05-30 16:35:26 +030010829 cntl |= pipe << 28; /* Connect to correct pipe */
Ville Syrjälä47bf17a2014-09-12 20:53:33 +030010830
Bob Paauwefc6f93b2015-08-31 14:03:30 -070010831 if (HAS_DDI(dev))
Ville Syrjälä47bf17a2014-09-12 20:53:33 +030010832 cntl |= CURSOR_PIPE_CSC_ENABLE;
Chris Wilson4b0e3332014-05-30 16:35:26 +030010833
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +030010834 if (plane_state->base.rotation == DRM_ROTATE_180)
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010835 cntl |= CURSOR_ROTATE_180;
10836 }
Ville Syrjälä4398ad42014-10-23 07:41:34 -070010837
Chris Wilson4b0e3332014-05-30 16:35:26 +030010838 if (intel_crtc->cursor_cntl != cntl) {
10839 I915_WRITE(CURCNTR(pipe), cntl);
10840 POSTING_READ(CURCNTR(pipe));
10841 intel_crtc->cursor_cntl = cntl;
10842 }
10843
Jesse Barnes65a21cd2011-10-12 11:10:21 -070010844 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030010845 I915_WRITE(CURBASE(pipe), base);
10846 POSTING_READ(CURBASE(pipe));
Ville Syrjälä99d1f382014-09-12 20:53:32 +030010847
10848 intel_crtc->cursor_base = base;
Jesse Barnes65a21cd2011-10-12 11:10:21 -070010849}
10850
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010851/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +010010852static void intel_crtc_update_cursor(struct drm_crtc *crtc,
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010853 const struct intel_plane_state *plane_state)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010854{
10855 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010010856 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858 int pipe = intel_crtc->pipe;
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010859 u32 base = intel_crtc->cursor_addr;
10860 u32 pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010861
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010862 if (plane_state) {
10863 int x = plane_state->base.crtc_x;
10864 int y = plane_state->base.crtc_y;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010865
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010866 if (x < 0) {
10867 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10868 x = -x;
10869 }
10870 pos |= x << CURSOR_X_SHIFT;
10871
10872 if (y < 0) {
10873 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10874 y = -y;
10875 }
10876 pos |= y << CURSOR_Y_SHIFT;
10877
10878 /* ILK+ do this automagically */
10879 if (HAS_GMCH_DISPLAY(dev) &&
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +030010880 plane_state->base.rotation == DRM_ROTATE_180) {
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010881 base += (plane_state->base.crtc_h *
10882 plane_state->base.crtc_w - 1) * 4;
10883 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010884 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010885
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030010886 I915_WRITE(CURPOS(pipe), pos);
10887
Ville Syrjälä8ac54662014-08-12 19:39:54 +030010888 if (IS_845G(dev) || IS_I865G(dev))
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010889 i845_update_cursor(crtc, base, plane_state);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030010890 else
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010010891 i9xx_update_cursor(crtc, base, plane_state);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010892}
10893
Ville Syrjälädc41c152014-08-13 11:57:05 +030010894static bool cursor_size_ok(struct drm_device *dev,
10895 uint32_t width, uint32_t height)
10896{
10897 if (width == 0 || height == 0)
10898 return false;
10899
10900 /*
10901 * 845g/865g are special in that they are only limited by
10902 * the width of their cursors, the height is arbitrary up to
10903 * the precision of the register. Everything else requires
10904 * square cursors, limited to a few power-of-two sizes.
10905 */
10906 if (IS_845G(dev) || IS_I865G(dev)) {
10907 if ((width & 63) != 0)
10908 return false;
10909
10910 if (width > (IS_845G(dev) ? 64 : 512))
10911 return false;
10912
10913 if (height > 1023)
10914 return false;
10915 } else {
10916 switch (width | height) {
10917 case 256:
10918 case 128:
10919 if (IS_GEN2(dev))
10920 return false;
10921 case 64:
10922 break;
10923 default:
10924 return false;
10925 }
10926 }
10927
10928 return true;
10929}
10930
Jesse Barnes79e53942008-11-07 14:24:08 -080010931/* VESA 640x480x72Hz mode to set on the pipe */
10932static struct drm_display_mode load_detect_mode = {
10933 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10934 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10935};
10936
Daniel Vettera8bb6812014-02-10 18:00:39 +010010937struct drm_framebuffer *
10938__intel_framebuffer_create(struct drm_device *dev,
10939 struct drm_mode_fb_cmd2 *mode_cmd,
10940 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +010010941{
10942 struct intel_framebuffer *intel_fb;
10943 int ret;
10944
10945 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010946 if (!intel_fb)
Chris Wilsond2dff872011-04-19 08:36:26 +010010947 return ERR_PTR(-ENOMEM);
Chris Wilsond2dff872011-04-19 08:36:26 +010010948
10949 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010950 if (ret)
10951 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +010010952
10953 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010954
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010955err:
10956 kfree(intel_fb);
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010957 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +010010958}
10959
Daniel Vetterb5ea6422014-03-02 21:18:00 +010010960static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +010010961intel_framebuffer_create(struct drm_device *dev,
10962 struct drm_mode_fb_cmd2 *mode_cmd,
10963 struct drm_i915_gem_object *obj)
10964{
10965 struct drm_framebuffer *fb;
10966 int ret;
10967
10968 ret = i915_mutex_lock_interruptible(dev);
10969 if (ret)
10970 return ERR_PTR(ret);
10971 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10972 mutex_unlock(&dev->struct_mutex);
10973
10974 return fb;
10975}
10976
Chris Wilsond2dff872011-04-19 08:36:26 +010010977static u32
10978intel_framebuffer_pitch_for_width(int width, int bpp)
10979{
10980 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10981 return ALIGN(pitch, 64);
10982}
10983
10984static u32
10985intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10986{
10987 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +020010988 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +010010989}
10990
10991static struct drm_framebuffer *
10992intel_framebuffer_create_for_mode(struct drm_device *dev,
10993 struct drm_display_mode *mode,
10994 int depth, int bpp)
10995{
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010996 struct drm_framebuffer *fb;
Chris Wilsond2dff872011-04-19 08:36:26 +010010997 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +000010998 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +010010999
Dave Gordond37cd8a2016-04-22 19:14:32 +010011000 obj = i915_gem_object_create(dev,
Chris Wilsond2dff872011-04-19 08:36:26 +010011001 intel_framebuffer_size_for_mode(mode, bpp));
Chris Wilsonfe3db792016-04-25 13:32:13 +010011002 if (IS_ERR(obj))
11003 return ERR_CAST(obj);
Chris Wilsond2dff872011-04-19 08:36:26 +010011004
11005 mode_cmd.width = mode->hdisplay;
11006 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011007 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11008 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +000011009 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +010011010
Lukas Wunnerdcb13942015-07-04 11:50:58 +020011011 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11012 if (IS_ERR(fb))
Chris Wilson34911fd2016-07-20 13:31:54 +010011013 i915_gem_object_put_unlocked(obj);
Lukas Wunnerdcb13942015-07-04 11:50:58 +020011014
11015 return fb;
Chris Wilsond2dff872011-04-19 08:36:26 +010011016}
11017
11018static struct drm_framebuffer *
11019mode_fits_in_fbdev(struct drm_device *dev,
11020 struct drm_display_mode *mode)
11021{
Daniel Vetter06957262015-08-10 13:34:08 +020011022#ifdef CONFIG_DRM_FBDEV_EMULATION
Chris Wilsonfac5e232016-07-04 11:34:36 +010011023 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsond2dff872011-04-19 08:36:26 +010011024 struct drm_i915_gem_object *obj;
11025 struct drm_framebuffer *fb;
11026
Daniel Vetter4c0e5522014-02-14 16:35:54 +010011027 if (!dev_priv->fbdev)
11028 return NULL;
11029
11030 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +010011031 return NULL;
11032
Jesse Barnes8bcd4552014-02-07 12:10:38 -080011033 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +010011034 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +010011035
Jesse Barnes8bcd4552014-02-07 12:10:38 -080011036 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +020011037 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11038 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +010011039 return NULL;
11040
Ville Syrjälä01f2c772011-12-20 00:06:49 +020011041 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +010011042 return NULL;
11043
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011044 drm_framebuffer_reference(fb);
Chris Wilsond2dff872011-04-19 08:36:26 +010011045 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +020011046#else
11047 return NULL;
11048#endif
Chris Wilsond2dff872011-04-19 08:36:26 +010011049}
11050
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030011051static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11052 struct drm_crtc *crtc,
11053 struct drm_display_mode *mode,
11054 struct drm_framebuffer *fb,
11055 int x, int y)
11056{
11057 struct drm_plane_state *plane_state;
11058 int hdisplay, vdisplay;
11059 int ret;
11060
11061 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11062 if (IS_ERR(plane_state))
11063 return PTR_ERR(plane_state);
11064
11065 if (mode)
11066 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11067 else
11068 hdisplay = vdisplay = 0;
11069
11070 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11071 if (ret)
11072 return ret;
11073 drm_atomic_set_fb_for_plane(plane_state, fb);
11074 plane_state->crtc_x = 0;
11075 plane_state->crtc_y = 0;
11076 plane_state->crtc_w = hdisplay;
11077 plane_state->crtc_h = vdisplay;
11078 plane_state->src_x = x << 16;
11079 plane_state->src_y = y << 16;
11080 plane_state->src_w = hdisplay << 16;
11081 plane_state->src_h = vdisplay << 16;
11082
11083 return 0;
11084}
11085
Daniel Vetterd2434ab2012-08-12 21:20:10 +020011086bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +010011087 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -050011088 struct intel_load_detect_pipe *old,
11089 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -080011090{
11091 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +020011092 struct intel_encoder *intel_encoder =
11093 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -080011094 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +010011095 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -080011096 struct drm_crtc *crtc = NULL;
11097 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +020011098 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -050011099 struct drm_mode_config *config = &dev->mode_config;
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011100 struct drm_atomic_state *state = NULL, *restore_state = NULL;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020011101 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030011102 struct intel_crtc_state *crtc_state;
Rob Clark51fd3712013-11-19 12:10:12 -050011103 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -080011104
Chris Wilsond2dff872011-04-19 08:36:26 +010011105 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +030011106 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +030011107 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +010011108
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011109 old->restore_state = NULL;
11110
Rob Clark51fd3712013-11-19 12:10:12 -050011111retry:
11112 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11113 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020011114 goto fail;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011115
Jesse Barnes79e53942008-11-07 14:24:08 -080011116 /*
11117 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +010011118 *
Jesse Barnes79e53942008-11-07 14:24:08 -080011119 * - if the connector already has an assigned crtc, use it (but make
11120 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +010011121 *
Jesse Barnes79e53942008-11-07 14:24:08 -080011122 * - try to find the first unused crtc that can drive this connector,
11123 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -080011124 */
11125
11126 /* See if we already have a CRTC for this connector */
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011127 if (connector->state->crtc) {
11128 crtc = connector->state->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +010011129
Rob Clark51fd3712013-11-19 12:10:12 -050011130 ret = drm_modeset_lock(&crtc->mutex, ctx);
11131 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020011132 goto fail;
Chris Wilson8261b192011-04-19 23:18:09 +010011133
11134 /* Make sure the crtc and connector are running */
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011135 goto found;
Jesse Barnes79e53942008-11-07 14:24:08 -080011136 }
11137
11138 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010011139 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -080011140 i++;
11141 if (!(encoder->possible_crtcs & (1 << i)))
11142 continue;
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011143
11144 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11145 if (ret)
11146 goto fail;
11147
11148 if (possible_crtc->state->enable) {
11149 drm_modeset_unlock(&possible_crtc->mutex);
Ville Syrjäläa4592492014-08-11 13:15:36 +030011150 continue;
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011151 }
Ville Syrjäläa4592492014-08-11 13:15:36 +030011152
11153 crtc = possible_crtc;
11154 break;
Jesse Barnes79e53942008-11-07 14:24:08 -080011155 }
11156
11157 /*
11158 * If we didn't find an unused CRTC, don't use any.
11159 */
11160 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +010011161 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020011162 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011163 }
11164
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011165found:
11166 intel_crtc = to_intel_crtc(crtc);
11167
Daniel Vetter4d02e2d2014-11-11 10:12:00 +010011168 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11169 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020011170 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011171
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011172 state = drm_atomic_state_alloc(dev);
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011173 restore_state = drm_atomic_state_alloc(dev);
11174 if (!state || !restore_state) {
11175 ret = -ENOMEM;
11176 goto fail;
11177 }
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011178
11179 state->acquire_ctx = ctx;
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011180 restore_state->acquire_ctx = ctx;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011181
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020011182 connector_state = drm_atomic_get_connector_state(state, connector);
11183 if (IS_ERR(connector_state)) {
11184 ret = PTR_ERR(connector_state);
11185 goto fail;
11186 }
11187
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011188 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11189 if (ret)
11190 goto fail;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020011191
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030011192 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11193 if (IS_ERR(crtc_state)) {
11194 ret = PTR_ERR(crtc_state);
11195 goto fail;
11196 }
11197
Maarten Lankhorst49d6fa22015-05-11 10:45:15 +020011198 crtc_state->base.active = crtc_state->base.enable = true;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030011199
Chris Wilson64927112011-04-20 07:25:26 +010011200 if (!mode)
11201 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -080011202
Chris Wilsond2dff872011-04-19 08:36:26 +010011203 /* We need a framebuffer large enough to accommodate all accesses
11204 * that the plane may generate whilst we perform load detection.
11205 * We can not rely on the fbcon either being present (we get called
11206 * during its initialisation to detect all boot displays, or it may
11207 * not even exist) or that it is large enough to satisfy the
11208 * requested mode.
11209 */
Daniel Vetter94352cf2012-07-05 22:51:56 +020011210 fb = mode_fits_in_fbdev(dev, mode);
11211 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +010011212 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +020011213 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
Chris Wilsond2dff872011-04-19 08:36:26 +010011214 } else
11215 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +020011216 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +010011217 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +020011218 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011219 }
Chris Wilsond2dff872011-04-19 08:36:26 +010011220
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030011221 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11222 if (ret)
11223 goto fail;
11224
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011225 drm_framebuffer_unreference(fb);
11226
11227 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11228 if (ret)
11229 goto fail;
11230
11231 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11232 if (!ret)
11233 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11234 if (!ret)
11235 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11236 if (ret) {
11237 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11238 goto fail;
11239 }
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030011240
Maarten Lankhorst3ba86072016-02-29 09:18:57 +010011241 ret = drm_atomic_commit(state);
11242 if (ret) {
Chris Wilson64927112011-04-20 07:25:26 +010011243 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +020011244 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011245 }
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011246
11247 old->restore_state = restore_state;
Chris Wilson71731882011-04-19 23:10:58 +010011248
Jesse Barnes79e53942008-11-07 14:24:08 -080011249 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -070011250 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +010011251 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +020011252
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020011253fail:
Chris Wilson08536952016-10-14 13:18:18 +010011254 drm_atomic_state_put(state);
11255 drm_atomic_state_put(restore_state);
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011256 restore_state = state = NULL;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011257
Rob Clark51fd3712013-11-19 12:10:12 -050011258 if (ret == -EDEADLK) {
11259 drm_modeset_backoff(ctx);
11260 goto retry;
11261 }
11262
Ville Syrjälä412b61d2014-01-17 15:59:39 +020011263 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -080011264}
11265
Daniel Vetterd2434ab2012-08-12 21:20:10 +020011266void intel_release_load_detect_pipe(struct drm_connector *connector,
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +020011267 struct intel_load_detect_pipe *old,
11268 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -080011269{
Daniel Vetterd2434ab2012-08-12 21:20:10 +020011270 struct intel_encoder *intel_encoder =
11271 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +010011272 struct drm_encoder *encoder = &intel_encoder->base;
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011273 struct drm_atomic_state *state = old->restore_state;
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030011274 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080011275
Chris Wilsond2dff872011-04-19 08:36:26 +010011276 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +030011277 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +030011278 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +010011279
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011280 if (!state)
Chris Wilson0622a532011-04-21 09:32:11 +010011281 return;
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011282
11283 ret = drm_atomic_commit(state);
Chris Wilson08536952016-10-14 13:18:18 +010011284 if (ret)
Maarten Lankhorstedde3612016-02-17 09:18:35 +010011285 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
Chris Wilson08536952016-10-14 13:18:18 +010011286 drm_atomic_state_put(state);
Jesse Barnes79e53942008-11-07 14:24:08 -080011287}
11288
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030011289static int i9xx_pll_refclk(struct drm_device *dev,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011290 const struct intel_crtc_state *pipe_config)
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030011291{
Chris Wilsonfac5e232016-07-04 11:34:36 +010011292 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030011293 u32 dpll = pipe_config->dpll_hw_state.dpll;
11294
11295 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +020011296 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030011297 else if (HAS_PCH_SPLIT(dev))
11298 return 120000;
11299 else if (!IS_GEN2(dev))
11300 return 96000;
11301 else
11302 return 48000;
11303}
11304
Jesse Barnes79e53942008-11-07 14:24:08 -080011305/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011306static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011307 struct intel_crtc_state *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -080011308{
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011309 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010011310 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011311 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +030011312 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -080011313 u32 fp;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +030011314 struct dpll clock;
Imre Deakdccbea32015-06-22 23:35:51 +030011315 int port_clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030011316 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -080011317
11318 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +030011319 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -080011320 else
Ville Syrjälä293623f2013-09-13 16:18:46 +030011321 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -080011322
11323 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -050011324 if (IS_PINEVIEW(dev)) {
11325 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11326 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +080011327 } else {
11328 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11329 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11330 }
11331
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011332 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -050011333 if (IS_PINEVIEW(dev))
11334 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11335 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +080011336 else
11337 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -080011338 DPLL_FPA01_P1_POST_DIV_SHIFT);
11339
11340 switch (dpll & DPLL_MODE_MASK) {
11341 case DPLLB_MODE_DAC_SERIAL:
11342 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11343 5 : 10;
11344 break;
11345 case DPLLB_MODE_LVDS:
11346 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11347 7 : 14;
11348 break;
11349 default:
Zhao Yakui28c97732009-10-09 11:39:41 +080011350 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -080011351 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011352 return;
Jesse Barnes79e53942008-11-07 14:24:08 -080011353 }
11354
Daniel Vetterac58c3f2013-06-01 17:16:17 +020011355 if (IS_PINEVIEW(dev))
Imre Deakdccbea32015-06-22 23:35:51 +030011356 port_clock = pnv_calc_dpll_params(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +020011357 else
Imre Deakdccbea32015-06-22 23:35:51 +030011358 port_clock = i9xx_calc_dpll_params(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080011359 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +020011360 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +020011361 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -080011362
11363 if (is_lvds) {
11364 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11365 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +020011366
11367 if (lvds & LVDS_CLKB_POWER_UP)
11368 clock.p2 = 7;
11369 else
11370 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -080011371 } else {
11372 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11373 clock.p1 = 2;
11374 else {
11375 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11376 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11377 }
11378 if (dpll & PLL_P2_DIVIDE_BY_4)
11379 clock.p2 = 4;
11380 else
11381 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -080011382 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030011383
Imre Deakdccbea32015-06-22 23:35:51 +030011384 port_clock = i9xx_calc_dpll_params(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080011385 }
11386
Ville Syrjälä18442d02013-09-13 16:00:08 +030011387 /*
11388 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +010011389 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +030011390 * encoder's get_config() function.
11391 */
Imre Deakdccbea32015-06-22 23:35:51 +030011392 pipe_config->port_clock = port_clock;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011393}
11394
Ville Syrjälä6878da02013-09-13 15:59:11 +030011395int intel_dotclock_calculate(int link_freq,
11396 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011397{
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011398 /*
11399 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +030011400 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011401 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +030011402 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011403 *
11404 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +030011405 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -080011406 */
11407
Ville Syrjälä6878da02013-09-13 15:59:11 +030011408 if (!m_n->link_n)
11409 return 0;
11410
11411 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11412}
11413
Ville Syrjälä18442d02013-09-13 16:00:08 +030011414static void ironlake_pch_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011415 struct intel_crtc_state *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +030011416{
Ville Syrjäläe3b247d2016-02-17 21:41:09 +020011417 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä18442d02013-09-13 16:00:08 +030011418
11419 /* read out port_clock from the DPLL */
11420 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +030011421
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011422 /*
Ville Syrjäläe3b247d2016-02-17 21:41:09 +020011423 * In case there is an active pipe without active ports,
11424 * we may need some idea for the dotclock anyway.
11425 * Calculate one based on the FDI configuration.
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011426 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011427 pipe_config->base.adjusted_mode.crtc_clock =
Ville Syrjälä21a727b2016-02-17 21:41:10 +020011428 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
Ville Syrjälä18442d02013-09-13 16:00:08 +030011429 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -080011430}
11431
11432/** Returns the currently programmed mode of the given pipe. */
11433struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11434 struct drm_crtc *crtc)
11435{
Chris Wilsonfac5e232016-07-04 11:34:36 +010011436 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020011438 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080011439 struct drm_display_mode *mode;
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +000011440 struct intel_crtc_state *pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -020011441 int htot = I915_READ(HTOTAL(cpu_transcoder));
11442 int hsync = I915_READ(HSYNC(cpu_transcoder));
11443 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11444 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +030011445 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -080011446
11447 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11448 if (!mode)
11449 return NULL;
11450
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +000011451 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11452 if (!pipe_config) {
11453 kfree(mode);
11454 return NULL;
11455 }
11456
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011457 /*
11458 * Construct a pipe_config sufficient for getting the clock info
11459 * back out of crtc_clock_get.
11460 *
11461 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11462 * to use a real value here instead.
11463 */
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +000011464 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11465 pipe_config->pixel_multiplier = 1;
11466 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11467 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11468 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11469 i9xx_crtc_clock_get(intel_crtc, pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011470
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +000011471 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -080011472 mode->hdisplay = (htot & 0xffff) + 1;
11473 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11474 mode->hsync_start = (hsync & 0xffff) + 1;
11475 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11476 mode->vdisplay = (vtot & 0xffff) + 1;
11477 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11478 mode->vsync_start = (vsync & 0xffff) + 1;
11479 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11480
11481 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -080011482
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +000011483 kfree(pipe_config);
11484
Jesse Barnes79e53942008-11-07 14:24:08 -080011485 return mode;
11486}
11487
11488static void intel_crtc_destroy(struct drm_crtc *crtc)
11489{
11490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +020011491 struct drm_device *dev = crtc->dev;
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011492 struct intel_flip_work *work;
Daniel Vetter67e77c52010-08-20 22:26:30 +020011493
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011494 spin_lock_irq(&dev->event_lock);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011495 work = intel_crtc->flip_work;
11496 intel_crtc->flip_work = NULL;
11497 spin_unlock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +020011498
Daniel Vetter5a21b662016-05-24 17:13:53 +020011499 if (work) {
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011500 cancel_work_sync(&work->mmio_work);
11501 cancel_work_sync(&work->unpin_work);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011502 kfree(work);
Daniel Vetter67e77c52010-08-20 22:26:30 +020011503 }
Jesse Barnes79e53942008-11-07 14:24:08 -080011504
11505 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +020011506
Jesse Barnes79e53942008-11-07 14:24:08 -080011507 kfree(intel_crtc);
11508}
11509
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011510static void intel_unpin_work_fn(struct work_struct *__work)
11511{
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011512 struct intel_flip_work *work =
11513 container_of(__work, struct intel_flip_work, unpin_work);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011514 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11515 struct drm_device *dev = crtc->base.dev;
11516 struct drm_plane *primary = crtc->base.primary;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011517
Daniel Vetter5a21b662016-05-24 17:13:53 +020011518 if (is_mmio_work(work))
11519 flush_work(&work->mmio_work);
11520
11521 mutex_lock(&dev->struct_mutex);
11522 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
Chris Wilsonf8c417c2016-07-20 13:31:53 +010011523 i915_gem_object_put(work->pending_flip_obj);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011524 mutex_unlock(&dev->struct_mutex);
11525
Chris Wilsone8a261e2016-07-20 13:31:49 +010011526 i915_gem_request_put(work->flip_queued_req);
11527
Chris Wilson5748b6a2016-08-04 16:32:38 +010011528 intel_frontbuffer_flip_complete(to_i915(dev),
11529 to_intel_plane(primary)->frontbuffer_bit);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011530 intel_fbc_post_update(crtc);
11531 drm_framebuffer_unreference(work->old_fb);
11532
11533 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11534 atomic_dec(&crtc->unpin_work_count);
11535
11536 kfree(work);
11537}
11538
11539/* Is 'a' after or equal to 'b'? */
11540static bool g4x_flip_count_after_eq(u32 a, u32 b)
11541{
11542 return !((a - b) & 0x80000000);
11543}
11544
11545static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11546 struct intel_flip_work *work)
11547{
11548 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010011549 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011550
Chris Wilson8af29b02016-09-09 14:11:47 +010011551 if (abort_flip_on_reset(crtc))
Daniel Vetter5a21b662016-05-24 17:13:53 +020011552 return true;
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011553
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020011554 /*
Daniel Vetter5a21b662016-05-24 17:13:53 +020011555 * The relevant registers doen't exist on pre-ctg.
11556 * As the flip done interrupt doesn't trigger for mmio
11557 * flips on gmch platforms, a flip count check isn't
11558 * really needed there. But since ctg has the registers,
11559 * include it in the check anyway.
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020011560 */
Daniel Vetter5a21b662016-05-24 17:13:53 +020011561 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11562 return true;
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020011563
Daniel Vetter5a21b662016-05-24 17:13:53 +020011564 /*
11565 * BDW signals flip done immediately if the plane
11566 * is disabled, even if the plane enable is already
11567 * armed to occur at the next vblank :(
11568 */
Maarten Lankhorsta6747b72016-05-17 15:08:01 +020011569
Daniel Vetter5a21b662016-05-24 17:13:53 +020011570 /*
11571 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11572 * used the same base address. In that case the mmio flip might
11573 * have completed, but the CS hasn't even executed the flip yet.
11574 *
11575 * A flip count check isn't enough as the CS might have updated
11576 * the base address just after start of vblank, but before we
11577 * managed to process the interrupt. This means we'd complete the
11578 * CS flip too soon.
11579 *
11580 * Combining both checks should get us a good enough result. It may
11581 * still happen that the CS flip has been executed, but has not
11582 * yet actually completed. But in case the base address is the same
11583 * anyway, we don't really care.
11584 */
11585 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11586 crtc->flip_work->gtt_offset &&
11587 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11588 crtc->flip_work->flip_count);
11589}
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020011590
Daniel Vetter5a21b662016-05-24 17:13:53 +020011591static bool
11592__pageflip_finished_mmio(struct intel_crtc *crtc,
11593 struct intel_flip_work *work)
11594{
11595 /*
11596 * MMIO work completes when vblank is different from
11597 * flip_queued_vblank.
11598 *
11599 * Reset counter value doesn't matter, this is handled by
11600 * i915_wait_request finishing early, so no need to handle
11601 * reset here.
11602 */
11603 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011604}
11605
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011606
11607static bool pageflip_finished(struct intel_crtc *crtc,
11608 struct intel_flip_work *work)
11609{
11610 if (!atomic_read(&work->pending))
11611 return false;
11612
11613 smp_rmb();
11614
Daniel Vetter5a21b662016-05-24 17:13:53 +020011615 if (is_mmio_work(work))
11616 return __pageflip_finished_mmio(crtc, work);
11617 else
11618 return __pageflip_finished_cs(crtc, work);
11619}
11620
11621void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11622{
Chris Wilson91c8a322016-07-05 10:40:23 +010011623 struct drm_device *dev = &dev_priv->drm;
Daniel Vetter5a21b662016-05-24 17:13:53 +020011624 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11626 struct intel_flip_work *work;
11627 unsigned long flags;
11628
11629 /* Ignore early vblank irqs */
11630 if (!crtc)
11631 return;
11632
Daniel Vetterf3260382014-09-15 14:55:23 +020011633 /*
Daniel Vetter5a21b662016-05-24 17:13:53 +020011634 * This is called both by irq handlers and the reset code (to complete
11635 * lost pageflips) so needs the full irqsave spinlocks.
Chris Wilsone7d841c2012-12-03 11:36:30 +000011636 */
Daniel Vetter5a21b662016-05-24 17:13:53 +020011637 spin_lock_irqsave(&dev->event_lock, flags);
11638 work = intel_crtc->flip_work;
11639
11640 if (work != NULL &&
11641 !is_mmio_work(work) &&
11642 pageflip_finished(intel_crtc, work))
11643 page_flip_completed(intel_crtc);
11644
11645 spin_unlock_irqrestore(&dev->event_lock, flags);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011646}
11647
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011648void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
Chris Wilsone7d841c2012-12-03 11:36:30 +000011649{
Chris Wilson91c8a322016-07-05 10:40:23 +010011650 struct drm_device *dev = &dev_priv->drm;
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11653 struct intel_flip_work *work;
11654 unsigned long flags;
11655
11656 /* Ignore early vblank irqs */
11657 if (!crtc)
11658 return;
11659
11660 /*
11661 * This is called both by irq handlers and the reset code (to complete
11662 * lost pageflips) so needs the full irqsave spinlocks.
11663 */
11664 spin_lock_irqsave(&dev->event_lock, flags);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011665 work = intel_crtc->flip_work;
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011666
Daniel Vetter5a21b662016-05-24 17:13:53 +020011667 if (work != NULL &&
11668 is_mmio_work(work) &&
11669 pageflip_finished(intel_crtc, work))
11670 page_flip_completed(intel_crtc);
Maarten Lankhorst68858432016-05-17 15:07:52 +020011671
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020011672 spin_unlock_irqrestore(&dev->event_lock, flags);
11673}
11674
Daniel Vetter5a21b662016-05-24 17:13:53 +020011675static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11676 struct intel_flip_work *work)
11677{
11678 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11679
11680 /* Ensure that the work item is consistent when activating it ... */
11681 smp_mb__before_atomic();
11682 atomic_set(&work->pending, 1);
11683}
11684
11685static int intel_gen2_queue_flip(struct drm_device *dev,
11686 struct drm_crtc *crtc,
11687 struct drm_framebuffer *fb,
11688 struct drm_i915_gem_object *obj,
11689 struct drm_i915_gem_request *req,
11690 uint32_t flags)
11691{
Chris Wilson7e37f882016-08-02 22:50:21 +010011692 struct intel_ring *ring = req->ring;
Daniel Vetter5a21b662016-05-24 17:13:53 +020011693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11694 u32 flip_mask;
11695 int ret;
11696
11697 ret = intel_ring_begin(req, 6);
11698 if (ret)
11699 return ret;
11700
11701 /* Can't queue multiple flips, so wait for the previous
11702 * one to finish before executing the next.
11703 */
11704 if (intel_crtc->plane)
11705 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11706 else
11707 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Chris Wilsonb5321f32016-08-02 22:50:18 +010011708 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11709 intel_ring_emit(ring, MI_NOOP);
11710 intel_ring_emit(ring, MI_DISPLAY_FLIP |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011711 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Chris Wilsonb5321f32016-08-02 22:50:18 +010011712 intel_ring_emit(ring, fb->pitches[0]);
11713 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11714 intel_ring_emit(ring, 0); /* aux display base address, unused */
Daniel Vetter5a21b662016-05-24 17:13:53 +020011715
11716 return 0;
11717}
11718
11719static int intel_gen3_queue_flip(struct drm_device *dev,
11720 struct drm_crtc *crtc,
11721 struct drm_framebuffer *fb,
11722 struct drm_i915_gem_object *obj,
11723 struct drm_i915_gem_request *req,
11724 uint32_t flags)
11725{
Chris Wilson7e37f882016-08-02 22:50:21 +010011726 struct intel_ring *ring = req->ring;
Daniel Vetter5a21b662016-05-24 17:13:53 +020011727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11728 u32 flip_mask;
11729 int ret;
11730
11731 ret = intel_ring_begin(req, 6);
11732 if (ret)
11733 return ret;
11734
11735 if (intel_crtc->plane)
11736 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11737 else
11738 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Chris Wilsonb5321f32016-08-02 22:50:18 +010011739 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11740 intel_ring_emit(ring, MI_NOOP);
11741 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011742 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Chris Wilsonb5321f32016-08-02 22:50:18 +010011743 intel_ring_emit(ring, fb->pitches[0]);
11744 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11745 intel_ring_emit(ring, MI_NOOP);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011746
11747 return 0;
11748}
11749
11750static int intel_gen4_queue_flip(struct drm_device *dev,
11751 struct drm_crtc *crtc,
11752 struct drm_framebuffer *fb,
11753 struct drm_i915_gem_object *obj,
11754 struct drm_i915_gem_request *req,
11755 uint32_t flags)
11756{
Chris Wilson7e37f882016-08-02 22:50:21 +010011757 struct intel_ring *ring = req->ring;
Chris Wilsonfac5e232016-07-04 11:34:36 +010011758 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11760 uint32_t pf, pipesrc;
11761 int ret;
11762
11763 ret = intel_ring_begin(req, 4);
11764 if (ret)
11765 return ret;
11766
11767 /* i965+ uses the linear or tiled offsets from the
11768 * Display Registers (which do not change across a page-flip)
11769 * so we need only reprogram the base address.
11770 */
Chris Wilsonb5321f32016-08-02 22:50:18 +010011771 intel_ring_emit(ring, MI_DISPLAY_FLIP |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011772 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Chris Wilsonb5321f32016-08-02 22:50:18 +010011773 intel_ring_emit(ring, fb->pitches[0]);
11774 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
Ville Syrjälä72618eb2016-02-04 20:38:20 +020011775 intel_fb_modifier_to_tiling(fb->modifier[0]));
Daniel Vetter5a21b662016-05-24 17:13:53 +020011776
11777 /* XXX Enabling the panel-fitter across page-flip is so far
11778 * untested on non-native modes, so ignore it for now.
11779 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11780 */
11781 pf = 0;
11782 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Chris Wilsonb5321f32016-08-02 22:50:18 +010011783 intel_ring_emit(ring, pf | pipesrc);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011784
11785 return 0;
11786}
11787
11788static int intel_gen6_queue_flip(struct drm_device *dev,
11789 struct drm_crtc *crtc,
11790 struct drm_framebuffer *fb,
11791 struct drm_i915_gem_object *obj,
11792 struct drm_i915_gem_request *req,
11793 uint32_t flags)
11794{
Chris Wilson7e37f882016-08-02 22:50:21 +010011795 struct intel_ring *ring = req->ring;
Chris Wilsonfac5e232016-07-04 11:34:36 +010011796 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11798 uint32_t pf, pipesrc;
11799 int ret;
11800
11801 ret = intel_ring_begin(req, 4);
11802 if (ret)
11803 return ret;
11804
Chris Wilsonb5321f32016-08-02 22:50:18 +010011805 intel_ring_emit(ring, MI_DISPLAY_FLIP |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011806 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Ville Syrjälä72618eb2016-02-04 20:38:20 +020011807 intel_ring_emit(ring, fb->pitches[0] |
11808 intel_fb_modifier_to_tiling(fb->modifier[0]));
Chris Wilsonb5321f32016-08-02 22:50:18 +010011809 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011810
11811 /* Contrary to the suggestions in the documentation,
11812 * "Enable Panel Fitter" does not seem to be required when page
11813 * flipping with a non-native mode, and worse causes a normal
11814 * modeset to fail.
11815 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11816 */
11817 pf = 0;
11818 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Chris Wilsonb5321f32016-08-02 22:50:18 +010011819 intel_ring_emit(ring, pf | pipesrc);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011820
11821 return 0;
11822}
11823
11824static int intel_gen7_queue_flip(struct drm_device *dev,
11825 struct drm_crtc *crtc,
11826 struct drm_framebuffer *fb,
11827 struct drm_i915_gem_object *obj,
11828 struct drm_i915_gem_request *req,
11829 uint32_t flags)
11830{
Chris Wilson7e37f882016-08-02 22:50:21 +010011831 struct intel_ring *ring = req->ring;
Daniel Vetter5a21b662016-05-24 17:13:53 +020011832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11833 uint32_t plane_bit = 0;
11834 int len, ret;
11835
11836 switch (intel_crtc->plane) {
11837 case PLANE_A:
11838 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11839 break;
11840 case PLANE_B:
11841 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11842 break;
11843 case PLANE_C:
11844 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11845 break;
11846 default:
11847 WARN_ONCE(1, "unknown plane in flip command\n");
11848 return -ENODEV;
11849 }
11850
11851 len = 4;
Chris Wilsonb5321f32016-08-02 22:50:18 +010011852 if (req->engine->id == RCS) {
Daniel Vetter5a21b662016-05-24 17:13:53 +020011853 len += 6;
11854 /*
11855 * On Gen 8, SRM is now taking an extra dword to accommodate
11856 * 48bits addresses, and we need a NOOP for the batch size to
11857 * stay even.
11858 */
11859 if (IS_GEN8(dev))
11860 len += 2;
11861 }
11862
11863 /*
11864 * BSpec MI_DISPLAY_FLIP for IVB:
11865 * "The full packet must be contained within the same cache line."
11866 *
11867 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11868 * cacheline, if we ever start emitting more commands before
11869 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11870 * then do the cacheline alignment, and finally emit the
11871 * MI_DISPLAY_FLIP.
11872 */
11873 ret = intel_ring_cacheline_align(req);
11874 if (ret)
11875 return ret;
11876
11877 ret = intel_ring_begin(req, len);
11878 if (ret)
11879 return ret;
11880
11881 /* Unmask the flip-done completion message. Note that the bspec says that
11882 * we should do this for both the BCS and RCS, and that we must not unmask
11883 * more than one flip event at any time (or ensure that one flip message
11884 * can be sent by waiting for flip-done prior to queueing new flips).
11885 * Experimentation says that BCS works despite DERRMR masking all
11886 * flip-done completion events and that unmasking all planes at once
11887 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11888 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11889 */
Chris Wilsonb5321f32016-08-02 22:50:18 +010011890 if (req->engine->id == RCS) {
11891 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11892 intel_ring_emit_reg(ring, DERRMR);
11893 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011894 DERRMR_PIPEB_PRI_FLIP_DONE |
11895 DERRMR_PIPEC_PRI_FLIP_DONE));
11896 if (IS_GEN8(dev))
Chris Wilsonb5321f32016-08-02 22:50:18 +010011897 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011898 MI_SRM_LRM_GLOBAL_GTT);
11899 else
Chris Wilsonb5321f32016-08-02 22:50:18 +010011900 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
Daniel Vetter5a21b662016-05-24 17:13:53 +020011901 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonb5321f32016-08-02 22:50:18 +010011902 intel_ring_emit_reg(ring, DERRMR);
Chris Wilsonbde13eb2016-08-15 10:49:07 +010011903 intel_ring_emit(ring,
11904 i915_ggtt_offset(req->engine->scratch) + 256);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011905 if (IS_GEN8(dev)) {
Chris Wilsonb5321f32016-08-02 22:50:18 +010011906 intel_ring_emit(ring, 0);
11907 intel_ring_emit(ring, MI_NOOP);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011908 }
11909 }
11910
Chris Wilsonb5321f32016-08-02 22:50:18 +010011911 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä72618eb2016-02-04 20:38:20 +020011912 intel_ring_emit(ring, fb->pitches[0] |
11913 intel_fb_modifier_to_tiling(fb->modifier[0]));
Chris Wilsonb5321f32016-08-02 22:50:18 +010011914 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11915 intel_ring_emit(ring, (MI_NOOP));
Daniel Vetter5a21b662016-05-24 17:13:53 +020011916
11917 return 0;
11918}
11919
11920static bool use_mmio_flip(struct intel_engine_cs *engine,
11921 struct drm_i915_gem_object *obj)
11922{
Chris Wilsonc37efb92016-06-17 08:28:47 +010011923 struct reservation_object *resv;
11924
Daniel Vetter5a21b662016-05-24 17:13:53 +020011925 /*
11926 * This is not being used for older platforms, because
11927 * non-availability of flip done interrupt forces us to use
11928 * CS flips. Older platforms derive flip done using some clever
11929 * tricks involving the flip_pending status bits and vblank irqs.
11930 * So using MMIO flips there would disrupt this mechanism.
11931 */
11932
11933 if (engine == NULL)
11934 return true;
11935
11936 if (INTEL_GEN(engine->i915) < 5)
11937 return false;
11938
11939 if (i915.use_mmio_flip < 0)
11940 return false;
11941 else if (i915.use_mmio_flip > 0)
11942 return true;
11943 else if (i915.enable_execlists)
11944 return true;
Chris Wilsonc37efb92016-06-17 08:28:47 +010011945
11946 resv = i915_gem_object_get_dmabuf_resv(obj);
11947 if (resv && !reservation_object_test_signaled_rcu(resv, false))
Daniel Vetter5a21b662016-05-24 17:13:53 +020011948 return true;
Chris Wilsonc37efb92016-06-17 08:28:47 +010011949
Chris Wilsond72d9082016-08-04 07:52:31 +010011950 return engine != i915_gem_active_get_engine(&obj->last_write,
11951 &obj->base.dev->struct_mutex);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011952}
11953
11954static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11955 unsigned int rotation,
11956 struct intel_flip_work *work)
11957{
11958 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010011959 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011960 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11961 const enum pipe pipe = intel_crtc->pipe;
Ville Syrjäläd2196772016-01-28 18:33:11 +020011962 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
Daniel Vetter5a21b662016-05-24 17:13:53 +020011963
11964 ctl = I915_READ(PLANE_CTL(pipe, 0));
11965 ctl &= ~PLANE_CTL_TILED_MASK;
11966 switch (fb->modifier[0]) {
11967 case DRM_FORMAT_MOD_NONE:
11968 break;
11969 case I915_FORMAT_MOD_X_TILED:
11970 ctl |= PLANE_CTL_TILED_X;
11971 break;
11972 case I915_FORMAT_MOD_Y_TILED:
11973 ctl |= PLANE_CTL_TILED_Y;
11974 break;
11975 case I915_FORMAT_MOD_Yf_TILED:
11976 ctl |= PLANE_CTL_TILED_YF;
11977 break;
11978 default:
11979 MISSING_CASE(fb->modifier[0]);
11980 }
11981
11982 /*
Daniel Vetter5a21b662016-05-24 17:13:53 +020011983 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11984 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11985 */
11986 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11987 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11988
11989 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11990 POSTING_READ(PLANE_SURF(pipe, 0));
11991}
11992
11993static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11994 struct intel_flip_work *work)
11995{
11996 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010011997 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä72618eb2016-02-04 20:38:20 +020011998 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
Daniel Vetter5a21b662016-05-24 17:13:53 +020011999 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12000 u32 dspcntr;
12001
12002 dspcntr = I915_READ(reg);
12003
Ville Syrjälä72618eb2016-02-04 20:38:20 +020012004 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
Daniel Vetter5a21b662016-05-24 17:13:53 +020012005 dspcntr |= DISPPLANE_TILED;
12006 else
12007 dspcntr &= ~DISPPLANE_TILED;
12008
12009 I915_WRITE(reg, dspcntr);
12010
12011 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12012 POSTING_READ(DSPSURF(intel_crtc->plane));
12013}
12014
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020012015static void intel_mmio_flip_work_func(struct work_struct *w)
Damien Lespiauff944562014-11-20 14:58:16 +000012016{
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +020012017 struct intel_flip_work *work =
12018 container_of(w, struct intel_flip_work, mmio_work);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012019 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12020 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12021 struct intel_framebuffer *intel_fb =
12022 to_intel_framebuffer(crtc->base.primary->fb);
12023 struct drm_i915_gem_object *obj = intel_fb->obj;
Chris Wilsonc37efb92016-06-17 08:28:47 +010012024 struct reservation_object *resv;
Daniel Vetter5a21b662016-05-24 17:13:53 +020012025
12026 if (work->flip_queued_req)
Chris Wilson776f3232016-08-04 07:52:40 +010012027 WARN_ON(i915_wait_request(work->flip_queued_req,
Chris Wilsonea746f32016-09-09 14:11:49 +010012028 0, NULL, NO_WAITBOOST));
Daniel Vetter5a21b662016-05-24 17:13:53 +020012029
12030 /* For framebuffer backed by dmabuf, wait for fence */
Chris Wilsonc37efb92016-06-17 08:28:47 +010012031 resv = i915_gem_object_get_dmabuf_resv(obj);
12032 if (resv)
12033 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
Daniel Vetter5a21b662016-05-24 17:13:53 +020012034 MAX_SCHEDULE_TIMEOUT) < 0);
12035
12036 intel_pipe_update_start(crtc);
12037
12038 if (INTEL_GEN(dev_priv) >= 9)
12039 skl_do_mmio_flip(crtc, work->rotation, work);
12040 else
12041 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12042 ilk_do_mmio_flip(crtc, work);
12043
12044 intel_pipe_update_end(crtc, work);
12045}
12046
12047static int intel_default_queue_flip(struct drm_device *dev,
12048 struct drm_crtc *crtc,
12049 struct drm_framebuffer *fb,
12050 struct drm_i915_gem_object *obj,
12051 struct drm_i915_gem_request *req,
12052 uint32_t flags)
12053{
12054 return -ENODEV;
12055}
12056
12057static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12058 struct intel_crtc *intel_crtc,
12059 struct intel_flip_work *work)
12060{
12061 u32 addr, vblank;
12062
12063 if (!atomic_read(&work->pending))
12064 return false;
12065
12066 smp_rmb();
12067
12068 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12069 if (work->flip_ready_vblank == 0) {
12070 if (work->flip_queued_req &&
Chris Wilsonf69a02c2016-07-01 17:23:16 +010012071 !i915_gem_request_completed(work->flip_queued_req))
Daniel Vetter5a21b662016-05-24 17:13:53 +020012072 return false;
12073
12074 work->flip_ready_vblank = vblank;
12075 }
12076
12077 if (vblank - work->flip_ready_vblank < 3)
12078 return false;
12079
12080 /* Potential stall - if we see that the flip has happened,
12081 * assume a missed interrupt. */
12082 if (INTEL_GEN(dev_priv) >= 4)
12083 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12084 else
12085 addr = I915_READ(DSPADDR(intel_crtc->plane));
12086
12087 /* There is a potential issue here with a false positive after a flip
12088 * to the same address. We could address this by checking for a
12089 * non-incrementing frame counter.
12090 */
12091 return addr == work->gtt_offset;
12092}
12093
12094void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12095{
Chris Wilson91c8a322016-07-05 10:40:23 +010012096 struct drm_device *dev = &dev_priv->drm;
Daniel Vetter5a21b662016-05-24 17:13:53 +020012097 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012099 struct intel_flip_work *work;
12100
12101 WARN_ON(!in_interrupt());
12102
12103 if (crtc == NULL)
12104 return;
12105
12106 spin_lock(&dev->event_lock);
12107 work = intel_crtc->flip_work;
12108
12109 if (work != NULL && !is_mmio_work(work) &&
12110 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12111 WARN_ONCE(1,
12112 "Kicking stuck page flip: queued at %d, now %d\n",
12113 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12114 page_flip_completed(intel_crtc);
12115 work = NULL;
12116 }
12117
12118 if (work != NULL && !is_mmio_work(work) &&
12119 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12120 intel_queue_rps_boost_for_request(work->flip_queued_req);
12121 spin_unlock(&dev->event_lock);
12122}
12123
12124static int intel_crtc_page_flip(struct drm_crtc *crtc,
12125 struct drm_framebuffer *fb,
12126 struct drm_pending_vblank_event *event,
12127 uint32_t page_flip_flags)
12128{
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012129 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010012130 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012131 struct drm_framebuffer *old_fb = crtc->primary->fb;
12132 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12134 struct drm_plane *primary = crtc->primary;
12135 enum pipe pipe = intel_crtc->pipe;
12136 struct intel_flip_work *work;
12137 struct intel_engine_cs *engine;
12138 bool mmio_flip;
Chris Wilson8e637172016-08-02 22:50:26 +010012139 struct drm_i915_gem_request *request;
Chris Wilson058d88c2016-08-15 10:49:06 +010012140 struct i915_vma *vma;
Daniel Vetter5a21b662016-05-24 17:13:53 +020012141 int ret;
Sourab Gupta84c33a62014-06-02 16:47:17 +053012142
Daniel Vetter5a21b662016-05-24 17:13:53 +020012143 /*
12144 * drm_mode_page_flip_ioctl() should already catch this, but double
12145 * check to be safe. In the future we may enable pageflipping from
12146 * a disabled primary plane.
12147 */
12148 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12149 return -EBUSY;
Maarten Lankhorsta6747b72016-05-17 15:08:01 +020012150
Daniel Vetter5a21b662016-05-24 17:13:53 +020012151 /* Can't change pixel format via MI display flips. */
12152 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12153 return -EINVAL;
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012154
Daniel Vetter5a21b662016-05-24 17:13:53 +020012155 /*
12156 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12157 * Note that pitch changes could also affect these register.
12158 */
12159 if (INTEL_INFO(dev)->gen > 3 &&
12160 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12161 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12162 return -EINVAL;
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012163
Daniel Vetter5a21b662016-05-24 17:13:53 +020012164 if (i915_terminally_wedged(&dev_priv->gpu_error))
12165 goto out_hang;
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012166
Daniel Vetter5a21b662016-05-24 17:13:53 +020012167 work = kzalloc(sizeof(*work), GFP_KERNEL);
12168 if (work == NULL)
12169 return -ENOMEM;
12170
12171 work->event = event;
12172 work->crtc = crtc;
12173 work->old_fb = old_fb;
12174 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
Sourab Gupta84c33a62014-06-02 16:47:17 +053012175
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020012176 ret = drm_crtc_vblank_get(crtc);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012177 if (ret)
12178 goto free_work;
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020012179
Daniel Vetter5a21b662016-05-24 17:13:53 +020012180 /* We borrow the event spin lock for protecting flip_work */
12181 spin_lock_irq(&dev->event_lock);
12182 if (intel_crtc->flip_work) {
12183 /* Before declaring the flip queue wedged, check if
12184 * the hardware completed the operation behind our backs.
12185 */
12186 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12187 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12188 page_flip_completed(intel_crtc);
12189 } else {
12190 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12191 spin_unlock_irq(&dev->event_lock);
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020012192
Daniel Vetter5a21b662016-05-24 17:13:53 +020012193 drm_crtc_vblank_put(crtc);
12194 kfree(work);
12195 return -EBUSY;
12196 }
12197 }
12198 intel_crtc->flip_work = work;
12199 spin_unlock_irq(&dev->event_lock);
Alex Goinsfd8e0582015-11-25 18:43:38 -080012200
Daniel Vetter5a21b662016-05-24 17:13:53 +020012201 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12202 flush_workqueue(dev_priv->wq);
12203
12204 /* Reference the objects for the scheduled work. */
12205 drm_framebuffer_reference(work->old_fb);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012206
12207 crtc->primary->fb = fb;
12208 update_state_fb(crtc->primary);
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +020012209
Chris Wilson25dc5562016-07-20 13:31:52 +010012210 work->pending_flip_obj = i915_gem_object_get(obj);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012211
12212 ret = i915_mutex_lock_interruptible(dev);
12213 if (ret)
12214 goto cleanup;
12215
Chris Wilson8af29b02016-09-09 14:11:47 +010012216 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12217 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
Daniel Vetter5a21b662016-05-24 17:13:53 +020012218 ret = -EIO;
12219 goto cleanup;
12220 }
12221
12222 atomic_inc(&intel_crtc->unpin_work_count);
12223
12224 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12225 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12226
12227 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12228 engine = &dev_priv->engine[BCS];
Ville Syrjälä72618eb2016-02-04 20:38:20 +020012229 if (fb->modifier[0] != old_fb->modifier[0])
Daniel Vetter5a21b662016-05-24 17:13:53 +020012230 /* vlv: DISPLAY_FLIP fails to change tiling */
12231 engine = NULL;
12232 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12233 engine = &dev_priv->engine[BCS];
12234 } else if (INTEL_INFO(dev)->gen >= 7) {
Chris Wilsond72d9082016-08-04 07:52:31 +010012235 engine = i915_gem_active_get_engine(&obj->last_write,
12236 &obj->base.dev->struct_mutex);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012237 if (engine == NULL || engine->id != RCS)
12238 engine = &dev_priv->engine[BCS];
12239 } else {
12240 engine = &dev_priv->engine[RCS];
12241 }
12242
12243 mmio_flip = use_mmio_flip(engine, obj);
12244
Chris Wilson058d88c2016-08-15 10:49:06 +010012245 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12246 if (IS_ERR(vma)) {
12247 ret = PTR_ERR(vma);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012248 goto cleanup_pending;
Chris Wilson058d88c2016-08-15 10:49:06 +010012249 }
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012250
Ville Syrjälä6687c902015-09-15 13:16:41 +030012251 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012252 work->gtt_offset += intel_crtc->dspaddr_offset;
12253 work->rotation = crtc->primary->state->rotation;
12254
Paulo Zanoni1f0613162016-08-17 16:41:44 -030012255 /*
12256 * There's the potential that the next frame will not be compatible with
12257 * FBC, so we want to call pre_update() before the actual page flip.
12258 * The problem is that pre_update() caches some information about the fb
12259 * object, so we want to do this only after the object is pinned. Let's
12260 * be on the safe side and do this immediately before scheduling the
12261 * flip.
12262 */
12263 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12264 to_intel_plane_state(primary->state));
12265
Daniel Vetter5a21b662016-05-24 17:13:53 +020012266 if (mmio_flip) {
12267 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12268
Chris Wilsond72d9082016-08-04 07:52:31 +010012269 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12270 &obj->base.dev->struct_mutex);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012271 schedule_work(&work->mmio_work);
12272 } else {
Chris Wilson8e637172016-08-02 22:50:26 +010012273 request = i915_gem_request_alloc(engine, engine->last_context);
12274 if (IS_ERR(request)) {
12275 ret = PTR_ERR(request);
12276 goto cleanup_unpin;
12277 }
12278
Chris Wilsona2bc4692016-09-09 14:11:56 +010012279 ret = i915_gem_request_await_object(request, obj, false);
Chris Wilson8e637172016-08-02 22:50:26 +010012280 if (ret)
12281 goto cleanup_request;
12282
Daniel Vetter5a21b662016-05-24 17:13:53 +020012283 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12284 page_flip_flags);
12285 if (ret)
Chris Wilson8e637172016-08-02 22:50:26 +010012286 goto cleanup_request;
Daniel Vetter5a21b662016-05-24 17:13:53 +020012287
12288 intel_mark_page_flip_active(intel_crtc, work);
12289
Chris Wilson8e637172016-08-02 22:50:26 +010012290 work->flip_queued_req = i915_gem_request_get(request);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012291 i915_add_request_no_flush(request);
Maarten Lankhorst143f73b32016-05-17 15:07:54 +020012292 }
12293
Daniel Vetter5a21b662016-05-24 17:13:53 +020012294 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12295 to_intel_plane(primary)->frontbuffer_bit);
12296 mutex_unlock(&dev->struct_mutex);
12297
Chris Wilson5748b6a2016-08-04 16:32:38 +010012298 intel_frontbuffer_flip_prepare(to_i915(dev),
Daniel Vetter5a21b662016-05-24 17:13:53 +020012299 to_intel_plane(primary)->frontbuffer_bit);
12300
12301 trace_i915_flip_request(intel_crtc->plane, obj);
12302
12303 return 0;
12304
Chris Wilson8e637172016-08-02 22:50:26 +010012305cleanup_request:
12306 i915_add_request_no_flush(request);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012307cleanup_unpin:
12308 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12309cleanup_pending:
Daniel Vetter5a21b662016-05-24 17:13:53 +020012310 atomic_dec(&intel_crtc->unpin_work_count);
12311 mutex_unlock(&dev->struct_mutex);
12312cleanup:
12313 crtc->primary->fb = old_fb;
12314 update_state_fb(crtc->primary);
12315
Chris Wilson34911fd2016-07-20 13:31:54 +010012316 i915_gem_object_put_unlocked(obj);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012317 drm_framebuffer_unreference(work->old_fb);
12318
12319 spin_lock_irq(&dev->event_lock);
12320 intel_crtc->flip_work = NULL;
12321 spin_unlock_irq(&dev->event_lock);
12322
12323 drm_crtc_vblank_put(crtc);
12324free_work:
12325 kfree(work);
12326
12327 if (ret == -EIO) {
12328 struct drm_atomic_state *state;
12329 struct drm_plane_state *plane_state;
12330
12331out_hang:
12332 state = drm_atomic_state_alloc(dev);
12333 if (!state)
12334 return -ENOMEM;
12335 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12336
12337retry:
12338 plane_state = drm_atomic_get_plane_state(state, primary);
12339 ret = PTR_ERR_OR_ZERO(plane_state);
12340 if (!ret) {
12341 drm_atomic_set_fb_for_plane(plane_state, fb);
12342
12343 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12344 if (!ret)
12345 ret = drm_atomic_commit(state);
12346 }
12347
12348 if (ret == -EDEADLK) {
12349 drm_modeset_backoff(state->acquire_ctx);
12350 drm_atomic_state_clear(state);
12351 goto retry;
12352 }
12353
Chris Wilson08536952016-10-14 13:18:18 +010012354 drm_atomic_state_put(state);
Daniel Vetter5a21b662016-05-24 17:13:53 +020012355
12356 if (ret == 0 && event) {
12357 spin_lock_irq(&dev->event_lock);
12358 drm_crtc_send_vblank_event(crtc, event);
12359 spin_unlock_irq(&dev->event_lock);
12360 }
12361 }
12362 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012363}
12364
Daniel Vetter5a21b662016-05-24 17:13:53 +020012365
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012366/**
12367 * intel_wm_need_update - Check whether watermarks need updating
12368 * @plane: drm plane
12369 * @state: new plane state
12370 *
12371 * Check current plane state versus the new one to determine whether
12372 * watermarks need to be recalculated.
12373 *
12374 * Returns true or false.
12375 */
12376static bool intel_wm_need_update(struct drm_plane *plane,
12377 struct drm_plane_state *state)
12378{
Matt Roperd21fbe82015-09-24 15:53:12 -070012379 struct intel_plane_state *new = to_intel_plane_state(state);
12380 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12381
12382 /* Update watermarks on tiling or size changes. */
Ville Syrjälä936e71e2016-07-26 19:06:59 +030012383 if (new->base.visible != cur->base.visible)
Maarten Lankhorst92826fc2015-12-03 13:49:13 +010012384 return true;
12385
12386 if (!cur->base.fb || !new->base.fb)
12387 return false;
12388
12389 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12390 cur->base.rotation != new->base.rotation ||
Ville Syrjälä936e71e2016-07-26 19:06:59 +030012391 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12392 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12393 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12394 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012395 return true;
12396
12397 return false;
12398}
12399
Matt Roperd21fbe82015-09-24 15:53:12 -070012400static bool needs_scaling(struct intel_plane_state *state)
12401{
Ville Syrjälä936e71e2016-07-26 19:06:59 +030012402 int src_w = drm_rect_width(&state->base.src) >> 16;
12403 int src_h = drm_rect_height(&state->base.src) >> 16;
12404 int dst_w = drm_rect_width(&state->base.dst);
12405 int dst_h = drm_rect_height(&state->base.dst);
Matt Roperd21fbe82015-09-24 15:53:12 -070012406
12407 return (src_w != dst_w || src_h != dst_h);
12408}
12409
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012410int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12411 struct drm_plane_state *plane_state)
12412{
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +010012413 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012414 struct drm_crtc *crtc = crtc_state->crtc;
12415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12416 struct drm_plane *plane = plane_state->plane;
12417 struct drm_device *dev = crtc->dev;
Matt Ropered4a6a72016-02-23 17:20:13 -080012418 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012419 struct intel_plane_state *old_plane_state =
12420 to_intel_plane_state(plane->state);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012421 bool mode_changed = needs_modeset(crtc_state);
12422 bool was_crtc_enabled = crtc->state->active;
12423 bool is_crtc_enabled = crtc_state->active;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012424 bool turn_off, turn_on, visible, was_visible;
12425 struct drm_framebuffer *fb = plane_state->fb;
Ville Syrjälä78108b72016-05-27 20:59:19 +030012426 int ret;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012427
Chris Wilson84114992016-07-02 15:36:06 +010012428 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012429 ret = skl_update_scaler_plane(
12430 to_intel_crtc_state(crtc_state),
12431 to_intel_plane_state(plane_state));
12432 if (ret)
12433 return ret;
12434 }
12435
Ville Syrjälä936e71e2016-07-26 19:06:59 +030012436 was_visible = old_plane_state->base.visible;
12437 visible = to_intel_plane_state(plane_state)->base.visible;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012438
12439 if (!was_crtc_enabled && WARN_ON(was_visible))
12440 was_visible = false;
12441
Maarten Lankhorst35c08f42015-12-03 14:31:07 +010012442 /*
12443 * Visibility is calculated as if the crtc was on, but
12444 * after scaler setup everything depends on it being off
12445 * when the crtc isn't active.
Ville Syrjäläf818ffe2016-04-29 17:31:18 +030012446 *
12447 * FIXME this is wrong for watermarks. Watermarks should also
12448 * be computed as if the pipe would be active. Perhaps move
12449 * per-plane wm computation to the .check_plane() hook, and
12450 * only combine the results from all planes in the current place?
Maarten Lankhorst35c08f42015-12-03 14:31:07 +010012451 */
12452 if (!is_crtc_enabled)
Ville Syrjälä936e71e2016-07-26 19:06:59 +030012453 to_intel_plane_state(plane_state)->base.visible = visible = false;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012454
12455 if (!was_visible && !visible)
12456 return 0;
12457
Maarten Lankhorste8861672016-02-24 11:24:26 +010012458 if (fb != old_plane_state->base.fb)
12459 pipe_config->fb_changed = true;
12460
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012461 turn_off = was_visible && (!visible || mode_changed);
12462 turn_on = visible && (!was_visible || mode_changed);
12463
Ville Syrjälä72660ce2016-05-27 20:59:20 +030012464 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
Ville Syrjälä78108b72016-05-27 20:59:19 +030012465 intel_crtc->base.base.id,
12466 intel_crtc->base.name,
Ville Syrjälä72660ce2016-05-27 20:59:20 +030012467 plane->base.id, plane->name,
12468 fb ? fb->base.id : -1);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012469
Ville Syrjälä72660ce2016-05-27 20:59:20 +030012470 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12471 plane->base.id, plane->name,
12472 was_visible, visible,
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012473 turn_off, turn_on, mode_changed);
12474
Ville Syrjäläcaed3612016-03-09 19:07:25 +020012475 if (turn_on) {
12476 pipe_config->update_wm_pre = true;
12477
12478 /* must disable cxsr around plane enable/disable */
12479 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12480 pipe_config->disable_cxsr = true;
12481 } else if (turn_off) {
12482 pipe_config->update_wm_post = true;
Maarten Lankhorst92826fc2015-12-03 13:49:13 +010012483
Ville Syrjälä852eb002015-06-24 22:00:07 +030012484 /* must disable cxsr around plane enable/disable */
Maarten Lankhorste8861672016-02-24 11:24:26 +010012485 if (plane->type != DRM_PLANE_TYPE_CURSOR)
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +010012486 pipe_config->disable_cxsr = true;
Ville Syrjälä852eb002015-06-24 22:00:07 +030012487 } else if (intel_wm_need_update(plane, plane_state)) {
Ville Syrjäläcaed3612016-03-09 19:07:25 +020012488 /* FIXME bollocks */
12489 pipe_config->update_wm_pre = true;
12490 pipe_config->update_wm_post = true;
Ville Syrjälä852eb002015-06-24 22:00:07 +030012491 }
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012492
Matt Ropered4a6a72016-02-23 17:20:13 -080012493 /* Pre-gen9 platforms need two-step watermark updates */
Ville Syrjäläcaed3612016-03-09 19:07:25 +020012494 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12495 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
Matt Ropered4a6a72016-02-23 17:20:13 -080012496 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12497
Rodrigo Vivi8be6ca82015-08-24 16:38:23 -070012498 if (visible || was_visible)
Maarten Lankhorstcd202f62016-03-09 10:35:44 +010012499 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030012500
Maarten Lankhorst31ae71f2016-03-09 10:35:45 +010012501 /*
12502 * WaCxSRDisabledForSpriteScaling:ivb
12503 *
12504 * cstate->update_wm was already set above, so this flag will
12505 * take effect when we commit and program watermarks.
12506 */
12507 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12508 needs_scaling(to_intel_plane_state(plane_state)) &&
12509 !needs_scaling(old_plane_state))
12510 pipe_config->disable_lp_wm = true;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012511
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020012512 return 0;
12513}
12514
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012515static bool encoders_cloneable(const struct intel_encoder *a,
12516 const struct intel_encoder *b)
12517{
12518 /* masks could be asymmetric, so check both ways */
12519 return a == b || (a->cloneable & (1 << b->type) &&
12520 b->cloneable & (1 << a->type));
12521}
12522
12523static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12524 struct intel_crtc *crtc,
12525 struct intel_encoder *encoder)
12526{
12527 struct intel_encoder *source_encoder;
12528 struct drm_connector *connector;
12529 struct drm_connector_state *connector_state;
12530 int i;
12531
12532 for_each_connector_in_state(state, connector, connector_state, i) {
12533 if (connector_state->crtc != &crtc->base)
12534 continue;
12535
12536 source_encoder =
12537 to_intel_encoder(connector_state->best_encoder);
12538 if (!encoders_cloneable(encoder, source_encoder))
12539 return false;
12540 }
12541
12542 return true;
12543}
12544
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012545static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12546 struct drm_crtc_state *crtc_state)
12547{
Maarten Lankhorstcf5a15b2015-06-15 12:33:41 +020012548 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010012549 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstcf5a15b2015-06-15 12:33:41 +020012551 struct intel_crtc_state *pipe_config =
12552 to_intel_crtc_state(crtc_state);
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012553 struct drm_atomic_state *state = crtc_state->state;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012554 int ret;
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012555 bool mode_changed = needs_modeset(crtc_state);
12556
Ville Syrjälä852eb002015-06-24 22:00:07 +030012557 if (mode_changed && !crtc_state->active)
Ville Syrjäläcaed3612016-03-09 19:07:25 +020012558 pipe_config->update_wm_post = true;
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +020012559
Maarten Lankhorstad421372015-06-15 12:33:42 +020012560 if (mode_changed && crtc_state->enable &&
12561 dev_priv->display.crtc_compute_clock &&
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020012562 !WARN_ON(pipe_config->shared_dpll)) {
Maarten Lankhorstad421372015-06-15 12:33:42 +020012563 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12564 pipe_config);
12565 if (ret)
12566 return ret;
12567 }
12568
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000012569 if (crtc_state->color_mgmt_changed) {
12570 ret = intel_color_check(crtc, crtc_state);
12571 if (ret)
12572 return ret;
Lionel Landwerlined2eebb2016-05-25 14:30:41 +010012573
12574 /*
12575 * Changing color management on Intel hardware is
12576 * handled as part of planes update.
12577 */
12578 crtc_state->planes_changed = true;
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000012579 }
12580
Maarten Lankhorste435d6e2015-07-13 16:30:15 +020012581 ret = 0;
Matt Roper86c8bbb2015-09-24 15:53:16 -070012582 if (dev_priv->display.compute_pipe_wm) {
Maarten Lankhorste3bddde2016-03-01 11:07:22 +010012583 ret = dev_priv->display.compute_pipe_wm(pipe_config);
Matt Ropered4a6a72016-02-23 17:20:13 -080012584 if (ret) {
12585 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
Matt Roper86c8bbb2015-09-24 15:53:16 -070012586 return ret;
Matt Ropered4a6a72016-02-23 17:20:13 -080012587 }
12588 }
12589
12590 if (dev_priv->display.compute_intermediate_wm &&
12591 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12592 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12593 return 0;
12594
12595 /*
12596 * Calculate 'intermediate' watermarks that satisfy both the
12597 * old state and the new state. We can program these
12598 * immediately.
12599 */
12600 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12601 intel_crtc,
12602 pipe_config);
12603 if (ret) {
12604 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12605 return ret;
12606 }
Ville Syrjäläe3d54572016-05-13 10:10:42 -070012607 } else if (dev_priv->display.compute_intermediate_wm) {
12608 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12609 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
Matt Roper86c8bbb2015-09-24 15:53:16 -070012610 }
12611
Maarten Lankhorste435d6e2015-07-13 16:30:15 +020012612 if (INTEL_INFO(dev)->gen >= 9) {
12613 if (mode_changed)
12614 ret = skl_update_scaler_crtc(pipe_config);
12615
12616 if (!ret)
12617 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12618 pipe_config);
12619 }
12620
12621 return ret;
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012622}
12623
Jani Nikula65b38e02015-04-13 11:26:56 +030012624static const struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012625 .mode_set_base_atomic = intel_pipe_set_base_atomic,
Daniel Vetter5a21b662016-05-24 17:13:53 +020012626 .atomic_begin = intel_begin_crtc_commit,
12627 .atomic_flush = intel_finish_crtc_commit,
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012628 .atomic_check = intel_crtc_atomic_check,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012629};
12630
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020012631static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12632{
12633 struct intel_connector *connector;
12634
12635 for_each_intel_connector(dev, connector) {
Daniel Vetter8863dc72016-05-06 15:39:03 +020012636 if (connector->base.state->crtc)
12637 drm_connector_unreference(&connector->base);
12638
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020012639 if (connector->base.encoder) {
12640 connector->base.state->best_encoder =
12641 connector->base.encoder;
12642 connector->base.state->crtc =
12643 connector->base.encoder->crtc;
Daniel Vetter8863dc72016-05-06 15:39:03 +020012644
12645 drm_connector_reference(&connector->base);
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020012646 } else {
12647 connector->base.state->best_encoder = NULL;
12648 connector->base.state->crtc = NULL;
12649 }
12650 }
12651}
12652
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012653static void
Robin Schroereba905b2014-05-18 02:24:50 +020012654connected_sink_compute_bpp(struct intel_connector *connector,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012655 struct intel_crtc_state *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012656{
Ville Syrjälä6a2a5c52016-09-28 16:51:42 +030012657 const struct drm_display_info *info = &connector->base.display_info;
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012658 int bpp = pipe_config->pipe_bpp;
12659
12660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
Ville Syrjälä6a2a5c52016-09-28 16:51:42 +030012661 connector->base.base.id,
12662 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012663
12664 /* Don't use an invalid EDID bpc value */
Ville Syrjälä6a2a5c52016-09-28 16:51:42 +030012665 if (info->bpc != 0 && info->bpc * 3 < bpp) {
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012666 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
Ville Syrjälä6a2a5c52016-09-28 16:51:42 +030012667 bpp, info->bpc * 3);
12668 pipe_config->pipe_bpp = info->bpc * 3;
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012669 }
12670
Mario Kleiner196f9542016-07-06 12:05:45 +020012671 /* Clamp bpp to 8 on screens without EDID 1.4 */
Ville Syrjälä6a2a5c52016-09-28 16:51:42 +030012672 if (info->bpc == 0 && bpp > 24) {
Mario Kleiner196f9542016-07-06 12:05:45 +020012673 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12674 bpp);
12675 pipe_config->pipe_bpp = 24;
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012676 }
12677}
12678
12679static int
12680compute_baseline_pipe_bpp(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012681 struct intel_crtc_state *pipe_config)
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012682{
12683 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012684 struct drm_atomic_state *state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012685 struct drm_connector *connector;
12686 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012687 int bpp, i;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012688
Wayne Boyer666a4532015-12-09 12:29:35 -080012689 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012690 bpp = 10*3;
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012691 else if (INTEL_INFO(dev)->gen >= 5)
12692 bpp = 12*3;
12693 else
12694 bpp = 8*3;
12695
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012696
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012697 pipe_config->pipe_bpp = bpp;
12698
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012699 state = pipe_config->base.state;
12700
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012701 /* Clamp display bpp to EDID value */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012702 for_each_connector_in_state(state, connector, connector_state, i) {
12703 if (connector_state->crtc != &crtc->base)
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012704 continue;
12705
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012706 connected_sink_compute_bpp(to_intel_connector(connector),
12707 pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012708 }
12709
12710 return bpp;
12711}
12712
Daniel Vetter644db712013-09-19 14:53:58 +020012713static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12714{
12715 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12716 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010012717 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020012718 mode->crtc_hdisplay, mode->crtc_hsync_start,
12719 mode->crtc_hsync_end, mode->crtc_htotal,
12720 mode->crtc_vdisplay, mode->crtc_vsync_start,
12721 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12722}
12723
Daniel Vetterc0b03412013-05-28 12:05:54 +020012724static void intel_dump_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012725 struct intel_crtc_state *pipe_config,
Daniel Vetterc0b03412013-05-28 12:05:54 +020012726 const char *context)
12727{
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012728 struct drm_device *dev = crtc->base.dev;
12729 struct drm_plane *plane;
12730 struct intel_plane *intel_plane;
12731 struct intel_plane_state *state;
12732 struct drm_framebuffer *fb;
12733
Ville Syrjälä78108b72016-05-27 20:59:19 +030012734 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12735 crtc->base.base.id, crtc->base.name,
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012736 context, pipe_config, pipe_name(crtc->pipe));
Daniel Vetterc0b03412013-05-28 12:05:54 +020012737
Jani Nikulada205632016-03-15 21:51:10 +020012738 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
Daniel Vetterc0b03412013-05-28 12:05:54 +020012739 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12740 pipe_config->pipe_bpp, pipe_config->dither);
12741 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12742 pipe_config->has_pch_encoder,
12743 pipe_config->fdi_lanes,
12744 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12745 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12746 pipe_config->fdi_m_n.tu);
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012747 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
Ville Syrjälä37a56502016-06-22 21:57:04 +030012748 intel_crtc_has_dp_encoder(pipe_config),
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012749 pipe_config->lane_count,
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030012750 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12751 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12752 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012753
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012754 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
Ville Syrjälä37a56502016-06-22 21:57:04 +030012755 intel_crtc_has_dp_encoder(pipe_config),
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012756 pipe_config->lane_count,
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012757 pipe_config->dp_m2_n2.gmch_m,
12758 pipe_config->dp_m2_n2.gmch_n,
12759 pipe_config->dp_m2_n2.link_m,
12760 pipe_config->dp_m2_n2.link_n,
12761 pipe_config->dp_m2_n2.tu);
12762
Daniel Vetter55072d12014-11-20 16:10:28 +010012763 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12764 pipe_config->has_audio,
12765 pipe_config->has_infoframe);
12766
Daniel Vetterc0b03412013-05-28 12:05:54 +020012767 DRM_DEBUG_KMS("requested mode:\n");
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012768 drm_mode_debug_printmodeline(&pipe_config->base.mode);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012769 DRM_DEBUG_KMS("adjusted mode:\n");
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012770 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12771 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030012772 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030012773 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12774 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Tvrtko Ursulin0ec463d2015-05-13 16:51:08 +010012775 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12776 crtc->num_scalers,
12777 pipe_config->scaler_state.scaler_users,
12778 pipe_config->scaler_state.scaler_id);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012779 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12780 pipe_config->gmch_pfit.control,
12781 pipe_config->gmch_pfit.pgm_ratios,
12782 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010012783 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020012784 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010012785 pipe_config->pch_pfit.size,
12786 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030012787 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030012788 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012789
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012790 if (IS_BROXTON(dev)) {
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070012791 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012792 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
Imre Deakc8453332015-06-18 17:25:55 +030012793 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012794 pipe_config->dpll_hw_state.ebb0,
Imre Deak05712c12015-06-18 17:25:54 +030012795 pipe_config->dpll_hw_state.ebb4,
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012796 pipe_config->dpll_hw_state.pll0,
12797 pipe_config->dpll_hw_state.pll1,
12798 pipe_config->dpll_hw_state.pll2,
12799 pipe_config->dpll_hw_state.pll3,
12800 pipe_config->dpll_hw_state.pll6,
12801 pipe_config->dpll_hw_state.pll8,
Imre Deak05712c12015-06-18 17:25:54 +030012802 pipe_config->dpll_hw_state.pll9,
Imre Deakc8453332015-06-18 17:25:55 +030012803 pipe_config->dpll_hw_state.pll10,
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012804 pipe_config->dpll_hw_state.pcsdw12);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070012805 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070012806 DRM_DEBUG_KMS("dpll_hw_state: "
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012807 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012808 pipe_config->dpll_hw_state.ctrl1,
12809 pipe_config->dpll_hw_state.cfgcr1,
12810 pipe_config->dpll_hw_state.cfgcr2);
12811 } else if (HAS_DDI(dev)) {
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -070012812 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
Maarten Lankhorst00490c22015-11-16 14:42:12 +010012813 pipe_config->dpll_hw_state.wrpll,
12814 pipe_config->dpll_hw_state.spll);
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012815 } else {
12816 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12817 "fp0: 0x%x, fp1: 0x%x\n",
12818 pipe_config->dpll_hw_state.dpll,
12819 pipe_config->dpll_hw_state.dpll_md,
12820 pipe_config->dpll_hw_state.fp0,
12821 pipe_config->dpll_hw_state.fp1);
12822 }
12823
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012824 DRM_DEBUG_KMS("planes on this crtc\n");
12825 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
Eric Engestromd3828142016-08-15 16:29:55 +010012826 char *format_name;
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012827 intel_plane = to_intel_plane(plane);
12828 if (intel_plane->pipe != crtc->pipe)
12829 continue;
12830
12831 state = to_intel_plane_state(plane->state);
12832 fb = state->base.fb;
12833 if (!fb) {
Ville Syrjälä1d577e02016-05-27 20:59:25 +030012834 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12835 plane->base.id, plane->name, state->scaler_id);
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012836 continue;
12837 }
12838
Eric Engestrom90844f02016-08-15 01:02:38 +010012839 format_name = drm_get_format_name(fb->pixel_format);
12840
Ville Syrjälä1d577e02016-05-27 20:59:25 +030012841 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12842 plane->base.id, plane->name);
12843 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
Eric Engestrom90844f02016-08-15 01:02:38 +010012844 fb->base.id, fb->width, fb->height, format_name);
Ville Syrjälä1d577e02016-05-27 20:59:25 +030012845 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12846 state->scaler_id,
Ville Syrjälä936e71e2016-07-26 19:06:59 +030012847 state->base.src.x1 >> 16,
12848 state->base.src.y1 >> 16,
12849 drm_rect_width(&state->base.src) >> 16,
12850 drm_rect_height(&state->base.src) >> 16,
12851 state->base.dst.x1, state->base.dst.y1,
12852 drm_rect_width(&state->base.dst),
12853 drm_rect_height(&state->base.dst));
Eric Engestrom90844f02016-08-15 01:02:38 +010012854
12855 kfree(format_name);
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012856 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020012857}
12858
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030012859static bool check_digital_port_conflicts(struct drm_atomic_state *state)
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012860{
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030012861 struct drm_device *dev = state->dev;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012862 struct drm_connector *connector;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012863 unsigned int used_ports = 0;
Ville Syrjälä477321e2016-07-28 17:50:40 +030012864 unsigned int used_mst_ports = 0;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012865
12866 /*
12867 * Walk the connector list instead of the encoder
12868 * list to detect the problem on ddi platforms
12869 * where there's just one encoder per digital port.
12870 */
Ville Syrjälä0bff4852015-12-10 18:22:31 +020012871 drm_for_each_connector(connector, dev) {
12872 struct drm_connector_state *connector_state;
12873 struct intel_encoder *encoder;
12874
12875 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12876 if (!connector_state)
12877 connector_state = connector->state;
12878
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030012879 if (!connector_state->best_encoder)
12880 continue;
12881
12882 encoder = to_intel_encoder(connector_state->best_encoder);
12883
12884 WARN_ON(!connector_state->crtc);
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012885
12886 switch (encoder->type) {
12887 unsigned int port_mask;
12888 case INTEL_OUTPUT_UNKNOWN:
12889 if (WARN_ON(!HAS_DDI(dev)))
12890 break;
Ville Syrjäläcca05022016-06-22 21:57:06 +030012891 case INTEL_OUTPUT_DP:
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012892 case INTEL_OUTPUT_HDMI:
12893 case INTEL_OUTPUT_EDP:
12894 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12895
12896 /* the same port mustn't appear more than once */
12897 if (used_ports & port_mask)
12898 return false;
12899
12900 used_ports |= port_mask;
Ville Syrjälä477321e2016-07-28 17:50:40 +030012901 break;
12902 case INTEL_OUTPUT_DP_MST:
12903 used_mst_ports |=
12904 1 << enc_to_mst(&encoder->base)->primary->port;
12905 break;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012906 default:
12907 break;
12908 }
12909 }
12910
Ville Syrjälä477321e2016-07-28 17:50:40 +030012911 /* can't mix MST and SST/HDMI on the same port */
12912 if (used_ports & used_mst_ports)
12913 return false;
12914
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012915 return true;
12916}
12917
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012918static void
12919clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12920{
12921 struct drm_crtc_state tmp_state;
Chandra Konduru663a3642015-04-07 15:28:41 -070012922 struct intel_crtc_scaler_state scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012923 struct intel_dpll_hw_state dpll_hw_state;
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020012924 struct intel_shared_dpll *shared_dpll;
Maarten Lankhorstc4e2d042015-08-05 12:36:59 +020012925 bool force_thru;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012926
Ander Conselvan de Oliveira7546a382015-05-20 09:03:27 +030012927 /* FIXME: before the switch to atomic started, a new pipe_config was
12928 * kzalloc'd. Code that depends on any field being zero should be
12929 * fixed, so that the crtc_state can be safely duplicated. For now,
12930 * only fields that are know to not cause problems are preserved. */
12931
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012932 tmp_state = crtc_state->base;
Chandra Konduru663a3642015-04-07 15:28:41 -070012933 scaler_state = crtc_state->scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012934 shared_dpll = crtc_state->shared_dpll;
12935 dpll_hw_state = crtc_state->dpll_hw_state;
Maarten Lankhorstc4e2d042015-08-05 12:36:59 +020012936 force_thru = crtc_state->pch_pfit.force_thru;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012937
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012938 memset(crtc_state, 0, sizeof *crtc_state);
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012939
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012940 crtc_state->base = tmp_state;
Chandra Konduru663a3642015-04-07 15:28:41 -070012941 crtc_state->scaler_state = scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012942 crtc_state->shared_dpll = shared_dpll;
12943 crtc_state->dpll_hw_state = dpll_hw_state;
Maarten Lankhorstc4e2d042015-08-05 12:36:59 +020012944 crtc_state->pch_pfit.force_thru = force_thru;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012945}
12946
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012947static int
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010012948intel_modeset_pipe_config(struct drm_crtc *crtc,
Maarten Lankhorstb3592832015-06-15 12:33:38 +020012949 struct intel_crtc_state *pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020012950{
Maarten Lankhorstb3592832015-06-15 12:33:38 +020012951 struct drm_atomic_state *state = pipe_config->base.state;
Daniel Vetter7758a112012-07-08 19:40:39 +020012952 struct intel_encoder *encoder;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012953 struct drm_connector *connector;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020012954 struct drm_connector_state *connector_state;
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012955 int base_bpp, ret = -EINVAL;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020012956 int i;
Daniel Vettere29c22c2013-02-21 00:00:16 +010012957 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020012958
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012959 clear_intel_crtc_state(pipe_config);
Daniel Vetter7758a112012-07-08 19:40:39 +020012960
Daniel Vettere143a212013-07-04 12:01:15 +020012961 pipe_config->cpu_transcoder =
12962 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010012963
Imre Deak2960bc92013-07-30 13:36:32 +030012964 /*
12965 * Sanitize sync polarity flags based on requested ones. If neither
12966 * positive or negative polarity is requested, treat this as meaning
12967 * negative polarity.
12968 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012969 if (!(pipe_config->base.adjusted_mode.flags &
Imre Deak2960bc92013-07-30 13:36:32 +030012970 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012971 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
Imre Deak2960bc92013-07-30 13:36:32 +030012972
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012973 if (!(pipe_config->base.adjusted_mode.flags &
Imre Deak2960bc92013-07-30 13:36:32 +030012974 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012975 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
Imre Deak2960bc92013-07-30 13:36:32 +030012976
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012977 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12978 pipe_config);
12979 if (base_bpp < 0)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012980 goto fail;
12981
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030012982 /*
12983 * Determine the real pipe dimensions. Note that stereo modes can
12984 * increase the actual pipe size due to the frame doubling and
12985 * insertion of additional space for blanks between the frame. This
12986 * is stored in the crtc timings. We use the requested mode to do this
12987 * computation to clearly distinguish it from the adjusted mode, which
12988 * can be changed by the connectors in the below retry loop.
12989 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012990 drm_crtc_get_hv_timing(&pipe_config->base.mode,
Gustavo Padovanecb7e162014-12-01 15:40:09 -080012991 &pipe_config->pipe_src_w,
12992 &pipe_config->pipe_src_h);
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030012993
Ville Syrjälä253c84c2016-06-22 21:57:01 +030012994 for_each_connector_in_state(state, connector, connector_state, i) {
12995 if (connector_state->crtc != crtc)
12996 continue;
12997
12998 encoder = to_intel_encoder(connector_state->best_encoder);
12999
Ville Syrjäläe25148d2016-06-22 21:57:09 +030013000 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13001 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13002 goto fail;
13003 }
13004
Ville Syrjälä253c84c2016-06-22 21:57:01 +030013005 /*
13006 * Determine output_types before calling the .compute_config()
13007 * hooks so that the hooks can use this information safely.
13008 */
13009 pipe_config->output_types |= 1 << encoder->type;
13010 }
13011
Daniel Vettere29c22c2013-02-21 00:00:16 +010013012encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020013013 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020013014 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020013015 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020013016
Daniel Vetter135c81b2013-07-21 21:37:09 +020013017 /* Fill in default crtc timings, allow encoders to overwrite them. */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013018 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13019 CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020013020
Daniel Vetter7758a112012-07-08 19:40:39 +020013021 /* Pass our mode to the connectors and the CRTC to give them a chance to
13022 * adjust it according to limitations or connector properties, and also
13023 * a chance to reject the mode entirely.
13024 */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030013025 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020013026 if (connector_state->crtc != crtc)
13027 continue;
13028
13029 encoder = to_intel_encoder(connector_state->best_encoder);
13030
Maarten Lankhorst0a478c22016-08-09 17:04:05 +020013031 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
Daniel Vetterefea6e82013-07-21 21:36:59 +020013032 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020013033 goto fail;
13034 }
13035 }
13036
Daniel Vetterff9a6752013-06-01 17:16:21 +020013037 /* Set default port clock if not overwritten by the encoder. Needs to be
13038 * done afterwards in case the encoder adjusts the mode. */
13039 if (!pipe_config->port_clock)
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013040 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
Damien Lespiau241bfc32013-09-25 16:45:37 +010013041 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020013042
Daniel Vettera43f6e02013-06-07 23:10:32 +020013043 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010013044 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020013045 DRM_DEBUG_KMS("CRTC fixup failed\n");
13046 goto fail;
13047 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010013048
13049 if (ret == RETRY) {
13050 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13051 ret = -EINVAL;
13052 goto fail;
13053 }
13054
13055 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13056 retry = false;
13057 goto encoder_retry;
13058 }
13059
Daniel Vettere8fa4272015-08-12 11:43:34 +020013060 /* Dithering seems to not pass-through bits correctly when it should, so
13061 * only enable it on 6bpc panels. */
13062 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
Daniel Vetter62f0ace2015-08-26 18:57:26 +020013063 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
Daniel Vetterd328c9d2015-04-10 16:22:37 +020013064 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010013065
Daniel Vetter7758a112012-07-08 19:40:39 +020013066fail:
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030013067 return ret;
Daniel Vetter7758a112012-07-08 19:40:39 +020013068}
13069
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013070static void
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020013071intel_modeset_update_crtc_state(struct drm_atomic_state *state)
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013072{
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013073 struct drm_crtc *crtc;
13074 struct drm_crtc_state *crtc_state;
Maarten Lankhorst8a75d152015-07-13 16:30:14 +020013075 int i;
Daniel Vetterea9d7582012-07-10 10:42:52 +020013076
Ville Syrjälä76688512014-01-10 11:28:06 +020013077 /* Double check state. */
Maarten Lankhorst8a75d152015-07-13 16:30:14 +020013078 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorst3cb480b2015-06-01 12:49:49 +020013079 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
Maarten Lankhorstfc467a222015-06-01 12:50:07 +020013080
13081 /* Update hwmode for vblank functions */
13082 if (crtc->state->active)
13083 crtc->hwmode = crtc->state->adjusted_mode;
13084 else
13085 crtc->hwmode.crtc_clock = 0;
Maarten Lankhorst61067a52015-09-23 16:29:36 +020013086
13087 /*
13088 * Update legacy state to satisfy fbc code. This can
13089 * be removed when fbc uses the atomic state.
13090 */
13091 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13092 struct drm_plane_state *plane_state = crtc->primary->state;
13093
13094 crtc->primary->fb = plane_state->fb;
13095 crtc->x = plane_state->src_x >> 16;
13096 crtc->y = plane_state->src_y >> 16;
13097 }
Daniel Vetterea9d7582012-07-10 10:42:52 +020013098 }
Daniel Vetterea9d7582012-07-10 10:42:52 +020013099}
13100
Ville Syrjälä3bd26262013-09-06 23:29:02 +030013101static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030013102{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030013103 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030013104
13105 if (clock1 == clock2)
13106 return true;
13107
13108 if (!clock1 || !clock2)
13109 return false;
13110
13111 diff = abs(clock1 - clock2);
13112
13113 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13114 return true;
13115
13116 return false;
13117}
13118
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013119static bool
13120intel_compare_m_n(unsigned int m, unsigned int n,
13121 unsigned int m2, unsigned int n2,
13122 bool exact)
13123{
13124 if (m == m2 && n == n2)
13125 return true;
13126
13127 if (exact || !m || !n || !m2 || !n2)
13128 return false;
13129
13130 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13131
Maarten Lankhorst31d10b52016-01-06 13:54:43 +010013132 if (n > n2) {
13133 while (n > n2) {
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013134 m2 <<= 1;
13135 n2 <<= 1;
13136 }
Maarten Lankhorst31d10b52016-01-06 13:54:43 +010013137 } else if (n < n2) {
13138 while (n < n2) {
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013139 m <<= 1;
13140 n <<= 1;
13141 }
13142 }
13143
Maarten Lankhorst31d10b52016-01-06 13:54:43 +010013144 if (n != n2)
13145 return false;
13146
13147 return intel_fuzzy_clock_check(m, m2);
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013148}
13149
13150static bool
13151intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13152 struct intel_link_m_n *m2_n2,
13153 bool adjust)
13154{
13155 if (m_n->tu == m2_n2->tu &&
13156 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13157 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13158 intel_compare_m_n(m_n->link_m, m_n->link_n,
13159 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13160 if (adjust)
13161 *m2_n2 = *m_n;
13162
13163 return true;
13164 }
13165
13166 return false;
13167}
13168
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013169static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020013170intel_pipe_config_compare(struct drm_device *dev,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020013171 struct intel_crtc_state *current_config,
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013172 struct intel_crtc_state *pipe_config,
13173 bool adjust)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013174{
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013175 bool ret = true;
13176
13177#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13178 do { \
13179 if (!adjust) \
13180 DRM_ERROR(fmt, ##__VA_ARGS__); \
13181 else \
13182 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13183 } while (0)
13184
Daniel Vetter66e985c2013-06-05 13:34:20 +020013185#define PIPE_CONF_CHECK_X(name) \
13186 if (current_config->name != pipe_config->name) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013187 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Daniel Vetter66e985c2013-06-05 13:34:20 +020013188 "(expected 0x%08x, found 0x%08x)\n", \
13189 current_config->name, \
13190 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013191 ret = false; \
Daniel Vetter66e985c2013-06-05 13:34:20 +020013192 }
13193
Daniel Vetter08a24032013-04-19 11:25:34 +020013194#define PIPE_CONF_CHECK_I(name) \
13195 if (current_config->name != pipe_config->name) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013196 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Daniel Vetter08a24032013-04-19 11:25:34 +020013197 "(expected %i, found %i)\n", \
13198 current_config->name, \
13199 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013200 ret = false; \
13201 }
13202
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013203#define PIPE_CONF_CHECK_P(name) \
13204 if (current_config->name != pipe_config->name) { \
13205 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13206 "(expected %p, found %p)\n", \
13207 current_config->name, \
13208 pipe_config->name); \
13209 ret = false; \
13210 }
13211
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013212#define PIPE_CONF_CHECK_M_N(name) \
13213 if (!intel_compare_link_m_n(&current_config->name, \
13214 &pipe_config->name,\
13215 adjust)) { \
13216 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13217 "(expected tu %i gmch %i/%i link %i/%i, " \
13218 "found tu %i, gmch %i/%i link %i/%i)\n", \
13219 current_config->name.tu, \
13220 current_config->name.gmch_m, \
13221 current_config->name.gmch_n, \
13222 current_config->name.link_m, \
13223 current_config->name.link_n, \
13224 pipe_config->name.tu, \
13225 pipe_config->name.gmch_m, \
13226 pipe_config->name.gmch_n, \
13227 pipe_config->name.link_m, \
13228 pipe_config->name.link_n); \
13229 ret = false; \
13230 }
13231
Daniel Vetter55c561a2016-03-30 11:34:36 +020013232/* This is required for BDW+ where there is only one set of registers for
13233 * switching between high and low RR.
13234 * This macro can be used whenever a comparison has to be made between one
13235 * hw state and multiple sw state variables.
13236 */
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013237#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13238 if (!intel_compare_link_m_n(&current_config->name, \
13239 &pipe_config->name, adjust) && \
13240 !intel_compare_link_m_n(&current_config->alt_name, \
13241 &pipe_config->name, adjust)) { \
13242 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13243 "(expected tu %i gmch %i/%i link %i/%i, " \
13244 "or tu %i gmch %i/%i link %i/%i, " \
13245 "found tu %i, gmch %i/%i link %i/%i)\n", \
13246 current_config->name.tu, \
13247 current_config->name.gmch_m, \
13248 current_config->name.gmch_n, \
13249 current_config->name.link_m, \
13250 current_config->name.link_n, \
13251 current_config->alt_name.tu, \
13252 current_config->alt_name.gmch_m, \
13253 current_config->alt_name.gmch_n, \
13254 current_config->alt_name.link_m, \
13255 current_config->alt_name.link_n, \
13256 pipe_config->name.tu, \
13257 pipe_config->name.gmch_m, \
13258 pipe_config->name.gmch_n, \
13259 pipe_config->name.link_m, \
13260 pipe_config->name.link_n); \
13261 ret = false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010013262 }
13263
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013264#define PIPE_CONF_CHECK_FLAGS(name, mask) \
13265 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013266 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013267 "(expected %i, found %i)\n", \
13268 current_config->name & (mask), \
13269 pipe_config->name & (mask)); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013270 ret = false; \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013271 }
13272
Ville Syrjälä5e550652013-09-06 23:29:07 +030013273#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13274 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013275 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Ville Syrjälä5e550652013-09-06 23:29:07 +030013276 "(expected %i, found %i)\n", \
13277 current_config->name, \
13278 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013279 ret = false; \
Ville Syrjälä5e550652013-09-06 23:29:07 +030013280 }
13281
Daniel Vetterbb760062013-06-06 14:55:52 +020013282#define PIPE_CONF_QUIRK(quirk) \
13283 ((current_config->quirks | pipe_config->quirks) & (quirk))
13284
Daniel Vettereccb1402013-05-22 00:50:22 +020013285 PIPE_CONF_CHECK_I(cpu_transcoder);
13286
Daniel Vetter08a24032013-04-19 11:25:34 +020013287 PIPE_CONF_CHECK_I(has_pch_encoder);
13288 PIPE_CONF_CHECK_I(fdi_lanes);
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013289 PIPE_CONF_CHECK_M_N(fdi_m_n);
Daniel Vetter08a24032013-04-19 11:25:34 +020013290
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030013291 PIPE_CONF_CHECK_I(lane_count);
Imre Deak95a7a2a2016-06-13 16:44:35 +030013292 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070013293
13294 if (INTEL_INFO(dev)->gen < 8) {
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013295 PIPE_CONF_CHECK_M_N(dp_m_n);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070013296
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013297 if (current_config->has_drrs)
13298 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13299 } else
13300 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030013301
Ville Syrjälä253c84c2016-06-22 21:57:01 +030013302 PIPE_CONF_CHECK_X(output_types);
Jani Nikulaa65347b2015-11-27 12:21:46 +020013303
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013304 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13305 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13306 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013310
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13312 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13313 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13314 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13315 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13316 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013317
Daniel Vetterc93f54c2013-06-27 19:47:19 +020013318 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b52014-04-24 23:54:47 +020013319 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020013320 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
Wayne Boyer666a4532015-12-09 12:29:35 -080013321 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020013322 PIPE_CONF_CHECK_I(limited_color_range);
Jesse Barnese43823e2014-11-05 14:26:08 -080013323 PIPE_CONF_CHECK_I(has_infoframe);
Daniel Vetter6c49f242013-06-06 12:45:25 +020013324
Daniel Vetter9ed109a2014-04-24 23:54:52 +020013325 PIPE_CONF_CHECK_I(has_audio);
13326
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013327 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013328 DRM_MODE_FLAG_INTERLACE);
13329
Daniel Vetterbb760062013-06-06 14:55:52 +020013330 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013331 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020013332 DRM_MODE_FLAG_PHSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013333 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020013334 DRM_MODE_FLAG_NHSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013335 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020013336 DRM_MODE_FLAG_PVSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013337 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020013338 DRM_MODE_FLAG_NVSYNC);
13339 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013340
Ville Syrjälä333b8ca2015-09-03 21:50:16 +030013341 PIPE_CONF_CHECK_X(gmch_pfit.control);
Daniel Vettere2ff2d42015-07-15 14:15:50 +020013342 /* pfit ratios are autocomputed by the hw on gen4+ */
13343 if (INTEL_INFO(dev)->gen < 4)
Ville Syrjälä7f7d8dd2016-03-15 16:40:07 +020013344 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
Ville Syrjälä333b8ca2015-09-03 21:50:16 +030013345 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
Daniel Vetter99535992014-04-13 12:00:33 +020013346
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013347 if (!adjust) {
13348 PIPE_CONF_CHECK_I(pipe_src_w);
13349 PIPE_CONF_CHECK_I(pipe_src_h);
13350
13351 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13352 if (current_config->pch_pfit.enabled) {
13353 PIPE_CONF_CHECK_X(pch_pfit.pos);
13354 PIPE_CONF_CHECK_X(pch_pfit.size);
13355 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020013356
Maarten Lankhorst7aefe2b2015-09-14 11:30:10 +020013357 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13358 }
Chandra Kondurua1b22782015-04-07 15:28:45 -070013359
Jesse Barnese59150d2014-01-07 13:30:45 -080013360 /* BDW+ don't expose a synchronous way to read the state */
13361 if (IS_HASWELL(dev))
13362 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030013363
Ville Syrjälä282740f2013-09-04 18:30:03 +030013364 PIPE_CONF_CHECK_I(double_wide);
13365
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013366 PIPE_CONF_CHECK_P(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020013367 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020013368 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020013369 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13370 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030013371 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Maarten Lankhorst00490c22015-11-16 14:42:12 +010013372 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
Damien Lespiau3f4cd192014-11-13 14:55:21 +000013373 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13374 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13375 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020013376
Ville Syrjälä47eacba2016-04-12 22:14:35 +030013377 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13378 PIPE_CONF_CHECK_X(dsi_pll.div);
13379
Ville Syrjälä42571ae2013-09-06 23:29:00 +030013380 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13381 PIPE_CONF_CHECK_I(pipe_bpp);
13382
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013383 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
Jesse Barnesa9a7e982014-01-20 14:18:04 -080013384 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030013385
Daniel Vetter66e985c2013-06-05 13:34:20 +020013386#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020013387#undef PIPE_CONF_CHECK_I
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013388#undef PIPE_CONF_CHECK_P
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020013389#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030013390#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020013391#undef PIPE_CONF_QUIRK
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013392#undef INTEL_ERR_OR_DBG_KMS
Daniel Vetter627eb5a2013-04-29 19:33:42 +020013393
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013394 return ret;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013395}
13396
Ville Syrjäläe3b247d2016-02-17 21:41:09 +020013397static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13398 const struct intel_crtc_state *pipe_config)
13399{
13400 if (pipe_config->has_pch_encoder) {
Ville Syrjälä21a727b2016-02-17 21:41:10 +020013401 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
Ville Syrjäläe3b247d2016-02-17 21:41:09 +020013402 &pipe_config->fdi_m_n);
13403 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13404
13405 /*
13406 * FDI already provided one idea for the dotclock.
13407 * Yell if the encoder disagrees.
13408 */
13409 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13410 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13411 fdi_dotclock, dotclock);
13412 }
13413}
13414
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013415static void verify_wm_state(struct drm_crtc *crtc,
13416 struct drm_crtc_state *new_state)
Damien Lespiau08db6652014-11-04 17:06:52 +000013417{
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013418 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010013419 struct drm_i915_private *dev_priv = to_i915(dev);
Damien Lespiau08db6652014-11-04 17:06:52 +000013420 struct skl_ddb_allocation hw_ddb, *sw_ddb;
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013421 struct skl_ddb_entry *hw_entry, *sw_entry;
13422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13423 const enum pipe pipe = intel_crtc->pipe;
Damien Lespiau08db6652014-11-04 17:06:52 +000013424 int plane;
13425
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013426 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
Damien Lespiau08db6652014-11-04 17:06:52 +000013427 return;
13428
13429 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13430 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13431
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013432 /* planes */
13433 for_each_plane(dev_priv, pipe, plane) {
13434 hw_entry = &hw_ddb.plane[pipe][plane];
13435 sw_entry = &sw_ddb->plane[pipe][plane];
Damien Lespiau08db6652014-11-04 17:06:52 +000013436
13437 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13438 continue;
13439
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013440 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13441 "(expected (%u,%u), found (%u,%u))\n",
13442 pipe_name(pipe), plane + 1,
13443 sw_entry->start, sw_entry->end,
13444 hw_entry->start, hw_entry->end);
13445 }
13446
Lyude27082492016-08-24 07:48:10 +020013447 /*
13448 * cursor
13449 * If the cursor plane isn't active, we may not have updated it's ddb
13450 * allocation. In that case since the ddb allocation will be updated
13451 * once the plane becomes visible, we can skip this check
13452 */
13453 if (intel_crtc->cursor_addr) {
13454 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13455 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013456
Lyude27082492016-08-24 07:48:10 +020013457 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13458 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13459 "(expected (%u,%u), found (%u,%u))\n",
13460 pipe_name(pipe),
13461 sw_entry->start, sw_entry->end,
13462 hw_entry->start, hw_entry->end);
13463 }
Damien Lespiau08db6652014-11-04 17:06:52 +000013464 }
13465}
13466
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013467static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013468verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013469{
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020013470 struct drm_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013471
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013472 drm_for_each_connector(connector, dev) {
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020013473 struct drm_encoder *encoder = connector->encoder;
13474 struct drm_connector_state *state = connector->state;
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020013475
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013476 if (state->crtc != crtc)
13477 continue;
13478
Daniel Vetter5a21b662016-05-24 17:13:53 +020013479 intel_connector_verify_state(to_intel_connector(connector));
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013480
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020013481 I915_STATE_WARN(state->best_encoder != encoder,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020013482 "connector's atomic encoder doesn't match legacy encoder\n");
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013483 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013484}
13485
13486static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013487verify_encoder_state(struct drm_device *dev)
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013488{
13489 struct intel_encoder *encoder;
13490 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013491
Damien Lespiaub2784e12014-08-05 11:29:37 +010013492 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013493 bool enabled = false;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013494 enum pipe pipe;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013495
13496 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13497 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030013498 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013499
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020013500 for_each_intel_connector(dev, connector) {
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013501 if (connector->base.state->best_encoder != &encoder->base)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013502 continue;
13503 enabled = true;
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020013504
13505 I915_STATE_WARN(connector->base.state->crtc !=
13506 encoder->base.crtc,
13507 "connector's crtc doesn't match encoder crtc\n");
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013508 }
Dave Airlie0e32b392014-05-02 14:02:48 +100013509
Rob Clarke2c719b2014-12-15 13:56:32 -050013510 I915_STATE_WARN(!!encoder->base.crtc != enabled,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013511 "encoder's enabled state mismatch "
13512 "(expected %i, found %i)\n",
13513 !!encoder->base.crtc, enabled);
Maarten Lankhorst7c60d192015-08-05 12:37:04 +020013514
13515 if (!encoder->base.crtc) {
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013516 bool active;
13517
13518 active = encoder->get_hw_state(encoder, &pipe);
Maarten Lankhorst7c60d192015-08-05 12:37:04 +020013519 I915_STATE_WARN(active,
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013520 "encoder detached but still enabled on pipe %c.\n",
13521 pipe_name(pipe));
Maarten Lankhorst7c60d192015-08-05 12:37:04 +020013522 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013523 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013524}
13525
13526static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013527verify_crtc_state(struct drm_crtc *crtc,
13528 struct drm_crtc_state *old_crtc_state,
13529 struct drm_crtc_state *new_crtc_state)
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013530{
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013531 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010013532 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013533 struct intel_encoder *encoder;
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13535 struct intel_crtc_state *pipe_config, *sw_config;
13536 struct drm_atomic_state *old_state;
13537 bool active;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013538
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013539 old_state = old_crtc_state->state;
Daniel Vetterec2dc6a2016-05-09 16:34:09 +020013540 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013541 pipe_config = to_intel_crtc_state(old_crtc_state);
13542 memset(pipe_config, 0, sizeof(*pipe_config));
13543 pipe_config->base.crtc = crtc;
13544 pipe_config->base.state = old_state;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013545
Ville Syrjälä78108b72016-05-27 20:59:19 +030013546 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013547
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013548 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013549
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013550 /* hw state is inconsistent with the pipe quirk */
13551 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13552 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13553 active = new_crtc_state->active;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013554
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013555 I915_STATE_WARN(new_crtc_state->active != active,
13556 "crtc active state doesn't match with hw state "
13557 "(expected %i, found %i)\n", new_crtc_state->active, active);
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013558
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013559 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13560 "transitional active state does not match atomic hw state "
13561 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013562
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013563 for_each_encoder_on_crtc(dev, crtc, encoder) {
13564 enum pipe pipe;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013565
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013566 active = encoder->get_hw_state(encoder, &pipe);
13567 I915_STATE_WARN(active != new_crtc_state->active,
13568 "[ENCODER:%i] active %i with crtc active %i\n",
13569 encoder->base.base.id, active, new_crtc_state->active);
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013570
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013571 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13572 "Encoder connected to wrong pipe %c\n",
13573 pipe_name(pipe));
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013574
Ville Syrjälä253c84c2016-06-22 21:57:01 +030013575 if (active) {
13576 pipe_config->output_types |= 1 << encoder->type;
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013577 encoder->get_config(encoder, pipe_config);
Ville Syrjälä253c84c2016-06-22 21:57:01 +030013578 }
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013579 }
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013580
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013581 if (!new_crtc_state->active)
13582 return;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013583
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013584 intel_pipe_config_sanity_check(dev_priv, pipe_config);
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013585
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013586 sw_config = to_intel_crtc_state(crtc->state);
13587 if (!intel_pipe_config_compare(dev, sw_config,
13588 pipe_config, false)) {
13589 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13590 intel_dump_pipe_config(intel_crtc, pipe_config,
13591 "[hw state]");
13592 intel_dump_pipe_config(intel_crtc, sw_config,
13593 "[sw state]");
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013594 }
13595}
13596
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013597static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013598verify_single_dpll_state(struct drm_i915_private *dev_priv,
13599 struct intel_shared_dpll *pll,
13600 struct drm_crtc *crtc,
13601 struct drm_crtc_state *new_state)
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013602{
13603 struct intel_dpll_hw_state dpll_hw_state;
13604 unsigned crtc_mask;
13605 bool active;
13606
13607 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13608
13609 DRM_DEBUG_KMS("%s\n", pll->name);
13610
13611 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13612
13613 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13614 I915_STATE_WARN(!pll->on && pll->active_mask,
13615 "pll in active use but not on in sw tracking\n");
13616 I915_STATE_WARN(pll->on && !pll->active_mask,
13617 "pll is on but not used by any active crtc\n");
13618 I915_STATE_WARN(pll->on != active,
13619 "pll on state mismatch (expected %i, found %i)\n",
13620 pll->on, active);
13621 }
13622
13623 if (!crtc) {
13624 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13625 "more active pll users than references: %x vs %x\n",
13626 pll->active_mask, pll->config.crtc_mask);
13627
13628 return;
13629 }
13630
13631 crtc_mask = 1 << drm_crtc_index(crtc);
13632
13633 if (new_state->active)
13634 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13635 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13636 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13637 else
13638 I915_STATE_WARN(pll->active_mask & crtc_mask,
13639 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13640 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13641
13642 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13643 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13644 crtc_mask, pll->config.crtc_mask);
13645
13646 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13647 &dpll_hw_state,
13648 sizeof(dpll_hw_state)),
13649 "pll hw state mismatch\n");
13650}
13651
13652static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013653verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13654 struct drm_crtc_state *old_crtc_state,
13655 struct drm_crtc_state *new_crtc_state)
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013656{
Chris Wilsonfac5e232016-07-04 11:34:36 +010013657 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013658 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13659 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13660
13661 if (new_state->shared_dpll)
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013662 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013663
13664 if (old_state->shared_dpll &&
13665 old_state->shared_dpll != new_state->shared_dpll) {
13666 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13667 struct intel_shared_dpll *pll = old_state->shared_dpll;
13668
13669 I915_STATE_WARN(pll->active_mask & crtc_mask,
13670 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13671 pipe_name(drm_crtc_index(crtc)));
13672 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13673 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13674 pipe_name(drm_crtc_index(crtc)));
13675 }
13676}
13677
13678static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013679intel_modeset_verify_crtc(struct drm_crtc *crtc,
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013680 struct drm_crtc_state *old_state,
13681 struct drm_crtc_state *new_state)
13682{
Daniel Vetter5a21b662016-05-24 17:13:53 +020013683 if (!needs_modeset(new_state) &&
13684 !to_intel_crtc_state(new_state)->update_pipe)
13685 return;
13686
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013687 verify_wm_state(crtc, new_state);
Daniel Vetter5a21b662016-05-24 17:13:53 +020013688 verify_connector_state(crtc->dev, crtc);
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013689 verify_crtc_state(crtc, old_state, new_state);
13690 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013691}
13692
13693static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013694verify_disabled_dpll_state(struct drm_device *dev)
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013695{
Chris Wilsonfac5e232016-07-04 11:34:36 +010013696 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013697 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020013698
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013699 for (i = 0; i < dev_priv->num_shared_dpll; i++)
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013700 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013701}
Daniel Vetter53589012013-06-05 13:34:16 +020013702
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013703static void
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013704intel_modeset_verify_disabled(struct drm_device *dev)
Maarten Lankhorste7c84542016-03-23 14:58:06 +010013705{
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020013706 verify_encoder_state(dev);
13707 verify_connector_state(dev, NULL);
13708 verify_disabled_dpll_state(dev);
Daniel Vetter25c5b262012-07-08 22:08:04 +020013709}
13710
Ville Syrjälä80715b22014-05-15 20:23:23 +030013711static void update_scanline_offset(struct intel_crtc *crtc)
13712{
13713 struct drm_device *dev = crtc->base.dev;
13714
13715 /*
13716 * The scanline counter increments at the leading edge of hsync.
13717 *
13718 * On most platforms it starts counting from vtotal-1 on the
13719 * first active line. That means the scanline counter value is
13720 * always one less than what we would expect. Ie. just after
13721 * start of vblank, which also occurs at start of hsync (on the
13722 * last active line), the scanline counter will read vblank_start-1.
13723 *
13724 * On gen2 the scanline counter starts counting from 1 instead
13725 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13726 * to keep the value positive), instead of adding one.
13727 *
13728 * On HSW+ the behaviour of the scanline counter depends on the output
13729 * type. For DP ports it behaves like most other platforms, but on HDMI
13730 * there's an extra 1 line difference. So we need to add two instead of
13731 * one to the value.
13732 */
13733 if (IS_GEN2(dev)) {
Ville Syrjälä124abe02015-09-08 13:40:45 +030013734 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Ville Syrjälä80715b22014-05-15 20:23:23 +030013735 int vtotal;
13736
Ville Syrjälä124abe02015-09-08 13:40:45 +030013737 vtotal = adjusted_mode->crtc_vtotal;
13738 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Ville Syrjälä80715b22014-05-15 20:23:23 +030013739 vtotal /= 2;
13740
13741 crtc->scanline_offset = vtotal - 1;
13742 } else if (HAS_DDI(dev) &&
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +030013743 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
Ville Syrjälä80715b22014-05-15 20:23:23 +030013744 crtc->scanline_offset = 2;
13745 } else
13746 crtc->scanline_offset = 1;
13747}
13748
Maarten Lankhorstad421372015-06-15 12:33:42 +020013749static void intel_modeset_clear_plls(struct drm_atomic_state *state)
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013750{
Ander Conselvan de Oliveira225da592015-04-02 14:47:57 +030013751 struct drm_device *dev = state->dev;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013752 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorstad421372015-06-15 12:33:42 +020013753 struct intel_shared_dpll_config *shared_dpll = NULL;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013754 struct drm_crtc *crtc;
13755 struct drm_crtc_state *crtc_state;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013756 int i;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013757
13758 if (!dev_priv->display.crtc_compute_clock)
Maarten Lankhorstad421372015-06-15 12:33:42 +020013759 return;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013760
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013761 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorstfb1a38a2016-02-09 13:02:17 +010013762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013763 struct intel_shared_dpll *old_dpll =
13764 to_intel_crtc_state(crtc->state)->shared_dpll;
Maarten Lankhorstad421372015-06-15 12:33:42 +020013765
Maarten Lankhorstfb1a38a2016-02-09 13:02:17 +010013766 if (!needs_modeset(crtc_state))
Ander Conselvan de Oliveira225da592015-04-02 14:47:57 +030013767 continue;
13768
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013769 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
Maarten Lankhorstfb1a38a2016-02-09 13:02:17 +010013770
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013771 if (!old_dpll)
Maarten Lankhorstfb1a38a2016-02-09 13:02:17 +010013772 continue;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013773
Maarten Lankhorstad421372015-06-15 12:33:42 +020013774 if (!shared_dpll)
13775 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13776
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +020013777 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013778 }
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013779}
13780
Maarten Lankhorst99d736a2015-06-01 12:50:09 +020013781/*
13782 * This implements the workaround described in the "notes" section of the mode
13783 * set sequence documentation. When going from no pipes or single pipe to
13784 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13785 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13786 */
13787static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13788{
13789 struct drm_crtc_state *crtc_state;
13790 struct intel_crtc *intel_crtc;
13791 struct drm_crtc *crtc;
13792 struct intel_crtc_state *first_crtc_state = NULL;
13793 struct intel_crtc_state *other_crtc_state = NULL;
13794 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13795 int i;
13796
13797 /* look at all crtc's that are going to be enabled in during modeset */
13798 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13799 intel_crtc = to_intel_crtc(crtc);
13800
13801 if (!crtc_state->active || !needs_modeset(crtc_state))
13802 continue;
13803
13804 if (first_crtc_state) {
13805 other_crtc_state = to_intel_crtc_state(crtc_state);
13806 break;
13807 } else {
13808 first_crtc_state = to_intel_crtc_state(crtc_state);
13809 first_pipe = intel_crtc->pipe;
13810 }
13811 }
13812
13813 /* No workaround needed? */
13814 if (!first_crtc_state)
13815 return 0;
13816
13817 /* w/a possibly needed, check how many crtc's are already enabled. */
13818 for_each_intel_crtc(state->dev, intel_crtc) {
13819 struct intel_crtc_state *pipe_config;
13820
13821 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13822 if (IS_ERR(pipe_config))
13823 return PTR_ERR(pipe_config);
13824
13825 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13826
13827 if (!pipe_config->base.active ||
13828 needs_modeset(&pipe_config->base))
13829 continue;
13830
13831 /* 2 or more enabled crtcs means no need for w/a */
13832 if (enabled_pipe != INVALID_PIPE)
13833 return 0;
13834
13835 enabled_pipe = intel_crtc->pipe;
13836 }
13837
13838 if (enabled_pipe != INVALID_PIPE)
13839 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13840 else if (other_crtc_state)
13841 other_crtc_state->hsw_workaround_pipe = first_pipe;
13842
13843 return 0;
13844}
13845
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013846static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13847{
13848 struct drm_crtc *crtc;
13849 struct drm_crtc_state *crtc_state;
13850 int ret = 0;
13851
13852 /* add all active pipes to the state */
13853 for_each_crtc(state->dev, crtc) {
13854 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13855 if (IS_ERR(crtc_state))
13856 return PTR_ERR(crtc_state);
13857
13858 if (!crtc_state->active || needs_modeset(crtc_state))
13859 continue;
13860
13861 crtc_state->mode_changed = true;
13862
13863 ret = drm_atomic_add_affected_connectors(state, crtc);
13864 if (ret)
13865 break;
13866
13867 ret = drm_atomic_add_affected_planes(state, crtc);
13868 if (ret)
13869 break;
13870 }
13871
13872 return ret;
13873}
13874
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013875static int intel_modeset_checks(struct drm_atomic_state *state)
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013876{
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013877 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Chris Wilsonfac5e232016-07-04 11:34:36 +010013878 struct drm_i915_private *dev_priv = to_i915(state->dev);
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013879 struct drm_crtc *crtc;
13880 struct drm_crtc_state *crtc_state;
13881 int ret = 0, i;
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013882
Maarten Lankhorstb3592832015-06-15 12:33:38 +020013883 if (!check_digital_port_conflicts(state)) {
13884 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13885 return -EINVAL;
13886 }
13887
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013888 intel_state->modeset = true;
13889 intel_state->active_crtcs = dev_priv->active_crtcs;
13890
13891 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13892 if (crtc_state->active)
13893 intel_state->active_crtcs |= 1 << i;
13894 else
13895 intel_state->active_crtcs &= ~(1 << i);
Matt Roper8b4a7d02016-05-12 07:06:00 -070013896
13897 if (crtc_state->active != crtc->state->active)
13898 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013899 }
13900
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013901 /*
13902 * See if the config requires any additional preparation, e.g.
13903 * to adjust global state with pipes off. We need to do this
13904 * here so we can get the modeset_pipe updated config for the new
13905 * mode set on this crtc. For other crtcs we need to use the
13906 * adjusted_mode bits in the crtc directly.
13907 */
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013908 if (dev_priv->display.modeset_calc_cdclk) {
Clint Taylorc89e39f2016-05-13 23:41:21 +030013909 if (!intel_state->cdclk_pll_vco)
Ville Syrjälä63911d72016-05-13 23:41:32 +030013910 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
Ville Syrjäläb2045352016-05-13 23:41:27 +030013911 if (!intel_state->cdclk_pll_vco)
13912 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013913
Clint Taylorc89e39f2016-05-13 23:41:21 +030013914 ret = dev_priv->display.modeset_calc_cdclk(state);
13915 if (ret < 0)
13916 return ret;
13917
13918 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
Ville Syrjälä63911d72016-05-13 23:41:32 +030013919 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013920 ret = intel_modeset_all_pipes(state);
13921
13922 if (ret < 0)
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013923 return ret;
Maarten Lankhorste8788cb2016-02-16 10:25:11 +010013924
13925 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13926 intel_state->cdclk, intel_state->dev_cdclk);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013927 } else
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010013928 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013929
Maarten Lankhorstad421372015-06-15 12:33:42 +020013930 intel_modeset_clear_plls(state);
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013931
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013932 if (IS_HASWELL(dev_priv))
Maarten Lankhorstad421372015-06-15 12:33:42 +020013933 return haswell_mode_set_planes_workaround(state);
Maarten Lankhorst99d736a2015-06-01 12:50:09 +020013934
Maarten Lankhorstad421372015-06-15 12:33:42 +020013935 return 0;
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013936}
13937
Matt Roperaa363132015-09-24 15:53:18 -070013938/*
13939 * Handle calculation of various watermark data at the end of the atomic check
13940 * phase. The code here should be run after the per-crtc and per-plane 'check'
13941 * handlers to ensure that all derived state has been updated.
13942 */
Matt Roper55994c22016-05-12 07:06:08 -070013943static int calc_watermark_data(struct drm_atomic_state *state)
Matt Roperaa363132015-09-24 15:53:18 -070013944{
13945 struct drm_device *dev = state->dev;
Matt Roper98d39492016-05-12 07:06:03 -070013946 struct drm_i915_private *dev_priv = to_i915(dev);
Matt Roper98d39492016-05-12 07:06:03 -070013947
13948 /* Is there platform-specific watermark information to calculate? */
13949 if (dev_priv->display.compute_global_watermarks)
Matt Roper55994c22016-05-12 07:06:08 -070013950 return dev_priv->display.compute_global_watermarks(state);
13951
13952 return 0;
Matt Roperaa363132015-09-24 15:53:18 -070013953}
13954
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013955/**
13956 * intel_atomic_check - validate state object
13957 * @dev: drm device
13958 * @state: state to validate
13959 */
13960static int intel_atomic_check(struct drm_device *dev,
13961 struct drm_atomic_state *state)
Daniel Vettera6778b32012-07-02 09:56:42 +020013962{
Paulo Zanonidd8b3bd2016-01-19 11:35:49 -020013963 struct drm_i915_private *dev_priv = to_i915(dev);
Matt Roperaa363132015-09-24 15:53:18 -070013964 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013965 struct drm_crtc *crtc;
13966 struct drm_crtc_state *crtc_state;
13967 int ret, i;
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013968 bool any_ms = false;
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013969
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013970 ret = drm_atomic_helper_check_modeset(dev, state);
Daniel Vettera6778b32012-07-02 09:56:42 +020013971 if (ret)
13972 return ret;
13973
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013974 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013975 struct intel_crtc_state *pipe_config =
13976 to_intel_crtc_state(crtc_state);
Daniel Vetter1ed51de2015-07-15 14:15:51 +020013977
13978 /* Catch I915_MODE_FLAG_INHERITED */
13979 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13980 crtc_state->mode_changed = true;
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013981
Daniel Vetter26495482015-07-15 14:15:52 +020013982 if (!needs_modeset(crtc_state))
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013983 continue;
13984
Daniel Vetteraf4a8792016-05-09 09:31:25 +020013985 if (!crtc_state->enable) {
13986 any_ms = true;
13987 continue;
13988 }
13989
Daniel Vetter26495482015-07-15 14:15:52 +020013990 /* FIXME: For only active_changed we shouldn't need to do any
13991 * state recomputation at all. */
13992
Daniel Vetter1ed51de2015-07-15 14:15:51 +020013993 ret = drm_atomic_add_affected_connectors(state, crtc);
13994 if (ret)
13995 return ret;
Maarten Lankhorstb3592832015-06-15 12:33:38 +020013996
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013997 ret = intel_modeset_pipe_config(crtc, pipe_config);
Maarten Lankhorst25aa1c32016-05-03 10:30:38 +020013998 if (ret) {
13999 intel_dump_pipe_config(to_intel_crtc(crtc),
14000 pipe_config, "[failed]");
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020014001 return ret;
Maarten Lankhorst25aa1c32016-05-03 10:30:38 +020014002 }
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020014003
Jani Nikula73831232015-11-19 10:26:30 +020014004 if (i915.fastboot &&
Paulo Zanonidd8b3bd2016-01-19 11:35:49 -020014005 intel_pipe_config_compare(dev,
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020014006 to_intel_crtc_state(crtc->state),
Daniel Vetter1ed51de2015-07-15 14:15:51 +020014007 pipe_config, true)) {
Daniel Vetter26495482015-07-15 14:15:52 +020014008 crtc_state->mode_changed = false;
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020014009 to_intel_crtc_state(crtc_state)->update_pipe = true;
Daniel Vetter26495482015-07-15 14:15:52 +020014010 }
14011
Daniel Vetteraf4a8792016-05-09 09:31:25 +020014012 if (needs_modeset(crtc_state))
Daniel Vetter26495482015-07-15 14:15:52 +020014013 any_ms = true;
Maarten Lankhorst61333b62015-06-15 12:33:50 +020014014
Daniel Vetteraf4a8792016-05-09 09:31:25 +020014015 ret = drm_atomic_add_affected_planes(state, crtc);
14016 if (ret)
14017 return ret;
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020014018
Daniel Vetter26495482015-07-15 14:15:52 +020014019 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14020 needs_modeset(crtc_state) ?
14021 "[modeset]" : "[fastset]");
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020014022 }
14023
Maarten Lankhorst61333b62015-06-15 12:33:50 +020014024 if (any_ms) {
14025 ret = intel_modeset_checks(state);
14026
14027 if (ret)
14028 return ret;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020014029 } else
Paulo Zanonidd8b3bd2016-01-19 11:35:49 -020014030 intel_state->cdclk = dev_priv->cdclk_freq;
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020014031
Paulo Zanonidd8b3bd2016-01-19 11:35:49 -020014032 ret = drm_atomic_helper_check_planes(dev, state);
Matt Roperaa363132015-09-24 15:53:18 -070014033 if (ret)
14034 return ret;
14035
Paulo Zanonif51be2e2016-01-19 11:35:50 -020014036 intel_fbc_choose_crtc(dev_priv, state);
Matt Roper55994c22016-05-12 07:06:08 -070014037 return calc_watermark_data(state);
Daniel Vettera6778b32012-07-02 09:56:42 +020014038}
14039
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014040static int intel_atomic_prepare_commit(struct drm_device *dev,
14041 struct drm_atomic_state *state,
Maarten Lankhorst81072bf2016-04-26 16:11:45 +020014042 bool nonblock)
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014043{
Chris Wilsonfac5e232016-07-04 11:34:36 +010014044 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014045 struct drm_plane_state *plane_state;
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014046 struct drm_crtc_state *crtc_state;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014047 struct drm_plane *plane;
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014048 struct drm_crtc *crtc;
14049 int i, ret;
14050
Daniel Vetter5a21b662016-05-24 17:13:53 +020014051 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14052 if (state->legacy_cursor_update)
14053 continue;
14054
14055 ret = intel_crtc_wait_for_pending_flips(crtc);
14056 if (ret)
14057 return ret;
14058
14059 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14060 flush_workqueue(dev_priv->wq);
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020014061 }
14062
Maarten Lankhorstf9356752015-08-18 13:40:05 +020014063 ret = mutex_lock_interruptible(&dev->struct_mutex);
14064 if (ret)
14065 return ret;
14066
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014067 ret = drm_atomic_helper_prepare_planes(dev, state);
Chris Wilsonf7e58382016-04-13 17:35:07 +010014068 mutex_unlock(&dev->struct_mutex);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014069
Dave Airlie21daaee2016-05-05 09:56:30 +100014070 if (!ret && !nonblock) {
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014071 for_each_plane_in_state(state, plane, plane_state, i) {
14072 struct intel_plane_state *intel_plane_state =
14073 to_intel_plane_state(plane_state);
14074
14075 if (!intel_plane_state->wait_req)
14076 continue;
14077
Chris Wilson776f3232016-08-04 07:52:40 +010014078 ret = i915_wait_request(intel_plane_state->wait_req,
Chris Wilsonea746f32016-09-09 14:11:49 +010014079 I915_WAIT_INTERRUPTIBLE,
14080 NULL, NULL);
Chris Wilsonf7e58382016-04-13 17:35:07 +010014081 if (ret) {
Chris Wilsonf4457ae2016-04-13 17:35:08 +010014082 /* Any hang should be swallowed by the wait */
14083 WARN_ON(ret == -EIO);
Chris Wilsonf7e58382016-04-13 17:35:07 +010014084 mutex_lock(&dev->struct_mutex);
14085 drm_atomic_helper_cleanup_planes(dev, state);
14086 mutex_unlock(&dev->struct_mutex);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014087 break;
Chris Wilsonf7e58382016-04-13 17:35:07 +010014088 }
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014089 }
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014090 }
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014091
14092 return ret;
14093}
14094
Maarten Lankhorsta2991412016-05-17 15:07:48 +020014095u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14096{
14097 struct drm_device *dev = crtc->base.dev;
14098
14099 if (!dev->max_vblank_count)
14100 return drm_accurate_vblank_count(&crtc->base);
14101
14102 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14103}
14104
Daniel Vetter5a21b662016-05-24 17:13:53 +020014105static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14106 struct drm_i915_private *dev_priv,
14107 unsigned crtc_mask)
Maarten Lankhorste8861672016-02-24 11:24:26 +010014108{
Daniel Vetter5a21b662016-05-24 17:13:53 +020014109 unsigned last_vblank_count[I915_MAX_PIPES];
14110 enum pipe pipe;
14111 int ret;
Maarten Lankhorste8861672016-02-24 11:24:26 +010014112
Daniel Vetter5a21b662016-05-24 17:13:53 +020014113 if (!crtc_mask)
14114 return;
Maarten Lankhorste8861672016-02-24 11:24:26 +010014115
Daniel Vetter5a21b662016-05-24 17:13:53 +020014116 for_each_pipe(dev_priv, pipe) {
14117 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Maarten Lankhorste8861672016-02-24 11:24:26 +010014118
Daniel Vetter5a21b662016-05-24 17:13:53 +020014119 if (!((1 << pipe) & crtc_mask))
Maarten Lankhorste8861672016-02-24 11:24:26 +010014120 continue;
14121
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020014122 ret = drm_crtc_vblank_get(crtc);
Daniel Vetter5a21b662016-05-24 17:13:53 +020014123 if (WARN_ON(ret != 0)) {
14124 crtc_mask &= ~(1 << pipe);
14125 continue;
14126 }
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020014127
Daniel Vetter5a21b662016-05-24 17:13:53 +020014128 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14129 }
14130
14131 for_each_pipe(dev_priv, pipe) {
14132 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14133 long lret;
14134
14135 if (!((1 << pipe) & crtc_mask))
14136 continue;
14137
14138 lret = wait_event_timeout(dev->vblank[pipe].queue,
14139 last_vblank_count[pipe] !=
14140 drm_crtc_vblank_count(crtc),
14141 msecs_to_jiffies(50));
14142
14143 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14144
14145 drm_crtc_vblank_put(crtc);
Maarten Lankhorstd55dbd02016-05-17 15:08:04 +020014146 }
14147}
14148
Daniel Vetter5a21b662016-05-24 17:13:53 +020014149static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
Maarten Lankhorsta6747b72016-05-17 15:08:01 +020014150{
Daniel Vetter5a21b662016-05-24 17:13:53 +020014151 /* fb updated, need to unpin old fb */
14152 if (crtc_state->fb_changed)
14153 return true;
Maarten Lankhorsta6747b72016-05-17 15:08:01 +020014154
Daniel Vetter5a21b662016-05-24 17:13:53 +020014155 /* wm changes, need vblank before final wm's */
14156 if (crtc_state->update_wm_post)
14157 return true;
Maarten Lankhorsta6747b72016-05-17 15:08:01 +020014158
Daniel Vetter5a21b662016-05-24 17:13:53 +020014159 /*
14160 * cxsr is re-enabled after vblank.
14161 * This is already handled by crtc_state->update_wm_post,
14162 * but added for clarity.
14163 */
14164 if (crtc_state->disable_cxsr)
14165 return true;
Maarten Lankhorsta6747b72016-05-17 15:08:01 +020014166
Daniel Vetter5a21b662016-05-24 17:13:53 +020014167 return false;
Maarten Lankhorste8861672016-02-24 11:24:26 +010014168}
14169
Lyude896e5bb2016-08-24 07:48:09 +020014170static void intel_update_crtc(struct drm_crtc *crtc,
14171 struct drm_atomic_state *state,
14172 struct drm_crtc_state *old_crtc_state,
14173 unsigned int *crtc_vblank_mask)
14174{
14175 struct drm_device *dev = crtc->dev;
14176 struct drm_i915_private *dev_priv = to_i915(dev);
14177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14178 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14179 bool modeset = needs_modeset(crtc->state);
14180
14181 if (modeset) {
14182 update_scanline_offset(intel_crtc);
14183 dev_priv->display.crtc_enable(pipe_config, state);
14184 } else {
14185 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14186 }
14187
14188 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14189 intel_fbc_enable(
14190 intel_crtc, pipe_config,
14191 to_intel_plane_state(crtc->primary->state));
14192 }
14193
14194 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14195
14196 if (needs_vblank_wait(pipe_config))
14197 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14198}
14199
14200static void intel_update_crtcs(struct drm_atomic_state *state,
14201 unsigned int *crtc_vblank_mask)
14202{
14203 struct drm_crtc *crtc;
14204 struct drm_crtc_state *old_crtc_state;
14205 int i;
14206
14207 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14208 if (!crtc->state->active)
14209 continue;
14210
14211 intel_update_crtc(crtc, state, old_crtc_state,
14212 crtc_vblank_mask);
14213 }
14214}
14215
Lyude27082492016-08-24 07:48:10 +020014216static void skl_update_crtcs(struct drm_atomic_state *state,
14217 unsigned int *crtc_vblank_mask)
14218{
14219 struct drm_device *dev = state->dev;
14220 struct drm_i915_private *dev_priv = to_i915(dev);
14221 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14222 struct drm_crtc *crtc;
14223 struct drm_crtc_state *old_crtc_state;
14224 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14225 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14226 unsigned int updated = 0;
14227 bool progress;
14228 enum pipe pipe;
14229
14230 /*
14231 * Whenever the number of active pipes changes, we need to make sure we
14232 * update the pipes in the right order so that their ddb allocations
14233 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14234 * cause pipe underruns and other bad stuff.
14235 */
14236 do {
14237 int i;
14238 progress = false;
14239
14240 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14241 bool vbl_wait = false;
14242 unsigned int cmask = drm_crtc_mask(crtc);
14243 pipe = to_intel_crtc(crtc)->pipe;
14244
14245 if (updated & cmask || !crtc->state->active)
14246 continue;
14247 if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14248 pipe))
14249 continue;
14250
14251 updated |= cmask;
14252
14253 /*
14254 * If this is an already active pipe, it's DDB changed,
14255 * and this isn't the last pipe that needs updating
14256 * then we need to wait for a vblank to pass for the
14257 * new ddb allocation to take effect.
14258 */
14259 if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14260 !crtc->state->active_changed &&
14261 intel_state->wm_results.dirty_pipes != updated)
14262 vbl_wait = true;
14263
14264 intel_update_crtc(crtc, state, old_crtc_state,
14265 crtc_vblank_mask);
14266
14267 if (vbl_wait)
14268 intel_wait_for_vblank(dev, pipe);
14269
14270 progress = true;
14271 }
14272 } while (progress);
14273}
14274
Daniel Vetter94f05022016-06-14 18:01:00 +020014275static void intel_atomic_commit_tail(struct drm_atomic_state *state)
Daniel Vettera6778b32012-07-02 09:56:42 +020014276{
Daniel Vetter94f05022016-06-14 18:01:00 +020014277 struct drm_device *dev = state->dev;
Maarten Lankhorst565602d2015-12-10 12:33:57 +010014278 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Chris Wilsonfac5e232016-07-04 11:34:36 +010014279 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä29ceb0e2016-03-09 19:07:27 +020014280 struct drm_crtc_state *old_crtc_state;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014281 struct drm_crtc *crtc;
Daniel Vetter5a21b662016-05-24 17:13:53 +020014282 struct intel_crtc_state *intel_cstate;
Daniel Vetter94f05022016-06-14 18:01:00 +020014283 struct drm_plane *plane;
14284 struct drm_plane_state *plane_state;
Daniel Vetter5a21b662016-05-24 17:13:53 +020014285 bool hw_check = intel_state->modeset;
14286 unsigned long put_domains[I915_MAX_PIPES] = {};
14287 unsigned crtc_vblank_mask = 0;
Daniel Vetter94f05022016-06-14 18:01:00 +020014288 int i, ret;
Daniel Vettera6778b32012-07-02 09:56:42 +020014289
Daniel Vetter94f05022016-06-14 18:01:00 +020014290 for_each_plane_in_state(state, plane, plane_state, i) {
14291 struct intel_plane_state *intel_plane_state =
14292 to_intel_plane_state(plane_state);
Daniel Vetterea0000f2016-06-13 16:13:46 +020014293
Daniel Vetter94f05022016-06-14 18:01:00 +020014294 if (!intel_plane_state->wait_req)
14295 continue;
14296
Chris Wilson776f3232016-08-04 07:52:40 +010014297 ret = i915_wait_request(intel_plane_state->wait_req,
Chris Wilsonea746f32016-09-09 14:11:49 +010014298 0, NULL, NULL);
Daniel Vetter94f05022016-06-14 18:01:00 +020014299 /* EIO should be eaten, and we can't get interrupted in the
14300 * worker, and blocking commits have waited already. */
14301 WARN_ON(ret);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014302 }
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030014303
Daniel Vetterea0000f2016-06-13 16:13:46 +020014304 drm_atomic_helper_wait_for_dependencies(state);
14305
Maarten Lankhorst565602d2015-12-10 12:33:57 +010014306 if (intel_state->modeset) {
14307 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14308 sizeof(intel_state->min_pixclk));
14309 dev_priv->active_crtcs = intel_state->active_crtcs;
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010014310 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
Daniel Vetter5a21b662016-05-24 17:13:53 +020014311
14312 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
Maarten Lankhorst565602d2015-12-10 12:33:57 +010014313 }
14314
Ville Syrjälä29ceb0e2016-03-09 19:07:27 +020014315 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
Maarten Lankhorsta5392052015-06-15 12:33:52 +020014316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14317
Daniel Vetter5a21b662016-05-24 17:13:53 +020014318 if (needs_modeset(crtc->state) ||
14319 to_intel_crtc_state(crtc->state)->update_pipe) {
14320 hw_check = true;
14321
14322 put_domains[to_intel_crtc(crtc)->pipe] =
14323 modeset_get_crtc_power_domains(crtc,
14324 to_intel_crtc_state(crtc->state));
14325 }
14326
Maarten Lankhorst61333b62015-06-15 12:33:50 +020014327 if (!needs_modeset(crtc->state))
14328 continue;
14329
Ville Syrjälä29ceb0e2016-03-09 19:07:27 +020014330 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
Daniel Vetter460da9162013-03-27 00:44:51 +010014331
Ville Syrjälä29ceb0e2016-03-09 19:07:27 +020014332 if (old_crtc_state->active) {
14333 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
Maarten Lankhorst4a806552016-08-09 17:04:01 +020014334 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +020014335 intel_crtc->active = false;
Paulo Zanoni58f9c0b2016-01-19 11:35:51 -020014336 intel_fbc_disable(intel_crtc);
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +020014337 intel_disable_shared_dpll(intel_crtc);
Ville Syrjälä9bbc8258a2015-11-20 22:09:20 +020014338
14339 /*
14340 * Underruns don't always raise
14341 * interrupts, so check manually.
14342 */
14343 intel_check_cpu_fifo_underruns(dev_priv);
14344 intel_check_pch_fifo_underruns(dev_priv);
Maarten Lankhorstb9001112015-11-19 16:07:16 +010014345
14346 if (!crtc->state->active)
14347 intel_update_watermarks(crtc);
Maarten Lankhorsta5392052015-06-15 12:33:52 +020014348 }
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010014349 }
Daniel Vetter7758a112012-07-08 19:40:39 +020014350
Daniel Vetterea9d7582012-07-10 10:42:52 +020014351 /* Only after disabling all output pipelines that will be changed can we
14352 * update the the output configuration. */
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020014353 intel_modeset_update_crtc_state(state);
Daniel Vetterea9d7582012-07-10 10:42:52 +020014354
Maarten Lankhorst565602d2015-12-10 12:33:57 +010014355 if (intel_state->modeset) {
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020014356 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
Maarten Lankhorst33c8df892016-02-10 13:49:37 +010014357
14358 if (dev_priv->display.modeset_commit_cdclk &&
Clint Taylorc89e39f2016-05-13 23:41:21 +030014359 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
Ville Syrjälä63911d72016-05-13 23:41:32 +030014360 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
Maarten Lankhorst33c8df892016-02-10 13:49:37 +010014361 dev_priv->display.modeset_commit_cdclk(state);
Maarten Lankhorstf6d19732016-03-23 14:58:07 +010014362
Lyude656d1b82016-08-17 15:55:54 -040014363 /*
14364 * SKL workaround: bspec recommends we disable the SAGV when we
14365 * have more then one pipe enabled
14366 */
14367 if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
14368 skl_disable_sagv(dev_priv);
14369
Maarten Lankhorstc0ead702016-03-30 10:00:05 +020014370 intel_modeset_verify_disabled(dev);
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020014371 }
Daniel Vetter47fab732012-10-26 10:58:18 +020014372
Lyude896e5bb2016-08-24 07:48:09 +020014373 /* Complete the events for pipes that have now been disabled */
Ville Syrjälä29ceb0e2016-03-09 19:07:27 +020014374 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
Maarten Lankhorstf6ac4b22015-07-13 16:30:31 +020014375 bool modeset = needs_modeset(crtc->state);
Maarten Lankhorsta5392052015-06-15 12:33:52 +020014376
Daniel Vetter1f7528c2016-06-13 16:13:45 +020014377 /* Complete events for now disable pipes here. */
14378 if (modeset && !crtc->state->active && crtc->state->event) {
14379 spin_lock_irq(&dev->event_lock);
14380 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14381 spin_unlock_irq(&dev->event_lock);
14382
14383 crtc->state->event = NULL;
14384 }
Matt Ropered4a6a72016-02-23 17:20:13 -080014385 }
14386
Lyude896e5bb2016-08-24 07:48:09 +020014387 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14388 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14389
Daniel Vetter94f05022016-06-14 18:01:00 +020014390 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14391 * already, but still need the state for the delayed optimization. To
14392 * fix this:
14393 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14394 * - schedule that vblank worker _before_ calling hw_done
14395 * - at the start of commit_tail, cancel it _synchrously
14396 * - switch over to the vblank wait helper in the core after that since
14397 * we don't need out special handling any more.
14398 */
Daniel Vetter5a21b662016-05-24 17:13:53 +020014399 if (!state->legacy_cursor_update)
14400 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14401
14402 /*
14403 * Now that the vblank has passed, we can go ahead and program the
14404 * optimal watermarks on platforms that need two-step watermark
14405 * programming.
14406 *
14407 * TODO: Move this (and other cleanup) to an async worker eventually.
14408 */
14409 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14410 intel_cstate = to_intel_crtc_state(crtc->state);
14411
14412 if (dev_priv->display.optimize_watermarks)
14413 dev_priv->display.optimize_watermarks(intel_cstate);
14414 }
14415
14416 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14417 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14418
14419 if (put_domains[i])
14420 modeset_put_power_domains(dev_priv, put_domains[i]);
14421
14422 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14423 }
14424
Lyude656d1b82016-08-17 15:55:54 -040014425 if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
14426 skl_can_enable_sagv(state))
14427 skl_enable_sagv(dev_priv);
14428
Daniel Vetter94f05022016-06-14 18:01:00 +020014429 drm_atomic_helper_commit_hw_done(state);
14430
Daniel Vetter5a21b662016-05-24 17:13:53 +020014431 if (intel_state->modeset)
14432 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14433
14434 mutex_lock(&dev->struct_mutex);
14435 drm_atomic_helper_cleanup_planes(dev, state);
14436 mutex_unlock(&dev->struct_mutex);
14437
Daniel Vetterea0000f2016-06-13 16:13:46 +020014438 drm_atomic_helper_commit_cleanup_done(state);
14439
Chris Wilson08536952016-10-14 13:18:18 +010014440 drm_atomic_state_put(state);
Jesse Barnes7f27126e2014-11-05 14:26:06 -080014441
Mika Kuoppala75714942015-12-16 09:26:48 +020014442 /* As one of the primary mmio accessors, KMS has a high likelihood
14443 * of triggering bugs in unclaimed access. After we finish
14444 * modesetting, see if an error has been flagged, and if so
14445 * enable debugging for the next modeset - and hope we catch
14446 * the culprit.
14447 *
14448 * XXX note that we assume display power is on at this point.
14449 * This might hold true now but we need to add pm helper to check
14450 * unclaimed only when the hardware is on, as atomic commits
14451 * can happen also when the device is completely off.
14452 */
14453 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
Daniel Vetter94f05022016-06-14 18:01:00 +020014454}
14455
14456static void intel_atomic_commit_work(struct work_struct *work)
14457{
14458 struct drm_atomic_state *state = container_of(work,
14459 struct drm_atomic_state,
14460 commit_work);
14461 intel_atomic_commit_tail(state);
14462}
14463
Daniel Vetter6c9c1b32016-06-13 16:13:48 +020014464static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14465{
14466 struct drm_plane_state *old_plane_state;
14467 struct drm_plane *plane;
Daniel Vetter6c9c1b32016-06-13 16:13:48 +020014468 int i;
14469
Chris Wilsonfaf5bf02016-08-04 16:32:37 +010014470 for_each_plane_in_state(state, plane, old_plane_state, i)
14471 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14472 intel_fb_obj(plane->state->fb),
14473 to_intel_plane(plane)->frontbuffer_bit);
Daniel Vetter6c9c1b32016-06-13 16:13:48 +020014474}
14475
Daniel Vetter94f05022016-06-14 18:01:00 +020014476/**
14477 * intel_atomic_commit - commit validated state object
14478 * @dev: DRM device
14479 * @state: the top-level driver state object
14480 * @nonblock: nonblocking commit
14481 *
14482 * This function commits a top-level state object that has been validated
14483 * with drm_atomic_helper_check().
14484 *
14485 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14486 * nonblocking commits are only safe for pure plane updates. Everything else
14487 * should work though.
14488 *
14489 * RETURNS
14490 * Zero for success or -errno.
14491 */
14492static int intel_atomic_commit(struct drm_device *dev,
14493 struct drm_atomic_state *state,
14494 bool nonblock)
14495{
14496 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Chris Wilsonfac5e232016-07-04 11:34:36 +010014497 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter94f05022016-06-14 18:01:00 +020014498 int ret = 0;
14499
14500 if (intel_state->modeset && nonblock) {
14501 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14502 return -EINVAL;
14503 }
14504
14505 ret = drm_atomic_helper_setup_commit(state, nonblock);
14506 if (ret)
14507 return ret;
14508
14509 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14510
14511 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14512 if (ret) {
14513 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14514 return ret;
14515 }
14516
14517 drm_atomic_helper_swap_state(state, true);
14518 dev_priv->wm.distrust_bios_wm = false;
14519 dev_priv->wm.skl_results = intel_state->wm_results;
14520 intel_shared_dpll_commit(state);
Daniel Vetter6c9c1b32016-06-13 16:13:48 +020014521 intel_atomic_track_fbs(state);
Daniel Vetter94f05022016-06-14 18:01:00 +020014522
Chris Wilson08536952016-10-14 13:18:18 +010014523 drm_atomic_state_get(state);
Daniel Vetter94f05022016-06-14 18:01:00 +020014524 if (nonblock)
14525 queue_work(system_unbound_wq, &state->commit_work);
14526 else
14527 intel_atomic_commit_tail(state);
Mika Kuoppala75714942015-12-16 09:26:48 +020014528
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020014529 return 0;
Daniel Vetterf30da182013-04-11 20:22:50 +020014530}
14531
Chris Wilsonc0c36b942012-12-19 16:08:43 +000014532void intel_crtc_restore_mode(struct drm_crtc *crtc)
14533{
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014534 struct drm_device *dev = crtc->dev;
14535 struct drm_atomic_state *state;
Maarten Lankhorste694eb02015-07-14 16:19:12 +020014536 struct drm_crtc_state *crtc_state;
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030014537 int ret;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014538
14539 state = drm_atomic_state_alloc(dev);
14540 if (!state) {
Ville Syrjälä78108b72016-05-27 20:59:19 +030014541 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14542 crtc->base.id, crtc->name);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014543 return;
14544 }
14545
Maarten Lankhorste694eb02015-07-14 16:19:12 +020014546 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014547
Maarten Lankhorste694eb02015-07-14 16:19:12 +020014548retry:
14549 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14550 ret = PTR_ERR_OR_ZERO(crtc_state);
14551 if (!ret) {
14552 if (!crtc_state->active)
14553 goto out;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014554
Maarten Lankhorste694eb02015-07-14 16:19:12 +020014555 crtc_state->mode_changed = true;
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020014556 ret = drm_atomic_commit(state);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014557 }
14558
Maarten Lankhorste694eb02015-07-14 16:19:12 +020014559 if (ret == -EDEADLK) {
14560 drm_atomic_state_clear(state);
14561 drm_modeset_backoff(state->acquire_ctx);
14562 goto retry;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030014563 }
14564
Maarten Lankhorste694eb02015-07-14 16:19:12 +020014565out:
Chris Wilson08536952016-10-14 13:18:18 +010014566 drm_atomic_state_put(state);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000014567}
14568
Bob Paauwefa959862016-07-15 14:59:02 +010014569/*
14570 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14571 * drm_atomic_helper_legacy_gamma_set() directly.
14572 */
14573static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14574 u16 *red, u16 *green, u16 *blue,
14575 uint32_t size)
14576{
14577 struct drm_device *dev = crtc->dev;
14578 struct drm_mode_config *config = &dev->mode_config;
14579 struct drm_crtc_state *state;
14580 int ret;
14581
14582 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14583 if (ret)
14584 return ret;
14585
14586 /*
14587 * Make sure we update the legacy properties so this works when
14588 * atomic is not enabled.
14589 */
14590
14591 state = crtc->state;
14592
14593 drm_object_property_set_value(&crtc->base,
14594 config->degamma_lut_property,
14595 (state->degamma_lut) ?
14596 state->degamma_lut->base.id : 0);
14597
14598 drm_object_property_set_value(&crtc->base,
14599 config->ctm_property,
14600 (state->ctm) ?
14601 state->ctm->base.id : 0);
14602
14603 drm_object_property_set_value(&crtc->base,
14604 config->gamma_lut_property,
14605 (state->gamma_lut) ?
14606 state->gamma_lut->base.id : 0);
14607
14608 return 0;
14609}
14610
Chris Wilsonf6e5b162011-04-12 18:06:51 +010014611static const struct drm_crtc_funcs intel_crtc_funcs = {
Bob Paauwefa959862016-07-15 14:59:02 +010014612 .gamma_set = intel_atomic_legacy_gamma_set,
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020014613 .set_config = drm_atomic_helper_set_config,
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000014614 .set_property = drm_atomic_helper_crtc_set_property,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010014615 .destroy = intel_crtc_destroy,
Chris Wilson527b6ab2016-06-24 13:44:03 +010014616 .page_flip = intel_crtc_page_flip,
Matt Roper13568372015-01-21 16:35:47 -080014617 .atomic_duplicate_state = intel_crtc_duplicate_state,
14618 .atomic_destroy_state = intel_crtc_destroy_state,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010014619};
14620
Matt Roper6beb8c232014-12-01 15:40:14 -080014621/**
14622 * intel_prepare_plane_fb - Prepare fb for usage on plane
14623 * @plane: drm plane to prepare for
14624 * @fb: framebuffer to prepare for presentation
14625 *
14626 * Prepares a framebuffer for usage on a display plane. Generally this
14627 * involves pinning the underlying object and updating the frontbuffer tracking
14628 * bits. Some older platforms need special physical address handling for
14629 * cursor planes.
14630 *
Maarten Lankhorstf9356752015-08-18 13:40:05 +020014631 * Must be called with struct_mutex held.
14632 *
Matt Roper6beb8c232014-12-01 15:40:14 -080014633 * Returns 0 on success, negative error code on failure.
14634 */
14635int
14636intel_prepare_plane_fb(struct drm_plane *plane,
Chris Wilson18320402016-08-18 19:00:16 +010014637 struct drm_plane_state *new_state)
Matt Roper465c1202014-05-29 08:06:54 -070014638{
14639 struct drm_device *dev = plane->dev;
Maarten Lankhorst844f9112015-09-02 10:42:40 +020014640 struct drm_framebuffer *fb = new_state->fb;
Matt Roper6beb8c232014-12-01 15:40:14 -080014641 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020014642 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
Chris Wilsonc37efb92016-06-17 08:28:47 +010014643 struct reservation_object *resv;
Matt Roper6beb8c232014-12-01 15:40:14 -080014644 int ret = 0;
Matt Roper465c1202014-05-29 08:06:54 -070014645
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020014646 if (!obj && !old_obj)
Matt Roper465c1202014-05-29 08:06:54 -070014647 return 0;
14648
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014649 if (old_obj) {
14650 struct drm_crtc_state *crtc_state =
14651 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14652
14653 /* Big Hammer, we also need to ensure that any pending
14654 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14655 * current scanout is retired before unpinning the old
14656 * framebuffer. Note that we rely on userspace rendering
14657 * into the buffer attached to the pipe they are waiting
14658 * on. If not, userspace generates a GPU hang with IPEHR
14659 * point to the MI_WAIT_FOR_EVENT.
14660 *
14661 * This should only fail upon a hung GPU, in which case we
14662 * can safely continue.
14663 */
14664 if (needs_modeset(crtc_state))
14665 ret = i915_gem_object_wait_rendering(old_obj, true);
Chris Wilsonf4457ae2016-04-13 17:35:08 +010014666 if (ret) {
14667 /* GPU hangs should have been swallowed by the wait */
14668 WARN_ON(ret == -EIO);
Maarten Lankhorstf9356752015-08-18 13:40:05 +020014669 return ret;
Chris Wilsonf4457ae2016-04-13 17:35:08 +010014670 }
Maarten Lankhorst5008e872015-08-18 13:40:05 +020014671 }
14672
Chris Wilsonc37efb92016-06-17 08:28:47 +010014673 if (!obj)
14674 return 0;
14675
Daniel Vetter5a21b662016-05-24 17:13:53 +020014676 /* For framebuffer backed by dmabuf, wait for fence */
Chris Wilsonc37efb92016-06-17 08:28:47 +010014677 resv = i915_gem_object_get_dmabuf_resv(obj);
14678 if (resv) {
Daniel Vetter5a21b662016-05-24 17:13:53 +020014679 long lret;
14680
Chris Wilsonc37efb92016-06-17 08:28:47 +010014681 lret = reservation_object_wait_timeout_rcu(resv, false, true,
Daniel Vetter5a21b662016-05-24 17:13:53 +020014682 MAX_SCHEDULE_TIMEOUT);
14683 if (lret == -ERESTARTSYS)
14684 return lret;
14685
14686 WARN(lret < 0, "waiting returns %li\n", lret);
14687 }
14688
Chris Wilsonc37efb92016-06-17 08:28:47 +010014689 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
Matt Roper6beb8c232014-12-01 15:40:14 -080014690 INTEL_INFO(dev)->cursor_needs_physical) {
14691 int align = IS_I830(dev) ? 16 * 1024 : 256;
14692 ret = i915_gem_object_attach_phys(obj, align);
14693 if (ret)
14694 DRM_DEBUG_KMS("failed to attach phys object\n");
14695 } else {
Chris Wilson058d88c2016-08-15 10:49:06 +010014696 struct i915_vma *vma;
14697
14698 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14699 if (IS_ERR(vma))
14700 ret = PTR_ERR(vma);
Matt Roper6beb8c232014-12-01 15:40:14 -080014701 }
14702
Chris Wilsonc37efb92016-06-17 08:28:47 +010014703 if (ret == 0) {
Chris Wilson27c01aa2016-08-04 07:52:30 +010014704 to_intel_plane_state(new_state)->wait_req =
Chris Wilsond72d9082016-08-04 07:52:31 +010014705 i915_gem_active_get(&obj->last_write,
14706 &obj->base.dev->struct_mutex);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014707 }
Matt Roper6beb8c232014-12-01 15:40:14 -080014708
Matt Roper6beb8c232014-12-01 15:40:14 -080014709 return ret;
14710}
14711
Matt Roper38f3ce32014-12-02 07:45:25 -080014712/**
14713 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14714 * @plane: drm plane to clean up for
14715 * @fb: old framebuffer that was on plane
14716 *
14717 * Cleans up a framebuffer that has just been removed from a plane.
Maarten Lankhorstf9356752015-08-18 13:40:05 +020014718 *
14719 * Must be called with struct_mutex held.
Matt Roper38f3ce32014-12-02 07:45:25 -080014720 */
14721void
14722intel_cleanup_plane_fb(struct drm_plane *plane,
Chris Wilson18320402016-08-18 19:00:16 +010014723 struct drm_plane_state *old_state)
Matt Roper38f3ce32014-12-02 07:45:25 -080014724{
14725 struct drm_device *dev = plane->dev;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014726 struct intel_plane_state *old_intel_state;
Keith Packard84978252016-07-31 00:54:51 -070014727 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020014728 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14729 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
Matt Roper38f3ce32014-12-02 07:45:25 -080014730
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014731 old_intel_state = to_intel_plane_state(old_state);
14732
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020014733 if (!obj && !old_obj)
Matt Roper38f3ce32014-12-02 07:45:25 -080014734 return;
14735
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020014736 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14737 !INTEL_INFO(dev)->cursor_needs_physical))
Ville Syrjälä3465c582016-02-15 22:54:43 +020014738 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020014739
Keith Packard84978252016-07-31 00:54:51 -070014740 i915_gem_request_assign(&intel_state->wait_req, NULL);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020014741 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
Matt Roper465c1202014-05-29 08:06:54 -070014742}
14743
Chandra Konduru6156a452015-04-27 13:48:39 -070014744int
14745skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14746{
14747 int max_scale;
Chandra Konduru6156a452015-04-27 13:48:39 -070014748 int crtc_clock, cdclk;
14749
Maarten Lankhorstbf8a0af2015-11-24 11:29:02 +010014750 if (!intel_crtc || !crtc_state->base.enable)
Chandra Konduru6156a452015-04-27 13:48:39 -070014751 return DRM_PLANE_HELPER_NO_SCALING;
14752
Chandra Konduru6156a452015-04-27 13:48:39 -070014753 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020014754 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
Chandra Konduru6156a452015-04-27 13:48:39 -070014755
Tvrtko Ursulin54bf1ce2015-10-20 17:17:07 +010014756 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
Chandra Konduru6156a452015-04-27 13:48:39 -070014757 return DRM_PLANE_HELPER_NO_SCALING;
14758
14759 /*
14760 * skl max scale is lower of:
14761 * close to 3 but not 3, -1 is for that purpose
14762 * or
14763 * cdclk/crtc_clock
14764 */
14765 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14766
14767 return max_scale;
14768}
14769
Matt Roper465c1202014-05-29 08:06:54 -070014770static int
Gustavo Padovan3c692a42014-09-05 17:04:49 -030014771intel_check_primary_plane(struct drm_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014772 struct intel_crtc_state *crtc_state,
Gustavo Padovan3c692a42014-09-05 17:04:49 -030014773 struct intel_plane_state *state)
Matt Roper465c1202014-05-29 08:06:54 -070014774{
Ville Syrjäläb63a16f2016-01-28 16:53:54 +020014775 struct drm_i915_private *dev_priv = to_i915(plane->dev);
Matt Roper2b875c22014-12-01 15:40:13 -080014776 struct drm_crtc *crtc = state->base.crtc;
Chandra Konduru6156a452015-04-27 13:48:39 -070014777 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014778 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14779 bool can_position = false;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +020014780 int ret;
Gustavo Padovan3c692a42014-09-05 17:04:49 -030014781
Ville Syrjäläb63a16f2016-01-28 16:53:54 +020014782 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjälä693bdc22016-01-15 20:46:53 +020014783 /* use scaler when colorkey is not required */
14784 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14785 min_scale = 1;
14786 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14787 }
Sonika Jindald8106362015-04-10 14:37:28 +053014788 can_position = true;
Chandra Konduru6156a452015-04-27 13:48:39 -070014789 }
Sonika Jindald8106362015-04-10 14:37:28 +053014790
Daniel Vettercc926382016-08-15 10:41:47 +020014791 ret = drm_plane_helper_check_state(&state->base,
14792 &state->clip,
14793 min_scale, max_scale,
14794 can_position, true);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +020014795 if (ret)
14796 return ret;
14797
Daniel Vettercc926382016-08-15 10:41:47 +020014798 if (!state->base.fb)
Ville Syrjäläb63a16f2016-01-28 16:53:54 +020014799 return 0;
14800
14801 if (INTEL_GEN(dev_priv) >= 9) {
14802 ret = skl_check_plane_surface(state);
14803 if (ret)
14804 return ret;
14805 }
14806
14807 return 0;
Matt Roper465c1202014-05-29 08:06:54 -070014808}
14809
Daniel Vetter5a21b662016-05-24 17:13:53 +020014810static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14811 struct drm_crtc_state *old_crtc_state)
14812{
14813 struct drm_device *dev = crtc->dev;
Lyude62e0fb82016-08-22 12:50:08 -040014814 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5a21b662016-05-24 17:13:53 +020014815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14816 struct intel_crtc_state *old_intel_state =
14817 to_intel_crtc_state(old_crtc_state);
14818 bool modeset = needs_modeset(crtc->state);
Lyude62e0fb82016-08-22 12:50:08 -040014819 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter5a21b662016-05-24 17:13:53 +020014820
14821 /* Perform vblank evasion around commit operation */
14822 intel_pipe_update_start(intel_crtc);
14823
14824 if (modeset)
14825 return;
14826
14827 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14828 intel_color_set_csc(crtc->state);
14829 intel_color_load_luts(crtc->state);
14830 }
14831
14832 if (to_intel_crtc_state(crtc->state)->update_pipe)
14833 intel_update_pipe_config(intel_crtc, old_intel_state);
Lyude62e0fb82016-08-22 12:50:08 -040014834 else if (INTEL_GEN(dev_priv) >= 9) {
Daniel Vetter5a21b662016-05-24 17:13:53 +020014835 skl_detach_scalers(intel_crtc);
Lyude62e0fb82016-08-22 12:50:08 -040014836
14837 I915_WRITE(PIPE_WM_LINETIME(pipe),
14838 dev_priv->wm.skl_hw.wm_linetime[pipe]);
14839 }
Daniel Vetter5a21b662016-05-24 17:13:53 +020014840}
14841
14842static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14843 struct drm_crtc_state *old_crtc_state)
14844{
14845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14846
14847 intel_pipe_update_end(intel_crtc, NULL);
14848}
14849
Matt Ropercf4c7c12014-12-04 10:27:42 -080014850/**
Matt Roper4a3b8762014-12-23 10:41:51 -080014851 * intel_plane_destroy - destroy a plane
14852 * @plane: plane to destroy
Matt Ropercf4c7c12014-12-04 10:27:42 -080014853 *
Matt Roper4a3b8762014-12-23 10:41:51 -080014854 * Common destruction function for all types of planes (primary, cursor,
14855 * sprite).
Matt Ropercf4c7c12014-12-04 10:27:42 -080014856 */
Matt Roper4a3b8762014-12-23 10:41:51 -080014857void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070014858{
Ville Syrjälä69ae5612016-05-27 20:59:22 +030014859 if (!plane)
14860 return;
14861
Matt Roper465c1202014-05-29 08:06:54 -070014862 drm_plane_cleanup(plane);
Ville Syrjälä69ae5612016-05-27 20:59:22 +030014863 kfree(to_intel_plane(plane));
Matt Roper465c1202014-05-29 08:06:54 -070014864}
14865
Matt Roper65a3fea2015-01-21 16:35:42 -080014866const struct drm_plane_funcs intel_plane_funcs = {
Matt Roper70a101f2015-04-08 18:56:53 -070014867 .update_plane = drm_atomic_helper_update_plane,
14868 .disable_plane = drm_atomic_helper_disable_plane,
Matt Roper3d7d6512014-06-10 08:28:13 -070014869 .destroy = intel_plane_destroy,
Matt Roperc196e1d2015-01-21 16:35:48 -080014870 .set_property = drm_atomic_helper_plane_set_property,
Matt Ropera98b3432015-01-21 16:35:43 -080014871 .atomic_get_property = intel_plane_atomic_get_property,
14872 .atomic_set_property = intel_plane_atomic_set_property,
Matt Roperea2c67b2014-12-23 10:41:52 -080014873 .atomic_duplicate_state = intel_plane_duplicate_state,
14874 .atomic_destroy_state = intel_plane_destroy_state,
14875
Matt Roper465c1202014-05-29 08:06:54 -070014876};
14877
14878static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14879 int pipe)
14880{
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000014881 struct intel_plane *primary = NULL;
14882 struct intel_plane_state *state = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070014883 const uint32_t *intel_primary_formats;
Thierry Reding45e37432015-08-12 16:54:28 +020014884 unsigned int num_formats;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000014885 int ret;
Matt Roper465c1202014-05-29 08:06:54 -070014886
14887 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000014888 if (!primary)
14889 goto fail;
Matt Roper465c1202014-05-29 08:06:54 -070014890
Matt Roper8e7d6882015-01-21 16:35:41 -080014891 state = intel_create_plane_state(&primary->base);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000014892 if (!state)
14893 goto fail;
Matt Roper8e7d6882015-01-21 16:35:41 -080014894 primary->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -080014895
Matt Roper465c1202014-05-29 08:06:54 -070014896 primary->can_scale = false;
14897 primary->max_downscale = 1;
Chandra Konduru6156a452015-04-27 13:48:39 -070014898 if (INTEL_INFO(dev)->gen >= 9) {
14899 primary->can_scale = true;
Chandra Konduruaf99ced2015-05-11 14:35:47 -070014900 state->scaler_id = -1;
Chandra Konduru6156a452015-04-27 13:48:39 -070014901 }
Matt Roper465c1202014-05-29 08:06:54 -070014902 primary->pipe = pipe;
14903 primary->plane = pipe;
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030014904 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
Matt Roperc59cb172014-12-01 15:40:16 -080014905 primary->check_plane = intel_check_primary_plane;
Matt Roper465c1202014-05-29 08:06:54 -070014906 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14907 primary->plane = !pipe;
14908
Damien Lespiau6c0fd452015-05-19 12:29:16 +010014909 if (INTEL_INFO(dev)->gen >= 9) {
14910 intel_primary_formats = skl_primary_formats;
14911 num_formats = ARRAY_SIZE(skl_primary_formats);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +010014912
14913 primary->update_plane = skylake_update_primary_plane;
14914 primary->disable_plane = skylake_disable_primary_plane;
14915 } else if (HAS_PCH_SPLIT(dev)) {
14916 intel_primary_formats = i965_primary_formats;
14917 num_formats = ARRAY_SIZE(i965_primary_formats);
14918
14919 primary->update_plane = ironlake_update_primary_plane;
14920 primary->disable_plane = i9xx_disable_primary_plane;
Damien Lespiau6c0fd452015-05-19 12:29:16 +010014921 } else if (INTEL_INFO(dev)->gen >= 4) {
Damien Lespiau568db4f2015-05-12 16:13:18 +010014922 intel_primary_formats = i965_primary_formats;
14923 num_formats = ARRAY_SIZE(i965_primary_formats);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +010014924
14925 primary->update_plane = i9xx_update_primary_plane;
14926 primary->disable_plane = i9xx_disable_primary_plane;
Damien Lespiau6c0fd452015-05-19 12:29:16 +010014927 } else {
14928 intel_primary_formats = i8xx_primary_formats;
14929 num_formats = ARRAY_SIZE(i8xx_primary_formats);
Maarten Lankhorsta8d201a2016-01-07 11:54:11 +010014930
14931 primary->update_plane = i9xx_update_primary_plane;
14932 primary->disable_plane = i9xx_disable_primary_plane;
Matt Roper465c1202014-05-29 08:06:54 -070014933 }
14934
Ville Syrjälä38573dc2016-05-27 20:59:23 +030014935 if (INTEL_INFO(dev)->gen >= 9)
14936 ret = drm_universal_plane_init(dev, &primary->base, 0,
14937 &intel_plane_funcs,
14938 intel_primary_formats, num_formats,
14939 DRM_PLANE_TYPE_PRIMARY,
14940 "plane 1%c", pipe_name(pipe));
14941 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14942 ret = drm_universal_plane_init(dev, &primary->base, 0,
14943 &intel_plane_funcs,
14944 intel_primary_formats, num_formats,
14945 DRM_PLANE_TYPE_PRIMARY,
14946 "primary %c", pipe_name(pipe));
14947 else
14948 ret = drm_universal_plane_init(dev, &primary->base, 0,
14949 &intel_plane_funcs,
14950 intel_primary_formats, num_formats,
14951 DRM_PLANE_TYPE_PRIMARY,
14952 "plane %c", plane_name(primary->plane));
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000014953 if (ret)
14954 goto fail;
Sonika Jindal48404c12014-08-22 14:06:04 +053014955
Sonika Jindal3b7a5112015-04-10 14:37:29 +053014956 if (INTEL_INFO(dev)->gen >= 4)
14957 intel_create_rotation_property(dev, primary);
Sonika Jindal48404c12014-08-22 14:06:04 +053014958
Matt Roperea2c67b2014-12-23 10:41:52 -080014959 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14960
Matt Roper465c1202014-05-29 08:06:54 -070014961 return &primary->base;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000014962
14963fail:
14964 kfree(state);
14965 kfree(primary);
14966
14967 return NULL;
Matt Roper465c1202014-05-29 08:06:54 -070014968}
14969
Sonika Jindal3b7a5112015-04-10 14:37:29 +053014970void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14971{
14972 if (!dev->mode_config.rotation_property) {
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +030014973 unsigned long flags = DRM_ROTATE_0 |
14974 DRM_ROTATE_180;
Sonika Jindal3b7a5112015-04-10 14:37:29 +053014975
14976 if (INTEL_INFO(dev)->gen >= 9)
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +030014977 flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
Sonika Jindal3b7a5112015-04-10 14:37:29 +053014978
14979 dev->mode_config.rotation_property =
14980 drm_mode_create_rotation_property(dev, flags);
14981 }
14982 if (dev->mode_config.rotation_property)
14983 drm_object_attach_property(&plane->base.base,
14984 dev->mode_config.rotation_property,
14985 plane->base.state->rotation);
14986}
14987
Matt Roper3d7d6512014-06-10 08:28:13 -070014988static int
Gustavo Padovan852e7872014-09-05 17:22:31 -030014989intel_check_cursor_plane(struct drm_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014990 struct intel_crtc_state *crtc_state,
Gustavo Padovan852e7872014-09-05 17:22:31 -030014991 struct intel_plane_state *state)
Matt Roper3d7d6512014-06-10 08:28:13 -070014992{
Matt Roper2b875c22014-12-01 15:40:13 -080014993 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014994 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Ville Syrjäläb29ec922015-12-18 19:24:39 +020014995 enum pipe pipe = to_intel_plane(plane)->pipe;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014996 unsigned stride;
14997 int ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030014998
Ville Syrjäläf8856a42016-07-26 19:07:00 +030014999 ret = drm_plane_helper_check_state(&state->base,
15000 &state->clip,
15001 DRM_PLANE_HELPER_NO_SCALING,
15002 DRM_PLANE_HELPER_NO_SCALING,
15003 true, true);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015004 if (ret)
15005 return ret;
15006
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015007 /* if we want to turn off the cursor ignore width and height */
15008 if (!obj)
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020015009 return 0;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015010
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015011 /* Check for which cursor types we support */
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020015012 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
Matt Roperea2c67b2014-12-23 10:41:52 -080015013 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15014 state->base.crtc_w, state->base.crtc_h);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015015 return -EINVAL;
15016 }
15017
Matt Roperea2c67b2014-12-23 10:41:52 -080015018 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15019 if (obj->base.size < stride * state->base.crtc_h) {
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015020 DRM_DEBUG_KMS("buffer is too small\n");
15021 return -ENOMEM;
15022 }
15023
Ville Syrjälä3a656b52015-03-09 21:08:37 +020015024 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015025 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020015026 return -EINVAL;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015027 }
Gustavo Padovan757f9a32014-09-24 14:20:24 -030015028
Ville Syrjäläb29ec922015-12-18 19:24:39 +020015029 /*
15030 * There's something wrong with the cursor on CHV pipe C.
15031 * If it straddles the left edge of the screen then
15032 * moving it away from the edge or disabling it often
15033 * results in a pipe underrun, and often that can lead to
15034 * dead pipe (constant underrun reported, and it scans
15035 * out just a solid color). To recover from that, the
15036 * display power well must be turned off and on again.
15037 * Refuse the put the cursor into that compromised position.
15038 */
15039 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
Ville Syrjälä936e71e2016-07-26 19:06:59 +030015040 state->base.visible && state->base.crtc_x < 0) {
Ville Syrjäläb29ec922015-12-18 19:24:39 +020015041 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15042 return -EINVAL;
15043 }
15044
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020015045 return 0;
Gustavo Padovan852e7872014-09-05 17:22:31 -030015046}
15047
Matt Roperf4a2cf22014-12-01 15:40:12 -080015048static void
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030015049intel_disable_cursor_plane(struct drm_plane *plane,
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +020015050 struct drm_crtc *crtc)
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030015051{
Maarten Lankhorstf2858022016-01-07 11:54:09 +010015052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15053
15054 intel_crtc->cursor_addr = 0;
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010015055 intel_crtc_update_cursor(crtc, NULL);
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030015056}
15057
15058static void
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010015059intel_update_cursor_plane(struct drm_plane *plane,
15060 const struct intel_crtc_state *crtc_state,
15061 const struct intel_plane_state *state)
Gustavo Padovan852e7872014-09-05 17:22:31 -030015062{
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010015063 struct drm_crtc *crtc = crtc_state->base.crtc;
15064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roperea2c67b2014-12-23 10:41:52 -080015065 struct drm_device *dev = plane->dev;
Matt Roper2b875c22014-12-01 15:40:13 -080015066 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
Gustavo Padovana912f122014-12-01 15:40:10 -080015067 uint32_t addr;
Matt Roper3d7d6512014-06-10 08:28:13 -070015068
Matt Roperf4a2cf22014-12-01 15:40:12 -080015069 if (!obj)
Gustavo Padovana912f122014-12-01 15:40:10 -080015070 addr = 0;
Matt Roperf4a2cf22014-12-01 15:40:12 -080015071 else if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilson058d88c2016-08-15 10:49:06 +010015072 addr = i915_gem_object_ggtt_offset(obj, NULL);
Matt Roperf4a2cf22014-12-01 15:40:12 -080015073 else
Gustavo Padovana912f122014-12-01 15:40:10 -080015074 addr = obj->phys_handle->busaddr;
Gustavo Padovana912f122014-12-01 15:40:10 -080015075
Gustavo Padovana912f122014-12-01 15:40:10 -080015076 intel_crtc->cursor_addr = addr;
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010015077 intel_crtc_update_cursor(crtc, state);
Matt Roper3d7d6512014-06-10 08:28:13 -070015078}
Gustavo Padovan852e7872014-09-05 17:22:31 -030015079
Matt Roper3d7d6512014-06-10 08:28:13 -070015080static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15081 int pipe)
15082{
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000015083 struct intel_plane *cursor = NULL;
15084 struct intel_plane_state *state = NULL;
15085 int ret;
Matt Roper3d7d6512014-06-10 08:28:13 -070015086
15087 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000015088 if (!cursor)
15089 goto fail;
Matt Roper3d7d6512014-06-10 08:28:13 -070015090
Matt Roper8e7d6882015-01-21 16:35:41 -080015091 state = intel_create_plane_state(&cursor->base);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000015092 if (!state)
15093 goto fail;
Matt Roper8e7d6882015-01-21 16:35:41 -080015094 cursor->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -080015095
Matt Roper3d7d6512014-06-10 08:28:13 -070015096 cursor->can_scale = false;
15097 cursor->max_downscale = 1;
15098 cursor->pipe = pipe;
15099 cursor->plane = pipe;
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030015100 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
Matt Roperc59cb172014-12-01 15:40:16 -080015101 cursor->check_plane = intel_check_cursor_plane;
Maarten Lankhorst55a08b3f2016-01-07 11:54:10 +010015102 cursor->update_plane = intel_update_cursor_plane;
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030015103 cursor->disable_plane = intel_disable_cursor_plane;
Matt Roper3d7d6512014-06-10 08:28:13 -070015104
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000015105 ret = drm_universal_plane_init(dev, &cursor->base, 0,
15106 &intel_plane_funcs,
15107 intel_cursor_formats,
15108 ARRAY_SIZE(intel_cursor_formats),
Ville Syrjälä38573dc2016-05-27 20:59:23 +030015109 DRM_PLANE_TYPE_CURSOR,
15110 "cursor %c", pipe_name(pipe));
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000015111 if (ret)
15112 goto fail;
Ville Syrjälä4398ad42014-10-23 07:41:34 -070015113
15114 if (INTEL_INFO(dev)->gen >= 4) {
15115 if (!dev->mode_config.rotation_property)
15116 dev->mode_config.rotation_property =
15117 drm_mode_create_rotation_property(dev,
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +030015118 DRM_ROTATE_0 |
15119 DRM_ROTATE_180);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070015120 if (dev->mode_config.rotation_property)
15121 drm_object_attach_property(&cursor->base.base,
15122 dev->mode_config.rotation_property,
Matt Roper8e7d6882015-01-21 16:35:41 -080015123 state->base.rotation);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070015124 }
15125
Chandra Konduruaf99ced2015-05-11 14:35:47 -070015126 if (INTEL_INFO(dev)->gen >=9)
15127 state->scaler_id = -1;
15128
Matt Roperea2c67b2014-12-23 10:41:52 -080015129 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15130
Matt Roper3d7d6512014-06-10 08:28:13 -070015131 return &cursor->base;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +000015132
15133fail:
15134 kfree(state);
15135 kfree(cursor);
15136
15137 return NULL;
Matt Roper3d7d6512014-06-10 08:28:13 -070015138}
15139
Chandra Konduru549e2bf2015-04-07 15:28:38 -070015140static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15141 struct intel_crtc_state *crtc_state)
15142{
15143 int i;
15144 struct intel_scaler *intel_scaler;
15145 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15146
15147 for (i = 0; i < intel_crtc->num_scalers; i++) {
15148 intel_scaler = &scaler_state->scalers[i];
15149 intel_scaler->in_use = 0;
Chandra Konduru549e2bf2015-04-07 15:28:38 -070015150 intel_scaler->mode = PS_SCALER_MODE_DYN;
15151 }
15152
15153 scaler_state->scaler_id = -1;
15154}
15155
Hannes Ederb358d0a2008-12-18 21:18:47 +010015156static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080015157{
Chris Wilsonfac5e232016-07-04 11:34:36 +010015158 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080015159 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020015160 struct intel_crtc_state *crtc_state = NULL;
Matt Roper3d7d6512014-06-10 08:28:13 -070015161 struct drm_plane *primary = NULL;
15162 struct drm_plane *cursor = NULL;
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +000015163 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080015164
Daniel Vetter955382f2013-09-19 14:05:45 +020015165 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080015166 if (intel_crtc == NULL)
15167 return;
15168
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020015169 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15170 if (!crtc_state)
15171 goto fail;
Ander Conselvan de Oliveira550acef2015-04-21 17:13:24 +030015172 intel_crtc->config = crtc_state;
15173 intel_crtc->base.state = &crtc_state->base;
Matt Roper07878242015-02-25 11:43:26 -080015174 crtc_state->base.crtc = &intel_crtc->base;
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020015175
Chandra Konduru549e2bf2015-04-07 15:28:38 -070015176 /* initialize shared scalers */
15177 if (INTEL_INFO(dev)->gen >= 9) {
15178 if (pipe == PIPE_C)
15179 intel_crtc->num_scalers = 1;
15180 else
15181 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15182
15183 skl_init_scalers(dev, intel_crtc, crtc_state);
15184 }
15185
Matt Roper465c1202014-05-29 08:06:54 -070015186 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070015187 if (!primary)
15188 goto fail;
15189
15190 cursor = intel_cursor_plane_create(dev, pipe);
15191 if (!cursor)
15192 goto fail;
15193
Matt Roper465c1202014-05-29 08:06:54 -070015194 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Ville Syrjälä4d5d72b72016-05-27 20:59:21 +030015195 cursor, &intel_crtc_funcs,
15196 "pipe %c", pipe_name(pipe));
Matt Roper3d7d6512014-06-10 08:28:13 -070015197 if (ret)
15198 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080015199
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020015200 /*
15201 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020015202 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020015203 */
Jesse Barnes80824002009-09-10 15:28:06 -070015204 intel_crtc->pipe = pipe;
15205 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010015206 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080015207 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010015208 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070015209 }
15210
Chris Wilson4b0e3332014-05-30 16:35:26 +030015211 intel_crtc->cursor_base = ~0;
15212 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030015213 intel_crtc->cursor_size = ~0;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030015214
Ville Syrjälä852eb002015-06-24 22:00:07 +030015215 intel_crtc->wm.cxsr_allowed = true;
15216
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080015217 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15218 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15219 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15220 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15221
Jesse Barnes79e53942008-11-07 14:24:08 -080015222 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020015223
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +000015224 intel_color_init(&intel_crtc->base);
15225
Daniel Vetter87b6b102014-05-15 15:33:46 +020015226 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070015227 return;
15228
15229fail:
Ville Syrjälä69ae5612016-05-27 20:59:22 +030015230 intel_plane_destroy(primary);
15231 intel_plane_destroy(cursor);
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020015232 kfree(crtc_state);
Matt Roper3d7d6512014-06-10 08:28:13 -070015233 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080015234}
15235
Jesse Barnes752aa882013-10-31 18:55:49 +020015236enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15237{
15238 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020015239 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020015240
Rob Clark51fd3712013-11-19 12:10:12 -050015241 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020015242
Ville Syrjäläd3babd32014-11-07 11:16:01 +020015243 if (!encoder || WARN_ON(!encoder->crtc))
Jesse Barnes752aa882013-10-31 18:55:49 +020015244 return INVALID_PIPE;
15245
15246 return to_intel_crtc(encoder->crtc)->pipe;
15247}
15248
Carl Worth08d7b3d2009-04-29 14:43:54 -070015249int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000015250 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070015251{
Carl Worth08d7b3d2009-04-29 14:43:54 -070015252 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040015253 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020015254 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070015255
Rob Clark7707e652014-07-17 23:30:04 -040015256 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Chris Wilson71240ed2016-06-24 14:00:24 +010015257 if (!drmmode_crtc)
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030015258 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070015259
Rob Clark7707e652014-07-17 23:30:04 -040015260 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020015261 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070015262
Daniel Vetterc05422d2009-08-11 16:05:30 +020015263 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070015264}
15265
Daniel Vetter66a92782012-07-12 20:08:18 +020015266static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080015267{
Daniel Vetter66a92782012-07-12 20:08:18 +020015268 struct drm_device *dev = encoder->base.dev;
15269 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080015270 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080015271 int entry = 0;
15272
Damien Lespiaub2784e12014-08-05 11:29:37 +010015273 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020015274 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020015275 index_mask |= (1 << entry);
15276
Jesse Barnes79e53942008-11-07 14:24:08 -080015277 entry++;
15278 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010015279
Jesse Barnes79e53942008-11-07 14:24:08 -080015280 return index_mask;
15281}
15282
Chris Wilson4d302442010-12-14 19:21:29 +000015283static bool has_edp_a(struct drm_device *dev)
15284{
Chris Wilsonfac5e232016-07-04 11:34:36 +010015285 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson4d302442010-12-14 19:21:29 +000015286
15287 if (!IS_MOBILE(dev))
15288 return false;
15289
15290 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15291 return false;
15292
Damien Lespiaue3589902014-02-07 19:12:50 +000015293 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000015294 return false;
15295
15296 return true;
15297}
15298
Jesse Barnes84b4e042014-06-25 08:24:29 -070015299static bool intel_crt_present(struct drm_device *dev)
15300{
Chris Wilsonfac5e232016-07-04 11:34:36 +010015301 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes84b4e042014-06-25 08:24:29 -070015302
Damien Lespiau884497e2013-12-03 13:56:23 +000015303 if (INTEL_INFO(dev)->gen >= 9)
15304 return false;
15305
Damien Lespiaucf404ce2014-10-01 20:04:15 +010015306 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Jesse Barnes84b4e042014-06-25 08:24:29 -070015307 return false;
15308
15309 if (IS_CHERRYVIEW(dev))
15310 return false;
15311
Ville Syrjälä65e472e2015-12-01 23:28:55 +020015312 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15313 return false;
15314
Ville Syrjälä70ac54d2015-12-01 23:29:56 +020015315 /* DDI E can't be used if DDI A requires 4 lanes */
15316 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15317 return false;
15318
Ville Syrjäläe4abb732015-12-01 23:31:33 +020015319 if (!dev_priv->vbt.int_crt_support)
Jesse Barnes84b4e042014-06-25 08:24:29 -070015320 return false;
15321
15322 return true;
15323}
15324
Imre Deak8090ba82016-08-10 14:07:33 +030015325void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15326{
15327 int pps_num;
15328 int pps_idx;
15329
15330 if (HAS_DDI(dev_priv))
15331 return;
15332 /*
15333 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15334 * everywhere where registers can be write protected.
15335 */
15336 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15337 pps_num = 2;
15338 else
15339 pps_num = 1;
15340
15341 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15342 u32 val = I915_READ(PP_CONTROL(pps_idx));
15343
15344 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15345 I915_WRITE(PP_CONTROL(pps_idx), val);
15346 }
15347}
15348
Imre Deak44cb7342016-08-10 14:07:29 +030015349static void intel_pps_init(struct drm_i915_private *dev_priv)
15350{
15351 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15352 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15353 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15354 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15355 else
15356 dev_priv->pps_mmio_base = PPS_BASE;
Imre Deak8090ba82016-08-10 14:07:33 +030015357
15358 intel_pps_unlock_regs_wa(dev_priv);
Imre Deak44cb7342016-08-10 14:07:29 +030015359}
15360
Jesse Barnes79e53942008-11-07 14:24:08 -080015361static void intel_setup_outputs(struct drm_device *dev)
15362{
Chris Wilsonfac5e232016-07-04 11:34:36 +010015363 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson4ef69c72010-09-09 15:14:28 +010015364 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040015365 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080015366
Imre Deak44cb7342016-08-10 14:07:29 +030015367 intel_pps_init(dev_priv);
15368
Imre Deak97a824e12016-06-21 11:51:47 +030015369 /*
15370 * intel_edp_init_connector() depends on this completing first, to
15371 * prevent the registeration of both eDP and LVDS and the incorrect
15372 * sharing of the PPS.
15373 */
Daniel Vetterc9093352013-06-06 22:22:47 +020015374 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080015375
Jesse Barnes84b4e042014-06-25 08:24:29 -070015376 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020015377 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040015378
Vandana Kannanc776eb22014-08-19 12:05:01 +053015379 if (IS_BROXTON(dev)) {
15380 /*
15381 * FIXME: Broxton doesn't support port detection via the
15382 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15383 * detect the ports.
15384 */
15385 intel_ddi_init(dev, PORT_A);
15386 intel_ddi_init(dev, PORT_B);
15387 intel_ddi_init(dev, PORT_C);
Shashank Sharmac6c794a2016-03-22 12:01:50 +020015388
15389 intel_dsi_init(dev);
Vandana Kannanc776eb22014-08-19 12:05:01 +053015390 } else if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030015391 int found;
15392
Jesse Barnesde31fac2015-03-06 15:53:32 -080015393 /*
15394 * Haswell uses DDI functions to detect digital outputs.
15395 * On SKL pre-D0 the strap isn't connected, so we assume
15396 * it's there.
15397 */
Ville Syrjälä77179402015-09-18 20:03:35 +030015398 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
Jesse Barnesde31fac2015-03-06 15:53:32 -080015399 /* WaIgnoreDDIAStrap: skl */
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070015400 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030015401 intel_ddi_init(dev, PORT_A);
15402
15403 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15404 * register */
15405 found = I915_READ(SFUSE_STRAP);
15406
15407 if (found & SFUSE_STRAP_DDIB_DETECTED)
15408 intel_ddi_init(dev, PORT_B);
15409 if (found & SFUSE_STRAP_DDIC_DETECTED)
15410 intel_ddi_init(dev, PORT_C);
15411 if (found & SFUSE_STRAP_DDID_DETECTED)
15412 intel_ddi_init(dev, PORT_D);
Rodrigo Vivi2800e4c2015-08-07 17:35:21 -070015413 /*
15414 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15415 */
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070015416 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
Rodrigo Vivi2800e4c2015-08-07 17:35:21 -070015417 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15418 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15419 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15420 intel_ddi_init(dev, PORT_E);
15421
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030015422 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040015423 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020015424 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020015425
15426 if (has_edp_a(dev))
15427 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040015428
Paulo Zanonidc0fa712013-02-19 16:21:46 -030015429 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080015430 /* PCH SDVOB multiplex with HDMIB */
Ville Syrjälä2a5c0832015-11-06 21:29:59 +020015431 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080015432 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030015433 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080015434 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030015435 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080015436 }
15437
Paulo Zanonidc0fa712013-02-19 16:21:46 -030015438 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030015439 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080015440
Paulo Zanonidc0fa712013-02-19 16:21:46 -030015441 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030015442 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080015443
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080015444 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030015445 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080015446
Daniel Vetter270b3042012-10-27 15:52:05 +020015447 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030015448 intel_dp_init(dev, PCH_DP_D, PORT_D);
Wayne Boyer666a4532015-12-09 12:29:35 -080015449 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjälä22f350422016-06-03 12:17:43 +030015450 bool has_edp, has_port;
Chris Wilson457c52d2016-06-01 08:27:50 +010015451
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030015452 /*
15453 * The DP_DETECTED bit is the latched state of the DDC
15454 * SDA pin at boot. However since eDP doesn't require DDC
15455 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15456 * eDP ports may have been muxed to an alternate function.
15457 * Thus we can't rely on the DP_DETECTED bit alone to detect
15458 * eDP ports. Consult the VBT as well as DP_DETECTED to
15459 * detect eDP ports.
Ville Syrjälä22f350422016-06-03 12:17:43 +030015460 *
15461 * Sadly the straps seem to be missing sometimes even for HDMI
15462 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15463 * and VBT for the presence of the port. Additionally we can't
15464 * trust the port type the VBT declares as we've seen at least
15465 * HDMI ports that the VBT claim are DP or eDP.
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030015466 */
Chris Wilson457c52d2016-06-01 08:27:50 +010015467 has_edp = intel_dp_is_edp(dev, PORT_B);
Ville Syrjälä22f350422016-06-03 12:17:43 +030015468 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15469 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
Chris Wilson457c52d2016-06-01 08:27:50 +010015470 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
Ville Syrjälä22f350422016-06-03 12:17:43 +030015471 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
Ville Syrjäläe66eb812015-09-18 20:03:34 +030015472 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030015473
Chris Wilson457c52d2016-06-01 08:27:50 +010015474 has_edp = intel_dp_is_edp(dev, PORT_C);
Ville Syrjälä22f350422016-06-03 12:17:43 +030015475 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15476 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
Chris Wilson457c52d2016-06-01 08:27:50 +010015477 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
Ville Syrjälä22f350422016-06-03 12:17:43 +030015478 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
Ville Syrjäläe66eb812015-09-18 20:03:34 +030015479 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +053015480
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030015481 if (IS_CHERRYVIEW(dev)) {
Ville Syrjälä22f350422016-06-03 12:17:43 +030015482 /*
15483 * eDP not supported on port D,
15484 * so no need to worry about it
15485 */
15486 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15487 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
Ville Syrjäläe66eb812015-09-18 20:03:34 +030015488 intel_dp_init(dev, CHV_DP_D, PORT_D);
Ville Syrjälä22f350422016-06-03 12:17:43 +030015489 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15490 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030015491 }
15492
Jani Nikula3cfca972013-08-27 15:12:26 +030015493 intel_dsi_init(dev);
Daniel Vetter09da55d2015-07-07 11:44:32 +020015494 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080015495 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080015496
Paulo Zanonie2debe92013-02-18 19:00:27 -030015497 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015498 DRM_DEBUG_KMS("probing SDVOB\n");
Ville Syrjälä2a5c0832015-11-06 21:29:59 +020015499 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
Daniel Vetter3fec3d22015-07-07 09:10:07 +020015500 if (!found && IS_G4X(dev)) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015501 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030015502 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015503 }
Ma Ling27185ae2009-08-24 13:50:23 +080015504
Daniel Vetter3fec3d22015-07-07 09:10:07 +020015505 if (!found && IS_G4X(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030015506 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080015507 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040015508
15509 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040015510
Paulo Zanonie2debe92013-02-18 19:00:27 -030015511 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015512 DRM_DEBUG_KMS("probing SDVOC\n");
Ville Syrjälä2a5c0832015-11-06 21:29:59 +020015513 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015514 }
Ma Ling27185ae2009-08-24 13:50:23 +080015515
Paulo Zanonie2debe92013-02-18 19:00:27 -030015516 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080015517
Daniel Vetter3fec3d22015-07-07 09:10:07 +020015518 if (IS_G4X(dev)) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015519 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030015520 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080015521 }
Daniel Vetter3fec3d22015-07-07 09:10:07 +020015522 if (IS_G4X(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030015523 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080015524 }
Ma Ling27185ae2009-08-24 13:50:23 +080015525
Daniel Vetter3fec3d22015-07-07 09:10:07 +020015526 if (IS_G4X(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030015527 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030015528 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070015529 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080015530 intel_dvo_init(dev);
15531
Zhenyu Wang103a1962009-11-27 11:44:36 +080015532 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080015533 intel_tv_init(dev);
15534
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -080015535 intel_psr_init(dev);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070015536
Damien Lespiaub2784e12014-08-05 11:29:37 +010015537 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010015538 encoder->base.possible_crtcs = encoder->crtc_mask;
15539 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020015540 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080015541 }
Chris Wilson47356eb2011-01-11 17:06:04 +000015542
Paulo Zanonidde86e22012-12-01 12:04:25 -020015543 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020015544
15545 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080015546}
15547
15548static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15549{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030015550 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080015551 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080015552
Daniel Vetteref2d6332014-02-10 18:00:38 +010015553 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030015554 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010015555 WARN_ON(!intel_fb->obj->framebuffer_references--);
Chris Wilsonf8c417c2016-07-20 13:31:53 +010015556 i915_gem_object_put(intel_fb->obj);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030015557 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080015558 kfree(intel_fb);
15559}
15560
15561static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000015562 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080015563 unsigned int *handle)
15564{
15565 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000015566 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080015567
Chris Wilsoncc917ab2015-10-13 14:22:26 +010015568 if (obj->userptr.mm) {
15569 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15570 return -EINVAL;
15571 }
15572
Chris Wilson05394f32010-11-08 19:18:58 +000015573 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080015574}
15575
Rodrigo Vivi86c98582015-07-08 16:22:45 -070015576static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15577 struct drm_file *file,
15578 unsigned flags, unsigned color,
15579 struct drm_clip_rect *clips,
15580 unsigned num_clips)
15581{
15582 struct drm_device *dev = fb->dev;
15583 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15584 struct drm_i915_gem_object *obj = intel_fb->obj;
15585
15586 mutex_lock(&dev->struct_mutex);
Paulo Zanoni74b4ea12015-07-14 16:29:14 -030015587 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
Rodrigo Vivi86c98582015-07-08 16:22:45 -070015588 mutex_unlock(&dev->struct_mutex);
15589
15590 return 0;
15591}
15592
Jesse Barnes79e53942008-11-07 14:24:08 -080015593static const struct drm_framebuffer_funcs intel_fb_funcs = {
15594 .destroy = intel_user_framebuffer_destroy,
15595 .create_handle = intel_user_framebuffer_create_handle,
Rodrigo Vivi86c98582015-07-08 16:22:45 -070015596 .dirty = intel_user_framebuffer_dirty,
Jesse Barnes79e53942008-11-07 14:24:08 -080015597};
15598
Damien Lespiaub3218032015-02-27 11:15:18 +000015599static
15600u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15601 uint32_t pixel_format)
15602{
15603 u32 gen = INTEL_INFO(dev)->gen;
15604
15605 if (gen >= 9) {
Ville Syrjäläac484962016-01-20 21:05:26 +020015606 int cpp = drm_format_plane_cpp(pixel_format, 0);
15607
Damien Lespiaub3218032015-02-27 11:15:18 +000015608 /* "The stride in bytes must not exceed the of the size of 8K
15609 * pixels and 32K bytes."
15610 */
Ville Syrjäläac484962016-01-20 21:05:26 +020015611 return min(8192 * cpp, 32768);
Wayne Boyer666a4532015-12-09 12:29:35 -080015612 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
Damien Lespiaub3218032015-02-27 11:15:18 +000015613 return 32*1024;
15614 } else if (gen >= 4) {
15615 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15616 return 16*1024;
15617 else
15618 return 32*1024;
15619 } else if (gen >= 3) {
15620 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15621 return 8*1024;
15622 else
15623 return 16*1024;
15624 } else {
15625 /* XXX DSPC is limited to 4k tiled */
15626 return 8*1024;
15627 }
15628}
15629
Daniel Vetterb5ea6422014-03-02 21:18:00 +010015630static int intel_framebuffer_init(struct drm_device *dev,
15631 struct intel_framebuffer *intel_fb,
15632 struct drm_mode_fb_cmd2 *mode_cmd,
15633 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080015634{
Ville Syrjälä7b49f942016-01-12 21:08:32 +020015635 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläc2ff7372016-02-11 19:16:37 +020015636 unsigned int tiling = i915_gem_object_get_tiling(obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080015637 int ret;
Damien Lespiaub3218032015-02-27 11:15:18 +000015638 u32 pitch_limit, stride_alignment;
Eric Engestromd3828142016-08-15 16:29:55 +010015639 char *format_name;
Jesse Barnes79e53942008-11-07 14:24:08 -080015640
Daniel Vetterdd4916c2013-10-09 21:23:51 +020015641 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15642
Daniel Vetter2a80ead2015-02-10 17:16:06 +000015643 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
Ville Syrjäläc2ff7372016-02-11 19:16:37 +020015644 /*
15645 * If there's a fence, enforce that
15646 * the fb modifier and tiling mode match.
15647 */
15648 if (tiling != I915_TILING_NONE &&
15649 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
Daniel Vetter2a80ead2015-02-10 17:16:06 +000015650 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15651 return -EINVAL;
15652 }
15653 } else {
Ville Syrjäläc2ff7372016-02-11 19:16:37 +020015654 if (tiling == I915_TILING_X) {
Daniel Vetter2a80ead2015-02-10 17:16:06 +000015655 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
Ville Syrjäläc2ff7372016-02-11 19:16:37 +020015656 } else if (tiling == I915_TILING_Y) {
Daniel Vetter2a80ead2015-02-10 17:16:06 +000015657 DRM_DEBUG("No Y tiling for legacy addfb\n");
15658 return -EINVAL;
15659 }
15660 }
15661
Tvrtko Ursulin9a8f0a12015-02-27 11:15:24 +000015662 /* Passed in modifier sanity checking. */
15663 switch (mode_cmd->modifier[0]) {
15664 case I915_FORMAT_MOD_Y_TILED:
15665 case I915_FORMAT_MOD_Yf_TILED:
15666 if (INTEL_INFO(dev)->gen < 9) {
15667 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15668 mode_cmd->modifier[0]);
15669 return -EINVAL;
15670 }
15671 case DRM_FORMAT_MOD_NONE:
15672 case I915_FORMAT_MOD_X_TILED:
15673 break;
15674 default:
Jesse Barnesc0f40422015-03-23 12:43:50 -070015675 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15676 mode_cmd->modifier[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010015677 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015678 }
Chris Wilson57cd6502010-08-08 12:34:44 +010015679
Ville Syrjäläc2ff7372016-02-11 19:16:37 +020015680 /*
15681 * gen2/3 display engine uses the fence if present,
15682 * so the tiling mode must match the fb modifier exactly.
15683 */
15684 if (INTEL_INFO(dev_priv)->gen < 4 &&
15685 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15686 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15687 return -EINVAL;
15688 }
15689
Ville Syrjälä7b49f942016-01-12 21:08:32 +020015690 stride_alignment = intel_fb_stride_alignment(dev_priv,
15691 mode_cmd->modifier[0],
Damien Lespiaub3218032015-02-27 11:15:18 +000015692 mode_cmd->pixel_format);
15693 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15694 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15695 mode_cmd->pitches[0], stride_alignment);
Chris Wilson57cd6502010-08-08 12:34:44 +010015696 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015697 }
Chris Wilson57cd6502010-08-08 12:34:44 +010015698
Damien Lespiaub3218032015-02-27 11:15:18 +000015699 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15700 mode_cmd->pixel_format);
Chris Wilsona35cdaa2013-06-25 17:26:45 +010015701 if (mode_cmd->pitches[0] > pitch_limit) {
Damien Lespiaub3218032015-02-27 11:15:18 +000015702 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15703 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
Daniel Vetter2a80ead2015-02-10 17:16:06 +000015704 "tiled" : "linear",
Chris Wilsona35cdaa2013-06-25 17:26:45 +010015705 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020015706 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015707 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020015708
Ville Syrjäläc2ff7372016-02-11 19:16:37 +020015709 /*
15710 * If there's a fence, enforce that
15711 * the fb pitch and fence stride match.
15712 */
15713 if (tiling != I915_TILING_NONE &&
Chris Wilson3e510a82016-08-05 10:14:23 +010015714 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015715 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
Chris Wilson3e510a82016-08-05 10:14:23 +010015716 mode_cmd->pitches[0],
15717 i915_gem_object_get_stride(obj));
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020015718 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015719 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020015720
Ville Syrjälä57779d02012-10-31 17:50:14 +020015721 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080015722 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020015723 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020015724 case DRM_FORMAT_RGB565:
15725 case DRM_FORMAT_XRGB8888:
15726 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020015727 break;
15728 case DRM_FORMAT_XRGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015729 if (INTEL_INFO(dev)->gen > 3) {
Eric Engestrom90844f02016-08-15 01:02:38 +010015730 format_name = drm_get_format_name(mode_cmd->pixel_format);
15731 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15732 kfree(format_name);
Ville Syrjälä57779d02012-10-31 17:50:14 +020015733 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015734 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020015735 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +020015736 case DRM_FORMAT_ABGR8888:
Wayne Boyer666a4532015-12-09 12:29:35 -080015737 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15738 INTEL_INFO(dev)->gen < 9) {
Eric Engestrom90844f02016-08-15 01:02:38 +010015739 format_name = drm_get_format_name(mode_cmd->pixel_format);
15740 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15741 kfree(format_name);
Damien Lespiau6c0fd452015-05-19 12:29:16 +010015742 return -EINVAL;
15743 }
15744 break;
15745 case DRM_FORMAT_XBGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020015746 case DRM_FORMAT_XRGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020015747 case DRM_FORMAT_XBGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015748 if (INTEL_INFO(dev)->gen < 4) {
Eric Engestrom90844f02016-08-15 01:02:38 +010015749 format_name = drm_get_format_name(mode_cmd->pixel_format);
15750 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15751 kfree(format_name);
Ville Syrjälä57779d02012-10-31 17:50:14 +020015752 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015753 }
Jesse Barnesb5626742011-06-24 12:19:27 -070015754 break;
Damien Lespiau75312082015-05-15 19:06:01 +010015755 case DRM_FORMAT_ABGR2101010:
Wayne Boyer666a4532015-12-09 12:29:35 -080015756 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
Eric Engestrom90844f02016-08-15 01:02:38 +010015757 format_name = drm_get_format_name(mode_cmd->pixel_format);
15758 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15759 kfree(format_name);
Damien Lespiau75312082015-05-15 19:06:01 +010015760 return -EINVAL;
15761 }
15762 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020015763 case DRM_FORMAT_YUYV:
15764 case DRM_FORMAT_UYVY:
15765 case DRM_FORMAT_YVYU:
15766 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015767 if (INTEL_INFO(dev)->gen < 5) {
Eric Engestrom90844f02016-08-15 01:02:38 +010015768 format_name = drm_get_format_name(mode_cmd->pixel_format);
15769 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15770 kfree(format_name);
Ville Syrjälä57779d02012-10-31 17:50:14 +020015771 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000015772 }
Chris Wilson57cd6502010-08-08 12:34:44 +010015773 break;
15774 default:
Eric Engestrom90844f02016-08-15 01:02:38 +010015775 format_name = drm_get_format_name(mode_cmd->pixel_format);
15776 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15777 kfree(format_name);
Chris Wilson57cd6502010-08-08 12:34:44 +010015778 return -EINVAL;
15779 }
15780
Ville Syrjälä90f9a332012-10-31 17:50:19 +020015781 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15782 if (mode_cmd->offsets[0] != 0)
15783 return -EINVAL;
15784
Daniel Vetterc7d73f62012-12-13 23:38:38 +010015785 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15786 intel_fb->obj = obj;
15787
Ville Syrjälä6687c902015-09-15 13:16:41 +030015788 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15789 if (ret)
15790 return ret;
Ville Syrjälä2d7a2152016-02-15 22:54:47 +020015791
Jesse Barnes79e53942008-11-07 14:24:08 -080015792 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15793 if (ret) {
15794 DRM_ERROR("framebuffer init failed %d\n", ret);
15795 return ret;
15796 }
15797
Ville Syrjälä0b05e1e2016-01-14 15:22:09 +020015798 intel_fb->obj->framebuffer_references++;
15799
Jesse Barnes79e53942008-11-07 14:24:08 -080015800 return 0;
15801}
15802
Jesse Barnes79e53942008-11-07 14:24:08 -080015803static struct drm_framebuffer *
15804intel_user_framebuffer_create(struct drm_device *dev,
15805 struct drm_file *filp,
Ville Syrjälä1eb834512015-11-11 19:11:29 +020015806 const struct drm_mode_fb_cmd2 *user_mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080015807{
Lukas Wunnerdcb13942015-07-04 11:50:58 +020015808 struct drm_framebuffer *fb;
Chris Wilson05394f32010-11-08 19:18:58 +000015809 struct drm_i915_gem_object *obj;
Ville Syrjälä76dc3762015-11-11 19:11:28 +020015810 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
Jesse Barnes79e53942008-11-07 14:24:08 -080015811
Chris Wilson03ac0642016-07-20 13:31:51 +010015812 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15813 if (!obj)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010015814 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080015815
Daniel Vetter92907cb2015-11-23 09:04:05 +010015816 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
Lukas Wunnerdcb13942015-07-04 11:50:58 +020015817 if (IS_ERR(fb))
Chris Wilson34911fd2016-07-20 13:31:54 +010015818 i915_gem_object_put_unlocked(obj);
Lukas Wunnerdcb13942015-07-04 11:50:58 +020015819
15820 return fb;
Jesse Barnes79e53942008-11-07 14:24:08 -080015821}
15822
Daniel Vetter06957262015-08-10 13:34:08 +020015823#ifndef CONFIG_DRM_FBDEV_EMULATION
Daniel Vetter0632fef2013-10-08 17:44:49 +020015824static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020015825{
15826}
15827#endif
15828
Jesse Barnes79e53942008-11-07 14:24:08 -080015829static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080015830 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020015831 .output_poll_changed = intel_fbdev_output_poll_changed,
Matt Roper5ee67f12015-01-21 16:35:44 -080015832 .atomic_check = intel_atomic_check,
15833 .atomic_commit = intel_atomic_commit,
Maarten Lankhorstde419ab2015-06-04 10:21:28 +020015834 .atomic_state_alloc = intel_atomic_state_alloc,
15835 .atomic_state_clear = intel_atomic_state_clear,
Jesse Barnes79e53942008-11-07 14:24:08 -080015836};
15837
Imre Deak88212942016-03-16 13:38:53 +020015838/**
15839 * intel_init_display_hooks - initialize the display modesetting hooks
15840 * @dev_priv: device private
15841 */
15842void intel_init_display_hooks(struct drm_i915_private *dev_priv)
Jesse Barnese70236a2009-09-21 10:42:27 -070015843{
Imre Deak88212942016-03-16 13:38:53 +020015844 if (INTEL_INFO(dev_priv)->gen >= 9) {
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000015845 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000015846 dev_priv->display.get_initial_plane_config =
15847 skylake_get_initial_plane_config;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000015848 dev_priv->display.crtc_compute_clock =
15849 haswell_crtc_compute_clock;
15850 dev_priv->display.crtc_enable = haswell_crtc_enable;
15851 dev_priv->display.crtc_disable = haswell_crtc_disable;
Imre Deak88212942016-03-16 13:38:53 +020015852 } else if (HAS_DDI(dev_priv)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010015853 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000015854 dev_priv->display.get_initial_plane_config =
15855 ironlake_get_initial_plane_config;
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +020015856 dev_priv->display.crtc_compute_clock =
15857 haswell_crtc_compute_clock;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020015858 dev_priv->display.crtc_enable = haswell_crtc_enable;
15859 dev_priv->display.crtc_disable = haswell_crtc_disable;
Imre Deak88212942016-03-16 13:38:53 +020015860 } else if (HAS_PCH_SPLIT(dev_priv)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010015861 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000015862 dev_priv->display.get_initial_plane_config =
15863 ironlake_get_initial_plane_config;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +020015864 dev_priv->display.crtc_compute_clock =
15865 ironlake_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020015866 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15867 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +020015868 } else if (IS_CHERRYVIEW(dev_priv)) {
Jesse Barnes89b667f2013-04-18 14:51:36 -070015869 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000015870 dev_priv->display.get_initial_plane_config =
15871 i9xx_get_initial_plane_config;
Ander Conselvan de Oliveira65b3d6a2016-03-21 18:00:13 +020015872 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15873 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15874 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15875 } else if (IS_VALLEYVIEW(dev_priv)) {
15876 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15877 dev_priv->display.get_initial_plane_config =
15878 i9xx_get_initial_plane_config;
15879 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
Jesse Barnes89b667f2013-04-18 14:51:36 -070015880 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15881 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Ander Conselvan de Oliveira19ec6692016-03-21 18:00:15 +020015882 } else if (IS_G4X(dev_priv)) {
15883 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15884 dev_priv->display.get_initial_plane_config =
15885 i9xx_get_initial_plane_config;
15886 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15887 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15888 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Ander Conselvan de Oliveira70e8aa22016-03-21 18:00:16 +020015889 } else if (IS_PINEVIEW(dev_priv)) {
15890 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15891 dev_priv->display.get_initial_plane_config =
15892 i9xx_get_initial_plane_config;
15893 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15894 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15895 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +020015896 } else if (!IS_GEN2(dev_priv)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010015897 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000015898 dev_priv->display.get_initial_plane_config =
15899 i9xx_get_initial_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020015900 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020015901 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15902 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Ander Conselvan de Oliveira81c97f52016-03-22 15:35:23 +020015903 } else {
15904 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15905 dev_priv->display.get_initial_plane_config =
15906 i9xx_get_initial_plane_config;
15907 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15908 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15909 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Eric Anholtf564048e2011-03-30 13:01:02 -070015910 }
Jesse Barnese70236a2009-09-21 10:42:27 -070015911
Jesse Barnese70236a2009-09-21 10:42:27 -070015912 /* Returns the core display clock speed */
Imre Deak88212942016-03-16 13:38:53 +020015913 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
Ville Syrjälä1652d192015-03-31 14:12:01 +030015914 dev_priv->display.get_display_clock_speed =
15915 skylake_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015916 else if (IS_BROXTON(dev_priv))
Bob Paauweacd3f3d2015-06-23 14:14:26 -070015917 dev_priv->display.get_display_clock_speed =
15918 broxton_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015919 else if (IS_BROADWELL(dev_priv))
Ville Syrjälä1652d192015-03-31 14:12:01 +030015920 dev_priv->display.get_display_clock_speed =
15921 broadwell_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015922 else if (IS_HASWELL(dev_priv))
Ville Syrjälä1652d192015-03-31 14:12:01 +030015923 dev_priv->display.get_display_clock_speed =
15924 haswell_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015925 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070015926 dev_priv->display.get_display_clock_speed =
15927 valleyview_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015928 else if (IS_GEN5(dev_priv))
Ville Syrjäläb37a6432015-03-31 14:11:54 +030015929 dev_priv->display.get_display_clock_speed =
15930 ilk_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015931 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15932 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
Jesse Barnese70236a2009-09-21 10:42:27 -070015933 dev_priv->display.get_display_clock_speed =
15934 i945_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015935 else if (IS_GM45(dev_priv))
Ville Syrjälä34edce22015-05-22 11:22:33 +030015936 dev_priv->display.get_display_clock_speed =
15937 gm45_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015938 else if (IS_CRESTLINE(dev_priv))
Ville Syrjälä34edce22015-05-22 11:22:33 +030015939 dev_priv->display.get_display_clock_speed =
15940 i965gm_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015941 else if (IS_PINEVIEW(dev_priv))
Ville Syrjälä34edce22015-05-22 11:22:33 +030015942 dev_priv->display.get_display_clock_speed =
15943 pnv_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015944 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
Ville Syrjälä34edce22015-05-22 11:22:33 +030015945 dev_priv->display.get_display_clock_speed =
15946 g33_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015947 else if (IS_I915G(dev_priv))
Jesse Barnese70236a2009-09-21 10:42:27 -070015948 dev_priv->display.get_display_clock_speed =
15949 i915_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015950 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
Jesse Barnese70236a2009-09-21 10:42:27 -070015951 dev_priv->display.get_display_clock_speed =
15952 i9xx_misc_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015953 else if (IS_I915GM(dev_priv))
Jesse Barnese70236a2009-09-21 10:42:27 -070015954 dev_priv->display.get_display_clock_speed =
15955 i915gm_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015956 else if (IS_I865G(dev_priv))
Jesse Barnese70236a2009-09-21 10:42:27 -070015957 dev_priv->display.get_display_clock_speed =
15958 i865_get_display_clock_speed;
Imre Deak88212942016-03-16 13:38:53 +020015959 else if (IS_I85X(dev_priv))
Jesse Barnese70236a2009-09-21 10:42:27 -070015960 dev_priv->display.get_display_clock_speed =
Ville Syrjälä1b1d2712015-05-22 11:22:31 +030015961 i85x_get_display_clock_speed;
Ville Syrjälä623e01e2015-05-22 11:22:34 +030015962 else { /* 830 */
Imre Deak88212942016-03-16 13:38:53 +020015963 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
Jesse Barnese70236a2009-09-21 10:42:27 -070015964 dev_priv->display.get_display_clock_speed =
15965 i830_get_display_clock_speed;
Ville Syrjälä623e01e2015-05-22 11:22:34 +030015966 }
Jesse Barnese70236a2009-09-21 10:42:27 -070015967
Imre Deak88212942016-03-16 13:38:53 +020015968 if (IS_GEN5(dev_priv)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053015969 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Imre Deak88212942016-03-16 13:38:53 +020015970 } else if (IS_GEN6(dev_priv)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053015971 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Imre Deak88212942016-03-16 13:38:53 +020015972 } else if (IS_IVYBRIDGE(dev_priv)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053015973 /* FIXME: detect B0+ stepping and use auto training */
15974 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Imre Deak88212942016-03-16 13:38:53 +020015975 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053015976 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Ville Syrjälä445e7802016-05-11 22:44:42 +030015977 }
15978
15979 if (IS_BROADWELL(dev_priv)) {
15980 dev_priv->display.modeset_commit_cdclk =
15981 broadwell_modeset_commit_cdclk;
15982 dev_priv->display.modeset_calc_cdclk =
15983 broadwell_modeset_calc_cdclk;
Imre Deak88212942016-03-16 13:38:53 +020015984 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020015985 dev_priv->display.modeset_commit_cdclk =
15986 valleyview_modeset_commit_cdclk;
15987 dev_priv->display.modeset_calc_cdclk =
15988 valleyview_modeset_calc_cdclk;
Imre Deak88212942016-03-16 13:38:53 +020015989 } else if (IS_BROXTON(dev_priv)) {
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020015990 dev_priv->display.modeset_commit_cdclk =
Imre Deak324513c2016-06-13 16:44:36 +030015991 bxt_modeset_commit_cdclk;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020015992 dev_priv->display.modeset_calc_cdclk =
Imre Deak324513c2016-06-13 16:44:36 +030015993 bxt_modeset_calc_cdclk;
Clint Taylorc89e39f2016-05-13 23:41:21 +030015994 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15995 dev_priv->display.modeset_commit_cdclk =
15996 skl_modeset_commit_cdclk;
15997 dev_priv->display.modeset_calc_cdclk =
15998 skl_modeset_calc_cdclk;
Jesse Barnese70236a2009-09-21 10:42:27 -070015999 }
Daniel Vetter5a21b662016-05-24 17:13:53 +020016000
Lyude27082492016-08-24 07:48:10 +020016001 if (dev_priv->info.gen >= 9)
16002 dev_priv->display.update_crtcs = skl_update_crtcs;
16003 else
16004 dev_priv->display.update_crtcs = intel_update_crtcs;
16005
Daniel Vetter5a21b662016-05-24 17:13:53 +020016006 switch (INTEL_INFO(dev_priv)->gen) {
16007 case 2:
16008 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16009 break;
16010
16011 case 3:
16012 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16013 break;
16014
16015 case 4:
16016 case 5:
16017 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16018 break;
16019
16020 case 6:
16021 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16022 break;
16023 case 7:
16024 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16025 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16026 break;
16027 case 9:
16028 /* Drop through - unsupported since execlist only. */
16029 default:
16030 /* Default just returns -ENODEV to indicate unsupported */
16031 dev_priv->display.queue_flip = intel_default_queue_flip;
16032 }
Jesse Barnese70236a2009-09-21 10:42:27 -070016033}
16034
Jesse Barnesb690e962010-07-19 13:53:12 -070016035/*
16036 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16037 * resume, or other times. This quirk makes sure that's the case for
16038 * affected systems.
16039 */
Akshay Joshi0206e352011-08-16 15:34:10 -040016040static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070016041{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016042 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesb690e962010-07-19 13:53:12 -070016043
16044 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020016045 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070016046}
16047
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030016048static void quirk_pipeb_force(struct drm_device *dev)
16049{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016050 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030016051
16052 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16053 DRM_INFO("applying pipe b force quirk\n");
16054}
16055
Keith Packard435793d2011-07-12 14:56:22 -070016056/*
16057 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16058 */
16059static void quirk_ssc_force_disable(struct drm_device *dev)
16060{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016061 struct drm_i915_private *dev_priv = to_i915(dev);
Keith Packard435793d2011-07-12 14:56:22 -070016062 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020016063 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070016064}
16065
Carsten Emde4dca20e2012-03-15 15:56:26 +010016066/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010016067 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16068 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010016069 */
16070static void quirk_invert_brightness(struct drm_device *dev)
16071{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016072 struct drm_i915_private *dev_priv = to_i915(dev);
Carsten Emde4dca20e2012-03-15 15:56:26 +010016073 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020016074 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070016075}
16076
Scot Doyle9c72cc62014-07-03 23:27:50 +000016077/* Some VBT's incorrectly indicate no backlight is present */
16078static void quirk_backlight_present(struct drm_device *dev)
16079{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016080 struct drm_i915_private *dev_priv = to_i915(dev);
Scot Doyle9c72cc62014-07-03 23:27:50 +000016081 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16082 DRM_INFO("applying backlight present quirk\n");
16083}
16084
Jesse Barnesb690e962010-07-19 13:53:12 -070016085struct intel_quirk {
16086 int device;
16087 int subsystem_vendor;
16088 int subsystem_device;
16089 void (*hook)(struct drm_device *dev);
16090};
16091
Egbert Eich5f85f172012-10-14 15:46:38 +020016092/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16093struct intel_dmi_quirk {
16094 void (*hook)(struct drm_device *dev);
16095 const struct dmi_system_id (*dmi_id_list)[];
16096};
16097
16098static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16099{
16100 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16101 return 1;
16102}
16103
16104static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16105 {
16106 .dmi_id_list = &(const struct dmi_system_id[]) {
16107 {
16108 .callback = intel_dmi_reverse_brightness,
16109 .ident = "NCR Corporation",
16110 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16111 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16112 },
16113 },
16114 { } /* terminating entry */
16115 },
16116 .hook = quirk_invert_brightness,
16117 },
16118};
16119
Ben Widawskyc43b5632012-04-16 14:07:40 -070016120static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070016121 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16122 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16123
Jesse Barnesb690e962010-07-19 13:53:12 -070016124 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16125 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16126
Ville Syrjälä5f080c02014-08-15 01:22:06 +030016127 /* 830 needs to leave pipe A & dpll A up */
16128 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16129
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030016130 /* 830 needs to leave pipe B & dpll B up */
16131 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16132
Keith Packard435793d2011-07-12 14:56:22 -070016133 /* Lenovo U160 cannot use SSC on LVDS */
16134 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020016135
16136 /* Sony Vaio Y cannot use SSC on LVDS */
16137 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010016138
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010016139 /* Acer Aspire 5734Z must invert backlight brightness */
16140 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16141
16142 /* Acer/eMachines G725 */
16143 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16144
16145 /* Acer/eMachines e725 */
16146 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16147
16148 /* Acer/Packard Bell NCL20 */
16149 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16150
16151 /* Acer Aspire 4736Z */
16152 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020016153
16154 /* Acer Aspire 5336 */
16155 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000016156
16157 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16158 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000016159
Scot Doyledfb3d47b2014-08-21 16:08:02 +000016160 /* Acer C720 Chromebook (Core i3 4005U) */
16161 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16162
jens steinb2a96012014-10-28 20:25:53 +010016163 /* Apple Macbook 2,1 (Core 2 T7400) */
16164 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16165
Jani Nikula1b9448b02015-11-05 11:49:59 +020016166 /* Apple Macbook 4,1 */
16167 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16168
Scot Doyled4967d82014-07-03 23:27:52 +000016169 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16170 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000016171
16172 /* HP Chromebook 14 (Celeron 2955U) */
16173 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jani Nikulacf6f0af2015-02-19 10:53:39 +020016174
16175 /* Dell Chromebook 11 */
16176 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
Jani Nikula9be64ee2015-10-30 14:50:24 +020016177
16178 /* Dell Chromebook 11 (2015 version) */
16179 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070016180};
16181
16182static void intel_init_quirks(struct drm_device *dev)
16183{
16184 struct pci_dev *d = dev->pdev;
16185 int i;
16186
16187 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16188 struct intel_quirk *q = &intel_quirks[i];
16189
16190 if (d->device == q->device &&
16191 (d->subsystem_vendor == q->subsystem_vendor ||
16192 q->subsystem_vendor == PCI_ANY_ID) &&
16193 (d->subsystem_device == q->subsystem_device ||
16194 q->subsystem_device == PCI_ANY_ID))
16195 q->hook(dev);
16196 }
Egbert Eich5f85f172012-10-14 15:46:38 +020016197 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16198 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16199 intel_dmi_quirks[i].hook(dev);
16200 }
Jesse Barnesb690e962010-07-19 13:53:12 -070016201}
16202
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016203/* Disable the VGA plane that we never use */
16204static void i915_disable_vga(struct drm_device *dev)
16205{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016206 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +030016207 struct pci_dev *pdev = dev_priv->drm.pdev;
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016208 u8 sr1;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020016209 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016210
Ville Syrjälä2b37c612014-01-22 21:32:38 +020016211 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
David Weinehall52a05c32016-08-22 13:32:44 +030016212 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070016213 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016214 sr1 = inb(VGA_SR_DATA);
16215 outb(sr1 | 1<<5, VGA_SR_DATA);
David Weinehall52a05c32016-08-22 13:32:44 +030016216 vga_put(pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016217 udelay(300);
16218
Ville Syrjälä01f5a622014-12-16 18:38:37 +020016219 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016220 POSTING_READ(vga_reg);
16221}
16222
Daniel Vetterf8175862012-04-10 15:50:11 +020016223void intel_modeset_init_hw(struct drm_device *dev)
16224{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016225 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010016226
Ville Syrjäläb6283052015-06-03 15:45:07 +030016227 intel_update_cdclk(dev);
Maarten Lankhorst1a617b72015-12-03 14:31:06 +010016228
16229 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16230
Daniel Vetterf8175862012-04-10 15:50:11 +020016231 intel_init_clock_gating(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020016232}
16233
Matt Roperd93c0372015-12-03 11:37:41 -080016234/*
16235 * Calculate what we think the watermarks should be for the state we've read
16236 * out of the hardware and then immediately program those watermarks so that
16237 * we ensure the hardware settings match our internal state.
16238 *
16239 * We can calculate what we think WM's should be by creating a duplicate of the
16240 * current state (which was constructed during hardware readout) and running it
16241 * through the atomic check code to calculate new watermark values in the
16242 * state object.
16243 */
16244static void sanitize_watermarks(struct drm_device *dev)
16245{
16246 struct drm_i915_private *dev_priv = to_i915(dev);
16247 struct drm_atomic_state *state;
16248 struct drm_crtc *crtc;
16249 struct drm_crtc_state *cstate;
16250 struct drm_modeset_acquire_ctx ctx;
16251 int ret;
16252 int i;
16253
16254 /* Only supported on platforms that use atomic watermark design */
Matt Ropered4a6a72016-02-23 17:20:13 -080016255 if (!dev_priv->display.optimize_watermarks)
Matt Roperd93c0372015-12-03 11:37:41 -080016256 return;
16257
16258 /*
16259 * We need to hold connection_mutex before calling duplicate_state so
16260 * that the connector loop is protected.
16261 */
16262 drm_modeset_acquire_init(&ctx, 0);
16263retry:
Matt Roper0cd12622016-01-12 07:13:37 -080016264 ret = drm_modeset_lock_all_ctx(dev, &ctx);
Matt Roperd93c0372015-12-03 11:37:41 -080016265 if (ret == -EDEADLK) {
16266 drm_modeset_backoff(&ctx);
16267 goto retry;
16268 } else if (WARN_ON(ret)) {
Matt Roper0cd12622016-01-12 07:13:37 -080016269 goto fail;
Matt Roperd93c0372015-12-03 11:37:41 -080016270 }
16271
16272 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16273 if (WARN_ON(IS_ERR(state)))
Matt Roper0cd12622016-01-12 07:13:37 -080016274 goto fail;
Matt Roperd93c0372015-12-03 11:37:41 -080016275
Matt Ropered4a6a72016-02-23 17:20:13 -080016276 /*
16277 * Hardware readout is the only time we don't want to calculate
16278 * intermediate watermarks (since we don't trust the current
16279 * watermarks).
16280 */
16281 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16282
Matt Roperd93c0372015-12-03 11:37:41 -080016283 ret = intel_atomic_check(dev, state);
16284 if (ret) {
16285 /*
16286 * If we fail here, it means that the hardware appears to be
16287 * programmed in a way that shouldn't be possible, given our
16288 * understanding of watermark requirements. This might mean a
16289 * mistake in the hardware readout code or a mistake in the
16290 * watermark calculations for a given platform. Raise a WARN
16291 * so that this is noticeable.
16292 *
16293 * If this actually happens, we'll have to just leave the
16294 * BIOS-programmed watermarks untouched and hope for the best.
16295 */
16296 WARN(true, "Could not determine valid watermarks for inherited state\n");
Arnd Bergmannb9a1b712016-10-18 17:16:23 +020016297 goto put_state;
Matt Roperd93c0372015-12-03 11:37:41 -080016298 }
16299
16300 /* Write calculated watermark values back */
Matt Roperd93c0372015-12-03 11:37:41 -080016301 for_each_crtc_in_state(state, crtc, cstate, i) {
16302 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16303
Matt Ropered4a6a72016-02-23 17:20:13 -080016304 cs->wm.need_postvbl_update = true;
16305 dev_priv->display.optimize_watermarks(cs);
Matt Roperd93c0372015-12-03 11:37:41 -080016306 }
16307
Arnd Bergmannb9a1b712016-10-18 17:16:23 +020016308put_state:
Chris Wilson08536952016-10-14 13:18:18 +010016309 drm_atomic_state_put(state);
Arnd Bergmannb9a1b712016-10-18 17:16:23 +020016310fail:
Matt Roperd93c0372015-12-03 11:37:41 -080016311 drm_modeset_drop_locks(&ctx);
16312 drm_modeset_acquire_fini(&ctx);
16313}
16314
Jesse Barnes79e53942008-11-07 14:24:08 -080016315void intel_modeset_init(struct drm_device *dev)
16316{
Joonas Lahtinen72e96d62016-03-30 16:57:10 +030016317 struct drm_i915_private *dev_priv = to_i915(dev);
16318 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Damien Lespiau1fe47782014-03-03 17:31:47 +000016319 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000016320 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080016321 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080016322
16323 drm_mode_config_init(dev);
16324
16325 dev->mode_config.min_width = 0;
16326 dev->mode_config.min_height = 0;
16327
Dave Airlie019d96c2011-09-29 16:20:42 +010016328 dev->mode_config.preferred_depth = 24;
16329 dev->mode_config.prefer_shadow = 1;
16330
Tvrtko Ursulin25bab382015-02-10 17:16:16 +000016331 dev->mode_config.allow_fb_modifiers = true;
16332
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020016333 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080016334
Jesse Barnesb690e962010-07-19 13:53:12 -070016335 intel_init_quirks(dev);
16336
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030016337 intel_init_pm(dev);
16338
Ben Widawskye3c74752013-04-05 13:12:39 -070016339 if (INTEL_INFO(dev)->num_pipes == 0)
16340 return;
16341
Lukas Wunner69f92f62015-07-15 13:57:35 +020016342 /*
16343 * There may be no VBT; and if the BIOS enabled SSC we can
16344 * just keep using it to avoid unnecessary flicker. Whereas if the
16345 * BIOS isn't using it, don't assume it will work even if the VBT
16346 * indicates as much.
16347 */
16348 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16349 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16350 DREF_SSC1_ENABLE);
16351
16352 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16353 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16354 bios_lvds_use_ssc ? "en" : "dis",
16355 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16356 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16357 }
16358 }
16359
Chris Wilsona6c45cf2010-09-17 00:32:17 +010016360 if (IS_GEN2(dev)) {
16361 dev->mode_config.max_width = 2048;
16362 dev->mode_config.max_height = 2048;
16363 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070016364 dev->mode_config.max_width = 4096;
16365 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080016366 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010016367 dev->mode_config.max_width = 8192;
16368 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080016369 }
Damien Lespiau068be562014-03-28 14:17:49 +000016370
Ville Syrjälädc41c152014-08-13 11:57:05 +030016371 if (IS_845G(dev) || IS_I865G(dev)) {
16372 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16373 dev->mode_config.cursor_height = 1023;
16374 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000016375 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16376 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16377 } else {
16378 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16379 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16380 }
16381
Joonas Lahtinen72e96d62016-03-30 16:57:10 +030016382 dev->mode_config.fb_base = ggtt->mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080016383
Zhao Yakui28c97732009-10-09 11:39:41 +080016384 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070016385 INTEL_INFO(dev)->num_pipes,
16386 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080016387
Damien Lespiau055e3932014-08-18 13:49:10 +010016388 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000016389 intel_crtc_init(dev, pipe);
Damien Lespiau3bdcfc02015-02-28 14:54:09 +000016390 for_each_sprite(dev_priv, pipe, sprite) {
Damien Lespiau1fe47782014-03-03 17:31:47 +000016391 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070016392 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030016393 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000016394 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070016395 }
Jesse Barnes79e53942008-11-07 14:24:08 -080016396 }
16397
Ville Syrjäläbfa7df02015-09-24 23:29:18 +030016398 intel_update_czclk(dev_priv);
16399 intel_update_cdclk(dev);
16400
Daniel Vettere72f9fb2013-06-05 13:34:06 +020016401 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010016402
Ville Syrjäläb2045352016-05-13 23:41:27 +030016403 if (dev_priv->max_cdclk_freq == 0)
16404 intel_update_max_cdclk(dev);
16405
Jesse Barnes9cce37f2010-08-13 15:11:26 -070016406 /* Just disable it once at startup */
16407 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080016408 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000016409
Daniel Vetter6e9f7982014-05-29 23:54:47 +020016410 drm_modeset_lock_all(dev);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016411 intel_modeset_setup_hw_state(dev);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020016412 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080016413
Damien Lespiaud3fcc802014-05-13 23:32:22 +010016414 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorsteeebeac2015-07-14 12:33:29 +020016415 struct intel_initial_plane_config plane_config = {};
16416
Jesse Barnes46f297f2014-03-07 08:57:48 -080016417 if (!crtc->active)
16418 continue;
16419
Jesse Barnes46f297f2014-03-07 08:57:48 -080016420 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080016421 * Note that reserving the BIOS fb up front prevents us
16422 * from stuffing other stolen allocations like the ring
16423 * on top. This prevents some ugliness at boot time, and
16424 * can even allow for smooth boot transitions if the BIOS
16425 * fb is large enough for the active pipe configuration.
16426 */
Maarten Lankhorsteeebeac2015-07-14 12:33:29 +020016427 dev_priv->display.get_initial_plane_config(crtc,
16428 &plane_config);
16429
16430 /*
16431 * If the fb is shared between multiple heads, we'll
16432 * just get the first one.
16433 */
16434 intel_find_initial_plane_obj(crtc, &plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080016435 }
Matt Roperd93c0372015-12-03 11:37:41 -080016436
16437 /*
16438 * Make sure hardware watermarks really match the state we read out.
16439 * Note that we need to do this after reconstructing the BIOS fb's
16440 * since the watermark calculation done here will use pstate->fb.
16441 */
16442 sanitize_watermarks(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010016443}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080016444
Daniel Vetter7fad7982012-07-04 17:51:47 +020016445static void intel_enable_pipe_a(struct drm_device *dev)
16446{
16447 struct intel_connector *connector;
16448 struct drm_connector *crt = NULL;
16449 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030016450 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020016451
16452 /* We can't just switch on the pipe A, we need to set things up with a
16453 * proper mode and output configuration. As a gross hack, enable pipe A
16454 * by enabling the load detect pipe once. */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020016455 for_each_intel_connector(dev, connector) {
Daniel Vetter7fad7982012-07-04 17:51:47 +020016456 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16457 crt = &connector->base;
16458 break;
16459 }
16460 }
16461
16462 if (!crt)
16463 return;
16464
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030016465 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +020016466 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
Daniel Vetter7fad7982012-07-04 17:51:47 +020016467}
16468
Daniel Vetterfa555832012-10-10 23:14:00 +020016469static bool
16470intel_check_plane_mapping(struct intel_crtc *crtc)
16471{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070016472 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010016473 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä649636e2015-09-22 19:50:01 +030016474 u32 val;
Daniel Vetterfa555832012-10-10 23:14:00 +020016475
Ben Widawsky7eb552a2013-03-13 14:05:41 -070016476 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020016477 return true;
16478
Ville Syrjälä649636e2015-09-22 19:50:01 +030016479 val = I915_READ(DSPCNTR(!crtc->plane));
Daniel Vetterfa555832012-10-10 23:14:00 +020016480
16481 if ((val & DISPLAY_PLANE_ENABLE) &&
16482 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16483 return false;
16484
16485 return true;
16486}
16487
Ville Syrjälä02e93c32015-08-26 19:39:19 +030016488static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16489{
16490 struct drm_device *dev = crtc->base.dev;
16491 struct intel_encoder *encoder;
16492
16493 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16494 return true;
16495
16496 return false;
16497}
16498
Maarten Lankhorst496b0fc2016-08-23 16:18:07 +020016499static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
Ville Syrjälädd756192016-02-17 21:28:45 +020016500{
16501 struct drm_device *dev = encoder->base.dev;
16502 struct intel_connector *connector;
16503
16504 for_each_connector_on_encoder(dev, &encoder->base, connector)
Maarten Lankhorst496b0fc2016-08-23 16:18:07 +020016505 return connector;
Ville Syrjälädd756192016-02-17 21:28:45 +020016506
Maarten Lankhorst496b0fc2016-08-23 16:18:07 +020016507 return NULL;
Ville Syrjälädd756192016-02-17 21:28:45 +020016508}
16509
Ville Syrjäläa168f5b2016-08-05 20:00:17 +030016510static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16511 enum transcoder pch_transcoder)
16512{
16513 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16514 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16515}
16516
Daniel Vetter24929352012-07-02 20:28:59 +020016517static void intel_sanitize_crtc(struct intel_crtc *crtc)
16518{
16519 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010016520 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula4d1de972016-03-18 17:05:42 +020016521 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Daniel Vetter24929352012-07-02 20:28:59 +020016522
Daniel Vetter24929352012-07-02 20:28:59 +020016523 /* Clear any frame start delays used for debugging left by the BIOS */
Jani Nikula4d1de972016-03-18 17:05:42 +020016524 if (!transcoder_is_dsi(cpu_transcoder)) {
16525 i915_reg_t reg = PIPECONF(cpu_transcoder);
16526
16527 I915_WRITE(reg,
16528 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16529 }
Daniel Vetter24929352012-07-02 20:28:59 +020016530
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030016531 /* restore vblank interrupts to correct state */
Daniel Vetter96256042015-02-13 21:03:42 +010016532 drm_crtc_vblank_reset(&crtc->base);
Ville Syrjäläd297e102014-08-06 14:50:01 +030016533 if (crtc->active) {
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016534 struct intel_plane *plane;
16535
Daniel Vetter96256042015-02-13 21:03:42 +010016536 drm_crtc_vblank_on(&crtc->base);
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016537
16538 /* Disable everything but the primary plane */
16539 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16540 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16541 continue;
16542
16543 plane->disable_plane(&plane->base, &crtc->base);
16544 }
Daniel Vetter96256042015-02-13 21:03:42 +010016545 }
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030016546
Daniel Vetter24929352012-07-02 20:28:59 +020016547 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020016548 * disable the crtc (and hence change the state) if it is wrong. Note
16549 * that gen4+ has a fixed plane -> pipe mapping. */
16550 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020016551 bool plane;
16552
Ville Syrjälä78108b72016-05-27 20:59:19 +030016553 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16554 crtc->base.base.id, crtc->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020016555
16556 /* Pipe has the wrong plane attached and the plane is active.
16557 * Temporarily change the plane mapping and disable everything
16558 * ... */
16559 plane = crtc->plane;
Ville Syrjälä936e71e2016-07-26 19:06:59 +030016560 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
Daniel Vetter24929352012-07-02 20:28:59 +020016561 crtc->plane = !plane;
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +020016562 intel_crtc_disable_noatomic(&crtc->base);
Daniel Vetter24929352012-07-02 20:28:59 +020016563 crtc->plane = plane;
Daniel Vetter24929352012-07-02 20:28:59 +020016564 }
Daniel Vetter24929352012-07-02 20:28:59 +020016565
Daniel Vetter7fad7982012-07-04 17:51:47 +020016566 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16567 crtc->pipe == PIPE_A && !crtc->active) {
16568 /* BIOS forgot to enable pipe A, this mostly happens after
16569 * resume. Force-enable the pipe to fix this, the update_dpms
16570 * call below we restore the pipe to the right state, but leave
16571 * the required bits on. */
16572 intel_enable_pipe_a(dev);
16573 }
16574
Daniel Vetter24929352012-07-02 20:28:59 +020016575 /* Adjust the state of the output pipe according to whether we
16576 * have active connectors/encoders. */
Maarten Lankhorst842e0302016-03-02 15:48:01 +010016577 if (crtc->active && !intel_crtc_has_encoders(crtc))
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +020016578 intel_crtc_disable_noatomic(&crtc->base);
Daniel Vetter24929352012-07-02 20:28:59 +020016579
Ville Syrjäläa3ed6aa2014-09-03 14:09:52 +030016580 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010016581 /*
16582 * We start out with underrun reporting disabled to avoid races.
16583 * For correct bookkeeping mark this on active crtcs.
16584 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020016585 * Also on gmch platforms we dont have any hardware bits to
16586 * disable the underrun reporting. Which means we need to start
16587 * out with underrun reporting disabled also on inactive pipes,
16588 * since otherwise we'll complain about the garbage we read when
16589 * e.g. coming up after runtime pm.
16590 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010016591 * No protection against concurrent access is required - at
16592 * worst a fifo underrun happens which also sets this to false.
16593 */
16594 crtc->cpu_fifo_underrun_disabled = true;
Ville Syrjäläa168f5b2016-08-05 20:00:17 +030016595 /*
16596 * We track the PCH trancoder underrun reporting state
16597 * within the crtc. With crtc for pipe A housing the underrun
16598 * reporting state for PCH transcoder A, crtc for pipe B housing
16599 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16600 * and marking underrun reporting as disabled for the non-existing
16601 * PCH transcoders B and C would prevent enabling the south
16602 * error interrupt (see cpt_can_enable_serr_int()).
16603 */
16604 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16605 crtc->pch_fifo_underrun_disabled = true;
Daniel Vetter4cc31482014-03-24 00:01:41 +010016606 }
Daniel Vetter24929352012-07-02 20:28:59 +020016607}
16608
16609static void intel_sanitize_encoder(struct intel_encoder *encoder)
16610{
16611 struct intel_connector *connector;
Daniel Vetter24929352012-07-02 20:28:59 +020016612
16613 /* We need to check both for a crtc link (meaning that the
16614 * encoder is active and trying to read from a pipe) and the
16615 * pipe itself being active. */
16616 bool has_active_crtc = encoder->base.crtc &&
16617 to_intel_crtc(encoder->base.crtc)->active;
16618
Maarten Lankhorst496b0fc2016-08-23 16:18:07 +020016619 connector = intel_encoder_find_connector(encoder);
16620 if (connector && !has_active_crtc) {
Daniel Vetter24929352012-07-02 20:28:59 +020016621 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16622 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030016623 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020016624
16625 /* Connector is active, but has no active pipe. This is
16626 * fallout from our resume register restoring. Disable
16627 * the encoder manually again. */
16628 if (encoder->base.crtc) {
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +020016629 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16630
Daniel Vetter24929352012-07-02 20:28:59 +020016631 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16632 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030016633 encoder->base.name);
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +020016634 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030016635 if (encoder->post_disable)
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +020016636 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
Daniel Vetter24929352012-07-02 20:28:59 +020016637 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020016638 encoder->base.crtc = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020016639
16640 /* Inconsistent output/port/pipe state happens presumably due to
16641 * a bug in one of the get_hw_state functions. Or someplace else
16642 * in our code, like the register restore mess on resume. Clamp
16643 * things to off as a safer default. */
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +020016644
16645 connector->base.dpms = DRM_MODE_DPMS_OFF;
16646 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020016647 }
16648 /* Enabled encoders without active connectors will be fixed in
16649 * the crtc fixup. */
16650}
16651
Imre Deak04098752014-02-18 00:02:16 +020016652void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010016653{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016654 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020016655 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010016656
Imre Deak04098752014-02-18 00:02:16 +020016657 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16658 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16659 i915_disable_vga(dev);
16660 }
16661}
16662
16663void i915_redisable_vga(struct drm_device *dev)
16664{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016665 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak04098752014-02-18 00:02:16 +020016666
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030016667 /* This function can be called both from intel_modeset_setup_hw_state or
16668 * at a very early point in our resume sequence, where the power well
16669 * structures are not yet restored. Since this function is at a very
16670 * paranoid "someone might have enabled VGA while we were not looking"
16671 * level, just check if the power well is enabled instead of trying to
16672 * follow the "don't touch the power well if we don't need it" policy
16673 * the rest of the driver uses. */
Imre Deak6392f842016-02-12 18:55:13 +020016674 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030016675 return;
16676
Imre Deak04098752014-02-18 00:02:16 +020016677 i915_redisable_vga_power_on(dev);
Imre Deak6392f842016-02-12 18:55:13 +020016678
16679 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010016680}
16681
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016682static bool primary_get_hw_state(struct intel_plane *plane)
Ville Syrjälä98ec7732014-04-30 17:43:01 +030016683{
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016684 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjälä98ec7732014-04-30 17:43:01 +030016685
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016686 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +020016687}
Ville Syrjälä98ec7732014-04-30 17:43:01 +030016688
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016689/* FIXME read out full plane state for all planes */
16690static void readout_plane_state(struct intel_crtc *crtc)
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +020016691{
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020016692 struct drm_plane *primary = crtc->base.primary;
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016693 struct intel_plane_state *plane_state =
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020016694 to_intel_plane_state(primary->state);
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +020016695
Ville Syrjälä936e71e2016-07-26 19:06:59 +030016696 plane_state->base.visible = crtc->active &&
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020016697 primary_get_hw_state(to_intel_plane(primary));
16698
Ville Syrjälä936e71e2016-07-26 19:06:59 +030016699 if (plane_state->base.visible)
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020016700 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
Ville Syrjälä98ec7732014-04-30 17:43:01 +030016701}
16702
Daniel Vetter30e984d2013-06-05 13:34:17 +020016703static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020016704{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016705 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020016706 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020016707 struct intel_crtc *crtc;
16708 struct intel_encoder *encoder;
16709 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020016710 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020016711
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016712 dev_priv->active_crtcs = 0;
16713
Damien Lespiaud3fcc802014-05-13 23:32:22 +010016714 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016715 struct intel_crtc_state *crtc_state = crtc->config;
16716 int pixclk = 0;
Daniel Vetter3b117c82013-04-17 20:15:07 +020016717
Daniel Vetterec2dc6a2016-05-09 16:34:09 +020016718 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016719 memset(crtc_state, 0, sizeof(*crtc_state));
16720 crtc_state->base.crtc = &crtc->base;
Daniel Vetter24929352012-07-02 20:28:59 +020016721
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016722 crtc_state->base.active = crtc_state->base.enable =
16723 dev_priv->display.get_pipe_config(crtc, crtc_state);
16724
16725 crtc->base.enabled = crtc_state->base.enable;
16726 crtc->active = crtc_state->base.active;
16727
16728 if (crtc_state->base.active) {
16729 dev_priv->active_crtcs |= 1 << crtc->pipe;
16730
Clint Taylorc89e39f2016-05-13 23:41:21 +030016731 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016732 pixclk = ilk_pipe_pixel_rate(crtc_state);
Ville Syrjälä9558d152016-05-13 23:41:20 +030016733 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016734 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16735 else
16736 WARN_ON(dev_priv->display.modeset_calc_cdclk);
Ville Syrjälä9558d152016-05-13 23:41:20 +030016737
16738 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16739 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16740 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
Maarten Lankhorst565602d2015-12-10 12:33:57 +010016741 }
16742
16743 dev_priv->min_pixclk[crtc->pipe] = pixclk;
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030016744
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030016745 readout_plane_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020016746
Ville Syrjälä78108b72016-05-27 20:59:19 +030016747 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16748 crtc->base.base.id, crtc->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020016749 crtc->active ? "enabled" : "disabled");
16750 }
16751
Daniel Vetter53589012013-06-05 13:34:16 +020016752 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16753 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16754
Ander Conselvan de Oliveira2edd6442016-03-08 17:46:21 +020016755 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16756 &pll->config.hw_state);
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020016757 pll->config.crtc_mask = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010016758 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorst2dd66ebd2016-03-14 09:27:52 +010016759 if (crtc->active && crtc->config->shared_dpll == pll)
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020016760 pll->config.crtc_mask |= 1 << crtc->pipe;
Daniel Vetter53589012013-06-05 13:34:16 +020016761 }
Maarten Lankhorst2dd66ebd2016-03-14 09:27:52 +010016762 pll->active_mask = pll->config.crtc_mask;
Daniel Vetter53589012013-06-05 13:34:16 +020016763
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020016764 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020016765 pll->name, pll->config.crtc_mask, pll->on);
Daniel Vetter53589012013-06-05 13:34:16 +020016766 }
16767
Damien Lespiaub2784e12014-08-05 11:29:37 +010016768 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020016769 pipe = 0;
16770
16771 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070016772 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16773 encoder->base.crtc = &crtc->base;
Ville Syrjälä253c84c2016-06-22 21:57:01 +030016774 crtc->config->output_types |= 1 << encoder->type;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020016775 encoder->get_config(encoder, crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020016776 } else {
16777 encoder->base.crtc = NULL;
16778 }
16779
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010016780 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020016781 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030016782 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020016783 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010016784 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020016785 }
16786
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020016787 for_each_intel_connector(dev, connector) {
Daniel Vetter24929352012-07-02 20:28:59 +020016788 if (connector->get_hw_state(connector)) {
16789 connector->base.dpms = DRM_MODE_DPMS_ON;
Maarten Lankhorst2aa974c2016-01-06 14:53:25 +010016790
16791 encoder = connector->encoder;
16792 connector->base.encoder = &encoder->base;
16793
16794 if (encoder->base.crtc &&
16795 encoder->base.crtc->state->active) {
16796 /*
16797 * This has to be done during hardware readout
16798 * because anything calling .crtc_disable may
16799 * rely on the connector_mask being accurate.
16800 */
16801 encoder->base.crtc->state->connector_mask |=
16802 1 << drm_connector_index(&connector->base);
Maarten Lankhorste87a52b2016-01-28 15:04:58 +010016803 encoder->base.crtc->state->encoder_mask |=
16804 1 << drm_encoder_index(&encoder->base);
Maarten Lankhorst2aa974c2016-01-06 14:53:25 +010016805 }
16806
Daniel Vetter24929352012-07-02 20:28:59 +020016807 } else {
16808 connector->base.dpms = DRM_MODE_DPMS_OFF;
16809 connector->base.encoder = NULL;
16810 }
16811 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16812 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030016813 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020016814 connector->base.encoder ? "enabled" : "disabled");
16815 }
Ville Syrjälä7f4c6282015-09-10 18:59:07 +030016816
16817 for_each_intel_crtc(dev, crtc) {
16818 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16819
16820 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16821 if (crtc->base.state->active) {
16822 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16823 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16824 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16825
16826 /*
16827 * The initial mode needs to be set in order to keep
16828 * the atomic core happy. It wants a valid mode if the
16829 * crtc's enabled, so we do the above call.
16830 *
16831 * At this point some state updated by the connectors
16832 * in their ->detect() callback has not run yet, so
16833 * no recalculation can be done yet.
16834 *
16835 * Even if we could do a recalculation and modeset
16836 * right now it would cause a double modeset if
16837 * fbdev or userspace chooses a different initial mode.
16838 *
16839 * If that happens, someone indicated they wanted a
16840 * mode change, which means it's safe to do a full
16841 * recalculation.
16842 */
16843 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
Ville Syrjälä9eca68322015-09-10 18:59:10 +030016844
16845 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16846 update_scanline_offset(crtc);
Ville Syrjälä7f4c6282015-09-10 18:59:07 +030016847 }
Ville Syrjäläe3b247d2016-02-17 21:41:09 +020016848
16849 intel_pipe_config_sanity_check(dev_priv, crtc->config);
Ville Syrjälä7f4c6282015-09-10 18:59:07 +030016850 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020016851}
16852
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016853/* Scan out the current hw modeset state,
16854 * and sanitizes it to the current state
16855 */
16856static void
16857intel_modeset_setup_hw_state(struct drm_device *dev)
Daniel Vetter30e984d2013-06-05 13:34:17 +020016858{
Chris Wilsonfac5e232016-07-04 11:34:36 +010016859 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter30e984d2013-06-05 13:34:17 +020016860 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020016861 struct intel_crtc *crtc;
16862 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020016863 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020016864
16865 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020016866
16867 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010016868 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020016869 intel_sanitize_encoder(encoder);
16870 }
16871
Damien Lespiau055e3932014-08-18 13:49:10 +010016872 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020016873 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16874 intel_sanitize_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020016875 intel_dump_pipe_config(crtc, crtc->config,
16876 "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020016877 }
Daniel Vetter9a935852012-07-05 22:34:27 +020016878
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020016879 intel_modeset_update_connector_atomic_state(dev);
16880
Daniel Vetter35c95372013-07-17 06:55:04 +020016881 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16882 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16883
Maarten Lankhorst2dd66ebd2016-03-14 09:27:52 +010016884 if (!pll->on || pll->active_mask)
Daniel Vetter35c95372013-07-17 06:55:04 +020016885 continue;
16886
16887 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16888
Ander Conselvan de Oliveira2edd6442016-03-08 17:46:21 +020016889 pll->funcs.disable(dev_priv, pll);
Daniel Vetter35c95372013-07-17 06:55:04 +020016890 pll->on = false;
16891 }
16892
Wayne Boyer666a4532015-12-09 12:29:35 -080016893 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Ville Syrjälä6eb1a682015-06-24 22:00:03 +030016894 vlv_wm_get_hw_state(dev);
16895 else if (IS_GEN9(dev))
Pradeep Bhat30789992014-11-04 17:06:45 +000016896 skl_wm_get_hw_state(dev);
16897 else if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030016898 ilk_wm_get_hw_state(dev);
Maarten Lankhorst292b9902015-07-13 16:30:27 +020016899
16900 for_each_intel_crtc(dev, crtc) {
16901 unsigned long put_domains;
16902
Maarten Lankhorst74bff5f2016-02-10 13:49:36 +010016903 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
Maarten Lankhorst292b9902015-07-13 16:30:27 +020016904 if (WARN_ON(put_domains))
16905 modeset_put_power_domains(dev_priv, put_domains);
16906 }
16907 intel_display_set_init_power(dev_priv, false);
Paulo Zanoni010cf732016-01-19 11:35:48 -020016908
16909 intel_fbc_init_pipe_state(dev_priv);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016910}
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030016911
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016912void intel_display_resume(struct drm_device *dev)
16913{
Maarten Lankhorste2c8b872016-02-16 10:06:14 +010016914 struct drm_i915_private *dev_priv = to_i915(dev);
16915 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16916 struct drm_modeset_acquire_ctx ctx;
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016917 int ret;
Daniel Vetterf30da182013-04-11 20:22:50 +020016918
Maarten Lankhorste2c8b872016-02-16 10:06:14 +010016919 dev_priv->modeset_restore_state = NULL;
Maarten Lankhorst73974892016-08-05 23:28:27 +030016920 if (state)
16921 state->acquire_ctx = &ctx;
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016922
Maarten Lankhorstea49c9a2016-02-16 15:27:42 +010016923 /*
16924 * This is a cludge because with real atomic modeset mode_config.mutex
16925 * won't be taken. Unfortunately some probed state like
16926 * audio_codec_enable is still protected by mode_config.mutex, so lock
16927 * it here for now.
16928 */
16929 mutex_lock(&dev->mode_config.mutex);
Maarten Lankhorste2c8b872016-02-16 10:06:14 +010016930 drm_modeset_acquire_init(&ctx, 0);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016931
Maarten Lankhorst73974892016-08-05 23:28:27 +030016932 while (1) {
16933 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16934 if (ret != -EDEADLK)
16935 break;
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016936
Maarten Lankhorste2c8b872016-02-16 10:06:14 +010016937 drm_modeset_backoff(&ctx);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016938 }
16939
Maarten Lankhorst73974892016-08-05 23:28:27 +030016940 if (!ret)
16941 ret = __intel_display_resume(dev, state);
16942
Maarten Lankhorste2c8b872016-02-16 10:06:14 +010016943 drm_modeset_drop_locks(&ctx);
16944 drm_modeset_acquire_fini(&ctx);
Maarten Lankhorstea49c9a2016-02-16 15:27:42 +010016945 mutex_unlock(&dev->mode_config.mutex);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020016946
Chris Wilson08536952016-10-14 13:18:18 +010016947 if (ret)
Maarten Lankhorste2c8b872016-02-16 10:06:14 +010016948 DRM_ERROR("Restoring old state failed with %i\n", ret);
Chris Wilson08536952016-10-14 13:18:18 +010016949 drm_atomic_state_put(state);
Chris Wilson2c7111d2011-03-29 10:40:27 +010016950}
16951
16952void intel_modeset_gem_init(struct drm_device *dev)
16953{
Chris Wilsondc979972016-05-10 14:10:04 +010016954 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080016955 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070016956 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080016957
Chris Wilsondc979972016-05-10 14:10:04 +010016958 intel_init_gt_powersave(dev_priv);
Imre Deakae484342014-03-31 15:10:44 +030016959
Chris Wilson1833b132012-05-09 11:56:28 +010016960 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020016961
Chris Wilson1ee8da62016-05-12 12:43:23 +010016962 intel_setup_overlay(dev_priv);
Jesse Barnes484b41d2014-03-07 08:57:55 -080016963
16964 /*
16965 * Make sure any fbs we allocated at startup are properly
16966 * pinned & fenced. When we do the allocation it's too early
16967 * for this.
16968 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010016969 for_each_crtc(dev, c) {
Chris Wilson058d88c2016-08-15 10:49:06 +010016970 struct i915_vma *vma;
16971
Matt Roper2ff8fde2014-07-08 07:50:07 -070016972 obj = intel_fb_obj(c->primary->fb);
16973 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080016974 continue;
16975
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010016976 mutex_lock(&dev->struct_mutex);
Chris Wilson058d88c2016-08-15 10:49:06 +010016977 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
Ville Syrjälä3465c582016-02-15 22:54:43 +020016978 c->primary->state->rotation);
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010016979 mutex_unlock(&dev->struct_mutex);
Chris Wilson058d88c2016-08-15 10:49:06 +010016980 if (IS_ERR(vma)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080016981 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16982 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100016983 drm_framebuffer_unreference(c->primary->fb);
Daniel Vetter5a21b662016-05-24 17:13:53 +020016984 c->primary->fb = NULL;
Maarten Lankhorst36750f22015-06-01 12:49:54 +020016985 c->primary->crtc = c->primary->state->crtc = NULL;
Daniel Vetter5a21b662016-05-24 17:13:53 +020016986 update_state_fb(c->primary);
Maarten Lankhorst36750f22015-06-01 12:49:54 +020016987 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
Jesse Barnes484b41d2014-03-07 08:57:55 -080016988 }
16989 }
Chris Wilson1ebaa0b2016-06-24 14:00:15 +010016990}
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020016991
Chris Wilson1ebaa0b2016-06-24 14:00:15 +010016992int intel_connector_register(struct drm_connector *connector)
16993{
16994 struct intel_connector *intel_connector = to_intel_connector(connector);
16995 int ret;
16996
16997 ret = intel_backlight_device_register(intel_connector);
16998 if (ret)
16999 goto err;
17000
17001 return 0;
17002
17003err:
17004 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080017005}
17006
Chris Wilsonc191eca2016-06-17 11:40:33 +010017007void intel_connector_unregister(struct drm_connector *connector)
Imre Deak4932e2c2014-02-11 17:12:48 +020017008{
Chris Wilsone63d87c2016-06-17 11:40:34 +010017009 struct intel_connector *intel_connector = to_intel_connector(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020017010
Chris Wilsone63d87c2016-06-17 11:40:34 +010017011 intel_backlight_device_unregister(intel_connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020017012 intel_panel_destroy_backlight(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020017013}
17014
Jesse Barnes79e53942008-11-07 14:24:08 -080017015void intel_modeset_cleanup(struct drm_device *dev)
17016{
Chris Wilsonfac5e232016-07-04 11:34:36 +010017017 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -070017018
Chris Wilsondc979972016-05-10 14:10:04 +010017019 intel_disable_gt_powersave(dev_priv);
Imre Deak2eb52522014-11-19 15:30:05 +020017020
Daniel Vetterfd0c0642013-04-24 11:13:35 +020017021 /*
17022 * Interrupts and polling as the first thing to avoid creating havoc.
Imre Deak2eb52522014-11-19 15:30:05 +020017023 * Too much stuff here (turning of connectors, ...) would
Daniel Vetterfd0c0642013-04-24 11:13:35 +020017024 * experience fancy races otherwise.
17025 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +020017026 intel_irq_uninstall(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070017027
Daniel Vetterfd0c0642013-04-24 11:13:35 +020017028 /*
17029 * Due to the hpd irq storm handling the hotplug work can re-arm the
17030 * poll handlers. Hence disable polling after hpd handling is shut down.
17031 */
Keith Packardf87ea762010-10-03 19:36:26 -070017032 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020017033
Jesse Barnes723bfd72010-10-07 16:01:13 -070017034 intel_unregister_dsm_handler();
17035
Paulo Zanonic937ab3e52016-01-19 11:35:46 -020017036 intel_fbc_global_disable(dev_priv);
Kristian Høgsberg69341a52009-11-11 12:19:17 -050017037
Chris Wilson1630fe72011-07-08 12:22:42 +010017038 /* flush any delayed tasks or pending work */
17039 flush_scheduled_work();
17040
Jesse Barnes79e53942008-11-07 14:24:08 -080017041 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010017042
Chris Wilson1ee8da62016-05-12 12:43:23 +010017043 intel_cleanup_overlay(dev_priv);
Imre Deakae484342014-03-31 15:10:44 +030017044
Chris Wilsondc979972016-05-10 14:10:04 +010017045 intel_cleanup_gt_powersave(dev_priv);
Daniel Vetterf5949142016-01-13 11:55:28 +010017046
17047 intel_teardown_gmbus(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080017048}
17049
Chris Wilsondf0e9242010-09-09 16:20:55 +010017050void intel_connector_attach_encoder(struct intel_connector *connector,
17051 struct intel_encoder *encoder)
17052{
17053 connector->encoder = encoder;
17054 drm_mode_connector_attach_encoder(&connector->base,
17055 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080017056}
Dave Airlie28d52042009-09-21 14:33:58 +100017057
17058/*
17059 * set vga decode state - true == enable VGA decode
17060 */
17061int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17062{
Chris Wilsonfac5e232016-07-04 11:34:36 +010017063 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsona885b3c2013-12-17 14:34:50 +000017064 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100017065 u16 gmch_ctrl;
17066
Chris Wilson75fa0412014-02-07 18:37:02 -020017067 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17068 DRM_ERROR("failed to read control word\n");
17069 return -EIO;
17070 }
17071
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020017072 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17073 return 0;
17074
Dave Airlie28d52042009-09-21 14:33:58 +100017075 if (state)
17076 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17077 else
17078 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020017079
17080 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17081 DRM_ERROR("failed to write control word\n");
17082 return -EIO;
17083 }
17084
Dave Airlie28d52042009-09-21 14:33:58 +100017085 return 0;
17086}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017087
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017088struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030017089
17090 u32 power_well_driver;
17091
Chris Wilson63b66e52013-08-08 15:12:06 +020017092 int num_transcoders;
17093
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017094 struct intel_cursor_error_state {
17095 u32 control;
17096 u32 position;
17097 u32 base;
17098 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010017099 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017100
17101 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020017102 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017103 u32 source;
Imre Deakf301b1e12014-04-18 15:55:04 +030017104 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010017105 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017106
17107 struct intel_plane_error_state {
17108 u32 control;
17109 u32 stride;
17110 u32 size;
17111 u32 pos;
17112 u32 addr;
17113 u32 surface;
17114 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010017115 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020017116
17117 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020017118 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020017119 enum transcoder cpu_transcoder;
17120
17121 u32 conf;
17122
17123 u32 htotal;
17124 u32 hblank;
17125 u32 hsync;
17126 u32 vtotal;
17127 u32 vblank;
17128 u32 vsync;
17129 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017130};
17131
17132struct intel_display_error_state *
Chris Wilsonc0336662016-05-06 15:40:21 +010017133intel_display_capture_error_state(struct drm_i915_private *dev_priv)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017134{
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017135 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020017136 int transcoders[] = {
17137 TRANSCODER_A,
17138 TRANSCODER_B,
17139 TRANSCODER_C,
17140 TRANSCODER_EDP,
17141 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017142 int i;
17143
Chris Wilsonc0336662016-05-06 15:40:21 +010017144 if (INTEL_INFO(dev_priv)->num_pipes == 0)
Chris Wilson63b66e52013-08-08 15:12:06 +020017145 return NULL;
17146
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020017147 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017148 if (error == NULL)
17149 return NULL;
17150
Chris Wilsonc0336662016-05-06 15:40:21 +010017151 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030017152 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17153
Damien Lespiau055e3932014-08-18 13:49:10 +010017154 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020017155 error->pipe[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020017156 __intel_display_power_is_enabled(dev_priv,
17157 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020017158 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020017159 continue;
17160
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030017161 error->cursor[i].control = I915_READ(CURCNTR(i));
17162 error->cursor[i].position = I915_READ(CURPOS(i));
17163 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017164
17165 error->plane[i].control = I915_READ(DSPCNTR(i));
17166 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Chris Wilsonc0336662016-05-06 15:40:21 +010017167 if (INTEL_GEN(dev_priv) <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030017168 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030017169 error->plane[i].pos = I915_READ(DSPPOS(i));
17170 }
Chris Wilsonc0336662016-05-06 15:40:21 +010017171 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
Paulo Zanonica291362013-03-06 20:03:14 -030017172 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc0336662016-05-06 15:40:21 +010017173 if (INTEL_GEN(dev_priv) >= 4) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017174 error->plane[i].surface = I915_READ(DSPSURF(i));
17175 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17176 }
17177
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017178 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e12014-04-18 15:55:04 +030017179
Chris Wilsonc0336662016-05-06 15:40:21 +010017180 if (HAS_GMCH_DISPLAY(dev_priv))
Imre Deakf301b1e12014-04-18 15:55:04 +030017181 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020017182 }
17183
Jani Nikula4d1de972016-03-18 17:05:42 +020017184 /* Note: this does not include DSI transcoders. */
Chris Wilsonc0336662016-05-06 15:40:21 +010017185 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +030017186 if (HAS_DDI(dev_priv))
Chris Wilson63b66e52013-08-08 15:12:06 +020017187 error->num_transcoders++; /* Account for eDP. */
17188
17189 for (i = 0; i < error->num_transcoders; i++) {
17190 enum transcoder cpu_transcoder = transcoders[i];
17191
Imre Deakddf9c532013-11-27 22:02:02 +020017192 error->transcoder[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020017193 __intel_display_power_is_enabled(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020017194 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020017195 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020017196 continue;
17197
Chris Wilson63b66e52013-08-08 15:12:06 +020017198 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17199
17200 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17201 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17202 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17203 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17204 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17205 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17206 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017207 }
17208
17209 return error;
17210}
17211
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017212#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17213
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017214void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017215intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017216 struct drm_device *dev,
17217 struct intel_display_error_state *error)
17218{
Chris Wilsonfac5e232016-07-04 11:34:36 +010017219 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017220 int i;
17221
Chris Wilson63b66e52013-08-08 15:12:06 +020017222 if (!error)
17223 return;
17224
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017225 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020017226 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017227 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030017228 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010017229 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017230 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020017231 err_printf(m, " Power: %s\n",
Jani Nikula87ad3212016-01-14 12:53:34 +020017232 onoff(error->pipe[i].power_domain_on));
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017233 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e12014-04-18 15:55:04 +030017234 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017235
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017236 err_printf(m, "Plane [%d]:\n", i);
17237 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17238 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030017239 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017240 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17241 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030017242 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030017243 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017244 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017245 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017246 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17247 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017248 }
17249
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030017250 err_printf(m, "Cursor [%d]:\n", i);
17251 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17252 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17253 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017254 }
Chris Wilson63b66e52013-08-08 15:12:06 +020017255
17256 for (i = 0; i < error->num_transcoders; i++) {
Jani Nikulada205632016-03-15 21:51:10 +020017257 err_printf(m, "CPU transcoder: %s\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020017258 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020017259 err_printf(m, " Power: %s\n",
Jani Nikula87ad3212016-01-14 12:53:34 +020017260 onoff(error->transcoder[i].power_domain_on));
Chris Wilson63b66e52013-08-08 15:12:06 +020017261 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17262 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17263 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17264 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17265 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17266 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17267 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17268 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000017269}