Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 31 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 34 | #include <drm/drm_edid.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drmP.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
Chris Wilson | 5d723d7 | 2016-08-04 16:32:35 +0100 | [diff] [blame] | 37 | #include "intel_frontbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 38 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 39 | #include "i915_drv.h" |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 40 | #include "i915_gem_dmabuf.h" |
Imre Deak | db18b6a | 2016-03-24 12:41:40 +0200 | [diff] [blame] | 41 | #include "intel_dsi.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 42 | #include "i915_trace.h" |
Xi Ruoyao | 319c1d4 | 2015-03-12 20:16:32 +0800 | [diff] [blame] | 43 | #include <drm/drm_atomic.h> |
Matt Roper | c196e1d | 2015-01-21 16:35:48 -0800 | [diff] [blame] | 44 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 45 | #include <drm/drm_dp_helper.h> |
| 46 | #include <drm/drm_crtc_helper.h> |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 47 | #include <drm/drm_plane_helper.h> |
| 48 | #include <drm/drm_rect.h> |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 49 | #include <linux/dma_remapping.h> |
Alex Goins | fd8e058 | 2015-11-25 18:43:38 -0800 | [diff] [blame] | 50 | #include <linux/reservation.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 51 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 52 | static bool is_mmio_work(struct intel_flip_work *work) |
| 53 | { |
| 54 | return work->mmio_work.func; |
| 55 | } |
| 56 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 57 | /* Primary plane formats for gen <= 3 */ |
Damien Lespiau | 568db4f | 2015-05-12 16:13:18 +0100 | [diff] [blame] | 58 | static const uint32_t i8xx_primary_formats[] = { |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 59 | DRM_FORMAT_C8, |
| 60 | DRM_FORMAT_RGB565, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 61 | DRM_FORMAT_XRGB1555, |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 62 | DRM_FORMAT_XRGB8888, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | /* Primary plane formats for gen >= 4 */ |
Damien Lespiau | 568db4f | 2015-05-12 16:13:18 +0100 | [diff] [blame] | 66 | static const uint32_t i965_primary_formats[] = { |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 67 | DRM_FORMAT_C8, |
| 68 | DRM_FORMAT_RGB565, |
| 69 | DRM_FORMAT_XRGB8888, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 70 | DRM_FORMAT_XBGR8888, |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 71 | DRM_FORMAT_XRGB2101010, |
| 72 | DRM_FORMAT_XBGR2101010, |
| 73 | }; |
| 74 | |
| 75 | static const uint32_t skl_primary_formats[] = { |
| 76 | DRM_FORMAT_C8, |
| 77 | DRM_FORMAT_RGB565, |
| 78 | DRM_FORMAT_XRGB8888, |
| 79 | DRM_FORMAT_XBGR8888, |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 80 | DRM_FORMAT_ARGB8888, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 81 | DRM_FORMAT_ABGR8888, |
| 82 | DRM_FORMAT_XRGB2101010, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 83 | DRM_FORMAT_XBGR2101010, |
Kumar, Mahesh | ea916ea | 2015-09-03 16:17:09 +0530 | [diff] [blame] | 84 | DRM_FORMAT_YUYV, |
| 85 | DRM_FORMAT_YVYU, |
| 86 | DRM_FORMAT_UYVY, |
| 87 | DRM_FORMAT_VYUY, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 90 | /* Cursor formats */ |
| 91 | static const uint32_t intel_cursor_formats[] = { |
| 92 | DRM_FORMAT_ARGB8888, |
| 93 | }; |
| 94 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 96 | struct intel_crtc_state *pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 98 | struct intel_crtc_state *pipe_config); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 99 | |
Jesse Barnes | eb1bfe8 | 2014-02-12 12:26:25 -0800 | [diff] [blame] | 100 | static int intel_framebuffer_init(struct drm_device *dev, |
| 101 | struct intel_framebuffer *ifb, |
| 102 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 103 | struct drm_i915_gem_object *obj); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 104 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
| 105 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 106 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 107 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 108 | struct intel_link_m_n *m_n, |
| 109 | struct intel_link_m_n *m2_n2); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 110 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 111 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 112 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 113 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 114 | const struct intel_crtc_state *pipe_config); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 115 | static void chv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 116 | const struct intel_crtc_state *pipe_config); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 117 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
| 118 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 119 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
| 120 | struct intel_crtc_state *crtc_state); |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
| 122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); |
| 123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
Ville Syrjälä | 4e5ca60 | 2016-05-11 22:44:44 +0300 | [diff] [blame] | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 127 | static int bxt_calc_cdclk(int max_pixclk); |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 128 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 129 | struct intel_limit { |
Ander Conselvan de Oliveira | 4c5def9 | 2016-05-04 12:11:58 +0300 | [diff] [blame] | 130 | struct { |
| 131 | int min, max; |
| 132 | } dot, vco, n, m, m1, m2, p, p1; |
| 133 | |
| 134 | struct { |
| 135 | int dot_limit; |
| 136 | int p2_slow, p2_fast; |
| 137 | } p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 138 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 139 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 140 | /* returns HPLL frequency in kHz */ |
| 141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
| 142 | { |
| 143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
| 144 | |
| 145 | /* Obtain SKU information */ |
| 146 | mutex_lock(&dev_priv->sb_lock); |
| 147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
| 148 | CCK_FUSE_HPLL_FREQ_MASK; |
| 149 | mutex_unlock(&dev_priv->sb_lock); |
| 150 | |
| 151 | return vco_freq[hpll_freq] * 1000; |
| 152 | } |
| 153 | |
Ville Syrjälä | c30fec6 | 2016-03-04 21:43:02 +0200 | [diff] [blame] | 154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
| 155 | const char *name, u32 reg, int ref_freq) |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 156 | { |
| 157 | u32 val; |
| 158 | int divider; |
| 159 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 160 | mutex_lock(&dev_priv->sb_lock); |
| 161 | val = vlv_cck_read(dev_priv, reg); |
| 162 | mutex_unlock(&dev_priv->sb_lock); |
| 163 | |
| 164 | divider = val & CCK_FREQUENCY_VALUES; |
| 165 | |
| 166 | WARN((val & CCK_FREQUENCY_STATUS) != |
| 167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), |
| 168 | "%s change in progress\n", name); |
| 169 | |
Ville Syrjälä | c30fec6 | 2016-03-04 21:43:02 +0200 | [diff] [blame] | 170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
| 171 | } |
| 172 | |
| 173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
| 174 | const char *name, u32 reg) |
| 175 | { |
| 176 | if (dev_priv->hpll_freq == 0) |
| 177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); |
| 178 | |
| 179 | return vlv_get_cck_clock(dev_priv, name, reg, |
| 180 | dev_priv->hpll_freq); |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 181 | } |
| 182 | |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 183 | static int |
| 184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) |
Daniel Vetter | d2acd21 | 2012-10-20 20:57:43 +0200 | [diff] [blame] | 185 | { |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
Daniel Vetter | d2acd21 | 2012-10-20 20:57:43 +0200 | [diff] [blame] | 187 | } |
| 188 | |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 189 | static int |
| 190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 191 | { |
Ville Syrjälä | 19ab4ed | 2016-04-27 17:43:22 +0300 | [diff] [blame] | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
Ville Syrjälä | 35d38d1 | 2016-03-02 17:22:16 +0200 | [diff] [blame] | 193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
| 194 | CCK_DISPLAY_REF_CLOCK_CONTROL); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 195 | } |
| 196 | |
| 197 | static int |
| 198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) |
| 199 | { |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 200 | uint32_t clkcfg; |
| 201 | |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 202 | /* hrawclock is 1/4 the FSB frequency */ |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 203 | clkcfg = I915_READ(CLKCFG); |
| 204 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 205 | case CLKCFG_FSB_400: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 206 | return 100000; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 207 | case CLKCFG_FSB_533: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 208 | return 133333; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 209 | case CLKCFG_FSB_667: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 210 | return 166667; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 211 | case CLKCFG_FSB_800: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 212 | return 200000; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 213 | case CLKCFG_FSB_1067: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 214 | return 266667; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 215 | case CLKCFG_FSB_1333: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 216 | return 333333; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 217 | /* these two are just a guess; one of them might be right */ |
| 218 | case CLKCFG_FSB_1600: |
| 219 | case CLKCFG_FSB_1600_ALT: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 220 | return 400000; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 221 | default: |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 222 | return 133333; |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 223 | } |
| 224 | } |
| 225 | |
Ville Syrjälä | 19ab4ed | 2016-04-27 17:43:22 +0300 | [diff] [blame] | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 227 | { |
| 228 | if (HAS_PCH_SPLIT(dev_priv)) |
| 229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); |
| 230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); |
| 232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) |
| 233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); |
| 234 | else |
| 235 | return; /* no rawclk on other platforms, or no need to know it */ |
| 236 | |
| 237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); |
| 238 | } |
| 239 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
| 241 | { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 243 | return; |
| 244 | |
| 245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", |
| 246 | CCK_CZ_CLOCK_CONTROL); |
| 247 | |
| 248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); |
| 249 | } |
| 250 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 251 | static inline u32 /* units of 100MHz */ |
Ville Syrjälä | 21a727b | 2016-02-17 21:41:10 +0200 | [diff] [blame] | 252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
| 253 | const struct intel_crtc_state *pipe_config) |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 254 | { |
Ville Syrjälä | 21a727b | 2016-02-17 21:41:10 +0200 | [diff] [blame] | 255 | if (HAS_DDI(dev_priv)) |
| 256 | return pipe_config->port_clock; /* SPLL */ |
| 257 | else if (IS_GEN5(dev_priv)) |
| 258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 259 | else |
Ville Syrjälä | 21a727b | 2016-02-17 21:41:10 +0200 | [diff] [blame] | 260 | return 270000; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 261 | } |
| 262 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 264 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 265 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 266 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 267 | .m = { .min = 96, .max = 140 }, |
| 268 | .m1 = { .min = 18, .max = 26 }, |
| 269 | .m2 = { .min = 6, .max = 16 }, |
| 270 | .p = { .min = 4, .max = 128 }, |
| 271 | .p1 = { .min = 2, .max = 33 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 272 | .p2 = { .dot_limit = 165000, |
| 273 | .p2_slow = 4, .p2_fast = 2 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 274 | }; |
| 275 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 277 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 278 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 279 | .n = { .min = 2, .max = 16 }, |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 280 | .m = { .min = 96, .max = 140 }, |
| 281 | .m1 = { .min = 18, .max = 26 }, |
| 282 | .m2 = { .min = 6, .max = 16 }, |
| 283 | .p = { .min = 4, .max = 128 }, |
| 284 | .p1 = { .min = 2, .max = 33 }, |
| 285 | .p2 = { .dot_limit = 165000, |
| 286 | .p2_slow = 4, .p2_fast = 4 }, |
| 287 | }; |
| 288 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 290 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 291 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 292 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 293 | .m = { .min = 96, .max = 140 }, |
| 294 | .m1 = { .min = 18, .max = 26 }, |
| 295 | .m2 = { .min = 6, .max = 16 }, |
| 296 | .p = { .min = 4, .max = 128 }, |
| 297 | .p1 = { .min = 1, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 298 | .p2 = { .dot_limit = 165000, |
| 299 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 300 | }; |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 301 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 303 | .dot = { .min = 20000, .max = 400000 }, |
| 304 | .vco = { .min = 1400000, .max = 2800000 }, |
| 305 | .n = { .min = 1, .max = 6 }, |
| 306 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 4f7dfb6 | 2013-02-13 22:20:22 +0100 | [diff] [blame] | 307 | .m1 = { .min = 8, .max = 18 }, |
| 308 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 309 | .p = { .min = 5, .max = 80 }, |
| 310 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 311 | .p2 = { .dot_limit = 200000, |
| 312 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 313 | }; |
| 314 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 316 | .dot = { .min = 20000, .max = 400000 }, |
| 317 | .vco = { .min = 1400000, .max = 2800000 }, |
| 318 | .n = { .min = 1, .max = 6 }, |
| 319 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 53a7d2d | 2013-02-13 22:20:21 +0100 | [diff] [blame] | 320 | .m1 = { .min = 8, .max = 18 }, |
| 321 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 322 | .p = { .min = 7, .max = 98 }, |
| 323 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 324 | .p2 = { .dot_limit = 112000, |
| 325 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 326 | }; |
| 327 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 328 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 330 | .dot = { .min = 25000, .max = 270000 }, |
| 331 | .vco = { .min = 1750000, .max = 3500000}, |
| 332 | .n = { .min = 1, .max = 4 }, |
| 333 | .m = { .min = 104, .max = 138 }, |
| 334 | .m1 = { .min = 17, .max = 23 }, |
| 335 | .m2 = { .min = 5, .max = 11 }, |
| 336 | .p = { .min = 10, .max = 30 }, |
| 337 | .p1 = { .min = 1, .max = 3}, |
| 338 | .p2 = { .dot_limit = 270000, |
| 339 | .p2_slow = 10, |
| 340 | .p2_fast = 10 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 341 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 342 | }; |
| 343 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 345 | .dot = { .min = 22000, .max = 400000 }, |
| 346 | .vco = { .min = 1750000, .max = 3500000}, |
| 347 | .n = { .min = 1, .max = 4 }, |
| 348 | .m = { .min = 104, .max = 138 }, |
| 349 | .m1 = { .min = 16, .max = 23 }, |
| 350 | .m2 = { .min = 5, .max = 11 }, |
| 351 | .p = { .min = 5, .max = 80 }, |
| 352 | .p1 = { .min = 1, .max = 8}, |
| 353 | .p2 = { .dot_limit = 165000, |
| 354 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 355 | }; |
| 356 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 358 | .dot = { .min = 20000, .max = 115000 }, |
| 359 | .vco = { .min = 1750000, .max = 3500000 }, |
| 360 | .n = { .min = 1, .max = 3 }, |
| 361 | .m = { .min = 104, .max = 138 }, |
| 362 | .m1 = { .min = 17, .max = 23 }, |
| 363 | .m2 = { .min = 5, .max = 11 }, |
| 364 | .p = { .min = 28, .max = 112 }, |
| 365 | .p1 = { .min = 2, .max = 8 }, |
| 366 | .p2 = { .dot_limit = 0, |
| 367 | .p2_slow = 14, .p2_fast = 14 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 368 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 369 | }; |
| 370 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 372 | .dot = { .min = 80000, .max = 224000 }, |
| 373 | .vco = { .min = 1750000, .max = 3500000 }, |
| 374 | .n = { .min = 1, .max = 3 }, |
| 375 | .m = { .min = 104, .max = 138 }, |
| 376 | .m1 = { .min = 17, .max = 23 }, |
| 377 | .m2 = { .min = 5, .max = 11 }, |
| 378 | .p = { .min = 14, .max = 42 }, |
| 379 | .p1 = { .min = 2, .max = 6 }, |
| 380 | .p2 = { .dot_limit = 0, |
| 381 | .p2_slow = 7, .p2_fast = 7 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 382 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 383 | }; |
| 384 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 386 | .dot = { .min = 20000, .max = 400000}, |
| 387 | .vco = { .min = 1700000, .max = 3500000 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 388 | /* Pineview's Ncounter is a ring counter */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 389 | .n = { .min = 3, .max = 6 }, |
| 390 | .m = { .min = 2, .max = 256 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 392 | .m1 = { .min = 0, .max = 0 }, |
| 393 | .m2 = { .min = 0, .max = 254 }, |
| 394 | .p = { .min = 5, .max = 80 }, |
| 395 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 396 | .p2 = { .dot_limit = 200000, |
| 397 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 398 | }; |
| 399 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 401 | .dot = { .min = 20000, .max = 400000 }, |
| 402 | .vco = { .min = 1700000, .max = 3500000 }, |
| 403 | .n = { .min = 3, .max = 6 }, |
| 404 | .m = { .min = 2, .max = 256 }, |
| 405 | .m1 = { .min = 0, .max = 0 }, |
| 406 | .m2 = { .min = 0, .max = 254 }, |
| 407 | .p = { .min = 7, .max = 112 }, |
| 408 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 409 | .p2 = { .dot_limit = 112000, |
| 410 | .p2_slow = 14, .p2_fast = 14 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 411 | }; |
| 412 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 413 | /* Ironlake / Sandybridge |
| 414 | * |
| 415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 416 | * the range value for them is (actual_value - 2). |
| 417 | */ |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 419 | .dot = { .min = 25000, .max = 350000 }, |
| 420 | .vco = { .min = 1760000, .max = 3510000 }, |
| 421 | .n = { .min = 1, .max = 5 }, |
| 422 | .m = { .min = 79, .max = 127 }, |
| 423 | .m1 = { .min = 12, .max = 22 }, |
| 424 | .m2 = { .min = 5, .max = 9 }, |
| 425 | .p = { .min = 5, .max = 80 }, |
| 426 | .p1 = { .min = 1, .max = 8 }, |
| 427 | .p2 = { .dot_limit = 225000, |
| 428 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 429 | }; |
| 430 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 432 | .dot = { .min = 25000, .max = 350000 }, |
| 433 | .vco = { .min = 1760000, .max = 3510000 }, |
| 434 | .n = { .min = 1, .max = 3 }, |
| 435 | .m = { .min = 79, .max = 118 }, |
| 436 | .m1 = { .min = 12, .max = 22 }, |
| 437 | .m2 = { .min = 5, .max = 9 }, |
| 438 | .p = { .min = 28, .max = 112 }, |
| 439 | .p1 = { .min = 2, .max = 8 }, |
| 440 | .p2 = { .dot_limit = 225000, |
| 441 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 442 | }; |
| 443 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 445 | .dot = { .min = 25000, .max = 350000 }, |
| 446 | .vco = { .min = 1760000, .max = 3510000 }, |
| 447 | .n = { .min = 1, .max = 3 }, |
| 448 | .m = { .min = 79, .max = 127 }, |
| 449 | .m1 = { .min = 12, .max = 22 }, |
| 450 | .m2 = { .min = 5, .max = 9 }, |
| 451 | .p = { .min = 14, .max = 56 }, |
| 452 | .p1 = { .min = 2, .max = 8 }, |
| 453 | .p2 = { .dot_limit = 225000, |
| 454 | .p2_slow = 7, .p2_fast = 7 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 455 | }; |
| 456 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 457 | /* LVDS 100mhz refclk limits. */ |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 459 | .dot = { .min = 25000, .max = 350000 }, |
| 460 | .vco = { .min = 1760000, .max = 3510000 }, |
| 461 | .n = { .min = 1, .max = 2 }, |
| 462 | .m = { .min = 79, .max = 126 }, |
| 463 | .m1 = { .min = 12, .max = 22 }, |
| 464 | .m2 = { .min = 5, .max = 9 }, |
| 465 | .p = { .min = 28, .max = 112 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 466 | .p1 = { .min = 2, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 467 | .p2 = { .dot_limit = 225000, |
| 468 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 469 | }; |
| 470 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 472 | .dot = { .min = 25000, .max = 350000 }, |
| 473 | .vco = { .min = 1760000, .max = 3510000 }, |
| 474 | .n = { .min = 1, .max = 3 }, |
| 475 | .m = { .min = 79, .max = 126 }, |
| 476 | .m1 = { .min = 12, .max = 22 }, |
| 477 | .m2 = { .min = 5, .max = 9 }, |
| 478 | .p = { .min = 14, .max = 42 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 479 | .p1 = { .min = 2, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 480 | .p2 = { .dot_limit = 225000, |
| 481 | .p2_slow = 7, .p2_fast = 7 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 482 | }; |
| 483 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 484 | static const struct intel_limit intel_limits_vlv = { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 485 | /* |
| 486 | * These are the data rate limits (measured in fast clocks) |
| 487 | * since those are the strictest limits we have. The fast |
| 488 | * clock and actual rate limits are more relaxed, so checking |
| 489 | * them would make no difference. |
| 490 | */ |
| 491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
Daniel Vetter | 75e5398 | 2013-04-18 21:10:43 +0200 | [diff] [blame] | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 493 | .n = { .min = 1, .max = 7 }, |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 494 | .m1 = { .min = 2, .max = 3 }, |
| 495 | .m2 = { .min = 11, .max = 156 }, |
Ville Syrjälä | b99ab66 | 2013-09-24 21:26:26 +0300 | [diff] [blame] | 496 | .p1 = { .min = 2, .max = 3 }, |
Ville Syrjälä | 5fdc9c49 | 2013-09-24 21:26:29 +0300 | [diff] [blame] | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 498 | }; |
| 499 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 500 | static const struct intel_limit intel_limits_chv = { |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 501 | /* |
| 502 | * These are the data rate limits (measured in fast clocks) |
| 503 | * since those are the strictest limits we have. The fast |
| 504 | * clock and actual rate limits are more relaxed, so checking |
| 505 | * them would make no difference. |
| 506 | */ |
| 507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
Ville Syrjälä | 17fe102 | 2015-02-26 21:01:52 +0200 | [diff] [blame] | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 509 | .n = { .min = 1, .max = 1 }, |
| 510 | .m1 = { .min = 2, .max = 2 }, |
| 511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
| 512 | .p1 = { .min = 2, .max = 4 }, |
| 513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
| 514 | }; |
| 515 | |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 516 | static const struct intel_limit intel_limits_bxt = { |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 517 | /* FIXME: find real dot limits */ |
| 518 | .dot = { .min = 0, .max = INT_MAX }, |
Vandana Kannan | e629255 | 2015-07-01 17:02:57 +0530 | [diff] [blame] | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 520 | .n = { .min = 1, .max = 1 }, |
| 521 | .m1 = { .min = 2, .max = 2 }, |
| 522 | /* FIXME: find real m2 limits */ |
| 523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, |
| 524 | .p1 = { .min = 2, .max = 4 }, |
| 525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, |
| 526 | }; |
| 527 | |
Ander Conselvan de Oliveira | cdba954 | 2015-06-01 12:49:51 +0200 | [diff] [blame] | 528 | static bool |
| 529 | needs_modeset(struct drm_crtc_state *state) |
| 530 | { |
Maarten Lankhorst | fc59666 | 2015-07-21 13:28:57 +0200 | [diff] [blame] | 531 | return drm_atomic_crtc_needs_modeset(state); |
Ander Conselvan de Oliveira | cdba954 | 2015-06-01 12:49:51 +0200 | [diff] [blame] | 532 | } |
| 533 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 534 | /* |
| 535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), |
| 536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast |
| 537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. |
| 538 | * The helpers' return value is the rate of the clock that is fed to the |
| 539 | * display engine's pipe which can be the above fast dot clock rate or a |
| 540 | * divided-down version of it. |
| 541 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 544 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 545 | clock->m = clock->m2 + 2; |
| 546 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 548 | return 0; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 551 | |
| 552 | return clock->dot; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 553 | } |
| 554 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
| 556 | { |
| 557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
| 558 | } |
| 559 | |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 561 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 562 | clock->m = i9xx_dpll_compute_m(clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 563 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 565 | return 0; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
| 567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 568 | |
| 569 | return clock->dot; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 570 | } |
| 571 | |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
Imre Deak | 589eca6 | 2015-06-22 23:35:50 +0300 | [diff] [blame] | 573 | { |
| 574 | clock->m = clock->m1 * clock->m2; |
| 575 | clock->p = clock->p1 * clock->p2; |
| 576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 577 | return 0; |
Imre Deak | 589eca6 | 2015-06-22 23:35:50 +0300 | [diff] [blame] | 578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 580 | |
| 581 | return clock->dot / 5; |
Imre Deak | 589eca6 | 2015-06-22 23:35:50 +0300 | [diff] [blame] | 582 | } |
| 583 | |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 585 | { |
| 586 | clock->m = clock->m1 * clock->m2; |
| 587 | clock->p = clock->p1 * clock->p2; |
| 588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 589 | return 0; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
| 591 | clock->n << 22); |
| 592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 593 | |
| 594 | return clock->dot / 5; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 595 | } |
| 596 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 598 | /** |
| 599 | * Returns whether the given set of divisors are valid for a given refclk with |
| 600 | * the given connectors. |
| 601 | */ |
| 602 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 603 | static bool intel_PLL_is_valid(struct drm_device *dev, |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 604 | const struct intel_limit *limit, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 605 | const struct dpll *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 606 | { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 608 | INTELPllInvalid("n out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 610 | INTELPllInvalid("p1 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 612 | INTELPllInvalid("m2 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 614 | INTELPllInvalid("m1 out of range\n"); |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 615 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 616 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
| 617 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 618 | if (clock->m1 <= clock->m2) |
| 619 | INTELPllInvalid("m1 <= m2\n"); |
| 620 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 621 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 623 | INTELPllInvalid("p out of range\n"); |
| 624 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 625 | INTELPllInvalid("m out of range\n"); |
| 626 | } |
| 627 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 629 | INTELPllInvalid("vco out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 631 | * connector, etc., rather than just a single range. |
| 632 | */ |
| 633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 634 | INTELPllInvalid("dot out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 635 | |
| 636 | return true; |
| 637 | } |
| 638 | |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 639 | static int |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 640 | i9xx_select_p2_div(const struct intel_limit *limit, |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 641 | const struct intel_crtc_state *crtc_state, |
| 642 | int target) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 643 | { |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 644 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 645 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 646 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 647 | /* |
Daniel Vetter | a210b02 | 2012-11-26 17:22:08 +0100 | [diff] [blame] | 648 | * For LVDS just rely on its current settings for dual-channel. |
| 649 | * We haven't figured out how to reliably set up different |
| 650 | * single/dual channel state, if we even can. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 651 | */ |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 652 | if (intel_is_dual_link_lvds(dev)) |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 653 | return limit->p2.p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 654 | else |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 655 | return limit->p2.p2_slow; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 656 | } else { |
| 657 | if (target < limit->p2.dot_limit) |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 658 | return limit->p2.p2_slow; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 659 | else |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 660 | return limit->p2.p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | } |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 662 | } |
| 663 | |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 664 | /* |
| 665 | * Returns a set of divisors for the desired target clock with the given |
| 666 | * refclk, or FALSE. The returned values represent the clock equation: |
| 667 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 668 | * |
| 669 | * Target and reference clocks are specified in kHz. |
| 670 | * |
| 671 | * If match_clock is provided, then best_clock P divider must match the P |
| 672 | * divider from @match_clock used for LVDS downclocking. |
| 673 | */ |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 674 | static bool |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 675 | i9xx_find_best_dpll(const struct intel_limit *limit, |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 676 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 677 | int target, int refclk, struct dpll *match_clock, |
| 678 | struct dpll *best_clock) |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 679 | { |
| 680 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 681 | struct dpll clock; |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 682 | int err = target; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 683 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 684 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 685 | |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 686 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 687 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 688 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 689 | clock.m1++) { |
| 690 | for (clock.m2 = limit->m2.min; |
| 691 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | c0efc38 | 2013-06-03 20:56:24 +0200 | [diff] [blame] | 692 | if (clock.m2 >= clock.m1) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 693 | break; |
| 694 | for (clock.n = limit->n.min; |
| 695 | clock.n <= limit->n.max; clock.n++) { |
| 696 | for (clock.p1 = limit->p1.min; |
| 697 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 698 | int this_err; |
| 699 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 700 | i9xx_calc_dpll_params(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 701 | if (!intel_PLL_is_valid(dev, limit, |
| 702 | &clock)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 703 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 704 | if (match_clock && |
| 705 | clock.p != match_clock->p) |
| 706 | continue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 707 | |
| 708 | this_err = abs(clock.dot - target); |
| 709 | if (this_err < err) { |
| 710 | *best_clock = clock; |
| 711 | err = this_err; |
| 712 | } |
| 713 | } |
| 714 | } |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | return (err != target); |
| 719 | } |
| 720 | |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 721 | /* |
| 722 | * Returns a set of divisors for the desired target clock with the given |
| 723 | * refclk, or FALSE. The returned values represent the clock equation: |
| 724 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 725 | * |
| 726 | * Target and reference clocks are specified in kHz. |
| 727 | * |
| 728 | * If match_clock is provided, then best_clock P divider must match the P |
| 729 | * divider from @match_clock used for LVDS downclocking. |
| 730 | */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 731 | static bool |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 732 | pnv_find_best_dpll(const struct intel_limit *limit, |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 733 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 734 | int target, int refclk, struct dpll *match_clock, |
| 735 | struct dpll *best_clock) |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 736 | { |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 738 | struct dpll clock; |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 739 | int err = target; |
| 740 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 741 | memset(best_clock, 0, sizeof(*best_clock)); |
| 742 | |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 743 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 744 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 745 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 746 | clock.m1++) { |
| 747 | for (clock.m2 = limit->m2.min; |
| 748 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 749 | for (clock.n = limit->n.min; |
| 750 | clock.n <= limit->n.max; clock.n++) { |
| 751 | for (clock.p1 = limit->p1.min; |
| 752 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 753 | int this_err; |
| 754 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 755 | pnv_calc_dpll_params(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 756 | if (!intel_PLL_is_valid(dev, limit, |
| 757 | &clock)) |
| 758 | continue; |
| 759 | if (match_clock && |
| 760 | clock.p != match_clock->p) |
| 761 | continue; |
| 762 | |
| 763 | this_err = abs(clock.dot - target); |
| 764 | if (this_err < err) { |
| 765 | *best_clock = clock; |
| 766 | err = this_err; |
| 767 | } |
| 768 | } |
| 769 | } |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | return (err != target); |
| 774 | } |
| 775 | |
Ander Conselvan de Oliveira | 997c030 | 2016-03-21 18:00:12 +0200 | [diff] [blame] | 776 | /* |
| 777 | * Returns a set of divisors for the desired target clock with the given |
| 778 | * refclk, or FALSE. The returned values represent the clock equation: |
| 779 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 780 | * |
| 781 | * Target and reference clocks are specified in kHz. |
| 782 | * |
| 783 | * If match_clock is provided, then best_clock P divider must match the P |
| 784 | * divider from @match_clock used for LVDS downclocking. |
Ander Conselvan de Oliveira | 997c030 | 2016-03-21 18:00:12 +0200 | [diff] [blame] | 785 | */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 786 | static bool |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 787 | g4x_find_best_dpll(const struct intel_limit *limit, |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 788 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 789 | int target, int refclk, struct dpll *match_clock, |
| 790 | struct dpll *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 791 | { |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 792 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 793 | struct dpll clock; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 794 | int max_n; |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 795 | bool found = false; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 796 | /* approximately equals target * 0.00585 */ |
| 797 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 798 | |
| 799 | memset(best_clock, 0, sizeof(*best_clock)); |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 800 | |
| 801 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 802 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 803 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 804 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 805 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 806 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 807 | for (clock.m1 = limit->m1.max; |
| 808 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 809 | for (clock.m2 = limit->m2.max; |
| 810 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 811 | for (clock.p1 = limit->p1.max; |
| 812 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 813 | int this_err; |
| 814 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 815 | i9xx_calc_dpll_params(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 816 | if (!intel_PLL_is_valid(dev, limit, |
| 817 | &clock)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 818 | continue; |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 819 | |
| 820 | this_err = abs(clock.dot - target); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 821 | if (this_err < err_most) { |
| 822 | *best_clock = clock; |
| 823 | err_most = this_err; |
| 824 | max_n = clock.n; |
| 825 | found = true; |
| 826 | } |
| 827 | } |
| 828 | } |
| 829 | } |
| 830 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 831 | return found; |
| 832 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 833 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 834 | /* |
| 835 | * Check if the calculated PLL configuration is more optimal compared to the |
| 836 | * best configuration and error found so far. Return the calculated error. |
| 837 | */ |
| 838 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 839 | const struct dpll *calculated_clock, |
| 840 | const struct dpll *best_clock, |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 841 | unsigned int best_error_ppm, |
| 842 | unsigned int *error_ppm) |
| 843 | { |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 844 | /* |
| 845 | * For CHV ignore the error and consider only the P value. |
| 846 | * Prefer a bigger P value based on HW requirements. |
| 847 | */ |
| 848 | if (IS_CHERRYVIEW(dev)) { |
| 849 | *error_ppm = 0; |
| 850 | |
| 851 | return calculated_clock->p > best_clock->p; |
| 852 | } |
| 853 | |
Imre Deak | 24be4e4 | 2015-03-17 11:40:04 +0200 | [diff] [blame] | 854 | if (WARN_ON_ONCE(!target_freq)) |
| 855 | return false; |
| 856 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 857 | *error_ppm = div_u64(1000000ULL * |
| 858 | abs(target_freq - calculated_clock->dot), |
| 859 | target_freq); |
| 860 | /* |
| 861 | * Prefer a better P value over a better (smaller) error if the error |
| 862 | * is small. Ensure this preference for future configurations too by |
| 863 | * setting the error to 0. |
| 864 | */ |
| 865 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { |
| 866 | *error_ppm = 0; |
| 867 | |
| 868 | return true; |
| 869 | } |
| 870 | |
| 871 | return *error_ppm + 10 < best_error_ppm; |
| 872 | } |
| 873 | |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 874 | /* |
| 875 | * Returns a set of divisors for the desired target clock with the given |
| 876 | * refclk, or FALSE. The returned values represent the clock equation: |
| 877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 878 | */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 879 | static bool |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 880 | vlv_find_best_dpll(const struct intel_limit *limit, |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 881 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 882 | int target, int refclk, struct dpll *match_clock, |
| 883 | struct dpll *best_clock) |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 884 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | a919ff1 | 2014-10-20 13:46:43 +0300 | [diff] [blame] | 886 | struct drm_device *dev = crtc->base.dev; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 887 | struct dpll clock; |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 888 | unsigned int bestppm = 1000000; |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 889 | /* min update 19.2 MHz */ |
| 890 | int max_n = min(limit->n.max, refclk / 19200); |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 891 | bool found = false; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 892 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 893 | target *= 5; /* fast clock */ |
| 894 | |
| 895 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 896 | |
| 897 | /* based on hardware requirement, prefer smaller n to precision */ |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 898 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Ville Syrjälä | 811bbf0 | 2013-09-24 21:26:25 +0300 | [diff] [blame] | 899 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
Ville Syrjälä | 889059d | 2013-09-24 21:26:27 +0300 | [diff] [blame] | 900 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
Ville Syrjälä | c1a9ae4 | 2013-09-24 21:26:23 +0300 | [diff] [blame] | 901 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 902 | clock.p = clock.p1 * clock.p2; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 903 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 904 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 905 | unsigned int ppm; |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 906 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 907 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
| 908 | refclk * clock.m1); |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 909 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 910 | vlv_calc_dpll_params(refclk, &clock); |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 911 | |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 912 | if (!intel_PLL_is_valid(dev, limit, |
| 913 | &clock)) |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 914 | continue; |
| 915 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 916 | if (!vlv_PLL_is_optimal(dev, target, |
| 917 | &clock, |
| 918 | best_clock, |
| 919 | bestppm, &ppm)) |
| 920 | continue; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 921 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 922 | *best_clock = clock; |
| 923 | bestppm = ppm; |
| 924 | found = true; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 925 | } |
| 926 | } |
| 927 | } |
| 928 | } |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 929 | |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 930 | return found; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 931 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 932 | |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 933 | /* |
| 934 | * Returns a set of divisors for the desired target clock with the given |
| 935 | * refclk, or FALSE. The returned values represent the clock equation: |
| 936 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 937 | */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 938 | static bool |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 939 | chv_find_best_dpll(const struct intel_limit *limit, |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 940 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 941 | int target, int refclk, struct dpll *match_clock, |
| 942 | struct dpll *best_clock) |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 943 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 944 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | a919ff1 | 2014-10-20 13:46:43 +0300 | [diff] [blame] | 945 | struct drm_device *dev = crtc->base.dev; |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 946 | unsigned int best_error_ppm; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 947 | struct dpll clock; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 948 | uint64_t m2; |
| 949 | int found = false; |
| 950 | |
| 951 | memset(best_clock, 0, sizeof(*best_clock)); |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 952 | best_error_ppm = 1000000; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 953 | |
| 954 | /* |
| 955 | * Based on hardware doc, the n always set to 1, and m1 always |
| 956 | * set to 2. If requires to support 200Mhz refclk, we need to |
| 957 | * revisit this because n may not 1 anymore. |
| 958 | */ |
| 959 | clock.n = 1, clock.m1 = 2; |
| 960 | target *= 5; /* fast clock */ |
| 961 | |
| 962 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 963 | for (clock.p2 = limit->p2.p2_fast; |
| 964 | clock.p2 >= limit->p2.p2_slow; |
| 965 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 966 | unsigned int error_ppm; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 967 | |
| 968 | clock.p = clock.p1 * clock.p2; |
| 969 | |
| 970 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * |
| 971 | clock.n) << 22, refclk * clock.m1); |
| 972 | |
| 973 | if (m2 > INT_MAX/clock.m1) |
| 974 | continue; |
| 975 | |
| 976 | clock.m2 = m2; |
| 977 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 978 | chv_calc_dpll_params(refclk, &clock); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 979 | |
| 980 | if (!intel_PLL_is_valid(dev, limit, &clock)) |
| 981 | continue; |
| 982 | |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 983 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
| 984 | best_error_ppm, &error_ppm)) |
| 985 | continue; |
| 986 | |
| 987 | *best_clock = clock; |
| 988 | best_error_ppm = error_ppm; |
| 989 | found = true; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 990 | } |
| 991 | } |
| 992 | |
| 993 | return found; |
| 994 | } |
| 995 | |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 996 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 997 | struct dpll *best_clock) |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 998 | { |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 999 | int refclk = 100000; |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 1000 | const struct intel_limit *limit = &intel_limits_bxt; |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 1001 | |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 1002 | return chv_find_best_dpll(limit, crtc_state, |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 1003 | target_clock, refclk, NULL, best_clock); |
| 1004 | } |
| 1005 | |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1006 | bool intel_crtc_active(struct drm_crtc *crtc) |
| 1007 | { |
| 1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1009 | |
| 1010 | /* Be paranoid as we can arrive here with only partial |
| 1011 | * state retrieved from the hardware during setup. |
| 1012 | * |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1013 | * We can ditch the adjusted_mode.crtc_clock check as soon |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1014 | * as Haswell has gained clock readout/fastboot support. |
| 1015 | * |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 1016 | * We can ditch the crtc->primary->fb check as soon as we can |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1017 | * properly reconstruct framebuffers. |
Matt Roper | c3d1f43 | 2015-03-09 10:19:23 -0700 | [diff] [blame] | 1018 | * |
| 1019 | * FIXME: The intel_crtc->active here should be switched to |
| 1020 | * crtc->state->active once we have proper CRTC states wired up |
| 1021 | * for atomic. |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1022 | */ |
Matt Roper | c3d1f43 | 2015-03-09 10:19:23 -0700 | [diff] [blame] | 1023 | return intel_crtc->active && crtc->primary->state->fb && |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1024 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1025 | } |
| 1026 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 1027 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 1028 | enum pipe pipe) |
| 1029 | { |
| 1030 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1032 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1033 | return intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 1034 | } |
| 1035 | |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1036 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
| 1037 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1038 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1039 | i915_reg_t reg = PIPEDSL(pipe); |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1040 | u32 line1, line2; |
| 1041 | u32 line_mask; |
| 1042 | |
| 1043 | if (IS_GEN2(dev)) |
| 1044 | line_mask = DSL_LINEMASK_GEN2; |
| 1045 | else |
| 1046 | line_mask = DSL_LINEMASK_GEN3; |
| 1047 | |
| 1048 | line1 = I915_READ(reg) & line_mask; |
Daniel Vetter | 6adfb1e | 2015-07-07 09:10:40 +0200 | [diff] [blame] | 1049 | msleep(5); |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1050 | line2 = I915_READ(reg) & line_mask; |
| 1051 | |
| 1052 | return line1 == line2; |
| 1053 | } |
| 1054 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1055 | /* |
| 1056 | * intel_wait_for_pipe_off - wait for pipe to turn off |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1057 | * @crtc: crtc whose pipe to wait for |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1058 | * |
| 1059 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 1060 | * spinning on the vblank interrupt status bit, since we won't actually |
| 1061 | * see an interrupt when the pipe is disabled. |
| 1062 | * |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1063 | * On Gen4 and above: |
| 1064 | * wait for the pipe register state bit to turn off |
| 1065 | * |
| 1066 | * Otherwise: |
| 1067 | * wait for the display line value to settle (it usually |
| 1068 | * ends up stopping at the start of the next frame). |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1069 | * |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1070 | */ |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1071 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1072 | { |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1073 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1074 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1075 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1076 | enum pipe pipe = crtc->pipe; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1077 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1078 | if (INTEL_INFO(dev)->gen >= 4) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1079 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1080 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1081 | /* Wait for the Pipe State to go off */ |
Chris Wilson | b8511f5 | 2016-06-30 15:32:53 +0100 | [diff] [blame] | 1082 | if (intel_wait_for_register(dev_priv, |
| 1083 | reg, I965_PIPECONF_ACTIVE, 0, |
| 1084 | 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 1085 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1086 | } else { |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1087 | /* Wait for the display line to settle */ |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1088 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 1089 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1090 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1091 | } |
| 1092 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1093 | /* Only for pre-ILK configs */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1094 | void assert_pll(struct drm_i915_private *dev_priv, |
| 1095 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1096 | { |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1097 | u32 val; |
| 1098 | bool cur_state; |
| 1099 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1100 | val = I915_READ(DPLL(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1101 | cur_state = !!(val & DPLL_VCO_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1102 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1103 | "PLL state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1104 | onoff(state), onoff(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1105 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1106 | |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1107 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
Lionel Landwerlin | 8563b1e | 2016-03-16 10:57:14 +0000 | [diff] [blame] | 1108 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1109 | { |
| 1110 | u32 val; |
| 1111 | bool cur_state; |
| 1112 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1113 | mutex_lock(&dev_priv->sb_lock); |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1114 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1115 | mutex_unlock(&dev_priv->sb_lock); |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1116 | |
| 1117 | cur_state = val & DSI_PLL_VCO_EN; |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1118 | I915_STATE_WARN(cur_state != state, |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1119 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1120 | onoff(state), onoff(cur_state)); |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1121 | } |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1122 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 1124 | enum pipe pipe, bool state) |
| 1125 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1126 | bool cur_state; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1127 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1128 | pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1129 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1130 | if (HAS_DDI(dev_priv)) { |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1131 | /* DDI does not have a specific FDI_TX register */ |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1132 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1133 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1134 | } else { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1135 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1136 | cur_state = !!(val & FDI_TX_ENABLE); |
| 1137 | } |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1138 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1139 | "FDI TX state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1140 | onoff(state), onoff(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1141 | } |
| 1142 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 1143 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 1144 | |
| 1145 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 1146 | enum pipe pipe, bool state) |
| 1147 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1148 | u32 val; |
| 1149 | bool cur_state; |
| 1150 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1151 | val = I915_READ(FDI_RX_CTL(pipe)); |
Paulo Zanoni | d63fa0d | 2012-11-20 13:27:35 -0200 | [diff] [blame] | 1152 | cur_state = !!(val & FDI_RX_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1153 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1154 | "FDI RX state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1155 | onoff(state), onoff(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1156 | } |
| 1157 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 1158 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 1159 | |
| 1160 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 1161 | enum pipe pipe) |
| 1162 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1163 | u32 val; |
| 1164 | |
| 1165 | /* ILK FDI PLL is always enabled */ |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 1166 | if (IS_GEN5(dev_priv)) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1167 | return; |
| 1168 | |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1169 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1170 | if (HAS_DDI(dev_priv)) |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1171 | return; |
| 1172 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1173 | val = I915_READ(FDI_TX_CTL(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1174 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1175 | } |
| 1176 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 1178 | enum pipe pipe, bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1179 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1180 | u32 val; |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1181 | bool cur_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1182 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1183 | val = I915_READ(FDI_RX_CTL(pipe)); |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1184 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1185 | I915_STATE_WARN(cur_state != state, |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1186 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1187 | onoff(state), onoff(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1188 | } |
| 1189 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 1190 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 1191 | enum pipe pipe) |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1192 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1193 | struct drm_device *dev = &dev_priv->drm; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1194 | i915_reg_t pp_reg; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1195 | u32 val; |
| 1196 | enum pipe panel_pipe = PIPE_A; |
Thomas Jarosch | 0de3b48 | 2011-08-25 15:37:45 +0200 | [diff] [blame] | 1197 | bool locked = true; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1198 | |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1199 | if (WARN_ON(HAS_DDI(dev))) |
| 1200 | return; |
| 1201 | |
| 1202 | if (HAS_PCH_SPLIT(dev)) { |
| 1203 | u32 port_sel; |
| 1204 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 1205 | pp_reg = PP_CONTROL(0); |
| 1206 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1207 | |
| 1208 | if (port_sel == PANEL_PORT_SELECT_LVDS && |
| 1209 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) |
| 1210 | panel_pipe = PIPE_B; |
| 1211 | /* XXX: else fix for eDP */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1212 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1213 | /* presumably write lock depends on pipe, not port select */ |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 1214 | pp_reg = PP_CONTROL(pipe); |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1215 | panel_pipe = pipe; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1216 | } else { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 1217 | pp_reg = PP_CONTROL(0); |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1218 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
| 1219 | panel_pipe = PIPE_B; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1220 | } |
| 1221 | |
| 1222 | val = I915_READ(pp_reg); |
| 1223 | if (!(val & PANEL_POWER_ON) || |
Jani Nikula | ec49ba2 | 2014-08-21 15:06:25 +0300 | [diff] [blame] | 1224 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1225 | locked = false; |
| 1226 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1227 | I915_STATE_WARN(panel_pipe == pipe && locked, |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1228 | "panel assertion failure, pipe %c regs locked\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1229 | pipe_name(pipe)); |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1230 | } |
| 1231 | |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1232 | static void assert_cursor(struct drm_i915_private *dev_priv, |
| 1233 | enum pipe pipe, bool state) |
| 1234 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1235 | struct drm_device *dev = &dev_priv->drm; |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1236 | bool cur_state; |
| 1237 | |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1238 | if (IS_845G(dev) || IS_I865G(dev)) |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 1239 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1240 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 1241 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1242 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1243 | I915_STATE_WARN(cur_state != state, |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1244 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1245 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1246 | } |
| 1247 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
| 1248 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
| 1249 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1250 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 1251 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1252 | { |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1253 | bool cur_state; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1254 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1255 | pipe); |
Imre Deak | 4feed0e | 2016-02-12 18:55:14 +0200 | [diff] [blame] | 1256 | enum intel_display_power_domain power_domain; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1257 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 1258 | /* if we need the pipe quirk it must be always on */ |
| 1259 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1260 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Daniel Vetter | 8e63678 | 2012-01-22 01:36:48 +0100 | [diff] [blame] | 1261 | state = true; |
| 1262 | |
Imre Deak | 4feed0e | 2016-02-12 18:55:14 +0200 | [diff] [blame] | 1263 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
| 1264 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1265 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
Paulo Zanoni | 6931016 | 2013-01-29 16:35:19 -0200 | [diff] [blame] | 1266 | cur_state = !!(val & PIPECONF_ENABLE); |
Imre Deak | 4feed0e | 2016-02-12 18:55:14 +0200 | [diff] [blame] | 1267 | |
| 1268 | intel_display_power_put(dev_priv, power_domain); |
| 1269 | } else { |
| 1270 | cur_state = false; |
Paulo Zanoni | 6931016 | 2013-01-29 16:35:19 -0200 | [diff] [blame] | 1271 | } |
| 1272 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1273 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1274 | "pipe %c assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1275 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1276 | } |
| 1277 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1278 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 1279 | enum plane plane, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1280 | { |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1281 | u32 val; |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1282 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1283 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1284 | val = I915_READ(DSPCNTR(plane)); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1285 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1286 | I915_STATE_WARN(cur_state != state, |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1287 | "plane %c assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 1288 | plane_name(plane), onoff(state), onoff(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1289 | } |
| 1290 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1291 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 1292 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 1293 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1294 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 1295 | enum pipe pipe) |
| 1296 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1297 | struct drm_device *dev = &dev_priv->drm; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1298 | int i; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1299 | |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1300 | /* Primary planes are fixed to pipes on gen4+ */ |
| 1301 | if (INTEL_INFO(dev)->gen >= 4) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1302 | u32 val = I915_READ(DSPCNTR(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1303 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1304 | "plane %c assertion failure, should be disabled but not\n", |
| 1305 | plane_name(pipe)); |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1306 | return; |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1307 | } |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1308 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1309 | /* Need to check both planes against the pipe */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1310 | for_each_pipe(dev_priv, i) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1311 | u32 val = I915_READ(DSPCNTR(i)); |
| 1312 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1313 | DISPPLANE_SEL_PIPE_SHIFT; |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1314 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1315 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 1316 | plane_name(i), pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1317 | } |
| 1318 | } |
| 1319 | |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1320 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
| 1321 | enum pipe pipe) |
| 1322 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1323 | struct drm_device *dev = &dev_priv->drm; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1324 | int sprite; |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1325 | |
Damien Lespiau | 7feb8b8 | 2014-03-12 21:05:38 +0000 | [diff] [blame] | 1326 | if (INTEL_INFO(dev)->gen >= 9) { |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 1327 | for_each_sprite(dev_priv, pipe, sprite) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1328 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1329 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
Damien Lespiau | 7feb8b8 | 2014-03-12 21:05:38 +0000 | [diff] [blame] | 1330 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
| 1331 | sprite, pipe_name(pipe)); |
| 1332 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1333 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 1334 | for_each_sprite(dev_priv, pipe, sprite) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1335 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1336 | I915_STATE_WARN(val & SP_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1337 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1338 | sprite_name(pipe, sprite), pipe_name(pipe)); |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1339 | } |
| 1340 | } else if (INTEL_INFO(dev)->gen >= 7) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1341 | u32 val = I915_READ(SPRCTL(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1342 | I915_STATE_WARN(val & SPRITE_ENABLE, |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1344 | plane_name(pipe), pipe_name(pipe)); |
| 1345 | } else if (INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1346 | u32 val = I915_READ(DVSCNTR(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1347 | I915_STATE_WARN(val & DVS_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1348 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1349 | plane_name(pipe), pipe_name(pipe)); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1350 | } |
| 1351 | } |
| 1352 | |
Ville Syrjälä | 08c71e5 | 2014-08-06 14:49:45 +0300 | [diff] [blame] | 1353 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
| 1354 | { |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1355 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
Ville Syrjälä | 08c71e5 | 2014-08-06 14:49:45 +0300 | [diff] [blame] | 1356 | drm_crtc_vblank_put(crtc); |
| 1357 | } |
| 1358 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1359 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1360 | enum pipe pipe) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1361 | { |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1362 | u32 val; |
| 1363 | bool enabled; |
| 1364 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1365 | val = I915_READ(PCH_TRANSCONF(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1366 | enabled = !!(val & TRANS_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1367 | I915_STATE_WARN(enabled, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1368 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1369 | pipe_name(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1370 | } |
| 1371 | |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1372 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1373 | enum pipe pipe, u32 port_sel, u32 val) |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1374 | { |
| 1375 | if ((val & DP_PORT_EN) == 0) |
| 1376 | return false; |
| 1377 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1378 | if (HAS_PCH_CPT(dev_priv)) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1379 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1380 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1381 | return false; |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1382 | } else if (IS_CHERRYVIEW(dev_priv)) { |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1383 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
| 1384 | return false; |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1385 | } else { |
| 1386 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1387 | return false; |
| 1388 | } |
| 1389 | return true; |
| 1390 | } |
| 1391 | |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1392 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1393 | enum pipe pipe, u32 val) |
| 1394 | { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1395 | if ((val & SDVO_ENABLE) == 0) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1396 | return false; |
| 1397 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1398 | if (HAS_PCH_CPT(dev_priv)) { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1399 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1400 | return false; |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1401 | } else if (IS_CHERRYVIEW(dev_priv)) { |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1402 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
| 1403 | return false; |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1404 | } else { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1405 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1406 | return false; |
| 1407 | } |
| 1408 | return true; |
| 1409 | } |
| 1410 | |
| 1411 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1412 | enum pipe pipe, u32 val) |
| 1413 | { |
| 1414 | if ((val & LVDS_PORT_EN) == 0) |
| 1415 | return false; |
| 1416 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1417 | if (HAS_PCH_CPT(dev_priv)) { |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1418 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1419 | return false; |
| 1420 | } else { |
| 1421 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1422 | return false; |
| 1423 | } |
| 1424 | return true; |
| 1425 | } |
| 1426 | |
| 1427 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1428 | enum pipe pipe, u32 val) |
| 1429 | { |
| 1430 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1431 | return false; |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1432 | if (HAS_PCH_CPT(dev_priv)) { |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1433 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1434 | return false; |
| 1435 | } else { |
| 1436 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1437 | return false; |
| 1438 | } |
| 1439 | return true; |
| 1440 | } |
| 1441 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1442 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1443 | enum pipe pipe, i915_reg_t reg, |
| 1444 | u32 port_sel) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1445 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1446 | u32 val = I915_READ(reg); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1447 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1448 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1449 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1450 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1451 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1452 | && (val & DP_PIPEB_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1453 | "IBX PCH dp port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1454 | } |
| 1455 | |
| 1456 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1457 | enum pipe pipe, i915_reg_t reg) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1458 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1459 | u32 val = I915_READ(reg); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1460 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
Adam Jackson | 23c99e7 | 2011-10-07 14:38:43 -0400 | [diff] [blame] | 1461 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1462 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1463 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1464 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1465 | && (val & SDVO_PIPE_B_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1466 | "IBX PCH hdmi port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1467 | } |
| 1468 | |
| 1469 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1470 | enum pipe pipe) |
| 1471 | { |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1472 | u32 val; |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1473 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1477 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1478 | val = I915_READ(PCH_ADPA); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1479 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1480 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1481 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1482 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1483 | val = I915_READ(PCH_LVDS); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1484 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1486 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1487 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
| 1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
| 1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1491 | } |
| 1492 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1493 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
| 1494 | const struct intel_crtc_state *pipe_config) |
| 1495 | { |
| 1496 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 1497 | enum pipe pipe = crtc->pipe; |
| 1498 | |
| 1499 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
| 1500 | POSTING_READ(DPLL(pipe)); |
| 1501 | udelay(150); |
| 1502 | |
Chris Wilson | 2c30b43 | 2016-06-30 15:32:54 +0100 | [diff] [blame] | 1503 | if (intel_wait_for_register(dev_priv, |
| 1504 | DPLL(pipe), |
| 1505 | DPLL_LOCK_VLV, |
| 1506 | DPLL_LOCK_VLV, |
| 1507 | 1)) |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1508 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
| 1509 | } |
| 1510 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1511 | static void vlv_enable_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1512 | const struct intel_crtc_state *pipe_config) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1513 | { |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ville Syrjälä | 8bd3f30 | 2016-03-15 16:39:57 +0200 | [diff] [blame] | 1515 | enum pipe pipe = crtc->pipe; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1516 | |
Ville Syrjälä | 8bd3f30 | 2016-03-15 16:39:57 +0200 | [diff] [blame] | 1517 | assert_pipe_disabled(dev_priv, pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1518 | |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1519 | /* PLL is protected by panel, make sure we can write it */ |
Ville Syrjälä | 7d1a83c | 2016-03-15 16:39:58 +0200 | [diff] [blame] | 1520 | assert_panel_unlocked(dev_priv, pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1521 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1522 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
| 1523 | _vlv_enable_pll(crtc, pipe_config); |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1524 | |
Ville Syrjälä | 8bd3f30 | 2016-03-15 16:39:57 +0200 | [diff] [blame] | 1525 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
| 1526 | POSTING_READ(DPLL_MD(pipe)); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1527 | } |
| 1528 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1529 | |
| 1530 | static void _chv_enable_pll(struct intel_crtc *crtc, |
| 1531 | const struct intel_crtc_state *pipe_config) |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1532 | { |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1533 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ville Syrjälä | 8bd3f30 | 2016-03-15 16:39:57 +0200 | [diff] [blame] | 1534 | enum pipe pipe = crtc->pipe; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1535 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1536 | u32 tmp; |
| 1537 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1538 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1539 | |
| 1540 | /* Enable back the 10bit clock to display controller */ |
| 1541 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1542 | tmp |= DPIO_DCLKP_EN; |
| 1543 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
| 1544 | |
Ville Syrjälä | 54433e9 | 2015-05-26 20:42:31 +0300 | [diff] [blame] | 1545 | mutex_unlock(&dev_priv->sb_lock); |
| 1546 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1547 | /* |
| 1548 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
| 1549 | */ |
| 1550 | udelay(1); |
| 1551 | |
| 1552 | /* Enable PLL */ |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1553 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1554 | |
| 1555 | /* Check PLL is locked */ |
Chris Wilson | 6b18826 | 2016-06-30 15:32:55 +0100 | [diff] [blame] | 1556 | if (intel_wait_for_register(dev_priv, |
| 1557 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, |
| 1558 | 1)) |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1559 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 1560 | } |
| 1561 | |
| 1562 | static void chv_enable_pll(struct intel_crtc *crtc, |
| 1563 | const struct intel_crtc_state *pipe_config) |
| 1564 | { |
| 1565 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 1566 | enum pipe pipe = crtc->pipe; |
| 1567 | |
| 1568 | assert_pipe_disabled(dev_priv, pipe); |
| 1569 | |
| 1570 | /* PLL is protected by panel, make sure we can write it */ |
| 1571 | assert_panel_unlocked(dev_priv, pipe); |
| 1572 | |
| 1573 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
| 1574 | _chv_enable_pll(crtc, pipe_config); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1575 | |
Ville Syrjälä | c231775 | 2016-03-15 16:39:56 +0200 | [diff] [blame] | 1576 | if (pipe != PIPE_A) { |
| 1577 | /* |
| 1578 | * WaPixelRepeatModeFixForC0:chv |
| 1579 | * |
| 1580 | * DPLLCMD is AWOL. Use chicken bits to propagate |
| 1581 | * the value from DPLLBMD to either pipe B or C. |
| 1582 | */ |
| 1583 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); |
| 1584 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); |
| 1585 | I915_WRITE(CBR4_VLV, 0); |
| 1586 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; |
| 1587 | |
| 1588 | /* |
| 1589 | * DPLLB VGA mode also seems to cause problems. |
| 1590 | * We should always have it disabled. |
| 1591 | */ |
| 1592 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); |
| 1593 | } else { |
| 1594 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
| 1595 | POSTING_READ(DPLL_MD(pipe)); |
| 1596 | } |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1597 | } |
| 1598 | |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1599 | static int intel_num_dvo_pipes(struct drm_device *dev) |
| 1600 | { |
| 1601 | struct intel_crtc *crtc; |
| 1602 | int count = 0; |
| 1603 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 1604 | for_each_intel_crtc(dev, crtc) { |
Maarten Lankhorst | 3538b9d | 2015-06-01 12:50:10 +0200 | [diff] [blame] | 1605 | count += crtc->base.state->active && |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 1606 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
| 1607 | } |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1608 | |
| 1609 | return count; |
| 1610 | } |
| 1611 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1612 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1613 | { |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1614 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1615 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1616 | i915_reg_t reg = DPLL(crtc->pipe); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1617 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1618 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1619 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1620 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1621 | /* PLL is protected by panel, make sure we can write it */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
| 1623 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1624 | |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1625 | /* Enable DVO 2x clock on both PLLs if necessary */ |
| 1626 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { |
| 1627 | /* |
| 1628 | * It appears to be important that we don't enable this |
| 1629 | * for the current pipe before otherwise configuring the |
| 1630 | * PLL. No idea how this should be handled if multiple |
| 1631 | * DVO outputs are enabled simultaneosly. |
| 1632 | */ |
| 1633 | dpll |= DPLL_DVO_2X_MODE; |
| 1634 | I915_WRITE(DPLL(!crtc->pipe), |
| 1635 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); |
| 1636 | } |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1637 | |
Ville Syrjälä | c2b6337 | 2015-10-07 22:08:25 +0300 | [diff] [blame] | 1638 | /* |
| 1639 | * Apparently we need to have VGA mode enabled prior to changing |
| 1640 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old |
| 1641 | * dividers, even though the register value does change. |
| 1642 | */ |
| 1643 | I915_WRITE(reg, 0); |
| 1644 | |
Ville Syrjälä | 8e7a65a | 2015-10-07 22:08:24 +0300 | [diff] [blame] | 1645 | I915_WRITE(reg, dpll); |
| 1646 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1647 | /* Wait for the clocks to stabilize. */ |
| 1648 | POSTING_READ(reg); |
| 1649 | udelay(150); |
| 1650 | |
| 1651 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1652 | I915_WRITE(DPLL_MD(crtc->pipe), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1653 | crtc->config->dpll_hw_state.dpll_md); |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1654 | } else { |
| 1655 | /* The pixel multiplier can only be updated once the |
| 1656 | * DPLL is enabled and the clocks are stable. |
| 1657 | * |
| 1658 | * So write it again. |
| 1659 | */ |
| 1660 | I915_WRITE(reg, dpll); |
| 1661 | } |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1662 | |
| 1663 | /* We do this three times for luck */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1664 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1665 | POSTING_READ(reg); |
| 1666 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1667 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1668 | POSTING_READ(reg); |
| 1669 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1670 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1671 | POSTING_READ(reg); |
| 1672 | udelay(150); /* wait for warmup */ |
| 1673 | } |
| 1674 | |
| 1675 | /** |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1676 | * i9xx_disable_pll - disable a PLL |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1677 | * @dev_priv: i915 private structure |
| 1678 | * @pipe: pipe PLL to disable |
| 1679 | * |
| 1680 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1681 | * |
| 1682 | * Note! This is for pre-ILK only. |
| 1683 | */ |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1684 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1685 | { |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1686 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1687 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1688 | enum pipe pipe = crtc->pipe; |
| 1689 | |
| 1690 | /* Disable DVO 2x clock on both PLLs if necessary */ |
| 1691 | if (IS_I830(dev) && |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 1692 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
Maarten Lankhorst | 3538b9d | 2015-06-01 12:50:10 +0200 | [diff] [blame] | 1693 | !intel_num_dvo_pipes(dev)) { |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1694 | I915_WRITE(DPLL(PIPE_B), |
| 1695 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); |
| 1696 | I915_WRITE(DPLL(PIPE_A), |
| 1697 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); |
| 1698 | } |
| 1699 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 1700 | /* Don't disable pipe or pipe PLLs if needed */ |
| 1701 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1702 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1703 | return; |
| 1704 | |
| 1705 | /* Make sure the pipe isn't still relying on us */ |
| 1706 | assert_pipe_disabled(dev_priv, pipe); |
| 1707 | |
Ville Syrjälä | b8afb91 | 2015-06-29 15:25:48 +0300 | [diff] [blame] | 1708 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1709 | POSTING_READ(DPLL(pipe)); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1710 | } |
| 1711 | |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1712 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1713 | { |
Ville Syrjälä | b8afb91 | 2015-06-29 15:25:48 +0300 | [diff] [blame] | 1714 | u32 val; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1715 | |
| 1716 | /* Make sure the pipe isn't still relying on us */ |
| 1717 | assert_pipe_disabled(dev_priv, pipe); |
| 1718 | |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 1719 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
| 1720 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
| 1721 | if (pipe != PIPE_A) |
| 1722 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 1723 | |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1724 | I915_WRITE(DPLL(pipe), val); |
| 1725 | POSTING_READ(DPLL(pipe)); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1726 | } |
| 1727 | |
| 1728 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1729 | { |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1730 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1731 | u32 val; |
| 1732 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1733 | /* Make sure the pipe isn't still relying on us */ |
| 1734 | assert_pipe_disabled(dev_priv, pipe); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1735 | |
Ville Syrjälä | 60bfe44 | 2015-06-29 15:25:49 +0300 | [diff] [blame] | 1736 | val = DPLL_SSC_REF_CLK_CHV | |
| 1737 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1738 | if (pipe != PIPE_A) |
| 1739 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 1740 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1741 | I915_WRITE(DPLL(pipe), val); |
| 1742 | POSTING_READ(DPLL(pipe)); |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1743 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1744 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1745 | |
| 1746 | /* Disable 10bit clock to display controller */ |
| 1747 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1748 | val &= ~DPIO_DCLKP_EN; |
| 1749 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
| 1750 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1751 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1752 | } |
| 1753 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1754 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 1755 | struct intel_digital_port *dport, |
| 1756 | unsigned int expected_mask) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1757 | { |
| 1758 | u32 port_mask; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1759 | i915_reg_t dpll_reg; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1760 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1761 | switch (dport->port) { |
| 1762 | case PORT_B: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1763 | port_mask = DPLL_PORTB_READY_MASK; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1764 | dpll_reg = DPLL(0); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1765 | break; |
| 1766 | case PORT_C: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1767 | port_mask = DPLL_PORTC_READY_MASK; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1768 | dpll_reg = DPLL(0); |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 1769 | expected_mask <<= 4; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1770 | break; |
| 1771 | case PORT_D: |
| 1772 | port_mask = DPLL_PORTD_READY_MASK; |
| 1773 | dpll_reg = DPIO_PHY_STATUS; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1774 | break; |
| 1775 | default: |
| 1776 | BUG(); |
| 1777 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1778 | |
Chris Wilson | 370004d | 2016-06-30 15:32:56 +0100 | [diff] [blame] | 1779 | if (intel_wait_for_register(dev_priv, |
| 1780 | dpll_reg, port_mask, expected_mask, |
| 1781 | 1000)) |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 1782 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
| 1783 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1784 | } |
| 1785 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1786 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1787 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1788 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1789 | struct drm_device *dev = &dev_priv->drm; |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1790 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1792 | i915_reg_t reg; |
| 1793 | uint32_t val, pipeconf_val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1794 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1795 | /* Make sure PCH DPLL is enabled */ |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 1796 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1797 | |
| 1798 | /* FDI must be feeding us bits for PCH ports */ |
| 1799 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1800 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1801 | |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1802 | if (HAS_PCH_CPT(dev)) { |
| 1803 | /* Workaround: Set the timing override bit before enabling the |
| 1804 | * pch transcoder. */ |
| 1805 | reg = TRANS_CHICKEN2(pipe); |
| 1806 | val = I915_READ(reg); |
| 1807 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1808 | I915_WRITE(reg, val); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 1809 | } |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1810 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1811 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1812 | val = I915_READ(reg); |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1813 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1814 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1815 | if (HAS_PCH_IBX(dev_priv)) { |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1816 | /* |
Ville Syrjälä | c5de7c6 | 2015-05-05 17:06:22 +0300 | [diff] [blame] | 1817 | * Make the BPC in transcoder be consistent with |
| 1818 | * that in pipeconf reg. For HDMI we must use 8bpc |
| 1819 | * here for both 8bpc and 12bpc. |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1820 | */ |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 1821 | val &= ~PIPECONF_BPC_MASK; |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 1822 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
Ville Syrjälä | c5de7c6 | 2015-05-05 17:06:22 +0300 | [diff] [blame] | 1823 | val |= PIPECONF_8BPC; |
| 1824 | else |
| 1825 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1826 | } |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1827 | |
| 1828 | val &= ~TRANS_INTERLACE_MASK; |
| 1829 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1830 | if (HAS_PCH_IBX(dev_priv) && |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 1831 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1832 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 1833 | else |
| 1834 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1835 | else |
| 1836 | val |= TRANS_PROGRESSIVE; |
| 1837 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1838 | I915_WRITE(reg, val | TRANS_ENABLE); |
Chris Wilson | 650fbd8 | 2016-06-30 15:32:57 +0100 | [diff] [blame] | 1839 | if (intel_wait_for_register(dev_priv, |
| 1840 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, |
| 1841 | 100)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 1842 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1843 | } |
| 1844 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1845 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1846 | enum transcoder cpu_transcoder) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1847 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1848 | u32 val, pipeconf_val; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1849 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1850 | /* FDI must be feeding us bits for PCH ports */ |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1851 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1852 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1853 | |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1854 | /* Workaround: set timing override bit. */ |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1858 | |
Paulo Zanoni | 25f3ef1 | 2012-10-31 18:12:49 -0200 | [diff] [blame] | 1859 | val = TRANS_ENABLE; |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1860 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1861 | |
Paulo Zanoni | 9a76b1c | 2012-10-31 18:12:48 -0200 | [diff] [blame] | 1862 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
| 1863 | PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | a35f267 | 2012-10-31 18:12:45 -0200 | [diff] [blame] | 1864 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1865 | else |
| 1866 | val |= TRANS_PROGRESSIVE; |
| 1867 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1868 | I915_WRITE(LPT_TRANSCONF, val); |
Chris Wilson | d9f9624 | 2016-06-30 15:32:58 +0100 | [diff] [blame] | 1869 | if (intel_wait_for_register(dev_priv, |
| 1870 | LPT_TRANSCONF, |
| 1871 | TRANS_STATE_ENABLE, |
| 1872 | TRANS_STATE_ENABLE, |
| 1873 | 100)) |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1874 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1875 | } |
| 1876 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1877 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1878 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1879 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 1880 | struct drm_device *dev = &dev_priv->drm; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1881 | i915_reg_t reg; |
| 1882 | uint32_t val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1883 | |
| 1884 | /* FDI relies on the transcoder */ |
| 1885 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 1886 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 1887 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1888 | /* Ports must be off as well */ |
| 1889 | assert_pch_ports_disabled(dev_priv, pipe); |
| 1890 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1891 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1892 | val = I915_READ(reg); |
| 1893 | val &= ~TRANS_ENABLE; |
| 1894 | I915_WRITE(reg, val); |
| 1895 | /* wait for PCH transcoder off, transcoder state */ |
Chris Wilson | a7d0466 | 2016-06-30 15:32:59 +0100 | [diff] [blame] | 1896 | if (intel_wait_for_register(dev_priv, |
| 1897 | reg, TRANS_STATE_ENABLE, 0, |
| 1898 | 50)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 1899 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1900 | |
Ville Syrjälä | c465613 | 2015-10-29 21:25:56 +0200 | [diff] [blame] | 1901 | if (HAS_PCH_CPT(dev)) { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1902 | /* Workaround: Clear the timing override chicken bit again. */ |
| 1903 | reg = TRANS_CHICKEN2(pipe); |
| 1904 | val = I915_READ(reg); |
| 1905 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1906 | I915_WRITE(reg, val); |
| 1907 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1908 | } |
| 1909 | |
Maarten Lankhorst | b707654 | 2016-08-23 16:18:08 +0200 | [diff] [blame] | 1910 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1911 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1912 | u32 val; |
| 1913 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1914 | val = I915_READ(LPT_TRANSCONF); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1915 | val &= ~TRANS_ENABLE; |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1916 | I915_WRITE(LPT_TRANSCONF, val); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1917 | /* wait for PCH transcoder off, transcoder state */ |
Chris Wilson | dfdb474 | 2016-06-30 15:33:00 +0100 | [diff] [blame] | 1918 | if (intel_wait_for_register(dev_priv, |
| 1919 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, |
| 1920 | 50)) |
Paulo Zanoni | 8a52fd9 | 2012-10-31 18:12:51 -0200 | [diff] [blame] | 1921 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1922 | |
| 1923 | /* Workaround: clear timing override bit. */ |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 1924 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1925 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 1926 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1927 | } |
| 1928 | |
| 1929 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1930 | * intel_enable_pipe - enable a pipe, asserting requirements |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1931 | * @crtc: crtc responsible for the pipe |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1932 | * |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1933 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1934 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1935 | */ |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 1936 | static void intel_enable_pipe(struct intel_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1937 | { |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1938 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1939 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1940 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | 1a70a728 | 2015-10-29 21:25:50 +0200 | [diff] [blame] | 1941 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1942 | enum pipe pch_transcoder; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1943 | i915_reg_t reg; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1944 | u32 val; |
| 1945 | |
Ville Syrjälä | 9e2ee2d | 2015-06-24 21:59:35 +0300 | [diff] [blame] | 1946 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
| 1947 | |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1948 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1949 | assert_cursor_disabled(dev_priv, pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1950 | assert_sprites_disabled(dev_priv, pipe); |
| 1951 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 1952 | if (HAS_PCH_LPT(dev_priv)) |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 1953 | pch_transcoder = TRANSCODER_A; |
| 1954 | else |
| 1955 | pch_transcoder = pipe; |
| 1956 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1957 | /* |
| 1958 | * A pipe without a PLL won't actually be able to drive bits from |
| 1959 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 1960 | * need the check. |
| 1961 | */ |
Ville Syrjälä | 09fa8bb | 2016-08-05 20:41:34 +0300 | [diff] [blame] | 1962 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 1963 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1964 | assert_dsi_pll_enabled(dev_priv); |
| 1965 | else |
| 1966 | assert_pll_enabled(dev_priv, pipe); |
Ville Syrjälä | 09fa8bb | 2016-08-05 20:41:34 +0300 | [diff] [blame] | 1967 | } else { |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1968 | if (crtc->config->has_pch_encoder) { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1969 | /* if driving the PCH, we need FDI enabled */ |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 1970 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1971 | assert_fdi_tx_pll_enabled(dev_priv, |
| 1972 | (enum pipe) cpu_transcoder); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1973 | } |
| 1974 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 1975 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1976 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1977 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1978 | val = I915_READ(reg); |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 1979 | if (val & PIPECONF_ENABLE) { |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 1980 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1981 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1982 | return; |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 1983 | } |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1984 | |
| 1985 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Paulo Zanoni | 851855d | 2013-12-19 19:12:29 -0200 | [diff] [blame] | 1986 | POSTING_READ(reg); |
Ville Syrjälä | b7792d8 | 2015-12-14 18:23:43 +0200 | [diff] [blame] | 1987 | |
| 1988 | /* |
| 1989 | * Until the pipe starts DSL will read as 0, which would cause |
| 1990 | * an apparent vblank timestamp jump, which messes up also the |
| 1991 | * frame count when it's derived from the timestamps. So let's |
| 1992 | * wait for the pipe to start properly before we call |
| 1993 | * drm_crtc_vblank_on() |
| 1994 | */ |
| 1995 | if (dev->max_vblank_count == 0 && |
| 1996 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) |
| 1997 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1998 | } |
| 1999 | |
| 2000 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 2001 | * intel_disable_pipe - disable a pipe, asserting requirements |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2002 | * @crtc: crtc whose pipes is to be disabled |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2003 | * |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2004 | * Disable the pipe of @crtc, making sure that various hardware |
| 2005 | * specific requirements are met, if applicable, e.g. plane |
| 2006 | * disabled, panel fitter off, etc. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2007 | * |
| 2008 | * Will wait until the pipe has shut down before returning. |
| 2009 | */ |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2010 | static void intel_disable_pipe(struct intel_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2011 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2012 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2013 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2014 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2015 | i915_reg_t reg; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2016 | u32 val; |
| 2017 | |
Ville Syrjälä | 9e2ee2d | 2015-06-24 21:59:35 +0300 | [diff] [blame] | 2018 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
| 2019 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2020 | /* |
| 2021 | * Make sure planes won't keep trying to pump pixels to us, |
| 2022 | * or we might hang the display. |
| 2023 | */ |
| 2024 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 2025 | assert_cursor_disabled(dev_priv, pipe); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 2026 | assert_sprites_disabled(dev_priv, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2027 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 2028 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2029 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2030 | if ((val & PIPECONF_ENABLE) == 0) |
| 2031 | return; |
| 2032 | |
Ville Syrjälä | 67adc64 | 2014-08-15 01:21:57 +0300 | [diff] [blame] | 2033 | /* |
| 2034 | * Double wide has implications for planes |
| 2035 | * so best keep it disabled when not needed. |
| 2036 | */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2037 | if (crtc->config->double_wide) |
Ville Syrjälä | 67adc64 | 2014-08-15 01:21:57 +0300 | [diff] [blame] | 2038 | val &= ~PIPECONF_DOUBLE_WIDE; |
| 2039 | |
| 2040 | /* Don't disable pipe or pipe PLLs if needed */ |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 2041 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
| 2042 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Ville Syrjälä | 67adc64 | 2014-08-15 01:21:57 +0300 | [diff] [blame] | 2043 | val &= ~PIPECONF_ENABLE; |
| 2044 | |
| 2045 | I915_WRITE(reg, val); |
| 2046 | if ((val & PIPECONF_ENABLE) == 0) |
| 2047 | intel_wait_for_pipe_off(crtc); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2048 | } |
| 2049 | |
Ville Syrjälä | 832be82 | 2016-01-12 21:08:33 +0200 | [diff] [blame] | 2050 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
| 2051 | { |
| 2052 | return IS_GEN2(dev_priv) ? 2048 : 4096; |
| 2053 | } |
| 2054 | |
Ville Syrjälä | 27ba391 | 2016-02-15 22:54:40 +0200 | [diff] [blame] | 2055 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
| 2056 | uint64_t fb_modifier, unsigned int cpp) |
Ville Syrjälä | 7b49f94 | 2016-01-12 21:08:32 +0200 | [diff] [blame] | 2057 | { |
| 2058 | switch (fb_modifier) { |
| 2059 | case DRM_FORMAT_MOD_NONE: |
| 2060 | return cpp; |
| 2061 | case I915_FORMAT_MOD_X_TILED: |
| 2062 | if (IS_GEN2(dev_priv)) |
| 2063 | return 128; |
| 2064 | else |
| 2065 | return 512; |
| 2066 | case I915_FORMAT_MOD_Y_TILED: |
| 2067 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) |
| 2068 | return 128; |
| 2069 | else |
| 2070 | return 512; |
| 2071 | case I915_FORMAT_MOD_Yf_TILED: |
| 2072 | switch (cpp) { |
| 2073 | case 1: |
| 2074 | return 64; |
| 2075 | case 2: |
| 2076 | case 4: |
| 2077 | return 128; |
| 2078 | case 8: |
| 2079 | case 16: |
| 2080 | return 256; |
| 2081 | default: |
| 2082 | MISSING_CASE(cpp); |
| 2083 | return cpp; |
| 2084 | } |
| 2085 | break; |
| 2086 | default: |
| 2087 | MISSING_CASE(fb_modifier); |
| 2088 | return cpp; |
| 2089 | } |
| 2090 | } |
| 2091 | |
Ville Syrjälä | 832be82 | 2016-01-12 21:08:33 +0200 | [diff] [blame] | 2092 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
| 2093 | uint64_t fb_modifier, unsigned int cpp) |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 2094 | { |
Ville Syrjälä | 832be82 | 2016-01-12 21:08:33 +0200 | [diff] [blame] | 2095 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
| 2096 | return 1; |
| 2097 | else |
| 2098 | return intel_tile_size(dev_priv) / |
Ville Syrjälä | 27ba391 | 2016-02-15 22:54:40 +0200 | [diff] [blame] | 2099 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2100 | } |
| 2101 | |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2102 | /* Return the tile dimensions in pixel units */ |
| 2103 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, |
| 2104 | unsigned int *tile_width, |
| 2105 | unsigned int *tile_height, |
| 2106 | uint64_t fb_modifier, |
| 2107 | unsigned int cpp) |
| 2108 | { |
| 2109 | unsigned int tile_width_bytes = |
| 2110 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
| 2111 | |
| 2112 | *tile_width = tile_width_bytes / cpp; |
| 2113 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; |
| 2114 | } |
| 2115 | |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2116 | unsigned int |
| 2117 | intel_fb_align_height(struct drm_device *dev, unsigned int height, |
Ville Syrjälä | 832be82 | 2016-01-12 21:08:33 +0200 | [diff] [blame] | 2118 | uint32_t pixel_format, uint64_t fb_modifier) |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2119 | { |
Ville Syrjälä | 832be82 | 2016-01-12 21:08:33 +0200 | [diff] [blame] | 2120 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
| 2121 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); |
| 2122 | |
| 2123 | return ALIGN(height, tile_height); |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 2124 | } |
| 2125 | |
Ville Syrjälä | 1663b9d | 2016-02-15 22:54:45 +0200 | [diff] [blame] | 2126 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
| 2127 | { |
| 2128 | unsigned int size = 0; |
| 2129 | int i; |
| 2130 | |
| 2131 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) |
| 2132 | size += rot_info->plane[i].width * rot_info->plane[i].height; |
| 2133 | |
| 2134 | return size; |
| 2135 | } |
| 2136 | |
Daniel Vetter | 75c82a5 | 2015-10-14 16:51:04 +0200 | [diff] [blame] | 2137 | static void |
Ville Syrjälä | 3465c58 | 2016-02-15 22:54:43 +0200 | [diff] [blame] | 2138 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
| 2139 | const struct drm_framebuffer *fb, |
| 2140 | unsigned int rotation) |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2141 | { |
Ville Syrjälä | 2d7a215 | 2016-02-15 22:54:47 +0200 | [diff] [blame] | 2142 | if (intel_rotation_90_or_270(rotation)) { |
| 2143 | *view = i915_ggtt_view_rotated; |
| 2144 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; |
| 2145 | } else { |
| 2146 | *view = i915_ggtt_view_normal; |
| 2147 | } |
| 2148 | } |
| 2149 | |
Ville Syrjälä | 603525d | 2016-01-12 21:08:37 +0200 | [diff] [blame] | 2150 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2151 | { |
| 2152 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 2153 | return 256 * 1024; |
Ville Syrjälä | 985b8bb | 2015-06-11 16:31:15 +0300 | [diff] [blame] | 2154 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2155 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2156 | return 128 * 1024; |
| 2157 | else if (INTEL_INFO(dev_priv)->gen >= 4) |
| 2158 | return 4 * 1024; |
| 2159 | else |
Ville Syrjälä | 44c5905 | 2015-06-11 16:31:16 +0300 | [diff] [blame] | 2160 | return 0; |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2161 | } |
| 2162 | |
Ville Syrjälä | 603525d | 2016-01-12 21:08:37 +0200 | [diff] [blame] | 2163 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
| 2164 | uint64_t fb_modifier) |
| 2165 | { |
| 2166 | switch (fb_modifier) { |
| 2167 | case DRM_FORMAT_MOD_NONE: |
| 2168 | return intel_linear_alignment(dev_priv); |
| 2169 | case I915_FORMAT_MOD_X_TILED: |
| 2170 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 2171 | return 256 * 1024; |
| 2172 | return 0; |
| 2173 | case I915_FORMAT_MOD_Y_TILED: |
| 2174 | case I915_FORMAT_MOD_Yf_TILED: |
| 2175 | return 1 * 1024 * 1024; |
| 2176 | default: |
| 2177 | MISSING_CASE(fb_modifier); |
| 2178 | return 0; |
| 2179 | } |
| 2180 | } |
| 2181 | |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2182 | struct i915_vma * |
| 2183 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2184 | { |
Tvrtko Ursulin | 850c4cd | 2014-10-30 16:39:38 +0000 | [diff] [blame] | 2185 | struct drm_device *dev = fb->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2186 | struct drm_i915_private *dev_priv = to_i915(dev); |
Tvrtko Ursulin | 850c4cd | 2014-10-30 16:39:38 +0000 | [diff] [blame] | 2187 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2188 | struct i915_ggtt_view view; |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2189 | struct i915_vma *vma; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2190 | u32 alignment; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2191 | |
Matt Roper | ebcdd39 | 2014-07-09 16:22:11 -0700 | [diff] [blame] | 2192 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2193 | |
Ville Syrjälä | 603525d | 2016-01-12 21:08:37 +0200 | [diff] [blame] | 2194 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2195 | |
Ville Syrjälä | 3465c58 | 2016-02-15 22:54:43 +0200 | [diff] [blame] | 2196 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2197 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 2198 | /* Note that the w/a also requires 64 PTE of padding following the |
| 2199 | * bo. We currently fill all unused PTE with the shadow page and so |
| 2200 | * we should always have valid PTE following the scanout preventing |
| 2201 | * the VT-d warning. |
| 2202 | */ |
Chris Wilson | 48f112f | 2016-06-24 14:07:14 +0100 | [diff] [blame] | 2203 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 2204 | alignment = 256 * 1024; |
| 2205 | |
Paulo Zanoni | d6dd684 | 2014-08-15 15:59:32 -0300 | [diff] [blame] | 2206 | /* |
| 2207 | * Global gtt pte registers are special registers which actually forward |
| 2208 | * writes to a chunk of system memory. Which means that there is no risk |
| 2209 | * that the register values disappear as soon as we call |
| 2210 | * intel_runtime_pm_put(), so it is correct to wrap only the |
| 2211 | * pin/unpin/fence and not more. |
| 2212 | */ |
| 2213 | intel_runtime_pm_get(dev_priv); |
| 2214 | |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2215 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
Chris Wilson | 49ef529 | 2016-08-18 17:17:00 +0100 | [diff] [blame] | 2216 | if (IS_ERR(vma)) |
| 2217 | goto err; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2218 | |
Chris Wilson | 05a20d0 | 2016-08-18 17:16:55 +0100 | [diff] [blame] | 2219 | if (i915_vma_is_map_and_fenceable(vma)) { |
Chris Wilson | 49ef529 | 2016-08-18 17:17:00 +0100 | [diff] [blame] | 2220 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 2221 | * fence, whereas 965+ only requires a fence if using |
| 2222 | * framebuffer compression. For simplicity, we always, when |
| 2223 | * possible, install a fence as the cost is not that onerous. |
| 2224 | * |
| 2225 | * If we fail to fence the tiled scanout, then either the |
| 2226 | * modeset will reject the change (which is highly unlikely as |
| 2227 | * the affected systems, all but one, do not have unmappable |
| 2228 | * space) or we will not be able to enable full powersaving |
| 2229 | * techniques (also likely not to apply due to various limits |
| 2230 | * FBC and the like impose on the size of the buffer, which |
| 2231 | * presumably we violated anyway with this unmappable buffer). |
| 2232 | * Anyway, it is presumably better to stumble onwards with |
| 2233 | * something and try to run the system in a "less than optimal" |
| 2234 | * mode that matches the user configuration. |
| 2235 | */ |
| 2236 | if (i915_vma_get_fence(vma) == 0) |
| 2237 | i915_vma_pin_fence(vma); |
Vivek Kasireddy | 9807216 | 2015-10-29 18:54:38 -0700 | [diff] [blame] | 2238 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2239 | |
Chris Wilson | 49ef529 | 2016-08-18 17:17:00 +0100 | [diff] [blame] | 2240 | err: |
Paulo Zanoni | d6dd684 | 2014-08-15 15:59:32 -0300 | [diff] [blame] | 2241 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2242 | return vma; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2243 | } |
| 2244 | |
Chris Wilson | fb4b8ce | 2016-04-28 09:56:35 +0100 | [diff] [blame] | 2245 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2246 | { |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 2247 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2248 | struct i915_ggtt_view view; |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2249 | struct i915_vma *vma; |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 2250 | |
Matt Roper | ebcdd39 | 2014-07-09 16:22:11 -0700 | [diff] [blame] | 2251 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
| 2252 | |
Ville Syrjälä | 3465c58 | 2016-02-15 22:54:43 +0200 | [diff] [blame] | 2253 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
Chris Wilson | 05a20d0 | 2016-08-18 17:16:55 +0100 | [diff] [blame] | 2254 | vma = i915_gem_object_to_ggtt(obj, &view); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2255 | |
Chris Wilson | 49ef529 | 2016-08-18 17:17:00 +0100 | [diff] [blame] | 2256 | i915_vma_unpin_fence(vma); |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2257 | i915_gem_object_unpin_from_display_plane(vma); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2258 | } |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2259 | |
Ville Syrjälä | ef78ec9 | 2015-10-13 22:48:39 +0300 | [diff] [blame] | 2260 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
| 2261 | unsigned int rotation) |
| 2262 | { |
| 2263 | if (intel_rotation_90_or_270(rotation)) |
| 2264 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
| 2265 | else |
| 2266 | return fb->pitches[plane]; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2267 | } |
| 2268 | |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2269 | /* |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2270 | * Convert the x/y offsets into a linear offset. |
| 2271 | * Only valid with 0/180 degree rotation, which is fine since linear |
| 2272 | * offset is only used with linear buffers on pre-hsw and tiled buffers |
| 2273 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. |
| 2274 | */ |
| 2275 | u32 intel_fb_xy_to_linear(int x, int y, |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 2276 | const struct intel_plane_state *state, |
| 2277 | int plane) |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2278 | { |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 2279 | const struct drm_framebuffer *fb = state->base.fb; |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2280 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
| 2281 | unsigned int pitch = fb->pitches[plane]; |
| 2282 | |
| 2283 | return y * pitch + x * cpp; |
| 2284 | } |
| 2285 | |
| 2286 | /* |
| 2287 | * Add the x/y offsets derived from fb->offsets[] to the user |
| 2288 | * specified plane src x/y offsets. The resulting x/y offsets |
| 2289 | * specify the start of scanout from the beginning of the gtt mapping. |
| 2290 | */ |
| 2291 | void intel_add_fb_offsets(int *x, int *y, |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 2292 | const struct intel_plane_state *state, |
| 2293 | int plane) |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2294 | |
| 2295 | { |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 2296 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
| 2297 | unsigned int rotation = state->base.rotation; |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2298 | |
| 2299 | if (intel_rotation_90_or_270(rotation)) { |
| 2300 | *x += intel_fb->rotated[plane].x; |
| 2301 | *y += intel_fb->rotated[plane].y; |
| 2302 | } else { |
| 2303 | *x += intel_fb->normal[plane].x; |
| 2304 | *y += intel_fb->normal[plane].y; |
| 2305 | } |
| 2306 | } |
| 2307 | |
| 2308 | /* |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2309 | * Input tile dimensions and pitch must already be |
| 2310 | * rotated to match x and y, and in pixel units. |
| 2311 | */ |
Ville Syrjälä | 66a2d92 | 2016-02-05 18:44:05 +0200 | [diff] [blame] | 2312 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
| 2313 | unsigned int tile_width, |
| 2314 | unsigned int tile_height, |
| 2315 | unsigned int tile_size, |
| 2316 | unsigned int pitch_tiles, |
| 2317 | u32 old_offset, |
| 2318 | u32 new_offset) |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2319 | { |
Ville Syrjälä | b9b2403 | 2016-02-08 18:28:00 +0200 | [diff] [blame] | 2320 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2321 | unsigned int tiles; |
| 2322 | |
| 2323 | WARN_ON(old_offset & (tile_size - 1)); |
| 2324 | WARN_ON(new_offset & (tile_size - 1)); |
| 2325 | WARN_ON(new_offset > old_offset); |
| 2326 | |
| 2327 | tiles = (old_offset - new_offset) / tile_size; |
| 2328 | |
| 2329 | *y += tiles / pitch_tiles * tile_height; |
| 2330 | *x += tiles % pitch_tiles * tile_width; |
| 2331 | |
Ville Syrjälä | b9b2403 | 2016-02-08 18:28:00 +0200 | [diff] [blame] | 2332 | /* minimize x in case it got needlessly big */ |
| 2333 | *y += *x / pitch_pixels * tile_height; |
| 2334 | *x %= pitch_pixels; |
| 2335 | |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2336 | return new_offset; |
| 2337 | } |
| 2338 | |
| 2339 | /* |
Ville Syrjälä | 66a2d92 | 2016-02-05 18:44:05 +0200 | [diff] [blame] | 2340 | * Adjust the tile offset by moving the difference into |
| 2341 | * the x/y offsets. |
| 2342 | */ |
| 2343 | static u32 intel_adjust_tile_offset(int *x, int *y, |
| 2344 | const struct intel_plane_state *state, int plane, |
| 2345 | u32 old_offset, u32 new_offset) |
| 2346 | { |
| 2347 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
| 2348 | const struct drm_framebuffer *fb = state->base.fb; |
| 2349 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
| 2350 | unsigned int rotation = state->base.rotation; |
| 2351 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); |
| 2352 | |
| 2353 | WARN_ON(new_offset > old_offset); |
| 2354 | |
| 2355 | if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) { |
| 2356 | unsigned int tile_size, tile_width, tile_height; |
| 2357 | unsigned int pitch_tiles; |
| 2358 | |
| 2359 | tile_size = intel_tile_size(dev_priv); |
| 2360 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
| 2361 | fb->modifier[plane], cpp); |
| 2362 | |
| 2363 | if (intel_rotation_90_or_270(rotation)) { |
| 2364 | pitch_tiles = pitch / tile_height; |
| 2365 | swap(tile_width, tile_height); |
| 2366 | } else { |
| 2367 | pitch_tiles = pitch / (tile_width * cpp); |
| 2368 | } |
| 2369 | |
| 2370 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
| 2371 | tile_size, pitch_tiles, |
| 2372 | old_offset, new_offset); |
| 2373 | } else { |
| 2374 | old_offset += *y * pitch + *x * cpp; |
| 2375 | |
| 2376 | *y = (old_offset - new_offset) / pitch; |
| 2377 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; |
| 2378 | } |
| 2379 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2380 | return new_offset; |
| 2381 | } |
| 2382 | |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2383 | /* |
| 2384 | * Computes the linear offset to the base tile and adjusts |
| 2385 | * x, y. bytes per pixel is assumed to be a power-of-two. |
| 2386 | * |
| 2387 | * In the 90/270 rotated case, x and y are assumed |
| 2388 | * to be already rotated to match the rotated GTT view, and |
| 2389 | * pitch is the tile_height aligned framebuffer height. |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2390 | * |
| 2391 | * This function is used when computing the derived information |
| 2392 | * under intel_framebuffer, so using any of that information |
| 2393 | * here is not allowed. Anything under drm_framebuffer can be |
| 2394 | * used. This is why the user has to pass in the pitch since it |
| 2395 | * is specified in the rotated orientation. |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2396 | */ |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2397 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
| 2398 | int *x, int *y, |
| 2399 | const struct drm_framebuffer *fb, int plane, |
| 2400 | unsigned int pitch, |
| 2401 | unsigned int rotation, |
| 2402 | u32 alignment) |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2403 | { |
Ville Syrjälä | 4f2d993 | 2016-02-15 22:54:44 +0200 | [diff] [blame] | 2404 | uint64_t fb_modifier = fb->modifier[plane]; |
| 2405 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2406 | u32 offset, offset_aligned; |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2407 | |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2408 | if (alignment) |
| 2409 | alignment--; |
| 2410 | |
Ville Syrjälä | b5c6533 | 2016-01-12 21:08:31 +0200 | [diff] [blame] | 2411 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2412 | unsigned int tile_size, tile_width, tile_height; |
| 2413 | unsigned int tile_rows, tiles, pitch_tiles; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2414 | |
Ville Syrjälä | d843310 | 2016-01-12 21:08:35 +0200 | [diff] [blame] | 2415 | tile_size = intel_tile_size(dev_priv); |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2416 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
| 2417 | fb_modifier, cpp); |
| 2418 | |
| 2419 | if (intel_rotation_90_or_270(rotation)) { |
| 2420 | pitch_tiles = pitch / tile_height; |
| 2421 | swap(tile_width, tile_height); |
| 2422 | } else { |
| 2423 | pitch_tiles = pitch / (tile_width * cpp); |
| 2424 | } |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2425 | |
Ville Syrjälä | d843310 | 2016-01-12 21:08:35 +0200 | [diff] [blame] | 2426 | tile_rows = *y / tile_height; |
| 2427 | *y %= tile_height; |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2428 | |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 2429 | tiles = *x / tile_width; |
| 2430 | *x %= tile_width; |
Ville Syrjälä | d843310 | 2016-01-12 21:08:35 +0200 | [diff] [blame] | 2431 | |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2432 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
| 2433 | offset_aligned = offset & ~alignment; |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2434 | |
Ville Syrjälä | 66a2d92 | 2016-02-05 18:44:05 +0200 | [diff] [blame] | 2435 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
| 2436 | tile_size, pitch_tiles, |
| 2437 | offset, offset_aligned); |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2438 | } else { |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2439 | offset = *y * pitch + *x * cpp; |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2440 | offset_aligned = offset & ~alignment; |
| 2441 | |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2442 | *y = (offset & alignment) / pitch; |
| 2443 | *x = ((offset & alignment) - *y * pitch) / cpp; |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2444 | } |
Ville Syrjälä | 29cf949 | 2016-02-15 22:54:42 +0200 | [diff] [blame] | 2445 | |
| 2446 | return offset_aligned; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2447 | } |
| 2448 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2449 | u32 intel_compute_tile_offset(int *x, int *y, |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 2450 | const struct intel_plane_state *state, |
| 2451 | int plane) |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2452 | { |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 2453 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
| 2454 | const struct drm_framebuffer *fb = state->base.fb; |
| 2455 | unsigned int rotation = state->base.rotation; |
Ville Syrjälä | ef78ec9 | 2015-10-13 22:48:39 +0300 | [diff] [blame] | 2456 | int pitch = intel_fb_pitch(fb, plane, rotation); |
Ville Syrjälä | 8d97065 | 2016-01-28 16:30:28 +0200 | [diff] [blame] | 2457 | u32 alignment; |
| 2458 | |
| 2459 | /* AUX_DIST needs only 4K alignment */ |
| 2460 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) |
| 2461 | alignment = 4096; |
| 2462 | else |
| 2463 | alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2464 | |
| 2465 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, |
| 2466 | rotation, alignment); |
| 2467 | } |
| 2468 | |
| 2469 | /* Convert the fb->offset[] linear offset into x/y offsets */ |
| 2470 | static void intel_fb_offset_to_xy(int *x, int *y, |
| 2471 | const struct drm_framebuffer *fb, int plane) |
| 2472 | { |
| 2473 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
| 2474 | unsigned int pitch = fb->pitches[plane]; |
| 2475 | u32 linear_offset = fb->offsets[plane]; |
| 2476 | |
| 2477 | *y = linear_offset / pitch; |
| 2478 | *x = linear_offset % pitch / cpp; |
| 2479 | } |
| 2480 | |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 2481 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
| 2482 | { |
| 2483 | switch (fb_modifier) { |
| 2484 | case I915_FORMAT_MOD_X_TILED: |
| 2485 | return I915_TILING_X; |
| 2486 | case I915_FORMAT_MOD_Y_TILED: |
| 2487 | return I915_TILING_Y; |
| 2488 | default: |
| 2489 | return I915_TILING_NONE; |
| 2490 | } |
| 2491 | } |
| 2492 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2493 | static int |
| 2494 | intel_fill_fb_info(struct drm_i915_private *dev_priv, |
| 2495 | struct drm_framebuffer *fb) |
| 2496 | { |
| 2497 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 2498 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; |
| 2499 | u32 gtt_offset_rotated = 0; |
| 2500 | unsigned int max_size = 0; |
| 2501 | uint32_t format = fb->pixel_format; |
| 2502 | int i, num_planes = drm_format_num_planes(format); |
| 2503 | unsigned int tile_size = intel_tile_size(dev_priv); |
| 2504 | |
| 2505 | for (i = 0; i < num_planes; i++) { |
| 2506 | unsigned int width, height; |
| 2507 | unsigned int cpp, size; |
| 2508 | u32 offset; |
| 2509 | int x, y; |
| 2510 | |
| 2511 | cpp = drm_format_plane_cpp(format, i); |
| 2512 | width = drm_format_plane_width(fb->width, format, i); |
| 2513 | height = drm_format_plane_height(fb->height, format, i); |
| 2514 | |
| 2515 | intel_fb_offset_to_xy(&x, &y, fb, i); |
| 2516 | |
| 2517 | /* |
Ville Syrjälä | 60d5f2a | 2016-01-22 18:41:24 +0200 | [diff] [blame] | 2518 | * The fence (if used) is aligned to the start of the object |
| 2519 | * so having the framebuffer wrap around across the edge of the |
| 2520 | * fenced region doesn't really work. We have no API to configure |
| 2521 | * the fence start offset within the object (nor could we probably |
| 2522 | * on gen2/3). So it's just easier if we just require that the |
| 2523 | * fb layout agrees with the fence layout. We already check that the |
| 2524 | * fb stride matches the fence stride elsewhere. |
| 2525 | */ |
| 2526 | if (i915_gem_object_is_tiled(intel_fb->obj) && |
| 2527 | (x + width) * cpp > fb->pitches[i]) { |
| 2528 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", |
| 2529 | i, fb->offsets[i]); |
| 2530 | return -EINVAL; |
| 2531 | } |
| 2532 | |
| 2533 | /* |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2534 | * First pixel of the framebuffer from |
| 2535 | * the start of the normal gtt mapping. |
| 2536 | */ |
| 2537 | intel_fb->normal[i].x = x; |
| 2538 | intel_fb->normal[i].y = y; |
| 2539 | |
| 2540 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, |
| 2541 | fb, 0, fb->pitches[i], |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 2542 | DRM_ROTATE_0, tile_size); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2543 | offset /= tile_size; |
| 2544 | |
| 2545 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { |
| 2546 | unsigned int tile_width, tile_height; |
| 2547 | unsigned int pitch_tiles; |
| 2548 | struct drm_rect r; |
| 2549 | |
| 2550 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
| 2551 | fb->modifier[i], cpp); |
| 2552 | |
| 2553 | rot_info->plane[i].offset = offset; |
| 2554 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); |
| 2555 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); |
| 2556 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); |
| 2557 | |
| 2558 | intel_fb->rotated[i].pitch = |
| 2559 | rot_info->plane[i].height * tile_height; |
| 2560 | |
| 2561 | /* how many tiles does this plane need */ |
| 2562 | size = rot_info->plane[i].stride * rot_info->plane[i].height; |
| 2563 | /* |
| 2564 | * If the plane isn't horizontally tile aligned, |
| 2565 | * we need one more tile. |
| 2566 | */ |
| 2567 | if (x != 0) |
| 2568 | size++; |
| 2569 | |
| 2570 | /* rotate the x/y offsets to match the GTT view */ |
| 2571 | r.x1 = x; |
| 2572 | r.y1 = y; |
| 2573 | r.x2 = x + width; |
| 2574 | r.y2 = y + height; |
| 2575 | drm_rect_rotate(&r, |
| 2576 | rot_info->plane[i].width * tile_width, |
| 2577 | rot_info->plane[i].height * tile_height, |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 2578 | DRM_ROTATE_270); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2579 | x = r.x1; |
| 2580 | y = r.y1; |
| 2581 | |
| 2582 | /* rotate the tile dimensions to match the GTT view */ |
| 2583 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; |
| 2584 | swap(tile_width, tile_height); |
| 2585 | |
| 2586 | /* |
| 2587 | * We only keep the x/y offsets, so push all of the |
| 2588 | * gtt offset into the x/y offsets. |
| 2589 | */ |
Ville Syrjälä | 66a2d92 | 2016-02-05 18:44:05 +0200 | [diff] [blame] | 2590 | _intel_adjust_tile_offset(&x, &y, tile_size, |
| 2591 | tile_width, tile_height, pitch_tiles, |
| 2592 | gtt_offset_rotated * tile_size, 0); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 2593 | |
| 2594 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; |
| 2595 | |
| 2596 | /* |
| 2597 | * First pixel of the framebuffer from |
| 2598 | * the start of the rotated gtt mapping. |
| 2599 | */ |
| 2600 | intel_fb->rotated[i].x = x; |
| 2601 | intel_fb->rotated[i].y = y; |
| 2602 | } else { |
| 2603 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + |
| 2604 | x * cpp, tile_size); |
| 2605 | } |
| 2606 | |
| 2607 | /* how many tiles in total needed in the bo */ |
| 2608 | max_size = max(max_size, offset + size); |
| 2609 | } |
| 2610 | |
| 2611 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { |
| 2612 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", |
| 2613 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); |
| 2614 | return -EINVAL; |
| 2615 | } |
| 2616 | |
| 2617 | return 0; |
| 2618 | } |
| 2619 | |
Damien Lespiau | b35d63f | 2015-01-20 12:51:50 +0000 | [diff] [blame] | 2620 | static int i9xx_format_to_fourcc(int format) |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2621 | { |
| 2622 | switch (format) { |
| 2623 | case DISPPLANE_8BPP: |
| 2624 | return DRM_FORMAT_C8; |
| 2625 | case DISPPLANE_BGRX555: |
| 2626 | return DRM_FORMAT_XRGB1555; |
| 2627 | case DISPPLANE_BGRX565: |
| 2628 | return DRM_FORMAT_RGB565; |
| 2629 | default: |
| 2630 | case DISPPLANE_BGRX888: |
| 2631 | return DRM_FORMAT_XRGB8888; |
| 2632 | case DISPPLANE_RGBX888: |
| 2633 | return DRM_FORMAT_XBGR8888; |
| 2634 | case DISPPLANE_BGRX101010: |
| 2635 | return DRM_FORMAT_XRGB2101010; |
| 2636 | case DISPPLANE_RGBX101010: |
| 2637 | return DRM_FORMAT_XBGR2101010; |
| 2638 | } |
| 2639 | } |
| 2640 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 2641 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
| 2642 | { |
| 2643 | switch (format) { |
| 2644 | case PLANE_CTL_FORMAT_RGB_565: |
| 2645 | return DRM_FORMAT_RGB565; |
| 2646 | default: |
| 2647 | case PLANE_CTL_FORMAT_XRGB_8888: |
| 2648 | if (rgb_order) { |
| 2649 | if (alpha) |
| 2650 | return DRM_FORMAT_ABGR8888; |
| 2651 | else |
| 2652 | return DRM_FORMAT_XBGR8888; |
| 2653 | } else { |
| 2654 | if (alpha) |
| 2655 | return DRM_FORMAT_ARGB8888; |
| 2656 | else |
| 2657 | return DRM_FORMAT_XRGB8888; |
| 2658 | } |
| 2659 | case PLANE_CTL_FORMAT_XRGB_2101010: |
| 2660 | if (rgb_order) |
| 2661 | return DRM_FORMAT_XBGR2101010; |
| 2662 | else |
| 2663 | return DRM_FORMAT_XRGB2101010; |
| 2664 | } |
| 2665 | } |
| 2666 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 2667 | static bool |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2668 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
| 2669 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2670 | { |
| 2671 | struct drm_device *dev = crtc->base.dev; |
Paulo Zanoni | 3badb49 | 2015-09-23 12:52:23 -0300 | [diff] [blame] | 2672 | struct drm_i915_private *dev_priv = to_i915(dev); |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 2673 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2674 | struct drm_i915_gem_object *obj = NULL; |
| 2675 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 2676 | struct drm_framebuffer *fb = &plane_config->fb->base; |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 2677 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
| 2678 | u32 size_aligned = round_up(plane_config->base + plane_config->size, |
| 2679 | PAGE_SIZE); |
| 2680 | |
| 2681 | size_aligned -= base_aligned; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2682 | |
Chris Wilson | ff2652e | 2014-03-10 08:07:02 +0000 | [diff] [blame] | 2683 | if (plane_config->size == 0) |
| 2684 | return false; |
| 2685 | |
Paulo Zanoni | 3badb49 | 2015-09-23 12:52:23 -0300 | [diff] [blame] | 2686 | /* If the FB is too big, just don't use it since fbdev is not very |
| 2687 | * important and we should probably use that space with FBC or other |
| 2688 | * features. */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 2689 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
Paulo Zanoni | 3badb49 | 2015-09-23 12:52:23 -0300 | [diff] [blame] | 2690 | return false; |
| 2691 | |
Tvrtko Ursulin | 12c83d9 | 2016-02-11 10:27:29 +0000 | [diff] [blame] | 2692 | mutex_lock(&dev->struct_mutex); |
| 2693 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 2694 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
| 2695 | base_aligned, |
| 2696 | base_aligned, |
| 2697 | size_aligned); |
Tvrtko Ursulin | 12c83d9 | 2016-02-11 10:27:29 +0000 | [diff] [blame] | 2698 | if (!obj) { |
| 2699 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2700 | return false; |
Tvrtko Ursulin | 12c83d9 | 2016-02-11 10:27:29 +0000 | [diff] [blame] | 2701 | } |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2702 | |
Chris Wilson | 3e510a8 | 2016-08-05 10:14:23 +0100 | [diff] [blame] | 2703 | if (plane_config->tiling == I915_TILING_X) |
| 2704 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2705 | |
Damien Lespiau | 6bf129d | 2015-02-05 17:22:16 +0000 | [diff] [blame] | 2706 | mode_cmd.pixel_format = fb->pixel_format; |
| 2707 | mode_cmd.width = fb->width; |
| 2708 | mode_cmd.height = fb->height; |
| 2709 | mode_cmd.pitches[0] = fb->pitches[0]; |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 2710 | mode_cmd.modifier[0] = fb->modifier[0]; |
| 2711 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2712 | |
Damien Lespiau | 6bf129d | 2015-02-05 17:22:16 +0000 | [diff] [blame] | 2713 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2714 | &mode_cmd, obj)) { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2715 | DRM_DEBUG_KMS("intel fb init failed\n"); |
| 2716 | goto out_unref_obj; |
| 2717 | } |
Tvrtko Ursulin | 12c83d9 | 2016-02-11 10:27:29 +0000 | [diff] [blame] | 2718 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2719 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2720 | |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2721 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2722 | return true; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2723 | |
| 2724 | out_unref_obj: |
Chris Wilson | f8c417c | 2016-07-20 13:31:53 +0100 | [diff] [blame] | 2725 | i915_gem_object_put(obj); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2726 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2727 | return false; |
| 2728 | } |
| 2729 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 2730 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
| 2731 | static void |
| 2732 | update_state_fb(struct drm_plane *plane) |
| 2733 | { |
| 2734 | if (plane->fb == plane->state->fb) |
| 2735 | return; |
| 2736 | |
| 2737 | if (plane->state->fb) |
| 2738 | drm_framebuffer_unreference(plane->state->fb); |
| 2739 | plane->state->fb = plane->fb; |
| 2740 | if (plane->state->fb) |
| 2741 | drm_framebuffer_reference(plane->state->fb); |
| 2742 | } |
| 2743 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 2744 | static void |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2745 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
| 2746 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2747 | { |
| 2748 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2749 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2750 | struct drm_crtc *c; |
| 2751 | struct intel_crtc *i; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2752 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2753 | struct drm_plane *primary = intel_crtc->base.primary; |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2754 | struct drm_plane_state *plane_state = primary->state; |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 2755 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
| 2756 | struct intel_plane *intel_plane = to_intel_plane(primary); |
Matt Roper | 0a8d8a8 | 2015-12-03 11:37:38 -0800 | [diff] [blame] | 2757 | struct intel_plane_state *intel_state = |
| 2758 | to_intel_plane_state(plane_state); |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2759 | struct drm_framebuffer *fb; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2760 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 2761 | if (!plane_config->fb) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2762 | return; |
| 2763 | |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2764 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2765 | fb = &plane_config->fb->base; |
| 2766 | goto valid_fb; |
Damien Lespiau | f55548b | 2015-02-05 18:30:20 +0000 | [diff] [blame] | 2767 | } |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2768 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 2769 | kfree(plane_config->fb); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2770 | |
| 2771 | /* |
| 2772 | * Failed to alloc the obj, check to see if we should share |
| 2773 | * an fb with another CRTC instead |
| 2774 | */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 2775 | for_each_crtc(dev, c) { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2776 | i = to_intel_crtc(c); |
| 2777 | |
| 2778 | if (c == &intel_crtc->base) |
| 2779 | continue; |
| 2780 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2781 | if (!i->active) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2782 | continue; |
| 2783 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2784 | fb = c->primary->fb; |
| 2785 | if (!fb) |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2786 | continue; |
| 2787 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2788 | obj = intel_fb_obj(fb); |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 2789 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2790 | drm_framebuffer_reference(fb); |
| 2791 | goto valid_fb; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2792 | } |
| 2793 | } |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2794 | |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 2795 | /* |
| 2796 | * We've failed to reconstruct the BIOS FB. Current display state |
| 2797 | * indicates that the primary plane is visible, but has a NULL FB, |
| 2798 | * which will lead to problems later if we don't fix it up. The |
| 2799 | * simplest solution is to just disable the primary plane now and |
| 2800 | * pretend the BIOS never had it enabled. |
| 2801 | */ |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 2802 | to_intel_plane_state(plane_state)->base.visible = false; |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 2803 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 2804 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 2805 | intel_plane->disable_plane(primary, &intel_crtc->base); |
| 2806 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2807 | return; |
| 2808 | |
| 2809 | valid_fb: |
Ville Syrjälä | f44e265 | 2015-11-13 19:16:13 +0200 | [diff] [blame] | 2810 | plane_state->src_x = 0; |
| 2811 | plane_state->src_y = 0; |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2812 | plane_state->src_w = fb->width << 16; |
| 2813 | plane_state->src_h = fb->height << 16; |
| 2814 | |
Ville Syrjälä | f44e265 | 2015-11-13 19:16:13 +0200 | [diff] [blame] | 2815 | plane_state->crtc_x = 0; |
| 2816 | plane_state->crtc_y = 0; |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2817 | plane_state->crtc_w = fb->width; |
| 2818 | plane_state->crtc_h = fb->height; |
| 2819 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 2820 | intel_state->base.src.x1 = plane_state->src_x; |
| 2821 | intel_state->base.src.y1 = plane_state->src_y; |
| 2822 | intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w; |
| 2823 | intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h; |
| 2824 | intel_state->base.dst.x1 = plane_state->crtc_x; |
| 2825 | intel_state->base.dst.y1 = plane_state->crtc_y; |
| 2826 | intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w; |
| 2827 | intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h; |
Matt Roper | 0a8d8a8 | 2015-12-03 11:37:38 -0800 | [diff] [blame] | 2828 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2829 | obj = intel_fb_obj(fb); |
Chris Wilson | 3e510a8 | 2016-08-05 10:14:23 +0100 | [diff] [blame] | 2830 | if (i915_gem_object_is_tiled(obj)) |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2831 | dev_priv->preserve_bios_swizzle = true; |
| 2832 | |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2833 | drm_framebuffer_reference(fb); |
| 2834 | primary->fb = primary->state->fb = fb; |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 2835 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 2836 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
Chris Wilson | faf5bf0 | 2016-08-04 16:32:37 +0100 | [diff] [blame] | 2837 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
| 2838 | &obj->frontbuffer_bits); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2839 | } |
| 2840 | |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2841 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
| 2842 | unsigned int rotation) |
| 2843 | { |
| 2844 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
| 2845 | |
| 2846 | switch (fb->modifier[plane]) { |
| 2847 | case DRM_FORMAT_MOD_NONE: |
| 2848 | case I915_FORMAT_MOD_X_TILED: |
| 2849 | switch (cpp) { |
| 2850 | case 8: |
| 2851 | return 4096; |
| 2852 | case 4: |
| 2853 | case 2: |
| 2854 | case 1: |
| 2855 | return 8192; |
| 2856 | default: |
| 2857 | MISSING_CASE(cpp); |
| 2858 | break; |
| 2859 | } |
| 2860 | break; |
| 2861 | case I915_FORMAT_MOD_Y_TILED: |
| 2862 | case I915_FORMAT_MOD_Yf_TILED: |
| 2863 | switch (cpp) { |
| 2864 | case 8: |
| 2865 | return 2048; |
| 2866 | case 4: |
| 2867 | return 4096; |
| 2868 | case 2: |
| 2869 | case 1: |
| 2870 | return 8192; |
| 2871 | default: |
| 2872 | MISSING_CASE(cpp); |
| 2873 | break; |
| 2874 | } |
| 2875 | break; |
| 2876 | default: |
| 2877 | MISSING_CASE(fb->modifier[plane]); |
| 2878 | } |
| 2879 | |
| 2880 | return 2048; |
| 2881 | } |
| 2882 | |
| 2883 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
| 2884 | { |
| 2885 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); |
| 2886 | const struct drm_framebuffer *fb = plane_state->base.fb; |
| 2887 | unsigned int rotation = plane_state->base.rotation; |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 2888 | int x = plane_state->base.src.x1 >> 16; |
| 2889 | int y = plane_state->base.src.y1 >> 16; |
| 2890 | int w = drm_rect_width(&plane_state->base.src) >> 16; |
| 2891 | int h = drm_rect_height(&plane_state->base.src) >> 16; |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2892 | int max_width = skl_max_plane_width(fb, 0, rotation); |
| 2893 | int max_height = 4096; |
Ville Syrjälä | 8d97065 | 2016-01-28 16:30:28 +0200 | [diff] [blame] | 2894 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2895 | |
| 2896 | if (w > max_width || h > max_height) { |
| 2897 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", |
| 2898 | w, h, max_width, max_height); |
| 2899 | return -EINVAL; |
| 2900 | } |
| 2901 | |
| 2902 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
| 2903 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); |
| 2904 | |
| 2905 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
| 2906 | |
| 2907 | /* |
Ville Syrjälä | 8d97065 | 2016-01-28 16:30:28 +0200 | [diff] [blame] | 2908 | * AUX surface offset is specified as the distance from the |
| 2909 | * main surface offset, and it must be non-negative. Make |
| 2910 | * sure that is what we will get. |
| 2911 | */ |
| 2912 | if (offset > aux_offset) |
| 2913 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, |
| 2914 | offset, aux_offset & ~(alignment - 1)); |
| 2915 | |
| 2916 | /* |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2917 | * When using an X-tiled surface, the plane blows up |
| 2918 | * if the x offset + width exceed the stride. |
| 2919 | * |
| 2920 | * TODO: linear and Y-tiled seem fine, Yf untested, |
| 2921 | */ |
| 2922 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) { |
| 2923 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2924 | |
| 2925 | while ((x + w) * cpp > fb->pitches[0]) { |
| 2926 | if (offset == 0) { |
| 2927 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); |
| 2928 | return -EINVAL; |
| 2929 | } |
| 2930 | |
| 2931 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, |
| 2932 | offset, offset - alignment); |
| 2933 | } |
| 2934 | } |
| 2935 | |
| 2936 | plane_state->main.offset = offset; |
| 2937 | plane_state->main.x = x; |
| 2938 | plane_state->main.y = y; |
| 2939 | |
| 2940 | return 0; |
| 2941 | } |
| 2942 | |
Ville Syrjälä | 8d97065 | 2016-01-28 16:30:28 +0200 | [diff] [blame] | 2943 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
| 2944 | { |
| 2945 | const struct drm_framebuffer *fb = plane_state->base.fb; |
| 2946 | unsigned int rotation = plane_state->base.rotation; |
| 2947 | int max_width = skl_max_plane_width(fb, 1, rotation); |
| 2948 | int max_height = 4096; |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 2949 | int x = plane_state->base.src.x1 >> 17; |
| 2950 | int y = plane_state->base.src.y1 >> 17; |
| 2951 | int w = drm_rect_width(&plane_state->base.src) >> 17; |
| 2952 | int h = drm_rect_height(&plane_state->base.src) >> 17; |
Ville Syrjälä | 8d97065 | 2016-01-28 16:30:28 +0200 | [diff] [blame] | 2953 | u32 offset; |
| 2954 | |
| 2955 | intel_add_fb_offsets(&x, &y, plane_state, 1); |
| 2956 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); |
| 2957 | |
| 2958 | /* FIXME not quite sure how/if these apply to the chroma plane */ |
| 2959 | if (w > max_width || h > max_height) { |
| 2960 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", |
| 2961 | w, h, max_width, max_height); |
| 2962 | return -EINVAL; |
| 2963 | } |
| 2964 | |
| 2965 | plane_state->aux.offset = offset; |
| 2966 | plane_state->aux.x = x; |
| 2967 | plane_state->aux.y = y; |
| 2968 | |
| 2969 | return 0; |
| 2970 | } |
| 2971 | |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2972 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
| 2973 | { |
| 2974 | const struct drm_framebuffer *fb = plane_state->base.fb; |
| 2975 | unsigned int rotation = plane_state->base.rotation; |
| 2976 | int ret; |
| 2977 | |
| 2978 | /* Rotate src coordinates to match rotated GTT view */ |
| 2979 | if (intel_rotation_90_or_270(rotation)) |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 2980 | drm_rect_rotate(&plane_state->base.src, |
| 2981 | fb->width, fb->height, DRM_ROTATE_270); |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2982 | |
Ville Syrjälä | 8d97065 | 2016-01-28 16:30:28 +0200 | [diff] [blame] | 2983 | /* |
| 2984 | * Handle the AUX surface first since |
| 2985 | * the main surface setup depends on it. |
| 2986 | */ |
| 2987 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
| 2988 | ret = skl_check_nv12_aux_surface(plane_state); |
| 2989 | if (ret) |
| 2990 | return ret; |
| 2991 | } else { |
| 2992 | plane_state->aux.offset = ~0xfff; |
| 2993 | plane_state->aux.x = 0; |
| 2994 | plane_state->aux.y = 0; |
| 2995 | } |
| 2996 | |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 2997 | ret = skl_check_main_surface(plane_state); |
| 2998 | if (ret) |
| 2999 | return ret; |
| 3000 | |
| 3001 | return 0; |
| 3002 | } |
| 3003 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3004 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
| 3005 | const struct intel_crtc_state *crtc_state, |
| 3006 | const struct intel_plane_state *plane_state) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3007 | { |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3008 | struct drm_device *dev = primary->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3009 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 3011 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 3012 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3013 | int plane = intel_crtc->plane; |
Ville Syrjälä | 54ea9da | 2016-01-20 21:05:25 +0200 | [diff] [blame] | 3014 | u32 linear_offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3015 | u32 dspcntr; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3016 | i915_reg_t reg = DSPCNTR(plane); |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 3017 | unsigned int rotation = plane_state->base.rotation; |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 3018 | int x = plane_state->base.src.x1 >> 16; |
| 3019 | int y = plane_state->base.src.y1 >> 16; |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame] | 3020 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3021 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 3022 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 3023 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3024 | |
| 3025 | if (INTEL_INFO(dev)->gen < 4) { |
| 3026 | if (intel_crtc->pipe == PIPE_B) |
| 3027 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 3028 | |
| 3029 | /* pipesrc and dspsize control the size that is scaled from, |
| 3030 | * which should always be the user's requested size. |
| 3031 | */ |
| 3032 | I915_WRITE(DSPSIZE(plane), |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3033 | ((crtc_state->pipe_src_h - 1) << 16) | |
| 3034 | (crtc_state->pipe_src_w - 1)); |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3035 | I915_WRITE(DSPPOS(plane), 0); |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 3036 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
| 3037 | I915_WRITE(PRIMSIZE(plane), |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3038 | ((crtc_state->pipe_src_h - 1) << 16) | |
| 3039 | (crtc_state->pipe_src_w - 1)); |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 3040 | I915_WRITE(PRIMPOS(plane), 0); |
| 3041 | I915_WRITE(PRIMCNSTALPHA(plane), 0); |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3042 | } |
| 3043 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3044 | switch (fb->pixel_format) { |
| 3045 | case DRM_FORMAT_C8: |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3046 | dspcntr |= DISPPLANE_8BPP; |
| 3047 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3048 | case DRM_FORMAT_XRGB1555: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3049 | dspcntr |= DISPPLANE_BGRX555; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3050 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3051 | case DRM_FORMAT_RGB565: |
| 3052 | dspcntr |= DISPPLANE_BGRX565; |
| 3053 | break; |
| 3054 | case DRM_FORMAT_XRGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3055 | dspcntr |= DISPPLANE_BGRX888; |
| 3056 | break; |
| 3057 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3058 | dspcntr |= DISPPLANE_RGBX888; |
| 3059 | break; |
| 3060 | case DRM_FORMAT_XRGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3061 | dspcntr |= DISPPLANE_BGRX101010; |
| 3062 | break; |
| 3063 | case DRM_FORMAT_XBGR2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3064 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3065 | break; |
| 3066 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 3067 | BUG(); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3068 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3069 | |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 3070 | if (INTEL_GEN(dev_priv) >= 4 && |
| 3071 | fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3072 | dspcntr |= DISPPLANE_TILED; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3073 | |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 3074 | if (IS_G4X(dev)) |
| 3075 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 3076 | |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 3077 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3078 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3079 | if (INTEL_INFO(dev)->gen >= 4) |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 3080 | intel_crtc->dspaddr_offset = |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 3081 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 3082 | |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 3083 | if (rotation == DRM_ROTATE_180) { |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 3084 | dspcntr |= DISPPLANE_ROTATE_180; |
| 3085 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3086 | x += (crtc_state->pipe_src_w - 1); |
| 3087 | y += (crtc_state->pipe_src_h - 1); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 3088 | } |
| 3089 | |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 3090 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3091 | |
| 3092 | if (INTEL_INFO(dev)->gen < 4) |
| 3093 | intel_crtc->dspaddr_offset = linear_offset; |
| 3094 | |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 3095 | intel_crtc->adjusted_x = x; |
| 3096 | intel_crtc->adjusted_y = y; |
| 3097 | |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 3098 | I915_WRITE(reg, dspcntr); |
| 3099 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 3100 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3101 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 3102 | I915_WRITE(DSPSURF(plane), |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3103 | intel_fb_gtt_offset(fb, rotation) + |
| 3104 | intel_crtc->dspaddr_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3105 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 3106 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3107 | } else |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 3108 | I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3109 | POSTING_READ(reg); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3110 | } |
| 3111 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3112 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
| 3113 | struct drm_crtc *crtc) |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3114 | { |
| 3115 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3116 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3118 | int plane = intel_crtc->plane; |
| 3119 | |
| 3120 | I915_WRITE(DSPCNTR(plane), 0); |
| 3121 | if (INTEL_INFO(dev_priv)->gen >= 4) |
| 3122 | I915_WRITE(DSPSURF(plane), 0); |
| 3123 | else |
| 3124 | I915_WRITE(DSPADDR(plane), 0); |
| 3125 | POSTING_READ(DSPCNTR(plane)); |
| 3126 | } |
| 3127 | |
| 3128 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
| 3129 | const struct intel_crtc_state *crtc_state, |
| 3130 | const struct intel_plane_state *plane_state) |
| 3131 | { |
| 3132 | struct drm_device *dev = primary->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3133 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 3135 | struct drm_framebuffer *fb = plane_state->base.fb; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3136 | int plane = intel_crtc->plane; |
Ville Syrjälä | 54ea9da | 2016-01-20 21:05:25 +0200 | [diff] [blame] | 3137 | u32 linear_offset; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3138 | u32 dspcntr; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3139 | i915_reg_t reg = DSPCNTR(plane); |
Ville Syrjälä | 8d0deca | 2016-02-15 22:54:41 +0200 | [diff] [blame] | 3140 | unsigned int rotation = plane_state->base.rotation; |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 3141 | int x = plane_state->base.src.x1 >> 16; |
| 3142 | int y = plane_state->base.src.y1 >> 16; |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame] | 3143 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3144 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 3145 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3146 | |
| 3147 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 3148 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
| 3149 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3150 | switch (fb->pixel_format) { |
| 3151 | case DRM_FORMAT_C8: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3152 | dspcntr |= DISPPLANE_8BPP; |
| 3153 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3154 | case DRM_FORMAT_RGB565: |
| 3155 | dspcntr |= DISPPLANE_BGRX565; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3156 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3157 | case DRM_FORMAT_XRGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3158 | dspcntr |= DISPPLANE_BGRX888; |
| 3159 | break; |
| 3160 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3161 | dspcntr |= DISPPLANE_RGBX888; |
| 3162 | break; |
| 3163 | case DRM_FORMAT_XRGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3164 | dspcntr |= DISPPLANE_BGRX101010; |
| 3165 | break; |
| 3166 | case DRM_FORMAT_XBGR2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 3167 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3168 | break; |
| 3169 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 3170 | BUG(); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3171 | } |
| 3172 | |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 3173 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3174 | dspcntr |= DISPPLANE_TILED; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3175 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 3176 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
Paulo Zanoni | 1f5d76d | 2013-08-23 19:51:28 -0300 | [diff] [blame] | 3177 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3178 | |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 3179 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3180 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 3181 | intel_crtc->dspaddr_offset = |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 3182 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3183 | |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 3184 | if (rotation == DRM_ROTATE_180) { |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 3185 | dspcntr |= DISPPLANE_ROTATE_180; |
| 3186 | |
| 3187 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3188 | x += (crtc_state->pipe_src_w - 1); |
| 3189 | y += (crtc_state->pipe_src_h - 1); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 3190 | } |
| 3191 | } |
| 3192 | |
Ville Syrjälä | 2949056 | 2016-01-20 18:02:50 +0200 | [diff] [blame] | 3193 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3194 | |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 3195 | intel_crtc->adjusted_x = x; |
| 3196 | intel_crtc->adjusted_y = y; |
| 3197 | |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 3198 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3199 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 3200 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 3201 | I915_WRITE(DSPSURF(plane), |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3202 | intel_fb_gtt_offset(fb, rotation) + |
| 3203 | intel_crtc->dspaddr_offset); |
Paulo Zanoni | b3dc685 | 2013-11-02 21:07:33 -0700 | [diff] [blame] | 3204 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Damien Lespiau | bc1c91e | 2012-10-29 12:14:21 +0000 | [diff] [blame] | 3205 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
| 3206 | } else { |
| 3207 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 3208 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
| 3209 | } |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3210 | POSTING_READ(reg); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3211 | } |
| 3212 | |
Ville Syrjälä | 7b49f94 | 2016-01-12 21:08:32 +0200 | [diff] [blame] | 3213 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
| 3214 | uint64_t fb_modifier, uint32_t pixel_format) |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 3215 | { |
Ville Syrjälä | 7b49f94 | 2016-01-12 21:08:32 +0200 | [diff] [blame] | 3216 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
| 3217 | return 64; |
| 3218 | } else { |
| 3219 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 3220 | |
Ville Syrjälä | 27ba391 | 2016-02-15 22:54:40 +0200 | [diff] [blame] | 3221 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 3222 | } |
| 3223 | } |
| 3224 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3225 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
| 3226 | unsigned int rotation) |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 3227 | { |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3228 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Daniel Vetter | ce7f172 | 2015-10-14 16:51:06 +0200 | [diff] [blame] | 3229 | struct i915_ggtt_view view; |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 3230 | struct i915_vma *vma; |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 3231 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3232 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 3233 | |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 3234 | vma = i915_gem_object_to_ggtt(obj, &view); |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 3235 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 3236 | view.type)) |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 3237 | return -1; |
| 3238 | |
Chris Wilson | bde13eb | 2016-08-15 10:49:07 +0100 | [diff] [blame] | 3239 | return i915_ggtt_offset(vma); |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 3240 | } |
| 3241 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 3242 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
| 3243 | { |
| 3244 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3245 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 3246 | |
| 3247 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); |
| 3248 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); |
| 3249 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 3250 | } |
| 3251 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 3252 | /* |
| 3253 | * This function detaches (aka. unbinds) unused scalers in hardware |
| 3254 | */ |
Maarten Lankhorst | 0583236 | 2015-06-15 12:33:48 +0200 | [diff] [blame] | 3255 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 3256 | { |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 3257 | struct intel_crtc_scaler_state *scaler_state; |
| 3258 | int i; |
| 3259 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 3260 | scaler_state = &intel_crtc->config->scaler_state; |
| 3261 | |
| 3262 | /* loop through and disable scalers that aren't in use */ |
| 3263 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 3264 | if (!scaler_state->scalers[i].in_use) |
| 3265 | skl_detach_scaler(intel_crtc, i); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 3266 | } |
| 3267 | } |
| 3268 | |
Ville Syrjälä | d219677 | 2016-01-28 18:33:11 +0200 | [diff] [blame] | 3269 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
| 3270 | unsigned int rotation) |
| 3271 | { |
| 3272 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
| 3273 | u32 stride = intel_fb_pitch(fb, plane, rotation); |
| 3274 | |
| 3275 | /* |
| 3276 | * The stride is either expressed as a multiple of 64 bytes chunks for |
| 3277 | * linear buffers or in number of tiles for tiled buffers. |
| 3278 | */ |
| 3279 | if (intel_rotation_90_or_270(rotation)) { |
| 3280 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
| 3281 | |
| 3282 | stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp); |
| 3283 | } else { |
| 3284 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
| 3285 | fb->pixel_format); |
| 3286 | } |
| 3287 | |
| 3288 | return stride; |
| 3289 | } |
| 3290 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3291 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
| 3292 | { |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3293 | switch (pixel_format) { |
Damien Lespiau | d161cf7 | 2015-05-12 16:13:17 +0100 | [diff] [blame] | 3294 | case DRM_FORMAT_C8: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3295 | return PLANE_CTL_FORMAT_INDEXED; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3296 | case DRM_FORMAT_RGB565: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3297 | return PLANE_CTL_FORMAT_RGB_565; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3298 | case DRM_FORMAT_XBGR8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3299 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3300 | case DRM_FORMAT_XRGB8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3301 | return PLANE_CTL_FORMAT_XRGB_8888; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3302 | /* |
| 3303 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers |
| 3304 | * to be already pre-multiplied. We need to add a knob (or a different |
| 3305 | * DRM_FORMAT) for user-space to configure that. |
| 3306 | */ |
| 3307 | case DRM_FORMAT_ABGR8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3308 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3309 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3310 | case DRM_FORMAT_ARGB8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3311 | return PLANE_CTL_FORMAT_XRGB_8888 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3312 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3313 | case DRM_FORMAT_XRGB2101010: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3314 | return PLANE_CTL_FORMAT_XRGB_2101010; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3315 | case DRM_FORMAT_XBGR2101010: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3316 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3317 | case DRM_FORMAT_YUYV: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3318 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3319 | case DRM_FORMAT_YVYU: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3320 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3321 | case DRM_FORMAT_UYVY: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3322 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3323 | case DRM_FORMAT_VYUY: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3324 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3325 | default: |
Damien Lespiau | 4249eee | 2015-05-12 16:13:16 +0100 | [diff] [blame] | 3326 | MISSING_CASE(pixel_format); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3327 | } |
Damien Lespiau | 8cfcba4 | 2015-05-12 16:13:14 +0100 | [diff] [blame] | 3328 | |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3329 | return 0; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3330 | } |
| 3331 | |
| 3332 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
| 3333 | { |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3334 | switch (fb_modifier) { |
| 3335 | case DRM_FORMAT_MOD_NONE: |
| 3336 | break; |
| 3337 | case I915_FORMAT_MOD_X_TILED: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3338 | return PLANE_CTL_TILED_X; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3339 | case I915_FORMAT_MOD_Y_TILED: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3340 | return PLANE_CTL_TILED_Y; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3341 | case I915_FORMAT_MOD_Yf_TILED: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3342 | return PLANE_CTL_TILED_YF; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3343 | default: |
| 3344 | MISSING_CASE(fb_modifier); |
| 3345 | } |
Damien Lespiau | 8cfcba4 | 2015-05-12 16:13:14 +0100 | [diff] [blame] | 3346 | |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3347 | return 0; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3348 | } |
| 3349 | |
| 3350 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
| 3351 | { |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3352 | switch (rotation) { |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 3353 | case DRM_ROTATE_0: |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3354 | break; |
Sonika Jindal | 1e8df16 | 2015-05-20 13:40:48 +0530 | [diff] [blame] | 3355 | /* |
| 3356 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr |
| 3357 | * while i915 HW rotation is clockwise, thats why this swapping. |
| 3358 | */ |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 3359 | case DRM_ROTATE_90: |
Sonika Jindal | 1e8df16 | 2015-05-20 13:40:48 +0530 | [diff] [blame] | 3360 | return PLANE_CTL_ROTATE_270; |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 3361 | case DRM_ROTATE_180: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3362 | return PLANE_CTL_ROTATE_180; |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 3363 | case DRM_ROTATE_270: |
Sonika Jindal | 1e8df16 | 2015-05-20 13:40:48 +0530 | [diff] [blame] | 3364 | return PLANE_CTL_ROTATE_90; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3365 | default: |
| 3366 | MISSING_CASE(rotation); |
| 3367 | } |
| 3368 | |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3369 | return 0; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3370 | } |
| 3371 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3372 | static void skylake_update_primary_plane(struct drm_plane *plane, |
| 3373 | const struct intel_crtc_state *crtc_state, |
| 3374 | const struct intel_plane_state *plane_state) |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3375 | { |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3376 | struct drm_device *dev = plane->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3377 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 3379 | struct drm_framebuffer *fb = plane_state->base.fb; |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 3380 | const struct skl_wm_values *wm = &dev_priv->wm.skl_results; |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3381 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | d219677 | 2016-01-28 18:33:11 +0200 | [diff] [blame] | 3382 | u32 plane_ctl; |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3383 | unsigned int rotation = plane_state->base.rotation; |
Ville Syrjälä | d219677 | 2016-01-28 18:33:11 +0200 | [diff] [blame] | 3384 | u32 stride = skl_plane_stride(fb, 0, rotation); |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 3385 | u32 surf_addr = plane_state->main.offset; |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3386 | int scaler_id = plane_state->scaler_id; |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 3387 | int src_x = plane_state->main.x; |
| 3388 | int src_y = plane_state->main.y; |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 3389 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
| 3390 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; |
| 3391 | int dst_x = plane_state->base.dst.x1; |
| 3392 | int dst_y = plane_state->base.dst.y1; |
| 3393 | int dst_w = drm_rect_width(&plane_state->base.dst); |
| 3394 | int dst_h = drm_rect_height(&plane_state->base.dst); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3395 | |
| 3396 | plane_ctl = PLANE_CTL_ENABLE | |
| 3397 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
| 3398 | PLANE_CTL_PIPE_CSC_ENABLE; |
| 3399 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3400 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
| 3401 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3402 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3403 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3404 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3405 | /* Sizes are 0 based */ |
| 3406 | src_w--; |
| 3407 | src_h--; |
| 3408 | dst_w--; |
| 3409 | dst_h--; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3410 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3411 | intel_crtc->adjusted_x = src_x; |
| 3412 | intel_crtc->adjusted_y = src_y; |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 3413 | |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 3414 | if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) |
| 3415 | skl_write_plane_wm(intel_crtc, wm, 0); |
| 3416 | |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3417 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3418 | I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3419 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3420 | I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3421 | |
| 3422 | if (scaler_id >= 0) { |
| 3423 | uint32_t ps_ctrl = 0; |
| 3424 | |
| 3425 | WARN_ON(!dst_w || !dst_h); |
| 3426 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | |
| 3427 | crtc_state->scaler_state.scalers[scaler_id].mode; |
| 3428 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
| 3429 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
| 3430 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); |
| 3431 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); |
| 3432 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
| 3433 | } else { |
| 3434 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); |
| 3435 | } |
| 3436 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 3437 | I915_WRITE(PLANE_SURF(pipe, 0), |
| 3438 | intel_fb_gtt_offset(fb, rotation) + surf_addr); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3439 | |
| 3440 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 3441 | } |
| 3442 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3443 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
| 3444 | struct drm_crtc *crtc) |
| 3445 | { |
| 3446 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3447 | struct drm_i915_private *dev_priv = to_i915(dev); |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 3448 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3449 | int pipe = intel_crtc->pipe; |
| 3450 | |
Lyude | ccebc23 | 2016-08-29 12:31:27 -0400 | [diff] [blame] | 3451 | /* |
| 3452 | * We only populate skl_results on watermark updates, and if the |
| 3453 | * plane's visiblity isn't actually changing neither is its watermarks. |
| 3454 | */ |
| 3455 | if (!crtc->primary->state->visible) |
| 3456 | skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3457 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3458 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
| 3459 | I915_WRITE(PLANE_SURF(pipe, 0), 0); |
| 3460 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 3461 | } |
| 3462 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3463 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 3464 | static int |
| 3465 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 3466 | int x, int y, enum mode_set_atomic state) |
| 3467 | { |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3468 | /* Support for kgdboc is disabled, this needs a major rework. */ |
| 3469 | DRM_ERROR("legacy panic handler not supported any more.\n"); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3470 | |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3471 | return -ENODEV; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3472 | } |
| 3473 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 3474 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
| 3475 | { |
| 3476 | struct intel_crtc *crtc; |
| 3477 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 3478 | for_each_intel_crtc(&dev_priv->drm, crtc) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 3479 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
| 3480 | } |
| 3481 | |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3482 | static void intel_update_primary_planes(struct drm_device *dev) |
| 3483 | { |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3484 | struct drm_crtc *crtc; |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3485 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 3486 | for_each_crtc(dev, crtc) { |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3487 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3488 | struct intel_plane_state *plane_state = |
| 3489 | to_intel_plane_state(plane->base.state); |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3490 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 3491 | if (plane_state->base.visible) |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 3492 | plane->update_plane(&plane->base, |
| 3493 | to_intel_crtc_state(crtc->state), |
| 3494 | plane_state); |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3495 | } |
| 3496 | } |
| 3497 | |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3498 | static int |
| 3499 | __intel_display_resume(struct drm_device *dev, |
| 3500 | struct drm_atomic_state *state) |
| 3501 | { |
| 3502 | struct drm_crtc_state *crtc_state; |
| 3503 | struct drm_crtc *crtc; |
| 3504 | int i, ret; |
| 3505 | |
| 3506 | intel_modeset_setup_hw_state(dev); |
| 3507 | i915_redisable_vga(dev); |
| 3508 | |
| 3509 | if (!state) |
| 3510 | return 0; |
| 3511 | |
| 3512 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 3513 | /* |
| 3514 | * Force recalculation even if we restore |
| 3515 | * current state. With fast modeset this may not result |
| 3516 | * in a modeset when the state is compatible. |
| 3517 | */ |
| 3518 | crtc_state->mode_changed = true; |
| 3519 | } |
| 3520 | |
| 3521 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
| 3522 | to_intel_atomic_state(state)->skip_intermediate_wm = true; |
| 3523 | |
| 3524 | ret = drm_atomic_commit(state); |
| 3525 | |
| 3526 | WARN_ON(ret == -EDEADLK); |
| 3527 | return ret; |
| 3528 | } |
| 3529 | |
Ville Syrjälä | 4ac2ba2 | 2016-08-05 23:28:29 +0300 | [diff] [blame] | 3530 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
| 3531 | { |
Ville Syrjälä | ae98104 | 2016-08-05 23:28:30 +0300 | [diff] [blame] | 3532 | return intel_has_gpu_reset(dev_priv) && |
| 3533 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); |
Ville Syrjälä | 4ac2ba2 | 2016-08-05 23:28:29 +0300 | [diff] [blame] | 3534 | } |
| 3535 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3536 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3537 | { |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3538 | struct drm_device *dev = &dev_priv->drm; |
| 3539 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; |
| 3540 | struct drm_atomic_state *state; |
| 3541 | int ret; |
| 3542 | |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3543 | /* |
| 3544 | * Need mode_config.mutex so that we don't |
| 3545 | * trample ongoing ->detect() and whatnot. |
| 3546 | */ |
| 3547 | mutex_lock(&dev->mode_config.mutex); |
| 3548 | drm_modeset_acquire_init(ctx, 0); |
| 3549 | while (1) { |
| 3550 | ret = drm_modeset_lock_all_ctx(dev, ctx); |
| 3551 | if (ret != -EDEADLK) |
| 3552 | break; |
| 3553 | |
| 3554 | drm_modeset_backoff(ctx); |
| 3555 | } |
| 3556 | |
| 3557 | /* reset doesn't touch the display, but flips might get nuked anyway, */ |
Maarten Lankhorst | 522a63d | 2016-08-05 23:28:28 +0300 | [diff] [blame] | 3558 | if (!i915.force_reset_modeset_test && |
Ville Syrjälä | 4ac2ba2 | 2016-08-05 23:28:29 +0300 | [diff] [blame] | 3559 | !gpu_reset_clobbers_display(dev_priv)) |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3560 | return; |
| 3561 | |
Ville Syrjälä | f98ce92 | 2014-11-21 21:54:30 +0200 | [diff] [blame] | 3562 | /* |
| 3563 | * Disabling the crtcs gracefully seems nicer. Also the |
| 3564 | * g33 docs say we should at least disable all the planes. |
| 3565 | */ |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3566 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
| 3567 | if (IS_ERR(state)) { |
| 3568 | ret = PTR_ERR(state); |
| 3569 | state = NULL; |
| 3570 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
| 3571 | goto err; |
| 3572 | } |
| 3573 | |
| 3574 | ret = drm_atomic_helper_disable_all(dev, ctx); |
| 3575 | if (ret) { |
| 3576 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
| 3577 | goto err; |
| 3578 | } |
| 3579 | |
| 3580 | dev_priv->modeset_restore_state = state; |
| 3581 | state->acquire_ctx = ctx; |
| 3582 | return; |
| 3583 | |
| 3584 | err: |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 3585 | drm_atomic_state_put(state); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3586 | } |
| 3587 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3588 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3589 | { |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3590 | struct drm_device *dev = &dev_priv->drm; |
| 3591 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; |
| 3592 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; |
| 3593 | int ret; |
| 3594 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 3595 | /* |
| 3596 | * Flips in the rings will be nuked by the reset, |
| 3597 | * so complete all pending flips so that user space |
| 3598 | * will get its events and not get stuck. |
| 3599 | */ |
| 3600 | intel_complete_page_flips(dev_priv); |
| 3601 | |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3602 | dev_priv->modeset_restore_state = NULL; |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3603 | |
Maarten Lankhorst | dfa2997 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3604 | dev_priv->modeset_restore_state = NULL; |
| 3605 | |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3606 | /* reset doesn't touch the display */ |
Ville Syrjälä | 4ac2ba2 | 2016-08-05 23:28:29 +0300 | [diff] [blame] | 3607 | if (!gpu_reset_clobbers_display(dev_priv)) { |
Maarten Lankhorst | 522a63d | 2016-08-05 23:28:28 +0300 | [diff] [blame] | 3608 | if (!state) { |
| 3609 | /* |
| 3610 | * Flips in the rings have been nuked by the reset, |
| 3611 | * so update the base address of all primary |
| 3612 | * planes to the the last fb to make sure we're |
| 3613 | * showing the correct fb after a reset. |
| 3614 | * |
| 3615 | * FIXME: Atomic will make this obsolete since we won't schedule |
| 3616 | * CS-based flips (which might get lost in gpu resets) any more. |
| 3617 | */ |
| 3618 | intel_update_primary_planes(dev); |
| 3619 | } else { |
| 3620 | ret = __intel_display_resume(dev, state); |
| 3621 | if (ret) |
| 3622 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
| 3623 | } |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3624 | } else { |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3625 | /* |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3626 | * The display has been reset as well, |
| 3627 | * so need a full re-initialization. |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3628 | */ |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3629 | intel_runtime_pm_disable_interrupts(dev_priv); |
| 3630 | intel_runtime_pm_enable_interrupts(dev_priv); |
| 3631 | |
| 3632 | intel_modeset_init_hw(dev); |
| 3633 | |
| 3634 | spin_lock_irq(&dev_priv->irq_lock); |
| 3635 | if (dev_priv->display.hpd_irq_setup) |
| 3636 | dev_priv->display.hpd_irq_setup(dev_priv); |
| 3637 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3638 | |
| 3639 | ret = __intel_display_resume(dev, state); |
| 3640 | if (ret) |
| 3641 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
| 3642 | |
| 3643 | intel_hpd_init(dev_priv); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3644 | } |
| 3645 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 3646 | if (state) |
| 3647 | drm_atomic_state_put(state); |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 3648 | drm_modeset_drop_locks(ctx); |
| 3649 | drm_modeset_acquire_fini(ctx); |
| 3650 | mutex_unlock(&dev->mode_config.mutex); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3651 | } |
| 3652 | |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 3653 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
| 3654 | { |
| 3655 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; |
| 3656 | |
| 3657 | if (i915_reset_in_progress(error)) |
| 3658 | return true; |
| 3659 | |
| 3660 | if (crtc->reset_count != i915_reset_count(error)) |
| 3661 | return true; |
| 3662 | |
| 3663 | return false; |
| 3664 | } |
| 3665 | |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 3666 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
| 3667 | { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 3668 | struct drm_device *dev = crtc->dev; |
| 3669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 3670 | bool pending; |
| 3671 | |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 3672 | if (abort_flip_on_reset(intel_crtc)) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 3673 | return false; |
| 3674 | |
| 3675 | spin_lock_irq(&dev->event_lock); |
| 3676 | pending = to_intel_crtc(crtc)->flip_work != NULL; |
| 3677 | spin_unlock_irq(&dev->event_lock); |
| 3678 | |
| 3679 | return pending; |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 3680 | } |
| 3681 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3682 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
| 3683 | struct intel_crtc_state *old_crtc_state) |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3684 | { |
| 3685 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3686 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3687 | struct intel_crtc_state *pipe_config = |
| 3688 | to_intel_crtc_state(crtc->base.state); |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3689 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3690 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
| 3691 | crtc->base.mode = crtc->base.state->mode; |
| 3692 | |
| 3693 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", |
| 3694 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, |
| 3695 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3696 | |
| 3697 | /* |
| 3698 | * Update pipe size and adjust fitter if needed: the reason for this is |
| 3699 | * that in compute_mode_changes we check the native mode (not the pfit |
| 3700 | * mode) to see if we can flip rather than do a full mode set. In the |
| 3701 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
| 3702 | * pfit state, we'll end up with a big fb scanned out into the wrong |
| 3703 | * sized surface. |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3704 | */ |
| 3705 | |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3706 | I915_WRITE(PIPESRC(crtc->pipe), |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3707 | ((pipe_config->pipe_src_w - 1) << 16) | |
| 3708 | (pipe_config->pipe_src_h - 1)); |
| 3709 | |
| 3710 | /* on skylake this is done by detaching scalers */ |
| 3711 | if (INTEL_INFO(dev)->gen >= 9) { |
| 3712 | skl_detach_scalers(crtc); |
| 3713 | |
| 3714 | if (pipe_config->pch_pfit.enabled) |
| 3715 | skylake_pfit_enable(crtc); |
| 3716 | } else if (HAS_PCH_SPLIT(dev)) { |
| 3717 | if (pipe_config->pch_pfit.enabled) |
| 3718 | ironlake_pfit_enable(crtc); |
| 3719 | else if (old_crtc_state->pch_pfit.enabled) |
| 3720 | ironlake_pfit_disable(crtc, true); |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3721 | } |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3722 | } |
| 3723 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3724 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 3725 | { |
| 3726 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3727 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3728 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3729 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3730 | i915_reg_t reg; |
| 3731 | u32 temp; |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3732 | |
| 3733 | /* enable normal train */ |
| 3734 | reg = FDI_TX_CTL(pipe); |
| 3735 | temp = I915_READ(reg); |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 3736 | if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3737 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 3738 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 3739 | } else { |
| 3740 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3741 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3742 | } |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3743 | I915_WRITE(reg, temp); |
| 3744 | |
| 3745 | reg = FDI_RX_CTL(pipe); |
| 3746 | temp = I915_READ(reg); |
| 3747 | if (HAS_PCH_CPT(dev)) { |
| 3748 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3749 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 3750 | } else { |
| 3751 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3752 | temp |= FDI_LINK_TRAIN_NONE; |
| 3753 | } |
| 3754 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 3755 | |
| 3756 | /* wait one idle pattern time */ |
| 3757 | POSTING_READ(reg); |
| 3758 | udelay(1000); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3759 | |
| 3760 | /* IVB wants error correction enabled */ |
| 3761 | if (IS_IVYBRIDGE(dev)) |
| 3762 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 3763 | FDI_FE_ERRC_ENABLE); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3764 | } |
| 3765 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3766 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 3767 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 3768 | { |
| 3769 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3770 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3772 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3773 | i915_reg_t reg; |
| 3774 | u32 temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3775 | |
Ville Syrjälä | 1c8562f | 2014-04-25 22:12:07 +0300 | [diff] [blame] | 3776 | /* FDI needs bits from pipe first */ |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3777 | assert_pipe_enabled(dev_priv, pipe); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3778 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3779 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3780 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3781 | reg = FDI_RX_IMR(pipe); |
| 3782 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3783 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3784 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3785 | I915_WRITE(reg, temp); |
| 3786 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3787 | udelay(150); |
| 3788 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3789 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3790 | reg = FDI_TX_CTL(pipe); |
| 3791 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3792 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3793 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3794 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3795 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3796 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3797 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3798 | reg = FDI_RX_CTL(pipe); |
| 3799 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3800 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3801 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3802 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3803 | |
| 3804 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3805 | udelay(150); |
| 3806 | |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 3807 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
Daniel Vetter | 8f5718a | 2012-10-31 22:52:28 +0100 | [diff] [blame] | 3808 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 3809 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 3810 | FDI_RX_PHASE_SYNC_POINTER_EN); |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 3811 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3812 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3813 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3814 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3815 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3816 | |
| 3817 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 3818 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3819 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3820 | break; |
| 3821 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3822 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3823 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3824 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3825 | |
| 3826 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3827 | reg = FDI_TX_CTL(pipe); |
| 3828 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3829 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3830 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3831 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3832 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3833 | reg = FDI_RX_CTL(pipe); |
| 3834 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3835 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3836 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3837 | I915_WRITE(reg, temp); |
| 3838 | |
| 3839 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3840 | udelay(150); |
| 3841 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3842 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3843 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3844 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3845 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3846 | |
| 3847 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3848 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3849 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3850 | break; |
| 3851 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3852 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3853 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3854 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3855 | |
| 3856 | DRM_DEBUG_KMS("FDI train done\n"); |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 3857 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3858 | } |
| 3859 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3860 | static const int snb_b_fdi_train_param[] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3861 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 3862 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 3863 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 3864 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 3865 | }; |
| 3866 | |
| 3867 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 3868 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 3869 | { |
| 3870 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3871 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3873 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3874 | i915_reg_t reg; |
| 3875 | u32 temp, i, retry; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3876 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3877 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3878 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3879 | reg = FDI_RX_IMR(pipe); |
| 3880 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3881 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3882 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3883 | I915_WRITE(reg, temp); |
| 3884 | |
| 3885 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3886 | udelay(150); |
| 3887 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3888 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3889 | reg = FDI_TX_CTL(pipe); |
| 3890 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3891 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3892 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3893 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3894 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3895 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3896 | /* SNB-B */ |
| 3897 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3898 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3899 | |
Daniel Vetter | d74cf32 | 2012-10-26 10:58:13 +0200 | [diff] [blame] | 3900 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3901 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3902 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3903 | reg = FDI_RX_CTL(pipe); |
| 3904 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3905 | if (HAS_PCH_CPT(dev)) { |
| 3906 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3907 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3908 | } else { |
| 3909 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3910 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3911 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3912 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3913 | |
| 3914 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3915 | udelay(150); |
| 3916 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3917 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3918 | reg = FDI_TX_CTL(pipe); |
| 3919 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3920 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3921 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3922 | I915_WRITE(reg, temp); |
| 3923 | |
| 3924 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3925 | udelay(500); |
| 3926 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3927 | for (retry = 0; retry < 5; retry++) { |
| 3928 | reg = FDI_RX_IIR(pipe); |
| 3929 | temp = I915_READ(reg); |
| 3930 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3931 | if (temp & FDI_RX_BIT_LOCK) { |
| 3932 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3933 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 3934 | break; |
| 3935 | } |
| 3936 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3937 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3938 | if (retry < 5) |
| 3939 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3940 | } |
| 3941 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3942 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3943 | |
| 3944 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3945 | reg = FDI_TX_CTL(pipe); |
| 3946 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3947 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3948 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3949 | if (IS_GEN6(dev)) { |
| 3950 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3951 | /* SNB-B */ |
| 3952 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 3953 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3954 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3955 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3956 | reg = FDI_RX_CTL(pipe); |
| 3957 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3958 | if (HAS_PCH_CPT(dev)) { |
| 3959 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3960 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 3961 | } else { |
| 3962 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3963 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3964 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3965 | I915_WRITE(reg, temp); |
| 3966 | |
| 3967 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3968 | udelay(150); |
| 3969 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3970 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3971 | reg = FDI_TX_CTL(pipe); |
| 3972 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3973 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3974 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3975 | I915_WRITE(reg, temp); |
| 3976 | |
| 3977 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3978 | udelay(500); |
| 3979 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3980 | for (retry = 0; retry < 5; retry++) { |
| 3981 | reg = FDI_RX_IIR(pipe); |
| 3982 | temp = I915_READ(reg); |
| 3983 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3984 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 3985 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3986 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3987 | break; |
| 3988 | } |
| 3989 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3990 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3991 | if (retry < 5) |
| 3992 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3993 | } |
| 3994 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3995 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3996 | |
| 3997 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3998 | } |
| 3999 | |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4000 | /* Manual link training for Ivy Bridge A0 parts */ |
| 4001 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 4002 | { |
| 4003 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4004 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4006 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4007 | i915_reg_t reg; |
| 4008 | u32 temp, i, j; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4009 | |
| 4010 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 4011 | for train result */ |
| 4012 | reg = FDI_RX_IMR(pipe); |
| 4013 | temp = I915_READ(reg); |
| 4014 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 4015 | temp &= ~FDI_RX_BIT_LOCK; |
| 4016 | I915_WRITE(reg, temp); |
| 4017 | |
| 4018 | POSTING_READ(reg); |
| 4019 | udelay(150); |
| 4020 | |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 4021 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
| 4022 | I915_READ(FDI_RX_IIR(pipe))); |
| 4023 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4024 | /* Try each vswing and preemphasis setting twice before moving on */ |
| 4025 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
| 4026 | /* disable first in case we need to retry */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4027 | reg = FDI_TX_CTL(pipe); |
| 4028 | temp = I915_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4029 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 4030 | temp &= ~FDI_TX_ENABLE; |
| 4031 | I915_WRITE(reg, temp); |
| 4032 | |
| 4033 | reg = FDI_RX_CTL(pipe); |
| 4034 | temp = I915_READ(reg); |
| 4035 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 4036 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 4037 | temp &= ~FDI_RX_ENABLE; |
| 4038 | I915_WRITE(reg, temp); |
| 4039 | |
| 4040 | /* enable CPU FDI TX and PCH FDI RX */ |
| 4041 | reg = FDI_TX_CTL(pipe); |
| 4042 | temp = I915_READ(reg); |
| 4043 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4044 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4045 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4046 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4047 | temp |= snb_b_fdi_train_param[j/2]; |
| 4048 | temp |= FDI_COMPOSITE_SYNC; |
| 4049 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 4050 | |
| 4051 | I915_WRITE(FDI_RX_MISC(pipe), |
| 4052 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 4053 | |
| 4054 | reg = FDI_RX_CTL(pipe); |
| 4055 | temp = I915_READ(reg); |
| 4056 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 4057 | temp |= FDI_COMPOSITE_SYNC; |
| 4058 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 4059 | |
| 4060 | POSTING_READ(reg); |
| 4061 | udelay(1); /* should be 0.5us */ |
| 4062 | |
| 4063 | for (i = 0; i < 4; i++) { |
| 4064 | reg = FDI_RX_IIR(pipe); |
| 4065 | temp = I915_READ(reg); |
| 4066 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 4067 | |
| 4068 | if (temp & FDI_RX_BIT_LOCK || |
| 4069 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 4070 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 4071 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
| 4072 | i); |
| 4073 | break; |
| 4074 | } |
| 4075 | udelay(1); /* should be 0.5us */ |
| 4076 | } |
| 4077 | if (i == 4) { |
| 4078 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
| 4079 | continue; |
| 4080 | } |
| 4081 | |
| 4082 | /* Train 2 */ |
| 4083 | reg = FDI_TX_CTL(pipe); |
| 4084 | temp = I915_READ(reg); |
| 4085 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 4086 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 4087 | I915_WRITE(reg, temp); |
| 4088 | |
| 4089 | reg = FDI_RX_CTL(pipe); |
| 4090 | temp = I915_READ(reg); |
| 4091 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 4092 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4093 | I915_WRITE(reg, temp); |
| 4094 | |
| 4095 | POSTING_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4096 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4097 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4098 | for (i = 0; i < 4; i++) { |
| 4099 | reg = FDI_RX_IIR(pipe); |
| 4100 | temp = I915_READ(reg); |
| 4101 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4102 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4103 | if (temp & FDI_RX_SYMBOL_LOCK || |
| 4104 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
| 4105 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 4106 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
| 4107 | i); |
| 4108 | goto train_done; |
| 4109 | } |
| 4110 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4111 | } |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4112 | if (i == 4) |
| 4113 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4114 | } |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4115 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 4116 | train_done: |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 4117 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 4118 | } |
| 4119 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4120 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 4121 | { |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4122 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4123 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 4124 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4125 | i915_reg_t reg; |
| 4126 | u32 temp; |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 4127 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 4128 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4129 | reg = FDI_RX_CTL(pipe); |
| 4130 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 4131 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4132 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 4133 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4134 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 4135 | |
| 4136 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 4137 | udelay(200); |
| 4138 | |
| 4139 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4140 | temp = I915_READ(reg); |
| 4141 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 4142 | |
| 4143 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 4144 | udelay(200); |
| 4145 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 4146 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
| 4147 | reg = FDI_TX_CTL(pipe); |
| 4148 | temp = I915_READ(reg); |
| 4149 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 4150 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4151 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 4152 | POSTING_READ(reg); |
| 4153 | udelay(100); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 4154 | } |
| 4155 | } |
| 4156 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4157 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
| 4158 | { |
| 4159 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4160 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4161 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4162 | i915_reg_t reg; |
| 4163 | u32 temp; |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4164 | |
| 4165 | /* Switch from PCDclk to Rawclk */ |
| 4166 | reg = FDI_RX_CTL(pipe); |
| 4167 | temp = I915_READ(reg); |
| 4168 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
| 4169 | |
| 4170 | /* Disable CPU FDI TX PLL */ |
| 4171 | reg = FDI_TX_CTL(pipe); |
| 4172 | temp = I915_READ(reg); |
| 4173 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 4174 | |
| 4175 | POSTING_READ(reg); |
| 4176 | udelay(100); |
| 4177 | |
| 4178 | reg = FDI_RX_CTL(pipe); |
| 4179 | temp = I915_READ(reg); |
| 4180 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
| 4181 | |
| 4182 | /* Wait for the clocks to turn off. */ |
| 4183 | POSTING_READ(reg); |
| 4184 | udelay(100); |
| 4185 | } |
| 4186 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 4187 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 4188 | { |
| 4189 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4190 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 4191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4192 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4193 | i915_reg_t reg; |
| 4194 | u32 temp; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 4195 | |
| 4196 | /* disable CPU FDI tx and PCH FDI rx */ |
| 4197 | reg = FDI_TX_CTL(pipe); |
| 4198 | temp = I915_READ(reg); |
| 4199 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 4200 | POSTING_READ(reg); |
| 4201 | |
| 4202 | reg = FDI_RX_CTL(pipe); |
| 4203 | temp = I915_READ(reg); |
| 4204 | temp &= ~(0x7 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 4205 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 4206 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 4207 | |
| 4208 | POSTING_READ(reg); |
| 4209 | udelay(100); |
| 4210 | |
| 4211 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 4212 | if (HAS_PCH_IBX(dev)) |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 4213 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 4214 | |
| 4215 | /* still set train pattern 1 */ |
| 4216 | reg = FDI_TX_CTL(pipe); |
| 4217 | temp = I915_READ(reg); |
| 4218 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 4219 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 4220 | I915_WRITE(reg, temp); |
| 4221 | |
| 4222 | reg = FDI_RX_CTL(pipe); |
| 4223 | temp = I915_READ(reg); |
| 4224 | if (HAS_PCH_CPT(dev)) { |
| 4225 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 4226 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 4227 | } else { |
| 4228 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 4229 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 4230 | } |
| 4231 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 4232 | temp &= ~(0x07 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 4233 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 4234 | I915_WRITE(reg, temp); |
| 4235 | |
| 4236 | POSTING_READ(reg); |
| 4237 | udelay(100); |
| 4238 | } |
| 4239 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 4240 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
| 4241 | { |
| 4242 | struct intel_crtc *crtc; |
| 4243 | |
| 4244 | /* Note that we don't need to be called with mode_config.lock here |
| 4245 | * as our list of CRTC objects is static for the lifetime of the |
| 4246 | * device and so cannot disappear as we iterate. Similarly, we can |
| 4247 | * happily treat the predicates as racy, atomic checks as userspace |
| 4248 | * cannot claim and pin a new fb without at least acquring the |
| 4249 | * struct_mutex and so serialising with us. |
| 4250 | */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 4251 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 4252 | if (atomic_read(&crtc->unpin_work_count) == 0) |
| 4253 | continue; |
| 4254 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 4255 | if (crtc->flip_work) |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 4256 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4257 | |
| 4258 | return true; |
| 4259 | } |
| 4260 | |
| 4261 | return false; |
| 4262 | } |
| 4263 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 4264 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4265 | { |
| 4266 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 4267 | struct intel_flip_work *work = intel_crtc->flip_work; |
| 4268 | |
| 4269 | intel_crtc->flip_work = NULL; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4270 | |
| 4271 | if (work->event) |
Gustavo Padovan | 560ce1d | 2016-04-14 10:48:15 -0700 | [diff] [blame] | 4272 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4273 | |
| 4274 | drm_crtc_vblank_put(&intel_crtc->base); |
| 4275 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 4276 | wake_up_all(&dev_priv->pending_flip_queue); |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 4277 | queue_work(dev_priv->wq, &work->unpin_work); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 4278 | |
| 4279 | trace_i915_flip_complete(intel_crtc->plane, |
| 4280 | work->pending_flip_obj); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4281 | } |
| 4282 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 4283 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 4284 | { |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 4285 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4286 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 4287 | long ret; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 4288 | |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 4289 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 4290 | |
| 4291 | ret = wait_event_interruptible_timeout( |
| 4292 | dev_priv->pending_flip_queue, |
| 4293 | !intel_crtc_has_pending_flip(crtc), |
| 4294 | 60*HZ); |
| 4295 | |
| 4296 | if (ret < 0) |
| 4297 | return ret; |
| 4298 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 4299 | if (ret == 0) { |
| 4300 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4301 | struct intel_flip_work *work; |
| 4302 | |
| 4303 | spin_lock_irq(&dev->event_lock); |
| 4304 | work = intel_crtc->flip_work; |
| 4305 | if (work && !is_mmio_work(work)) { |
| 4306 | WARN_ONCE(1, "Removing stuck page flip\n"); |
| 4307 | page_flip_completed(intel_crtc); |
| 4308 | } |
| 4309 | spin_unlock_irq(&dev->event_lock); |
| 4310 | } |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 4311 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 4312 | return 0; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 4313 | } |
| 4314 | |
Maarten Lankhorst | b707654 | 2016-08-23 16:18:08 +0200 | [diff] [blame] | 4315 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 4316 | { |
| 4317 | u32 temp; |
| 4318 | |
| 4319 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
| 4320 | |
| 4321 | mutex_lock(&dev_priv->sb_lock); |
| 4322 | |
| 4323 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
| 4324 | temp |= SBI_SSCCTL_DISABLE; |
| 4325 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
| 4326 | |
| 4327 | mutex_unlock(&dev_priv->sb_lock); |
| 4328 | } |
| 4329 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4330 | /* Program iCLKIP clock to the desired frequency */ |
| 4331 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
| 4332 | { |
Ville Syrjälä | 64b46a0 | 2016-02-17 21:41:11 +0200 | [diff] [blame] | 4333 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4334 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4335 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
| 4336 | u32 temp; |
| 4337 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 4338 | lpt_disable_iclkip(dev_priv); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4339 | |
Ville Syrjälä | 64b46a0 | 2016-02-17 21:41:11 +0200 | [diff] [blame] | 4340 | /* The iCLK virtual clock root frequency is in MHz, |
| 4341 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
| 4342 | * divisors, it is necessary to divide one by another, so we |
| 4343 | * convert the virtual clock precision to KHz here for higher |
| 4344 | * precision. |
| 4345 | */ |
| 4346 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4347 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 4348 | u32 iclk_pi_range = 64; |
Ville Syrjälä | 64b46a0 | 2016-02-17 21:41:11 +0200 | [diff] [blame] | 4349 | u32 desired_divisor; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4350 | |
Ville Syrjälä | 64b46a0 | 2016-02-17 21:41:11 +0200 | [diff] [blame] | 4351 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
| 4352 | clock << auxdiv); |
| 4353 | divsel = (desired_divisor / iclk_pi_range) - 2; |
| 4354 | phaseinc = desired_divisor % iclk_pi_range; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4355 | |
Ville Syrjälä | 64b46a0 | 2016-02-17 21:41:11 +0200 | [diff] [blame] | 4356 | /* |
| 4357 | * Near 20MHz is a corner case which is |
| 4358 | * out of range for the 7-bit divisor |
| 4359 | */ |
| 4360 | if (divsel <= 0x7f) |
| 4361 | break; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4362 | } |
| 4363 | |
| 4364 | /* This should not happen with any sane values */ |
| 4365 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
| 4366 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
| 4367 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
| 4368 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
| 4369 | |
| 4370 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 4371 | clock, |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4372 | auxdiv, |
| 4373 | divsel, |
| 4374 | phasedir, |
| 4375 | phaseinc); |
| 4376 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 4377 | mutex_lock(&dev_priv->sb_lock); |
| 4378 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4379 | /* Program SSCDIVINTPHASE6 */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4380 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4381 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
| 4382 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
| 4383 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
| 4384 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
| 4385 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
| 4386 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4387 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4388 | |
| 4389 | /* Program SSCAUXDIV */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4390 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4391 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
| 4392 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4393 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4394 | |
| 4395 | /* Enable modulator and associated divider */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4396 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4397 | temp &= ~SBI_SSCCTL_DISABLE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4398 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4399 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 4400 | mutex_unlock(&dev_priv->sb_lock); |
| 4401 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4402 | /* Wait for initialization time */ |
| 4403 | udelay(24); |
| 4404 | |
| 4405 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
| 4406 | } |
| 4407 | |
Ville Syrjälä | 8802e5b | 2016-02-17 21:41:12 +0200 | [diff] [blame] | 4408 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
| 4409 | { |
| 4410 | u32 divsel, phaseinc, auxdiv; |
| 4411 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 4412 | u32 iclk_pi_range = 64; |
| 4413 | u32 desired_divisor; |
| 4414 | u32 temp; |
| 4415 | |
| 4416 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) |
| 4417 | return 0; |
| 4418 | |
| 4419 | mutex_lock(&dev_priv->sb_lock); |
| 4420 | |
| 4421 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
| 4422 | if (temp & SBI_SSCCTL_DISABLE) { |
| 4423 | mutex_unlock(&dev_priv->sb_lock); |
| 4424 | return 0; |
| 4425 | } |
| 4426 | |
| 4427 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
| 4428 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> |
| 4429 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; |
| 4430 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> |
| 4431 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; |
| 4432 | |
| 4433 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
| 4434 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> |
| 4435 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; |
| 4436 | |
| 4437 | mutex_unlock(&dev_priv->sb_lock); |
| 4438 | |
| 4439 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; |
| 4440 | |
| 4441 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
| 4442 | desired_divisor << auxdiv); |
| 4443 | } |
| 4444 | |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4445 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
| 4446 | enum pipe pch_transcoder) |
| 4447 | { |
| 4448 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4449 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4450 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4451 | |
| 4452 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
| 4453 | I915_READ(HTOTAL(cpu_transcoder))); |
| 4454 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
| 4455 | I915_READ(HBLANK(cpu_transcoder))); |
| 4456 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
| 4457 | I915_READ(HSYNC(cpu_transcoder))); |
| 4458 | |
| 4459 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
| 4460 | I915_READ(VTOTAL(cpu_transcoder))); |
| 4461 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
| 4462 | I915_READ(VBLANK(cpu_transcoder))); |
| 4463 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
| 4464 | I915_READ(VSYNC(cpu_transcoder))); |
| 4465 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
| 4466 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
| 4467 | } |
| 4468 | |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4469 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4470 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4471 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4472 | uint32_t temp; |
| 4473 | |
| 4474 | temp = I915_READ(SOUTH_CHICKEN1); |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4475 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4476 | return; |
| 4477 | |
| 4478 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 4479 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 4480 | |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4481 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
| 4482 | if (enable) |
| 4483 | temp |= FDI_BC_BIFURCATION_SELECT; |
| 4484 | |
| 4485 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4486 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 4487 | POSTING_READ(SOUTH_CHICKEN1); |
| 4488 | } |
| 4489 | |
| 4490 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
| 4491 | { |
| 4492 | struct drm_device *dev = intel_crtc->base.dev; |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4493 | |
| 4494 | switch (intel_crtc->pipe) { |
| 4495 | case PIPE_A: |
| 4496 | break; |
| 4497 | case PIPE_B: |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4498 | if (intel_crtc->config->fdi_lanes > 2) |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4499 | cpt_set_fdi_bc_bifurcation(dev, false); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4500 | else |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4501 | cpt_set_fdi_bc_bifurcation(dev, true); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4502 | |
| 4503 | break; |
| 4504 | case PIPE_C: |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4505 | cpt_set_fdi_bc_bifurcation(dev, true); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4506 | |
| 4507 | break; |
| 4508 | default: |
| 4509 | BUG(); |
| 4510 | } |
| 4511 | } |
| 4512 | |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4513 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 4514 | static enum port |
| 4515 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
| 4516 | { |
| 4517 | struct drm_device *dev = crtc->dev; |
| 4518 | struct intel_encoder *encoder; |
| 4519 | |
| 4520 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4521 | if (encoder->type == INTEL_OUTPUT_DP || |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4522 | encoder->type == INTEL_OUTPUT_EDP) |
| 4523 | return enc_to_dig_port(&encoder->base)->port; |
| 4524 | } |
| 4525 | |
| 4526 | return -1; |
| 4527 | } |
| 4528 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4529 | /* |
| 4530 | * Enable PCH resources required for PCH ports: |
| 4531 | * - PCH PLLs |
| 4532 | * - FDI training & RX/TX |
| 4533 | * - update transcoder timings |
| 4534 | * - DP transcoding bits |
| 4535 | * - transcoder |
| 4536 | */ |
| 4537 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4538 | { |
| 4539 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4540 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4542 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4543 | u32 temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4544 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 4545 | assert_pch_transcoder_disabled(dev_priv, pipe); |
Chris Wilson | e7e164d | 2012-05-11 09:21:25 +0100 | [diff] [blame] | 4546 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4547 | if (IS_IVYBRIDGE(dev)) |
| 4548 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
| 4549 | |
Daniel Vetter | cd986ab | 2012-10-26 10:58:12 +0200 | [diff] [blame] | 4550 | /* Write the TU size bits before fdi link training, so that error |
| 4551 | * detection works. */ |
| 4552 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 4553 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
| 4554 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4555 | /* For PCH output, training FDI link */ |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 4556 | dev_priv->display.fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4557 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 4558 | /* We need to program the right clock selection before writing the pixel |
| 4559 | * mutliplier into the DPLL. */ |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 4560 | if (HAS_PCH_CPT(dev)) { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4561 | u32 sel; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4562 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4563 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 4564 | temp |= TRANS_DPLL_ENABLE(pipe); |
| 4565 | sel = TRANS_DPLLB_SEL(pipe); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 4566 | if (intel_crtc->config->shared_dpll == |
| 4567 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4568 | temp |= sel; |
| 4569 | else |
| 4570 | temp &= ~sel; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4571 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4572 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4573 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 4574 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
| 4575 | * transcoder, and we actually should do this to not upset any PCH |
| 4576 | * transcoder that already use the clock when we share it. |
| 4577 | * |
| 4578 | * Note that enable_shared_dpll tries to do the right thing, but |
| 4579 | * get_shared_dpll unconditionally resets the pll - we need that to have |
| 4580 | * the right LVDS enable sequence. */ |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 4581 | intel_enable_shared_dpll(intel_crtc); |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 4582 | |
Jesse Barnes | d9b6cb5 | 2011-01-04 15:09:35 -0800 | [diff] [blame] | 4583 | /* set transcoder timing, panel must allow it */ |
| 4584 | assert_panel_unlocked(dev_priv, pipe); |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4585 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4586 | |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 4587 | intel_fdi_normal_train(crtc); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 4588 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4589 | /* For PCH DP, enable TRANS_DP_CTL */ |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 4590 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
Ville Syrjälä | 9c4edae | 2015-10-29 21:25:51 +0200 | [diff] [blame] | 4591 | const struct drm_display_mode *adjusted_mode = |
| 4592 | &intel_crtc->config->base.adjusted_mode; |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 4593 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4594 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4595 | temp = I915_READ(reg); |
| 4596 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
Eric Anholt | 220cad3 | 2010-11-18 09:32:58 +0800 | [diff] [blame] | 4597 | TRANS_DP_SYNC_MASK | |
| 4598 | TRANS_DP_BPC_MASK); |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 4599 | temp |= TRANS_DP_OUTPUT_ENABLE; |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 4600 | temp |= bpc << 9; /* same format but at 11:9 */ |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4601 | |
Ville Syrjälä | 9c4edae | 2015-10-29 21:25:51 +0200 | [diff] [blame] | 4602 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4603 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Ville Syrjälä | 9c4edae | 2015-10-29 21:25:51 +0200 | [diff] [blame] | 4604 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4605 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4606 | |
| 4607 | switch (intel_trans_dp_port_sel(crtc)) { |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4608 | case PORT_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4609 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4610 | break; |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4611 | case PORT_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4612 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4613 | break; |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4614 | case PORT_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4615 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4616 | break; |
| 4617 | default: |
Daniel Vetter | e95d41e | 2012-10-26 10:58:16 +0200 | [diff] [blame] | 4618 | BUG(); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4619 | } |
| 4620 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4621 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4622 | } |
| 4623 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 4624 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4625 | } |
| 4626 | |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4627 | static void lpt_pch_enable(struct drm_crtc *crtc) |
| 4628 | { |
| 4629 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4630 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4632 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4633 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 4634 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4635 | |
Paulo Zanoni | 8c52b5e | 2012-10-31 18:12:24 -0200 | [diff] [blame] | 4636 | lpt_program_iclkip(crtc); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4637 | |
Paulo Zanoni | 0540e48 | 2012-10-31 18:12:40 -0200 | [diff] [blame] | 4638 | /* Set transcoder timing. */ |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4639 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4640 | |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 4641 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4642 | } |
| 4643 | |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 4644 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4645 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4646 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4647 | i915_reg_t dslreg = PIPEDSL(pipe); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4648 | u32 temp; |
| 4649 | |
| 4650 | temp = I915_READ(dslreg); |
| 4651 | udelay(500); |
| 4652 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4653 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 4654 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4655 | } |
| 4656 | } |
| 4657 | |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4658 | static int |
| 4659 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, |
| 4660 | unsigned scaler_user, int *scaler_id, unsigned int rotation, |
| 4661 | int src_w, int src_h, int dst_w, int dst_h) |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4662 | { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4663 | struct intel_crtc_scaler_state *scaler_state = |
| 4664 | &crtc_state->scaler_state; |
| 4665 | struct intel_crtc *intel_crtc = |
| 4666 | to_intel_crtc(crtc_state->base.crtc); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4667 | int need_scaling; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 4668 | |
| 4669 | need_scaling = intel_rotation_90_or_270(rotation) ? |
| 4670 | (src_h != dst_w || src_w != dst_h): |
| 4671 | (src_w != dst_w || src_h != dst_h); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4672 | |
| 4673 | /* |
| 4674 | * if plane is being disabled or scaler is no more required or force detach |
| 4675 | * - free scaler binded to this plane/crtc |
| 4676 | * - in order to do this, update crtc->scaler_usage |
| 4677 | * |
| 4678 | * Here scaler state in crtc_state is set free so that |
| 4679 | * scaler can be assigned to other user. Actual register |
| 4680 | * update to free the scaler is done in plane/panel-fit programming. |
| 4681 | * For this purpose crtc/plane_state->scaler_id isn't reset here. |
| 4682 | */ |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4683 | if (force_detach || !need_scaling) { |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4684 | if (*scaler_id >= 0) { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4685 | scaler_state->scaler_users &= ~(1 << scaler_user); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4686 | scaler_state->scalers[*scaler_id].in_use = 0; |
| 4687 | |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4688 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
| 4689 | "Staged freeing scaler id %d scaler_users = 0x%x\n", |
| 4690 | intel_crtc->pipe, scaler_user, *scaler_id, |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4691 | scaler_state->scaler_users); |
| 4692 | *scaler_id = -1; |
| 4693 | } |
| 4694 | return 0; |
| 4695 | } |
| 4696 | |
| 4697 | /* range checks */ |
| 4698 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || |
| 4699 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || |
| 4700 | |
| 4701 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || |
| 4702 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4703 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4704 | "size is out of scaler range\n", |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4705 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4706 | return -EINVAL; |
| 4707 | } |
| 4708 | |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4709 | /* mark this plane as a scaler user in crtc_state */ |
| 4710 | scaler_state->scaler_users |= (1 << scaler_user); |
| 4711 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
| 4712 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", |
| 4713 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, |
| 4714 | scaler_state->scaler_users); |
| 4715 | |
| 4716 | return 0; |
| 4717 | } |
| 4718 | |
| 4719 | /** |
| 4720 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. |
| 4721 | * |
| 4722 | * @state: crtc's scaler state |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4723 | * |
| 4724 | * Return |
| 4725 | * 0 - scaler_usage updated successfully |
| 4726 | * error - requested scaling cannot be supported or other error condition |
| 4727 | */ |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 4728 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4729 | { |
| 4730 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 4731 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4732 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 4733 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
| 4734 | intel_crtc->base.base.id, intel_crtc->base.name, |
| 4735 | intel_crtc->pipe, SKL_CRTC_INDEX); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4736 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 4737 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 4738 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4739 | state->pipe_src_w, state->pipe_src_h, |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 4740 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4741 | } |
| 4742 | |
| 4743 | /** |
| 4744 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. |
| 4745 | * |
| 4746 | * @state: crtc's scaler state |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4747 | * @plane_state: atomic plane state to update |
| 4748 | * |
| 4749 | * Return |
| 4750 | * 0 - scaler_usage updated successfully |
| 4751 | * error - requested scaling cannot be supported or other error condition |
| 4752 | */ |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 4753 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
| 4754 | struct intel_plane_state *plane_state) |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4755 | { |
| 4756 | |
| 4757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 4758 | struct intel_plane *intel_plane = |
| 4759 | to_intel_plane(plane_state->base.plane); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4760 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 4761 | int ret; |
| 4762 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 4763 | bool force_detach = !fb || !plane_state->base.visible; |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4764 | |
Ville Syrjälä | 72660ce | 2016-05-27 20:59:20 +0300 | [diff] [blame] | 4765 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
| 4766 | intel_plane->base.base.id, intel_plane->base.name, |
| 4767 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4768 | |
| 4769 | ret = skl_update_scaler(crtc_state, force_detach, |
| 4770 | drm_plane_index(&intel_plane->base), |
| 4771 | &plane_state->scaler_id, |
| 4772 | plane_state->base.rotation, |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 4773 | drm_rect_width(&plane_state->base.src) >> 16, |
| 4774 | drm_rect_height(&plane_state->base.src) >> 16, |
| 4775 | drm_rect_width(&plane_state->base.dst), |
| 4776 | drm_rect_height(&plane_state->base.dst)); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4777 | |
| 4778 | if (ret || plane_state->scaler_id < 0) |
| 4779 | return ret; |
| 4780 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4781 | /* check colorkey */ |
Maarten Lankhorst | 818ed96 | 2015-06-15 12:33:54 +0200 | [diff] [blame] | 4782 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
Ville Syrjälä | 72660ce | 2016-05-27 20:59:20 +0300 | [diff] [blame] | 4783 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
| 4784 | intel_plane->base.base.id, |
| 4785 | intel_plane->base.name); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4786 | return -EINVAL; |
| 4787 | } |
| 4788 | |
| 4789 | /* Check src format */ |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4790 | switch (fb->pixel_format) { |
| 4791 | case DRM_FORMAT_RGB565: |
| 4792 | case DRM_FORMAT_XBGR8888: |
| 4793 | case DRM_FORMAT_XRGB8888: |
| 4794 | case DRM_FORMAT_ABGR8888: |
| 4795 | case DRM_FORMAT_ARGB8888: |
| 4796 | case DRM_FORMAT_XRGB2101010: |
| 4797 | case DRM_FORMAT_XBGR2101010: |
| 4798 | case DRM_FORMAT_YUYV: |
| 4799 | case DRM_FORMAT_YVYU: |
| 4800 | case DRM_FORMAT_UYVY: |
| 4801 | case DRM_FORMAT_VYUY: |
| 4802 | break; |
| 4803 | default: |
Ville Syrjälä | 72660ce | 2016-05-27 20:59:20 +0300 | [diff] [blame] | 4804 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
| 4805 | intel_plane->base.base.id, intel_plane->base.name, |
| 4806 | fb->base.id, fb->pixel_format); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4807 | return -EINVAL; |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4808 | } |
| 4809 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4810 | return 0; |
| 4811 | } |
| 4812 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 4813 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
| 4814 | { |
| 4815 | int i; |
| 4816 | |
| 4817 | for (i = 0; i < crtc->num_scalers; i++) |
| 4818 | skl_detach_scaler(crtc, i); |
| 4819 | } |
| 4820 | |
| 4821 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 4822 | { |
| 4823 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4824 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 4825 | int pipe = crtc->pipe; |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4826 | struct intel_crtc_scaler_state *scaler_state = |
| 4827 | &crtc->config->scaler_state; |
| 4828 | |
| 4829 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); |
| 4830 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4831 | if (crtc->config->pch_pfit.enabled) { |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4832 | int id; |
| 4833 | |
| 4834 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { |
| 4835 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); |
| 4836 | return; |
| 4837 | } |
| 4838 | |
| 4839 | id = scaler_state->scaler_id; |
| 4840 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | |
| 4841 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); |
| 4842 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); |
| 4843 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); |
| 4844 | |
| 4845 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 4846 | } |
| 4847 | } |
| 4848 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4849 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
| 4850 | { |
| 4851 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4852 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4853 | int pipe = crtc->pipe; |
| 4854 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4855 | if (crtc->config->pch_pfit.enabled) { |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4856 | /* Force use of hard-coded filter coefficients |
| 4857 | * as some pre-programmed values are broken, |
| 4858 | * e.g. x201. |
| 4859 | */ |
| 4860 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 4861 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
| 4862 | PF_PIPE_SEL_IVB(pipe)); |
| 4863 | else |
| 4864 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4865 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
| 4866 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 4867 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4868 | } |
| 4869 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 4870 | void hsw_enable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4871 | { |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 4872 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4873 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4874 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4875 | if (!crtc->config->ips_enabled) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4876 | return; |
| 4877 | |
Maarten Lankhorst | 307e449 | 2016-03-23 14:33:28 +0100 | [diff] [blame] | 4878 | /* |
| 4879 | * We can only enable IPS after we enable a plane and wait for a vblank |
| 4880 | * This function is called from post_plane_update, which is run after |
| 4881 | * a vblank wait. |
| 4882 | */ |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 4883 | |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4884 | assert_plane_enabled(dev_priv, crtc->plane); |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 4885 | if (IS_BROADWELL(dev)) { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4886 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4887 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
| 4888 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4889 | /* Quoting Art Runyan: "its not safe to expect any particular |
| 4890 | * value in IPS_CTL bit 31 after enabling IPS through the |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 4891 | * mailbox." Moreover, the mailbox may return a bogus state, |
| 4892 | * so we need to just enable it and continue on. |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4893 | */ |
| 4894 | } else { |
| 4895 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
| 4896 | /* The bit only becomes 1 in the next vblank, so this wait here |
| 4897 | * is essentially intel_wait_for_vblank. If we don't have this |
| 4898 | * and don't wait for vblanks until the end of crtc_enable, then |
| 4899 | * the HW state readout code will complain that the expected |
| 4900 | * IPS_CTL value is not the one we read. */ |
Chris Wilson | 2ec9ba3 | 2016-06-30 15:33:01 +0100 | [diff] [blame] | 4901 | if (intel_wait_for_register(dev_priv, |
| 4902 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, |
| 4903 | 50)) |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4904 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
| 4905 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4906 | } |
| 4907 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 4908 | void hsw_disable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4909 | { |
| 4910 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4911 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4912 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4913 | if (!crtc->config->ips_enabled) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4914 | return; |
| 4915 | |
| 4916 | assert_plane_enabled(dev_priv, crtc->plane); |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 4917 | if (IS_BROADWELL(dev)) { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4918 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4919 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
| 4920 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 4921 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
Chris Wilson | b85c1ec | 2016-06-30 15:33:02 +0100 | [diff] [blame] | 4922 | if (intel_wait_for_register(dev_priv, |
| 4923 | IPS_CTL, IPS_ENABLE, 0, |
| 4924 | 42)) |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 4925 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 4926 | } else { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4927 | I915_WRITE(IPS_CTL, 0); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 4928 | POSTING_READ(IPS_CTL); |
| 4929 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4930 | |
| 4931 | /* We need to wait for a vblank before we can disable the plane. */ |
| 4932 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4933 | } |
| 4934 | |
Maarten Lankhorst | 7cac945 | 2015-04-21 17:12:55 +0300 | [diff] [blame] | 4935 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4936 | { |
Maarten Lankhorst | 7cac945 | 2015-04-21 17:12:55 +0300 | [diff] [blame] | 4937 | if (intel_crtc->overlay) { |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4938 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4939 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4940 | |
| 4941 | mutex_lock(&dev->struct_mutex); |
| 4942 | dev_priv->mm.interruptible = false; |
| 4943 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 4944 | dev_priv->mm.interruptible = true; |
| 4945 | mutex_unlock(&dev->struct_mutex); |
| 4946 | } |
| 4947 | |
| 4948 | /* Let userspace switch the overlay on again. In most cases userspace |
| 4949 | * has to recompute where to put it anyway. |
| 4950 | */ |
| 4951 | } |
| 4952 | |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4953 | /** |
| 4954 | * intel_post_enable_primary - Perform operations after enabling primary plane |
| 4955 | * @crtc: the CRTC whose primary plane was just enabled |
| 4956 | * |
| 4957 | * Performs potentially sleeping operations that must be done after the primary |
| 4958 | * plane is enabled, such as updating FBC and IPS. Note that this may be |
| 4959 | * called due to an explicit primary plane update, or due to an implicit |
| 4960 | * re-enable that is caused when a sprite plane is updated to no longer |
| 4961 | * completely hide the primary plane. |
| 4962 | */ |
| 4963 | static void |
| 4964 | intel_post_enable_primary(struct drm_crtc *crtc) |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4965 | { |
| 4966 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4967 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4968 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4969 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4970 | |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4971 | /* |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4972 | * FIXME IPS should be fine as long as one plane is |
| 4973 | * enabled, but in practice it seems to have problems |
| 4974 | * when going from primary only to sprite only and vice |
| 4975 | * versa. |
| 4976 | */ |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4977 | hsw_enable_ips(intel_crtc); |
| 4978 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4979 | /* |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4980 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4981 | * So don't enable underrun reporting before at least some planes |
| 4982 | * are enabled. |
| 4983 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4984 | * but leave the pipe running. |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4985 | */ |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4986 | if (IS_GEN2(dev)) |
| 4987 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4988 | |
Ville Syrjälä | aca7b68 | 2015-10-30 19:22:21 +0200 | [diff] [blame] | 4989 | /* Underruns don't always raise interrupts, so check manually. */ |
| 4990 | intel_check_cpu_fifo_underruns(dev_priv); |
| 4991 | intel_check_pch_fifo_underruns(dev_priv); |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4992 | } |
| 4993 | |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 4994 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4995 | static void |
| 4996 | intel_pre_disable_primary(struct drm_crtc *crtc) |
| 4997 | { |
| 4998 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4999 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 5000 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5001 | int pipe = intel_crtc->pipe; |
| 5002 | |
| 5003 | /* |
| 5004 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 5005 | * So diasble underrun reporting before all the planes get disabled. |
| 5006 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 5007 | * but leave the pipe running. |
| 5008 | */ |
| 5009 | if (IS_GEN2(dev)) |
| 5010 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5011 | |
| 5012 | /* |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 5013 | * FIXME IPS should be fine as long as one plane is |
| 5014 | * enabled, but in practice it seems to have problems |
| 5015 | * when going from primary only to sprite only and vice |
| 5016 | * versa. |
| 5017 | */ |
| 5018 | hsw_disable_ips(intel_crtc); |
| 5019 | } |
| 5020 | |
| 5021 | /* FIXME get rid of this and use pre_plane_update */ |
| 5022 | static void |
| 5023 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) |
| 5024 | { |
| 5025 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5026 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 5027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5028 | int pipe = intel_crtc->pipe; |
| 5029 | |
| 5030 | intel_pre_disable_primary(crtc); |
| 5031 | |
| 5032 | /* |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 5033 | * Vblank time updates from the shadow to live plane control register |
| 5034 | * are blocked if the memory self-refresh mode is active at that |
| 5035 | * moment. So to make sure the plane gets truly disabled, disable |
| 5036 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 5037 | * will be checked/applied by the HW only at the next frame start |
| 5038 | * event which is after the vblank start event, so we need to have a |
| 5039 | * wait-for-vblank between disabling the plane and the pipe. |
| 5040 | */ |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 5041 | if (HAS_GMCH_DISPLAY(dev)) { |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 5042 | intel_set_memory_cxsr(dev_priv, false); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 5043 | dev_priv->wm.vlv.cxsr = false; |
| 5044 | intel_wait_for_vblank(dev, pipe); |
| 5045 | } |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 5046 | } |
| 5047 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5048 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
| 5049 | { |
| 5050 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
| 5051 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
| 5052 | struct intel_crtc_state *pipe_config = |
| 5053 | to_intel_crtc_state(crtc->base.state); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5054 | struct drm_plane *primary = crtc->base.primary; |
| 5055 | struct drm_plane_state *old_pri_state = |
| 5056 | drm_atomic_get_existing_plane_state(old_state, primary); |
| 5057 | |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5058 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5059 | |
| 5060 | crtc->wm.cxsr_allowed = true; |
| 5061 | |
| 5062 | if (pipe_config->update_wm_post && pipe_config->base.active) |
| 5063 | intel_update_watermarks(&crtc->base); |
| 5064 | |
| 5065 | if (old_pri_state) { |
| 5066 | struct intel_plane_state *primary_state = |
| 5067 | to_intel_plane_state(primary->state); |
| 5068 | struct intel_plane_state *old_primary_state = |
| 5069 | to_intel_plane_state(old_pri_state); |
| 5070 | |
| 5071 | intel_fbc_post_update(crtc); |
| 5072 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 5073 | if (primary_state->base.visible && |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5074 | (needs_modeset(&pipe_config->base) || |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 5075 | !old_primary_state->base.visible)) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5076 | intel_post_enable_primary(&crtc->base); |
| 5077 | } |
| 5078 | } |
| 5079 | |
Maarten Lankhorst | 5c74cd7 | 2016-02-03 16:53:24 +0100 | [diff] [blame] | 5080 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 5081 | { |
Maarten Lankhorst | 5c74cd7 | 2016-02-03 16:53:24 +0100 | [diff] [blame] | 5082 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 5083 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5084 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 5085 | struct intel_crtc_state *pipe_config = |
| 5086 | to_intel_crtc_state(crtc->base.state); |
Maarten Lankhorst | 5c74cd7 | 2016-02-03 16:53:24 +0100 | [diff] [blame] | 5087 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
| 5088 | struct drm_plane *primary = crtc->base.primary; |
| 5089 | struct drm_plane_state *old_pri_state = |
| 5090 | drm_atomic_get_existing_plane_state(old_state, primary); |
| 5091 | bool modeset = needs_modeset(&pipe_config->base); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 5092 | |
Maarten Lankhorst | 5c74cd7 | 2016-02-03 16:53:24 +0100 | [diff] [blame] | 5093 | if (old_pri_state) { |
| 5094 | struct intel_plane_state *primary_state = |
| 5095 | to_intel_plane_state(primary->state); |
| 5096 | struct intel_plane_state *old_primary_state = |
| 5097 | to_intel_plane_state(old_pri_state); |
| 5098 | |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 5099 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
Maarten Lankhorst | 31ae71f | 2016-03-09 10:35:45 +0100 | [diff] [blame] | 5100 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 5101 | if (old_primary_state->base.visible && |
| 5102 | (modeset || !primary_state->base.visible)) |
Maarten Lankhorst | 5c74cd7 | 2016-02-03 16:53:24 +0100 | [diff] [blame] | 5103 | intel_pre_disable_primary(&crtc->base); |
| 5104 | } |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 5105 | |
David Weinehall | a4015f9 | 2016-05-19 15:50:36 +0300 | [diff] [blame] | 5106 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 5107 | crtc->wm.cxsr_allowed = false; |
Maarten Lankhorst | 2dfd178 | 2016-02-03 16:53:25 +0100 | [diff] [blame] | 5108 | |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 5109 | /* |
| 5110 | * Vblank time updates from the shadow to live plane control register |
| 5111 | * are blocked if the memory self-refresh mode is active at that |
| 5112 | * moment. So to make sure the plane gets truly disabled, disable |
| 5113 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 5114 | * will be checked/applied by the HW only at the next frame start |
| 5115 | * event which is after the vblank start event, so we need to have a |
| 5116 | * wait-for-vblank between disabling the plane and the pipe. |
| 5117 | */ |
| 5118 | if (old_crtc_state->base.active) { |
Maarten Lankhorst | 2dfd178 | 2016-02-03 16:53:25 +0100 | [diff] [blame] | 5119 | intel_set_memory_cxsr(dev_priv, false); |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 5120 | dev_priv->wm.vlv.cxsr = false; |
| 5121 | intel_wait_for_vblank(dev, crtc->pipe); |
| 5122 | } |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 5123 | } |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 5124 | |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 5125 | /* |
| 5126 | * IVB workaround: must disable low power watermarks for at least |
| 5127 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 5128 | * when scaling is disabled. |
| 5129 | * |
| 5130 | * WaCxSRDisabledForSpriteScaling:ivb |
| 5131 | */ |
| 5132 | if (pipe_config->disable_lp_wm) { |
| 5133 | ilk_disable_lp_wm(dev); |
| 5134 | intel_wait_for_vblank(dev, crtc->pipe); |
| 5135 | } |
| 5136 | |
| 5137 | /* |
| 5138 | * If we're doing a modeset, we're done. No need to do any pre-vblank |
| 5139 | * watermark programming here. |
| 5140 | */ |
| 5141 | if (needs_modeset(&pipe_config->base)) |
| 5142 | return; |
| 5143 | |
| 5144 | /* |
| 5145 | * For platforms that support atomic watermarks, program the |
| 5146 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these |
| 5147 | * will be the intermediate values that are safe for both pre- and |
| 5148 | * post- vblank; when vblank happens, the 'active' values will be set |
| 5149 | * to the final 'target' values and we'll do this again to get the |
| 5150 | * optimal watermarks. For gen9+ platforms, the values we program here |
| 5151 | * will be the final target values which will get automatically latched |
| 5152 | * at vblank time; no further programming will be necessary. |
| 5153 | * |
| 5154 | * If a platform hasn't been transitioned to atomic watermarks yet, |
| 5155 | * we'll continue to update watermarks the old way, if flags tell |
| 5156 | * us to. |
| 5157 | */ |
| 5158 | if (dev_priv->display.initial_watermarks != NULL) |
| 5159 | dev_priv->display.initial_watermarks(pipe_config); |
Ville Syrjälä | caed361 | 2016-03-09 19:07:25 +0200 | [diff] [blame] | 5160 | else if (pipe_config->update_wm_pre) |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 5161 | intel_update_watermarks(&crtc->base); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 5162 | } |
| 5163 | |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 5164 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 5165 | { |
| 5166 | struct drm_device *dev = crtc->dev; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 5167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 5168 | struct drm_plane *p; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 5169 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 5170 | |
Maarten Lankhorst | 7cac945 | 2015-04-21 17:12:55 +0300 | [diff] [blame] | 5171 | intel_crtc_dpms_overlay_disable(intel_crtc); |
Maarten Lankhorst | 27321ae | 2015-04-21 17:12:52 +0300 | [diff] [blame] | 5172 | |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 5173 | drm_for_each_plane_mask(p, dev, plane_mask) |
| 5174 | to_intel_plane(p)->disable_plane(p, crtc); |
Ville Syrjälä | f98551a | 2014-05-22 17:48:06 +0300 | [diff] [blame] | 5175 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 5176 | /* |
| 5177 | * FIXME: Once we grow proper nuclear flip support out of this we need |
| 5178 | * to compute the mask of flip planes precisely. For the time being |
| 5179 | * consider this a flip to a NULL plane. |
| 5180 | */ |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5181 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 5182 | } |
| 5183 | |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5184 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5185 | struct intel_crtc_state *crtc_state, |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5186 | struct drm_atomic_state *old_state) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5187 | { |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5188 | struct drm_connector_state *old_conn_state; |
| 5189 | struct drm_connector *conn; |
| 5190 | int i; |
| 5191 | |
| 5192 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { |
| 5193 | struct drm_connector_state *conn_state = conn->state; |
| 5194 | struct intel_encoder *encoder = |
| 5195 | to_intel_encoder(conn_state->best_encoder); |
| 5196 | |
| 5197 | if (conn_state->crtc != crtc) |
| 5198 | continue; |
| 5199 | |
| 5200 | if (encoder->pre_pll_enable) |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5201 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5202 | } |
| 5203 | } |
| 5204 | |
| 5205 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5206 | struct intel_crtc_state *crtc_state, |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5207 | struct drm_atomic_state *old_state) |
| 5208 | { |
| 5209 | struct drm_connector_state *old_conn_state; |
| 5210 | struct drm_connector *conn; |
| 5211 | int i; |
| 5212 | |
| 5213 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { |
| 5214 | struct drm_connector_state *conn_state = conn->state; |
| 5215 | struct intel_encoder *encoder = |
| 5216 | to_intel_encoder(conn_state->best_encoder); |
| 5217 | |
| 5218 | if (conn_state->crtc != crtc) |
| 5219 | continue; |
| 5220 | |
| 5221 | if (encoder->pre_enable) |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5222 | encoder->pre_enable(encoder, crtc_state, conn_state); |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5223 | } |
| 5224 | } |
| 5225 | |
| 5226 | static void intel_encoders_enable(struct drm_crtc *crtc, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5227 | struct intel_crtc_state *crtc_state, |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5228 | struct drm_atomic_state *old_state) |
| 5229 | { |
| 5230 | struct drm_connector_state *old_conn_state; |
| 5231 | struct drm_connector *conn; |
| 5232 | int i; |
| 5233 | |
| 5234 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { |
| 5235 | struct drm_connector_state *conn_state = conn->state; |
| 5236 | struct intel_encoder *encoder = |
| 5237 | to_intel_encoder(conn_state->best_encoder); |
| 5238 | |
| 5239 | if (conn_state->crtc != crtc) |
| 5240 | continue; |
| 5241 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5242 | encoder->enable(encoder, crtc_state, conn_state); |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5243 | intel_opregion_notify_encoder(encoder, true); |
| 5244 | } |
| 5245 | } |
| 5246 | |
| 5247 | static void intel_encoders_disable(struct drm_crtc *crtc, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5248 | struct intel_crtc_state *old_crtc_state, |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5249 | struct drm_atomic_state *old_state) |
| 5250 | { |
| 5251 | struct drm_connector_state *old_conn_state; |
| 5252 | struct drm_connector *conn; |
| 5253 | int i; |
| 5254 | |
| 5255 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { |
| 5256 | struct intel_encoder *encoder = |
| 5257 | to_intel_encoder(old_conn_state->best_encoder); |
| 5258 | |
| 5259 | if (old_conn_state->crtc != crtc) |
| 5260 | continue; |
| 5261 | |
| 5262 | intel_opregion_notify_encoder(encoder, false); |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5263 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5264 | } |
| 5265 | } |
| 5266 | |
| 5267 | static void intel_encoders_post_disable(struct drm_crtc *crtc, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5268 | struct intel_crtc_state *old_crtc_state, |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5269 | struct drm_atomic_state *old_state) |
| 5270 | { |
| 5271 | struct drm_connector_state *old_conn_state; |
| 5272 | struct drm_connector *conn; |
| 5273 | int i; |
| 5274 | |
| 5275 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { |
| 5276 | struct intel_encoder *encoder = |
| 5277 | to_intel_encoder(old_conn_state->best_encoder); |
| 5278 | |
| 5279 | if (old_conn_state->crtc != crtc) |
| 5280 | continue; |
| 5281 | |
| 5282 | if (encoder->post_disable) |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5283 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5284 | } |
| 5285 | } |
| 5286 | |
| 5287 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5288 | struct intel_crtc_state *old_crtc_state, |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5289 | struct drm_atomic_state *old_state) |
| 5290 | { |
| 5291 | struct drm_connector_state *old_conn_state; |
| 5292 | struct drm_connector *conn; |
| 5293 | int i; |
| 5294 | |
| 5295 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { |
| 5296 | struct intel_encoder *encoder = |
| 5297 | to_intel_encoder(old_conn_state->best_encoder); |
| 5298 | |
| 5299 | if (old_conn_state->crtc != crtc) |
| 5300 | continue; |
| 5301 | |
| 5302 | if (encoder->post_pll_disable) |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5303 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
Maarten Lankhorst | fb1c98b | 2016-08-09 17:04:03 +0200 | [diff] [blame] | 5304 | } |
| 5305 | } |
| 5306 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5307 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
| 5308 | struct drm_atomic_state *old_state) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5309 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5310 | struct drm_crtc *crtc = pipe_config->base.crtc; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5311 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5312 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5314 | int pipe = intel_crtc->pipe; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5315 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 5316 | if (WARN_ON(intel_crtc->active)) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5317 | return; |
| 5318 | |
Ville Syrjälä | b2c0593 | 2016-04-01 21:53:17 +0300 | [diff] [blame] | 5319 | /* |
| 5320 | * Sometimes spurious CPU pipe underruns happen during FDI |
| 5321 | * training, at least with VGA+HDMI cloning. Suppress them. |
| 5322 | * |
| 5323 | * On ILK we get an occasional spurious CPU pipe underruns |
| 5324 | * between eDP port A enable and vdd enable. Also PCH port |
| 5325 | * enable seems to result in the occasional CPU pipe underrun. |
| 5326 | * |
| 5327 | * Spurious PCH underruns also occur during PCH enabling. |
| 5328 | */ |
| 5329 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) |
| 5330 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5331 | if (intel_crtc->config->has_pch_encoder) |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5332 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5333 | |
| 5334 | if (intel_crtc->config->has_pch_encoder) |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 5335 | intel_prepare_shared_dpll(intel_crtc); |
| 5336 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 5337 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 5338 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 5339 | |
| 5340 | intel_set_pipe_timings(intel_crtc); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 5341 | intel_set_pipe_src_size(intel_crtc); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 5342 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5343 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 5344 | intel_cpu_transcoder_set_m_n(intel_crtc, |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5345 | &intel_crtc->config->fdi_m_n, NULL); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 5346 | } |
| 5347 | |
| 5348 | ironlake_set_pipeconf(crtc); |
| 5349 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5350 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 5351 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5352 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5353 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5354 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | fff367c | 2012-10-27 15:50:28 +0200 | [diff] [blame] | 5355 | /* Note: FDI PLL enabling _must_ be done before we enable the |
| 5356 | * cpu pipes, hence this is separate from all the other fdi/pch |
| 5357 | * enabling. */ |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 5358 | ironlake_fdi_pll_enable(intel_crtc); |
Daniel Vetter | 46b6f81 | 2012-09-06 22:08:33 +0200 | [diff] [blame] | 5359 | } else { |
| 5360 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 5361 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 5362 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5363 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 5364 | ironlake_pfit_enable(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5365 | |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 5366 | /* |
| 5367 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 5368 | * clocks enabled |
| 5369 | */ |
Maarten Lankhorst | b95c532 | 2016-03-30 17:16:34 +0200 | [diff] [blame] | 5370 | intel_color_load_luts(&pipe_config->base); |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 5371 | |
Imre Deak | 1d5bf5d | 2016-02-29 22:10:33 +0200 | [diff] [blame] | 5372 | if (dev_priv->display.initial_watermarks != NULL) |
| 5373 | dev_priv->display.initial_watermarks(intel_crtc->config); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 5374 | intel_enable_pipe(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5375 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5376 | if (intel_crtc->config->has_pch_encoder) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 5377 | ironlake_pch_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5378 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5379 | assert_vblank_disabled(crtc); |
| 5380 | drm_crtc_vblank_on(crtc); |
| 5381 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5382 | intel_encoders_enable(crtc, pipe_config, old_state); |
Daniel Vetter | 61b77dd | 2012-07-02 00:16:19 +0200 | [diff] [blame] | 5383 | |
| 5384 | if (HAS_PCH_CPT(dev)) |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 5385 | cpt_verify_modeset(dev, intel_crtc->pipe); |
Ville Syrjälä | 37ca8d4 | 2015-10-30 19:20:27 +0200 | [diff] [blame] | 5386 | |
| 5387 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ |
| 5388 | if (intel_crtc->config->has_pch_encoder) |
| 5389 | intel_wait_for_vblank(dev, pipe); |
Ville Syrjälä | b2c0593 | 2016-04-01 21:53:17 +0300 | [diff] [blame] | 5390 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | 37ca8d4 | 2015-10-30 19:20:27 +0200 | [diff] [blame] | 5391 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5392 | } |
| 5393 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5394 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 5395 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
| 5396 | { |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 5397 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5398 | } |
| 5399 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5400 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
| 5401 | struct drm_atomic_state *old_state) |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5402 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5403 | struct drm_crtc *crtc = pipe_config->base.crtc; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5404 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5405 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5406 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 5407 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5408 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5409 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 5410 | if (WARN_ON(intel_crtc->active)) |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5411 | return; |
| 5412 | |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5413 | if (intel_crtc->config->has_pch_encoder) |
| 5414 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5415 | false); |
| 5416 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5417 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 5418 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 5419 | if (intel_crtc->config->shared_dpll) |
Daniel Vetter | df8ad70 | 2014-06-25 22:02:03 +0300 | [diff] [blame] | 5420 | intel_enable_shared_dpll(intel_crtc); |
| 5421 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 5422 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 5423 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5424 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5425 | if (!transcoder_is_dsi(cpu_transcoder)) |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5426 | intel_set_pipe_timings(intel_crtc); |
| 5427 | |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 5428 | intel_set_pipe_src_size(intel_crtc); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5429 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5430 | if (cpu_transcoder != TRANSCODER_EDP && |
| 5431 | !transcoder_is_dsi(cpu_transcoder)) { |
| 5432 | I915_WRITE(PIPE_MULT(cpu_transcoder), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5433 | intel_crtc->config->pixel_multiplier - 1); |
Clint Taylor | ebb69c9 | 2014-09-30 10:30:22 -0700 | [diff] [blame] | 5434 | } |
| 5435 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5436 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5437 | intel_cpu_transcoder_set_m_n(intel_crtc, |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5438 | &intel_crtc->config->fdi_m_n, NULL); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5439 | } |
| 5440 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5441 | if (!transcoder_is_dsi(cpu_transcoder)) |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5442 | haswell_set_pipeconf(crtc); |
| 5443 | |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 5444 | haswell_set_pipemisc(crtc); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5445 | |
Maarten Lankhorst | b95c532 | 2016-03-30 17:16:34 +0200 | [diff] [blame] | 5446 | intel_color_set_csc(&pipe_config->base); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5447 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5448 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 5449 | |
Daniel Vetter | 6b69851 | 2015-11-28 11:05:39 +0100 | [diff] [blame] | 5450 | if (intel_crtc->config->has_pch_encoder) |
| 5451 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5452 | else |
| 5453 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5454 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5455 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5456 | |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5457 | if (intel_crtc->config->has_pch_encoder) |
Imre Deak | 4fe9467 | 2014-06-25 22:01:49 +0300 | [diff] [blame] | 5458 | dev_priv->display.fdi_link_train(crtc); |
Imre Deak | 4fe9467 | 2014-06-25 22:01:49 +0300 | [diff] [blame] | 5459 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5460 | if (!transcoder_is_dsi(cpu_transcoder)) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5461 | intel_ddi_enable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5462 | |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 5463 | if (INTEL_INFO(dev)->gen >= 9) |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 5464 | skylake_pfit_enable(intel_crtc); |
Jesse Barnes | ff6d9f5 | 2015-01-21 17:19:54 -0800 | [diff] [blame] | 5465 | else |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 5466 | ironlake_pfit_enable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5467 | |
| 5468 | /* |
| 5469 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 5470 | * clocks enabled |
| 5471 | */ |
Maarten Lankhorst | b95c532 | 2016-03-30 17:16:34 +0200 | [diff] [blame] | 5472 | intel_color_load_luts(&pipe_config->base); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5473 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 5474 | intel_ddi_set_pipe_settings(crtc); |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5475 | if (!transcoder_is_dsi(cpu_transcoder)) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5476 | intel_ddi_enable_transcoder_func(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5477 | |
Imre Deak | 1d5bf5d | 2016-02-29 22:10:33 +0200 | [diff] [blame] | 5478 | if (dev_priv->display.initial_watermarks != NULL) |
| 5479 | dev_priv->display.initial_watermarks(pipe_config); |
| 5480 | else |
| 5481 | intel_update_watermarks(crtc); |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5482 | |
| 5483 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5484 | if (!transcoder_is_dsi(cpu_transcoder)) |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5485 | intel_enable_pipe(intel_crtc); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5486 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5487 | if (intel_crtc->config->has_pch_encoder) |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 5488 | lpt_pch_enable(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5489 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 5490 | if (intel_crtc->config->dp_encoder_is_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5491 | intel_ddi_set_vc_payload_alloc(crtc, true); |
| 5492 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5493 | assert_vblank_disabled(crtc); |
| 5494 | drm_crtc_vblank_on(crtc); |
| 5495 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5496 | intel_encoders_enable(crtc, pipe_config, old_state); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5497 | |
Daniel Vetter | 6b69851 | 2015-11-28 11:05:39 +0100 | [diff] [blame] | 5498 | if (intel_crtc->config->has_pch_encoder) { |
| 5499 | intel_wait_for_vblank(dev, pipe); |
| 5500 | intel_wait_for_vblank(dev, pipe); |
| 5501 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5502 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5503 | true); |
Daniel Vetter | 6b69851 | 2015-11-28 11:05:39 +0100 | [diff] [blame] | 5504 | } |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5505 | |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 5506 | /* If we change the relative order between pipe/planes enabling, we need |
| 5507 | * to change the workaround. */ |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 5508 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
| 5509 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
| 5510 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
| 5511 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
| 5512 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5513 | } |
| 5514 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5515 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 5516 | { |
| 5517 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5518 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 5519 | int pipe = crtc->pipe; |
| 5520 | |
| 5521 | /* To avoid upsetting the power well on haswell only disable the pfit if |
| 5522 | * it's in use. The hw state code will make sure we get this right. */ |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5523 | if (force || crtc->config->pch_pfit.enabled) { |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 5524 | I915_WRITE(PF_CTL(pipe), 0); |
| 5525 | I915_WRITE(PF_WIN_POS(pipe), 0); |
| 5526 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
| 5527 | } |
| 5528 | } |
| 5529 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5530 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
| 5531 | struct drm_atomic_state *old_state) |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5532 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5533 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5534 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5535 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5536 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5537 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5538 | |
Ville Syrjälä | b2c0593 | 2016-04-01 21:53:17 +0300 | [diff] [blame] | 5539 | /* |
| 5540 | * Sometimes spurious CPU pipe underruns happen when the |
| 5541 | * pipe is already disabled, but FDI RX/TX is still enabled. |
| 5542 | * Happens at least with VGA+HDMI cloning. Suppress them. |
| 5543 | */ |
| 5544 | if (intel_crtc->config->has_pch_encoder) { |
| 5545 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
Ville Syrjälä | 37ca8d4 | 2015-10-30 19:20:27 +0200 | [diff] [blame] | 5546 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
Ville Syrjälä | b2c0593 | 2016-04-01 21:53:17 +0300 | [diff] [blame] | 5547 | } |
Ville Syrjälä | 37ca8d4 | 2015-10-30 19:20:27 +0200 | [diff] [blame] | 5548 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5549 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 5550 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5551 | drm_crtc_vblank_off(crtc); |
| 5552 | assert_vblank_disabled(crtc); |
| 5553 | |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 5554 | intel_disable_pipe(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5555 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5556 | ironlake_pfit_disable(intel_crtc, false); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5557 | |
Ville Syrjälä | b2c0593 | 2016-04-01 21:53:17 +0300 | [diff] [blame] | 5558 | if (intel_crtc->config->has_pch_encoder) |
Ville Syrjälä | 5a74f70 | 2015-05-05 17:17:38 +0300 | [diff] [blame] | 5559 | ironlake_fdi_disable(crtc); |
| 5560 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5561 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5562 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5563 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5564 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5565 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5566 | if (HAS_PCH_CPT(dev)) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5567 | i915_reg_t reg; |
| 5568 | u32 temp; |
| 5569 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5570 | /* disable TRANS_DP_CTL */ |
| 5571 | reg = TRANS_DP_CTL(pipe); |
| 5572 | temp = I915_READ(reg); |
| 5573 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
| 5574 | TRANS_DP_PORT_SEL_MASK); |
| 5575 | temp |= TRANS_DP_PORT_SEL_NONE; |
| 5576 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5577 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5578 | /* disable DPLL_SEL */ |
| 5579 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 5580 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5581 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 5582 | } |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5583 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5584 | ironlake_fdi_pll_disable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5585 | } |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5586 | |
Ville Syrjälä | b2c0593 | 2016-04-01 21:53:17 +0300 | [diff] [blame] | 5587 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5588 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5589 | } |
| 5590 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5591 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
| 5592 | struct drm_atomic_state *old_state) |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5593 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 5594 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5595 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5596 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5597 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5598 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5599 | |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5600 | if (intel_crtc->config->has_pch_encoder) |
| 5601 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5602 | false); |
| 5603 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5604 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5605 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5606 | drm_crtc_vblank_off(crtc); |
| 5607 | assert_vblank_disabled(crtc); |
| 5608 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5609 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5610 | if (!transcoder_is_dsi(cpu_transcoder)) |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 5611 | intel_disable_pipe(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5612 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5613 | if (intel_crtc->config->dp_encoder_is_mst) |
Ville Syrjälä | a4bf214 | 2014-08-18 21:27:34 +0300 | [diff] [blame] | 5614 | intel_ddi_set_vc_payload_alloc(crtc, false); |
| 5615 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5616 | if (!transcoder_is_dsi(cpu_transcoder)) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5617 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5618 | |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 5619 | if (INTEL_INFO(dev)->gen >= 9) |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 5620 | skylake_scaler_disable(intel_crtc); |
Jesse Barnes | ff6d9f5 | 2015-01-21 17:19:54 -0800 | [diff] [blame] | 5621 | else |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5622 | ironlake_pfit_disable(intel_crtc, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5623 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 5624 | if (!transcoder_is_dsi(cpu_transcoder)) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5625 | intel_ddi_disable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5626 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 5627 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5628 | |
Maarten Lankhorst | b707654 | 2016-08-23 16:18:08 +0200 | [diff] [blame] | 5629 | if (old_crtc_state->has_pch_encoder) |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5630 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5631 | true); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5632 | } |
| 5633 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5634 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
| 5635 | { |
| 5636 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5637 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5638 | struct intel_crtc_state *pipe_config = crtc->config; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5639 | |
Ander Conselvan de Oliveira | 681a850 | 2015-01-15 14:55:24 +0200 | [diff] [blame] | 5640 | if (!pipe_config->gmch_pfit.control) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5641 | return; |
| 5642 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 5643 | /* |
| 5644 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
| 5645 | * according to register description and PRM. |
| 5646 | */ |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5647 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
| 5648 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 5649 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 5650 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
| 5651 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
Daniel Vetter | 5a80c45 | 2013-04-25 22:52:18 +0200 | [diff] [blame] | 5652 | |
| 5653 | /* Border color in case we don't scale up to the full screen. Black by |
| 5654 | * default, change to something else for debugging. */ |
| 5655 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5656 | } |
| 5657 | |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5658 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
| 5659 | { |
| 5660 | switch (port) { |
| 5661 | case PORT_A: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5662 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5663 | case PORT_B: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5664 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5665 | case PORT_C: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5666 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5667 | case PORT_D: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5668 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
Xiong Zhang | d8e19f9 | 2015-08-13 18:00:12 +0800 | [diff] [blame] | 5669 | case PORT_E: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5670 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5671 | default: |
Imre Deak | b9fec16 | 2015-11-18 15:57:25 +0200 | [diff] [blame] | 5672 | MISSING_CASE(port); |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5673 | return POWER_DOMAIN_PORT_OTHER; |
| 5674 | } |
| 5675 | } |
| 5676 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5677 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
| 5678 | { |
| 5679 | switch (port) { |
| 5680 | case PORT_A: |
| 5681 | return POWER_DOMAIN_AUX_A; |
| 5682 | case PORT_B: |
| 5683 | return POWER_DOMAIN_AUX_B; |
| 5684 | case PORT_C: |
| 5685 | return POWER_DOMAIN_AUX_C; |
| 5686 | case PORT_D: |
| 5687 | return POWER_DOMAIN_AUX_D; |
| 5688 | case PORT_E: |
| 5689 | /* FIXME: Check VBT for actual wiring of PORT E */ |
| 5690 | return POWER_DOMAIN_AUX_D; |
| 5691 | default: |
Imre Deak | b9fec16 | 2015-11-18 15:57:25 +0200 | [diff] [blame] | 5692 | MISSING_CASE(port); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5693 | return POWER_DOMAIN_AUX_A; |
| 5694 | } |
| 5695 | } |
| 5696 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5697 | enum intel_display_power_domain |
| 5698 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5699 | { |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5700 | struct drm_device *dev = intel_encoder->base.dev; |
| 5701 | struct intel_digital_port *intel_dig_port; |
| 5702 | |
| 5703 | switch (intel_encoder->type) { |
| 5704 | case INTEL_OUTPUT_UNKNOWN: |
| 5705 | /* Only DDI platforms should ever use this output type */ |
| 5706 | WARN_ON_ONCE(!HAS_DDI(dev)); |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 5707 | case INTEL_OUTPUT_DP: |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5708 | case INTEL_OUTPUT_HDMI: |
| 5709 | case INTEL_OUTPUT_EDP: |
| 5710 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5711 | return port_to_power_domain(intel_dig_port->port); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5712 | case INTEL_OUTPUT_DP_MST: |
| 5713 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 5714 | return port_to_power_domain(intel_dig_port->port); |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5715 | case INTEL_OUTPUT_ANALOG: |
| 5716 | return POWER_DOMAIN_PORT_CRT; |
| 5717 | case INTEL_OUTPUT_DSI: |
| 5718 | return POWER_DOMAIN_PORT_DSI; |
| 5719 | default: |
| 5720 | return POWER_DOMAIN_PORT_OTHER; |
| 5721 | } |
| 5722 | } |
| 5723 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5724 | enum intel_display_power_domain |
| 5725 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) |
| 5726 | { |
| 5727 | struct drm_device *dev = intel_encoder->base.dev; |
| 5728 | struct intel_digital_port *intel_dig_port; |
| 5729 | |
| 5730 | switch (intel_encoder->type) { |
| 5731 | case INTEL_OUTPUT_UNKNOWN: |
Imre Deak | 651174a | 2015-11-18 15:57:24 +0200 | [diff] [blame] | 5732 | case INTEL_OUTPUT_HDMI: |
| 5733 | /* |
| 5734 | * Only DDI platforms should ever use these output types. |
| 5735 | * We can get here after the HDMI detect code has already set |
| 5736 | * the type of the shared encoder. Since we can't be sure |
| 5737 | * what's the status of the given connectors, play safe and |
| 5738 | * run the DP detection too. |
| 5739 | */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5740 | WARN_ON_ONCE(!HAS_DDI(dev)); |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 5741 | case INTEL_OUTPUT_DP: |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5742 | case INTEL_OUTPUT_EDP: |
| 5743 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 5744 | return port_to_aux_power_domain(intel_dig_port->port); |
| 5745 | case INTEL_OUTPUT_DP_MST: |
| 5746 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 5747 | return port_to_aux_power_domain(intel_dig_port->port); |
| 5748 | default: |
Imre Deak | b9fec16 | 2015-11-18 15:57:25 +0200 | [diff] [blame] | 5749 | MISSING_CASE(intel_encoder->type); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5750 | return POWER_DOMAIN_AUX_A; |
| 5751 | } |
| 5752 | } |
| 5753 | |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5754 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
| 5755 | struct intel_crtc_state *crtc_state) |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5756 | { |
| 5757 | struct drm_device *dev = crtc->dev; |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5758 | struct drm_encoder *encoder; |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5760 | enum pipe pipe = intel_crtc->pipe; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5761 | unsigned long mask; |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5762 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5763 | |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5764 | if (!crtc_state->base.active) |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5765 | return 0; |
| 5766 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5767 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
| 5768 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5769 | if (crtc_state->pch_pfit.enabled || |
| 5770 | crtc_state->pch_pfit.force_thru) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5771 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
| 5772 | |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5773 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
| 5774 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 5775 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5776 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5777 | } |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5778 | |
Maarten Lankhorst | 15e7ec2 | 2016-03-14 09:27:54 +0100 | [diff] [blame] | 5779 | if (crtc_state->shared_dpll) |
| 5780 | mask |= BIT(POWER_DOMAIN_PLLS); |
| 5781 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5782 | return mask; |
| 5783 | } |
| 5784 | |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5785 | static unsigned long |
| 5786 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
| 5787 | struct intel_crtc_state *crtc_state) |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5788 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5789 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5791 | enum intel_display_power_domain domain; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5792 | unsigned long domains, new_domains, old_domains; |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5793 | |
| 5794 | old_domains = intel_crtc->enabled_power_domains; |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 5795 | intel_crtc->enabled_power_domains = new_domains = |
| 5796 | get_crtc_power_domains(crtc, crtc_state); |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5797 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5798 | domains = new_domains & ~old_domains; |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5799 | |
| 5800 | for_each_power_domain(domain, domains) |
| 5801 | intel_display_power_get(dev_priv, domain); |
| 5802 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 5803 | return old_domains & ~new_domains; |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5804 | } |
| 5805 | |
| 5806 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, |
| 5807 | unsigned long domains) |
| 5808 | { |
| 5809 | enum intel_display_power_domain domain; |
| 5810 | |
| 5811 | for_each_power_domain(domain, domains) |
| 5812 | intel_display_power_put(dev_priv, domain); |
| 5813 | } |
| 5814 | |
Mika Kahola | adafdc6 | 2015-08-18 14:36:59 +0300 | [diff] [blame] | 5815 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
| 5816 | { |
| 5817 | int max_cdclk_freq = dev_priv->max_cdclk_freq; |
| 5818 | |
| 5819 | if (INTEL_INFO(dev_priv)->gen >= 9 || |
| 5820 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 5821 | return max_cdclk_freq; |
| 5822 | else if (IS_CHERRYVIEW(dev_priv)) |
| 5823 | return max_cdclk_freq*95/100; |
| 5824 | else if (INTEL_INFO(dev_priv)->gen < 4) |
| 5825 | return 2*max_cdclk_freq*90/100; |
| 5826 | else |
| 5827 | return max_cdclk_freq*90/100; |
| 5828 | } |
| 5829 | |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5830 | static int skl_calc_cdclk(int max_pixclk, int vco); |
| 5831 | |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5832 | static void intel_update_max_cdclk(struct drm_device *dev) |
| 5833 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5834 | struct drm_i915_private *dev_priv = to_i915(dev); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5835 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 5836 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5837 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5838 | int max_cdclk, vco; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5839 | |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5840 | vco = dev_priv->skl_preferred_vco_freq; |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 5841 | WARN_ON(vco != 8100000 && vco != 8640000); |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5842 | |
| 5843 | /* |
| 5844 | * Use the lower (vco 8640) cdclk values as a |
| 5845 | * first guess. skl_calc_cdclk() will correct it |
| 5846 | * if the preferred vco is 8100 instead. |
| 5847 | */ |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5848 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 5849 | max_cdclk = 617143; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5850 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5851 | max_cdclk = 540000; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5852 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5853 | max_cdclk = 432000; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5854 | else |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 5855 | max_cdclk = 308571; |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 5856 | |
| 5857 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); |
Matt Roper | 281c114 | 2016-04-05 14:37:19 -0700 | [diff] [blame] | 5858 | } else if (IS_BROXTON(dev)) { |
| 5859 | dev_priv->max_cdclk_freq = 624000; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5860 | } else if (IS_BROADWELL(dev)) { |
| 5861 | /* |
| 5862 | * FIXME with extra cooling we can allow |
| 5863 | * 540 MHz for ULX and 675 Mhz for ULT. |
| 5864 | * How can we know if extra cooling is |
| 5865 | * available? PCI ID, VTB, something else? |
| 5866 | */ |
| 5867 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 5868 | dev_priv->max_cdclk_freq = 450000; |
| 5869 | else if (IS_BDW_ULX(dev)) |
| 5870 | dev_priv->max_cdclk_freq = 450000; |
| 5871 | else if (IS_BDW_ULT(dev)) |
| 5872 | dev_priv->max_cdclk_freq = 540000; |
| 5873 | else |
| 5874 | dev_priv->max_cdclk_freq = 675000; |
Mika Kahola | 0904dea | 2015-06-12 10:11:32 +0300 | [diff] [blame] | 5875 | } else if (IS_CHERRYVIEW(dev)) { |
| 5876 | dev_priv->max_cdclk_freq = 320000; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5877 | } else if (IS_VALLEYVIEW(dev)) { |
| 5878 | dev_priv->max_cdclk_freq = 400000; |
| 5879 | } else { |
| 5880 | /* otherwise assume cdclk is fixed */ |
| 5881 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; |
| 5882 | } |
| 5883 | |
Mika Kahola | adafdc6 | 2015-08-18 14:36:59 +0300 | [diff] [blame] | 5884 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
| 5885 | |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5886 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
| 5887 | dev_priv->max_cdclk_freq); |
Mika Kahola | adafdc6 | 2015-08-18 14:36:59 +0300 | [diff] [blame] | 5888 | |
| 5889 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", |
| 5890 | dev_priv->max_dotclk_freq); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5891 | } |
| 5892 | |
| 5893 | static void intel_update_cdclk(struct drm_device *dev) |
| 5894 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5895 | struct drm_i915_private *dev_priv = to_i915(dev); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5896 | |
| 5897 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
Ville Syrjälä | 2f2a121 | 2016-05-13 23:41:25 +0300 | [diff] [blame] | 5898 | |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 5899 | if (INTEL_GEN(dev_priv) >= 9) |
Ville Syrjälä | 709e05c | 2016-05-13 23:41:33 +0300 | [diff] [blame] | 5900 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
| 5901 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, |
| 5902 | dev_priv->cdclk_pll.ref); |
Ville Syrjälä | 2f2a121 | 2016-05-13 23:41:25 +0300 | [diff] [blame] | 5903 | else |
| 5904 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
| 5905 | dev_priv->cdclk_freq); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5906 | |
| 5907 | /* |
Ville Syrjälä | b5d99ff | 2016-04-26 19:46:34 +0300 | [diff] [blame] | 5908 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
| 5909 | * Programmng [sic] note: bit[9:2] should be programmed to the number |
| 5910 | * of cdclk that generates 4MHz reference clock freq which is used to |
| 5911 | * generate GMBus clock. This will vary with the cdclk freq. |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5912 | */ |
Ville Syrjälä | b5d99ff | 2016-04-26 19:46:34 +0300 | [diff] [blame] | 5913 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5914 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5915 | } |
| 5916 | |
Ville Syrjälä | 92891e4 | 2016-05-11 22:44:45 +0300 | [diff] [blame] | 5917 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
| 5918 | static int skl_cdclk_decimal(int cdclk) |
| 5919 | { |
| 5920 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); |
| 5921 | } |
| 5922 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5923 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
| 5924 | { |
| 5925 | int ratio; |
| 5926 | |
| 5927 | if (cdclk == dev_priv->cdclk_pll.ref) |
| 5928 | return 0; |
| 5929 | |
| 5930 | switch (cdclk) { |
| 5931 | default: |
| 5932 | MISSING_CASE(cdclk); |
| 5933 | case 144000: |
| 5934 | case 288000: |
| 5935 | case 384000: |
| 5936 | case 576000: |
| 5937 | ratio = 60; |
| 5938 | break; |
| 5939 | case 624000: |
| 5940 | ratio = 65; |
| 5941 | break; |
| 5942 | } |
| 5943 | |
| 5944 | return dev_priv->cdclk_pll.ref * ratio; |
| 5945 | } |
| 5946 | |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5947 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
| 5948 | { |
| 5949 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); |
| 5950 | |
| 5951 | /* Timeout 200us */ |
Chris Wilson | 95cac28 | 2016-06-30 15:33:03 +0100 | [diff] [blame] | 5952 | if (intel_wait_for_register(dev_priv, |
| 5953 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, |
| 5954 | 1)) |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5955 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 5956 | |
| 5957 | dev_priv->cdclk_pll.vco = 0; |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5958 | } |
| 5959 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5960 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5961 | { |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5962 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5963 | u32 val; |
| 5964 | |
| 5965 | val = I915_READ(BXT_DE_PLL_CTL); |
| 5966 | val &= ~BXT_DE_PLL_RATIO_MASK; |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5967 | val |= BXT_DE_PLL_RATIO(ratio); |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5968 | I915_WRITE(BXT_DE_PLL_CTL, val); |
| 5969 | |
| 5970 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); |
| 5971 | |
| 5972 | /* Timeout 200us */ |
Chris Wilson | e084e1b | 2016-06-30 15:33:04 +0100 | [diff] [blame] | 5973 | if (intel_wait_for_register(dev_priv, |
| 5974 | BXT_DE_PLL_ENABLE, |
| 5975 | BXT_DE_PLL_LOCK, |
| 5976 | BXT_DE_PLL_LOCK, |
| 5977 | 1)) |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5978 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 5979 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5980 | dev_priv->cdclk_pll.vco = vco; |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 5981 | } |
| 5982 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 5983 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5984 | { |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5985 | u32 val, divider; |
| 5986 | int vco, ret; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5987 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5988 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
| 5989 | |
| 5990 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
| 5991 | |
| 5992 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ |
| 5993 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { |
| 5994 | case 8: |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5995 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5996 | break; |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 5997 | case 4: |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5998 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5999 | break; |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6000 | case 3: |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6001 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6002 | break; |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6003 | case 2: |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6004 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6005 | break; |
| 6006 | default: |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6007 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
| 6008 | WARN_ON(vco != 0); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6009 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6010 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 6011 | break; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6012 | } |
| 6013 | |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6014 | /* Inform power controller of upcoming frequency change */ |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6015 | mutex_lock(&dev_priv->rps.hw_lock); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6016 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 6017 | 0x80000000); |
| 6018 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6019 | |
| 6020 | if (ret) { |
| 6021 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", |
Ville Syrjälä | 9ef5615 | 2016-05-11 22:44:49 +0300 | [diff] [blame] | 6022 | ret, cdclk); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6023 | return; |
| 6024 | } |
| 6025 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6026 | if (dev_priv->cdclk_pll.vco != 0 && |
| 6027 | dev_priv->cdclk_pll.vco != vco) |
Ville Syrjälä | 2b73001 | 2016-05-13 23:41:34 +0300 | [diff] [blame] | 6028 | bxt_de_pll_disable(dev_priv); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6029 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6030 | if (dev_priv->cdclk_pll.vco != vco) |
| 6031 | bxt_de_pll_enable(dev_priv, vco); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6032 | |
Ville Syrjälä | 5f199df | 2016-05-13 23:41:38 +0300 | [diff] [blame] | 6033 | val = divider | skl_cdclk_decimal(cdclk); |
| 6034 | /* |
| 6035 | * FIXME if only the cd2x divider needs changing, it could be done |
| 6036 | * without shutting off the pipe (if only one pipe is active). |
| 6037 | */ |
| 6038 | val |= BXT_CDCLK_CD2X_PIPE_NONE; |
| 6039 | /* |
| 6040 | * Disable SSA Precharge when CD clock frequency < 500 MHz, |
| 6041 | * enable otherwise. |
| 6042 | */ |
| 6043 | if (cdclk >= 500000) |
| 6044 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 6045 | I915_WRITE(CDCLK_CTL, val); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6046 | |
| 6047 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6048 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
Ville Syrjälä | 9ef5615 | 2016-05-11 22:44:49 +0300 | [diff] [blame] | 6049 | DIV_ROUND_UP(cdclk, 25000)); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6050 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6051 | |
| 6052 | if (ret) { |
| 6053 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", |
Ville Syrjälä | 9ef5615 | 2016-05-11 22:44:49 +0300 | [diff] [blame] | 6054 | ret, cdclk); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6055 | return; |
| 6056 | } |
| 6057 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 6058 | intel_update_cdclk(&dev_priv->drm); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6059 | } |
| 6060 | |
Imre Deak | d66a219 | 2016-05-24 15:38:33 +0300 | [diff] [blame] | 6061 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6062 | { |
Imre Deak | d66a219 | 2016-05-24 15:38:33 +0300 | [diff] [blame] | 6063 | u32 cdctl, expected; |
| 6064 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 6065 | intel_update_cdclk(&dev_priv->drm); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6066 | |
Imre Deak | d66a219 | 2016-05-24 15:38:33 +0300 | [diff] [blame] | 6067 | if (dev_priv->cdclk_pll.vco == 0 || |
| 6068 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) |
| 6069 | goto sanitize; |
| 6070 | |
| 6071 | /* DPLL okay; verify the cdclock |
| 6072 | * |
| 6073 | * Some BIOS versions leave an incorrect decimal frequency value and |
| 6074 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, |
| 6075 | * so sanitize this register. |
| 6076 | */ |
| 6077 | cdctl = I915_READ(CDCLK_CTL); |
| 6078 | /* |
| 6079 | * Let's ignore the pipe field, since BIOS could have configured the |
| 6080 | * dividers both synching to an active pipe, or asynchronously |
| 6081 | * (PIPE_NONE). |
| 6082 | */ |
| 6083 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; |
| 6084 | |
| 6085 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | |
| 6086 | skl_cdclk_decimal(dev_priv->cdclk_freq); |
| 6087 | /* |
| 6088 | * Disable SSA Precharge when CD clock frequency < 500 MHz, |
| 6089 | * enable otherwise. |
| 6090 | */ |
| 6091 | if (dev_priv->cdclk_freq >= 500000) |
| 6092 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 6093 | |
| 6094 | if (cdctl == expected) |
| 6095 | /* All well; nothing to sanitize */ |
| 6096 | return; |
| 6097 | |
| 6098 | sanitize: |
| 6099 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); |
| 6100 | |
| 6101 | /* force cdclk programming */ |
| 6102 | dev_priv->cdclk_freq = 0; |
| 6103 | |
| 6104 | /* force full PLL disable + enable */ |
| 6105 | dev_priv->cdclk_pll.vco = -1; |
| 6106 | } |
| 6107 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6108 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
Imre Deak | d66a219 | 2016-05-24 15:38:33 +0300 | [diff] [blame] | 6109 | { |
| 6110 | bxt_sanitize_cdclk(dev_priv); |
| 6111 | |
| 6112 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) |
Ville Syrjälä | 089c6fd | 2016-05-13 23:41:36 +0300 | [diff] [blame] | 6113 | return; |
Imre Deak | c2e001e | 2016-04-01 16:02:43 +0300 | [diff] [blame] | 6114 | |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6115 | /* |
| 6116 | * FIXME: |
| 6117 | * - The initial CDCLK needs to be read from VBT. |
| 6118 | * Need to make this change after VBT has changes for BXT. |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6119 | */ |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6120 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6121 | } |
| 6122 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6123 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6124 | { |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6125 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6126 | } |
| 6127 | |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6128 | static int skl_calc_cdclk(int max_pixclk, int vco) |
| 6129 | { |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6130 | if (vco == 8640000) { |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6131 | if (max_pixclk > 540000) |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 6132 | return 617143; |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6133 | else if (max_pixclk > 432000) |
| 6134 | return 540000; |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 6135 | else if (max_pixclk > 308571) |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6136 | return 432000; |
| 6137 | else |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 6138 | return 308571; |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6139 | } else { |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6140 | if (max_pixclk > 540000) |
| 6141 | return 675000; |
| 6142 | else if (max_pixclk > 450000) |
| 6143 | return 540000; |
| 6144 | else if (max_pixclk > 337500) |
| 6145 | return 450000; |
| 6146 | else |
| 6147 | return 337500; |
| 6148 | } |
| 6149 | } |
| 6150 | |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6151 | static void |
| 6152 | skl_dpll0_update(struct drm_i915_private *dev_priv) |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6153 | { |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6154 | u32 val; |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6155 | |
Ville Syrjälä | 709e05c | 2016-05-13 23:41:33 +0300 | [diff] [blame] | 6156 | dev_priv->cdclk_pll.ref = 24000; |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 6157 | dev_priv->cdclk_pll.vco = 0; |
Ville Syrjälä | 709e05c | 2016-05-13 23:41:33 +0300 | [diff] [blame] | 6158 | |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6159 | val = I915_READ(LCPLL1_CTL); |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 6160 | if ((val & LCPLL_PLL_ENABLE) == 0) |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6161 | return; |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6162 | |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 6163 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
| 6164 | return; |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6165 | |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6166 | val = I915_READ(DPLL_CTRL1); |
| 6167 | |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 6168 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
| 6169 | DPLL_CTRL1_SSC(SKL_DPLL0) | |
| 6170 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != |
| 6171 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) |
| 6172 | return; |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6173 | |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6174 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
| 6175 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): |
| 6176 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): |
| 6177 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): |
| 6178 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6179 | dev_priv->cdclk_pll.vco = 8100000; |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6180 | break; |
| 6181 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): |
| 6182 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6183 | dev_priv->cdclk_pll.vco = 8640000; |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6184 | break; |
| 6185 | default: |
| 6186 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 6187 | break; |
| 6188 | } |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6189 | } |
| 6190 | |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 6191 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
| 6192 | { |
| 6193 | bool changed = dev_priv->skl_preferred_vco_freq != vco; |
| 6194 | |
| 6195 | dev_priv->skl_preferred_vco_freq = vco; |
| 6196 | |
| 6197 | if (changed) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 6198 | intel_update_max_cdclk(&dev_priv->drm); |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 6199 | } |
| 6200 | |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6201 | static void |
Ville Syrjälä | 3861fc6 | 2016-05-11 22:44:50 +0300 | [diff] [blame] | 6202 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6203 | { |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6204 | int min_cdclk = skl_calc_cdclk(0, vco); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6205 | u32 val; |
| 6206 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6207 | WARN_ON(vco != 8100000 && vco != 8640000); |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 6208 | |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6209 | /* select the minimum CDCLK before enabling DPLL 0 */ |
Ville Syrjälä | 9ef5615 | 2016-05-11 22:44:49 +0300 | [diff] [blame] | 6210 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6211 | I915_WRITE(CDCLK_CTL, val); |
| 6212 | POSTING_READ(CDCLK_CTL); |
| 6213 | |
| 6214 | /* |
| 6215 | * We always enable DPLL0 with the lowest link rate possible, but still |
| 6216 | * taking into account the VCO required to operate the eDP panel at the |
| 6217 | * desired frequency. The usual DP link rates operate with a VCO of |
| 6218 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. |
| 6219 | * The modeset code is responsible for the selection of the exact link |
| 6220 | * rate later on, with the constraint of choosing a frequency that |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 6221 | * works with vco. |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6222 | */ |
| 6223 | val = I915_READ(DPLL_CTRL1); |
| 6224 | |
| 6225 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | |
| 6226 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
| 6227 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6228 | if (vco == 8640000) |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6229 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
| 6230 | SKL_DPLL0); |
| 6231 | else |
| 6232 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
| 6233 | SKL_DPLL0); |
| 6234 | |
| 6235 | I915_WRITE(DPLL_CTRL1, val); |
| 6236 | POSTING_READ(DPLL_CTRL1); |
| 6237 | |
| 6238 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); |
| 6239 | |
Chris Wilson | e24ca05 | 2016-06-30 15:33:05 +0100 | [diff] [blame] | 6240 | if (intel_wait_for_register(dev_priv, |
| 6241 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, |
| 6242 | 5)) |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6243 | DRM_ERROR("DPLL0 not locked\n"); |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6244 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6245 | dev_priv->cdclk_pll.vco = vco; |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 6246 | |
| 6247 | /* We'll want to keep using the current vco from now on. */ |
| 6248 | skl_set_preferred_cdclk_vco(dev_priv, vco); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6249 | } |
| 6250 | |
Ville Syrjälä | 430e05d | 2016-05-11 22:44:47 +0300 | [diff] [blame] | 6251 | static void |
| 6252 | skl_dpll0_disable(struct drm_i915_private *dev_priv) |
| 6253 | { |
| 6254 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); |
Chris Wilson | 8ad32a05 | 2016-06-30 15:33:06 +0100 | [diff] [blame] | 6255 | if (intel_wait_for_register(dev_priv, |
| 6256 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, |
| 6257 | 1)) |
Ville Syrjälä | 430e05d | 2016-05-11 22:44:47 +0300 | [diff] [blame] | 6258 | DRM_ERROR("Couldn't disable DPLL0\n"); |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6259 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6260 | dev_priv->cdclk_pll.vco = 0; |
Ville Syrjälä | 430e05d | 2016-05-11 22:44:47 +0300 | [diff] [blame] | 6261 | } |
| 6262 | |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6263 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
| 6264 | { |
| 6265 | int ret; |
| 6266 | u32 val; |
| 6267 | |
| 6268 | /* inform PCU we want to change CDCLK */ |
| 6269 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; |
| 6270 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6271 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); |
| 6272 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6273 | |
| 6274 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); |
| 6275 | } |
| 6276 | |
| 6277 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) |
| 6278 | { |
Ville Syrjälä | 3b2c171 | 2016-07-13 16:32:03 +0300 | [diff] [blame] | 6279 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6280 | } |
| 6281 | |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6282 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6283 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 6284 | struct drm_device *dev = &dev_priv->drm; |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6285 | u32 freq_select, pcu_ack; |
| 6286 | |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6287 | WARN_ON((cdclk == 24000) != (vco == 0)); |
| 6288 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6289 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6290 | |
| 6291 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { |
| 6292 | DRM_ERROR("failed to inform PCU about cdclk change\n"); |
| 6293 | return; |
| 6294 | } |
| 6295 | |
| 6296 | /* set CDCLK_CTL */ |
Ville Syrjälä | 9ef5615 | 2016-05-11 22:44:49 +0300 | [diff] [blame] | 6297 | switch (cdclk) { |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6298 | case 450000: |
| 6299 | case 432000: |
| 6300 | freq_select = CDCLK_FREQ_450_432; |
| 6301 | pcu_ack = 1; |
| 6302 | break; |
| 6303 | case 540000: |
| 6304 | freq_select = CDCLK_FREQ_540; |
| 6305 | pcu_ack = 2; |
| 6306 | break; |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 6307 | case 308571: |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6308 | case 337500: |
| 6309 | default: |
| 6310 | freq_select = CDCLK_FREQ_337_308; |
| 6311 | pcu_ack = 0; |
| 6312 | break; |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 6313 | case 617143: |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6314 | case 675000: |
| 6315 | freq_select = CDCLK_FREQ_675_617; |
| 6316 | pcu_ack = 3; |
| 6317 | break; |
| 6318 | } |
| 6319 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6320 | if (dev_priv->cdclk_pll.vco != 0 && |
| 6321 | dev_priv->cdclk_pll.vco != vco) |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6322 | skl_dpll0_disable(dev_priv); |
| 6323 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6324 | if (dev_priv->cdclk_pll.vco != vco) |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6325 | skl_dpll0_enable(dev_priv, vco); |
| 6326 | |
Ville Syrjälä | 9ef5615 | 2016-05-11 22:44:49 +0300 | [diff] [blame] | 6327 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6328 | POSTING_READ(CDCLK_CTL); |
| 6329 | |
| 6330 | /* inform PCU of the change */ |
| 6331 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6332 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); |
| 6333 | mutex_unlock(&dev_priv->rps.hw_lock); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 6334 | |
| 6335 | intel_update_cdclk(dev); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6336 | } |
| 6337 | |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6338 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
| 6339 | |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6340 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
| 6341 | { |
Ville Syrjälä | 709e05c | 2016-05-13 23:41:33 +0300 | [diff] [blame] | 6342 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6343 | } |
| 6344 | |
| 6345 | void skl_init_cdclk(struct drm_i915_private *dev_priv) |
| 6346 | { |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6347 | int cdclk, vco; |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6348 | |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6349 | skl_sanitize_cdclk(dev_priv); |
| 6350 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6351 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6352 | /* |
| 6353 | * Use the current vco as our initial |
| 6354 | * guess as to what the preferred vco is. |
| 6355 | */ |
| 6356 | if (dev_priv->skl_preferred_vco_freq == 0) |
| 6357 | skl_set_preferred_cdclk_vco(dev_priv, |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6358 | dev_priv->cdclk_pll.vco); |
Ville Syrjälä | 70c2c18 | 2016-05-13 23:41:30 +0300 | [diff] [blame] | 6359 | return; |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 6360 | } |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6361 | |
Ville Syrjälä | 70c2c18 | 2016-05-13 23:41:30 +0300 | [diff] [blame] | 6362 | vco = dev_priv->skl_preferred_vco_freq; |
| 6363 | if (vco == 0) |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6364 | vco = 8100000; |
Ville Syrjälä | 70c2c18 | 2016-05-13 23:41:30 +0300 | [diff] [blame] | 6365 | cdclk = skl_calc_cdclk(0, vco); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6366 | |
Ville Syrjälä | 70c2c18 | 2016-05-13 23:41:30 +0300 | [diff] [blame] | 6367 | skl_set_cdclk(dev_priv, cdclk, vco); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 6368 | } |
| 6369 | |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6370 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 6371 | { |
Ville Syrjälä | 0949249 | 2016-05-13 23:41:28 +0300 | [diff] [blame] | 6372 | uint32_t cdctl, expected; |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 6373 | |
Shobhit Kumar | f1b391a | 2015-11-05 18:05:32 +0530 | [diff] [blame] | 6374 | /* |
| 6375 | * check if the pre-os intialized the display |
| 6376 | * There is SWF18 scratchpad register defined which is set by the |
| 6377 | * pre-os which can be used by the OS drivers to check the status |
| 6378 | */ |
| 6379 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) |
| 6380 | goto sanitize; |
| 6381 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 6382 | intel_update_cdclk(&dev_priv->drm); |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 6383 | /* Is PLL enabled and locked ? */ |
| 6384 | if (dev_priv->cdclk_pll.vco == 0 || |
| 6385 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) |
| 6386 | goto sanitize; |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6387 | |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 6388 | /* DPLL okay; verify the cdclock |
| 6389 | * |
| 6390 | * Noticed in some instances that the freq selection is correct but |
| 6391 | * decimal part is programmed wrong from BIOS where pre-os does not |
| 6392 | * enable display. Verify the same as well. |
| 6393 | */ |
Ville Syrjälä | 0949249 | 2016-05-13 23:41:28 +0300 | [diff] [blame] | 6394 | cdctl = I915_READ(CDCLK_CTL); |
| 6395 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | |
| 6396 | skl_cdclk_decimal(dev_priv->cdclk_freq); |
| 6397 | if (cdctl == expected) |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 6398 | /* All well; nothing to sanitize */ |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6399 | return; |
| 6400 | |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 6401 | sanitize: |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6402 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 6403 | |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 6404 | /* force cdclk programming */ |
| 6405 | dev_priv->cdclk_freq = 0; |
| 6406 | /* force full PLL disable + enable */ |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 6407 | dev_priv->cdclk_pll.vco = -1; |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 6408 | } |
| 6409 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6410 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
| 6411 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
| 6412 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6413 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6414 | u32 val, cmd; |
| 6415 | |
Vandana Kannan | 164dfd2 | 2014-11-24 13:37:41 +0530 | [diff] [blame] | 6416 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
| 6417 | != dev_priv->cdclk_freq); |
Imre Deak | d60c447 | 2014-03-27 17:45:10 +0200 | [diff] [blame] | 6418 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6419 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6420 | cmd = 2; |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6421 | else if (cdclk == 266667) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6422 | cmd = 1; |
| 6423 | else |
| 6424 | cmd = 0; |
| 6425 | |
| 6426 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6427 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 6428 | val &= ~DSPFREQGUAR_MASK; |
| 6429 | val |= (cmd << DSPFREQGUAR_SHIFT); |
| 6430 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 6431 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 6432 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
| 6433 | 50)) { |
| 6434 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 6435 | } |
| 6436 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6437 | |
Ville Syrjälä | 54433e9 | 2015-05-26 20:42:31 +0300 | [diff] [blame] | 6438 | mutex_lock(&dev_priv->sb_lock); |
| 6439 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6440 | if (cdclk == 400000) { |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 6441 | u32 divider; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6442 | |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 6443 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6444 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6445 | /* adjust cdclk divider */ |
| 6446 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
Vandana Kannan | 87d5d25 | 2015-09-24 23:29:17 +0300 | [diff] [blame] | 6447 | val &= ~CCK_FREQUENCY_VALUES; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6448 | val |= divider; |
| 6449 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
Ville Syrjälä | a877e80 | 2014-06-13 13:37:52 +0300 | [diff] [blame] | 6450 | |
| 6451 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
Vandana Kannan | 87d5d25 | 2015-09-24 23:29:17 +0300 | [diff] [blame] | 6452 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
Ville Syrjälä | a877e80 | 2014-06-13 13:37:52 +0300 | [diff] [blame] | 6453 | 50)) |
| 6454 | DRM_ERROR("timed out waiting for CDclk change\n"); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6455 | } |
| 6456 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6457 | /* adjust self-refresh exit latency value */ |
| 6458 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
| 6459 | val &= ~0x7f; |
| 6460 | |
| 6461 | /* |
| 6462 | * For high bandwidth configs, we set a higher latency in the bunit |
| 6463 | * so that the core display fetch happens in time to avoid underruns. |
| 6464 | */ |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6465 | if (cdclk == 400000) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6466 | val |= 4500 / 250; /* 4.5 usec */ |
| 6467 | else |
| 6468 | val |= 3000 / 250; /* 3.0 usec */ |
| 6469 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
Ville Syrjälä | 54433e9 | 2015-05-26 20:42:31 +0300 | [diff] [blame] | 6470 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 6471 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6472 | |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 6473 | intel_update_cdclk(dev); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6474 | } |
| 6475 | |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6476 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
| 6477 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6478 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6479 | u32 val, cmd; |
| 6480 | |
Vandana Kannan | 164dfd2 | 2014-11-24 13:37:41 +0530 | [diff] [blame] | 6481 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
| 6482 | != dev_priv->cdclk_freq); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6483 | |
| 6484 | switch (cdclk) { |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6485 | case 333333: |
| 6486 | case 320000: |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6487 | case 266667: |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6488 | case 200000: |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6489 | break; |
| 6490 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 6491 | MISSING_CASE(cdclk); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6492 | return; |
| 6493 | } |
| 6494 | |
Ville Syrjälä | 9d0d3fd | 2015-03-02 20:07:17 +0200 | [diff] [blame] | 6495 | /* |
| 6496 | * Specs are full of misinformation, but testing on actual |
| 6497 | * hardware has shown that we just need to write the desired |
| 6498 | * CCK divider into the Punit register. |
| 6499 | */ |
| 6500 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
| 6501 | |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6502 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6503 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 6504 | val &= ~DSPFREQGUAR_MASK_CHV; |
| 6505 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); |
| 6506 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 6507 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 6508 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), |
| 6509 | 50)) { |
| 6510 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 6511 | } |
| 6512 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6513 | |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 6514 | intel_update_cdclk(dev); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6515 | } |
| 6516 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6517 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
| 6518 | int max_pixclk) |
| 6519 | { |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 6520 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6521 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 6522 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6523 | /* |
| 6524 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
| 6525 | * 200MHz |
| 6526 | * 267MHz |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 6527 | * 320/333MHz (depends on HPLL freq) |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6528 | * 400MHz (VLV only) |
| 6529 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) |
| 6530 | * of the lower bin and adjust if needed. |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 6531 | * |
| 6532 | * We seem to get an unstable or solid color picture at 200MHz. |
| 6533 | * Not sure what's wrong. For now use 200MHz only when all pipes |
| 6534 | * are off. |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6535 | */ |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6536 | if (!IS_CHERRYVIEW(dev_priv) && |
| 6537 | max_pixclk > freq_320*limit/100) |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6538 | return 400000; |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6539 | else if (max_pixclk > 266667*limit/100) |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 6540 | return freq_320; |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 6541 | else if (max_pixclk > 0) |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6542 | return 266667; |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 6543 | else |
| 6544 | return 200000; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6545 | } |
| 6546 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6547 | static int bxt_calc_cdclk(int max_pixclk) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6548 | { |
Ville Syrjälä | 760e147 | 2016-05-11 22:44:46 +0300 | [diff] [blame] | 6549 | if (max_pixclk > 576000) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6550 | return 624000; |
Ville Syrjälä | 760e147 | 2016-05-11 22:44:46 +0300 | [diff] [blame] | 6551 | else if (max_pixclk > 384000) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6552 | return 576000; |
Ville Syrjälä | 760e147 | 2016-05-11 22:44:46 +0300 | [diff] [blame] | 6553 | else if (max_pixclk > 288000) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6554 | return 384000; |
Ville Syrjälä | 760e147 | 2016-05-11 22:44:46 +0300 | [diff] [blame] | 6555 | else if (max_pixclk > 144000) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6556 | return 288000; |
| 6557 | else |
| 6558 | return 144000; |
| 6559 | } |
| 6560 | |
Maarten Lankhorst | e8788cb | 2016-02-16 10:25:11 +0100 | [diff] [blame] | 6561 | /* Compute the max pixel clock for new configuration. */ |
Ander Conselvan de Oliveira | a821fc4 | 2015-04-21 17:13:23 +0300 | [diff] [blame] | 6562 | static int intel_mode_max_pixclk(struct drm_device *dev, |
| 6563 | struct drm_atomic_state *state) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6564 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6565 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6566 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6567 | struct drm_crtc *crtc; |
| 6568 | struct drm_crtc_state *crtc_state; |
| 6569 | unsigned max_pixclk = 0, i; |
| 6570 | enum pipe pipe; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6571 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6572 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 6573 | sizeof(intel_state->min_pixclk)); |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6574 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6575 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 6576 | int pixclk = 0; |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6577 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6578 | if (crtc_state->enable) |
| 6579 | pixclk = crtc_state->adjusted_mode.crtc_clock; |
| 6580 | |
| 6581 | intel_state->min_pixclk[i] = pixclk; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6582 | } |
| 6583 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6584 | for_each_pipe(dev_priv, pipe) |
| 6585 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); |
| 6586 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6587 | return max_pixclk; |
| 6588 | } |
| 6589 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6590 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6591 | { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6592 | struct drm_device *dev = state->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6593 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6594 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6595 | struct intel_atomic_state *intel_state = |
| 6596 | to_intel_atomic_state(state); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6597 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6598 | intel_state->cdclk = intel_state->dev_cdclk = |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6599 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6600 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6601 | if (!intel_state->active_crtcs) |
| 6602 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); |
| 6603 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6604 | return 0; |
| 6605 | } |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6606 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6607 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6608 | { |
Ville Syrjälä | 4e5ca60 | 2016-05-11 22:44:44 +0300 | [diff] [blame] | 6609 | int max_pixclk = ilk_max_pixel_rate(state); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6610 | struct intel_atomic_state *intel_state = |
| 6611 | to_intel_atomic_state(state); |
Maarten Lankhorst | 85a96e7 | 2015-06-01 12:49:53 +0200 | [diff] [blame] | 6612 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6613 | intel_state->cdclk = intel_state->dev_cdclk = |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6614 | bxt_calc_cdclk(max_pixclk); |
Maarten Lankhorst | 85a96e7 | 2015-06-01 12:49:53 +0200 | [diff] [blame] | 6615 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6616 | if (!intel_state->active_crtcs) |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 6617 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6618 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6619 | return 0; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6620 | } |
| 6621 | |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 6622 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
| 6623 | { |
| 6624 | unsigned int credits, default_credits; |
| 6625 | |
| 6626 | if (IS_CHERRYVIEW(dev_priv)) |
| 6627 | default_credits = PFI_CREDIT(12); |
| 6628 | else |
| 6629 | default_credits = PFI_CREDIT(8); |
| 6630 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 6631 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 6632 | /* CHV suggested value is 31 or 63 */ |
| 6633 | if (IS_CHERRYVIEW(dev_priv)) |
Ville Syrjälä | fcc0008 | 2015-05-26 20:22:40 +0300 | [diff] [blame] | 6634 | credits = PFI_CREDIT_63; |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 6635 | else |
| 6636 | credits = PFI_CREDIT(15); |
| 6637 | } else { |
| 6638 | credits = default_credits; |
| 6639 | } |
| 6640 | |
| 6641 | /* |
| 6642 | * WA - write default credits before re-programming |
| 6643 | * FIXME: should we also set the resend bit here? |
| 6644 | */ |
| 6645 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 6646 | default_credits); |
| 6647 | |
| 6648 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 6649 | credits | PFI_CREDIT_RESEND); |
| 6650 | |
| 6651 | /* |
| 6652 | * FIXME is this guaranteed to clear |
| 6653 | * immediately or should we poll for it? |
| 6654 | */ |
| 6655 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); |
| 6656 | } |
| 6657 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6658 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6659 | { |
Ander Conselvan de Oliveira | a821fc4 | 2015-04-21 17:13:23 +0300 | [diff] [blame] | 6660 | struct drm_device *dev = old_state->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6661 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6662 | struct intel_atomic_state *old_intel_state = |
| 6663 | to_intel_atomic_state(old_state); |
| 6664 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6665 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6666 | /* |
| 6667 | * FIXME: We can end up here with all power domains off, yet |
| 6668 | * with a CDCLK frequency other than the minimum. To account |
| 6669 | * for this take the PIPE-A power domain, which covers the HW |
| 6670 | * blocks needed for the following programming. This can be |
| 6671 | * removed once it's guaranteed that we get here either with |
| 6672 | * the minimum CDCLK set, or the required power domains |
| 6673 | * enabled. |
| 6674 | */ |
| 6675 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6676 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6677 | if (IS_CHERRYVIEW(dev)) |
| 6678 | cherryview_set_cdclk(dev, req_cdclk); |
| 6679 | else |
| 6680 | valleyview_set_cdclk(dev, req_cdclk); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6681 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6682 | vlv_program_pfi_credits(dev_priv); |
Imre Deak | 738c05c | 2014-11-19 16:25:37 +0200 | [diff] [blame] | 6683 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6684 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6685 | } |
| 6686 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6687 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
| 6688 | struct drm_atomic_state *old_state) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6689 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6690 | struct drm_crtc *crtc = pipe_config->base.crtc; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6691 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6692 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6694 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6695 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 6696 | if (WARN_ON(intel_crtc->active)) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6697 | return; |
| 6698 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 6699 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 6700 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6701 | |
| 6702 | intel_set_pipe_timings(intel_crtc); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 6703 | intel_set_pipe_src_size(intel_crtc); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6704 | |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 6705 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6706 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 6707 | |
| 6708 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
| 6709 | I915_WRITE(CHV_CANVAS(pipe), 0); |
| 6710 | } |
| 6711 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6712 | i9xx_set_pipeconf(intel_crtc); |
| 6713 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6714 | intel_crtc->active = true; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6715 | |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6716 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6717 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6718 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6719 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 6720 | if (IS_CHERRYVIEW(dev)) { |
| 6721 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
| 6722 | chv_enable_pll(intel_crtc, intel_crtc->config); |
| 6723 | } else { |
| 6724 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
| 6725 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 6726 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6727 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6728 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6729 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 6730 | i9xx_pfit_enable(intel_crtc); |
| 6731 | |
Maarten Lankhorst | b95c532 | 2016-03-30 17:16:34 +0200 | [diff] [blame] | 6732 | intel_color_load_luts(&pipe_config->base); |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 6733 | |
Ville Syrjälä | caed361 | 2016-03-09 19:07:25 +0200 | [diff] [blame] | 6734 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 6735 | intel_enable_pipe(intel_crtc); |
Daniel Vetter | be6a6f8 | 2014-04-15 18:41:22 +0200 | [diff] [blame] | 6736 | |
Ville Syrjälä | 4b3a952 | 2014-08-14 22:04:37 +0300 | [diff] [blame] | 6737 | assert_vblank_disabled(crtc); |
| 6738 | drm_crtc_vblank_on(crtc); |
| 6739 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6740 | intel_encoders_enable(crtc, pipe_config, old_state); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6741 | } |
| 6742 | |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6743 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
| 6744 | { |
| 6745 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6746 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6747 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6748 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
| 6749 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6750 | } |
| 6751 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6752 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
| 6753 | struct drm_atomic_state *old_state) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6754 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6755 | struct drm_crtc *crtc = pipe_config->base.crtc; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6756 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6757 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 6759 | enum pipe pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6760 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 6761 | if (WARN_ON(intel_crtc->active)) |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 6762 | return; |
| 6763 | |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6764 | i9xx_set_pll_dividers(intel_crtc); |
| 6765 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 6766 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 6767 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6768 | |
| 6769 | intel_set_pipe_timings(intel_crtc); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 6770 | intel_set_pipe_src_size(intel_crtc); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6771 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6772 | i9xx_set_pipeconf(intel_crtc); |
| 6773 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 6774 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 6775 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6776 | if (!IS_GEN2(dev)) |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6777 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6778 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6779 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
Mika Kuoppala | 9d6d9f1 | 2013-02-08 16:35:38 +0200 | [diff] [blame] | 6780 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 6781 | i9xx_enable_pll(intel_crtc); |
| 6782 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 6783 | i9xx_pfit_enable(intel_crtc); |
| 6784 | |
Maarten Lankhorst | b95c532 | 2016-03-30 17:16:34 +0200 | [diff] [blame] | 6785 | intel_color_load_luts(&pipe_config->base); |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 6786 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 6787 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 6788 | intel_enable_pipe(intel_crtc); |
Daniel Vetter | be6a6f8 | 2014-04-15 18:41:22 +0200 | [diff] [blame] | 6789 | |
Ville Syrjälä | 4b3a952 | 2014-08-14 22:04:37 +0300 | [diff] [blame] | 6790 | assert_vblank_disabled(crtc); |
| 6791 | drm_crtc_vblank_on(crtc); |
| 6792 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6793 | intel_encoders_enable(crtc, pipe_config, old_state); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6794 | } |
| 6795 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6796 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
| 6797 | { |
| 6798 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6799 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 6800 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6801 | if (!crtc->config->gmch_pfit.control) |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 6802 | return; |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6803 | |
| 6804 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 6805 | |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 6806 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
| 6807 | I915_READ(PFIT_CONTROL)); |
| 6808 | I915_WRITE(PFIT_CONTROL, 0); |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6809 | } |
| 6810 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6811 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
| 6812 | struct drm_atomic_state *old_state) |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6813 | { |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6814 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6815 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 6816 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6818 | int pipe = intel_crtc->pipe; |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 6819 | |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 6820 | /* |
| 6821 | * On gen2 planes are double buffered but the pipe isn't, so we must |
| 6822 | * wait for planes to fully turn off before disabling the pipe. |
| 6823 | */ |
Ander Conselvan de Oliveira | 90e83e5 | 2016-03-22 10:11:24 +0200 | [diff] [blame] | 6824 | if (IS_GEN2(dev)) |
| 6825 | intel_wait_for_vblank(dev, pipe); |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 6826 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6827 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
Ville Syrjälä | 4b3a952 | 2014-08-14 22:04:37 +0300 | [diff] [blame] | 6828 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 6829 | drm_crtc_vblank_off(crtc); |
| 6830 | assert_vblank_disabled(crtc); |
| 6831 | |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 6832 | intel_disable_pipe(intel_crtc); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 6833 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6834 | i9xx_pfit_disable(intel_crtc); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 6835 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6836 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6837 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 6838 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 6839 | if (IS_CHERRYVIEW(dev)) |
| 6840 | chv_disable_pll(dev_priv, pipe); |
| 6841 | else if (IS_VALLEYVIEW(dev)) |
| 6842 | vlv_disable_pll(dev_priv, pipe); |
| 6843 | else |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 6844 | i9xx_disable_pll(intel_crtc); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 6845 | } |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6846 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 6847 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 6848 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6849 | if (!IS_GEN2(dev)) |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6850 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6851 | } |
| 6852 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6853 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6854 | { |
Maarten Lankhorst | 842e030 | 2016-03-02 15:48:01 +0100 | [diff] [blame] | 6855 | struct intel_encoder *encoder; |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6857 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6858 | enum intel_display_power_domain domain; |
| 6859 | unsigned long domains; |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6860 | struct drm_atomic_state *state; |
| 6861 | struct intel_crtc_state *crtc_state; |
| 6862 | int ret; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 6863 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6864 | if (!intel_crtc->active) |
| 6865 | return; |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6866 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 6867 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 6868 | WARN_ON(intel_crtc->flip_work); |
Maarten Lankhorst | fc32b1f | 2015-10-19 17:09:23 +0200 | [diff] [blame] | 6869 | |
Ville Syrjälä | 2622a08 | 2016-03-09 19:07:26 +0200 | [diff] [blame] | 6870 | intel_pre_disable_primary_noatomic(crtc); |
Maarten Lankhorst | 54a41961 | 2015-11-23 10:25:28 +0100 | [diff] [blame] | 6871 | |
| 6872 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 6873 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 6874 | } |
| 6875 | |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 6876 | state = drm_atomic_state_alloc(crtc->dev); |
| 6877 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
| 6878 | |
| 6879 | /* Everything's already locked, -EDEADLK can't happen. */ |
| 6880 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 6881 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 6882 | |
| 6883 | WARN_ON(IS_ERR(crtc_state) || ret); |
| 6884 | |
| 6885 | dev_priv->display.crtc_disable(crtc_state, state); |
| 6886 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 6887 | drm_atomic_state_put(state); |
Maarten Lankhorst | 842e030 | 2016-03-02 15:48:01 +0100 | [diff] [blame] | 6888 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 6889 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
| 6890 | crtc->base.id, crtc->name); |
Maarten Lankhorst | 842e030 | 2016-03-02 15:48:01 +0100 | [diff] [blame] | 6891 | |
| 6892 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); |
| 6893 | crtc->state->active = false; |
Matt Roper | 37d9078 | 2015-09-24 15:53:06 -0700 | [diff] [blame] | 6894 | intel_crtc->active = false; |
Maarten Lankhorst | 842e030 | 2016-03-02 15:48:01 +0100 | [diff] [blame] | 6895 | crtc->enabled = false; |
| 6896 | crtc->state->connector_mask = 0; |
| 6897 | crtc->state->encoder_mask = 0; |
| 6898 | |
| 6899 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) |
| 6900 | encoder->base.crtc = NULL; |
| 6901 | |
Paulo Zanoni | 58f9c0b | 2016-01-19 11:35:51 -0200 | [diff] [blame] | 6902 | intel_fbc_disable(intel_crtc); |
Matt Roper | 37d9078 | 2015-09-24 15:53:06 -0700 | [diff] [blame] | 6903 | intel_update_watermarks(crtc); |
Maarten Lankhorst | 1f7457b | 2015-07-13 11:55:05 +0200 | [diff] [blame] | 6904 | intel_disable_shared_dpll(intel_crtc); |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6905 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6906 | domains = intel_crtc->enabled_power_domains; |
| 6907 | for_each_power_domain(domain, domains) |
| 6908 | intel_display_power_put(dev_priv, domain); |
| 6909 | intel_crtc->enabled_power_domains = 0; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6910 | |
| 6911 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); |
| 6912 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6913 | } |
| 6914 | |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6915 | /* |
| 6916 | * turn all crtc's off, but do not adjust state |
| 6917 | * This has to be paired with a call to intel_modeset_setup_hw_state. |
| 6918 | */ |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6919 | int intel_display_suspend(struct drm_device *dev) |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6920 | { |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 6921 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6922 | struct drm_atomic_state *state; |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 6923 | int ret; |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6924 | |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 6925 | state = drm_atomic_helper_suspend(dev); |
| 6926 | ret = PTR_ERR_OR_ZERO(state); |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6927 | if (ret) |
| 6928 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 6929 | else |
| 6930 | dev_priv->modeset_restore_state = state; |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6931 | return ret; |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6932 | } |
| 6933 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 6934 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 6935 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6936 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 6937 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 6938 | drm_encoder_cleanup(encoder); |
| 6939 | kfree(intel_encoder); |
| 6940 | } |
| 6941 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6942 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
| 6943 | * internal consistency). */ |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 6944 | static void intel_connector_verify_state(struct intel_connector *connector) |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6945 | { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 6946 | struct drm_crtc *crtc = connector->base.state->crtc; |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6947 | |
| 6948 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 6949 | connector->base.base.id, |
| 6950 | connector->base.name); |
| 6951 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6952 | if (connector->get_hw_state(connector)) { |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6953 | struct intel_encoder *encoder = connector->encoder; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 6954 | struct drm_connector_state *conn_state = connector->base.state; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6955 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6956 | I915_STATE_WARN(!crtc, |
| 6957 | "connector enabled without attached crtc\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6958 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6959 | if (!crtc) |
| 6960 | return; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6961 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6962 | I915_STATE_WARN(!crtc->state->active, |
| 6963 | "connector is active, but attached crtc isn't\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6964 | |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6965 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6966 | return; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6967 | |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6968 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6969 | "atomic encoder doesn't match attached encoder\n"); |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 6970 | |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6971 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6972 | "attached encoder crtc differs from connector crtc\n"); |
| 6973 | } else { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 6974 | I915_STATE_WARN(crtc && crtc->state->active, |
| 6975 | "attached crtc is active, but connector isn't\n"); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 6976 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6977 | "best encoder set without crtc!\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6978 | } |
| 6979 | } |
| 6980 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 6981 | int intel_connector_init(struct intel_connector *connector) |
| 6982 | { |
Maarten Lankhorst | 5350a03 | 2016-01-04 12:53:15 +0100 | [diff] [blame] | 6983 | drm_atomic_helper_connector_reset(&connector->base); |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 6984 | |
Maarten Lankhorst | 5350a03 | 2016-01-04 12:53:15 +0100 | [diff] [blame] | 6985 | if (!connector->base.state) |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 6986 | return -ENOMEM; |
| 6987 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 6988 | return 0; |
| 6989 | } |
| 6990 | |
| 6991 | struct intel_connector *intel_connector_alloc(void) |
| 6992 | { |
| 6993 | struct intel_connector *connector; |
| 6994 | |
| 6995 | connector = kzalloc(sizeof *connector, GFP_KERNEL); |
| 6996 | if (!connector) |
| 6997 | return NULL; |
| 6998 | |
| 6999 | if (intel_connector_init(connector) < 0) { |
| 7000 | kfree(connector); |
| 7001 | return NULL; |
| 7002 | } |
| 7003 | |
| 7004 | return connector; |
| 7005 | } |
| 7006 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 7007 | /* Simple connector->get_hw_state implementation for encoders that support only |
| 7008 | * one connector and no cloning and hence the encoder state determines the state |
| 7009 | * of the connector. */ |
| 7010 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
| 7011 | { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 7012 | enum pipe pipe = 0; |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 7013 | struct intel_encoder *encoder = connector->encoder; |
| 7014 | |
| 7015 | return encoder->get_hw_state(encoder, &pipe); |
| 7016 | } |
| 7017 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7018 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
Ville Syrjälä | d272ddf | 2015-03-11 18:52:31 +0200 | [diff] [blame] | 7019 | { |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7020 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
| 7021 | return crtc_state->fdi_lanes; |
Ville Syrjälä | d272ddf | 2015-03-11 18:52:31 +0200 | [diff] [blame] | 7022 | |
| 7023 | return 0; |
| 7024 | } |
| 7025 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7026 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7027 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7028 | { |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7029 | struct drm_atomic_state *state = pipe_config->base.state; |
| 7030 | struct intel_crtc *other_crtc; |
| 7031 | struct intel_crtc_state *other_crtc_state; |
| 7032 | |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7033 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
| 7034 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 7035 | if (pipe_config->fdi_lanes > 4) { |
| 7036 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
| 7037 | pipe_name(pipe), pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7038 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7039 | } |
| 7040 | |
Paulo Zanoni | bafb655 | 2013-11-02 21:07:44 -0700 | [diff] [blame] | 7041 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7042 | if (pipe_config->fdi_lanes > 2) { |
| 7043 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
| 7044 | pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7045 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7046 | } else { |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7047 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7048 | } |
| 7049 | } |
| 7050 | |
| 7051 | if (INTEL_INFO(dev)->num_pipes == 2) |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7052 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7053 | |
| 7054 | /* Ivybridge 3 pipe is really complicated */ |
| 7055 | switch (pipe) { |
| 7056 | case PIPE_A: |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7057 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7058 | case PIPE_B: |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7059 | if (pipe_config->fdi_lanes <= 2) |
| 7060 | return 0; |
| 7061 | |
| 7062 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); |
| 7063 | other_crtc_state = |
| 7064 | intel_atomic_get_crtc_state(state, other_crtc); |
| 7065 | if (IS_ERR(other_crtc_state)) |
| 7066 | return PTR_ERR(other_crtc_state); |
| 7067 | |
| 7068 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7069 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 7070 | pipe_name(pipe), pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7071 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7072 | } |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7073 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7074 | case PIPE_C: |
Ville Syrjälä | 251cc67 | 2015-03-11 18:52:30 +0200 | [diff] [blame] | 7075 | if (pipe_config->fdi_lanes > 2) { |
| 7076 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", |
| 7077 | pipe_name(pipe), pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7078 | return -EINVAL; |
Ville Syrjälä | 251cc67 | 2015-03-11 18:52:30 +0200 | [diff] [blame] | 7079 | } |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7080 | |
| 7081 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); |
| 7082 | other_crtc_state = |
| 7083 | intel_atomic_get_crtc_state(state, other_crtc); |
| 7084 | if (IS_ERR(other_crtc_state)) |
| 7085 | return PTR_ERR(other_crtc_state); |
| 7086 | |
| 7087 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7088 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7089 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7090 | } |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7091 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7092 | default: |
| 7093 | BUG(); |
| 7094 | } |
| 7095 | } |
| 7096 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 7097 | #define RETRY 1 |
| 7098 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7099 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7100 | { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7101 | struct drm_device *dev = intel_crtc->base.dev; |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 7102 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7103 | int lane, link_bw, fdi_dotclock, ret; |
| 7104 | bool needs_recompute = false; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7105 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 7106 | retry: |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7107 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 7108 | * each output octet as 10 bits. The actual frequency |
| 7109 | * is stored as a divider into a 100MHz clock, and the |
| 7110 | * mode pixel clock is stored in units of 1KHz. |
| 7111 | * Hence the bw of each lane in terms of the mode signal |
| 7112 | * is: |
| 7113 | */ |
Ville Syrjälä | 21a727b | 2016-02-17 21:41:10 +0200 | [diff] [blame] | 7114 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7115 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 7116 | fdi_dotclock = adjusted_mode->crtc_clock; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7117 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 7118 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7119 | pipe_config->pipe_bpp); |
| 7120 | |
| 7121 | pipe_config->fdi_lanes = lane; |
| 7122 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 7123 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7124 | link_bw, &pipe_config->fdi_m_n); |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 7125 | |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 7126 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7127 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 7128 | pipe_config->pipe_bpp -= 2*3; |
| 7129 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
| 7130 | pipe_config->pipe_bpp); |
| 7131 | needs_recompute = true; |
| 7132 | pipe_config->bw_constrained = true; |
| 7133 | |
| 7134 | goto retry; |
| 7135 | } |
| 7136 | |
| 7137 | if (needs_recompute) |
| 7138 | return RETRY; |
| 7139 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 7140 | return ret; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7141 | } |
| 7142 | |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 7143 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
| 7144 | struct intel_crtc_state *pipe_config) |
| 7145 | { |
| 7146 | if (pipe_config->pipe_bpp > 24) |
| 7147 | return false; |
| 7148 | |
| 7149 | /* HSW can handle pixel rate up to cdclk? */ |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 7150 | if (IS_HASWELL(dev_priv)) |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 7151 | return true; |
| 7152 | |
| 7153 | /* |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 7154 | * We compare against max which means we must take |
| 7155 | * the increased cdclk requirement into account when |
| 7156 | * calculating the new cdclk. |
| 7157 | * |
| 7158 | * Should measure whether using a lower cdclk w/o IPS |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 7159 | */ |
| 7160 | return ilk_pipe_pixel_rate(pipe_config) <= |
| 7161 | dev_priv->max_cdclk_freq * 95 / 100; |
| 7162 | } |
| 7163 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 7164 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7165 | struct intel_crtc_state *pipe_config) |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 7166 | { |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 7167 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7168 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 7169 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 7170 | pipe_config->ips_enabled = i915.enable_ips && |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 7171 | hsw_crtc_supports_ips(crtc) && |
| 7172 | pipe_config_supports_ips(dev_priv, pipe_config); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 7173 | } |
| 7174 | |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 7175 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
| 7176 | { |
| 7177 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 7178 | |
| 7179 | /* GDG double wide on either pipe, otherwise pipe A only */ |
| 7180 | return INTEL_INFO(dev_priv)->gen < 4 && |
| 7181 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); |
| 7182 | } |
| 7183 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 7184 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7185 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7186 | { |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 7187 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7188 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 7189 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Ville Syrjälä | f326115 | 2016-05-24 21:34:18 +0300 | [diff] [blame] | 7190 | int clock_limit = dev_priv->max_dotclk_freq; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 7191 | |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 7192 | if (INTEL_INFO(dev)->gen < 4) { |
Ville Syrjälä | f326115 | 2016-05-24 21:34:18 +0300 | [diff] [blame] | 7193 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 7194 | |
| 7195 | /* |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 7196 | * Enable double wide mode when the dot clock |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 7197 | * is > 90% of the (display) core speed. |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 7198 | */ |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 7199 | if (intel_crtc_supports_double_wide(crtc) && |
| 7200 | adjusted_mode->crtc_clock > clock_limit) { |
Ville Syrjälä | f326115 | 2016-05-24 21:34:18 +0300 | [diff] [blame] | 7201 | clock_limit = dev_priv->max_dotclk_freq; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 7202 | pipe_config->double_wide = true; |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 7203 | } |
Ville Syrjälä | f326115 | 2016-05-24 21:34:18 +0300 | [diff] [blame] | 7204 | } |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 7205 | |
Ville Syrjälä | f326115 | 2016-05-24 21:34:18 +0300 | [diff] [blame] | 7206 | if (adjusted_mode->crtc_clock > clock_limit) { |
| 7207 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", |
| 7208 | adjusted_mode->crtc_clock, clock_limit, |
| 7209 | yesno(pipe_config->double_wide)); |
| 7210 | return -EINVAL; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7211 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 7212 | |
Ville Syrjälä | 1d1d0e2 | 2013-09-04 18:30:05 +0300 | [diff] [blame] | 7213 | /* |
| 7214 | * Pipe horizontal size must be even in: |
| 7215 | * - DVO ganged mode |
| 7216 | * - LVDS dual channel mode |
| 7217 | * - Double wide pipe |
| 7218 | */ |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 7219 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
Ville Syrjälä | 1d1d0e2 | 2013-09-04 18:30:05 +0300 | [diff] [blame] | 7220 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
| 7221 | pipe_config->pipe_src_w &= ~1; |
| 7222 | |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 7223 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
| 7224 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 7225 | */ |
| 7226 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 7227 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 7228 | return -EINVAL; |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 7229 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 7230 | if (HAS_IPS(dev)) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 7231 | hsw_compute_ips_config(crtc, pipe_config); |
| 7232 | |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7233 | if (pipe_config->has_pch_encoder) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 7234 | return ironlake_fdi_compute_config(crtc, pipe_config); |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 7235 | |
Maarten Lankhorst | cf5a15b | 2015-06-15 12:33:41 +0200 | [diff] [blame] | 7236 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7237 | } |
| 7238 | |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7239 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
| 7240 | { |
| 7241 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7242 | uint32_t cdctl; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7243 | |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7244 | skl_dpll0_update(dev_priv); |
| 7245 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 7246 | if (dev_priv->cdclk_pll.vco == 0) |
Ville Syrjälä | 709e05c | 2016-05-13 23:41:33 +0300 | [diff] [blame] | 7247 | return dev_priv->cdclk_pll.ref; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7248 | |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7249 | cdctl = I915_READ(CDCLK_CTL); |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7250 | |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 7251 | if (dev_priv->cdclk_pll.vco == 8640000) { |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7252 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 7253 | case CDCLK_FREQ_450_432: |
| 7254 | return 432000; |
| 7255 | case CDCLK_FREQ_337_308: |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 7256 | return 308571; |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7257 | case CDCLK_FREQ_540: |
| 7258 | return 540000; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7259 | case CDCLK_FREQ_675_617: |
Ville Syrjälä | 487ed2e | 2016-05-13 23:41:31 +0300 | [diff] [blame] | 7260 | return 617143; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7261 | default: |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7262 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7263 | } |
| 7264 | } else { |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7265 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 7266 | case CDCLK_FREQ_450_432: |
| 7267 | return 450000; |
| 7268 | case CDCLK_FREQ_337_308: |
| 7269 | return 337500; |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7270 | case CDCLK_FREQ_540: |
| 7271 | return 540000; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7272 | case CDCLK_FREQ_675_617: |
| 7273 | return 675000; |
| 7274 | default: |
Ville Syrjälä | ea61791 | 2016-05-13 23:41:24 +0300 | [diff] [blame] | 7275 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7276 | } |
| 7277 | } |
| 7278 | |
Ville Syrjälä | 709e05c | 2016-05-13 23:41:33 +0300 | [diff] [blame] | 7279 | return dev_priv->cdclk_pll.ref; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7280 | } |
| 7281 | |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 7282 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
| 7283 | { |
| 7284 | u32 val; |
| 7285 | |
| 7286 | dev_priv->cdclk_pll.ref = 19200; |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 7287 | dev_priv->cdclk_pll.vco = 0; |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 7288 | |
| 7289 | val = I915_READ(BXT_DE_PLL_ENABLE); |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 7290 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 7291 | return; |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 7292 | |
Imre Deak | 1c3f770 | 2016-05-24 15:38:32 +0300 | [diff] [blame] | 7293 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
| 7294 | return; |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 7295 | |
| 7296 | val = I915_READ(BXT_DE_PLL_CTL); |
| 7297 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * |
| 7298 | dev_priv->cdclk_pll.ref; |
| 7299 | } |
| 7300 | |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7301 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
| 7302 | { |
| 7303 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7304 | u32 divider; |
| 7305 | int div, vco; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7306 | |
Ville Syrjälä | 83d7c81 | 2016-05-13 23:41:35 +0300 | [diff] [blame] | 7307 | bxt_de_pll_update(dev_priv); |
| 7308 | |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7309 | vco = dev_priv->cdclk_pll.vco; |
| 7310 | if (vco == 0) |
| 7311 | return dev_priv->cdclk_pll.ref; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7312 | |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7313 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7314 | |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7315 | switch (divider) { |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7316 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7317 | div = 2; |
| 7318 | break; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7319 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7320 | div = 3; |
| 7321 | break; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7322 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7323 | div = 4; |
| 7324 | break; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7325 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7326 | div = 8; |
| 7327 | break; |
| 7328 | default: |
| 7329 | MISSING_CASE(divider); |
| 7330 | return dev_priv->cdclk_pll.ref; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7331 | } |
| 7332 | |
Ville Syrjälä | f598624 | 2016-05-13 23:41:37 +0300 | [diff] [blame] | 7333 | return DIV_ROUND_CLOSEST(vco, div); |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 7334 | } |
| 7335 | |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7336 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
| 7337 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7338 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7339 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 7340 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 7341 | |
| 7342 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 7343 | return 800000; |
| 7344 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 7345 | return 450000; |
| 7346 | else if (freq == LCPLL_CLK_FREQ_450) |
| 7347 | return 450000; |
| 7348 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
| 7349 | return 540000; |
| 7350 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
| 7351 | return 337500; |
| 7352 | else |
| 7353 | return 675000; |
| 7354 | } |
| 7355 | |
| 7356 | static int haswell_get_display_clock_speed(struct drm_device *dev) |
| 7357 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7358 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 7359 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 7360 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 7361 | |
| 7362 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 7363 | return 800000; |
| 7364 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 7365 | return 450000; |
| 7366 | else if (freq == LCPLL_CLK_FREQ_450) |
| 7367 | return 450000; |
| 7368 | else if (IS_HSW_ULT(dev)) |
| 7369 | return 337500; |
| 7370 | else |
| 7371 | return 540000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7372 | } |
| 7373 | |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 7374 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
| 7375 | { |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 7376 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
| 7377 | CCK_DISPLAY_CLOCK_CONTROL); |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 7378 | } |
| 7379 | |
Ville Syrjälä | b37a643 | 2015-03-31 14:11:54 +0300 | [diff] [blame] | 7380 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
| 7381 | { |
| 7382 | return 450000; |
| 7383 | } |
| 7384 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7385 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7386 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7387 | return 400000; |
| 7388 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7389 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7390 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 7391 | { |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7392 | return 333333; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7393 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7394 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7395 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 7396 | { |
| 7397 | return 200000; |
| 7398 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7399 | |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7400 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
| 7401 | { |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7402 | struct pci_dev *pdev = dev->pdev; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7403 | u16 gcfgc = 0; |
| 7404 | |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7405 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7406 | |
| 7407 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 7408 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7409 | return 266667; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7410 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7411 | return 333333; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7412 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7413 | return 444444; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7414 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
| 7415 | return 200000; |
| 7416 | default: |
| 7417 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
| 7418 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7419 | return 133333; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7420 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7421 | return 166667; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 7422 | } |
| 7423 | } |
| 7424 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7425 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 7426 | { |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7427 | struct pci_dev *pdev = dev->pdev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7428 | u16 gcfgc = 0; |
| 7429 | |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7430 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7431 | |
| 7432 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7433 | return 133333; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7434 | else { |
| 7435 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 7436 | case GC_DISPLAY_CLOCK_333_MHZ: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7437 | return 333333; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7438 | default: |
| 7439 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 7440 | return 190000; |
| 7441 | } |
| 7442 | } |
| 7443 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7444 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7445 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 7446 | { |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7447 | return 266667; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7448 | } |
| 7449 | |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 7450 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7451 | { |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7452 | struct pci_dev *pdev = dev->pdev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7453 | u16 hpllcc = 0; |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 7454 | |
Ville Syrjälä | 65cd2b3 | 2015-05-22 11:22:32 +0300 | [diff] [blame] | 7455 | /* |
| 7456 | * 852GM/852GMV only supports 133 MHz and the HPLLCC |
| 7457 | * encoding is different :( |
| 7458 | * FIXME is this the right way to detect 852GM/852GMV? |
| 7459 | */ |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7460 | if (pdev->revision == 0x1) |
Ville Syrjälä | 65cd2b3 | 2015-05-22 11:22:32 +0300 | [diff] [blame] | 7461 | return 133333; |
| 7462 | |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7463 | pci_bus_read_config_word(pdev->bus, |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 7464 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
| 7465 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7466 | /* Assume that the hardware is in the high speed state. This |
| 7467 | * should be the default. |
| 7468 | */ |
| 7469 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 7470 | case GC_CLOCK_133_200: |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 7471 | case GC_CLOCK_133_200_2: |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7472 | case GC_CLOCK_100_200: |
| 7473 | return 200000; |
| 7474 | case GC_CLOCK_166_250: |
| 7475 | return 250000; |
| 7476 | case GC_CLOCK_100_133: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7477 | return 133333; |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 7478 | case GC_CLOCK_133_266: |
| 7479 | case GC_CLOCK_133_266_2: |
| 7480 | case GC_CLOCK_166_266: |
| 7481 | return 266667; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7482 | } |
| 7483 | |
| 7484 | /* Shouldn't happen */ |
| 7485 | return 0; |
| 7486 | } |
| 7487 | |
| 7488 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 7489 | { |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7490 | return 133333; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7491 | } |
| 7492 | |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7493 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
| 7494 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7495 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7496 | static const unsigned int blb_vco[8] = { |
| 7497 | [0] = 3200000, |
| 7498 | [1] = 4000000, |
| 7499 | [2] = 5333333, |
| 7500 | [3] = 4800000, |
| 7501 | [4] = 6400000, |
| 7502 | }; |
| 7503 | static const unsigned int pnv_vco[8] = { |
| 7504 | [0] = 3200000, |
| 7505 | [1] = 4000000, |
| 7506 | [2] = 5333333, |
| 7507 | [3] = 4800000, |
| 7508 | [4] = 2666667, |
| 7509 | }; |
| 7510 | static const unsigned int cl_vco[8] = { |
| 7511 | [0] = 3200000, |
| 7512 | [1] = 4000000, |
| 7513 | [2] = 5333333, |
| 7514 | [3] = 6400000, |
| 7515 | [4] = 3333333, |
| 7516 | [5] = 3566667, |
| 7517 | [6] = 4266667, |
| 7518 | }; |
| 7519 | static const unsigned int elk_vco[8] = { |
| 7520 | [0] = 3200000, |
| 7521 | [1] = 4000000, |
| 7522 | [2] = 5333333, |
| 7523 | [3] = 4800000, |
| 7524 | }; |
| 7525 | static const unsigned int ctg_vco[8] = { |
| 7526 | [0] = 3200000, |
| 7527 | [1] = 4000000, |
| 7528 | [2] = 5333333, |
| 7529 | [3] = 6400000, |
| 7530 | [4] = 2666667, |
| 7531 | [5] = 4266667, |
| 7532 | }; |
| 7533 | const unsigned int *vco_table; |
| 7534 | unsigned int vco; |
| 7535 | uint8_t tmp = 0; |
| 7536 | |
| 7537 | /* FIXME other chipsets? */ |
| 7538 | if (IS_GM45(dev)) |
| 7539 | vco_table = ctg_vco; |
| 7540 | else if (IS_G4X(dev)) |
| 7541 | vco_table = elk_vco; |
| 7542 | else if (IS_CRESTLINE(dev)) |
| 7543 | vco_table = cl_vco; |
| 7544 | else if (IS_PINEVIEW(dev)) |
| 7545 | vco_table = pnv_vco; |
| 7546 | else if (IS_G33(dev)) |
| 7547 | vco_table = blb_vco; |
| 7548 | else |
| 7549 | return 0; |
| 7550 | |
| 7551 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); |
| 7552 | |
| 7553 | vco = vco_table[tmp & 0x7]; |
| 7554 | if (vco == 0) |
| 7555 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); |
| 7556 | else |
| 7557 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); |
| 7558 | |
| 7559 | return vco; |
| 7560 | } |
| 7561 | |
| 7562 | static int gm45_get_display_clock_speed(struct drm_device *dev) |
| 7563 | { |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7564 | struct pci_dev *pdev = dev->pdev; |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7565 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7566 | uint16_t tmp = 0; |
| 7567 | |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7568 | pci_read_config_word(pdev, GCFGC, &tmp); |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7569 | |
| 7570 | cdclk_sel = (tmp >> 12) & 0x1; |
| 7571 | |
| 7572 | switch (vco) { |
| 7573 | case 2666667: |
| 7574 | case 4000000: |
| 7575 | case 5333333: |
| 7576 | return cdclk_sel ? 333333 : 222222; |
| 7577 | case 3200000: |
| 7578 | return cdclk_sel ? 320000 : 228571; |
| 7579 | default: |
| 7580 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); |
| 7581 | return 222222; |
| 7582 | } |
| 7583 | } |
| 7584 | |
| 7585 | static int i965gm_get_display_clock_speed(struct drm_device *dev) |
| 7586 | { |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7587 | struct pci_dev *pdev = dev->pdev; |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7588 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
| 7589 | static const uint8_t div_4000[] = { 20, 12, 10 }; |
| 7590 | static const uint8_t div_5333[] = { 24, 16, 14 }; |
| 7591 | const uint8_t *div_table; |
| 7592 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7593 | uint16_t tmp = 0; |
| 7594 | |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7595 | pci_read_config_word(pdev, GCFGC, &tmp); |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7596 | |
| 7597 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; |
| 7598 | |
| 7599 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 7600 | goto fail; |
| 7601 | |
| 7602 | switch (vco) { |
| 7603 | case 3200000: |
| 7604 | div_table = div_3200; |
| 7605 | break; |
| 7606 | case 4000000: |
| 7607 | div_table = div_4000; |
| 7608 | break; |
| 7609 | case 5333333: |
| 7610 | div_table = div_5333; |
| 7611 | break; |
| 7612 | default: |
| 7613 | goto fail; |
| 7614 | } |
| 7615 | |
| 7616 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 7617 | |
Damien Lespiau | caf4e25 | 2015-06-04 16:56:18 +0100 | [diff] [blame] | 7618 | fail: |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7619 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
| 7620 | return 200000; |
| 7621 | } |
| 7622 | |
| 7623 | static int g33_get_display_clock_speed(struct drm_device *dev) |
| 7624 | { |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7625 | struct pci_dev *pdev = dev->pdev; |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7626 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
| 7627 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; |
| 7628 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; |
| 7629 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; |
| 7630 | const uint8_t *div_table; |
| 7631 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7632 | uint16_t tmp = 0; |
| 7633 | |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 7634 | pci_read_config_word(pdev, GCFGC, &tmp); |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7635 | |
| 7636 | cdclk_sel = (tmp >> 4) & 0x7; |
| 7637 | |
| 7638 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 7639 | goto fail; |
| 7640 | |
| 7641 | switch (vco) { |
| 7642 | case 3200000: |
| 7643 | div_table = div_3200; |
| 7644 | break; |
| 7645 | case 4000000: |
| 7646 | div_table = div_4000; |
| 7647 | break; |
| 7648 | case 4800000: |
| 7649 | div_table = div_4800; |
| 7650 | break; |
| 7651 | case 5333333: |
| 7652 | div_table = div_5333; |
| 7653 | break; |
| 7654 | default: |
| 7655 | goto fail; |
| 7656 | } |
| 7657 | |
| 7658 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 7659 | |
Damien Lespiau | caf4e25 | 2015-06-04 16:56:18 +0100 | [diff] [blame] | 7660 | fail: |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7661 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
| 7662 | return 190476; |
| 7663 | } |
| 7664 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7665 | static void |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7666 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7667 | { |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7668 | while (*num > DATA_LINK_M_N_MASK || |
| 7669 | *den > DATA_LINK_M_N_MASK) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7670 | *num >>= 1; |
| 7671 | *den >>= 1; |
| 7672 | } |
| 7673 | } |
| 7674 | |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7675 | static void compute_m_n(unsigned int m, unsigned int n, |
| 7676 | uint32_t *ret_m, uint32_t *ret_n) |
| 7677 | { |
| 7678 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
| 7679 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
| 7680 | intel_reduce_m_n_ratio(ret_m, ret_n); |
| 7681 | } |
| 7682 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 7683 | void |
| 7684 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
| 7685 | int pixel_clock, int link_clock, |
| 7686 | struct intel_link_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7687 | { |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 7688 | m_n->tu = 64; |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7689 | |
| 7690 | compute_m_n(bits_per_pixel * pixel_clock, |
| 7691 | link_clock * nlanes * 8, |
| 7692 | &m_n->gmch_m, &m_n->gmch_n); |
| 7693 | |
| 7694 | compute_m_n(pixel_clock, link_clock, |
| 7695 | &m_n->link_m, &m_n->link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7696 | } |
| 7697 | |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 7698 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 7699 | { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 7700 | if (i915.panel_use_ssc >= 0) |
| 7701 | return i915.panel_use_ssc != 0; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 7702 | return dev_priv->vbt.lvds_use_ssc |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 7703 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 7704 | } |
| 7705 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7706 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7707 | { |
Daniel Vetter | 7df00d7 | 2013-05-21 21:54:55 +0200 | [diff] [blame] | 7708 | return (1 << dpll->n) << 16 | dpll->m2; |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7709 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7710 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7711 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
| 7712 | { |
| 7713 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7714 | } |
| 7715 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7716 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7717 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 7718 | struct dpll *reduced_clock) |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7719 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7720 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7721 | u32 fp, fp2 = 0; |
| 7722 | |
| 7723 | if (IS_PINEVIEW(dev)) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7724 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7725 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7726 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7727 | } else { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7728 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7729 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7730 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7731 | } |
| 7732 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7733 | crtc_state->dpll_hw_state.fp0 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7734 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7735 | crtc->lowfreq_avail = false; |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 7736 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Rodrigo Vivi | ab585de | 2015-03-24 12:40:09 -0700 | [diff] [blame] | 7737 | reduced_clock) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7738 | crtc_state->dpll_hw_state.fp1 = fp2; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7739 | crtc->lowfreq_avail = true; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7740 | } else { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7741 | crtc_state->dpll_hw_state.fp1 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7742 | } |
| 7743 | } |
| 7744 | |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 7745 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
| 7746 | pipe) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7747 | { |
| 7748 | u32 reg_val; |
| 7749 | |
| 7750 | /* |
| 7751 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
| 7752 | * and set it to a reasonable value instead. |
| 7753 | */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7754 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7755 | reg_val &= 0xffffff00; |
| 7756 | reg_val |= 0x00000030; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7757 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7758 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7759 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7760 | reg_val &= 0x8cffffff; |
| 7761 | reg_val = 0x8c000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7762 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7763 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7764 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7765 | reg_val &= 0xffffff00; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7766 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7767 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7768 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7769 | reg_val &= 0x00ffffff; |
| 7770 | reg_val |= 0xb0000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7771 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7772 | } |
| 7773 | |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7774 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
| 7775 | struct intel_link_m_n *m_n) |
| 7776 | { |
| 7777 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7778 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7779 | int pipe = crtc->pipe; |
| 7780 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 7781 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7782 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
| 7783 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
| 7784 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7785 | } |
| 7786 | |
| 7787 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 7788 | struct intel_link_m_n *m_n, |
| 7789 | struct intel_link_m_n *m2_n2) |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7790 | { |
| 7791 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7792 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7793 | int pipe = crtc->pipe; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7794 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7795 | |
| 7796 | if (INTEL_INFO(dev)->gen >= 5) { |
| 7797 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7798 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
| 7799 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
| 7800 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 7801 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
| 7802 | * for gen < 8) and if DRRS is supported (to make sure the |
| 7803 | * registers are not unnecessarily accessed). |
| 7804 | */ |
Durgadoss R | 44395bf | 2015-02-13 15:33:02 +0530 | [diff] [blame] | 7805 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7806 | crtc->config->has_drrs) { |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 7807 | I915_WRITE(PIPE_DATA_M2(transcoder), |
| 7808 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); |
| 7809 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); |
| 7810 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); |
| 7811 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); |
| 7812 | } |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7813 | } else { |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 7814 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7815 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
| 7816 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
| 7817 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7818 | } |
| 7819 | } |
| 7820 | |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 7821 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7822 | { |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 7823 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
| 7824 | |
| 7825 | if (m_n == M1_N1) { |
| 7826 | dp_m_n = &crtc->config->dp_m_n; |
| 7827 | dp_m2_n2 = &crtc->config->dp_m2_n2; |
| 7828 | } else if (m_n == M2_N2) { |
| 7829 | |
| 7830 | /* |
| 7831 | * M2_N2 registers are not supported. Hence m2_n2 divider value |
| 7832 | * needs to be programmed into M1_N1. |
| 7833 | */ |
| 7834 | dp_m_n = &crtc->config->dp_m2_n2; |
| 7835 | } else { |
| 7836 | DRM_ERROR("Unsupported divider value\n"); |
| 7837 | return; |
| 7838 | } |
| 7839 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7840 | if (crtc->config->has_pch_encoder) |
| 7841 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7842 | else |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 7843 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7844 | } |
| 7845 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7846 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
| 7847 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7848 | { |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 7849 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7850 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 7851 | if (crtc->pipe != PIPE_A) |
| 7852 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7853 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7854 | /* DPLL not used with DSI, but still need the rest set up */ |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 7855 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7856 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
| 7857 | DPLL_EXT_BUFFER_ENABLE_VLV; |
| 7858 | |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 7859 | pipe_config->dpll_hw_state.dpll_md = |
| 7860 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 7861 | } |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7862 | |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 7863 | static void chv_compute_dpll(struct intel_crtc *crtc, |
| 7864 | struct intel_crtc_state *pipe_config) |
| 7865 | { |
| 7866 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7867 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 7868 | if (crtc->pipe != PIPE_A) |
| 7869 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 7870 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7871 | /* DPLL not used with DSI, but still need the rest set up */ |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 7872 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7873 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
| 7874 | |
Ville Syrjälä | 03ed5cbf | 2016-03-15 16:39:55 +0200 | [diff] [blame] | 7875 | pipe_config->dpll_hw_state.dpll_md = |
| 7876 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7877 | } |
| 7878 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7879 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7880 | const struct intel_crtc_state *pipe_config) |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7881 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7882 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7883 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7884 | enum pipe pipe = crtc->pipe; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7885 | u32 mdiv; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7886 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7887 | u32 coreclk, reg_val; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7888 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7889 | /* Enable Refclk */ |
| 7890 | I915_WRITE(DPLL(pipe), |
| 7891 | pipe_config->dpll_hw_state.dpll & |
| 7892 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); |
| 7893 | |
| 7894 | /* No need to actually set up the DPLL with DSI */ |
| 7895 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) |
| 7896 | return; |
| 7897 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 7898 | mutex_lock(&dev_priv->sb_lock); |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 7899 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7900 | bestn = pipe_config->dpll.n; |
| 7901 | bestm1 = pipe_config->dpll.m1; |
| 7902 | bestm2 = pipe_config->dpll.m2; |
| 7903 | bestp1 = pipe_config->dpll.p1; |
| 7904 | bestp2 = pipe_config->dpll.p2; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7905 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7906 | /* See eDP HDMI DPIO driver vbios notes doc */ |
| 7907 | |
| 7908 | /* PLL B needs special handling */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7909 | if (pipe == PIPE_B) |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 7910 | vlv_pllb_recal_opamp(dev_priv, pipe); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7911 | |
| 7912 | /* Set up Tx target for periodic Rcomp update */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7913 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7914 | |
| 7915 | /* Disable target IRef on PLL */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7916 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7917 | reg_val &= 0x00ffffff; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7918 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7919 | |
| 7920 | /* Disable fast lock */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7921 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7922 | |
| 7923 | /* Set idtafcrecal before PLL is enabled */ |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7924 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
| 7925 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
| 7926 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7927 | mdiv |= (1 << DPIO_K_SHIFT); |
Jesse Barnes | 7df5080 | 2013-05-02 10:48:09 -0700 | [diff] [blame] | 7928 | |
| 7929 | /* |
| 7930 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| 7931 | * but we don't support that). |
| 7932 | * Note: don't use the DAC post divider as it seems unstable. |
| 7933 | */ |
| 7934 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7935 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7936 | |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7937 | mdiv |= DPIO_ENABLE_CALIBRATION; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7938 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7939 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7940 | /* Set HBR and RBR LPF coefficients */ |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7941 | if (pipe_config->port_clock == 162000 || |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 7942 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
| 7943 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7944 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Ville Syrjälä | 885b0120 | 2013-07-05 19:21:38 +0300 | [diff] [blame] | 7945 | 0x009f0003); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7946 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7947 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7948 | 0x00d0000f); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7949 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 7950 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7951 | /* Use SSC source */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7952 | if (pipe == PIPE_A) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7954 | 0x0df40000); |
| 7955 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7956 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7957 | 0x0df70000); |
| 7958 | } else { /* HDMI or VGA */ |
| 7959 | /* Use bend source */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7960 | if (pipe == PIPE_A) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7961 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7962 | 0x0df70000); |
| 7963 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7964 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7965 | 0x0df40000); |
| 7966 | } |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7967 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7968 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7969 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
Ville Syrjälä | 2210ce7 | 2016-06-22 21:57:05 +0300 | [diff] [blame] | 7970 | if (intel_crtc_has_dp_encoder(crtc->config)) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7971 | coreclk |= 0x01000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7972 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7973 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7974 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 7975 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7976 | } |
| 7977 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7978 | static void chv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7979 | const struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 7980 | { |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7981 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 7982 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7983 | enum pipe pipe = crtc->pipe; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7984 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7985 | u32 loopfilter, tribuf_calcntr; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7986 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
Vijay Purushothaman | a945ce7e | 2015-03-05 19:30:57 +0530 | [diff] [blame] | 7987 | u32 dpio_val; |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7988 | int vco; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7989 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 7990 | /* Enable Refclk and SSC */ |
| 7991 | I915_WRITE(DPLL(pipe), |
| 7992 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
| 7993 | |
| 7994 | /* No need to actually set up the DPLL with DSI */ |
| 7995 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) |
| 7996 | return; |
| 7997 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7998 | bestn = pipe_config->dpll.n; |
| 7999 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; |
| 8000 | bestm1 = pipe_config->dpll.m1; |
| 8001 | bestm2 = pipe_config->dpll.m2 >> 22; |
| 8002 | bestp1 = pipe_config->dpll.p1; |
| 8003 | bestp2 = pipe_config->dpll.p2; |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 8004 | vco = pipe_config->dpll.vco; |
Vijay Purushothaman | a945ce7e | 2015-03-05 19:30:57 +0530 | [diff] [blame] | 8005 | dpio_val = 0; |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 8006 | loopfilter = 0; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8007 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8008 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8009 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8010 | /* p1 and p2 divider */ |
| 8011 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
| 8012 | 5 << DPIO_CHV_S1_DIV_SHIFT | |
| 8013 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | |
| 8014 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | |
| 8015 | 1 << DPIO_CHV_K_DIV_SHIFT); |
| 8016 | |
| 8017 | /* Feedback post-divider - m2 */ |
| 8018 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); |
| 8019 | |
| 8020 | /* Feedback refclk divider - n and m1 */ |
| 8021 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), |
| 8022 | DPIO_CHV_M1_DIV_BY_2 | |
| 8023 | 1 << DPIO_CHV_N_DIV_SHIFT); |
| 8024 | |
| 8025 | /* M2 fraction division */ |
Ville Syrjälä | 25a25df | 2015-07-08 23:45:47 +0300 | [diff] [blame] | 8026 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8027 | |
| 8028 | /* M2 fraction division enable */ |
Vijay Purushothaman | a945ce7e | 2015-03-05 19:30:57 +0530 | [diff] [blame] | 8029 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
| 8030 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); |
| 8031 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); |
| 8032 | if (bestm2_frac) |
| 8033 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; |
| 8034 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8035 | |
Vijay Purushothaman | de3a0fd | 2015-03-05 19:32:06 +0530 | [diff] [blame] | 8036 | /* Program digital lock detect threshold */ |
| 8037 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); |
| 8038 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | |
| 8039 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); |
| 8040 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); |
| 8041 | if (!bestm2_frac) |
| 8042 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; |
| 8043 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); |
| 8044 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8045 | /* Loop filter */ |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 8046 | if (vco == 5400000) { |
| 8047 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 8048 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); |
| 8049 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 8050 | tribuf_calcntr = 0x9; |
| 8051 | } else if (vco <= 6200000) { |
| 8052 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 8053 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); |
| 8054 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 8055 | tribuf_calcntr = 0x9; |
| 8056 | } else if (vco <= 6480000) { |
| 8057 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 8058 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
| 8059 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 8060 | tribuf_calcntr = 0x8; |
| 8061 | } else { |
| 8062 | /* Not supported. Apply the same limits as in the max case */ |
| 8063 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 8064 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
| 8065 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 8066 | tribuf_calcntr = 0; |
| 8067 | } |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8068 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
| 8069 | |
Ville Syrjälä | 968040b | 2015-03-11 22:52:08 +0200 | [diff] [blame] | 8070 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 8071 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
| 8072 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); |
| 8073 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); |
| 8074 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8075 | /* AFC Recal */ |
| 8076 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
| 8077 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
| 8078 | DPIO_AFC_RECAL); |
| 8079 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8080 | mutex_unlock(&dev_priv->sb_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8081 | } |
| 8082 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 8083 | /** |
| 8084 | * vlv_force_pll_on - forcibly enable just the PLL |
| 8085 | * @dev_priv: i915 private structure |
| 8086 | * @pipe: pipe PLL to enable |
| 8087 | * @dpll: PLL configuration |
| 8088 | * |
| 8089 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
| 8090 | * in cases where we need the PLL enabled even when @pipe is not going to |
| 8091 | * be enabled. |
| 8092 | */ |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 8093 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
| 8094 | const struct dpll *dpll) |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 8095 | { |
| 8096 | struct intel_crtc *crtc = |
| 8097 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 8098 | struct intel_crtc_state *pipe_config; |
| 8099 | |
| 8100 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
| 8101 | if (!pipe_config) |
| 8102 | return -ENOMEM; |
| 8103 | |
| 8104 | pipe_config->base.crtc = &crtc->base; |
| 8105 | pipe_config->pixel_multiplier = 1; |
| 8106 | pipe_config->dpll = *dpll; |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 8107 | |
| 8108 | if (IS_CHERRYVIEW(dev)) { |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 8109 | chv_compute_dpll(crtc, pipe_config); |
| 8110 | chv_prepare_pll(crtc, pipe_config); |
| 8111 | chv_enable_pll(crtc, pipe_config); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 8112 | } else { |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 8113 | vlv_compute_dpll(crtc, pipe_config); |
| 8114 | vlv_prepare_pll(crtc, pipe_config); |
| 8115 | vlv_enable_pll(crtc, pipe_config); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 8116 | } |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 8117 | |
| 8118 | kfree(pipe_config); |
| 8119 | |
| 8120 | return 0; |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 8121 | } |
| 8122 | |
| 8123 | /** |
| 8124 | * vlv_force_pll_off - forcibly disable just the PLL |
| 8125 | * @dev_priv: i915 private structure |
| 8126 | * @pipe: pipe PLL to disable |
| 8127 | * |
| 8128 | * Disable the PLL for @pipe. To be used in cases where we need |
| 8129 | * the PLL enabled even when @pipe is not going to be enabled. |
| 8130 | */ |
| 8131 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) |
| 8132 | { |
| 8133 | if (IS_CHERRYVIEW(dev)) |
| 8134 | chv_disable_pll(to_i915(dev), pipe); |
| 8135 | else |
| 8136 | vlv_disable_pll(to_i915(dev), pipe); |
| 8137 | } |
| 8138 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 8139 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
| 8140 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 8141 | struct dpll *reduced_clock) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8142 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 8143 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8144 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8145 | u32 dpll; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8146 | struct dpll *clock = &crtc_state->dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8147 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8148 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 8149 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8150 | dpll = DPLL_VGA_MODE_DIS; |
| 8151 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8152 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8153 | dpll |= DPLLB_MODE_LVDS; |
| 8154 | else |
| 8155 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 8156 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 8157 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8158 | dpll |= (crtc_state->pixel_multiplier - 1) |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 8159 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8160 | } |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 8161 | |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 8162 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
| 8163 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 8164 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 8165 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 8166 | if (intel_crtc_has_dp_encoder(crtc_state)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 8167 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8168 | |
| 8169 | /* compute bitmask from p1 value */ |
| 8170 | if (IS_PINEVIEW(dev)) |
| 8171 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 8172 | else { |
| 8173 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 8174 | if (IS_G4X(dev) && reduced_clock) |
| 8175 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 8176 | } |
| 8177 | switch (clock->p2) { |
| 8178 | case 5: |
| 8179 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 8180 | break; |
| 8181 | case 7: |
| 8182 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 8183 | break; |
| 8184 | case 10: |
| 8185 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 8186 | break; |
| 8187 | case 14: |
| 8188 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 8189 | break; |
| 8190 | } |
| 8191 | if (INTEL_INFO(dev)->gen >= 4) |
| 8192 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 8193 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8194 | if (crtc_state->sdvo_tv_clock) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8195 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8196 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Ander Conselvan de Oliveira | ceb4100 | 2016-03-21 18:00:02 +0200 | [diff] [blame] | 8197 | intel_panel_use_ssc(dev_priv)) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8198 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 8199 | else |
| 8200 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 8201 | |
| 8202 | dpll |= DPLL_VCO_ENABLE; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8203 | crtc_state->dpll_hw_state.dpll = dpll; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8204 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8205 | if (INTEL_INFO(dev)->gen >= 4) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8206 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 8207 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8208 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8209 | } |
| 8210 | } |
| 8211 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 8212 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
| 8213 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 8214 | struct dpll *reduced_clock) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8215 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 8216 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8217 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8218 | u32 dpll; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8219 | struct dpll *clock = &crtc_state->dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8220 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8221 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 8222 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8223 | dpll = DPLL_VGA_MODE_DIS; |
| 8224 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8225 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8226 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 8227 | } else { |
| 8228 | if (clock->p1 == 2) |
| 8229 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 8230 | else |
| 8231 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 8232 | if (clock->p2 == 4) |
| 8233 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 8234 | } |
| 8235 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8236 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 8237 | dpll |= DPLL_DVO_2X_MODE; |
| 8238 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8239 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Ander Conselvan de Oliveira | ceb4100 | 2016-03-21 18:00:02 +0200 | [diff] [blame] | 8240 | intel_panel_use_ssc(dev_priv)) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8241 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 8242 | else |
| 8243 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 8244 | |
| 8245 | dpll |= DPLL_VCO_ENABLE; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8246 | crtc_state->dpll_hw_state.dpll = dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 8247 | } |
| 8248 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 8249 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8250 | { |
| 8251 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8252 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8253 | enum pipe pipe = intel_crtc->pipe; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8254 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 8255 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
Ville Syrjälä | 1caea6e | 2014-03-28 23:29:32 +0200 | [diff] [blame] | 8256 | uint32_t crtc_vtotal, crtc_vblank_end; |
| 8257 | int vsyncshift = 0; |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 8258 | |
| 8259 | /* We need to be careful not to changed the adjusted mode, for otherwise |
| 8260 | * the hw state checker will get angry at the mismatch. */ |
| 8261 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
| 8262 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8263 | |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 8264 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8265 | /* the chip adds 2 halflines automatically */ |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 8266 | crtc_vtotal -= 1; |
| 8267 | crtc_vblank_end -= 1; |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 8268 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8269 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 8270 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
| 8271 | else |
| 8272 | vsyncshift = adjusted_mode->crtc_hsync_start - |
| 8273 | adjusted_mode->crtc_htotal / 2; |
Ville Syrjälä | 1caea6e | 2014-03-28 23:29:32 +0200 | [diff] [blame] | 8274 | if (vsyncshift < 0) |
| 8275 | vsyncshift += adjusted_mode->crtc_htotal; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8276 | } |
| 8277 | |
| 8278 | if (INTEL_INFO(dev)->gen > 3) |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8279 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8280 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8281 | I915_WRITE(HTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8282 | (adjusted_mode->crtc_hdisplay - 1) | |
| 8283 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8284 | I915_WRITE(HBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8285 | (adjusted_mode->crtc_hblank_start - 1) | |
| 8286 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8287 | I915_WRITE(HSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8288 | (adjusted_mode->crtc_hsync_start - 1) | |
| 8289 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 8290 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8291 | I915_WRITE(VTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8292 | (adjusted_mode->crtc_vdisplay - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 8293 | ((crtc_vtotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8294 | I915_WRITE(VBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8295 | (adjusted_mode->crtc_vblank_start - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 8296 | ((crtc_vblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8297 | I915_WRITE(VSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8298 | (adjusted_mode->crtc_vsync_start - 1) | |
| 8299 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 8300 | |
Paulo Zanoni | b5e508d | 2012-10-24 11:34:43 -0200 | [diff] [blame] | 8301 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
| 8302 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
| 8303 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
| 8304 | * bits. */ |
| 8305 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
| 8306 | (pipe == PIPE_B || pipe == PIPE_C)) |
| 8307 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
| 8308 | |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 8309 | } |
| 8310 | |
| 8311 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) |
| 8312 | { |
| 8313 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8314 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 8315 | enum pipe pipe = intel_crtc->pipe; |
| 8316 | |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8317 | /* pipesrc controls the size that is scaled from, which should |
| 8318 | * always be the user's requested size. |
| 8319 | */ |
| 8320 | I915_WRITE(PIPESRC(pipe), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8321 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
| 8322 | (intel_crtc->config->pipe_src_h - 1)); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 8323 | } |
| 8324 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8325 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8326 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8327 | { |
| 8328 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8329 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8330 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 8331 | uint32_t tmp; |
| 8332 | |
| 8333 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8334 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
| 8335 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8336 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8337 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
| 8338 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8339 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8340 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
| 8341 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8342 | |
| 8343 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8344 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
| 8345 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8346 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8347 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
| 8348 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8349 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8350 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
| 8351 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8352 | |
| 8353 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8354 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 8355 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; |
| 8356 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8357 | } |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 8358 | } |
| 8359 | |
| 8360 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, |
| 8361 | struct intel_crtc_state *pipe_config) |
| 8362 | { |
| 8363 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8364 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 8365 | u32 tmp; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8366 | |
| 8367 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 8368 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
| 8369 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
| 8370 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8371 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
| 8372 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8373 | } |
| 8374 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 8375 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8376 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 8377 | { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8378 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
| 8379 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; |
| 8380 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; |
| 8381 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 8382 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8383 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
| 8384 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; |
| 8385 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; |
| 8386 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 8387 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8388 | mode->flags = pipe_config->base.adjusted_mode.flags; |
Maarten Lankhorst | cd13f5a | 2015-07-14 14:12:02 +0200 | [diff] [blame] | 8389 | mode->type = DRM_MODE_TYPE_DRIVER; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 8390 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 8391 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
| 8392 | mode->flags |= pipe_config->base.adjusted_mode.flags; |
Maarten Lankhorst | cd13f5a | 2015-07-14 14:12:02 +0200 | [diff] [blame] | 8393 | |
| 8394 | mode->hsync = drm_mode_hsync(mode); |
| 8395 | mode->vrefresh = drm_mode_vrefresh(mode); |
| 8396 | drm_mode_set_name(mode); |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 8397 | } |
| 8398 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8399 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
| 8400 | { |
| 8401 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8402 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8403 | uint32_t pipeconf; |
| 8404 | |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 8405 | pipeconf = 0; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8406 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 8407 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 8408 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 8409 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
Daniel Vetter | 67c72a1 | 2013-09-24 11:46:14 +0200 | [diff] [blame] | 8410 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8411 | if (intel_crtc->config->double_wide) |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 8412 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8413 | |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 8414 | /* only g4x and later have fancy bpc/dither controls */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8415 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 8416 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8417 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 8418 | pipeconf |= PIPECONF_DITHER_EN | |
| 8419 | PIPECONF_DITHER_TYPE_SP; |
| 8420 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8421 | switch (intel_crtc->config->pipe_bpp) { |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 8422 | case 18: |
| 8423 | pipeconf |= PIPECONF_6BPC; |
| 8424 | break; |
| 8425 | case 24: |
| 8426 | pipeconf |= PIPECONF_8BPC; |
| 8427 | break; |
| 8428 | case 30: |
| 8429 | pipeconf |= PIPECONF_10BPC; |
| 8430 | break; |
| 8431 | default: |
| 8432 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 8433 | BUG(); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8434 | } |
| 8435 | } |
| 8436 | |
| 8437 | if (HAS_PIPE_CXSR(dev)) { |
| 8438 | if (intel_crtc->lowfreq_avail) { |
| 8439 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 8440 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 8441 | } else { |
| 8442 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8443 | } |
| 8444 | } |
| 8445 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8446 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
Ville Syrjälä | efc2cff | 2014-03-28 23:29:31 +0200 | [diff] [blame] | 8447 | if (INTEL_INFO(dev)->gen < 4 || |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8448 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
Ville Syrjälä | efc2cff | 2014-03-28 23:29:31 +0200 | [diff] [blame] | 8449 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 8450 | else |
| 8451 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
| 8452 | } else |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8453 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 8454 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8455 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 8456 | intel_crtc->config->limited_color_range) |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 8457 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 9c8e09b | 2013-04-02 16:10:09 +0300 | [diff] [blame] | 8458 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 8459 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
| 8460 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
| 8461 | } |
| 8462 | |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8463 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
| 8464 | struct intel_crtc_state *crtc_state) |
| 8465 | { |
| 8466 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8467 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 8468 | const struct intel_limit *limit; |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8469 | int refclk = 48000; |
| 8470 | |
| 8471 | memset(&crtc_state->dpll_hw_state, 0, |
| 8472 | sizeof(crtc_state->dpll_hw_state)); |
| 8473 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8474 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8475 | if (intel_panel_use_ssc(dev_priv)) { |
| 8476 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 8477 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
| 8478 | } |
| 8479 | |
| 8480 | limit = &intel_limits_i8xx_lvds; |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8481 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8482 | limit = &intel_limits_i8xx_dvo; |
| 8483 | } else { |
| 8484 | limit = &intel_limits_i8xx_dac; |
| 8485 | } |
| 8486 | |
| 8487 | if (!crtc_state->clock_set && |
| 8488 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 8489 | refclk, NULL, &crtc_state->dpll)) { |
| 8490 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8491 | return -EINVAL; |
| 8492 | } |
| 8493 | |
| 8494 | i8xx_compute_dpll(crtc, crtc_state, NULL); |
| 8495 | |
| 8496 | return 0; |
| 8497 | } |
| 8498 | |
Ander Conselvan de Oliveira | 19ec669 | 2016-03-21 18:00:15 +0200 | [diff] [blame] | 8499 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
| 8500 | struct intel_crtc_state *crtc_state) |
| 8501 | { |
| 8502 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8503 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 8504 | const struct intel_limit *limit; |
Ander Conselvan de Oliveira | 19ec669 | 2016-03-21 18:00:15 +0200 | [diff] [blame] | 8505 | int refclk = 96000; |
| 8506 | |
| 8507 | memset(&crtc_state->dpll_hw_state, 0, |
| 8508 | sizeof(crtc_state->dpll_hw_state)); |
| 8509 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8510 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Ander Conselvan de Oliveira | 19ec669 | 2016-03-21 18:00:15 +0200 | [diff] [blame] | 8511 | if (intel_panel_use_ssc(dev_priv)) { |
| 8512 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 8513 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
| 8514 | } |
| 8515 | |
| 8516 | if (intel_is_dual_link_lvds(dev)) |
| 8517 | limit = &intel_limits_g4x_dual_channel_lvds; |
| 8518 | else |
| 8519 | limit = &intel_limits_g4x_single_channel_lvds; |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8520 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
| 8521 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
Ander Conselvan de Oliveira | 19ec669 | 2016-03-21 18:00:15 +0200 | [diff] [blame] | 8522 | limit = &intel_limits_g4x_hdmi; |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8523 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
Ander Conselvan de Oliveira | 19ec669 | 2016-03-21 18:00:15 +0200 | [diff] [blame] | 8524 | limit = &intel_limits_g4x_sdvo; |
| 8525 | } else { |
| 8526 | /* The option is for other outputs */ |
| 8527 | limit = &intel_limits_i9xx_sdvo; |
| 8528 | } |
| 8529 | |
| 8530 | if (!crtc_state->clock_set && |
| 8531 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 8532 | refclk, NULL, &crtc_state->dpll)) { |
| 8533 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8534 | return -EINVAL; |
| 8535 | } |
| 8536 | |
| 8537 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
| 8538 | |
| 8539 | return 0; |
| 8540 | } |
| 8541 | |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8542 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
| 8543 | struct intel_crtc_state *crtc_state) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8544 | { |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 8545 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8546 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 8547 | const struct intel_limit *limit; |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8548 | int refclk = 96000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8549 | |
Ander Conselvan de Oliveira | dd3cd74 | 2015-05-15 13:34:29 +0300 | [diff] [blame] | 8550 | memset(&crtc_state->dpll_hw_state, 0, |
| 8551 | sizeof(crtc_state->dpll_hw_state)); |
| 8552 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8553 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8554 | if (intel_panel_use_ssc(dev_priv)) { |
| 8555 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 8556 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
| 8557 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8558 | |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8559 | limit = &intel_limits_pineview_lvds; |
| 8560 | } else { |
| 8561 | limit = &intel_limits_pineview_sdvo; |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8562 | } |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 8563 | |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8564 | if (!crtc_state->clock_set && |
| 8565 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 8566 | refclk, NULL, &crtc_state->dpll)) { |
| 8567 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8568 | return -EINVAL; |
| 8569 | } |
| 8570 | |
| 8571 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
| 8572 | |
| 8573 | return 0; |
| 8574 | } |
| 8575 | |
| 8576 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
| 8577 | struct intel_crtc_state *crtc_state) |
| 8578 | { |
| 8579 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8580 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 8581 | const struct intel_limit *limit; |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8582 | int refclk = 96000; |
| 8583 | |
| 8584 | memset(&crtc_state->dpll_hw_state, 0, |
| 8585 | sizeof(crtc_state->dpll_hw_state)); |
| 8586 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 8587 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8588 | if (intel_panel_use_ssc(dev_priv)) { |
| 8589 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 8590 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8591 | } |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 8592 | |
| 8593 | limit = &intel_limits_i9xx_lvds; |
| 8594 | } else { |
| 8595 | limit = &intel_limits_i9xx_sdvo; |
| 8596 | } |
| 8597 | |
| 8598 | if (!crtc_state->clock_set && |
| 8599 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 8600 | refclk, NULL, &crtc_state->dpll)) { |
| 8601 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8602 | return -EINVAL; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 8603 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8604 | |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 8605 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8606 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 8607 | return 0; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8608 | } |
| 8609 | |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 8610 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
| 8611 | struct intel_crtc_state *crtc_state) |
| 8612 | { |
| 8613 | int refclk = 100000; |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 8614 | const struct intel_limit *limit = &intel_limits_chv; |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 8615 | |
| 8616 | memset(&crtc_state->dpll_hw_state, 0, |
| 8617 | sizeof(crtc_state->dpll_hw_state)); |
| 8618 | |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 8619 | if (!crtc_state->clock_set && |
| 8620 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 8621 | refclk, NULL, &crtc_state->dpll)) { |
| 8622 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8623 | return -EINVAL; |
| 8624 | } |
| 8625 | |
| 8626 | chv_compute_dpll(crtc, crtc_state); |
| 8627 | |
| 8628 | return 0; |
| 8629 | } |
| 8630 | |
| 8631 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, |
| 8632 | struct intel_crtc_state *crtc_state) |
| 8633 | { |
| 8634 | int refclk = 100000; |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 8635 | const struct intel_limit *limit = &intel_limits_vlv; |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 8636 | |
| 8637 | memset(&crtc_state->dpll_hw_state, 0, |
| 8638 | sizeof(crtc_state->dpll_hw_state)); |
| 8639 | |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 8640 | if (!crtc_state->clock_set && |
| 8641 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 8642 | refclk, NULL, &crtc_state->dpll)) { |
| 8643 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8644 | return -EINVAL; |
| 8645 | } |
| 8646 | |
| 8647 | vlv_compute_dpll(crtc, crtc_state); |
| 8648 | |
| 8649 | return 0; |
| 8650 | } |
| 8651 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8652 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8653 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8654 | { |
| 8655 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8656 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8657 | uint32_t tmp; |
| 8658 | |
Ville Syrjälä | dc9e7dec | 2014-01-10 14:06:45 +0200 | [diff] [blame] | 8659 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
| 8660 | return; |
| 8661 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8662 | tmp = I915_READ(PFIT_CONTROL); |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 8663 | if (!(tmp & PFIT_ENABLE)) |
| 8664 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8665 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 8666 | /* Check whether the pfit is attached to our pipe. */ |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8667 | if (INTEL_INFO(dev)->gen < 4) { |
| 8668 | if (crtc->pipe != PIPE_B) |
| 8669 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8670 | } else { |
| 8671 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
| 8672 | return; |
| 8673 | } |
| 8674 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 8675 | pipe_config->gmch_pfit.control = tmp; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8676 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8677 | } |
| 8678 | |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8679 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8680 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8681 | { |
| 8682 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8683 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8684 | int pipe = pipe_config->cpu_transcoder; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 8685 | struct dpll clock; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8686 | u32 mdiv; |
Chris Wilson | 662c6ec | 2013-09-25 14:24:01 -0700 | [diff] [blame] | 8687 | int refclk = 100000; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8688 | |
Ville Syrjälä | b521973 | 2016-03-15 16:40:01 +0200 | [diff] [blame] | 8689 | /* In case of DSI, DPLL will not be used */ |
| 8690 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 8691 | return; |
| 8692 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8693 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 8694 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8695 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8696 | |
| 8697 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
| 8698 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
| 8699 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
| 8700 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
| 8701 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
| 8702 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 8703 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8704 | } |
| 8705 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 8706 | static void |
| 8707 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, |
| 8708 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8709 | { |
| 8710 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8711 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8712 | u32 val, base, offset; |
| 8713 | int pipe = crtc->pipe, plane = crtc->plane; |
| 8714 | int fourcc, pixel_format; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 8715 | unsigned int aligned_height; |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8716 | struct drm_framebuffer *fb; |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 8717 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8718 | |
Damien Lespiau | 42a7b08 | 2015-02-05 19:35:13 +0000 | [diff] [blame] | 8719 | val = I915_READ(DSPCNTR(plane)); |
| 8720 | if (!(val & DISPLAY_PLANE_ENABLE)) |
| 8721 | return; |
| 8722 | |
Damien Lespiau | d9806c9 | 2015-01-21 14:07:19 +0000 | [diff] [blame] | 8723 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 8724 | if (!intel_fb) { |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8725 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 8726 | return; |
| 8727 | } |
| 8728 | |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 8729 | fb = &intel_fb->base; |
| 8730 | |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 8731 | if (INTEL_INFO(dev)->gen >= 4) { |
| 8732 | if (val & DISPPLANE_TILED) { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 8733 | plane_config->tiling = I915_TILING_X; |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 8734 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 8735 | } |
| 8736 | } |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8737 | |
| 8738 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
Damien Lespiau | b35d63f | 2015-01-20 12:51:50 +0000 | [diff] [blame] | 8739 | fourcc = i9xx_format_to_fourcc(pixel_format); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8740 | fb->pixel_format = fourcc; |
| 8741 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8742 | |
| 8743 | if (INTEL_INFO(dev)->gen >= 4) { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 8744 | if (plane_config->tiling) |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8745 | offset = I915_READ(DSPTILEOFF(plane)); |
| 8746 | else |
| 8747 | offset = I915_READ(DSPLINOFF(plane)); |
| 8748 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 8749 | } else { |
| 8750 | base = I915_READ(DSPADDR(plane)); |
| 8751 | } |
| 8752 | plane_config->base = base; |
| 8753 | |
| 8754 | val = I915_READ(PIPESRC(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8755 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 8756 | fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8757 | |
| 8758 | val = I915_READ(DSPSTRIDE(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8759 | fb->pitches[0] = val & 0xffffffc0; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8760 | |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8761 | aligned_height = intel_fb_align_height(dev, fb->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 8762 | fb->pixel_format, |
| 8763 | fb->modifier[0]); |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8764 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 8765 | plane_config->size = fb->pitches[0] * aligned_height; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8766 | |
Damien Lespiau | 2844a92 | 2015-01-20 12:51:48 +0000 | [diff] [blame] | 8767 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 8768 | pipe_name(pipe), plane, fb->width, fb->height, |
| 8769 | fb->bits_per_pixel, base, fb->pitches[0], |
| 8770 | plane_config->size); |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8771 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 8772 | plane_config->fb = intel_fb; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8773 | } |
| 8774 | |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8775 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8776 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8777 | { |
| 8778 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8779 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8780 | int pipe = pipe_config->cpu_transcoder; |
| 8781 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 8782 | struct dpll clock; |
Imre Deak | 0d7b6b1 | 2015-07-02 14:29:58 +0300 | [diff] [blame] | 8783 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8784 | int refclk = 100000; |
| 8785 | |
Ville Syrjälä | b521973 | 2016-03-15 16:40:01 +0200 | [diff] [blame] | 8786 | /* In case of DSI, DPLL will not be used */ |
| 8787 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) |
| 8788 | return; |
| 8789 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8790 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8791 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
| 8792 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
| 8793 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
| 8794 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
Imre Deak | 0d7b6b1 | 2015-07-02 14:29:58 +0300 | [diff] [blame] | 8795 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8796 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8797 | |
| 8798 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
Imre Deak | 0d7b6b1 | 2015-07-02 14:29:58 +0300 | [diff] [blame] | 8799 | clock.m2 = (pll_dw0 & 0xff) << 22; |
| 8800 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) |
| 8801 | clock.m2 |= pll_dw2 & 0x3fffff; |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8802 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
| 8803 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
| 8804 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
| 8805 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 8806 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8807 | } |
| 8808 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8809 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8810 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8811 | { |
| 8812 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8813 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 8814 | enum intel_display_power_domain power_domain; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8815 | uint32_t tmp; |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 8816 | bool ret; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8817 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 8818 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
| 8819 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 8820 | return false; |
| 8821 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 8822 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 8823 | pipe_config->shared_dpll = NULL; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 8824 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 8825 | ret = false; |
| 8826 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8827 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 8828 | if (!(tmp & PIPECONF_ENABLE)) |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 8829 | goto out; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8830 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8831 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 8832 | switch (tmp & PIPECONF_BPC_MASK) { |
| 8833 | case PIPECONF_6BPC: |
| 8834 | pipe_config->pipe_bpp = 18; |
| 8835 | break; |
| 8836 | case PIPECONF_8BPC: |
| 8837 | pipe_config->pipe_bpp = 24; |
| 8838 | break; |
| 8839 | case PIPECONF_10BPC: |
| 8840 | pipe_config->pipe_bpp = 30; |
| 8841 | break; |
| 8842 | default: |
| 8843 | break; |
| 8844 | } |
| 8845 | } |
| 8846 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8847 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 8848 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 8849 | pipe_config->limited_color_range = true; |
| 8850 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 8851 | if (INTEL_INFO(dev)->gen < 4) |
| 8852 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
| 8853 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8854 | intel_get_pipe_timings(crtc, pipe_config); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 8855 | intel_get_pipe_src_size(crtc, pipe_config); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8856 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8857 | i9xx_get_pfit_config(crtc, pipe_config); |
| 8858 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8859 | if (INTEL_INFO(dev)->gen >= 4) { |
Ville Syrjälä | c231775 | 2016-03-15 16:39:56 +0200 | [diff] [blame] | 8860 | /* No way to read it out on pipes B and C */ |
| 8861 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) |
| 8862 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
| 8863 | else |
| 8864 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8865 | pipe_config->pixel_multiplier = |
| 8866 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
| 8867 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8868 | pipe_config->dpll_hw_state.dpll_md = tmp; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8869 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 8870 | tmp = I915_READ(DPLL(crtc->pipe)); |
| 8871 | pipe_config->pixel_multiplier = |
| 8872 | ((tmp & SDVO_MULTIPLIER_MASK) |
| 8873 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
| 8874 | } else { |
| 8875 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
| 8876 | * port and will be fixed up in the encoder->get_config |
| 8877 | * function. */ |
| 8878 | pipe_config->pixel_multiplier = 1; |
| 8879 | } |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8880 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8881 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 8882 | /* |
| 8883 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs |
| 8884 | * on 830. Filter it out here so that we don't |
| 8885 | * report errors due to that. |
| 8886 | */ |
| 8887 | if (IS_I830(dev)) |
| 8888 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
| 8889 | |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8890 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
| 8891 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
Ville Syrjälä | 165e901 | 2013-06-26 17:44:15 +0300 | [diff] [blame] | 8892 | } else { |
| 8893 | /* Mask out read-only status bits. */ |
| 8894 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
| 8895 | DPLL_PORTC_READY_MASK | |
| 8896 | DPLL_PORTB_READY_MASK); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8897 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8898 | |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8899 | if (IS_CHERRYVIEW(dev)) |
| 8900 | chv_crtc_clock_get(crtc, pipe_config); |
| 8901 | else if (IS_VALLEYVIEW(dev)) |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8902 | vlv_crtc_clock_get(crtc, pipe_config); |
| 8903 | else |
| 8904 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8905 | |
Ville Syrjälä | 0f64614 | 2015-08-26 19:39:18 +0300 | [diff] [blame] | 8906 | /* |
| 8907 | * Normally the dotclock is filled in by the encoder .get_config() |
| 8908 | * but in case the pipe is enabled w/o any ports we need a sane |
| 8909 | * default. |
| 8910 | */ |
| 8911 | pipe_config->base.adjusted_mode.crtc_clock = |
| 8912 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
| 8913 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 8914 | ret = true; |
| 8915 | |
| 8916 | out: |
| 8917 | intel_display_power_put(dev_priv, power_domain); |
| 8918 | |
| 8919 | return ret; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8920 | } |
| 8921 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8922 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8923 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 8924 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8925 | struct intel_encoder *encoder; |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 8926 | int i; |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8927 | u32 val, final; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8928 | bool has_lvds = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8929 | bool has_cpu_edp = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8930 | bool has_panel = false; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8931 | bool has_ck505 = false; |
| 8932 | bool can_ssc = false; |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 8933 | bool using_ssc_source = false; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8934 | |
| 8935 | /* We need to take the global config into account */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 8936 | for_each_intel_encoder(dev, encoder) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8937 | switch (encoder->type) { |
| 8938 | case INTEL_OUTPUT_LVDS: |
| 8939 | has_panel = true; |
| 8940 | has_lvds = true; |
| 8941 | break; |
| 8942 | case INTEL_OUTPUT_EDP: |
| 8943 | has_panel = true; |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 8944 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8945 | has_cpu_edp = true; |
| 8946 | break; |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 8947 | default: |
| 8948 | break; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8949 | } |
| 8950 | } |
| 8951 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8952 | if (HAS_PCH_IBX(dev)) { |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 8953 | has_ck505 = dev_priv->vbt.display_clock_mode; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8954 | can_ssc = has_ck505; |
| 8955 | } else { |
| 8956 | has_ck505 = false; |
| 8957 | can_ssc = true; |
| 8958 | } |
| 8959 | |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 8960 | /* Check if any DPLLs are using the SSC source */ |
| 8961 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 8962 | u32 temp = I915_READ(PCH_DPLL(i)); |
| 8963 | |
| 8964 | if (!(temp & DPLL_VCO_ENABLE)) |
| 8965 | continue; |
| 8966 | |
| 8967 | if ((temp & PLL_REF_INPUT_MASK) == |
| 8968 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 8969 | using_ssc_source = true; |
| 8970 | break; |
| 8971 | } |
| 8972 | } |
| 8973 | |
| 8974 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", |
| 8975 | has_panel, has_lvds, has_ck505, using_ssc_source); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8976 | |
| 8977 | /* Ironlake: try to setup display ref clock before DPLL |
| 8978 | * enabling. This is only under driver's control after |
| 8979 | * PCH B stepping, previous chipset stepping should be |
| 8980 | * ignoring this setting. |
| 8981 | */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8982 | val = I915_READ(PCH_DREF_CONTROL); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8983 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8984 | /* As we must carefully and slowly disable/enable each source in turn, |
| 8985 | * compute the final state we want first and check if we need to |
| 8986 | * make any changes at all. |
| 8987 | */ |
| 8988 | final = val; |
| 8989 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8990 | if (has_ck505) |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8991 | final |= DREF_NONSPREAD_CK505_ENABLE; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8992 | else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8993 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 8994 | |
Daniel Vetter | 8c07eb6 | 2016-06-09 18:39:07 +0200 | [diff] [blame] | 8995 | final &= ~DREF_SSC_SOURCE_MASK; |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8996 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Daniel Vetter | 8c07eb6 | 2016-06-09 18:39:07 +0200 | [diff] [blame] | 8997 | final &= ~DREF_SSC1_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8998 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8999 | if (has_panel) { |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9000 | final |= DREF_SSC_SOURCE_ENABLE; |
| 9001 | |
| 9002 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 9003 | final |= DREF_SSC1_ENABLE; |
| 9004 | |
| 9005 | if (has_cpu_edp) { |
| 9006 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 9007 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 9008 | else |
| 9009 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 9010 | } else |
| 9011 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 9012 | } else if (using_ssc_source) { |
| 9013 | final |= DREF_SSC_SOURCE_ENABLE; |
| 9014 | final |= DREF_SSC1_ENABLE; |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9015 | } |
| 9016 | |
| 9017 | if (final == val) |
| 9018 | return; |
| 9019 | |
| 9020 | /* Always enable nonspread source */ |
| 9021 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 9022 | |
| 9023 | if (has_ck505) |
| 9024 | val |= DREF_NONSPREAD_CK505_ENABLE; |
| 9025 | else |
| 9026 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 9027 | |
| 9028 | if (has_panel) { |
| 9029 | val &= ~DREF_SSC_SOURCE_MASK; |
| 9030 | val |= DREF_SSC_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 9031 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9032 | /* SSC must be turned on before enabling the CPU output */ |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 9033 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9034 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9035 | val |= DREF_SSC1_ENABLE; |
Daniel Vetter | e77166b | 2012-03-30 22:14:05 +0200 | [diff] [blame] | 9036 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9037 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9038 | |
| 9039 | /* Get SSC going before enabling the outputs */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9040 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9041 | POSTING_READ(PCH_DREF_CONTROL); |
| 9042 | udelay(200); |
| 9043 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9044 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 9045 | |
| 9046 | /* Enable CPU source on CPU attached eDP */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9047 | if (has_cpu_edp) { |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 9048 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9049 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9050 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 9051 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9052 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9053 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9054 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9055 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9056 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9057 | POSTING_READ(PCH_DREF_CONTROL); |
| 9058 | udelay(200); |
| 9059 | } else { |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 9060 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9061 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9062 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9063 | |
| 9064 | /* Turn off CPU output */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9065 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9066 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9067 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9068 | POSTING_READ(PCH_DREF_CONTROL); |
| 9069 | udelay(200); |
| 9070 | |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 9071 | if (!using_ssc_source) { |
| 9072 | DRM_DEBUG_KMS("Disabling SSC source\n"); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9073 | |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 9074 | /* Turn off the SSC source */ |
| 9075 | val &= ~DREF_SSC_SOURCE_MASK; |
| 9076 | val |= DREF_SSC_SOURCE_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 9077 | |
Lyude | 1c1a24d | 2016-06-14 11:04:09 -0400 | [diff] [blame] | 9078 | /* Turn off SSC1 */ |
| 9079 | val &= ~DREF_SSC1_ENABLE; |
| 9080 | |
| 9081 | I915_WRITE(PCH_DREF_CONTROL, val); |
| 9082 | POSTING_READ(PCH_DREF_CONTROL); |
| 9083 | udelay(200); |
| 9084 | } |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 9085 | } |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 9086 | |
| 9087 | BUG_ON(val != final); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 9088 | } |
| 9089 | |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9090 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9091 | { |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9092 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9093 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9094 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 9095 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
| 9096 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9097 | |
Imre Deak | cf3598c | 2016-06-28 13:37:31 +0300 | [diff] [blame] | 9098 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
| 9099 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9100 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9101 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9102 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 9103 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
| 9104 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9105 | |
Imre Deak | cf3598c | 2016-06-28 13:37:31 +0300 | [diff] [blame] | 9106 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
| 9107 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9108 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9109 | } |
| 9110 | |
| 9111 | /* WaMPhyProgramming:hsw */ |
| 9112 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
| 9113 | { |
| 9114 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9115 | |
| 9116 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
| 9117 | tmp &= ~(0xFF << 24); |
| 9118 | tmp |= (0x12 << 24); |
| 9119 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
| 9120 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9121 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
| 9122 | tmp |= (1 << 11); |
| 9123 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
| 9124 | |
| 9125 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
| 9126 | tmp |= (1 << 11); |
| 9127 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
| 9128 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9129 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
| 9130 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 9131 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
| 9132 | |
| 9133 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
| 9134 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 9135 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
| 9136 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9137 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
| 9138 | tmp &= ~(7 << 13); |
| 9139 | tmp |= (5 << 13); |
| 9140 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9141 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9142 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
| 9143 | tmp &= ~(7 << 13); |
| 9144 | tmp |= (5 << 13); |
| 9145 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9146 | |
| 9147 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
| 9148 | tmp &= ~0xFF; |
| 9149 | tmp |= 0x1C; |
| 9150 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
| 9151 | |
| 9152 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
| 9153 | tmp &= ~0xFF; |
| 9154 | tmp |= 0x1C; |
| 9155 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
| 9156 | |
| 9157 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
| 9158 | tmp &= ~(0xFF << 16); |
| 9159 | tmp |= (0x1C << 16); |
| 9160 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
| 9161 | |
| 9162 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
| 9163 | tmp &= ~(0xFF << 16); |
| 9164 | tmp |= (0x1C << 16); |
| 9165 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
| 9166 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9167 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
| 9168 | tmp |= (1 << 27); |
| 9169 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9170 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9171 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
| 9172 | tmp |= (1 << 27); |
| 9173 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9174 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9175 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
| 9176 | tmp &= ~(0xF << 28); |
| 9177 | tmp |= (4 << 28); |
| 9178 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9179 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 9180 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
| 9181 | tmp &= ~(0xF << 28); |
| 9182 | tmp |= (4 << 28); |
| 9183 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9184 | } |
| 9185 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 9186 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
| 9187 | * Programming" based on the parameters passed: |
| 9188 | * - Sequence to enable CLKOUT_DP |
| 9189 | * - Sequence to enable CLKOUT_DP without spread |
| 9190 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
| 9191 | */ |
| 9192 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
| 9193 | bool with_fdi) |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9194 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9195 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 9196 | uint32_t reg, tmp; |
| 9197 | |
| 9198 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
| 9199 | with_spread = true; |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 9200 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 9201 | with_fdi = false; |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9202 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 9203 | mutex_lock(&dev_priv->sb_lock); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9204 | |
| 9205 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 9206 | tmp &= ~SBI_SSCCTL_DISABLE; |
| 9207 | tmp |= SBI_SSCCTL_PATHALT; |
| 9208 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 9209 | |
| 9210 | udelay(24); |
| 9211 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 9212 | if (with_spread) { |
| 9213 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 9214 | tmp &= ~SBI_SSCCTL_PATHALT; |
| 9215 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 9216 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 9217 | if (with_fdi) { |
| 9218 | lpt_reset_fdi_mphy(dev_priv); |
| 9219 | lpt_program_fdi_mphy(dev_priv); |
| 9220 | } |
| 9221 | } |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9222 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 9223 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 9224 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 9225 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 9226 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
Daniel Vetter | c00db24 | 2013-01-22 15:33:27 +0100 | [diff] [blame] | 9227 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 9228 | mutex_unlock(&dev_priv->sb_lock); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9229 | } |
| 9230 | |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9231 | /* Sequence to disable CLKOUT_DP */ |
| 9232 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
| 9233 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9234 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9235 | uint32_t reg, tmp; |
| 9236 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 9237 | mutex_lock(&dev_priv->sb_lock); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9238 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 9239 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9240 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 9241 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 9242 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 9243 | |
| 9244 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 9245 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
| 9246 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
| 9247 | tmp |= SBI_SSCCTL_PATHALT; |
| 9248 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 9249 | udelay(32); |
| 9250 | } |
| 9251 | tmp |= SBI_SSCCTL_DISABLE; |
| 9252 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 9253 | } |
| 9254 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 9255 | mutex_unlock(&dev_priv->sb_lock); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9256 | } |
| 9257 | |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 9258 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
| 9259 | |
| 9260 | static const uint16_t sscdivintphase[] = { |
| 9261 | [BEND_IDX( 50)] = 0x3B23, |
| 9262 | [BEND_IDX( 45)] = 0x3B23, |
| 9263 | [BEND_IDX( 40)] = 0x3C23, |
| 9264 | [BEND_IDX( 35)] = 0x3C23, |
| 9265 | [BEND_IDX( 30)] = 0x3D23, |
| 9266 | [BEND_IDX( 25)] = 0x3D23, |
| 9267 | [BEND_IDX( 20)] = 0x3E23, |
| 9268 | [BEND_IDX( 15)] = 0x3E23, |
| 9269 | [BEND_IDX( 10)] = 0x3F23, |
| 9270 | [BEND_IDX( 5)] = 0x3F23, |
| 9271 | [BEND_IDX( 0)] = 0x0025, |
| 9272 | [BEND_IDX( -5)] = 0x0025, |
| 9273 | [BEND_IDX(-10)] = 0x0125, |
| 9274 | [BEND_IDX(-15)] = 0x0125, |
| 9275 | [BEND_IDX(-20)] = 0x0225, |
| 9276 | [BEND_IDX(-25)] = 0x0225, |
| 9277 | [BEND_IDX(-30)] = 0x0325, |
| 9278 | [BEND_IDX(-35)] = 0x0325, |
| 9279 | [BEND_IDX(-40)] = 0x0425, |
| 9280 | [BEND_IDX(-45)] = 0x0425, |
| 9281 | [BEND_IDX(-50)] = 0x0525, |
| 9282 | }; |
| 9283 | |
| 9284 | /* |
| 9285 | * Bend CLKOUT_DP |
| 9286 | * steps -50 to 50 inclusive, in steps of 5 |
| 9287 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) |
| 9288 | * change in clock period = -(steps / 10) * 5.787 ps |
| 9289 | */ |
| 9290 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) |
| 9291 | { |
| 9292 | uint32_t tmp; |
| 9293 | int idx = BEND_IDX(steps); |
| 9294 | |
| 9295 | if (WARN_ON(steps % 5 != 0)) |
| 9296 | return; |
| 9297 | |
| 9298 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) |
| 9299 | return; |
| 9300 | |
| 9301 | mutex_lock(&dev_priv->sb_lock); |
| 9302 | |
| 9303 | if (steps % 10 != 0) |
| 9304 | tmp = 0xAAAAAAAB; |
| 9305 | else |
| 9306 | tmp = 0x00000000; |
| 9307 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); |
| 9308 | |
| 9309 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); |
| 9310 | tmp &= 0xffff0000; |
| 9311 | tmp |= sscdivintphase[idx]; |
| 9312 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); |
| 9313 | |
| 9314 | mutex_unlock(&dev_priv->sb_lock); |
| 9315 | } |
| 9316 | |
| 9317 | #undef BEND_IDX |
| 9318 | |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 9319 | static void lpt_init_pch_refclk(struct drm_device *dev) |
| 9320 | { |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 9321 | struct intel_encoder *encoder; |
| 9322 | bool has_vga = false; |
| 9323 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 9324 | for_each_intel_encoder(dev, encoder) { |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 9325 | switch (encoder->type) { |
| 9326 | case INTEL_OUTPUT_ANALOG: |
| 9327 | has_vga = true; |
| 9328 | break; |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 9329 | default: |
| 9330 | break; |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 9331 | } |
| 9332 | } |
| 9333 | |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 9334 | if (has_vga) { |
| 9335 | lpt_bend_clkout_dp(to_i915(dev), 0); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9336 | lpt_enable_clkout_dp(dev, true, true); |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 9337 | } else { |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 9338 | lpt_disable_clkout_dp(dev); |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 9339 | } |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 9340 | } |
| 9341 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 9342 | /* |
| 9343 | * Initialize reference clocks when the driver loads |
| 9344 | */ |
| 9345 | void intel_init_pch_refclk(struct drm_device *dev) |
| 9346 | { |
| 9347 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 9348 | ironlake_init_pch_refclk(dev); |
| 9349 | else if (HAS_PCH_LPT(dev)) |
| 9350 | lpt_init_pch_refclk(dev); |
| 9351 | } |
| 9352 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 9353 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9354 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9355 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 9357 | int pipe = intel_crtc->pipe; |
| 9358 | uint32_t val; |
| 9359 | |
Daniel Vetter | 7811407 | 2013-06-13 00:54:57 +0200 | [diff] [blame] | 9360 | val = 0; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9361 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9362 | switch (intel_crtc->config->pipe_bpp) { |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9363 | case 18: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 9364 | val |= PIPECONF_6BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9365 | break; |
| 9366 | case 24: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 9367 | val |= PIPECONF_8BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9368 | break; |
| 9369 | case 30: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 9370 | val |= PIPECONF_10BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9371 | break; |
| 9372 | case 36: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 9373 | val |= PIPECONF_12BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9374 | break; |
| 9375 | default: |
Paulo Zanoni | cc769b6 | 2012-09-20 18:36:03 -0300 | [diff] [blame] | 9376 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 9377 | BUG(); |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9378 | } |
| 9379 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9380 | if (intel_crtc->config->dither) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9381 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 9382 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9383 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9384 | val |= PIPECONF_INTERLACED_ILK; |
| 9385 | else |
| 9386 | val |= PIPECONF_PROGRESSIVE; |
| 9387 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9388 | if (intel_crtc->config->limited_color_range) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 9389 | val |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 9390 | |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 9391 | I915_WRITE(PIPECONF(pipe), val); |
| 9392 | POSTING_READ(PIPECONF(pipe)); |
| 9393 | } |
| 9394 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 9395 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 9396 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9397 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 9398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9399 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 9400 | u32 val = 0; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 9401 | |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 9402 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 9403 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 9404 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9405 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 9406 | val |= PIPECONF_INTERLACED_ILK; |
| 9407 | else |
| 9408 | val |= PIPECONF_PROGRESSIVE; |
| 9409 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 9410 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
| 9411 | POSTING_READ(PIPECONF(cpu_transcoder)); |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 9412 | } |
| 9413 | |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 9414 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
| 9415 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9416 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 9417 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 9418 | |
| 9419 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
| 9420 | u32 val = 0; |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 9421 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9422 | switch (intel_crtc->config->pipe_bpp) { |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 9423 | case 18: |
| 9424 | val |= PIPEMISC_DITHER_6_BPC; |
| 9425 | break; |
| 9426 | case 24: |
| 9427 | val |= PIPEMISC_DITHER_8_BPC; |
| 9428 | break; |
| 9429 | case 30: |
| 9430 | val |= PIPEMISC_DITHER_10_BPC; |
| 9431 | break; |
| 9432 | case 36: |
| 9433 | val |= PIPEMISC_DITHER_12_BPC; |
| 9434 | break; |
| 9435 | default: |
| 9436 | /* Case prevented by pipe_config_set_bpp. */ |
| 9437 | BUG(); |
| 9438 | } |
| 9439 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9440 | if (intel_crtc->config->dither) |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 9441 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
| 9442 | |
Jani Nikula | 391bf04 | 2016-03-18 17:05:40 +0200 | [diff] [blame] | 9443 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 9444 | } |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 9445 | } |
| 9446 | |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 9447 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
| 9448 | { |
| 9449 | /* |
| 9450 | * Account for spread spectrum to avoid |
| 9451 | * oversubscribing the link. Max center spread |
| 9452 | * is 2.5%; use 5% for safety's sake. |
| 9453 | */ |
| 9454 | u32 bps = target_clock * bpp * 21 / 20; |
Ville Syrjälä | 619d4d0 | 2014-02-27 14:23:14 +0200 | [diff] [blame] | 9455 | return DIV_ROUND_UP(bps, link_bw * 8); |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 9456 | } |
| 9457 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 9458 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 9459 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 9460 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
Paulo Zanoni | f48d8f2 | 2012-09-20 18:36:04 -0300 | [diff] [blame] | 9461 | } |
| 9462 | |
Ander Conselvan de Oliveira | b75ca6f | 2016-03-21 18:00:11 +0200 | [diff] [blame] | 9463 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
| 9464 | struct intel_crtc_state *crtc_state, |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 9465 | struct dpll *reduced_clock) |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 9466 | { |
| 9467 | struct drm_crtc *crtc = &intel_crtc->base; |
| 9468 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9469 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | b75ca6f | 2016-03-21 18:00:11 +0200 | [diff] [blame] | 9470 | u32 dpll, fp, fp2; |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 9471 | int factor; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9472 | |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 9473 | /* Enable autotuning of the PLL clock (if permissible) */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 9474 | factor = 21; |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 9475 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 9476 | if ((intel_panel_use_ssc(dev_priv) && |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 9477 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
Daniel Vetter | f0b4405 | 2013-04-04 22:20:33 +0200 | [diff] [blame] | 9478 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 9479 | factor = 25; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9480 | } else if (crtc_state->sdvo_tv_clock) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 9481 | factor = 20; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 9482 | |
Ander Conselvan de Oliveira | b75ca6f | 2016-03-21 18:00:11 +0200 | [diff] [blame] | 9483 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 9484 | |
Ander Conselvan de Oliveira | b75ca6f | 2016-03-21 18:00:11 +0200 | [diff] [blame] | 9485 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
| 9486 | fp |= FP_CB_TUNE; |
| 9487 | |
| 9488 | if (reduced_clock) { |
| 9489 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
| 9490 | |
| 9491 | if (reduced_clock->m < factor * reduced_clock->n) |
| 9492 | fp2 |= FP_CB_TUNE; |
| 9493 | } else { |
| 9494 | fp2 = fp; |
| 9495 | } |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 9496 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 9497 | dpll = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 9498 | |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 9499 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9500 | dpll |= DPLLB_MODE_LVDS; |
| 9501 | else |
| 9502 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 9503 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9504 | dpll |= (crtc_state->pixel_multiplier - 1) |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 9505 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 9506 | |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 9507 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
| 9508 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 9509 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 9510 | |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 9511 | if (intel_crtc_has_dp_encoder(crtc_state)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 9512 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9513 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9514 | /* compute bitmask from p1 value */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9515 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9516 | /* also FPA1 */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9517 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9518 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9519 | switch (crtc_state->dpll.p2) { |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9520 | case 5: |
| 9521 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 9522 | break; |
| 9523 | case 7: |
| 9524 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 9525 | break; |
| 9526 | case 10: |
| 9527 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 9528 | break; |
| 9529 | case 14: |
| 9530 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 9531 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9532 | } |
| 9533 | |
Ville Syrjälä | 3d6e9ee | 2016-06-22 21:57:03 +0300 | [diff] [blame] | 9534 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 9535 | intel_panel_use_ssc(dev_priv)) |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 9536 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9537 | else |
| 9538 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 9539 | |
Ander Conselvan de Oliveira | b75ca6f | 2016-03-21 18:00:11 +0200 | [diff] [blame] | 9540 | dpll |= DPLL_VCO_ENABLE; |
| 9541 | |
| 9542 | crtc_state->dpll_hw_state.dpll = dpll; |
| 9543 | crtc_state->dpll_hw_state.fp0 = fp; |
| 9544 | crtc_state->dpll_hw_state.fp1 = fp2; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 9545 | } |
| 9546 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9547 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
| 9548 | struct intel_crtc_state *crtc_state) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9549 | { |
Ander Conselvan de Oliveira | 997c030 | 2016-03-21 18:00:12 +0200 | [diff] [blame] | 9550 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9551 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 9552 | struct dpll reduced_clock; |
Ander Conselvan de Oliveira | 7ed9f89 | 2016-03-21 18:00:07 +0200 | [diff] [blame] | 9553 | bool has_reduced_clock = false; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 9554 | struct intel_shared_dpll *pll; |
Ander Conselvan de Oliveira | 1b6f495 | 2016-05-04 12:11:59 +0300 | [diff] [blame] | 9555 | const struct intel_limit *limit; |
Ander Conselvan de Oliveira | 997c030 | 2016-03-21 18:00:12 +0200 | [diff] [blame] | 9556 | int refclk = 120000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9557 | |
Ander Conselvan de Oliveira | dd3cd74 | 2015-05-15 13:34:29 +0300 | [diff] [blame] | 9558 | memset(&crtc_state->dpll_hw_state, 0, |
| 9559 | sizeof(crtc_state->dpll_hw_state)); |
| 9560 | |
Ander Conselvan de Oliveira | ded220e | 2016-03-21 18:00:09 +0200 | [diff] [blame] | 9561 | crtc->lowfreq_avail = false; |
| 9562 | |
| 9563 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
| 9564 | if (!crtc_state->has_pch_encoder) |
| 9565 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9566 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 9567 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Ander Conselvan de Oliveira | 997c030 | 2016-03-21 18:00:12 +0200 | [diff] [blame] | 9568 | if (intel_panel_use_ssc(dev_priv)) { |
| 9569 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
| 9570 | dev_priv->vbt.lvds_ssc_freq); |
| 9571 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 9572 | } |
| 9573 | |
| 9574 | if (intel_is_dual_link_lvds(dev)) { |
| 9575 | if (refclk == 100000) |
| 9576 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 9577 | else |
| 9578 | limit = &intel_limits_ironlake_dual_lvds; |
| 9579 | } else { |
| 9580 | if (refclk == 100000) |
| 9581 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 9582 | else |
| 9583 | limit = &intel_limits_ironlake_single_lvds; |
| 9584 | } |
| 9585 | } else { |
| 9586 | limit = &intel_limits_ironlake_dac; |
| 9587 | } |
| 9588 | |
Ander Conselvan de Oliveira | 364ee29 | 2016-03-21 18:00:10 +0200 | [diff] [blame] | 9589 | if (!crtc_state->clock_set && |
Ander Conselvan de Oliveira | 997c030 | 2016-03-21 18:00:12 +0200 | [diff] [blame] | 9590 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9591 | refclk, NULL, &crtc_state->dpll)) { |
Ander Conselvan de Oliveira | 364ee29 | 2016-03-21 18:00:10 +0200 | [diff] [blame] | 9592 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 9593 | return -EINVAL; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 9594 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9595 | |
Ander Conselvan de Oliveira | b75ca6f | 2016-03-21 18:00:11 +0200 | [diff] [blame] | 9596 | ironlake_compute_dpll(crtc, crtc_state, |
| 9597 | has_reduced_clock ? &reduced_clock : NULL); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9598 | |
Ander Conselvan de Oliveira | ded220e | 2016-03-21 18:00:09 +0200 | [diff] [blame] | 9599 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
| 9600 | if (pll == NULL) { |
| 9601 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
| 9602 | pipe_name(crtc->pipe)); |
| 9603 | return -EINVAL; |
Ander Conselvan de Oliveira | 3fb3770 | 2014-10-29 11:32:35 +0200 | [diff] [blame] | 9604 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9605 | |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 9606 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Ander Conselvan de Oliveira | ded220e | 2016-03-21 18:00:09 +0200 | [diff] [blame] | 9607 | has_reduced_clock) |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 9608 | crtc->lowfreq_avail = true; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 9609 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 9610 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9611 | } |
| 9612 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9613 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
| 9614 | struct intel_link_m_n *m_n) |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9615 | { |
| 9616 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9617 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9618 | enum pipe pipe = crtc->pipe; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9619 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9620 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
| 9621 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
| 9622 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 9623 | & ~TU_SIZE_MASK; |
| 9624 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
| 9625 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 9626 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9627 | } |
| 9628 | |
| 9629 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
| 9630 | enum transcoder transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9631 | struct intel_link_m_n *m_n, |
| 9632 | struct intel_link_m_n *m2_n2) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9633 | { |
| 9634 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9635 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9636 | enum pipe pipe = crtc->pipe; |
| 9637 | |
| 9638 | if (INTEL_INFO(dev)->gen >= 5) { |
| 9639 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
| 9640 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
| 9641 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
| 9642 | & ~TU_SIZE_MASK; |
| 9643 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
| 9644 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
| 9645 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9646 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
| 9647 | * gen < 8) and if DRRS is supported (to make sure the |
| 9648 | * registers are not unnecessarily read). |
| 9649 | */ |
| 9650 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9651 | crtc->config->has_drrs) { |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9652 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
| 9653 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); |
| 9654 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) |
| 9655 | & ~TU_SIZE_MASK; |
| 9656 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); |
| 9657 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) |
| 9658 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9659 | } |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9660 | } else { |
| 9661 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
| 9662 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
| 9663 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 9664 | & ~TU_SIZE_MASK; |
| 9665 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
| 9666 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 9667 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9668 | } |
| 9669 | } |
| 9670 | |
| 9671 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9672 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9673 | { |
Ander Conselvan de Oliveira | 681a850 | 2015-01-15 14:55:24 +0200 | [diff] [blame] | 9674 | if (pipe_config->has_pch_encoder) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9675 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
| 9676 | else |
| 9677 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9678 | &pipe_config->dp_m_n, |
| 9679 | &pipe_config->dp_m2_n2); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9680 | } |
| 9681 | |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9682 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9683 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9684 | { |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9685 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9686 | &pipe_config->fdi_m_n, NULL); |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9687 | } |
| 9688 | |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9689 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9690 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9691 | { |
| 9692 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9693 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 9694 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
| 9695 | uint32_t ps_ctrl = 0; |
| 9696 | int id = -1; |
| 9697 | int i; |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9698 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 9699 | /* find scaler attached to this pipe */ |
| 9700 | for (i = 0; i < crtc->num_scalers; i++) { |
| 9701 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); |
| 9702 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { |
| 9703 | id = i; |
| 9704 | pipe_config->pch_pfit.enabled = true; |
| 9705 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); |
| 9706 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); |
| 9707 | break; |
| 9708 | } |
| 9709 | } |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9710 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 9711 | scaler_state->scaler_id = id; |
| 9712 | if (id >= 0) { |
| 9713 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); |
| 9714 | } else { |
| 9715 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9716 | } |
| 9717 | } |
| 9718 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 9719 | static void |
| 9720 | skylake_get_initial_plane_config(struct intel_crtc *crtc, |
| 9721 | struct intel_initial_plane_config *plane_config) |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9722 | { |
| 9723 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9724 | struct drm_i915_private *dev_priv = to_i915(dev); |
Damien Lespiau | 40f4628 | 2015-02-27 11:15:21 +0000 | [diff] [blame] | 9725 | u32 val, base, offset, stride_mult, tiling; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9726 | int pipe = crtc->pipe; |
| 9727 | int fourcc, pixel_format; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 9728 | unsigned int aligned_height; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9729 | struct drm_framebuffer *fb; |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9730 | struct intel_framebuffer *intel_fb; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9731 | |
Damien Lespiau | d9806c9 | 2015-01-21 14:07:19 +0000 | [diff] [blame] | 9732 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9733 | if (!intel_fb) { |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9734 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 9735 | return; |
| 9736 | } |
| 9737 | |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9738 | fb = &intel_fb->base; |
| 9739 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9740 | val = I915_READ(PLANE_CTL(pipe, 0)); |
Damien Lespiau | 42a7b08 | 2015-02-05 19:35:13 +0000 | [diff] [blame] | 9741 | if (!(val & PLANE_CTL_ENABLE)) |
| 9742 | goto error; |
| 9743 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9744 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
| 9745 | fourcc = skl_format_to_fourcc(pixel_format, |
| 9746 | val & PLANE_CTL_ORDER_RGBX, |
| 9747 | val & PLANE_CTL_ALPHA_MASK); |
| 9748 | fb->pixel_format = fourcc; |
| 9749 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
| 9750 | |
Damien Lespiau | 40f4628 | 2015-02-27 11:15:21 +0000 | [diff] [blame] | 9751 | tiling = val & PLANE_CTL_TILED_MASK; |
| 9752 | switch (tiling) { |
| 9753 | case PLANE_CTL_TILED_LINEAR: |
| 9754 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; |
| 9755 | break; |
| 9756 | case PLANE_CTL_TILED_X: |
| 9757 | plane_config->tiling = I915_TILING_X; |
| 9758 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 9759 | break; |
| 9760 | case PLANE_CTL_TILED_Y: |
| 9761 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; |
| 9762 | break; |
| 9763 | case PLANE_CTL_TILED_YF: |
| 9764 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; |
| 9765 | break; |
| 9766 | default: |
| 9767 | MISSING_CASE(tiling); |
| 9768 | goto error; |
| 9769 | } |
| 9770 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9771 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
| 9772 | plane_config->base = base; |
| 9773 | |
| 9774 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); |
| 9775 | |
| 9776 | val = I915_READ(PLANE_SIZE(pipe, 0)); |
| 9777 | fb->height = ((val >> 16) & 0xfff) + 1; |
| 9778 | fb->width = ((val >> 0) & 0x1fff) + 1; |
| 9779 | |
| 9780 | val = I915_READ(PLANE_STRIDE(pipe, 0)); |
Ville Syrjälä | 7b49f94 | 2016-01-12 21:08:32 +0200 | [diff] [blame] | 9781 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
Damien Lespiau | 40f4628 | 2015-02-27 11:15:21 +0000 | [diff] [blame] | 9782 | fb->pixel_format); |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9783 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
| 9784 | |
| 9785 | aligned_height = intel_fb_align_height(dev, fb->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 9786 | fb->pixel_format, |
| 9787 | fb->modifier[0]); |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9788 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 9789 | plane_config->size = fb->pitches[0] * aligned_height; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9790 | |
| 9791 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 9792 | pipe_name(pipe), fb->width, fb->height, |
| 9793 | fb->bits_per_pixel, base, fb->pitches[0], |
| 9794 | plane_config->size); |
| 9795 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 9796 | plane_config->fb = intel_fb; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9797 | return; |
| 9798 | |
| 9799 | error: |
Matthew Auld | d1a3a03 | 2016-08-23 16:00:44 +0100 | [diff] [blame] | 9800 | kfree(intel_fb); |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9801 | } |
| 9802 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9803 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9804 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9805 | { |
| 9806 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9807 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9808 | uint32_t tmp; |
| 9809 | |
| 9810 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
| 9811 | |
| 9812 | if (tmp & PF_ENABLE) { |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 9813 | pipe_config->pch_pfit.enabled = true; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9814 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
| 9815 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
Daniel Vetter | cb8b2a3 | 2013-06-01 17:16:23 +0200 | [diff] [blame] | 9816 | |
| 9817 | /* We currently do not free assignements of panel fitters on |
| 9818 | * ivb/hsw (since we don't use the higher upscaling modes which |
| 9819 | * differentiates them) so just WARN about this case for now. */ |
| 9820 | if (IS_GEN7(dev)) { |
| 9821 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
| 9822 | PF_PIPE_SEL_IVB(crtc->pipe)); |
| 9823 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9824 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9825 | } |
| 9826 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 9827 | static void |
| 9828 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, |
| 9829 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9830 | { |
| 9831 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9832 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9833 | u32 val, base, offset; |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9834 | int pipe = crtc->pipe; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9835 | int fourcc, pixel_format; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 9836 | unsigned int aligned_height; |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9837 | struct drm_framebuffer *fb; |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9838 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9839 | |
Damien Lespiau | 42a7b08 | 2015-02-05 19:35:13 +0000 | [diff] [blame] | 9840 | val = I915_READ(DSPCNTR(pipe)); |
| 9841 | if (!(val & DISPLAY_PLANE_ENABLE)) |
| 9842 | return; |
| 9843 | |
Damien Lespiau | d9806c9 | 2015-01-21 14:07:19 +0000 | [diff] [blame] | 9844 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9845 | if (!intel_fb) { |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9846 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 9847 | return; |
| 9848 | } |
| 9849 | |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9850 | fb = &intel_fb->base; |
| 9851 | |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 9852 | if (INTEL_INFO(dev)->gen >= 4) { |
| 9853 | if (val & DISPPLANE_TILED) { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 9854 | plane_config->tiling = I915_TILING_X; |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 9855 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 9856 | } |
| 9857 | } |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9858 | |
| 9859 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
Damien Lespiau | b35d63f | 2015-01-20 12:51:50 +0000 | [diff] [blame] | 9860 | fourcc = i9xx_format_to_fourcc(pixel_format); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9861 | fb->pixel_format = fourcc; |
| 9862 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9863 | |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9864 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9865 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9866 | offset = I915_READ(DSPOFFSET(pipe)); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9867 | } else { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 9868 | if (plane_config->tiling) |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9869 | offset = I915_READ(DSPTILEOFF(pipe)); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9870 | else |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9871 | offset = I915_READ(DSPLINOFF(pipe)); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9872 | } |
| 9873 | plane_config->base = base; |
| 9874 | |
| 9875 | val = I915_READ(PIPESRC(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9876 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 9877 | fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9878 | |
| 9879 | val = I915_READ(DSPSTRIDE(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9880 | fb->pitches[0] = val & 0xffffffc0; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9881 | |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9882 | aligned_height = intel_fb_align_height(dev, fb->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 9883 | fb->pixel_format, |
| 9884 | fb->modifier[0]); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9885 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 9886 | plane_config->size = fb->pitches[0] * aligned_height; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9887 | |
Damien Lespiau | 2844a92 | 2015-01-20 12:51:48 +0000 | [diff] [blame] | 9888 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 9889 | pipe_name(pipe), fb->width, fb->height, |
| 9890 | fb->bits_per_pixel, base, fb->pitches[0], |
| 9891 | plane_config->size); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9892 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 9893 | plane_config->fb = intel_fb; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9894 | } |
| 9895 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9896 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9897 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9898 | { |
| 9899 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 9900 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 9901 | enum intel_display_power_domain power_domain; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9902 | uint32_t tmp; |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 9903 | bool ret; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9904 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 9905 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
| 9906 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Paulo Zanoni | 930e8c9 | 2014-07-04 13:38:34 -0300 | [diff] [blame] | 9907 | return false; |
| 9908 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 9909 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 9910 | pipe_config->shared_dpll = NULL; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 9911 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 9912 | ret = false; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9913 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 9914 | if (!(tmp & PIPECONF_ENABLE)) |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 9915 | goto out; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9916 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 9917 | switch (tmp & PIPECONF_BPC_MASK) { |
| 9918 | case PIPECONF_6BPC: |
| 9919 | pipe_config->pipe_bpp = 18; |
| 9920 | break; |
| 9921 | case PIPECONF_8BPC: |
| 9922 | pipe_config->pipe_bpp = 24; |
| 9923 | break; |
| 9924 | case PIPECONF_10BPC: |
| 9925 | pipe_config->pipe_bpp = 30; |
| 9926 | break; |
| 9927 | case PIPECONF_12BPC: |
| 9928 | pipe_config->pipe_bpp = 36; |
| 9929 | break; |
| 9930 | default: |
| 9931 | break; |
| 9932 | } |
| 9933 | |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 9934 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
| 9935 | pipe_config->limited_color_range = true; |
| 9936 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 9937 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9938 | struct intel_shared_dpll *pll; |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 9939 | enum intel_dpll_id pll_id; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9940 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 9941 | pipe_config->has_pch_encoder = true; |
| 9942 | |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 9943 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
| 9944 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 9945 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9946 | |
| 9947 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9948 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 9949 | if (HAS_PCH_IBX(dev_priv)) { |
Imre Deak | d9a7bc6 | 2016-05-12 16:18:50 +0300 | [diff] [blame] | 9950 | /* |
| 9951 | * The pipe->pch transcoder and pch transcoder->pll |
| 9952 | * mapping is fixed. |
| 9953 | */ |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 9954 | pll_id = (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9955 | } else { |
| 9956 | tmp = I915_READ(PCH_DPLL_SEL); |
| 9957 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 9958 | pll_id = DPLL_ID_PCH_PLL_B; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9959 | else |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 9960 | pll_id= DPLL_ID_PCH_PLL_A; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9961 | } |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9962 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 9963 | pipe_config->shared_dpll = |
| 9964 | intel_get_shared_dpll_by_id(dev_priv, pll_id); |
| 9965 | pll = pipe_config->shared_dpll; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9966 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 9967 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
| 9968 | &pipe_config->dpll_hw_state)); |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 9969 | |
| 9970 | tmp = pipe_config->dpll_hw_state.dpll; |
| 9971 | pipe_config->pixel_multiplier = |
| 9972 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
| 9973 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 9974 | |
| 9975 | ironlake_pch_clock_get(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9976 | } else { |
| 9977 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 9978 | } |
| 9979 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9980 | intel_get_pipe_timings(crtc, pipe_config); |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 9981 | intel_get_pipe_src_size(crtc, pipe_config); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9982 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9983 | ironlake_get_pfit_config(crtc, pipe_config); |
| 9984 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 9985 | ret = true; |
| 9986 | |
| 9987 | out: |
| 9988 | intel_display_power_put(dev_priv, power_domain); |
| 9989 | |
| 9990 | return ret; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9991 | } |
| 9992 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9993 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
| 9994 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 9995 | struct drm_device *dev = &dev_priv->drm; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9996 | struct intel_crtc *crtc; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9997 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 9998 | for_each_intel_crtc(dev, crtc) |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9999 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10000 | pipe_name(crtc->pipe)); |
| 10001 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10002 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
| 10003 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
Ville Syrjälä | 01403de | 2015-09-18 20:03:33 +0300 | [diff] [blame] | 10004 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
| 10005 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 10006 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10007 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10008 | "CPU PWM1 enabled\n"); |
Paulo Zanoni | c5107b8 | 2014-07-04 11:50:30 -0300 | [diff] [blame] | 10009 | if (IS_HASWELL(dev)) |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10010 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
Paulo Zanoni | c5107b8 | 2014-07-04 11:50:30 -0300 | [diff] [blame] | 10011 | "CPU PWM2 enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10012 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10013 | "PCH PWM1 enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10014 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10015 | "Utility pin enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10016 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10017 | |
Paulo Zanoni | 9926ada | 2014-04-01 19:39:47 -0300 | [diff] [blame] | 10018 | /* |
| 10019 | * In theory we can still leave IRQs enabled, as long as only the HPD |
| 10020 | * interrupts remain enabled. We used to check for that, but since it's |
| 10021 | * gen-specific and since we only disable LCPLL after we fully disable |
| 10022 | * the interrupts, the check below should be enough. |
| 10023 | */ |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 10024 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10025 | } |
| 10026 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 10027 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
| 10028 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 10029 | struct drm_device *dev = &dev_priv->drm; |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 10030 | |
| 10031 | if (IS_HASWELL(dev)) |
| 10032 | return I915_READ(D_COMP_HSW); |
| 10033 | else |
| 10034 | return I915_READ(D_COMP_BDW); |
| 10035 | } |
| 10036 | |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 10037 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
| 10038 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 10039 | struct drm_device *dev = &dev_priv->drm; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 10040 | |
| 10041 | if (IS_HASWELL(dev)) { |
| 10042 | mutex_lock(&dev_priv->rps.hw_lock); |
| 10043 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
| 10044 | val)) |
Chris Wilson | 79cf219 | 2016-08-24 11:16:07 +0100 | [diff] [blame] | 10045 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 10046 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 10047 | } else { |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 10048 | I915_WRITE(D_COMP_BDW, val); |
| 10049 | POSTING_READ(D_COMP_BDW); |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 10050 | } |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10051 | } |
| 10052 | |
| 10053 | /* |
| 10054 | * This function implements pieces of two sequences from BSpec: |
| 10055 | * - Sequence for display software to disable LCPLL |
| 10056 | * - Sequence for display software to allow package C8+ |
| 10057 | * The steps implemented here are just the steps that actually touch the LCPLL |
| 10058 | * register. Callers should take care of disabling all the display engine |
| 10059 | * functions, doing the mode unset, fixing interrupts, etc. |
| 10060 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 10061 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
| 10062 | bool switch_to_fclk, bool allow_power_down) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10063 | { |
| 10064 | uint32_t val; |
| 10065 | |
| 10066 | assert_can_disable_lcpll(dev_priv); |
| 10067 | |
| 10068 | val = I915_READ(LCPLL_CTL); |
| 10069 | |
| 10070 | if (switch_to_fclk) { |
| 10071 | val |= LCPLL_CD_SOURCE_FCLK; |
| 10072 | I915_WRITE(LCPLL_CTL, val); |
| 10073 | |
Imre Deak | f53dd63 | 2016-06-28 13:37:32 +0300 | [diff] [blame] | 10074 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
| 10075 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10076 | DRM_ERROR("Switching to FCLK failed\n"); |
| 10077 | |
| 10078 | val = I915_READ(LCPLL_CTL); |
| 10079 | } |
| 10080 | |
| 10081 | val |= LCPLL_PLL_DISABLE; |
| 10082 | I915_WRITE(LCPLL_CTL, val); |
| 10083 | POSTING_READ(LCPLL_CTL); |
| 10084 | |
Chris Wilson | 24d8441 | 2016-06-30 15:33:07 +0100 | [diff] [blame] | 10085 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10086 | DRM_ERROR("LCPLL still locked\n"); |
| 10087 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 10088 | val = hsw_read_dcomp(dev_priv); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10089 | val |= D_COMP_COMP_DISABLE; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 10090 | hsw_write_dcomp(dev_priv, val); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10091 | ndelay(100); |
| 10092 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 10093 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
| 10094 | 1)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10095 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
| 10096 | |
| 10097 | if (allow_power_down) { |
| 10098 | val = I915_READ(LCPLL_CTL); |
| 10099 | val |= LCPLL_POWER_DOWN_ALLOW; |
| 10100 | I915_WRITE(LCPLL_CTL, val); |
| 10101 | POSTING_READ(LCPLL_CTL); |
| 10102 | } |
| 10103 | } |
| 10104 | |
| 10105 | /* |
| 10106 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
| 10107 | * source. |
| 10108 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 10109 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10110 | { |
| 10111 | uint32_t val; |
| 10112 | |
| 10113 | val = I915_READ(LCPLL_CTL); |
| 10114 | |
| 10115 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
| 10116 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
| 10117 | return; |
| 10118 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 10119 | /* |
| 10120 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
| 10121 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 10122 | */ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 10123 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 10124 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10125 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
| 10126 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
| 10127 | I915_WRITE(LCPLL_CTL, val); |
Daniel Vetter | 35d8f2e | 2013-08-21 23:38:08 +0200 | [diff] [blame] | 10128 | POSTING_READ(LCPLL_CTL); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10129 | } |
| 10130 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 10131 | val = hsw_read_dcomp(dev_priv); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10132 | val |= D_COMP_COMP_FORCE; |
| 10133 | val &= ~D_COMP_COMP_DISABLE; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 10134 | hsw_write_dcomp(dev_priv, val); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10135 | |
| 10136 | val = I915_READ(LCPLL_CTL); |
| 10137 | val &= ~LCPLL_PLL_DISABLE; |
| 10138 | I915_WRITE(LCPLL_CTL, val); |
| 10139 | |
Chris Wilson | 93220c0 | 2016-06-30 15:33:08 +0100 | [diff] [blame] | 10140 | if (intel_wait_for_register(dev_priv, |
| 10141 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, |
| 10142 | 5)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10143 | DRM_ERROR("LCPLL not locked yet\n"); |
| 10144 | |
| 10145 | if (val & LCPLL_CD_SOURCE_FCLK) { |
| 10146 | val = I915_READ(LCPLL_CTL); |
| 10147 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 10148 | I915_WRITE(LCPLL_CTL, val); |
| 10149 | |
Imre Deak | f53dd63 | 2016-06-28 13:37:32 +0300 | [diff] [blame] | 10150 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
| 10151 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10152 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 10153 | } |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 10154 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 10155 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 10156 | intel_update_cdclk(&dev_priv->drm); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 10157 | } |
| 10158 | |
Paulo Zanoni | 765dab67 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 10159 | /* |
| 10160 | * Package states C8 and deeper are really deep PC states that can only be |
| 10161 | * reached when all the devices on the system allow it, so even if the graphics |
| 10162 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 10163 | * states. Our driver only allows PC8+ when going into runtime PM. |
| 10164 | * |
| 10165 | * The requirements for PC8+ are that all the outputs are disabled, the power |
| 10166 | * well is disabled and most interrupts are disabled, and these are also |
| 10167 | * requirements for runtime PM. When these conditions are met, we manually do |
| 10168 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
| 10169 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
| 10170 | * hang the machine. |
| 10171 | * |
| 10172 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 10173 | * the state of some registers, so when we come back from PC8+ we need to |
| 10174 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 10175 | * need to take care of the registers kept by RC6. Notice that this happens even |
| 10176 | * if we don't put the device in PCI D3 state (which is what currently happens |
| 10177 | * because of the runtime PM support). |
| 10178 | * |
| 10179 | * For more, read "Display Sequences for Package C8" on the hardware |
| 10180 | * documentation. |
| 10181 | */ |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 10182 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10183 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 10184 | struct drm_device *dev = &dev_priv->drm; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10185 | uint32_t val; |
| 10186 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10187 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
| 10188 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 10189 | if (HAS_PCH_LPT_LP(dev)) { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10190 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 10191 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 10192 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 10193 | } |
| 10194 | |
| 10195 | lpt_disable_clkout_dp(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10196 | hsw_disable_lcpll(dev_priv, true, true); |
| 10197 | } |
| 10198 | |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 10199 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10200 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 10201 | struct drm_device *dev = &dev_priv->drm; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10202 | uint32_t val; |
| 10203 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10204 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
| 10205 | |
| 10206 | hsw_restore_lcpll(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10207 | lpt_init_pch_refclk(dev); |
| 10208 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 10209 | if (HAS_PCH_LPT_LP(dev)) { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10210 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 10211 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
| 10212 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 10213 | } |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10214 | } |
| 10215 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 10216 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 10217 | { |
Ander Conselvan de Oliveira | a821fc4 | 2015-04-21 17:13:23 +0300 | [diff] [blame] | 10218 | struct drm_device *dev = old_state->dev; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 10219 | struct intel_atomic_state *old_intel_state = |
| 10220 | to_intel_atomic_state(old_state); |
| 10221 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 10222 | |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 10223 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 10224 | } |
| 10225 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10226 | /* compute the max rate for new configuration */ |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10227 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10228 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10229 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10230 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10231 | struct drm_crtc *crtc; |
| 10232 | struct drm_crtc_state *cstate; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10233 | struct intel_crtc_state *crtc_state; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10234 | unsigned max_pixel_rate = 0, i; |
| 10235 | enum pipe pipe; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10236 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10237 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 10238 | sizeof(intel_state->min_pixclk)); |
| 10239 | |
| 10240 | for_each_crtc_in_state(state, crtc, cstate, i) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10241 | int pixel_rate; |
| 10242 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10243 | crtc_state = to_intel_crtc_state(cstate); |
| 10244 | if (!crtc_state->base.enable) { |
| 10245 | intel_state->min_pixclk[i] = 0; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10246 | continue; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10247 | } |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10248 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10249 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10250 | |
| 10251 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10252 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10253 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
| 10254 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10255 | intel_state->min_pixclk[i] = pixel_rate; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10256 | } |
| 10257 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 10258 | for_each_pipe(dev_priv, pipe) |
| 10259 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); |
| 10260 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10261 | return max_pixel_rate; |
| 10262 | } |
| 10263 | |
| 10264 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) |
| 10265 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10266 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10267 | uint32_t val, data; |
| 10268 | int ret; |
| 10269 | |
| 10270 | if (WARN((I915_READ(LCPLL_CTL) & |
| 10271 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | |
| 10272 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | |
| 10273 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | |
| 10274 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, |
| 10275 | "trying to change cdclk frequency with cdclk not enabled\n")) |
| 10276 | return; |
| 10277 | |
| 10278 | mutex_lock(&dev_priv->rps.hw_lock); |
| 10279 | ret = sandybridge_pcode_write(dev_priv, |
| 10280 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); |
| 10281 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 10282 | if (ret) { |
| 10283 | DRM_ERROR("failed to inform pcode about cdclk change\n"); |
| 10284 | return; |
| 10285 | } |
| 10286 | |
| 10287 | val = I915_READ(LCPLL_CTL); |
| 10288 | val |= LCPLL_CD_SOURCE_FCLK; |
| 10289 | I915_WRITE(LCPLL_CTL, val); |
| 10290 | |
Tvrtko Ursulin | 5ba0017 | 2016-03-03 14:36:45 +0000 | [diff] [blame] | 10291 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
| 10292 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10293 | DRM_ERROR("Switching to FCLK failed\n"); |
| 10294 | |
| 10295 | val = I915_READ(LCPLL_CTL); |
| 10296 | val &= ~LCPLL_CLK_FREQ_MASK; |
| 10297 | |
| 10298 | switch (cdclk) { |
| 10299 | case 450000: |
| 10300 | val |= LCPLL_CLK_FREQ_450; |
| 10301 | data = 0; |
| 10302 | break; |
| 10303 | case 540000: |
| 10304 | val |= LCPLL_CLK_FREQ_54O_BDW; |
| 10305 | data = 1; |
| 10306 | break; |
| 10307 | case 337500: |
| 10308 | val |= LCPLL_CLK_FREQ_337_5_BDW; |
| 10309 | data = 2; |
| 10310 | break; |
| 10311 | case 675000: |
| 10312 | val |= LCPLL_CLK_FREQ_675_BDW; |
| 10313 | data = 3; |
| 10314 | break; |
| 10315 | default: |
| 10316 | WARN(1, "invalid cdclk frequency\n"); |
| 10317 | return; |
| 10318 | } |
| 10319 | |
| 10320 | I915_WRITE(LCPLL_CTL, val); |
| 10321 | |
| 10322 | val = I915_READ(LCPLL_CTL); |
| 10323 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 10324 | I915_WRITE(LCPLL_CTL, val); |
| 10325 | |
Tvrtko Ursulin | 5ba0017 | 2016-03-03 14:36:45 +0000 | [diff] [blame] | 10326 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
| 10327 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10328 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 10329 | |
| 10330 | mutex_lock(&dev_priv->rps.hw_lock); |
| 10331 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); |
| 10332 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 10333 | |
Ville Syrjälä | 7f1052a | 2016-04-26 19:46:32 +0300 | [diff] [blame] | 10334 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
| 10335 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10336 | intel_update_cdclk(dev); |
| 10337 | |
| 10338 | WARN(cdclk != dev_priv->cdclk_freq, |
| 10339 | "cdclk requested %d kHz but got %d kHz\n", |
| 10340 | cdclk, dev_priv->cdclk_freq); |
| 10341 | } |
| 10342 | |
Ville Syrjälä | 587c791 | 2016-05-11 22:44:41 +0300 | [diff] [blame] | 10343 | static int broadwell_calc_cdclk(int max_pixclk) |
| 10344 | { |
| 10345 | if (max_pixclk > 540000) |
| 10346 | return 675000; |
| 10347 | else if (max_pixclk > 450000) |
| 10348 | return 540000; |
| 10349 | else if (max_pixclk > 337500) |
| 10350 | return 450000; |
| 10351 | else |
| 10352 | return 337500; |
| 10353 | } |
| 10354 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10355 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10356 | { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10357 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 10358 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10359 | int max_pixclk = ilk_max_pixel_rate(state); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10360 | int cdclk; |
| 10361 | |
| 10362 | /* |
| 10363 | * FIXME should also account for plane ratio |
| 10364 | * once 64bpp pixel formats are supported. |
| 10365 | */ |
Ville Syrjälä | 587c791 | 2016-05-11 22:44:41 +0300 | [diff] [blame] | 10366 | cdclk = broadwell_calc_cdclk(max_pixclk); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10367 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10368 | if (cdclk > dev_priv->max_cdclk_freq) { |
Maarten Lankhorst | 63ba534 | 2015-11-24 11:29:03 +0100 | [diff] [blame] | 10369 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
| 10370 | cdclk, dev_priv->max_cdclk_freq); |
| 10371 | return -EINVAL; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10372 | } |
| 10373 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 10374 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 10375 | if (!intel_state->active_crtcs) |
Ville Syrjälä | 587c791 | 2016-05-11 22:44:41 +0300 | [diff] [blame] | 10376 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10377 | |
| 10378 | return 0; |
| 10379 | } |
| 10380 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10381 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10382 | { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10383 | struct drm_device *dev = old_state->dev; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 10384 | struct intel_atomic_state *old_intel_state = |
| 10385 | to_intel_atomic_state(old_state); |
| 10386 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10387 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 10388 | broadwell_set_cdclk(dev, req_cdclk); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 10389 | } |
| 10390 | |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 10391 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 10392 | { |
| 10393 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 10394 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 10395 | const int max_pixclk = ilk_max_pixel_rate(state); |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 10396 | int vco = intel_state->cdclk_pll_vco; |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 10397 | int cdclk; |
| 10398 | |
| 10399 | /* |
| 10400 | * FIXME should also account for plane ratio |
| 10401 | * once 64bpp pixel formats are supported. |
| 10402 | */ |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 10403 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 10404 | |
| 10405 | /* |
| 10406 | * FIXME move the cdclk caclulation to |
| 10407 | * compute_config() so we can fail gracegully. |
| 10408 | */ |
| 10409 | if (cdclk > dev_priv->max_cdclk_freq) { |
| 10410 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
| 10411 | cdclk, dev_priv->max_cdclk_freq); |
| 10412 | cdclk = dev_priv->max_cdclk_freq; |
| 10413 | } |
| 10414 | |
| 10415 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 10416 | if (!intel_state->active_crtcs) |
Ville Syrjälä | a8ca493 | 2016-05-13 23:41:23 +0300 | [diff] [blame] | 10417 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 10418 | |
| 10419 | return 0; |
| 10420 | } |
| 10421 | |
| 10422 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 10423 | { |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 10424 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
| 10425 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); |
| 10426 | unsigned int req_cdclk = intel_state->dev_cdclk; |
| 10427 | unsigned int req_vco = intel_state->cdclk_pll_vco; |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 10428 | |
Ville Syrjälä | 1cd593e | 2016-05-13 23:41:26 +0300 | [diff] [blame] | 10429 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 10430 | } |
| 10431 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 10432 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
| 10433 | struct intel_crtc_state *crtc_state) |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 10434 | { |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 10435 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
Mika Kahola | af3997b | 2016-02-05 13:29:28 +0200 | [diff] [blame] | 10436 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
| 10437 | return -EINVAL; |
| 10438 | } |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 10439 | |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 10440 | crtc->lowfreq_avail = false; |
Daniel Vetter | 644cef3 | 2014-04-24 23:55:07 +0200 | [diff] [blame] | 10441 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 10442 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10443 | } |
| 10444 | |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10445 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 10446 | enum port port, |
| 10447 | struct intel_crtc_state *pipe_config) |
| 10448 | { |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10449 | enum intel_dpll_id id; |
| 10450 | |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10451 | switch (port) { |
| 10452 | case PORT_A: |
Imre Deak | 08250c4 | 2016-03-14 19:55:34 +0200 | [diff] [blame] | 10453 | id = DPLL_ID_SKL_DPLL0; |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10454 | break; |
| 10455 | case PORT_B: |
Imre Deak | 08250c4 | 2016-03-14 19:55:34 +0200 | [diff] [blame] | 10456 | id = DPLL_ID_SKL_DPLL1; |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10457 | break; |
| 10458 | case PORT_C: |
Imre Deak | 08250c4 | 2016-03-14 19:55:34 +0200 | [diff] [blame] | 10459 | id = DPLL_ID_SKL_DPLL2; |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10460 | break; |
| 10461 | default: |
| 10462 | DRM_ERROR("Incorrect port type\n"); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10463 | return; |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10464 | } |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10465 | |
| 10466 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10467 | } |
| 10468 | |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10469 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 10470 | enum port port, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10471 | struct intel_crtc_state *pipe_config) |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10472 | { |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10473 | enum intel_dpll_id id; |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 10474 | u32 temp; |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10475 | |
| 10476 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 10477 | id = temp >> (port * 3 + 1); |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10478 | |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 10479 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10480 | return; |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10481 | |
| 10482 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10483 | } |
| 10484 | |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10485 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 10486 | enum port port, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10487 | struct intel_crtc_state *pipe_config) |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10488 | { |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10489 | enum intel_dpll_id id; |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 10490 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10491 | |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 10492 | switch (ddi_pll_sel) { |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10493 | case PORT_CLK_SEL_WRPLL1: |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10494 | id = DPLL_ID_WRPLL1; |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10495 | break; |
| 10496 | case PORT_CLK_SEL_WRPLL2: |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10497 | id = DPLL_ID_WRPLL2; |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10498 | break; |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 10499 | case PORT_CLK_SEL_SPLL: |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10500 | id = DPLL_ID_SPLL; |
Ville Syrjälä | 79bd23d | 2015-12-01 23:32:07 +0200 | [diff] [blame] | 10501 | break; |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 10502 | case PORT_CLK_SEL_LCPLL_810: |
| 10503 | id = DPLL_ID_LCPLL_810; |
| 10504 | break; |
| 10505 | case PORT_CLK_SEL_LCPLL_1350: |
| 10506 | id = DPLL_ID_LCPLL_1350; |
| 10507 | break; |
| 10508 | case PORT_CLK_SEL_LCPLL_2700: |
| 10509 | id = DPLL_ID_LCPLL_2700; |
| 10510 | break; |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10511 | default: |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 10512 | MISSING_CASE(ddi_pll_sel); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10513 | /* fall through */ |
| 10514 | case PORT_CLK_SEL_NONE: |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10515 | return; |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10516 | } |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10517 | |
| 10518 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 10519 | } |
| 10520 | |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10521 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
| 10522 | struct intel_crtc_state *pipe_config, |
| 10523 | unsigned long *power_domain_mask) |
| 10524 | { |
| 10525 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10526 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10527 | enum intel_display_power_domain power_domain; |
| 10528 | u32 tmp; |
| 10529 | |
Imre Deak | d9a7bc6 | 2016-05-12 16:18:50 +0300 | [diff] [blame] | 10530 | /* |
| 10531 | * The pipe->transcoder mapping is fixed with the exception of the eDP |
| 10532 | * transcoder handled below. |
| 10533 | */ |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10534 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 10535 | |
| 10536 | /* |
| 10537 | * XXX: Do intel_display_power_get_if_enabled before reading this (for |
| 10538 | * consistency and less surprising code; it's in always on power). |
| 10539 | */ |
| 10540 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
| 10541 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
| 10542 | enum pipe trans_edp_pipe; |
| 10543 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 10544 | default: |
| 10545 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
| 10546 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 10547 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 10548 | trans_edp_pipe = PIPE_A; |
| 10549 | break; |
| 10550 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 10551 | trans_edp_pipe = PIPE_B; |
| 10552 | break; |
| 10553 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 10554 | trans_edp_pipe = PIPE_C; |
| 10555 | break; |
| 10556 | } |
| 10557 | |
| 10558 | if (trans_edp_pipe == crtc->pipe) |
| 10559 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 10560 | } |
| 10561 | |
| 10562 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
| 10563 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
| 10564 | return false; |
| 10565 | *power_domain_mask |= BIT(power_domain); |
| 10566 | |
| 10567 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
| 10568 | |
| 10569 | return tmp & PIPECONF_ENABLE; |
| 10570 | } |
| 10571 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10572 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
| 10573 | struct intel_crtc_state *pipe_config, |
| 10574 | unsigned long *power_domain_mask) |
| 10575 | { |
| 10576 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10577 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10578 | enum intel_display_power_domain power_domain; |
| 10579 | enum port port; |
| 10580 | enum transcoder cpu_transcoder; |
| 10581 | u32 tmp; |
| 10582 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10583 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
| 10584 | if (port == PORT_A) |
| 10585 | cpu_transcoder = TRANSCODER_DSI_A; |
| 10586 | else |
| 10587 | cpu_transcoder = TRANSCODER_DSI_C; |
| 10588 | |
| 10589 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
| 10590 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
| 10591 | continue; |
| 10592 | *power_domain_mask |= BIT(power_domain); |
| 10593 | |
Imre Deak | db18b6a | 2016-03-24 12:41:40 +0200 | [diff] [blame] | 10594 | /* |
| 10595 | * The PLL needs to be enabled with a valid divider |
| 10596 | * configuration, otherwise accessing DSI registers will hang |
| 10597 | * the machine. See BSpec North Display Engine |
| 10598 | * registers/MIPI[BXT]. We can break out here early, since we |
| 10599 | * need the same DSI PLL to be enabled for both DSI ports. |
| 10600 | */ |
| 10601 | if (!intel_dsi_pll_is_enabled(dev_priv)) |
| 10602 | break; |
| 10603 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10604 | /* XXX: this works for video mode only */ |
| 10605 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
| 10606 | if (!(tmp & DPI_ENABLE)) |
| 10607 | continue; |
| 10608 | |
| 10609 | tmp = I915_READ(MIPI_CTRL(port)); |
| 10610 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) |
| 10611 | continue; |
| 10612 | |
| 10613 | pipe_config->cpu_transcoder = cpu_transcoder; |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10614 | break; |
| 10615 | } |
| 10616 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 10617 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10618 | } |
| 10619 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10620 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10621 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10622 | { |
| 10623 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10624 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 10625 | struct intel_shared_dpll *pll; |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10626 | enum port port; |
| 10627 | uint32_t tmp; |
| 10628 | |
| 10629 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
| 10630 | |
| 10631 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
| 10632 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 10633 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10634 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 10635 | else if (IS_BROXTON(dev)) |
| 10636 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 10637 | else |
| 10638 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 10639 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10640 | pll = pipe_config->shared_dpll; |
| 10641 | if (pll) { |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 10642 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
| 10643 | &pipe_config->dpll_hw_state)); |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 10644 | } |
| 10645 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10646 | /* |
| 10647 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
| 10648 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
| 10649 | * the PCH transcoder is on. |
| 10650 | */ |
Damien Lespiau | ca37045 | 2013-12-03 13:56:24 +0000 | [diff] [blame] | 10651 | if (INTEL_INFO(dev)->gen < 9 && |
| 10652 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10653 | pipe_config->has_pch_encoder = true; |
| 10654 | |
| 10655 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 10656 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 10657 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
| 10658 | |
| 10659 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
| 10660 | } |
| 10661 | } |
| 10662 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10663 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10664 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10665 | { |
| 10666 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10667 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 10668 | enum intel_display_power_domain power_domain; |
| 10669 | unsigned long power_domain_mask; |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10670 | bool active; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10671 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 10672 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
| 10673 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 10674 | return false; |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 10675 | power_domain_mask = BIT(power_domain); |
| 10676 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 10677 | pipe_config->shared_dpll = NULL; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 10678 | |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10679 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 10680 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 10681 | if (IS_BROXTON(dev_priv) && |
| 10682 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
| 10683 | WARN_ON(active); |
| 10684 | active = true; |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10685 | } |
| 10686 | |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10687 | if (!active) |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 10688 | goto out; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10689 | |
Ville Syrjälä | d7edc4e | 2016-06-22 21:57:07 +0300 | [diff] [blame] | 10690 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10691 | haswell_get_ddi_port_state(crtc, pipe_config); |
| 10692 | intel_get_pipe_timings(crtc, pipe_config); |
| 10693 | } |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 10694 | |
Jani Nikula | bc58be6 | 2016-03-18 17:05:39 +0200 | [diff] [blame] | 10695 | intel_get_pipe_src_size(crtc, pipe_config); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10696 | |
Lionel Landwerlin | 05dc698 | 2016-03-16 10:57:15 +0000 | [diff] [blame] | 10697 | pipe_config->gamma_mode = |
| 10698 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; |
| 10699 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 10700 | if (INTEL_INFO(dev)->gen >= 9) { |
| 10701 | skl_init_scalers(dev, crtc, pipe_config); |
| 10702 | } |
| 10703 | |
Chandra Konduru | af99ced | 2015-05-11 14:35:47 -0700 | [diff] [blame] | 10704 | if (INTEL_INFO(dev)->gen >= 9) { |
| 10705 | pipe_config->scaler_state.scaler_id = -1; |
| 10706 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |
| 10707 | } |
| 10708 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 10709 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
| 10710 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { |
| 10711 | power_domain_mask |= BIT(power_domain); |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 10712 | if (INTEL_INFO(dev)->gen >= 9) |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 10713 | skylake_get_pfit_config(crtc, pipe_config); |
Jesse Barnes | ff6d9f5 | 2015-01-21 17:19:54 -0800 | [diff] [blame] | 10714 | else |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 10715 | ironlake_get_pfit_config(crtc, pipe_config); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 10716 | } |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 10717 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 10718 | if (IS_HASWELL(dev)) |
| 10719 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
| 10720 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 10721 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 10722 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
| 10723 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
Clint Taylor | ebb69c9 | 2014-09-30 10:30:22 -0700 | [diff] [blame] | 10724 | pipe_config->pixel_multiplier = |
| 10725 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; |
| 10726 | } else { |
| 10727 | pipe_config->pixel_multiplier = 1; |
| 10728 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 10729 | |
Imre Deak | 1729050 | 2016-02-12 18:55:11 +0200 | [diff] [blame] | 10730 | out: |
| 10731 | for_each_power_domain(power_domain, power_domain_mask) |
| 10732 | intel_display_power_put(dev_priv, power_domain); |
| 10733 | |
Jani Nikula | cf30429 | 2016-03-18 17:05:41 +0200 | [diff] [blame] | 10734 | return active; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10735 | } |
| 10736 | |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10737 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
| 10738 | const struct intel_plane_state *plane_state) |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10739 | { |
| 10740 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10741 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10743 | uint32_t cntl = 0, size = 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10744 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 10745 | if (plane_state && plane_state->base.visible) { |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10746 | unsigned int width = plane_state->base.crtc_w; |
| 10747 | unsigned int height = plane_state->base.crtc_h; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10748 | unsigned int stride = roundup_pow_of_two(width) * 4; |
| 10749 | |
| 10750 | switch (stride) { |
| 10751 | default: |
| 10752 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", |
| 10753 | width, stride); |
| 10754 | stride = 256; |
| 10755 | /* fallthrough */ |
| 10756 | case 256: |
| 10757 | case 512: |
| 10758 | case 1024: |
| 10759 | case 2048: |
| 10760 | break; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10761 | } |
| 10762 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10763 | cntl |= CURSOR_ENABLE | |
| 10764 | CURSOR_GAMMA_ENABLE | |
| 10765 | CURSOR_FORMAT_ARGB | |
| 10766 | CURSOR_STRIDE(stride); |
| 10767 | |
| 10768 | size = (height << 12) | width; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10769 | } |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10770 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10771 | if (intel_crtc->cursor_cntl != 0 && |
| 10772 | (intel_crtc->cursor_base != base || |
| 10773 | intel_crtc->cursor_size != size || |
| 10774 | intel_crtc->cursor_cntl != cntl)) { |
| 10775 | /* On these chipsets we can only modify the base/size/stride |
| 10776 | * whilst the cursor is disabled. |
| 10777 | */ |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 10778 | I915_WRITE(CURCNTR(PIPE_A), 0); |
| 10779 | POSTING_READ(CURCNTR(PIPE_A)); |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10780 | intel_crtc->cursor_cntl = 0; |
| 10781 | } |
| 10782 | |
Ville Syrjälä | 99d1f38 | 2014-09-12 20:53:32 +0300 | [diff] [blame] | 10783 | if (intel_crtc->cursor_base != base) { |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 10784 | I915_WRITE(CURBASE(PIPE_A), base); |
Ville Syrjälä | 99d1f38 | 2014-09-12 20:53:32 +0300 | [diff] [blame] | 10785 | intel_crtc->cursor_base = base; |
| 10786 | } |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10787 | |
| 10788 | if (intel_crtc->cursor_size != size) { |
| 10789 | I915_WRITE(CURSIZE, size); |
| 10790 | intel_crtc->cursor_size = size; |
| 10791 | } |
| 10792 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10793 | if (intel_crtc->cursor_cntl != cntl) { |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 10794 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
| 10795 | POSTING_READ(CURCNTR(PIPE_A)); |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10796 | intel_crtc->cursor_cntl = cntl; |
| 10797 | } |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10798 | } |
| 10799 | |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10800 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
| 10801 | const struct intel_plane_state *plane_state) |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10802 | { |
| 10803 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10804 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 10806 | const struct skl_wm_values *wm = &dev_priv->wm.skl_results; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10807 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10808 | uint32_t cntl = 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10809 | |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 10810 | if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc)) |
| 10811 | skl_write_cursor_wm(intel_crtc, wm); |
| 10812 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 10813 | if (plane_state && plane_state->base.visible) { |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10814 | cntl = MCURSOR_GAMMA_ENABLE; |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10815 | switch (plane_state->base.crtc_w) { |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 10816 | case 64: |
| 10817 | cntl |= CURSOR_MODE_64_ARGB_AX; |
| 10818 | break; |
| 10819 | case 128: |
| 10820 | cntl |= CURSOR_MODE_128_ARGB_AX; |
| 10821 | break; |
| 10822 | case 256: |
| 10823 | cntl |= CURSOR_MODE_256_ARGB_AX; |
| 10824 | break; |
| 10825 | default: |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10826 | MISSING_CASE(plane_state->base.crtc_w); |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 10827 | return; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10828 | } |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10829 | cntl |= pipe << 28; /* Connect to correct pipe */ |
Ville Syrjälä | 47bf17a | 2014-09-12 20:53:33 +0300 | [diff] [blame] | 10830 | |
Bob Paauwe | fc6f93b | 2015-08-31 14:03:30 -0700 | [diff] [blame] | 10831 | if (HAS_DDI(dev)) |
Ville Syrjälä | 47bf17a | 2014-09-12 20:53:33 +0300 | [diff] [blame] | 10832 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10833 | |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 10834 | if (plane_state->base.rotation == DRM_ROTATE_180) |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10835 | cntl |= CURSOR_ROTATE_180; |
| 10836 | } |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 10837 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10838 | if (intel_crtc->cursor_cntl != cntl) { |
| 10839 | I915_WRITE(CURCNTR(pipe), cntl); |
| 10840 | POSTING_READ(CURCNTR(pipe)); |
| 10841 | intel_crtc->cursor_cntl = cntl; |
| 10842 | } |
| 10843 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 10844 | /* and commit changes on next vblank */ |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 10845 | I915_WRITE(CURBASE(pipe), base); |
| 10846 | POSTING_READ(CURBASE(pipe)); |
Ville Syrjälä | 99d1f38 | 2014-09-12 20:53:32 +0300 | [diff] [blame] | 10847 | |
| 10848 | intel_crtc->cursor_base = base; |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 10849 | } |
| 10850 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10851 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 10852 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10853 | const struct intel_plane_state *plane_state) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10854 | { |
| 10855 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 10856 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10858 | int pipe = intel_crtc->pipe; |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10859 | u32 base = intel_crtc->cursor_addr; |
| 10860 | u32 pos = 0; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10861 | |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10862 | if (plane_state) { |
| 10863 | int x = plane_state->base.crtc_x; |
| 10864 | int y = plane_state->base.crtc_y; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10865 | |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10866 | if (x < 0) { |
| 10867 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 10868 | x = -x; |
| 10869 | } |
| 10870 | pos |= x << CURSOR_X_SHIFT; |
| 10871 | |
| 10872 | if (y < 0) { |
| 10873 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 10874 | y = -y; |
| 10875 | } |
| 10876 | pos |= y << CURSOR_Y_SHIFT; |
| 10877 | |
| 10878 | /* ILK+ do this automagically */ |
| 10879 | if (HAS_GMCH_DISPLAY(dev) && |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 10880 | plane_state->base.rotation == DRM_ROTATE_180) { |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10881 | base += (plane_state->base.crtc_h * |
| 10882 | plane_state->base.crtc_w - 1) * 4; |
| 10883 | } |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10884 | } |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10885 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 10886 | I915_WRITE(CURPOS(pipe), pos); |
| 10887 | |
Ville Syrjälä | 8ac5466 | 2014-08-12 19:39:54 +0300 | [diff] [blame] | 10888 | if (IS_845G(dev) || IS_I865G(dev)) |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10889 | i845_update_cursor(crtc, base, plane_state); |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 10890 | else |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 10891 | i9xx_update_cursor(crtc, base, plane_state); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10892 | } |
| 10893 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10894 | static bool cursor_size_ok(struct drm_device *dev, |
| 10895 | uint32_t width, uint32_t height) |
| 10896 | { |
| 10897 | if (width == 0 || height == 0) |
| 10898 | return false; |
| 10899 | |
| 10900 | /* |
| 10901 | * 845g/865g are special in that they are only limited by |
| 10902 | * the width of their cursors, the height is arbitrary up to |
| 10903 | * the precision of the register. Everything else requires |
| 10904 | * square cursors, limited to a few power-of-two sizes. |
| 10905 | */ |
| 10906 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 10907 | if ((width & 63) != 0) |
| 10908 | return false; |
| 10909 | |
| 10910 | if (width > (IS_845G(dev) ? 64 : 512)) |
| 10911 | return false; |
| 10912 | |
| 10913 | if (height > 1023) |
| 10914 | return false; |
| 10915 | } else { |
| 10916 | switch (width | height) { |
| 10917 | case 256: |
| 10918 | case 128: |
| 10919 | if (IS_GEN2(dev)) |
| 10920 | return false; |
| 10921 | case 64: |
| 10922 | break; |
| 10923 | default: |
| 10924 | return false; |
| 10925 | } |
| 10926 | } |
| 10927 | |
| 10928 | return true; |
| 10929 | } |
| 10930 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10931 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 10932 | static struct drm_display_mode load_detect_mode = { |
| 10933 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 10934 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 10935 | }; |
| 10936 | |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 10937 | struct drm_framebuffer * |
| 10938 | __intel_framebuffer_create(struct drm_device *dev, |
| 10939 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10940 | struct drm_i915_gem_object *obj) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10941 | { |
| 10942 | struct intel_framebuffer *intel_fb; |
| 10943 | int ret; |
| 10944 | |
| 10945 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10946 | if (!intel_fb) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10947 | return ERR_PTR(-ENOMEM); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10948 | |
| 10949 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10950 | if (ret) |
| 10951 | goto err; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10952 | |
| 10953 | return &intel_fb->base; |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10954 | |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10955 | err: |
| 10956 | kfree(intel_fb); |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10957 | return ERR_PTR(ret); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10958 | } |
| 10959 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 10960 | static struct drm_framebuffer * |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 10961 | intel_framebuffer_create(struct drm_device *dev, |
| 10962 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10963 | struct drm_i915_gem_object *obj) |
| 10964 | { |
| 10965 | struct drm_framebuffer *fb; |
| 10966 | int ret; |
| 10967 | |
| 10968 | ret = i915_mutex_lock_interruptible(dev); |
| 10969 | if (ret) |
| 10970 | return ERR_PTR(ret); |
| 10971 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
| 10972 | mutex_unlock(&dev->struct_mutex); |
| 10973 | |
| 10974 | return fb; |
| 10975 | } |
| 10976 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10977 | static u32 |
| 10978 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 10979 | { |
| 10980 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 10981 | return ALIGN(pitch, 64); |
| 10982 | } |
| 10983 | |
| 10984 | static u32 |
| 10985 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 10986 | { |
| 10987 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
Fabian Frederick | 1267a26 | 2014-07-01 20:39:41 +0200 | [diff] [blame] | 10988 | return PAGE_ALIGN(pitch * mode->vdisplay); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10989 | } |
| 10990 | |
| 10991 | static struct drm_framebuffer * |
| 10992 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 10993 | struct drm_display_mode *mode, |
| 10994 | int depth, int bpp) |
| 10995 | { |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10996 | struct drm_framebuffer *fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10997 | struct drm_i915_gem_object *obj; |
Chris Wilson | 0fed39b | 2012-11-05 22:25:07 +0000 | [diff] [blame] | 10998 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10999 | |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 11000 | obj = i915_gem_object_create(dev, |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11001 | intel_framebuffer_size_for_mode(mode, bpp)); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 11002 | if (IS_ERR(obj)) |
| 11003 | return ERR_CAST(obj); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11004 | |
| 11005 | mode_cmd.width = mode->hdisplay; |
| 11006 | mode_cmd.height = mode->vdisplay; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 11007 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 11008 | bpp); |
Dave Airlie | 5ca0c34 | 2012-02-23 15:33:40 +0000 | [diff] [blame] | 11009 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11010 | |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 11011 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
| 11012 | if (IS_ERR(fb)) |
Chris Wilson | 34911fd | 2016-07-20 13:31:54 +0100 | [diff] [blame] | 11013 | i915_gem_object_put_unlocked(obj); |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 11014 | |
| 11015 | return fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11016 | } |
| 11017 | |
| 11018 | static struct drm_framebuffer * |
| 11019 | mode_fits_in_fbdev(struct drm_device *dev, |
| 11020 | struct drm_display_mode *mode) |
| 11021 | { |
Daniel Vetter | 0695726 | 2015-08-10 13:34:08 +0200 | [diff] [blame] | 11022 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11023 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11024 | struct drm_i915_gem_object *obj; |
| 11025 | struct drm_framebuffer *fb; |
| 11026 | |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 11027 | if (!dev_priv->fbdev) |
| 11028 | return NULL; |
| 11029 | |
| 11030 | if (!dev_priv->fbdev->fb) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11031 | return NULL; |
| 11032 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 11033 | obj = dev_priv->fbdev->fb->obj; |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 11034 | BUG_ON(!obj); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11035 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 11036 | fb = &dev_priv->fbdev->fb->base; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 11037 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 11038 | fb->bits_per_pixel)) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11039 | return NULL; |
| 11040 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 11041 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11042 | return NULL; |
| 11043 | |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11044 | drm_framebuffer_reference(fb); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11045 | return fb; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 11046 | #else |
| 11047 | return NULL; |
| 11048 | #endif |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11049 | } |
| 11050 | |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 11051 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
| 11052 | struct drm_crtc *crtc, |
| 11053 | struct drm_display_mode *mode, |
| 11054 | struct drm_framebuffer *fb, |
| 11055 | int x, int y) |
| 11056 | { |
| 11057 | struct drm_plane_state *plane_state; |
| 11058 | int hdisplay, vdisplay; |
| 11059 | int ret; |
| 11060 | |
| 11061 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); |
| 11062 | if (IS_ERR(plane_state)) |
| 11063 | return PTR_ERR(plane_state); |
| 11064 | |
| 11065 | if (mode) |
| 11066 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
| 11067 | else |
| 11068 | hdisplay = vdisplay = 0; |
| 11069 | |
| 11070 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); |
| 11071 | if (ret) |
| 11072 | return ret; |
| 11073 | drm_atomic_set_fb_for_plane(plane_state, fb); |
| 11074 | plane_state->crtc_x = 0; |
| 11075 | plane_state->crtc_y = 0; |
| 11076 | plane_state->crtc_w = hdisplay; |
| 11077 | plane_state->crtc_h = vdisplay; |
| 11078 | plane_state->src_x = x << 16; |
| 11079 | plane_state->src_y = y << 16; |
| 11080 | plane_state->src_w = hdisplay << 16; |
| 11081 | plane_state->src_h = vdisplay << 16; |
| 11082 | |
| 11083 | return 0; |
| 11084 | } |
| 11085 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 11086 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 11087 | struct drm_display_mode *mode, |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11088 | struct intel_load_detect_pipe *old, |
| 11089 | struct drm_modeset_acquire_ctx *ctx) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11090 | { |
| 11091 | struct intel_crtc *intel_crtc; |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 11092 | struct intel_encoder *intel_encoder = |
| 11093 | intel_attached_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11094 | struct drm_crtc *possible_crtc; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 11095 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11096 | struct drm_crtc *crtc = NULL; |
| 11097 | struct drm_device *dev = encoder->dev; |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 11098 | struct drm_framebuffer *fb; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11099 | struct drm_mode_config *config = &dev->mode_config; |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11100 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 11101 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 11102 | struct intel_crtc_state *crtc_state; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11103 | int ret, i = -1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11104 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11105 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 11106 | connector->base.id, connector->name, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 11107 | encoder->base.id, encoder->name); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11108 | |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11109 | old->restore_state = NULL; |
| 11110 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11111 | retry: |
| 11112 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
| 11113 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 11114 | goto fail; |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 11115 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11116 | /* |
| 11117 | * Algorithm gets a little messy: |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 11118 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11119 | * - if the connector already has an assigned crtc, use it (but make |
| 11120 | * sure it's on first) |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 11121 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11122 | * - try to find the first unused crtc that can drive this connector, |
| 11123 | * and use that if we find one |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11124 | */ |
| 11125 | |
| 11126 | /* See if we already have a CRTC for this connector */ |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11127 | if (connector->state->crtc) { |
| 11128 | crtc = connector->state->crtc; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 11129 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11130 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 11131 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 11132 | goto fail; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 11133 | |
| 11134 | /* Make sure the crtc and connector are running */ |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11135 | goto found; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11136 | } |
| 11137 | |
| 11138 | /* Find an unused one (if possible) */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 11139 | for_each_crtc(dev, possible_crtc) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11140 | i++; |
| 11141 | if (!(encoder->possible_crtcs & (1 << i))) |
| 11142 | continue; |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11143 | |
| 11144 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); |
| 11145 | if (ret) |
| 11146 | goto fail; |
| 11147 | |
| 11148 | if (possible_crtc->state->enable) { |
| 11149 | drm_modeset_unlock(&possible_crtc->mutex); |
Ville Syrjälä | a459249 | 2014-08-11 13:15:36 +0300 | [diff] [blame] | 11150 | continue; |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11151 | } |
Ville Syrjälä | a459249 | 2014-08-11 13:15:36 +0300 | [diff] [blame] | 11152 | |
| 11153 | crtc = possible_crtc; |
| 11154 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11155 | } |
| 11156 | |
| 11157 | /* |
| 11158 | * If we didn't find an unused CRTC, don't use any. |
| 11159 | */ |
| 11160 | if (!crtc) { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 11161 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 11162 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11163 | } |
| 11164 | |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11165 | found: |
| 11166 | intel_crtc = to_intel_crtc(crtc); |
| 11167 | |
Daniel Vetter | 4d02e2d | 2014-11-11 10:12:00 +0100 | [diff] [blame] | 11168 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
| 11169 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 11170 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11171 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 11172 | state = drm_atomic_state_alloc(dev); |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11173 | restore_state = drm_atomic_state_alloc(dev); |
| 11174 | if (!state || !restore_state) { |
| 11175 | ret = -ENOMEM; |
| 11176 | goto fail; |
| 11177 | } |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 11178 | |
| 11179 | state->acquire_ctx = ctx; |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11180 | restore_state->acquire_ctx = ctx; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 11181 | |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 11182 | connector_state = drm_atomic_get_connector_state(state, connector); |
| 11183 | if (IS_ERR(connector_state)) { |
| 11184 | ret = PTR_ERR(connector_state); |
| 11185 | goto fail; |
| 11186 | } |
| 11187 | |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11188 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
| 11189 | if (ret) |
| 11190 | goto fail; |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 11191 | |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 11192 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 11193 | if (IS_ERR(crtc_state)) { |
| 11194 | ret = PTR_ERR(crtc_state); |
| 11195 | goto fail; |
| 11196 | } |
| 11197 | |
Maarten Lankhorst | 49d6fa2 | 2015-05-11 10:45:15 +0200 | [diff] [blame] | 11198 | crtc_state->base.active = crtc_state->base.enable = true; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 11199 | |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 11200 | if (!mode) |
| 11201 | mode = &load_detect_mode; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11202 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11203 | /* We need a framebuffer large enough to accommodate all accesses |
| 11204 | * that the plane may generate whilst we perform load detection. |
| 11205 | * We can not rely on the fbcon either being present (we get called |
| 11206 | * during its initialisation to detect all boot displays, or it may |
| 11207 | * not even exist) or that it is large enough to satisfy the |
| 11208 | * requested mode. |
| 11209 | */ |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 11210 | fb = mode_fits_in_fbdev(dev, mode); |
| 11211 | if (fb == NULL) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11212 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 11213 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11214 | } else |
| 11215 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 11216 | if (IS_ERR(fb)) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11217 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 11218 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11219 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11220 | |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 11221 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
| 11222 | if (ret) |
| 11223 | goto fail; |
| 11224 | |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11225 | drm_framebuffer_unreference(fb); |
| 11226 | |
| 11227 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); |
| 11228 | if (ret) |
| 11229 | goto fail; |
| 11230 | |
| 11231 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); |
| 11232 | if (!ret) |
| 11233 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); |
| 11234 | if (!ret) |
| 11235 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); |
| 11236 | if (ret) { |
| 11237 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); |
| 11238 | goto fail; |
| 11239 | } |
Ander Conselvan de Oliveira | 8c7b5cc | 2015-04-21 17:13:19 +0300 | [diff] [blame] | 11240 | |
Maarten Lankhorst | 3ba8607 | 2016-02-29 09:18:57 +0100 | [diff] [blame] | 11241 | ret = drm_atomic_commit(state); |
| 11242 | if (ret) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 11243 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 11244 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11245 | } |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11246 | |
| 11247 | old->restore_state = restore_state; |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 11248 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11249 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 11250 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 11251 | return true; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 11252 | |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 11253 | fail: |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 11254 | drm_atomic_state_put(state); |
| 11255 | drm_atomic_state_put(restore_state); |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11256 | restore_state = state = NULL; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 11257 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11258 | if (ret == -EDEADLK) { |
| 11259 | drm_modeset_backoff(ctx); |
| 11260 | goto retry; |
| 11261 | } |
| 11262 | |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 11263 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11264 | } |
| 11265 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 11266 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
Ander Conselvan de Oliveira | 49172fe | 2015-03-20 16:18:02 +0200 | [diff] [blame] | 11267 | struct intel_load_detect_pipe *old, |
| 11268 | struct drm_modeset_acquire_ctx *ctx) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11269 | { |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 11270 | struct intel_encoder *intel_encoder = |
| 11271 | intel_attached_encoder(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 11272 | struct drm_encoder *encoder = &intel_encoder->base; |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11273 | struct drm_atomic_state *state = old->restore_state; |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 11274 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11275 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11276 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 11277 | connector->base.id, connector->name, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 11278 | encoder->base.id, encoder->name); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 11279 | |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11280 | if (!state) |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 11281 | return; |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11282 | |
| 11283 | ret = drm_atomic_commit(state); |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 11284 | if (ret) |
Maarten Lankhorst | edde361 | 2016-02-17 09:18:35 +0100 | [diff] [blame] | 11285 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 11286 | drm_atomic_state_put(state); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11287 | } |
| 11288 | |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 11289 | static int i9xx_pll_refclk(struct drm_device *dev, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 11290 | const struct intel_crtc_state *pipe_config) |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 11291 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11292 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 11293 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 11294 | |
| 11295 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 11296 | return dev_priv->vbt.lvds_ssc_freq; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 11297 | else if (HAS_PCH_SPLIT(dev)) |
| 11298 | return 120000; |
| 11299 | else if (!IS_GEN2(dev)) |
| 11300 | return 96000; |
| 11301 | else |
| 11302 | return 48000; |
| 11303 | } |
| 11304 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11305 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11306 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 11307 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11308 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11309 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11310 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11311 | int pipe = pipe_config->cpu_transcoder; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 11312 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11313 | u32 fp; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 11314 | struct dpll clock; |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 11315 | int port_clock; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 11316 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11317 | |
| 11318 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 11319 | fp = pipe_config->dpll_hw_state.fp0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11320 | else |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 11321 | fp = pipe_config->dpll_hw_state.fp1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11322 | |
| 11323 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 11324 | if (IS_PINEVIEW(dev)) { |
| 11325 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 11326 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 11327 | } else { |
| 11328 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 11329 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 11330 | } |
| 11331 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 11332 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 11333 | if (IS_PINEVIEW(dev)) |
| 11334 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 11335 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 11336 | else |
| 11337 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11338 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 11339 | |
| 11340 | switch (dpll & DPLL_MODE_MASK) { |
| 11341 | case DPLLB_MODE_DAC_SERIAL: |
| 11342 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 11343 | 5 : 10; |
| 11344 | break; |
| 11345 | case DPLLB_MODE_LVDS: |
| 11346 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 11347 | 7 : 14; |
| 11348 | break; |
| 11349 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 11350 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11351 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11352 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11353 | } |
| 11354 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 11355 | if (IS_PINEVIEW(dev)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 11356 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 11357 | else |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 11358 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11359 | } else { |
Ville Syrjälä | 0fb5822 | 2014-01-10 14:06:46 +0200 | [diff] [blame] | 11360 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 11361 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11362 | |
| 11363 | if (is_lvds) { |
| 11364 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 11365 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 11366 | |
| 11367 | if (lvds & LVDS_CLKB_POWER_UP) |
| 11368 | clock.p2 = 7; |
| 11369 | else |
| 11370 | clock.p2 = 14; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11371 | } else { |
| 11372 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 11373 | clock.p1 = 2; |
| 11374 | else { |
| 11375 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 11376 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 11377 | } |
| 11378 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 11379 | clock.p2 = 4; |
| 11380 | else |
| 11381 | clock.p2 = 2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11382 | } |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 11383 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 11384 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11385 | } |
| 11386 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 11387 | /* |
| 11388 | * This value includes pixel_multiplier. We will use |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 11389 | * port_clock to compute adjusted_mode.crtc_clock in the |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 11390 | * encoder's get_config() function. |
| 11391 | */ |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 11392 | pipe_config->port_clock = port_clock; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11393 | } |
| 11394 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 11395 | int intel_dotclock_calculate(int link_freq, |
| 11396 | const struct intel_link_m_n *m_n) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11397 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11398 | /* |
| 11399 | * The calculation for the data clock is: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 11400 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11401 | * But we want to avoid losing precison if possible, so: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 11402 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11403 | * |
| 11404 | * and the link clock is simpler: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 11405 | * link_clock = (m * link_clock) / n |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11406 | */ |
| 11407 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 11408 | if (!m_n->link_n) |
| 11409 | return 0; |
| 11410 | |
| 11411 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
| 11412 | } |
| 11413 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 11414 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 11415 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 11416 | { |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 11417 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 11418 | |
| 11419 | /* read out port_clock from the DPLL */ |
| 11420 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 11421 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11422 | /* |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 11423 | * In case there is an active pipe without active ports, |
| 11424 | * we may need some idea for the dotclock anyway. |
| 11425 | * Calculate one based on the FDI configuration. |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11426 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 11427 | pipe_config->base.adjusted_mode.crtc_clock = |
Ville Syrjälä | 21a727b | 2016-02-17 21:41:10 +0200 | [diff] [blame] | 11428 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 11429 | &pipe_config->fdi_m_n); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11430 | } |
| 11431 | |
| 11432 | /** Returns the currently programmed mode of the given pipe. */ |
| 11433 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 11434 | struct drm_crtc *crtc) |
| 11435 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11436 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 11438 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11439 | struct drm_display_mode *mode; |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 11440 | struct intel_crtc_state *pipe_config; |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 11441 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
| 11442 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 11443 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
| 11444 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 11445 | enum pipe pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11446 | |
| 11447 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 11448 | if (!mode) |
| 11449 | return NULL; |
| 11450 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 11451 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
| 11452 | if (!pipe_config) { |
| 11453 | kfree(mode); |
| 11454 | return NULL; |
| 11455 | } |
| 11456 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11457 | /* |
| 11458 | * Construct a pipe_config sufficient for getting the clock info |
| 11459 | * back out of crtc_clock_get. |
| 11460 | * |
| 11461 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
| 11462 | * to use a real value here instead. |
| 11463 | */ |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 11464 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
| 11465 | pipe_config->pixel_multiplier = 1; |
| 11466 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
| 11467 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
| 11468 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
| 11469 | i9xx_crtc_clock_get(intel_crtc, pipe_config); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 11470 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 11471 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11472 | mode->hdisplay = (htot & 0xffff) + 1; |
| 11473 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 11474 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 11475 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 11476 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 11477 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 11478 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 11479 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 11480 | |
| 11481 | drm_mode_set_name(mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11482 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 11483 | kfree(pipe_config); |
| 11484 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11485 | return mode; |
| 11486 | } |
| 11487 | |
| 11488 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 11489 | { |
| 11490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 11491 | struct drm_device *dev = crtc->dev; |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11492 | struct intel_flip_work *work; |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 11493 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11494 | spin_lock_irq(&dev->event_lock); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11495 | work = intel_crtc->flip_work; |
| 11496 | intel_crtc->flip_work = NULL; |
| 11497 | spin_unlock_irq(&dev->event_lock); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 11498 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11499 | if (work) { |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11500 | cancel_work_sync(&work->mmio_work); |
| 11501 | cancel_work_sync(&work->unpin_work); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11502 | kfree(work); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 11503 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11504 | |
| 11505 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 11506 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11507 | kfree(intel_crtc); |
| 11508 | } |
| 11509 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11510 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 11511 | { |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11512 | struct intel_flip_work *work = |
| 11513 | container_of(__work, struct intel_flip_work, unpin_work); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11514 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
| 11515 | struct drm_device *dev = crtc->base.dev; |
| 11516 | struct drm_plane *primary = crtc->base.primary; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11517 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11518 | if (is_mmio_work(work)) |
| 11519 | flush_work(&work->mmio_work); |
| 11520 | |
| 11521 | mutex_lock(&dev->struct_mutex); |
| 11522 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
Chris Wilson | f8c417c | 2016-07-20 13:31:53 +0100 | [diff] [blame] | 11523 | i915_gem_object_put(work->pending_flip_obj); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11524 | mutex_unlock(&dev->struct_mutex); |
| 11525 | |
Chris Wilson | e8a261e | 2016-07-20 13:31:49 +0100 | [diff] [blame] | 11526 | i915_gem_request_put(work->flip_queued_req); |
| 11527 | |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 11528 | intel_frontbuffer_flip_complete(to_i915(dev), |
| 11529 | to_intel_plane(primary)->frontbuffer_bit); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11530 | intel_fbc_post_update(crtc); |
| 11531 | drm_framebuffer_unreference(work->old_fb); |
| 11532 | |
| 11533 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
| 11534 | atomic_dec(&crtc->unpin_work_count); |
| 11535 | |
| 11536 | kfree(work); |
| 11537 | } |
| 11538 | |
| 11539 | /* Is 'a' after or equal to 'b'? */ |
| 11540 | static bool g4x_flip_count_after_eq(u32 a, u32 b) |
| 11541 | { |
| 11542 | return !((a - b) & 0x80000000); |
| 11543 | } |
| 11544 | |
| 11545 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
| 11546 | struct intel_flip_work *work) |
| 11547 | { |
| 11548 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11549 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11550 | |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 11551 | if (abort_flip_on_reset(crtc)) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11552 | return true; |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11553 | |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 11554 | /* |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11555 | * The relevant registers doen't exist on pre-ctg. |
| 11556 | * As the flip done interrupt doesn't trigger for mmio |
| 11557 | * flips on gmch platforms, a flip count check isn't |
| 11558 | * really needed there. But since ctg has the registers, |
| 11559 | * include it in the check anyway. |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 11560 | */ |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11561 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
| 11562 | return true; |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 11563 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11564 | /* |
| 11565 | * BDW signals flip done immediately if the plane |
| 11566 | * is disabled, even if the plane enable is already |
| 11567 | * armed to occur at the next vblank :( |
| 11568 | */ |
Maarten Lankhorst | a6747b7 | 2016-05-17 15:08:01 +0200 | [diff] [blame] | 11569 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11570 | /* |
| 11571 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
| 11572 | * used the same base address. In that case the mmio flip might |
| 11573 | * have completed, but the CS hasn't even executed the flip yet. |
| 11574 | * |
| 11575 | * A flip count check isn't enough as the CS might have updated |
| 11576 | * the base address just after start of vblank, but before we |
| 11577 | * managed to process the interrupt. This means we'd complete the |
| 11578 | * CS flip too soon. |
| 11579 | * |
| 11580 | * Combining both checks should get us a good enough result. It may |
| 11581 | * still happen that the CS flip has been executed, but has not |
| 11582 | * yet actually completed. But in case the base address is the same |
| 11583 | * anyway, we don't really care. |
| 11584 | */ |
| 11585 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
| 11586 | crtc->flip_work->gtt_offset && |
| 11587 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
| 11588 | crtc->flip_work->flip_count); |
| 11589 | } |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 11590 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11591 | static bool |
| 11592 | __pageflip_finished_mmio(struct intel_crtc *crtc, |
| 11593 | struct intel_flip_work *work) |
| 11594 | { |
| 11595 | /* |
| 11596 | * MMIO work completes when vblank is different from |
| 11597 | * flip_queued_vblank. |
| 11598 | * |
| 11599 | * Reset counter value doesn't matter, this is handled by |
| 11600 | * i915_wait_request finishing early, so no need to handle |
| 11601 | * reset here. |
| 11602 | */ |
| 11603 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11604 | } |
| 11605 | |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11606 | |
| 11607 | static bool pageflip_finished(struct intel_crtc *crtc, |
| 11608 | struct intel_flip_work *work) |
| 11609 | { |
| 11610 | if (!atomic_read(&work->pending)) |
| 11611 | return false; |
| 11612 | |
| 11613 | smp_rmb(); |
| 11614 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11615 | if (is_mmio_work(work)) |
| 11616 | return __pageflip_finished_mmio(crtc, work); |
| 11617 | else |
| 11618 | return __pageflip_finished_cs(crtc, work); |
| 11619 | } |
| 11620 | |
| 11621 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) |
| 11622 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 11623 | struct drm_device *dev = &dev_priv->drm; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11624 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 11625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11626 | struct intel_flip_work *work; |
| 11627 | unsigned long flags; |
| 11628 | |
| 11629 | /* Ignore early vblank irqs */ |
| 11630 | if (!crtc) |
| 11631 | return; |
| 11632 | |
Daniel Vetter | f326038 | 2014-09-15 14:55:23 +0200 | [diff] [blame] | 11633 | /* |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11634 | * This is called both by irq handlers and the reset code (to complete |
| 11635 | * lost pageflips) so needs the full irqsave spinlocks. |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11636 | */ |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11637 | spin_lock_irqsave(&dev->event_lock, flags); |
| 11638 | work = intel_crtc->flip_work; |
| 11639 | |
| 11640 | if (work != NULL && |
| 11641 | !is_mmio_work(work) && |
| 11642 | pageflip_finished(intel_crtc, work)) |
| 11643 | page_flip_completed(intel_crtc); |
| 11644 | |
| 11645 | spin_unlock_irqrestore(&dev->event_lock, flags); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11646 | } |
| 11647 | |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11648 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11649 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 11650 | struct drm_device *dev = &dev_priv->drm; |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11651 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 11652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11653 | struct intel_flip_work *work; |
| 11654 | unsigned long flags; |
| 11655 | |
| 11656 | /* Ignore early vblank irqs */ |
| 11657 | if (!crtc) |
| 11658 | return; |
| 11659 | |
| 11660 | /* |
| 11661 | * This is called both by irq handlers and the reset code (to complete |
| 11662 | * lost pageflips) so needs the full irqsave spinlocks. |
| 11663 | */ |
| 11664 | spin_lock_irqsave(&dev->event_lock, flags); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11665 | work = intel_crtc->flip_work; |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11666 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11667 | if (work != NULL && |
| 11668 | is_mmio_work(work) && |
| 11669 | pageflip_finished(intel_crtc, work)) |
| 11670 | page_flip_completed(intel_crtc); |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 11671 | |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 11672 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 11673 | } |
| 11674 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11675 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
| 11676 | struct intel_flip_work *work) |
| 11677 | { |
| 11678 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
| 11679 | |
| 11680 | /* Ensure that the work item is consistent when activating it ... */ |
| 11681 | smp_mb__before_atomic(); |
| 11682 | atomic_set(&work->pending, 1); |
| 11683 | } |
| 11684 | |
| 11685 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 11686 | struct drm_crtc *crtc, |
| 11687 | struct drm_framebuffer *fb, |
| 11688 | struct drm_i915_gem_object *obj, |
| 11689 | struct drm_i915_gem_request *req, |
| 11690 | uint32_t flags) |
| 11691 | { |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 11692 | struct intel_ring *ring = req->ring; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11694 | u32 flip_mask; |
| 11695 | int ret; |
| 11696 | |
| 11697 | ret = intel_ring_begin(req, 6); |
| 11698 | if (ret) |
| 11699 | return ret; |
| 11700 | |
| 11701 | /* Can't queue multiple flips, so wait for the previous |
| 11702 | * one to finish before executing the next. |
| 11703 | */ |
| 11704 | if (intel_crtc->plane) |
| 11705 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 11706 | else |
| 11707 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11708 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 11709 | intel_ring_emit(ring, MI_NOOP); |
| 11710 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11711 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11712 | intel_ring_emit(ring, fb->pitches[0]); |
| 11713 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
| 11714 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11715 | |
| 11716 | return 0; |
| 11717 | } |
| 11718 | |
| 11719 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 11720 | struct drm_crtc *crtc, |
| 11721 | struct drm_framebuffer *fb, |
| 11722 | struct drm_i915_gem_object *obj, |
| 11723 | struct drm_i915_gem_request *req, |
| 11724 | uint32_t flags) |
| 11725 | { |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 11726 | struct intel_ring *ring = req->ring; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11728 | u32 flip_mask; |
| 11729 | int ret; |
| 11730 | |
| 11731 | ret = intel_ring_begin(req, 6); |
| 11732 | if (ret) |
| 11733 | return ret; |
| 11734 | |
| 11735 | if (intel_crtc->plane) |
| 11736 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 11737 | else |
| 11738 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11739 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 11740 | intel_ring_emit(ring, MI_NOOP); |
| 11741 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11742 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11743 | intel_ring_emit(ring, fb->pitches[0]); |
| 11744 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
| 11745 | intel_ring_emit(ring, MI_NOOP); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11746 | |
| 11747 | return 0; |
| 11748 | } |
| 11749 | |
| 11750 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 11751 | struct drm_crtc *crtc, |
| 11752 | struct drm_framebuffer *fb, |
| 11753 | struct drm_i915_gem_object *obj, |
| 11754 | struct drm_i915_gem_request *req, |
| 11755 | uint32_t flags) |
| 11756 | { |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 11757 | struct intel_ring *ring = req->ring; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11758 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11760 | uint32_t pf, pipesrc; |
| 11761 | int ret; |
| 11762 | |
| 11763 | ret = intel_ring_begin(req, 4); |
| 11764 | if (ret) |
| 11765 | return ret; |
| 11766 | |
| 11767 | /* i965+ uses the linear or tiled offsets from the |
| 11768 | * Display Registers (which do not change across a page-flip) |
| 11769 | * so we need only reprogram the base address. |
| 11770 | */ |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11771 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11772 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11773 | intel_ring_emit(ring, fb->pitches[0]); |
| 11774 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 11775 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11776 | |
| 11777 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 11778 | * untested on non-native modes, so ignore it for now. |
| 11779 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 11780 | */ |
| 11781 | pf = 0; |
| 11782 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11783 | intel_ring_emit(ring, pf | pipesrc); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11784 | |
| 11785 | return 0; |
| 11786 | } |
| 11787 | |
| 11788 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 11789 | struct drm_crtc *crtc, |
| 11790 | struct drm_framebuffer *fb, |
| 11791 | struct drm_i915_gem_object *obj, |
| 11792 | struct drm_i915_gem_request *req, |
| 11793 | uint32_t flags) |
| 11794 | { |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 11795 | struct intel_ring *ring = req->ring; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11796 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11798 | uint32_t pf, pipesrc; |
| 11799 | int ret; |
| 11800 | |
| 11801 | ret = intel_ring_begin(req, 4); |
| 11802 | if (ret) |
| 11803 | return ret; |
| 11804 | |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11805 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11806 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 11807 | intel_ring_emit(ring, fb->pitches[0] | |
| 11808 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11809 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11810 | |
| 11811 | /* Contrary to the suggestions in the documentation, |
| 11812 | * "Enable Panel Fitter" does not seem to be required when page |
| 11813 | * flipping with a non-native mode, and worse causes a normal |
| 11814 | * modeset to fail. |
| 11815 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 11816 | */ |
| 11817 | pf = 0; |
| 11818 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11819 | intel_ring_emit(ring, pf | pipesrc); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11820 | |
| 11821 | return 0; |
| 11822 | } |
| 11823 | |
| 11824 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 11825 | struct drm_crtc *crtc, |
| 11826 | struct drm_framebuffer *fb, |
| 11827 | struct drm_i915_gem_object *obj, |
| 11828 | struct drm_i915_gem_request *req, |
| 11829 | uint32_t flags) |
| 11830 | { |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 11831 | struct intel_ring *ring = req->ring; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11833 | uint32_t plane_bit = 0; |
| 11834 | int len, ret; |
| 11835 | |
| 11836 | switch (intel_crtc->plane) { |
| 11837 | case PLANE_A: |
| 11838 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
| 11839 | break; |
| 11840 | case PLANE_B: |
| 11841 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
| 11842 | break; |
| 11843 | case PLANE_C: |
| 11844 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
| 11845 | break; |
| 11846 | default: |
| 11847 | WARN_ONCE(1, "unknown plane in flip command\n"); |
| 11848 | return -ENODEV; |
| 11849 | } |
| 11850 | |
| 11851 | len = 4; |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11852 | if (req->engine->id == RCS) { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11853 | len += 6; |
| 11854 | /* |
| 11855 | * On Gen 8, SRM is now taking an extra dword to accommodate |
| 11856 | * 48bits addresses, and we need a NOOP for the batch size to |
| 11857 | * stay even. |
| 11858 | */ |
| 11859 | if (IS_GEN8(dev)) |
| 11860 | len += 2; |
| 11861 | } |
| 11862 | |
| 11863 | /* |
| 11864 | * BSpec MI_DISPLAY_FLIP for IVB: |
| 11865 | * "The full packet must be contained within the same cache line." |
| 11866 | * |
| 11867 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
| 11868 | * cacheline, if we ever start emitting more commands before |
| 11869 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
| 11870 | * then do the cacheline alignment, and finally emit the |
| 11871 | * MI_DISPLAY_FLIP. |
| 11872 | */ |
| 11873 | ret = intel_ring_cacheline_align(req); |
| 11874 | if (ret) |
| 11875 | return ret; |
| 11876 | |
| 11877 | ret = intel_ring_begin(req, len); |
| 11878 | if (ret) |
| 11879 | return ret; |
| 11880 | |
| 11881 | /* Unmask the flip-done completion message. Note that the bspec says that |
| 11882 | * we should do this for both the BCS and RCS, and that we must not unmask |
| 11883 | * more than one flip event at any time (or ensure that one flip message |
| 11884 | * can be sent by waiting for flip-done prior to queueing new flips). |
| 11885 | * Experimentation says that BCS works despite DERRMR masking all |
| 11886 | * flip-done completion events and that unmasking all planes at once |
| 11887 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
| 11888 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
| 11889 | */ |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11890 | if (req->engine->id == RCS) { |
| 11891 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 11892 | intel_ring_emit_reg(ring, DERRMR); |
| 11893 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11894 | DERRMR_PIPEB_PRI_FLIP_DONE | |
| 11895 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
| 11896 | if (IS_GEN8(dev)) |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11897 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11898 | MI_SRM_LRM_GLOBAL_GTT); |
| 11899 | else |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11900 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11901 | MI_SRM_LRM_GLOBAL_GTT); |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11902 | intel_ring_emit_reg(ring, DERRMR); |
Chris Wilson | bde13eb | 2016-08-15 10:49:07 +0100 | [diff] [blame] | 11903 | intel_ring_emit(ring, |
| 11904 | i915_ggtt_offset(req->engine->scratch) + 256); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11905 | if (IS_GEN8(dev)) { |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11906 | intel_ring_emit(ring, 0); |
| 11907 | intel_ring_emit(ring, MI_NOOP); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11908 | } |
| 11909 | } |
| 11910 | |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11911 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 11912 | intel_ring_emit(ring, fb->pitches[0] | |
| 11913 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 11914 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
| 11915 | intel_ring_emit(ring, (MI_NOOP)); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11916 | |
| 11917 | return 0; |
| 11918 | } |
| 11919 | |
| 11920 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
| 11921 | struct drm_i915_gem_object *obj) |
| 11922 | { |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 11923 | struct reservation_object *resv; |
| 11924 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11925 | /* |
| 11926 | * This is not being used for older platforms, because |
| 11927 | * non-availability of flip done interrupt forces us to use |
| 11928 | * CS flips. Older platforms derive flip done using some clever |
| 11929 | * tricks involving the flip_pending status bits and vblank irqs. |
| 11930 | * So using MMIO flips there would disrupt this mechanism. |
| 11931 | */ |
| 11932 | |
| 11933 | if (engine == NULL) |
| 11934 | return true; |
| 11935 | |
| 11936 | if (INTEL_GEN(engine->i915) < 5) |
| 11937 | return false; |
| 11938 | |
| 11939 | if (i915.use_mmio_flip < 0) |
| 11940 | return false; |
| 11941 | else if (i915.use_mmio_flip > 0) |
| 11942 | return true; |
| 11943 | else if (i915.enable_execlists) |
| 11944 | return true; |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 11945 | |
| 11946 | resv = i915_gem_object_get_dmabuf_resv(obj); |
| 11947 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11948 | return true; |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 11949 | |
Chris Wilson | d72d908 | 2016-08-04 07:52:31 +0100 | [diff] [blame] | 11950 | return engine != i915_gem_active_get_engine(&obj->last_write, |
| 11951 | &obj->base.dev->struct_mutex); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11952 | } |
| 11953 | |
| 11954 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
| 11955 | unsigned int rotation, |
| 11956 | struct intel_flip_work *work) |
| 11957 | { |
| 11958 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11959 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11960 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
| 11961 | const enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | d219677 | 2016-01-28 18:33:11 +0200 | [diff] [blame] | 11962 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11963 | |
| 11964 | ctl = I915_READ(PLANE_CTL(pipe, 0)); |
| 11965 | ctl &= ~PLANE_CTL_TILED_MASK; |
| 11966 | switch (fb->modifier[0]) { |
| 11967 | case DRM_FORMAT_MOD_NONE: |
| 11968 | break; |
| 11969 | case I915_FORMAT_MOD_X_TILED: |
| 11970 | ctl |= PLANE_CTL_TILED_X; |
| 11971 | break; |
| 11972 | case I915_FORMAT_MOD_Y_TILED: |
| 11973 | ctl |= PLANE_CTL_TILED_Y; |
| 11974 | break; |
| 11975 | case I915_FORMAT_MOD_Yf_TILED: |
| 11976 | ctl |= PLANE_CTL_TILED_YF; |
| 11977 | break; |
| 11978 | default: |
| 11979 | MISSING_CASE(fb->modifier[0]); |
| 11980 | } |
| 11981 | |
| 11982 | /* |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11983 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on |
| 11984 | * PLANE_SURF updates, the update is then guaranteed to be atomic. |
| 11985 | */ |
| 11986 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); |
| 11987 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
| 11988 | |
| 11989 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
| 11990 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 11991 | } |
| 11992 | |
| 11993 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
| 11994 | struct intel_flip_work *work) |
| 11995 | { |
| 11996 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 11997 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 11998 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 11999 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
| 12000 | u32 dspcntr; |
| 12001 | |
| 12002 | dspcntr = I915_READ(reg); |
| 12003 | |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 12004 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12005 | dspcntr |= DISPPLANE_TILED; |
| 12006 | else |
| 12007 | dspcntr &= ~DISPPLANE_TILED; |
| 12008 | |
| 12009 | I915_WRITE(reg, dspcntr); |
| 12010 | |
| 12011 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
| 12012 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
| 12013 | } |
| 12014 | |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 12015 | static void intel_mmio_flip_work_func(struct work_struct *w) |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 12016 | { |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 12017 | struct intel_flip_work *work = |
| 12018 | container_of(w, struct intel_flip_work, mmio_work); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12019 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
| 12020 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 12021 | struct intel_framebuffer *intel_fb = |
| 12022 | to_intel_framebuffer(crtc->base.primary->fb); |
| 12023 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 12024 | struct reservation_object *resv; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12025 | |
| 12026 | if (work->flip_queued_req) |
Chris Wilson | 776f323 | 2016-08-04 07:52:40 +0100 | [diff] [blame] | 12027 | WARN_ON(i915_wait_request(work->flip_queued_req, |
Chris Wilson | ea746f3 | 2016-09-09 14:11:49 +0100 | [diff] [blame] | 12028 | 0, NULL, NO_WAITBOOST)); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12029 | |
| 12030 | /* For framebuffer backed by dmabuf, wait for fence */ |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 12031 | resv = i915_gem_object_get_dmabuf_resv(obj); |
| 12032 | if (resv) |
| 12033 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12034 | MAX_SCHEDULE_TIMEOUT) < 0); |
| 12035 | |
| 12036 | intel_pipe_update_start(crtc); |
| 12037 | |
| 12038 | if (INTEL_GEN(dev_priv) >= 9) |
| 12039 | skl_do_mmio_flip(crtc, work->rotation, work); |
| 12040 | else |
| 12041 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ |
| 12042 | ilk_do_mmio_flip(crtc, work); |
| 12043 | |
| 12044 | intel_pipe_update_end(crtc, work); |
| 12045 | } |
| 12046 | |
| 12047 | static int intel_default_queue_flip(struct drm_device *dev, |
| 12048 | struct drm_crtc *crtc, |
| 12049 | struct drm_framebuffer *fb, |
| 12050 | struct drm_i915_gem_object *obj, |
| 12051 | struct drm_i915_gem_request *req, |
| 12052 | uint32_t flags) |
| 12053 | { |
| 12054 | return -ENODEV; |
| 12055 | } |
| 12056 | |
| 12057 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, |
| 12058 | struct intel_crtc *intel_crtc, |
| 12059 | struct intel_flip_work *work) |
| 12060 | { |
| 12061 | u32 addr, vblank; |
| 12062 | |
| 12063 | if (!atomic_read(&work->pending)) |
| 12064 | return false; |
| 12065 | |
| 12066 | smp_rmb(); |
| 12067 | |
| 12068 | vblank = intel_crtc_get_vblank_counter(intel_crtc); |
| 12069 | if (work->flip_ready_vblank == 0) { |
| 12070 | if (work->flip_queued_req && |
Chris Wilson | f69a02c | 2016-07-01 17:23:16 +0100 | [diff] [blame] | 12071 | !i915_gem_request_completed(work->flip_queued_req)) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12072 | return false; |
| 12073 | |
| 12074 | work->flip_ready_vblank = vblank; |
| 12075 | } |
| 12076 | |
| 12077 | if (vblank - work->flip_ready_vblank < 3) |
| 12078 | return false; |
| 12079 | |
| 12080 | /* Potential stall - if we see that the flip has happened, |
| 12081 | * assume a missed interrupt. */ |
| 12082 | if (INTEL_GEN(dev_priv) >= 4) |
| 12083 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); |
| 12084 | else |
| 12085 | addr = I915_READ(DSPADDR(intel_crtc->plane)); |
| 12086 | |
| 12087 | /* There is a potential issue here with a false positive after a flip |
| 12088 | * to the same address. We could address this by checking for a |
| 12089 | * non-incrementing frame counter. |
| 12090 | */ |
| 12091 | return addr == work->gtt_offset; |
| 12092 | } |
| 12093 | |
| 12094 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) |
| 12095 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 12096 | struct drm_device *dev = &dev_priv->drm; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12097 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12099 | struct intel_flip_work *work; |
| 12100 | |
| 12101 | WARN_ON(!in_interrupt()); |
| 12102 | |
| 12103 | if (crtc == NULL) |
| 12104 | return; |
| 12105 | |
| 12106 | spin_lock(&dev->event_lock); |
| 12107 | work = intel_crtc->flip_work; |
| 12108 | |
| 12109 | if (work != NULL && !is_mmio_work(work) && |
| 12110 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { |
| 12111 | WARN_ONCE(1, |
| 12112 | "Kicking stuck page flip: queued at %d, now %d\n", |
| 12113 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); |
| 12114 | page_flip_completed(intel_crtc); |
| 12115 | work = NULL; |
| 12116 | } |
| 12117 | |
| 12118 | if (work != NULL && !is_mmio_work(work) && |
| 12119 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) |
| 12120 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
| 12121 | spin_unlock(&dev->event_lock); |
| 12122 | } |
| 12123 | |
| 12124 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 12125 | struct drm_framebuffer *fb, |
| 12126 | struct drm_pending_vblank_event *event, |
| 12127 | uint32_t page_flip_flags) |
| 12128 | { |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12129 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 12130 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12131 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
| 12132 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 12133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 12134 | struct drm_plane *primary = crtc->primary; |
| 12135 | enum pipe pipe = intel_crtc->pipe; |
| 12136 | struct intel_flip_work *work; |
| 12137 | struct intel_engine_cs *engine; |
| 12138 | bool mmio_flip; |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 12139 | struct drm_i915_gem_request *request; |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 12140 | struct i915_vma *vma; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12141 | int ret; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 12142 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12143 | /* |
| 12144 | * drm_mode_page_flip_ioctl() should already catch this, but double |
| 12145 | * check to be safe. In the future we may enable pageflipping from |
| 12146 | * a disabled primary plane. |
| 12147 | */ |
| 12148 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) |
| 12149 | return -EBUSY; |
Maarten Lankhorst | a6747b7 | 2016-05-17 15:08:01 +0200 | [diff] [blame] | 12150 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12151 | /* Can't change pixel format via MI display flips. */ |
| 12152 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
| 12153 | return -EINVAL; |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12154 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12155 | /* |
| 12156 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
| 12157 | * Note that pitch changes could also affect these register. |
| 12158 | */ |
| 12159 | if (INTEL_INFO(dev)->gen > 3 && |
| 12160 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
| 12161 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
| 12162 | return -EINVAL; |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12163 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12164 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 12165 | goto out_hang; |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12166 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12167 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
| 12168 | if (work == NULL) |
| 12169 | return -ENOMEM; |
| 12170 | |
| 12171 | work->event = event; |
| 12172 | work->crtc = crtc; |
| 12173 | work->old_fb = old_fb; |
| 12174 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 12175 | |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 12176 | ret = drm_crtc_vblank_get(crtc); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12177 | if (ret) |
| 12178 | goto free_work; |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 12179 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12180 | /* We borrow the event spin lock for protecting flip_work */ |
| 12181 | spin_lock_irq(&dev->event_lock); |
| 12182 | if (intel_crtc->flip_work) { |
| 12183 | /* Before declaring the flip queue wedged, check if |
| 12184 | * the hardware completed the operation behind our backs. |
| 12185 | */ |
| 12186 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { |
| 12187 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); |
| 12188 | page_flip_completed(intel_crtc); |
| 12189 | } else { |
| 12190 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
| 12191 | spin_unlock_irq(&dev->event_lock); |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 12192 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12193 | drm_crtc_vblank_put(crtc); |
| 12194 | kfree(work); |
| 12195 | return -EBUSY; |
| 12196 | } |
| 12197 | } |
| 12198 | intel_crtc->flip_work = work; |
| 12199 | spin_unlock_irq(&dev->event_lock); |
Alex Goins | fd8e058 | 2015-11-25 18:43:38 -0800 | [diff] [blame] | 12200 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12201 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
| 12202 | flush_workqueue(dev_priv->wq); |
| 12203 | |
| 12204 | /* Reference the objects for the scheduled work. */ |
| 12205 | drm_framebuffer_reference(work->old_fb); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12206 | |
| 12207 | crtc->primary->fb = fb; |
| 12208 | update_state_fb(crtc->primary); |
Maarten Lankhorst | faf68d9 | 2016-06-14 14:24:20 +0200 | [diff] [blame] | 12209 | |
Chris Wilson | 25dc556 | 2016-07-20 13:31:52 +0100 | [diff] [blame] | 12210 | work->pending_flip_obj = i915_gem_object_get(obj); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12211 | |
| 12212 | ret = i915_mutex_lock_interruptible(dev); |
| 12213 | if (ret) |
| 12214 | goto cleanup; |
| 12215 | |
Chris Wilson | 8af29b0 | 2016-09-09 14:11:47 +0100 | [diff] [blame] | 12216 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 12217 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12218 | ret = -EIO; |
| 12219 | goto cleanup; |
| 12220 | } |
| 12221 | |
| 12222 | atomic_inc(&intel_crtc->unpin_work_count); |
| 12223 | |
| 12224 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 12225 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
| 12226 | |
| 12227 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 12228 | engine = &dev_priv->engine[BCS]; |
Ville Syrjälä | 72618eb | 2016-02-04 20:38:20 +0200 | [diff] [blame] | 12229 | if (fb->modifier[0] != old_fb->modifier[0]) |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12230 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
| 12231 | engine = NULL; |
| 12232 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
| 12233 | engine = &dev_priv->engine[BCS]; |
| 12234 | } else if (INTEL_INFO(dev)->gen >= 7) { |
Chris Wilson | d72d908 | 2016-08-04 07:52:31 +0100 | [diff] [blame] | 12235 | engine = i915_gem_active_get_engine(&obj->last_write, |
| 12236 | &obj->base.dev->struct_mutex); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12237 | if (engine == NULL || engine->id != RCS) |
| 12238 | engine = &dev_priv->engine[BCS]; |
| 12239 | } else { |
| 12240 | engine = &dev_priv->engine[RCS]; |
| 12241 | } |
| 12242 | |
| 12243 | mmio_flip = use_mmio_flip(engine, obj); |
| 12244 | |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 12245 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
| 12246 | if (IS_ERR(vma)) { |
| 12247 | ret = PTR_ERR(vma); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12248 | goto cleanup_pending; |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 12249 | } |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12250 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 12251 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12252 | work->gtt_offset += intel_crtc->dspaddr_offset; |
| 12253 | work->rotation = crtc->primary->state->rotation; |
| 12254 | |
Paulo Zanoni | 1f061316 | 2016-08-17 16:41:44 -0300 | [diff] [blame] | 12255 | /* |
| 12256 | * There's the potential that the next frame will not be compatible with |
| 12257 | * FBC, so we want to call pre_update() before the actual page flip. |
| 12258 | * The problem is that pre_update() caches some information about the fb |
| 12259 | * object, so we want to do this only after the object is pinned. Let's |
| 12260 | * be on the safe side and do this immediately before scheduling the |
| 12261 | * flip. |
| 12262 | */ |
| 12263 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, |
| 12264 | to_intel_plane_state(primary->state)); |
| 12265 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12266 | if (mmio_flip) { |
| 12267 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); |
| 12268 | |
Chris Wilson | d72d908 | 2016-08-04 07:52:31 +0100 | [diff] [blame] | 12269 | work->flip_queued_req = i915_gem_active_get(&obj->last_write, |
| 12270 | &obj->base.dev->struct_mutex); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12271 | schedule_work(&work->mmio_work); |
| 12272 | } else { |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 12273 | request = i915_gem_request_alloc(engine, engine->last_context); |
| 12274 | if (IS_ERR(request)) { |
| 12275 | ret = PTR_ERR(request); |
| 12276 | goto cleanup_unpin; |
| 12277 | } |
| 12278 | |
Chris Wilson | a2bc469 | 2016-09-09 14:11:56 +0100 | [diff] [blame] | 12279 | ret = i915_gem_request_await_object(request, obj, false); |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 12280 | if (ret) |
| 12281 | goto cleanup_request; |
| 12282 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12283 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
| 12284 | page_flip_flags); |
| 12285 | if (ret) |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 12286 | goto cleanup_request; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12287 | |
| 12288 | intel_mark_page_flip_active(intel_crtc, work); |
| 12289 | |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 12290 | work->flip_queued_req = i915_gem_request_get(request); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12291 | i915_add_request_no_flush(request); |
Maarten Lankhorst | 143f73b3 | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 12292 | } |
| 12293 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12294 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
| 12295 | to_intel_plane(primary)->frontbuffer_bit); |
| 12296 | mutex_unlock(&dev->struct_mutex); |
| 12297 | |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 12298 | intel_frontbuffer_flip_prepare(to_i915(dev), |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12299 | to_intel_plane(primary)->frontbuffer_bit); |
| 12300 | |
| 12301 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 12302 | |
| 12303 | return 0; |
| 12304 | |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 12305 | cleanup_request: |
| 12306 | i915_add_request_no_flush(request); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12307 | cleanup_unpin: |
| 12308 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
| 12309 | cleanup_pending: |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12310 | atomic_dec(&intel_crtc->unpin_work_count); |
| 12311 | mutex_unlock(&dev->struct_mutex); |
| 12312 | cleanup: |
| 12313 | crtc->primary->fb = old_fb; |
| 12314 | update_state_fb(crtc->primary); |
| 12315 | |
Chris Wilson | 34911fd | 2016-07-20 13:31:54 +0100 | [diff] [blame] | 12316 | i915_gem_object_put_unlocked(obj); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12317 | drm_framebuffer_unreference(work->old_fb); |
| 12318 | |
| 12319 | spin_lock_irq(&dev->event_lock); |
| 12320 | intel_crtc->flip_work = NULL; |
| 12321 | spin_unlock_irq(&dev->event_lock); |
| 12322 | |
| 12323 | drm_crtc_vblank_put(crtc); |
| 12324 | free_work: |
| 12325 | kfree(work); |
| 12326 | |
| 12327 | if (ret == -EIO) { |
| 12328 | struct drm_atomic_state *state; |
| 12329 | struct drm_plane_state *plane_state; |
| 12330 | |
| 12331 | out_hang: |
| 12332 | state = drm_atomic_state_alloc(dev); |
| 12333 | if (!state) |
| 12334 | return -ENOMEM; |
| 12335 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
| 12336 | |
| 12337 | retry: |
| 12338 | plane_state = drm_atomic_get_plane_state(state, primary); |
| 12339 | ret = PTR_ERR_OR_ZERO(plane_state); |
| 12340 | if (!ret) { |
| 12341 | drm_atomic_set_fb_for_plane(plane_state, fb); |
| 12342 | |
| 12343 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); |
| 12344 | if (!ret) |
| 12345 | ret = drm_atomic_commit(state); |
| 12346 | } |
| 12347 | |
| 12348 | if (ret == -EDEADLK) { |
| 12349 | drm_modeset_backoff(state->acquire_ctx); |
| 12350 | drm_atomic_state_clear(state); |
| 12351 | goto retry; |
| 12352 | } |
| 12353 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 12354 | drm_atomic_state_put(state); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12355 | |
| 12356 | if (ret == 0 && event) { |
| 12357 | spin_lock_irq(&dev->event_lock); |
| 12358 | drm_crtc_send_vblank_event(crtc, event); |
| 12359 | spin_unlock_irq(&dev->event_lock); |
| 12360 | } |
| 12361 | } |
| 12362 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 12363 | } |
| 12364 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12365 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12366 | /** |
| 12367 | * intel_wm_need_update - Check whether watermarks need updating |
| 12368 | * @plane: drm plane |
| 12369 | * @state: new plane state |
| 12370 | * |
| 12371 | * Check current plane state versus the new one to determine whether |
| 12372 | * watermarks need to be recalculated. |
| 12373 | * |
| 12374 | * Returns true or false. |
| 12375 | */ |
| 12376 | static bool intel_wm_need_update(struct drm_plane *plane, |
| 12377 | struct drm_plane_state *state) |
| 12378 | { |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 12379 | struct intel_plane_state *new = to_intel_plane_state(state); |
| 12380 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); |
| 12381 | |
| 12382 | /* Update watermarks on tiling or size changes. */ |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 12383 | if (new->base.visible != cur->base.visible) |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 12384 | return true; |
| 12385 | |
| 12386 | if (!cur->base.fb || !new->base.fb) |
| 12387 | return false; |
| 12388 | |
| 12389 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || |
| 12390 | cur->base.rotation != new->base.rotation || |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 12391 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
| 12392 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || |
| 12393 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || |
| 12394 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12395 | return true; |
| 12396 | |
| 12397 | return false; |
| 12398 | } |
| 12399 | |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 12400 | static bool needs_scaling(struct intel_plane_state *state) |
| 12401 | { |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 12402 | int src_w = drm_rect_width(&state->base.src) >> 16; |
| 12403 | int src_h = drm_rect_height(&state->base.src) >> 16; |
| 12404 | int dst_w = drm_rect_width(&state->base.dst); |
| 12405 | int dst_h = drm_rect_height(&state->base.dst); |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 12406 | |
| 12407 | return (src_w != dst_w || src_h != dst_h); |
| 12408 | } |
| 12409 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12410 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
| 12411 | struct drm_plane_state *plane_state) |
| 12412 | { |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 12413 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12414 | struct drm_crtc *crtc = crtc_state->crtc; |
| 12415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 12416 | struct drm_plane *plane = plane_state->plane; |
| 12417 | struct drm_device *dev = crtc->dev; |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 12418 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12419 | struct intel_plane_state *old_plane_state = |
| 12420 | to_intel_plane_state(plane->state); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12421 | bool mode_changed = needs_modeset(crtc_state); |
| 12422 | bool was_crtc_enabled = crtc->state->active; |
| 12423 | bool is_crtc_enabled = crtc_state->active; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12424 | bool turn_off, turn_on, visible, was_visible; |
| 12425 | struct drm_framebuffer *fb = plane_state->fb; |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 12426 | int ret; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12427 | |
Chris Wilson | 8411499 | 2016-07-02 15:36:06 +0100 | [diff] [blame] | 12428 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12429 | ret = skl_update_scaler_plane( |
| 12430 | to_intel_crtc_state(crtc_state), |
| 12431 | to_intel_plane_state(plane_state)); |
| 12432 | if (ret) |
| 12433 | return ret; |
| 12434 | } |
| 12435 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 12436 | was_visible = old_plane_state->base.visible; |
| 12437 | visible = to_intel_plane_state(plane_state)->base.visible; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12438 | |
| 12439 | if (!was_crtc_enabled && WARN_ON(was_visible)) |
| 12440 | was_visible = false; |
| 12441 | |
Maarten Lankhorst | 35c08f4 | 2015-12-03 14:31:07 +0100 | [diff] [blame] | 12442 | /* |
| 12443 | * Visibility is calculated as if the crtc was on, but |
| 12444 | * after scaler setup everything depends on it being off |
| 12445 | * when the crtc isn't active. |
Ville Syrjälä | f818ffe | 2016-04-29 17:31:18 +0300 | [diff] [blame] | 12446 | * |
| 12447 | * FIXME this is wrong for watermarks. Watermarks should also |
| 12448 | * be computed as if the pipe would be active. Perhaps move |
| 12449 | * per-plane wm computation to the .check_plane() hook, and |
| 12450 | * only combine the results from all planes in the current place? |
Maarten Lankhorst | 35c08f4 | 2015-12-03 14:31:07 +0100 | [diff] [blame] | 12451 | */ |
| 12452 | if (!is_crtc_enabled) |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 12453 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12454 | |
| 12455 | if (!was_visible && !visible) |
| 12456 | return 0; |
| 12457 | |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 12458 | if (fb != old_plane_state->base.fb) |
| 12459 | pipe_config->fb_changed = true; |
| 12460 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12461 | turn_off = was_visible && (!visible || mode_changed); |
| 12462 | turn_on = visible && (!was_visible || mode_changed); |
| 12463 | |
Ville Syrjälä | 72660ce | 2016-05-27 20:59:20 +0300 | [diff] [blame] | 12464 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 12465 | intel_crtc->base.base.id, |
| 12466 | intel_crtc->base.name, |
Ville Syrjälä | 72660ce | 2016-05-27 20:59:20 +0300 | [diff] [blame] | 12467 | plane->base.id, plane->name, |
| 12468 | fb ? fb->base.id : -1); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12469 | |
Ville Syrjälä | 72660ce | 2016-05-27 20:59:20 +0300 | [diff] [blame] | 12470 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
| 12471 | plane->base.id, plane->name, |
| 12472 | was_visible, visible, |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12473 | turn_off, turn_on, mode_changed); |
| 12474 | |
Ville Syrjälä | caed361 | 2016-03-09 19:07:25 +0200 | [diff] [blame] | 12475 | if (turn_on) { |
| 12476 | pipe_config->update_wm_pre = true; |
| 12477 | |
| 12478 | /* must disable cxsr around plane enable/disable */ |
| 12479 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
| 12480 | pipe_config->disable_cxsr = true; |
| 12481 | } else if (turn_off) { |
| 12482 | pipe_config->update_wm_post = true; |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 12483 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 12484 | /* must disable cxsr around plane enable/disable */ |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 12485 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 12486 | pipe_config->disable_cxsr = true; |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 12487 | } else if (intel_wm_need_update(plane, plane_state)) { |
Ville Syrjälä | caed361 | 2016-03-09 19:07:25 +0200 | [diff] [blame] | 12488 | /* FIXME bollocks */ |
| 12489 | pipe_config->update_wm_pre = true; |
| 12490 | pipe_config->update_wm_post = true; |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 12491 | } |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12492 | |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 12493 | /* Pre-gen9 platforms need two-step watermark updates */ |
Ville Syrjälä | caed361 | 2016-03-09 19:07:25 +0200 | [diff] [blame] | 12494 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
| 12495 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 12496 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
| 12497 | |
Rodrigo Vivi | 8be6ca8 | 2015-08-24 16:38:23 -0700 | [diff] [blame] | 12498 | if (visible || was_visible) |
Maarten Lankhorst | cd202f6 | 2016-03-09 10:35:44 +0100 | [diff] [blame] | 12499 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 12500 | |
Maarten Lankhorst | 31ae71f | 2016-03-09 10:35:45 +0100 | [diff] [blame] | 12501 | /* |
| 12502 | * WaCxSRDisabledForSpriteScaling:ivb |
| 12503 | * |
| 12504 | * cstate->update_wm was already set above, so this flag will |
| 12505 | * take effect when we commit and program watermarks. |
| 12506 | */ |
| 12507 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && |
| 12508 | needs_scaling(to_intel_plane_state(plane_state)) && |
| 12509 | !needs_scaling(old_plane_state)) |
| 12510 | pipe_config->disable_lp_wm = true; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12511 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 12512 | return 0; |
| 12513 | } |
| 12514 | |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12515 | static bool encoders_cloneable(const struct intel_encoder *a, |
| 12516 | const struct intel_encoder *b) |
| 12517 | { |
| 12518 | /* masks could be asymmetric, so check both ways */ |
| 12519 | return a == b || (a->cloneable & (1 << b->type) && |
| 12520 | b->cloneable & (1 << a->type)); |
| 12521 | } |
| 12522 | |
| 12523 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
| 12524 | struct intel_crtc *crtc, |
| 12525 | struct intel_encoder *encoder) |
| 12526 | { |
| 12527 | struct intel_encoder *source_encoder; |
| 12528 | struct drm_connector *connector; |
| 12529 | struct drm_connector_state *connector_state; |
| 12530 | int i; |
| 12531 | |
| 12532 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12533 | if (connector_state->crtc != &crtc->base) |
| 12534 | continue; |
| 12535 | |
| 12536 | source_encoder = |
| 12537 | to_intel_encoder(connector_state->best_encoder); |
| 12538 | if (!encoders_cloneable(encoder, source_encoder)) |
| 12539 | return false; |
| 12540 | } |
| 12541 | |
| 12542 | return true; |
| 12543 | } |
| 12544 | |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12545 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
| 12546 | struct drm_crtc_state *crtc_state) |
| 12547 | { |
Maarten Lankhorst | cf5a15b | 2015-06-15 12:33:41 +0200 | [diff] [blame] | 12548 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 12549 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | cf5a15b | 2015-06-15 12:33:41 +0200 | [diff] [blame] | 12551 | struct intel_crtc_state *pipe_config = |
| 12552 | to_intel_crtc_state(crtc_state); |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12553 | struct drm_atomic_state *state = crtc_state->state; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12554 | int ret; |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12555 | bool mode_changed = needs_modeset(crtc_state); |
| 12556 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 12557 | if (mode_changed && !crtc_state->active) |
Ville Syrjälä | caed361 | 2016-03-09 19:07:25 +0200 | [diff] [blame] | 12558 | pipe_config->update_wm_post = true; |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 12559 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 12560 | if (mode_changed && crtc_state->enable && |
| 12561 | dev_priv->display.crtc_compute_clock && |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 12562 | !WARN_ON(pipe_config->shared_dpll)) { |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 12563 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
| 12564 | pipe_config); |
| 12565 | if (ret) |
| 12566 | return ret; |
| 12567 | } |
| 12568 | |
Lionel Landwerlin | 82cf435 | 2016-03-16 10:57:16 +0000 | [diff] [blame] | 12569 | if (crtc_state->color_mgmt_changed) { |
| 12570 | ret = intel_color_check(crtc, crtc_state); |
| 12571 | if (ret) |
| 12572 | return ret; |
Lionel Landwerlin | ed2eebb | 2016-05-25 14:30:41 +0100 | [diff] [blame] | 12573 | |
| 12574 | /* |
| 12575 | * Changing color management on Intel hardware is |
| 12576 | * handled as part of planes update. |
| 12577 | */ |
| 12578 | crtc_state->planes_changed = true; |
Lionel Landwerlin | 82cf435 | 2016-03-16 10:57:16 +0000 | [diff] [blame] | 12579 | } |
| 12580 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 12581 | ret = 0; |
Matt Roper | 86c8bbb | 2015-09-24 15:53:16 -0700 | [diff] [blame] | 12582 | if (dev_priv->display.compute_pipe_wm) { |
Maarten Lankhorst | e3bddde | 2016-03-01 11:07:22 +0100 | [diff] [blame] | 12583 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 12584 | if (ret) { |
| 12585 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); |
Matt Roper | 86c8bbb | 2015-09-24 15:53:16 -0700 | [diff] [blame] | 12586 | return ret; |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 12587 | } |
| 12588 | } |
| 12589 | |
| 12590 | if (dev_priv->display.compute_intermediate_wm && |
| 12591 | !to_intel_atomic_state(state)->skip_intermediate_wm) { |
| 12592 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) |
| 12593 | return 0; |
| 12594 | |
| 12595 | /* |
| 12596 | * Calculate 'intermediate' watermarks that satisfy both the |
| 12597 | * old state and the new state. We can program these |
| 12598 | * immediately. |
| 12599 | */ |
| 12600 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, |
| 12601 | intel_crtc, |
| 12602 | pipe_config); |
| 12603 | if (ret) { |
| 12604 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); |
| 12605 | return ret; |
| 12606 | } |
Ville Syrjälä | e3d5457 | 2016-05-13 10:10:42 -0700 | [diff] [blame] | 12607 | } else if (dev_priv->display.compute_intermediate_wm) { |
| 12608 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) |
| 12609 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; |
Matt Roper | 86c8bbb | 2015-09-24 15:53:16 -0700 | [diff] [blame] | 12610 | } |
| 12611 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 12612 | if (INTEL_INFO(dev)->gen >= 9) { |
| 12613 | if (mode_changed) |
| 12614 | ret = skl_update_scaler_crtc(pipe_config); |
| 12615 | |
| 12616 | if (!ret) |
| 12617 | ret = intel_atomic_setup_scalers(dev, intel_crtc, |
| 12618 | pipe_config); |
| 12619 | } |
| 12620 | |
| 12621 | return ret; |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12622 | } |
| 12623 | |
Jani Nikula | 65b38e0 | 2015-04-13 11:26:56 +0300 | [diff] [blame] | 12624 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 12625 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 12626 | .atomic_begin = intel_begin_crtc_commit, |
| 12627 | .atomic_flush = intel_finish_crtc_commit, |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12628 | .atomic_check = intel_crtc_atomic_check, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 12629 | }; |
| 12630 | |
Ander Conselvan de Oliveira | d29b2f9 | 2015-03-20 16:18:05 +0200 | [diff] [blame] | 12631 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
| 12632 | { |
| 12633 | struct intel_connector *connector; |
| 12634 | |
| 12635 | for_each_intel_connector(dev, connector) { |
Daniel Vetter | 8863dc7 | 2016-05-06 15:39:03 +0200 | [diff] [blame] | 12636 | if (connector->base.state->crtc) |
| 12637 | drm_connector_unreference(&connector->base); |
| 12638 | |
Ander Conselvan de Oliveira | d29b2f9 | 2015-03-20 16:18:05 +0200 | [diff] [blame] | 12639 | if (connector->base.encoder) { |
| 12640 | connector->base.state->best_encoder = |
| 12641 | connector->base.encoder; |
| 12642 | connector->base.state->crtc = |
| 12643 | connector->base.encoder->crtc; |
Daniel Vetter | 8863dc7 | 2016-05-06 15:39:03 +0200 | [diff] [blame] | 12644 | |
| 12645 | drm_connector_reference(&connector->base); |
Ander Conselvan de Oliveira | d29b2f9 | 2015-03-20 16:18:05 +0200 | [diff] [blame] | 12646 | } else { |
| 12647 | connector->base.state->best_encoder = NULL; |
| 12648 | connector->base.state->crtc = NULL; |
| 12649 | } |
| 12650 | } |
| 12651 | } |
| 12652 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12653 | static void |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 12654 | connected_sink_compute_bpp(struct intel_connector *connector, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12655 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12656 | { |
Ville Syrjälä | 6a2a5c5 | 2016-09-28 16:51:42 +0300 | [diff] [blame] | 12657 | const struct drm_display_info *info = &connector->base.display_info; |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12658 | int bpp = pipe_config->pipe_bpp; |
| 12659 | |
| 12660 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
Ville Syrjälä | 6a2a5c5 | 2016-09-28 16:51:42 +0300 | [diff] [blame] | 12661 | connector->base.base.id, |
| 12662 | connector->base.name); |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12663 | |
| 12664 | /* Don't use an invalid EDID bpc value */ |
Ville Syrjälä | 6a2a5c5 | 2016-09-28 16:51:42 +0300 | [diff] [blame] | 12665 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12666 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
Ville Syrjälä | 6a2a5c5 | 2016-09-28 16:51:42 +0300 | [diff] [blame] | 12667 | bpp, info->bpc * 3); |
| 12668 | pipe_config->pipe_bpp = info->bpc * 3; |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12669 | } |
| 12670 | |
Mario Kleiner | 196f954 | 2016-07-06 12:05:45 +0200 | [diff] [blame] | 12671 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
Ville Syrjälä | 6a2a5c5 | 2016-09-28 16:51:42 +0300 | [diff] [blame] | 12672 | if (info->bpc == 0 && bpp > 24) { |
Mario Kleiner | 196f954 | 2016-07-06 12:05:45 +0200 | [diff] [blame] | 12673 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
| 12674 | bpp); |
| 12675 | pipe_config->pipe_bpp = 24; |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12676 | } |
| 12677 | } |
| 12678 | |
| 12679 | static int |
| 12680 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12681 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12682 | { |
| 12683 | struct drm_device *dev = crtc->base.dev; |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12684 | struct drm_atomic_state *state; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12685 | struct drm_connector *connector; |
| 12686 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12687 | int bpp, i; |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12688 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 12689 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12690 | bpp = 10*3; |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12691 | else if (INTEL_INFO(dev)->gen >= 5) |
| 12692 | bpp = 12*3; |
| 12693 | else |
| 12694 | bpp = 8*3; |
| 12695 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12696 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12697 | pipe_config->pipe_bpp = bpp; |
| 12698 | |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12699 | state = pipe_config->base.state; |
| 12700 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12701 | /* Clamp display bpp to EDID value */ |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12702 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12703 | if (connector_state->crtc != &crtc->base) |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12704 | continue; |
| 12705 | |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12706 | connected_sink_compute_bpp(to_intel_connector(connector), |
| 12707 | pipe_config); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12708 | } |
| 12709 | |
| 12710 | return bpp; |
| 12711 | } |
| 12712 | |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 12713 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
| 12714 | { |
| 12715 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
| 12716 | "type: 0x%x flags: 0x%x\n", |
Damien Lespiau | 1342830 | 2013-09-25 16:45:36 +0100 | [diff] [blame] | 12717 | mode->crtc_clock, |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 12718 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
| 12719 | mode->crtc_hsync_end, mode->crtc_htotal, |
| 12720 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
| 12721 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
| 12722 | } |
| 12723 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12724 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12725 | struct intel_crtc_state *pipe_config, |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12726 | const char *context) |
| 12727 | { |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12728 | struct drm_device *dev = crtc->base.dev; |
| 12729 | struct drm_plane *plane; |
| 12730 | struct intel_plane *intel_plane; |
| 12731 | struct intel_plane_state *state; |
| 12732 | struct drm_framebuffer *fb; |
| 12733 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 12734 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
| 12735 | crtc->base.base.id, crtc->base.name, |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12736 | context, pipe_config, pipe_name(crtc->pipe)); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12737 | |
Jani Nikula | da20563 | 2016-03-15 21:51:10 +0200 | [diff] [blame] | 12738 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12739 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
| 12740 | pipe_config->pipe_bpp, pipe_config->dither); |
| 12741 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 12742 | pipe_config->has_pch_encoder, |
| 12743 | pipe_config->fdi_lanes, |
| 12744 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
| 12745 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
| 12746 | pipe_config->fdi_m_n.tu); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12747 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 12748 | intel_crtc_has_dp_encoder(pipe_config), |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12749 | pipe_config->lane_count, |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 12750 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
| 12751 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
| 12752 | pipe_config->dp_m_n.tu); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12753 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12754 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 12755 | intel_crtc_has_dp_encoder(pipe_config), |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12756 | pipe_config->lane_count, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12757 | pipe_config->dp_m2_n2.gmch_m, |
| 12758 | pipe_config->dp_m2_n2.gmch_n, |
| 12759 | pipe_config->dp_m2_n2.link_m, |
| 12760 | pipe_config->dp_m2_n2.link_n, |
| 12761 | pipe_config->dp_m2_n2.tu); |
| 12762 | |
Daniel Vetter | 55072d1 | 2014-11-20 16:10:28 +0100 | [diff] [blame] | 12763 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
| 12764 | pipe_config->has_audio, |
| 12765 | pipe_config->has_infoframe); |
| 12766 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12767 | DRM_DEBUG_KMS("requested mode:\n"); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12768 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12769 | DRM_DEBUG_KMS("adjusted mode:\n"); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12770 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
| 12771 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); |
Ville Syrjälä | d71b8d4 | 2013-09-06 23:29:08 +0300 | [diff] [blame] | 12772 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 12773 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
| 12774 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
Tvrtko Ursulin | 0ec463d | 2015-05-13 16:51:08 +0100 | [diff] [blame] | 12775 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
| 12776 | crtc->num_scalers, |
| 12777 | pipe_config->scaler_state.scaler_users, |
| 12778 | pipe_config->scaler_state.scaler_id); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12779 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
| 12780 | pipe_config->gmch_pfit.control, |
| 12781 | pipe_config->gmch_pfit.pgm_ratios, |
| 12782 | pipe_config->gmch_pfit.lvds_border_bits); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 12783 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12784 | pipe_config->pch_pfit.pos, |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 12785 | pipe_config->pch_pfit.size, |
| 12786 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 12787 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 12788 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12789 | |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12790 | if (IS_BROXTON(dev)) { |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 12791 | DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12792 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
Imre Deak | c845333 | 2015-06-18 17:25:55 +0300 | [diff] [blame] | 12793 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12794 | pipe_config->dpll_hw_state.ebb0, |
Imre Deak | 05712c1 | 2015-06-18 17:25:54 +0300 | [diff] [blame] | 12795 | pipe_config->dpll_hw_state.ebb4, |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12796 | pipe_config->dpll_hw_state.pll0, |
| 12797 | pipe_config->dpll_hw_state.pll1, |
| 12798 | pipe_config->dpll_hw_state.pll2, |
| 12799 | pipe_config->dpll_hw_state.pll3, |
| 12800 | pipe_config->dpll_hw_state.pll6, |
| 12801 | pipe_config->dpll_hw_state.pll8, |
Imre Deak | 05712c1 | 2015-06-18 17:25:54 +0300 | [diff] [blame] | 12802 | pipe_config->dpll_hw_state.pll9, |
Imre Deak | c845333 | 2015-06-18 17:25:55 +0300 | [diff] [blame] | 12803 | pipe_config->dpll_hw_state.pll10, |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12804 | pipe_config->dpll_hw_state.pcsdw12); |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 12805 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 12806 | DRM_DEBUG_KMS("dpll_hw_state: " |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12807 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12808 | pipe_config->dpll_hw_state.ctrl1, |
| 12809 | pipe_config->dpll_hw_state.cfgcr1, |
| 12810 | pipe_config->dpll_hw_state.cfgcr2); |
| 12811 | } else if (HAS_DDI(dev)) { |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 12812 | DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 12813 | pipe_config->dpll_hw_state.wrpll, |
| 12814 | pipe_config->dpll_hw_state.spll); |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12815 | } else { |
| 12816 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " |
| 12817 | "fp0: 0x%x, fp1: 0x%x\n", |
| 12818 | pipe_config->dpll_hw_state.dpll, |
| 12819 | pipe_config->dpll_hw_state.dpll_md, |
| 12820 | pipe_config->dpll_hw_state.fp0, |
| 12821 | pipe_config->dpll_hw_state.fp1); |
| 12822 | } |
| 12823 | |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12824 | DRM_DEBUG_KMS("planes on this crtc\n"); |
| 12825 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
Eric Engestrom | d382814 | 2016-08-15 16:29:55 +0100 | [diff] [blame] | 12826 | char *format_name; |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12827 | intel_plane = to_intel_plane(plane); |
| 12828 | if (intel_plane->pipe != crtc->pipe) |
| 12829 | continue; |
| 12830 | |
| 12831 | state = to_intel_plane_state(plane->state); |
| 12832 | fb = state->base.fb; |
| 12833 | if (!fb) { |
Ville Syrjälä | 1d577e0 | 2016-05-27 20:59:25 +0300 | [diff] [blame] | 12834 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
| 12835 | plane->base.id, plane->name, state->scaler_id); |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12836 | continue; |
| 12837 | } |
| 12838 | |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 12839 | format_name = drm_get_format_name(fb->pixel_format); |
| 12840 | |
Ville Syrjälä | 1d577e0 | 2016-05-27 20:59:25 +0300 | [diff] [blame] | 12841 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
| 12842 | plane->base.id, plane->name); |
| 12843 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 12844 | fb->base.id, fb->width, fb->height, format_name); |
Ville Syrjälä | 1d577e0 | 2016-05-27 20:59:25 +0300 | [diff] [blame] | 12845 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", |
| 12846 | state->scaler_id, |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 12847 | state->base.src.x1 >> 16, |
| 12848 | state->base.src.y1 >> 16, |
| 12849 | drm_rect_width(&state->base.src) >> 16, |
| 12850 | drm_rect_height(&state->base.src) >> 16, |
| 12851 | state->base.dst.x1, state->base.dst.y1, |
| 12852 | drm_rect_width(&state->base.dst), |
| 12853 | drm_rect_height(&state->base.dst)); |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 12854 | |
| 12855 | kfree(format_name); |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12856 | } |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12857 | } |
| 12858 | |
Ander Conselvan de Oliveira | 5448a00 | 2015-04-02 14:47:59 +0300 | [diff] [blame] | 12859 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12860 | { |
Ander Conselvan de Oliveira | 5448a00 | 2015-04-02 14:47:59 +0300 | [diff] [blame] | 12861 | struct drm_device *dev = state->dev; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12862 | struct drm_connector *connector; |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12863 | unsigned int used_ports = 0; |
Ville Syrjälä | 477321e | 2016-07-28 17:50:40 +0300 | [diff] [blame] | 12864 | unsigned int used_mst_ports = 0; |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12865 | |
| 12866 | /* |
| 12867 | * Walk the connector list instead of the encoder |
| 12868 | * list to detect the problem on ddi platforms |
| 12869 | * where there's just one encoder per digital port. |
| 12870 | */ |
Ville Syrjälä | 0bff485 | 2015-12-10 18:22:31 +0200 | [diff] [blame] | 12871 | drm_for_each_connector(connector, dev) { |
| 12872 | struct drm_connector_state *connector_state; |
| 12873 | struct intel_encoder *encoder; |
| 12874 | |
| 12875 | connector_state = drm_atomic_get_existing_connector_state(state, connector); |
| 12876 | if (!connector_state) |
| 12877 | connector_state = connector->state; |
| 12878 | |
Ander Conselvan de Oliveira | 5448a00 | 2015-04-02 14:47:59 +0300 | [diff] [blame] | 12879 | if (!connector_state->best_encoder) |
| 12880 | continue; |
| 12881 | |
| 12882 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12883 | |
| 12884 | WARN_ON(!connector_state->crtc); |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12885 | |
| 12886 | switch (encoder->type) { |
| 12887 | unsigned int port_mask; |
| 12888 | case INTEL_OUTPUT_UNKNOWN: |
| 12889 | if (WARN_ON(!HAS_DDI(dev))) |
| 12890 | break; |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 12891 | case INTEL_OUTPUT_DP: |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12892 | case INTEL_OUTPUT_HDMI: |
| 12893 | case INTEL_OUTPUT_EDP: |
| 12894 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; |
| 12895 | |
| 12896 | /* the same port mustn't appear more than once */ |
| 12897 | if (used_ports & port_mask) |
| 12898 | return false; |
| 12899 | |
| 12900 | used_ports |= port_mask; |
Ville Syrjälä | 477321e | 2016-07-28 17:50:40 +0300 | [diff] [blame] | 12901 | break; |
| 12902 | case INTEL_OUTPUT_DP_MST: |
| 12903 | used_mst_ports |= |
| 12904 | 1 << enc_to_mst(&encoder->base)->primary->port; |
| 12905 | break; |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12906 | default: |
| 12907 | break; |
| 12908 | } |
| 12909 | } |
| 12910 | |
Ville Syrjälä | 477321e | 2016-07-28 17:50:40 +0300 | [diff] [blame] | 12911 | /* can't mix MST and SST/HDMI on the same port */ |
| 12912 | if (used_ports & used_mst_ports) |
| 12913 | return false; |
| 12914 | |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12915 | return true; |
| 12916 | } |
| 12917 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12918 | static void |
| 12919 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) |
| 12920 | { |
| 12921 | struct drm_crtc_state tmp_state; |
Chandra Konduru | 663a364 | 2015-04-07 15:28:41 -0700 | [diff] [blame] | 12922 | struct intel_crtc_scaler_state scaler_state; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12923 | struct intel_dpll_hw_state dpll_hw_state; |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 12924 | struct intel_shared_dpll *shared_dpll; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 12925 | bool force_thru; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12926 | |
Ander Conselvan de Oliveira | 7546a38 | 2015-05-20 09:03:27 +0300 | [diff] [blame] | 12927 | /* FIXME: before the switch to atomic started, a new pipe_config was |
| 12928 | * kzalloc'd. Code that depends on any field being zero should be |
| 12929 | * fixed, so that the crtc_state can be safely duplicated. For now, |
| 12930 | * only fields that are know to not cause problems are preserved. */ |
| 12931 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12932 | tmp_state = crtc_state->base; |
Chandra Konduru | 663a364 | 2015-04-07 15:28:41 -0700 | [diff] [blame] | 12933 | scaler_state = crtc_state->scaler_state; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12934 | shared_dpll = crtc_state->shared_dpll; |
| 12935 | dpll_hw_state = crtc_state->dpll_hw_state; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 12936 | force_thru = crtc_state->pch_pfit.force_thru; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12937 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12938 | memset(crtc_state, 0, sizeof *crtc_state); |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12939 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12940 | crtc_state->base = tmp_state; |
Chandra Konduru | 663a364 | 2015-04-07 15:28:41 -0700 | [diff] [blame] | 12941 | crtc_state->scaler_state = scaler_state; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12942 | crtc_state->shared_dpll = shared_dpll; |
| 12943 | crtc_state->dpll_hw_state = dpll_hw_state; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 12944 | crtc_state->pch_pfit.force_thru = force_thru; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12945 | } |
| 12946 | |
Ander Conselvan de Oliveira | 548ee15 | 2015-04-21 17:13:02 +0300 | [diff] [blame] | 12947 | static int |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 12948 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 12949 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12950 | { |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 12951 | struct drm_atomic_state *state = pipe_config->base.state; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12952 | struct intel_encoder *encoder; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12953 | struct drm_connector *connector; |
Ander Conselvan de Oliveira | 0b90187 | 2015-03-20 16:18:08 +0200 | [diff] [blame] | 12954 | struct drm_connector_state *connector_state; |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12955 | int base_bpp, ret = -EINVAL; |
Ander Conselvan de Oliveira | 0b90187 | 2015-03-20 16:18:08 +0200 | [diff] [blame] | 12956 | int i; |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 12957 | bool retry = true; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12958 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12959 | clear_intel_crtc_state(pipe_config); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12960 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 12961 | pipe_config->cpu_transcoder = |
| 12962 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 12963 | |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12964 | /* |
| 12965 | * Sanitize sync polarity flags based on requested ones. If neither |
| 12966 | * positive or negative polarity is requested, treat this as meaning |
| 12967 | * negative polarity. |
| 12968 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12969 | if (!(pipe_config->base.adjusted_mode.flags & |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12970 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12971 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12972 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12973 | if (!(pipe_config->base.adjusted_mode.flags & |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12974 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12975 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12976 | |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12977 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
| 12978 | pipe_config); |
| 12979 | if (base_bpp < 0) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12980 | goto fail; |
| 12981 | |
Ville Syrjälä | e41a56b | 2013-10-01 22:52:14 +0300 | [diff] [blame] | 12982 | /* |
| 12983 | * Determine the real pipe dimensions. Note that stereo modes can |
| 12984 | * increase the actual pipe size due to the frame doubling and |
| 12985 | * insertion of additional space for blanks between the frame. This |
| 12986 | * is stored in the crtc timings. We use the requested mode to do this |
| 12987 | * computation to clearly distinguish it from the adjusted mode, which |
| 12988 | * can be changed by the connectors in the below retry loop. |
| 12989 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12990 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
Gustavo Padovan | ecb7e16 | 2014-12-01 15:40:09 -0800 | [diff] [blame] | 12991 | &pipe_config->pipe_src_w, |
| 12992 | &pipe_config->pipe_src_h); |
Ville Syrjälä | e41a56b | 2013-10-01 22:52:14 +0300 | [diff] [blame] | 12993 | |
Ville Syrjälä | 253c84c | 2016-06-22 21:57:01 +0300 | [diff] [blame] | 12994 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12995 | if (connector_state->crtc != crtc) |
| 12996 | continue; |
| 12997 | |
| 12998 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12999 | |
Ville Syrjälä | e25148d | 2016-06-22 21:57:09 +0300 | [diff] [blame] | 13000 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
| 13001 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
| 13002 | goto fail; |
| 13003 | } |
| 13004 | |
Ville Syrjälä | 253c84c | 2016-06-22 21:57:01 +0300 | [diff] [blame] | 13005 | /* |
| 13006 | * Determine output_types before calling the .compute_config() |
| 13007 | * hooks so that the hooks can use this information safely. |
| 13008 | */ |
| 13009 | pipe_config->output_types |= 1 << encoder->type; |
| 13010 | } |
| 13011 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 13012 | encoder_retry: |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 13013 | /* Ensure the port clock defaults are reset when retrying. */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 13014 | pipe_config->port_clock = 0; |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 13015 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 13016 | |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 13017 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13018 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
| 13019 | CRTC_STEREO_DOUBLE); |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 13020 | |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 13021 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
| 13022 | * adjust it according to limitations or connector properties, and also |
| 13023 | * a chance to reject the mode entirely. |
| 13024 | */ |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 13025 | for_each_connector_in_state(state, connector, connector_state, i) { |
Ander Conselvan de Oliveira | 0b90187 | 2015-03-20 16:18:08 +0200 | [diff] [blame] | 13026 | if (connector_state->crtc != crtc) |
| 13027 | continue; |
| 13028 | |
| 13029 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 13030 | |
Maarten Lankhorst | 0a478c2 | 2016-08-09 17:04:05 +0200 | [diff] [blame] | 13031 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
Daniel Vetter | efea6e8 | 2013-07-21 21:36:59 +0200 | [diff] [blame] | 13032 | DRM_DEBUG_KMS("Encoder config failure\n"); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 13033 | goto fail; |
| 13034 | } |
| 13035 | } |
| 13036 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 13037 | /* Set default port clock if not overwritten by the encoder. Needs to be |
| 13038 | * done afterwards in case the encoder adjusts the mode. */ |
| 13039 | if (!pipe_config->port_clock) |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13040 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 13041 | * pipe_config->pixel_multiplier; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 13042 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 13043 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 13044 | if (ret < 0) { |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 13045 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
| 13046 | goto fail; |
| 13047 | } |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 13048 | |
| 13049 | if (ret == RETRY) { |
| 13050 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
| 13051 | ret = -EINVAL; |
| 13052 | goto fail; |
| 13053 | } |
| 13054 | |
| 13055 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
| 13056 | retry = false; |
| 13057 | goto encoder_retry; |
| 13058 | } |
| 13059 | |
Daniel Vetter | e8fa427 | 2015-08-12 11:43:34 +0200 | [diff] [blame] | 13060 | /* Dithering seems to not pass-through bits correctly when it should, so |
| 13061 | * only enable it on 6bpc panels. */ |
| 13062 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; |
Daniel Vetter | 62f0ace | 2015-08-26 18:57:26 +0200 | [diff] [blame] | 13063 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 13064 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 13065 | |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 13066 | fail: |
Ander Conselvan de Oliveira | 548ee15 | 2015-04-21 17:13:02 +0300 | [diff] [blame] | 13067 | return ret; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 13068 | } |
| 13069 | |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13070 | static void |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 13071 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13072 | { |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13073 | struct drm_crtc *crtc; |
| 13074 | struct drm_crtc_state *crtc_state; |
Maarten Lankhorst | 8a75d15 | 2015-07-13 16:30:14 +0200 | [diff] [blame] | 13075 | int i; |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 13076 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 13077 | /* Double check state. */ |
Maarten Lankhorst | 8a75d15 | 2015-07-13 16:30:14 +0200 | [diff] [blame] | 13078 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | 3cb480b | 2015-06-01 12:49:49 +0200 | [diff] [blame] | 13079 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
Maarten Lankhorst | fc467a22 | 2015-06-01 12:50:07 +0200 | [diff] [blame] | 13080 | |
| 13081 | /* Update hwmode for vblank functions */ |
| 13082 | if (crtc->state->active) |
| 13083 | crtc->hwmode = crtc->state->adjusted_mode; |
| 13084 | else |
| 13085 | crtc->hwmode.crtc_clock = 0; |
Maarten Lankhorst | 61067a5 | 2015-09-23 16:29:36 +0200 | [diff] [blame] | 13086 | |
| 13087 | /* |
| 13088 | * Update legacy state to satisfy fbc code. This can |
| 13089 | * be removed when fbc uses the atomic state. |
| 13090 | */ |
| 13091 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { |
| 13092 | struct drm_plane_state *plane_state = crtc->primary->state; |
| 13093 | |
| 13094 | crtc->primary->fb = plane_state->fb; |
| 13095 | crtc->x = plane_state->src_x >> 16; |
| 13096 | crtc->y = plane_state->src_y >> 16; |
| 13097 | } |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 13098 | } |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 13099 | } |
| 13100 | |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 13101 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 13102 | { |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 13103 | int diff; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 13104 | |
| 13105 | if (clock1 == clock2) |
| 13106 | return true; |
| 13107 | |
| 13108 | if (!clock1 || !clock2) |
| 13109 | return false; |
| 13110 | |
| 13111 | diff = abs(clock1 - clock2); |
| 13112 | |
| 13113 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
| 13114 | return true; |
| 13115 | |
| 13116 | return false; |
| 13117 | } |
| 13118 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13119 | static bool |
| 13120 | intel_compare_m_n(unsigned int m, unsigned int n, |
| 13121 | unsigned int m2, unsigned int n2, |
| 13122 | bool exact) |
| 13123 | { |
| 13124 | if (m == m2 && n == n2) |
| 13125 | return true; |
| 13126 | |
| 13127 | if (exact || !m || !n || !m2 || !n2) |
| 13128 | return false; |
| 13129 | |
| 13130 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); |
| 13131 | |
Maarten Lankhorst | 31d10b5 | 2016-01-06 13:54:43 +0100 | [diff] [blame] | 13132 | if (n > n2) { |
| 13133 | while (n > n2) { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13134 | m2 <<= 1; |
| 13135 | n2 <<= 1; |
| 13136 | } |
Maarten Lankhorst | 31d10b5 | 2016-01-06 13:54:43 +0100 | [diff] [blame] | 13137 | } else if (n < n2) { |
| 13138 | while (n < n2) { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13139 | m <<= 1; |
| 13140 | n <<= 1; |
| 13141 | } |
| 13142 | } |
| 13143 | |
Maarten Lankhorst | 31d10b5 | 2016-01-06 13:54:43 +0100 | [diff] [blame] | 13144 | if (n != n2) |
| 13145 | return false; |
| 13146 | |
| 13147 | return intel_fuzzy_clock_check(m, m2); |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13148 | } |
| 13149 | |
| 13150 | static bool |
| 13151 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, |
| 13152 | struct intel_link_m_n *m2_n2, |
| 13153 | bool adjust) |
| 13154 | { |
| 13155 | if (m_n->tu == m2_n2->tu && |
| 13156 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, |
| 13157 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && |
| 13158 | intel_compare_m_n(m_n->link_m, m_n->link_n, |
| 13159 | m2_n2->link_m, m2_n2->link_n, !adjust)) { |
| 13160 | if (adjust) |
| 13161 | *m2_n2 = *m_n; |
| 13162 | |
| 13163 | return true; |
| 13164 | } |
| 13165 | |
| 13166 | return false; |
| 13167 | } |
| 13168 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 13169 | static bool |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 13170 | intel_pipe_config_compare(struct drm_device *dev, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 13171 | struct intel_crtc_state *current_config, |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13172 | struct intel_crtc_state *pipe_config, |
| 13173 | bool adjust) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 13174 | { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13175 | bool ret = true; |
| 13176 | |
| 13177 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ |
| 13178 | do { \ |
| 13179 | if (!adjust) \ |
| 13180 | DRM_ERROR(fmt, ##__VA_ARGS__); \ |
| 13181 | else \ |
| 13182 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ |
| 13183 | } while (0) |
| 13184 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13185 | #define PIPE_CONF_CHECK_X(name) \ |
| 13186 | if (current_config->name != pipe_config->name) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13187 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13188 | "(expected 0x%08x, found 0x%08x)\n", \ |
| 13189 | current_config->name, \ |
| 13190 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13191 | ret = false; \ |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13192 | } |
| 13193 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 13194 | #define PIPE_CONF_CHECK_I(name) \ |
| 13195 | if (current_config->name != pipe_config->name) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13196 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 13197 | "(expected %i, found %i)\n", \ |
| 13198 | current_config->name, \ |
| 13199 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13200 | ret = false; \ |
| 13201 | } |
| 13202 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13203 | #define PIPE_CONF_CHECK_P(name) \ |
| 13204 | if (current_config->name != pipe_config->name) { \ |
| 13205 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 13206 | "(expected %p, found %p)\n", \ |
| 13207 | current_config->name, \ |
| 13208 | pipe_config->name); \ |
| 13209 | ret = false; \ |
| 13210 | } |
| 13211 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13212 | #define PIPE_CONF_CHECK_M_N(name) \ |
| 13213 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 13214 | &pipe_config->name,\ |
| 13215 | adjust)) { \ |
| 13216 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 13217 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 13218 | "found tu %i, gmch %i/%i link %i/%i)\n", \ |
| 13219 | current_config->name.tu, \ |
| 13220 | current_config->name.gmch_m, \ |
| 13221 | current_config->name.gmch_n, \ |
| 13222 | current_config->name.link_m, \ |
| 13223 | current_config->name.link_n, \ |
| 13224 | pipe_config->name.tu, \ |
| 13225 | pipe_config->name.gmch_m, \ |
| 13226 | pipe_config->name.gmch_n, \ |
| 13227 | pipe_config->name.link_m, \ |
| 13228 | pipe_config->name.link_n); \ |
| 13229 | ret = false; \ |
| 13230 | } |
| 13231 | |
Daniel Vetter | 55c561a | 2016-03-30 11:34:36 +0200 | [diff] [blame] | 13232 | /* This is required for BDW+ where there is only one set of registers for |
| 13233 | * switching between high and low RR. |
| 13234 | * This macro can be used whenever a comparison has to be made between one |
| 13235 | * hw state and multiple sw state variables. |
| 13236 | */ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13237 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
| 13238 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 13239 | &pipe_config->name, adjust) && \ |
| 13240 | !intel_compare_link_m_n(¤t_config->alt_name, \ |
| 13241 | &pipe_config->name, adjust)) { \ |
| 13242 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 13243 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 13244 | "or tu %i gmch %i/%i link %i/%i, " \ |
| 13245 | "found tu %i, gmch %i/%i link %i/%i)\n", \ |
| 13246 | current_config->name.tu, \ |
| 13247 | current_config->name.gmch_m, \ |
| 13248 | current_config->name.gmch_n, \ |
| 13249 | current_config->name.link_m, \ |
| 13250 | current_config->name.link_n, \ |
| 13251 | current_config->alt_name.tu, \ |
| 13252 | current_config->alt_name.gmch_m, \ |
| 13253 | current_config->alt_name.gmch_n, \ |
| 13254 | current_config->alt_name.link_m, \ |
| 13255 | current_config->alt_name.link_n, \ |
| 13256 | pipe_config->name.tu, \ |
| 13257 | pipe_config->name.gmch_m, \ |
| 13258 | pipe_config->name.gmch_n, \ |
| 13259 | pipe_config->name.link_m, \ |
| 13260 | pipe_config->name.link_n); \ |
| 13261 | ret = false; \ |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 13262 | } |
| 13263 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13264 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
| 13265 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13266 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13267 | "(expected %i, found %i)\n", \ |
| 13268 | current_config->name & (mask), \ |
| 13269 | pipe_config->name & (mask)); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13270 | ret = false; \ |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13271 | } |
| 13272 | |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 13273 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
| 13274 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13275 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 13276 | "(expected %i, found %i)\n", \ |
| 13277 | current_config->name, \ |
| 13278 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13279 | ret = false; \ |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 13280 | } |
| 13281 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13282 | #define PIPE_CONF_QUIRK(quirk) \ |
| 13283 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
| 13284 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 13285 | PIPE_CONF_CHECK_I(cpu_transcoder); |
| 13286 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 13287 | PIPE_CONF_CHECK_I(has_pch_encoder); |
| 13288 | PIPE_CONF_CHECK_I(fdi_lanes); |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13289 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 13290 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 13291 | PIPE_CONF_CHECK_I(lane_count); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 13292 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 13293 | |
| 13294 | if (INTEL_INFO(dev)->gen < 8) { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13295 | PIPE_CONF_CHECK_M_N(dp_m_n); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 13296 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13297 | if (current_config->has_drrs) |
| 13298 | PIPE_CONF_CHECK_M_N(dp_m2_n2); |
| 13299 | } else |
| 13300 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 13301 | |
Ville Syrjälä | 253c84c | 2016-06-22 21:57:01 +0300 | [diff] [blame] | 13302 | PIPE_CONF_CHECK_X(output_types); |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 13303 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13304 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
| 13305 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); |
| 13306 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); |
| 13307 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); |
| 13308 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); |
| 13309 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13310 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13311 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
| 13312 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); |
| 13313 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); |
| 13314 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); |
| 13315 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); |
| 13316 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13317 | |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 13318 | PIPE_CONF_CHECK_I(pixel_multiplier); |
Daniel Vetter | 6897b4b5 | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 13319 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 13320 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 13321 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 13322 | PIPE_CONF_CHECK_I(limited_color_range); |
Jesse Barnes | e43823e | 2014-11-05 14:26:08 -0800 | [diff] [blame] | 13323 | PIPE_CONF_CHECK_I(has_infoframe); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 13324 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 13325 | PIPE_CONF_CHECK_I(has_audio); |
| 13326 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13327 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13328 | DRM_MODE_FLAG_INTERLACE); |
| 13329 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13330 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13331 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13332 | DRM_MODE_FLAG_PHSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13333 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13334 | DRM_MODE_FLAG_NHSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13335 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13336 | DRM_MODE_FLAG_PVSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13337 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13338 | DRM_MODE_FLAG_NVSYNC); |
| 13339 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 13340 | |
Ville Syrjälä | 333b8ca | 2015-09-03 21:50:16 +0300 | [diff] [blame] | 13341 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
Daniel Vetter | e2ff2d4 | 2015-07-15 14:15:50 +0200 | [diff] [blame] | 13342 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
| 13343 | if (INTEL_INFO(dev)->gen < 4) |
Ville Syrjälä | 7f7d8dd | 2016-03-15 16:40:07 +0200 | [diff] [blame] | 13344 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
Ville Syrjälä | 333b8ca | 2015-09-03 21:50:16 +0300 | [diff] [blame] | 13345 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
Daniel Vetter | 9953599 | 2014-04-13 12:00:33 +0200 | [diff] [blame] | 13346 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 13347 | if (!adjust) { |
| 13348 | PIPE_CONF_CHECK_I(pipe_src_w); |
| 13349 | PIPE_CONF_CHECK_I(pipe_src_h); |
| 13350 | |
| 13351 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
| 13352 | if (current_config->pch_pfit.enabled) { |
| 13353 | PIPE_CONF_CHECK_X(pch_pfit.pos); |
| 13354 | PIPE_CONF_CHECK_X(pch_pfit.size); |
| 13355 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 13356 | |
Maarten Lankhorst | 7aefe2b | 2015-09-14 11:30:10 +0200 | [diff] [blame] | 13357 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
| 13358 | } |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 13359 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 13360 | /* BDW+ don't expose a synchronous way to read the state */ |
| 13361 | if (IS_HASWELL(dev)) |
| 13362 | PIPE_CONF_CHECK_I(ips_enabled); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 13363 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 13364 | PIPE_CONF_CHECK_I(double_wide); |
| 13365 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13366 | PIPE_CONF_CHECK_P(shared_dpll); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13367 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 13368 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13369 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
| 13370 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 13371 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 13372 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
Damien Lespiau | 3f4cd19 | 2014-11-13 14:55:21 +0000 | [diff] [blame] | 13373 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
| 13374 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); |
| 13375 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 13376 | |
Ville Syrjälä | 47eacba | 2016-04-12 22:14:35 +0300 | [diff] [blame] | 13377 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
| 13378 | PIPE_CONF_CHECK_X(dsi_pll.div); |
| 13379 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 13380 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
| 13381 | PIPE_CONF_CHECK_I(pipe_bpp); |
| 13382 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13383 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
Jesse Barnes | a9a7e98 | 2014-01-20 14:18:04 -0800 | [diff] [blame] | 13384 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 13385 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13386 | #undef PIPE_CONF_CHECK_X |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 13387 | #undef PIPE_CONF_CHECK_I |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13388 | #undef PIPE_CONF_CHECK_P |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 13389 | #undef PIPE_CONF_CHECK_FLAGS |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 13390 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 13391 | #undef PIPE_CONF_QUIRK |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13392 | #undef INTEL_ERR_OR_DBG_KMS |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 13393 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13394 | return ret; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 13395 | } |
| 13396 | |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 13397 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
| 13398 | const struct intel_crtc_state *pipe_config) |
| 13399 | { |
| 13400 | if (pipe_config->has_pch_encoder) { |
Ville Syrjälä | 21a727b | 2016-02-17 21:41:10 +0200 | [diff] [blame] | 13401 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 13402 | &pipe_config->fdi_m_n); |
| 13403 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; |
| 13404 | |
| 13405 | /* |
| 13406 | * FDI already provided one idea for the dotclock. |
| 13407 | * Yell if the encoder disagrees. |
| 13408 | */ |
| 13409 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), |
| 13410 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
| 13411 | fdi_dotclock, dotclock); |
| 13412 | } |
| 13413 | } |
| 13414 | |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13415 | static void verify_wm_state(struct drm_crtc *crtc, |
| 13416 | struct drm_crtc_state *new_state) |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13417 | { |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13418 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 13419 | struct drm_i915_private *dev_priv = to_i915(dev); |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13420 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13421 | struct skl_ddb_entry *hw_entry, *sw_entry; |
| 13422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13423 | const enum pipe pipe = intel_crtc->pipe; |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13424 | int plane; |
| 13425 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13426 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13427 | return; |
| 13428 | |
| 13429 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
| 13430 | sw_ddb = &dev_priv->wm.skl_hw.ddb; |
| 13431 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13432 | /* planes */ |
| 13433 | for_each_plane(dev_priv, pipe, plane) { |
| 13434 | hw_entry = &hw_ddb.plane[pipe][plane]; |
| 13435 | sw_entry = &sw_ddb->plane[pipe][plane]; |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13436 | |
| 13437 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
| 13438 | continue; |
| 13439 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13440 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
| 13441 | "(expected (%u,%u), found (%u,%u))\n", |
| 13442 | pipe_name(pipe), plane + 1, |
| 13443 | sw_entry->start, sw_entry->end, |
| 13444 | hw_entry->start, hw_entry->end); |
| 13445 | } |
| 13446 | |
Lyude | 2708249 | 2016-08-24 07:48:10 +0200 | [diff] [blame] | 13447 | /* |
| 13448 | * cursor |
| 13449 | * If the cursor plane isn't active, we may not have updated it's ddb |
| 13450 | * allocation. In that case since the ddb allocation will be updated |
| 13451 | * once the plane becomes visible, we can skip this check |
| 13452 | */ |
| 13453 | if (intel_crtc->cursor_addr) { |
| 13454 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
| 13455 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13456 | |
Lyude | 2708249 | 2016-08-24 07:48:10 +0200 | [diff] [blame] | 13457 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
| 13458 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
| 13459 | "(expected (%u,%u), found (%u,%u))\n", |
| 13460 | pipe_name(pipe), |
| 13461 | sw_entry->start, sw_entry->end, |
| 13462 | hw_entry->start, hw_entry->end); |
| 13463 | } |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13464 | } |
| 13465 | } |
| 13466 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13467 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13468 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13469 | { |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 13470 | struct drm_connector *connector; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13471 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13472 | drm_for_each_connector(connector, dev) { |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 13473 | struct drm_encoder *encoder = connector->encoder; |
| 13474 | struct drm_connector_state *state = connector->state; |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 13475 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13476 | if (state->crtc != crtc) |
| 13477 | continue; |
| 13478 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 13479 | intel_connector_verify_state(to_intel_connector(connector)); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13480 | |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 13481 | I915_STATE_WARN(state->best_encoder != encoder, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 13482 | "connector's atomic encoder doesn't match legacy encoder\n"); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13483 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13484 | } |
| 13485 | |
| 13486 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13487 | verify_encoder_state(struct drm_device *dev) |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13488 | { |
| 13489 | struct intel_encoder *encoder; |
| 13490 | struct intel_connector *connector; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13491 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 13492 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13493 | bool enabled = false; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13494 | enum pipe pipe; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13495 | |
| 13496 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
| 13497 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 13498 | encoder->base.name); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13499 | |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 13500 | for_each_intel_connector(dev, connector) { |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13501 | if (connector->base.state->best_encoder != &encoder->base) |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13502 | continue; |
| 13503 | enabled = true; |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 13504 | |
| 13505 | I915_STATE_WARN(connector->base.state->crtc != |
| 13506 | encoder->base.crtc, |
| 13507 | "connector's crtc doesn't match encoder crtc\n"); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13508 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 13509 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13510 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13511 | "encoder's enabled state mismatch " |
| 13512 | "(expected %i, found %i)\n", |
| 13513 | !!encoder->base.crtc, enabled); |
Maarten Lankhorst | 7c60d19 | 2015-08-05 12:37:04 +0200 | [diff] [blame] | 13514 | |
| 13515 | if (!encoder->base.crtc) { |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13516 | bool active; |
| 13517 | |
| 13518 | active = encoder->get_hw_state(encoder, &pipe); |
Maarten Lankhorst | 7c60d19 | 2015-08-05 12:37:04 +0200 | [diff] [blame] | 13519 | I915_STATE_WARN(active, |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13520 | "encoder detached but still enabled on pipe %c.\n", |
| 13521 | pipe_name(pipe)); |
Maarten Lankhorst | 7c60d19 | 2015-08-05 12:37:04 +0200 | [diff] [blame] | 13522 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13523 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13524 | } |
| 13525 | |
| 13526 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13527 | verify_crtc_state(struct drm_crtc *crtc, |
| 13528 | struct drm_crtc_state *old_crtc_state, |
| 13529 | struct drm_crtc_state *new_crtc_state) |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13530 | { |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13531 | struct drm_device *dev = crtc->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 13532 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13533 | struct intel_encoder *encoder; |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13534 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13535 | struct intel_crtc_state *pipe_config, *sw_config; |
| 13536 | struct drm_atomic_state *old_state; |
| 13537 | bool active; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13538 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13539 | old_state = old_crtc_state->state; |
Daniel Vetter | ec2dc6a | 2016-05-09 16:34:09 +0200 | [diff] [blame] | 13540 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13541 | pipe_config = to_intel_crtc_state(old_crtc_state); |
| 13542 | memset(pipe_config, 0, sizeof(*pipe_config)); |
| 13543 | pipe_config->base.crtc = crtc; |
| 13544 | pipe_config->base.state = old_state; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13545 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 13546 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13547 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13548 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13549 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13550 | /* hw state is inconsistent with the pipe quirk */ |
| 13551 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 13552 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 13553 | active = new_crtc_state->active; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13554 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13555 | I915_STATE_WARN(new_crtc_state->active != active, |
| 13556 | "crtc active state doesn't match with hw state " |
| 13557 | "(expected %i, found %i)\n", new_crtc_state->active, active); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13558 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13559 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
| 13560 | "transitional active state does not match atomic hw state " |
| 13561 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13562 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13563 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 13564 | enum pipe pipe; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13565 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13566 | active = encoder->get_hw_state(encoder, &pipe); |
| 13567 | I915_STATE_WARN(active != new_crtc_state->active, |
| 13568 | "[ENCODER:%i] active %i with crtc active %i\n", |
| 13569 | encoder->base.base.id, active, new_crtc_state->active); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13570 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13571 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
| 13572 | "Encoder connected to wrong pipe %c\n", |
| 13573 | pipe_name(pipe)); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13574 | |
Ville Syrjälä | 253c84c | 2016-06-22 21:57:01 +0300 | [diff] [blame] | 13575 | if (active) { |
| 13576 | pipe_config->output_types |= 1 << encoder->type; |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13577 | encoder->get_config(encoder, pipe_config); |
Ville Syrjälä | 253c84c | 2016-06-22 21:57:01 +0300 | [diff] [blame] | 13578 | } |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13579 | } |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13580 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13581 | if (!new_crtc_state->active) |
| 13582 | return; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13583 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13584 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13585 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13586 | sw_config = to_intel_crtc_state(crtc->state); |
| 13587 | if (!intel_pipe_config_compare(dev, sw_config, |
| 13588 | pipe_config, false)) { |
| 13589 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
| 13590 | intel_dump_pipe_config(intel_crtc, pipe_config, |
| 13591 | "[hw state]"); |
| 13592 | intel_dump_pipe_config(intel_crtc, sw_config, |
| 13593 | "[sw state]"); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13594 | } |
| 13595 | } |
| 13596 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13597 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13598 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
| 13599 | struct intel_shared_dpll *pll, |
| 13600 | struct drm_crtc *crtc, |
| 13601 | struct drm_crtc_state *new_state) |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13602 | { |
| 13603 | struct intel_dpll_hw_state dpll_hw_state; |
| 13604 | unsigned crtc_mask; |
| 13605 | bool active; |
| 13606 | |
| 13607 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
| 13608 | |
| 13609 | DRM_DEBUG_KMS("%s\n", pll->name); |
| 13610 | |
| 13611 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
| 13612 | |
| 13613 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
| 13614 | I915_STATE_WARN(!pll->on && pll->active_mask, |
| 13615 | "pll in active use but not on in sw tracking\n"); |
| 13616 | I915_STATE_WARN(pll->on && !pll->active_mask, |
| 13617 | "pll is on but not used by any active crtc\n"); |
| 13618 | I915_STATE_WARN(pll->on != active, |
| 13619 | "pll on state mismatch (expected %i, found %i)\n", |
| 13620 | pll->on, active); |
| 13621 | } |
| 13622 | |
| 13623 | if (!crtc) { |
| 13624 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
| 13625 | "more active pll users than references: %x vs %x\n", |
| 13626 | pll->active_mask, pll->config.crtc_mask); |
| 13627 | |
| 13628 | return; |
| 13629 | } |
| 13630 | |
| 13631 | crtc_mask = 1 << drm_crtc_index(crtc); |
| 13632 | |
| 13633 | if (new_state->active) |
| 13634 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), |
| 13635 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", |
| 13636 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); |
| 13637 | else |
| 13638 | I915_STATE_WARN(pll->active_mask & crtc_mask, |
| 13639 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", |
| 13640 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); |
| 13641 | |
| 13642 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
| 13643 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
| 13644 | crtc_mask, pll->config.crtc_mask); |
| 13645 | |
| 13646 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
| 13647 | &dpll_hw_state, |
| 13648 | sizeof(dpll_hw_state)), |
| 13649 | "pll hw state mismatch\n"); |
| 13650 | } |
| 13651 | |
| 13652 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13653 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
| 13654 | struct drm_crtc_state *old_crtc_state, |
| 13655 | struct drm_crtc_state *new_crtc_state) |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13656 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 13657 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13658 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
| 13659 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); |
| 13660 | |
| 13661 | if (new_state->shared_dpll) |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13662 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13663 | |
| 13664 | if (old_state->shared_dpll && |
| 13665 | old_state->shared_dpll != new_state->shared_dpll) { |
| 13666 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); |
| 13667 | struct intel_shared_dpll *pll = old_state->shared_dpll; |
| 13668 | |
| 13669 | I915_STATE_WARN(pll->active_mask & crtc_mask, |
| 13670 | "pll active mismatch (didn't expect pipe %c in active mask)\n", |
| 13671 | pipe_name(drm_crtc_index(crtc))); |
| 13672 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, |
| 13673 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
| 13674 | pipe_name(drm_crtc_index(crtc))); |
| 13675 | } |
| 13676 | } |
| 13677 | |
| 13678 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13679 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13680 | struct drm_crtc_state *old_state, |
| 13681 | struct drm_crtc_state *new_state) |
| 13682 | { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 13683 | if (!needs_modeset(new_state) && |
| 13684 | !to_intel_crtc_state(new_state)->update_pipe) |
| 13685 | return; |
| 13686 | |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13687 | verify_wm_state(crtc, new_state); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 13688 | verify_connector_state(crtc->dev, crtc); |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13689 | verify_crtc_state(crtc, old_state, new_state); |
| 13690 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13691 | } |
| 13692 | |
| 13693 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13694 | verify_disabled_dpll_state(struct drm_device *dev) |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13695 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 13696 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13697 | int i; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13698 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13699 | for (i = 0; i < dev_priv->num_shared_dpll; i++) |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13700 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13701 | } |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13702 | |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13703 | static void |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13704 | intel_modeset_verify_disabled(struct drm_device *dev) |
Maarten Lankhorst | e7c8454 | 2016-03-23 14:58:06 +0100 | [diff] [blame] | 13705 | { |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 13706 | verify_encoder_state(dev); |
| 13707 | verify_connector_state(dev, NULL); |
| 13708 | verify_disabled_dpll_state(dev); |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 13709 | } |
| 13710 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13711 | static void update_scanline_offset(struct intel_crtc *crtc) |
| 13712 | { |
| 13713 | struct drm_device *dev = crtc->base.dev; |
| 13714 | |
| 13715 | /* |
| 13716 | * The scanline counter increments at the leading edge of hsync. |
| 13717 | * |
| 13718 | * On most platforms it starts counting from vtotal-1 on the |
| 13719 | * first active line. That means the scanline counter value is |
| 13720 | * always one less than what we would expect. Ie. just after |
| 13721 | * start of vblank, which also occurs at start of hsync (on the |
| 13722 | * last active line), the scanline counter will read vblank_start-1. |
| 13723 | * |
| 13724 | * On gen2 the scanline counter starts counting from 1 instead |
| 13725 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
| 13726 | * to keep the value positive), instead of adding one. |
| 13727 | * |
| 13728 | * On HSW+ the behaviour of the scanline counter depends on the output |
| 13729 | * type. For DP ports it behaves like most other platforms, but on HDMI |
| 13730 | * there's an extra 1 line difference. So we need to add two instead of |
| 13731 | * one to the value. |
| 13732 | */ |
| 13733 | if (IS_GEN2(dev)) { |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 13734 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13735 | int vtotal; |
| 13736 | |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 13737 | vtotal = adjusted_mode->crtc_vtotal; |
| 13738 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13739 | vtotal /= 2; |
| 13740 | |
| 13741 | crtc->scanline_offset = vtotal - 1; |
| 13742 | } else if (HAS_DDI(dev) && |
Ville Syrjälä | 2d84d2b | 2016-06-22 21:57:02 +0300 | [diff] [blame] | 13743 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13744 | crtc->scanline_offset = 2; |
| 13745 | } else |
| 13746 | crtc->scanline_offset = 1; |
| 13747 | } |
| 13748 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13749 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13750 | { |
Ander Conselvan de Oliveira | 225da59 | 2015-04-02 14:47:57 +0300 | [diff] [blame] | 13751 | struct drm_device *dev = state->dev; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13752 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13753 | struct intel_shared_dpll_config *shared_dpll = NULL; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13754 | struct drm_crtc *crtc; |
| 13755 | struct drm_crtc_state *crtc_state; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13756 | int i; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13757 | |
| 13758 | if (!dev_priv->display.crtc_compute_clock) |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13759 | return; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13760 | |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13761 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | fb1a38a | 2016-02-09 13:02:17 +0100 | [diff] [blame] | 13762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13763 | struct intel_shared_dpll *old_dpll = |
| 13764 | to_intel_crtc_state(crtc->state)->shared_dpll; |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13765 | |
Maarten Lankhorst | fb1a38a | 2016-02-09 13:02:17 +0100 | [diff] [blame] | 13766 | if (!needs_modeset(crtc_state)) |
Ander Conselvan de Oliveira | 225da59 | 2015-04-02 14:47:57 +0300 | [diff] [blame] | 13767 | continue; |
| 13768 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13769 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
Maarten Lankhorst | fb1a38a | 2016-02-09 13:02:17 +0100 | [diff] [blame] | 13770 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13771 | if (!old_dpll) |
Maarten Lankhorst | fb1a38a | 2016-02-09 13:02:17 +0100 | [diff] [blame] | 13772 | continue; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13773 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13774 | if (!shared_dpll) |
| 13775 | shared_dpll = intel_atomic_get_shared_dpll_state(state); |
| 13776 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 13777 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13778 | } |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13779 | } |
| 13780 | |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 13781 | /* |
| 13782 | * This implements the workaround described in the "notes" section of the mode |
| 13783 | * set sequence documentation. When going from no pipes or single pipe to |
| 13784 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
| 13785 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
| 13786 | */ |
| 13787 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) |
| 13788 | { |
| 13789 | struct drm_crtc_state *crtc_state; |
| 13790 | struct intel_crtc *intel_crtc; |
| 13791 | struct drm_crtc *crtc; |
| 13792 | struct intel_crtc_state *first_crtc_state = NULL; |
| 13793 | struct intel_crtc_state *other_crtc_state = NULL; |
| 13794 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; |
| 13795 | int i; |
| 13796 | |
| 13797 | /* look at all crtc's that are going to be enabled in during modeset */ |
| 13798 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13799 | intel_crtc = to_intel_crtc(crtc); |
| 13800 | |
| 13801 | if (!crtc_state->active || !needs_modeset(crtc_state)) |
| 13802 | continue; |
| 13803 | |
| 13804 | if (first_crtc_state) { |
| 13805 | other_crtc_state = to_intel_crtc_state(crtc_state); |
| 13806 | break; |
| 13807 | } else { |
| 13808 | first_crtc_state = to_intel_crtc_state(crtc_state); |
| 13809 | first_pipe = intel_crtc->pipe; |
| 13810 | } |
| 13811 | } |
| 13812 | |
| 13813 | /* No workaround needed? */ |
| 13814 | if (!first_crtc_state) |
| 13815 | return 0; |
| 13816 | |
| 13817 | /* w/a possibly needed, check how many crtc's are already enabled. */ |
| 13818 | for_each_intel_crtc(state->dev, intel_crtc) { |
| 13819 | struct intel_crtc_state *pipe_config; |
| 13820 | |
| 13821 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); |
| 13822 | if (IS_ERR(pipe_config)) |
| 13823 | return PTR_ERR(pipe_config); |
| 13824 | |
| 13825 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; |
| 13826 | |
| 13827 | if (!pipe_config->base.active || |
| 13828 | needs_modeset(&pipe_config->base)) |
| 13829 | continue; |
| 13830 | |
| 13831 | /* 2 or more enabled crtcs means no need for w/a */ |
| 13832 | if (enabled_pipe != INVALID_PIPE) |
| 13833 | return 0; |
| 13834 | |
| 13835 | enabled_pipe = intel_crtc->pipe; |
| 13836 | } |
| 13837 | |
| 13838 | if (enabled_pipe != INVALID_PIPE) |
| 13839 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; |
| 13840 | else if (other_crtc_state) |
| 13841 | other_crtc_state->hsw_workaround_pipe = first_pipe; |
| 13842 | |
| 13843 | return 0; |
| 13844 | } |
| 13845 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13846 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
| 13847 | { |
| 13848 | struct drm_crtc *crtc; |
| 13849 | struct drm_crtc_state *crtc_state; |
| 13850 | int ret = 0; |
| 13851 | |
| 13852 | /* add all active pipes to the state */ |
| 13853 | for_each_crtc(state->dev, crtc) { |
| 13854 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 13855 | if (IS_ERR(crtc_state)) |
| 13856 | return PTR_ERR(crtc_state); |
| 13857 | |
| 13858 | if (!crtc_state->active || needs_modeset(crtc_state)) |
| 13859 | continue; |
| 13860 | |
| 13861 | crtc_state->mode_changed = true; |
| 13862 | |
| 13863 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 13864 | if (ret) |
| 13865 | break; |
| 13866 | |
| 13867 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 13868 | if (ret) |
| 13869 | break; |
| 13870 | } |
| 13871 | |
| 13872 | return ret; |
| 13873 | } |
| 13874 | |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13875 | static int intel_modeset_checks(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13876 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13877 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 13878 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13879 | struct drm_crtc *crtc; |
| 13880 | struct drm_crtc_state *crtc_state; |
| 13881 | int ret = 0, i; |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13882 | |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 13883 | if (!check_digital_port_conflicts(state)) { |
| 13884 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
| 13885 | return -EINVAL; |
| 13886 | } |
| 13887 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13888 | intel_state->modeset = true; |
| 13889 | intel_state->active_crtcs = dev_priv->active_crtcs; |
| 13890 | |
| 13891 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13892 | if (crtc_state->active) |
| 13893 | intel_state->active_crtcs |= 1 << i; |
| 13894 | else |
| 13895 | intel_state->active_crtcs &= ~(1 << i); |
Matt Roper | 8b4a7d0 | 2016-05-12 07:06:00 -0700 | [diff] [blame] | 13896 | |
| 13897 | if (crtc_state->active != crtc->state->active) |
| 13898 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13899 | } |
| 13900 | |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13901 | /* |
| 13902 | * See if the config requires any additional preparation, e.g. |
| 13903 | * to adjust global state with pipes off. We need to do this |
| 13904 | * here so we can get the modeset_pipe updated config for the new |
| 13905 | * mode set on this crtc. For other crtcs we need to use the |
| 13906 | * adjusted_mode bits in the crtc directly. |
| 13907 | */ |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13908 | if (dev_priv->display.modeset_calc_cdclk) { |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 13909 | if (!intel_state->cdclk_pll_vco) |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 13910 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 13911 | if (!intel_state->cdclk_pll_vco) |
| 13912 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13913 | |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 13914 | ret = dev_priv->display.modeset_calc_cdclk(state); |
| 13915 | if (ret < 0) |
| 13916 | return ret; |
| 13917 | |
| 13918 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 13919 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13920 | ret = intel_modeset_all_pipes(state); |
| 13921 | |
| 13922 | if (ret < 0) |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13923 | return ret; |
Maarten Lankhorst | e8788cb | 2016-02-16 10:25:11 +0100 | [diff] [blame] | 13924 | |
| 13925 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", |
| 13926 | intel_state->cdclk, intel_state->dev_cdclk); |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13927 | } else |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 13928 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13929 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13930 | intel_modeset_clear_plls(state); |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13931 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13932 | if (IS_HASWELL(dev_priv)) |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13933 | return haswell_mode_set_planes_workaround(state); |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 13934 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13935 | return 0; |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13936 | } |
| 13937 | |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13938 | /* |
| 13939 | * Handle calculation of various watermark data at the end of the atomic check |
| 13940 | * phase. The code here should be run after the per-crtc and per-plane 'check' |
| 13941 | * handlers to ensure that all derived state has been updated. |
| 13942 | */ |
Matt Roper | 55994c2 | 2016-05-12 07:06:08 -0700 | [diff] [blame] | 13943 | static int calc_watermark_data(struct drm_atomic_state *state) |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13944 | { |
| 13945 | struct drm_device *dev = state->dev; |
Matt Roper | 98d3949 | 2016-05-12 07:06:03 -0700 | [diff] [blame] | 13946 | struct drm_i915_private *dev_priv = to_i915(dev); |
Matt Roper | 98d3949 | 2016-05-12 07:06:03 -0700 | [diff] [blame] | 13947 | |
| 13948 | /* Is there platform-specific watermark information to calculate? */ |
| 13949 | if (dev_priv->display.compute_global_watermarks) |
Matt Roper | 55994c2 | 2016-05-12 07:06:08 -0700 | [diff] [blame] | 13950 | return dev_priv->display.compute_global_watermarks(state); |
| 13951 | |
| 13952 | return 0; |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13953 | } |
| 13954 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13955 | /** |
| 13956 | * intel_atomic_check - validate state object |
| 13957 | * @dev: drm device |
| 13958 | * @state: state to validate |
| 13959 | */ |
| 13960 | static int intel_atomic_check(struct drm_device *dev, |
| 13961 | struct drm_atomic_state *state) |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13962 | { |
Paulo Zanoni | dd8b3bd | 2016-01-19 11:35:49 -0200 | [diff] [blame] | 13963 | struct drm_i915_private *dev_priv = to_i915(dev); |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13964 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13965 | struct drm_crtc *crtc; |
| 13966 | struct drm_crtc_state *crtc_state; |
| 13967 | int ret, i; |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13968 | bool any_ms = false; |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13969 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13970 | ret = drm_atomic_helper_check_modeset(dev, state); |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13971 | if (ret) |
| 13972 | return ret; |
| 13973 | |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13974 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13975 | struct intel_crtc_state *pipe_config = |
| 13976 | to_intel_crtc_state(crtc_state); |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 13977 | |
| 13978 | /* Catch I915_MODE_FLAG_INHERITED */ |
| 13979 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) |
| 13980 | crtc_state->mode_changed = true; |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13981 | |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13982 | if (!needs_modeset(crtc_state)) |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13983 | continue; |
| 13984 | |
Daniel Vetter | af4a879 | 2016-05-09 09:31:25 +0200 | [diff] [blame] | 13985 | if (!crtc_state->enable) { |
| 13986 | any_ms = true; |
| 13987 | continue; |
| 13988 | } |
| 13989 | |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13990 | /* FIXME: For only active_changed we shouldn't need to do any |
| 13991 | * state recomputation at all. */ |
| 13992 | |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 13993 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 13994 | if (ret) |
| 13995 | return ret; |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 13996 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13997 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
Maarten Lankhorst | 25aa1c3 | 2016-05-03 10:30:38 +0200 | [diff] [blame] | 13998 | if (ret) { |
| 13999 | intel_dump_pipe_config(to_intel_crtc(crtc), |
| 14000 | pipe_config, "[failed]"); |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 14001 | return ret; |
Maarten Lankhorst | 25aa1c3 | 2016-05-03 10:30:38 +0200 | [diff] [blame] | 14002 | } |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 14003 | |
Jani Nikula | 7383123 | 2015-11-19 10:26:30 +0200 | [diff] [blame] | 14004 | if (i915.fastboot && |
Paulo Zanoni | dd8b3bd | 2016-01-19 11:35:49 -0200 | [diff] [blame] | 14005 | intel_pipe_config_compare(dev, |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 14006 | to_intel_crtc_state(crtc->state), |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 14007 | pipe_config, true)) { |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 14008 | crtc_state->mode_changed = false; |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 14009 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 14010 | } |
| 14011 | |
Daniel Vetter | af4a879 | 2016-05-09 09:31:25 +0200 | [diff] [blame] | 14012 | if (needs_modeset(crtc_state)) |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 14013 | any_ms = true; |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 14014 | |
Daniel Vetter | af4a879 | 2016-05-09 09:31:25 +0200 | [diff] [blame] | 14015 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 14016 | if (ret) |
| 14017 | return ret; |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 14018 | |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 14019 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
| 14020 | needs_modeset(crtc_state) ? |
| 14021 | "[modeset]" : "[fastset]"); |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 14022 | } |
| 14023 | |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 14024 | if (any_ms) { |
| 14025 | ret = intel_modeset_checks(state); |
| 14026 | |
| 14027 | if (ret) |
| 14028 | return ret; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 14029 | } else |
Paulo Zanoni | dd8b3bd | 2016-01-19 11:35:49 -0200 | [diff] [blame] | 14030 | intel_state->cdclk = dev_priv->cdclk_freq; |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 14031 | |
Paulo Zanoni | dd8b3bd | 2016-01-19 11:35:49 -0200 | [diff] [blame] | 14032 | ret = drm_atomic_helper_check_planes(dev, state); |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 14033 | if (ret) |
| 14034 | return ret; |
| 14035 | |
Paulo Zanoni | f51be2e | 2016-01-19 11:35:50 -0200 | [diff] [blame] | 14036 | intel_fbc_choose_crtc(dev_priv, state); |
Matt Roper | 55994c2 | 2016-05-12 07:06:08 -0700 | [diff] [blame] | 14037 | return calc_watermark_data(state); |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 14038 | } |
| 14039 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14040 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
| 14041 | struct drm_atomic_state *state, |
Maarten Lankhorst | 81072bf | 2016-04-26 16:11:45 +0200 | [diff] [blame] | 14042 | bool nonblock) |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14043 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 14044 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14045 | struct drm_plane_state *plane_state; |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14046 | struct drm_crtc_state *crtc_state; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14047 | struct drm_plane *plane; |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14048 | struct drm_crtc *crtc; |
| 14049 | int i, ret; |
| 14050 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14051 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 14052 | if (state->legacy_cursor_update) |
| 14053 | continue; |
| 14054 | |
| 14055 | ret = intel_crtc_wait_for_pending_flips(crtc); |
| 14056 | if (ret) |
| 14057 | return ret; |
| 14058 | |
| 14059 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
| 14060 | flush_workqueue(dev_priv->wq); |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 14061 | } |
| 14062 | |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14063 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 14064 | if (ret) |
| 14065 | return ret; |
| 14066 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14067 | ret = drm_atomic_helper_prepare_planes(dev, state); |
Chris Wilson | f7e5838 | 2016-04-13 17:35:07 +0100 | [diff] [blame] | 14068 | mutex_unlock(&dev->struct_mutex); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14069 | |
Dave Airlie | 21daaee | 2016-05-05 09:56:30 +1000 | [diff] [blame] | 14070 | if (!ret && !nonblock) { |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14071 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 14072 | struct intel_plane_state *intel_plane_state = |
| 14073 | to_intel_plane_state(plane_state); |
| 14074 | |
| 14075 | if (!intel_plane_state->wait_req) |
| 14076 | continue; |
| 14077 | |
Chris Wilson | 776f323 | 2016-08-04 07:52:40 +0100 | [diff] [blame] | 14078 | ret = i915_wait_request(intel_plane_state->wait_req, |
Chris Wilson | ea746f3 | 2016-09-09 14:11:49 +0100 | [diff] [blame] | 14079 | I915_WAIT_INTERRUPTIBLE, |
| 14080 | NULL, NULL); |
Chris Wilson | f7e5838 | 2016-04-13 17:35:07 +0100 | [diff] [blame] | 14081 | if (ret) { |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 14082 | /* Any hang should be swallowed by the wait */ |
| 14083 | WARN_ON(ret == -EIO); |
Chris Wilson | f7e5838 | 2016-04-13 17:35:07 +0100 | [diff] [blame] | 14084 | mutex_lock(&dev->struct_mutex); |
| 14085 | drm_atomic_helper_cleanup_planes(dev, state); |
| 14086 | mutex_unlock(&dev->struct_mutex); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14087 | break; |
Chris Wilson | f7e5838 | 2016-04-13 17:35:07 +0100 | [diff] [blame] | 14088 | } |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14089 | } |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14090 | } |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14091 | |
| 14092 | return ret; |
| 14093 | } |
| 14094 | |
Maarten Lankhorst | a299141 | 2016-05-17 15:07:48 +0200 | [diff] [blame] | 14095 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
| 14096 | { |
| 14097 | struct drm_device *dev = crtc->base.dev; |
| 14098 | |
| 14099 | if (!dev->max_vblank_count) |
| 14100 | return drm_accurate_vblank_count(&crtc->base); |
| 14101 | |
| 14102 | return dev->driver->get_vblank_counter(dev, crtc->pipe); |
| 14103 | } |
| 14104 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14105 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
| 14106 | struct drm_i915_private *dev_priv, |
| 14107 | unsigned crtc_mask) |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 14108 | { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14109 | unsigned last_vblank_count[I915_MAX_PIPES]; |
| 14110 | enum pipe pipe; |
| 14111 | int ret; |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 14112 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14113 | if (!crtc_mask) |
| 14114 | return; |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 14115 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14116 | for_each_pipe(dev_priv, pipe) { |
| 14117 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 14118 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14119 | if (!((1 << pipe) & crtc_mask)) |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 14120 | continue; |
| 14121 | |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 14122 | ret = drm_crtc_vblank_get(crtc); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14123 | if (WARN_ON(ret != 0)) { |
| 14124 | crtc_mask &= ~(1 << pipe); |
| 14125 | continue; |
| 14126 | } |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 14127 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14128 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
| 14129 | } |
| 14130 | |
| 14131 | for_each_pipe(dev_priv, pipe) { |
| 14132 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 14133 | long lret; |
| 14134 | |
| 14135 | if (!((1 << pipe) & crtc_mask)) |
| 14136 | continue; |
| 14137 | |
| 14138 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
| 14139 | last_vblank_count[pipe] != |
| 14140 | drm_crtc_vblank_count(crtc), |
| 14141 | msecs_to_jiffies(50)); |
| 14142 | |
| 14143 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
| 14144 | |
| 14145 | drm_crtc_vblank_put(crtc); |
Maarten Lankhorst | d55dbd0 | 2016-05-17 15:08:04 +0200 | [diff] [blame] | 14146 | } |
| 14147 | } |
| 14148 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14149 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
Maarten Lankhorst | a6747b7 | 2016-05-17 15:08:01 +0200 | [diff] [blame] | 14150 | { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14151 | /* fb updated, need to unpin old fb */ |
| 14152 | if (crtc_state->fb_changed) |
| 14153 | return true; |
Maarten Lankhorst | a6747b7 | 2016-05-17 15:08:01 +0200 | [diff] [blame] | 14154 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14155 | /* wm changes, need vblank before final wm's */ |
| 14156 | if (crtc_state->update_wm_post) |
| 14157 | return true; |
Maarten Lankhorst | a6747b7 | 2016-05-17 15:08:01 +0200 | [diff] [blame] | 14158 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14159 | /* |
| 14160 | * cxsr is re-enabled after vblank. |
| 14161 | * This is already handled by crtc_state->update_wm_post, |
| 14162 | * but added for clarity. |
| 14163 | */ |
| 14164 | if (crtc_state->disable_cxsr) |
| 14165 | return true; |
Maarten Lankhorst | a6747b7 | 2016-05-17 15:08:01 +0200 | [diff] [blame] | 14166 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14167 | return false; |
Maarten Lankhorst | e886167 | 2016-02-24 11:24:26 +0100 | [diff] [blame] | 14168 | } |
| 14169 | |
Lyude | 896e5bb | 2016-08-24 07:48:09 +0200 | [diff] [blame] | 14170 | static void intel_update_crtc(struct drm_crtc *crtc, |
| 14171 | struct drm_atomic_state *state, |
| 14172 | struct drm_crtc_state *old_crtc_state, |
| 14173 | unsigned int *crtc_vblank_mask) |
| 14174 | { |
| 14175 | struct drm_device *dev = crtc->dev; |
| 14176 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 14177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14178 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); |
| 14179 | bool modeset = needs_modeset(crtc->state); |
| 14180 | |
| 14181 | if (modeset) { |
| 14182 | update_scanline_offset(intel_crtc); |
| 14183 | dev_priv->display.crtc_enable(pipe_config, state); |
| 14184 | } else { |
| 14185 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
| 14186 | } |
| 14187 | |
| 14188 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { |
| 14189 | intel_fbc_enable( |
| 14190 | intel_crtc, pipe_config, |
| 14191 | to_intel_plane_state(crtc->primary->state)); |
| 14192 | } |
| 14193 | |
| 14194 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
| 14195 | |
| 14196 | if (needs_vblank_wait(pipe_config)) |
| 14197 | *crtc_vblank_mask |= drm_crtc_mask(crtc); |
| 14198 | } |
| 14199 | |
| 14200 | static void intel_update_crtcs(struct drm_atomic_state *state, |
| 14201 | unsigned int *crtc_vblank_mask) |
| 14202 | { |
| 14203 | struct drm_crtc *crtc; |
| 14204 | struct drm_crtc_state *old_crtc_state; |
| 14205 | int i; |
| 14206 | |
| 14207 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
| 14208 | if (!crtc->state->active) |
| 14209 | continue; |
| 14210 | |
| 14211 | intel_update_crtc(crtc, state, old_crtc_state, |
| 14212 | crtc_vblank_mask); |
| 14213 | } |
| 14214 | } |
| 14215 | |
Lyude | 2708249 | 2016-08-24 07:48:10 +0200 | [diff] [blame] | 14216 | static void skl_update_crtcs(struct drm_atomic_state *state, |
| 14217 | unsigned int *crtc_vblank_mask) |
| 14218 | { |
| 14219 | struct drm_device *dev = state->dev; |
| 14220 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 14221 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 14222 | struct drm_crtc *crtc; |
| 14223 | struct drm_crtc_state *old_crtc_state; |
| 14224 | struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; |
| 14225 | struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; |
| 14226 | unsigned int updated = 0; |
| 14227 | bool progress; |
| 14228 | enum pipe pipe; |
| 14229 | |
| 14230 | /* |
| 14231 | * Whenever the number of active pipes changes, we need to make sure we |
| 14232 | * update the pipes in the right order so that their ddb allocations |
| 14233 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll |
| 14234 | * cause pipe underruns and other bad stuff. |
| 14235 | */ |
| 14236 | do { |
| 14237 | int i; |
| 14238 | progress = false; |
| 14239 | |
| 14240 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
| 14241 | bool vbl_wait = false; |
| 14242 | unsigned int cmask = drm_crtc_mask(crtc); |
| 14243 | pipe = to_intel_crtc(crtc)->pipe; |
| 14244 | |
| 14245 | if (updated & cmask || !crtc->state->active) |
| 14246 | continue; |
| 14247 | if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb, |
| 14248 | pipe)) |
| 14249 | continue; |
| 14250 | |
| 14251 | updated |= cmask; |
| 14252 | |
| 14253 | /* |
| 14254 | * If this is an already active pipe, it's DDB changed, |
| 14255 | * and this isn't the last pipe that needs updating |
| 14256 | * then we need to wait for a vblank to pass for the |
| 14257 | * new ddb allocation to take effect. |
| 14258 | */ |
| 14259 | if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) && |
| 14260 | !crtc->state->active_changed && |
| 14261 | intel_state->wm_results.dirty_pipes != updated) |
| 14262 | vbl_wait = true; |
| 14263 | |
| 14264 | intel_update_crtc(crtc, state, old_crtc_state, |
| 14265 | crtc_vblank_mask); |
| 14266 | |
| 14267 | if (vbl_wait) |
| 14268 | intel_wait_for_vblank(dev, pipe); |
| 14269 | |
| 14270 | progress = true; |
| 14271 | } |
| 14272 | } while (progress); |
| 14273 | } |
| 14274 | |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14275 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 14276 | { |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14277 | struct drm_device *dev = state->dev; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 14278 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 14279 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 29ceb0e | 2016-03-09 19:07:27 +0200 | [diff] [blame] | 14280 | struct drm_crtc_state *old_crtc_state; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14281 | struct drm_crtc *crtc; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14282 | struct intel_crtc_state *intel_cstate; |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14283 | struct drm_plane *plane; |
| 14284 | struct drm_plane_state *plane_state; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14285 | bool hw_check = intel_state->modeset; |
| 14286 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
| 14287 | unsigned crtc_vblank_mask = 0; |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14288 | int i, ret; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 14289 | |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14290 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 14291 | struct intel_plane_state *intel_plane_state = |
| 14292 | to_intel_plane_state(plane_state); |
Daniel Vetter | ea0000f | 2016-06-13 16:13:46 +0200 | [diff] [blame] | 14293 | |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14294 | if (!intel_plane_state->wait_req) |
| 14295 | continue; |
| 14296 | |
Chris Wilson | 776f323 | 2016-08-04 07:52:40 +0100 | [diff] [blame] | 14297 | ret = i915_wait_request(intel_plane_state->wait_req, |
Chris Wilson | ea746f3 | 2016-09-09 14:11:49 +0100 | [diff] [blame] | 14298 | 0, NULL, NULL); |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14299 | /* EIO should be eaten, and we can't get interrupted in the |
| 14300 | * worker, and blocking commits have waited already. */ |
| 14301 | WARN_ON(ret); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14302 | } |
Ander Conselvan de Oliveira | d4afb8c | 2015-04-21 17:13:22 +0300 | [diff] [blame] | 14303 | |
Daniel Vetter | ea0000f | 2016-06-13 16:13:46 +0200 | [diff] [blame] | 14304 | drm_atomic_helper_wait_for_dependencies(state); |
| 14305 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 14306 | if (intel_state->modeset) { |
| 14307 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, |
| 14308 | sizeof(intel_state->min_pixclk)); |
| 14309 | dev_priv->active_crtcs = intel_state->active_crtcs; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 14310 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14311 | |
| 14312 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 14313 | } |
| 14314 | |
Ville Syrjälä | 29ceb0e | 2016-03-09 19:07:27 +0200 | [diff] [blame] | 14315 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 14316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14317 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14318 | if (needs_modeset(crtc->state) || |
| 14319 | to_intel_crtc_state(crtc->state)->update_pipe) { |
| 14320 | hw_check = true; |
| 14321 | |
| 14322 | put_domains[to_intel_crtc(crtc)->pipe] = |
| 14323 | modeset_get_crtc_power_domains(crtc, |
| 14324 | to_intel_crtc_state(crtc->state)); |
| 14325 | } |
| 14326 | |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 14327 | if (!needs_modeset(crtc->state)) |
| 14328 | continue; |
| 14329 | |
Ville Syrjälä | 29ceb0e | 2016-03-09 19:07:27 +0200 | [diff] [blame] | 14330 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
Daniel Vetter | 460da916 | 2013-03-27 00:44:51 +0100 | [diff] [blame] | 14331 | |
Ville Syrjälä | 29ceb0e | 2016-03-09 19:07:27 +0200 | [diff] [blame] | 14332 | if (old_crtc_state->active) { |
| 14333 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); |
Maarten Lankhorst | 4a80655 | 2016-08-09 17:04:01 +0200 | [diff] [blame] | 14334 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 14335 | intel_crtc->active = false; |
Paulo Zanoni | 58f9c0b | 2016-01-19 11:35:51 -0200 | [diff] [blame] | 14336 | intel_fbc_disable(intel_crtc); |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 14337 | intel_disable_shared_dpll(intel_crtc); |
Ville Syrjälä | 9bbc8258a | 2015-11-20 22:09:20 +0200 | [diff] [blame] | 14338 | |
| 14339 | /* |
| 14340 | * Underruns don't always raise |
| 14341 | * interrupts, so check manually. |
| 14342 | */ |
| 14343 | intel_check_cpu_fifo_underruns(dev_priv); |
| 14344 | intel_check_pch_fifo_underruns(dev_priv); |
Maarten Lankhorst | b900111 | 2015-11-19 16:07:16 +0100 | [diff] [blame] | 14345 | |
| 14346 | if (!crtc->state->active) |
| 14347 | intel_update_watermarks(crtc); |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 14348 | } |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 14349 | } |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 14350 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 14351 | /* Only after disabling all output pipelines that will be changed can we |
| 14352 | * update the the output configuration. */ |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 14353 | intel_modeset_update_crtc_state(state); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 14354 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 14355 | if (intel_state->modeset) { |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 14356 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
Maarten Lankhorst | 33c8df89 | 2016-02-10 13:49:37 +0100 | [diff] [blame] | 14357 | |
| 14358 | if (dev_priv->display.modeset_commit_cdclk && |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 14359 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 14360 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
Maarten Lankhorst | 33c8df89 | 2016-02-10 13:49:37 +0100 | [diff] [blame] | 14361 | dev_priv->display.modeset_commit_cdclk(state); |
Maarten Lankhorst | f6d1973 | 2016-03-23 14:58:07 +0100 | [diff] [blame] | 14362 | |
Lyude | 656d1b8 | 2016-08-17 15:55:54 -0400 | [diff] [blame] | 14363 | /* |
| 14364 | * SKL workaround: bspec recommends we disable the SAGV when we |
| 14365 | * have more then one pipe enabled |
| 14366 | */ |
| 14367 | if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state)) |
| 14368 | skl_disable_sagv(dev_priv); |
| 14369 | |
Maarten Lankhorst | c0ead70 | 2016-03-30 10:00:05 +0200 | [diff] [blame] | 14370 | intel_modeset_verify_disabled(dev); |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 14371 | } |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 14372 | |
Lyude | 896e5bb | 2016-08-24 07:48:09 +0200 | [diff] [blame] | 14373 | /* Complete the events for pipes that have now been disabled */ |
Ville Syrjälä | 29ceb0e | 2016-03-09 19:07:27 +0200 | [diff] [blame] | 14374 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
Maarten Lankhorst | f6ac4b2 | 2015-07-13 16:30:31 +0200 | [diff] [blame] | 14375 | bool modeset = needs_modeset(crtc->state); |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 14376 | |
Daniel Vetter | 1f7528c | 2016-06-13 16:13:45 +0200 | [diff] [blame] | 14377 | /* Complete events for now disable pipes here. */ |
| 14378 | if (modeset && !crtc->state->active && crtc->state->event) { |
| 14379 | spin_lock_irq(&dev->event_lock); |
| 14380 | drm_crtc_send_vblank_event(crtc, crtc->state->event); |
| 14381 | spin_unlock_irq(&dev->event_lock); |
| 14382 | |
| 14383 | crtc->state->event = NULL; |
| 14384 | } |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 14385 | } |
| 14386 | |
Lyude | 896e5bb | 2016-08-24 07:48:09 +0200 | [diff] [blame] | 14387 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
| 14388 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); |
| 14389 | |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14390 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
| 14391 | * already, but still need the state for the delayed optimization. To |
| 14392 | * fix this: |
| 14393 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. |
| 14394 | * - schedule that vblank worker _before_ calling hw_done |
| 14395 | * - at the start of commit_tail, cancel it _synchrously |
| 14396 | * - switch over to the vblank wait helper in the core after that since |
| 14397 | * we don't need out special handling any more. |
| 14398 | */ |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14399 | if (!state->legacy_cursor_update) |
| 14400 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); |
| 14401 | |
| 14402 | /* |
| 14403 | * Now that the vblank has passed, we can go ahead and program the |
| 14404 | * optimal watermarks on platforms that need two-step watermark |
| 14405 | * programming. |
| 14406 | * |
| 14407 | * TODO: Move this (and other cleanup) to an async worker eventually. |
| 14408 | */ |
| 14409 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
| 14410 | intel_cstate = to_intel_crtc_state(crtc->state); |
| 14411 | |
| 14412 | if (dev_priv->display.optimize_watermarks) |
| 14413 | dev_priv->display.optimize_watermarks(intel_cstate); |
| 14414 | } |
| 14415 | |
| 14416 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
| 14417 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
| 14418 | |
| 14419 | if (put_domains[i]) |
| 14420 | modeset_put_power_domains(dev_priv, put_domains[i]); |
| 14421 | |
| 14422 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); |
| 14423 | } |
| 14424 | |
Lyude | 656d1b8 | 2016-08-17 15:55:54 -0400 | [diff] [blame] | 14425 | if (IS_SKYLAKE(dev_priv) && intel_state->modeset && |
| 14426 | skl_can_enable_sagv(state)) |
| 14427 | skl_enable_sagv(dev_priv); |
| 14428 | |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14429 | drm_atomic_helper_commit_hw_done(state); |
| 14430 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14431 | if (intel_state->modeset) |
| 14432 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
| 14433 | |
| 14434 | mutex_lock(&dev->struct_mutex); |
| 14435 | drm_atomic_helper_cleanup_planes(dev, state); |
| 14436 | mutex_unlock(&dev->struct_mutex); |
| 14437 | |
Daniel Vetter | ea0000f | 2016-06-13 16:13:46 +0200 | [diff] [blame] | 14438 | drm_atomic_helper_commit_cleanup_done(state); |
| 14439 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 14440 | drm_atomic_state_put(state); |
Jesse Barnes | 7f27126e | 2014-11-05 14:26:06 -0800 | [diff] [blame] | 14441 | |
Mika Kuoppala | 7571494 | 2015-12-16 09:26:48 +0200 | [diff] [blame] | 14442 | /* As one of the primary mmio accessors, KMS has a high likelihood |
| 14443 | * of triggering bugs in unclaimed access. After we finish |
| 14444 | * modesetting, see if an error has been flagged, and if so |
| 14445 | * enable debugging for the next modeset - and hope we catch |
| 14446 | * the culprit. |
| 14447 | * |
| 14448 | * XXX note that we assume display power is on at this point. |
| 14449 | * This might hold true now but we need to add pm helper to check |
| 14450 | * unclaimed only when the hardware is on, as atomic commits |
| 14451 | * can happen also when the device is completely off. |
| 14452 | */ |
| 14453 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14454 | } |
| 14455 | |
| 14456 | static void intel_atomic_commit_work(struct work_struct *work) |
| 14457 | { |
| 14458 | struct drm_atomic_state *state = container_of(work, |
| 14459 | struct drm_atomic_state, |
| 14460 | commit_work); |
| 14461 | intel_atomic_commit_tail(state); |
| 14462 | } |
| 14463 | |
Daniel Vetter | 6c9c1b3 | 2016-06-13 16:13:48 +0200 | [diff] [blame] | 14464 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
| 14465 | { |
| 14466 | struct drm_plane_state *old_plane_state; |
| 14467 | struct drm_plane *plane; |
Daniel Vetter | 6c9c1b3 | 2016-06-13 16:13:48 +0200 | [diff] [blame] | 14468 | int i; |
| 14469 | |
Chris Wilson | faf5bf0 | 2016-08-04 16:32:37 +0100 | [diff] [blame] | 14470 | for_each_plane_in_state(state, plane, old_plane_state, i) |
| 14471 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
| 14472 | intel_fb_obj(plane->state->fb), |
| 14473 | to_intel_plane(plane)->frontbuffer_bit); |
Daniel Vetter | 6c9c1b3 | 2016-06-13 16:13:48 +0200 | [diff] [blame] | 14474 | } |
| 14475 | |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14476 | /** |
| 14477 | * intel_atomic_commit - commit validated state object |
| 14478 | * @dev: DRM device |
| 14479 | * @state: the top-level driver state object |
| 14480 | * @nonblock: nonblocking commit |
| 14481 | * |
| 14482 | * This function commits a top-level state object that has been validated |
| 14483 | * with drm_atomic_helper_check(). |
| 14484 | * |
| 14485 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment |
| 14486 | * nonblocking commits are only safe for pure plane updates. Everything else |
| 14487 | * should work though. |
| 14488 | * |
| 14489 | * RETURNS |
| 14490 | * Zero for success or -errno. |
| 14491 | */ |
| 14492 | static int intel_atomic_commit(struct drm_device *dev, |
| 14493 | struct drm_atomic_state *state, |
| 14494 | bool nonblock) |
| 14495 | { |
| 14496 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 14497 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14498 | int ret = 0; |
| 14499 | |
| 14500 | if (intel_state->modeset && nonblock) { |
| 14501 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); |
| 14502 | return -EINVAL; |
| 14503 | } |
| 14504 | |
| 14505 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
| 14506 | if (ret) |
| 14507 | return ret; |
| 14508 | |
| 14509 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); |
| 14510 | |
| 14511 | ret = intel_atomic_prepare_commit(dev, state, nonblock); |
| 14512 | if (ret) { |
| 14513 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); |
| 14514 | return ret; |
| 14515 | } |
| 14516 | |
| 14517 | drm_atomic_helper_swap_state(state, true); |
| 14518 | dev_priv->wm.distrust_bios_wm = false; |
| 14519 | dev_priv->wm.skl_results = intel_state->wm_results; |
| 14520 | intel_shared_dpll_commit(state); |
Daniel Vetter | 6c9c1b3 | 2016-06-13 16:13:48 +0200 | [diff] [blame] | 14521 | intel_atomic_track_fbs(state); |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14522 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 14523 | drm_atomic_state_get(state); |
Daniel Vetter | 94f0502 | 2016-06-14 18:01:00 +0200 | [diff] [blame] | 14524 | if (nonblock) |
| 14525 | queue_work(system_unbound_wq, &state->commit_work); |
| 14526 | else |
| 14527 | intel_atomic_commit_tail(state); |
Mika Kuoppala | 7571494 | 2015-12-16 09:26:48 +0200 | [diff] [blame] | 14528 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 14529 | return 0; |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 14530 | } |
| 14531 | |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 14532 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
| 14533 | { |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 14534 | struct drm_device *dev = crtc->dev; |
| 14535 | struct drm_atomic_state *state; |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 14536 | struct drm_crtc_state *crtc_state; |
Ander Conselvan de Oliveira | 2bfb462 | 2015-04-21 17:13:20 +0300 | [diff] [blame] | 14537 | int ret; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 14538 | |
| 14539 | state = drm_atomic_state_alloc(dev); |
| 14540 | if (!state) { |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 14541 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
| 14542 | crtc->base.id, crtc->name); |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 14543 | return; |
| 14544 | } |
| 14545 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 14546 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 14547 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 14548 | retry: |
| 14549 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 14550 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 14551 | if (!ret) { |
| 14552 | if (!crtc_state->active) |
| 14553 | goto out; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 14554 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 14555 | crtc_state->mode_changed = true; |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 14556 | ret = drm_atomic_commit(state); |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 14557 | } |
| 14558 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 14559 | if (ret == -EDEADLK) { |
| 14560 | drm_atomic_state_clear(state); |
| 14561 | drm_modeset_backoff(state->acquire_ctx); |
| 14562 | goto retry; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 14563 | } |
| 14564 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 14565 | out: |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 14566 | drm_atomic_state_put(state); |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 14567 | } |
| 14568 | |
Bob Paauwe | fa95986 | 2016-07-15 14:59:02 +0100 | [diff] [blame] | 14569 | /* |
| 14570 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling |
| 14571 | * drm_atomic_helper_legacy_gamma_set() directly. |
| 14572 | */ |
| 14573 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, |
| 14574 | u16 *red, u16 *green, u16 *blue, |
| 14575 | uint32_t size) |
| 14576 | { |
| 14577 | struct drm_device *dev = crtc->dev; |
| 14578 | struct drm_mode_config *config = &dev->mode_config; |
| 14579 | struct drm_crtc_state *state; |
| 14580 | int ret; |
| 14581 | |
| 14582 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); |
| 14583 | if (ret) |
| 14584 | return ret; |
| 14585 | |
| 14586 | /* |
| 14587 | * Make sure we update the legacy properties so this works when |
| 14588 | * atomic is not enabled. |
| 14589 | */ |
| 14590 | |
| 14591 | state = crtc->state; |
| 14592 | |
| 14593 | drm_object_property_set_value(&crtc->base, |
| 14594 | config->degamma_lut_property, |
| 14595 | (state->degamma_lut) ? |
| 14596 | state->degamma_lut->base.id : 0); |
| 14597 | |
| 14598 | drm_object_property_set_value(&crtc->base, |
| 14599 | config->ctm_property, |
| 14600 | (state->ctm) ? |
| 14601 | state->ctm->base.id : 0); |
| 14602 | |
| 14603 | drm_object_property_set_value(&crtc->base, |
| 14604 | config->gamma_lut_property, |
| 14605 | (state->gamma_lut) ? |
| 14606 | state->gamma_lut->base.id : 0); |
| 14607 | |
| 14608 | return 0; |
| 14609 | } |
| 14610 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 14611 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
Bob Paauwe | fa95986 | 2016-07-15 14:59:02 +0100 | [diff] [blame] | 14612 | .gamma_set = intel_atomic_legacy_gamma_set, |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 14613 | .set_config = drm_atomic_helper_set_config, |
Lionel Landwerlin | 82cf435 | 2016-03-16 10:57:16 +0000 | [diff] [blame] | 14614 | .set_property = drm_atomic_helper_crtc_set_property, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 14615 | .destroy = intel_crtc_destroy, |
Chris Wilson | 527b6ab | 2016-06-24 13:44:03 +0100 | [diff] [blame] | 14616 | .page_flip = intel_crtc_page_flip, |
Matt Roper | 1356837 | 2015-01-21 16:35:47 -0800 | [diff] [blame] | 14617 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
| 14618 | .atomic_destroy_state = intel_crtc_destroy_state, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 14619 | }; |
| 14620 | |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14621 | /** |
| 14622 | * intel_prepare_plane_fb - Prepare fb for usage on plane |
| 14623 | * @plane: drm plane to prepare for |
| 14624 | * @fb: framebuffer to prepare for presentation |
| 14625 | * |
| 14626 | * Prepares a framebuffer for usage on a display plane. Generally this |
| 14627 | * involves pinning the underlying object and updating the frontbuffer tracking |
| 14628 | * bits. Some older platforms need special physical address handling for |
| 14629 | * cursor planes. |
| 14630 | * |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14631 | * Must be called with struct_mutex held. |
| 14632 | * |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14633 | * Returns 0 on success, negative error code on failure. |
| 14634 | */ |
| 14635 | int |
| 14636 | intel_prepare_plane_fb(struct drm_plane *plane, |
Chris Wilson | 1832040 | 2016-08-18 19:00:16 +0100 | [diff] [blame] | 14637 | struct drm_plane_state *new_state) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14638 | { |
| 14639 | struct drm_device *dev = plane->dev; |
Maarten Lankhorst | 844f911 | 2015-09-02 10:42:40 +0200 | [diff] [blame] | 14640 | struct drm_framebuffer *fb = new_state->fb; |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14641 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 14642 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 14643 | struct reservation_object *resv; |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14644 | int ret = 0; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14645 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 14646 | if (!obj && !old_obj) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14647 | return 0; |
| 14648 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14649 | if (old_obj) { |
| 14650 | struct drm_crtc_state *crtc_state = |
| 14651 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); |
| 14652 | |
| 14653 | /* Big Hammer, we also need to ensure that any pending |
| 14654 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 14655 | * current scanout is retired before unpinning the old |
| 14656 | * framebuffer. Note that we rely on userspace rendering |
| 14657 | * into the buffer attached to the pipe they are waiting |
| 14658 | * on. If not, userspace generates a GPU hang with IPEHR |
| 14659 | * point to the MI_WAIT_FOR_EVENT. |
| 14660 | * |
| 14661 | * This should only fail upon a hung GPU, in which case we |
| 14662 | * can safely continue. |
| 14663 | */ |
| 14664 | if (needs_modeset(crtc_state)) |
| 14665 | ret = i915_gem_object_wait_rendering(old_obj, true); |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 14666 | if (ret) { |
| 14667 | /* GPU hangs should have been swallowed by the wait */ |
| 14668 | WARN_ON(ret == -EIO); |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14669 | return ret; |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 14670 | } |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14671 | } |
| 14672 | |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 14673 | if (!obj) |
| 14674 | return 0; |
| 14675 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14676 | /* For framebuffer backed by dmabuf, wait for fence */ |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 14677 | resv = i915_gem_object_get_dmabuf_resv(obj); |
| 14678 | if (resv) { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14679 | long lret; |
| 14680 | |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 14681 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14682 | MAX_SCHEDULE_TIMEOUT); |
| 14683 | if (lret == -ERESTARTSYS) |
| 14684 | return lret; |
| 14685 | |
| 14686 | WARN(lret < 0, "waiting returns %li\n", lret); |
| 14687 | } |
| 14688 | |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 14689 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14690 | INTEL_INFO(dev)->cursor_needs_physical) { |
| 14691 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
| 14692 | ret = i915_gem_object_attach_phys(obj, align); |
| 14693 | if (ret) |
| 14694 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
| 14695 | } else { |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 14696 | struct i915_vma *vma; |
| 14697 | |
| 14698 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
| 14699 | if (IS_ERR(vma)) |
| 14700 | ret = PTR_ERR(vma); |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14701 | } |
| 14702 | |
Chris Wilson | c37efb9 | 2016-06-17 08:28:47 +0100 | [diff] [blame] | 14703 | if (ret == 0) { |
Chris Wilson | 27c01aa | 2016-08-04 07:52:30 +0100 | [diff] [blame] | 14704 | to_intel_plane_state(new_state)->wait_req = |
Chris Wilson | d72d908 | 2016-08-04 07:52:31 +0100 | [diff] [blame] | 14705 | i915_gem_active_get(&obj->last_write, |
| 14706 | &obj->base.dev->struct_mutex); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14707 | } |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14708 | |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 14709 | return ret; |
| 14710 | } |
| 14711 | |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 14712 | /** |
| 14713 | * intel_cleanup_plane_fb - Cleans up an fb after plane use |
| 14714 | * @plane: drm plane to clean up for |
| 14715 | * @fb: old framebuffer that was on plane |
| 14716 | * |
| 14717 | * Cleans up a framebuffer that has just been removed from a plane. |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 14718 | * |
| 14719 | * Must be called with struct_mutex held. |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 14720 | */ |
| 14721 | void |
| 14722 | intel_cleanup_plane_fb(struct drm_plane *plane, |
Chris Wilson | 1832040 | 2016-08-18 19:00:16 +0100 | [diff] [blame] | 14723 | struct drm_plane_state *old_state) |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 14724 | { |
| 14725 | struct drm_device *dev = plane->dev; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14726 | struct intel_plane_state *old_intel_state; |
Keith Packard | 8497825 | 2016-07-31 00:54:51 -0700 | [diff] [blame] | 14727 | struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 14728 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
| 14729 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 14730 | |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14731 | old_intel_state = to_intel_plane_state(old_state); |
| 14732 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 14733 | if (!obj && !old_obj) |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 14734 | return; |
| 14735 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 14736 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
| 14737 | !INTEL_INFO(dev)->cursor_needs_physical)) |
Ville Syrjälä | 3465c58 | 2016-02-15 22:54:43 +0200 | [diff] [blame] | 14738 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 14739 | |
Keith Packard | 8497825 | 2016-07-31 00:54:51 -0700 | [diff] [blame] | 14740 | i915_gem_request_assign(&intel_state->wait_req, NULL); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 14741 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14742 | } |
| 14743 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14744 | int |
| 14745 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) |
| 14746 | { |
| 14747 | int max_scale; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14748 | int crtc_clock, cdclk; |
| 14749 | |
Maarten Lankhorst | bf8a0af | 2015-11-24 11:29:02 +0100 | [diff] [blame] | 14750 | if (!intel_crtc || !crtc_state->base.enable) |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14751 | return DRM_PLANE_HELPER_NO_SCALING; |
| 14752 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14753 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 14754 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14755 | |
Tvrtko Ursulin | 54bf1ce | 2015-10-20 17:17:07 +0100 | [diff] [blame] | 14756 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14757 | return DRM_PLANE_HELPER_NO_SCALING; |
| 14758 | |
| 14759 | /* |
| 14760 | * skl max scale is lower of: |
| 14761 | * close to 3 but not 3, -1 is for that purpose |
| 14762 | * or |
| 14763 | * cdclk/crtc_clock |
| 14764 | */ |
| 14765 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); |
| 14766 | |
| 14767 | return max_scale; |
| 14768 | } |
| 14769 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14770 | static int |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 14771 | intel_check_primary_plane(struct drm_plane *plane, |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14772 | struct intel_crtc_state *crtc_state, |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 14773 | struct intel_plane_state *state) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14774 | { |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 14775 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 14776 | struct drm_crtc *crtc = state->base.crtc; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14777 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14778 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
| 14779 | bool can_position = false; |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 14780 | int ret; |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 14781 | |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 14782 | if (INTEL_GEN(dev_priv) >= 9) { |
Ville Syrjälä | 693bdc2 | 2016-01-15 20:46:53 +0200 | [diff] [blame] | 14783 | /* use scaler when colorkey is not required */ |
| 14784 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
| 14785 | min_scale = 1; |
| 14786 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); |
| 14787 | } |
Sonika Jindal | d810636 | 2015-04-10 14:37:28 +0530 | [diff] [blame] | 14788 | can_position = true; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14789 | } |
Sonika Jindal | d810636 | 2015-04-10 14:37:28 +0530 | [diff] [blame] | 14790 | |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 14791 | ret = drm_plane_helper_check_state(&state->base, |
| 14792 | &state->clip, |
| 14793 | min_scale, max_scale, |
| 14794 | can_position, true); |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 14795 | if (ret) |
| 14796 | return ret; |
| 14797 | |
Daniel Vetter | cc92638 | 2016-08-15 10:41:47 +0200 | [diff] [blame] | 14798 | if (!state->base.fb) |
Ville Syrjälä | b63a16f | 2016-01-28 16:53:54 +0200 | [diff] [blame] | 14799 | return 0; |
| 14800 | |
| 14801 | if (INTEL_GEN(dev_priv) >= 9) { |
| 14802 | ret = skl_check_plane_surface(state); |
| 14803 | if (ret) |
| 14804 | return ret; |
| 14805 | } |
| 14806 | |
| 14807 | return 0; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14808 | } |
| 14809 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14810 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
| 14811 | struct drm_crtc_state *old_crtc_state) |
| 14812 | { |
| 14813 | struct drm_device *dev = crtc->dev; |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 14814 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14816 | struct intel_crtc_state *old_intel_state = |
| 14817 | to_intel_crtc_state(old_crtc_state); |
| 14818 | bool modeset = needs_modeset(crtc->state); |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 14819 | enum pipe pipe = intel_crtc->pipe; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14820 | |
| 14821 | /* Perform vblank evasion around commit operation */ |
| 14822 | intel_pipe_update_start(intel_crtc); |
| 14823 | |
| 14824 | if (modeset) |
| 14825 | return; |
| 14826 | |
| 14827 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { |
| 14828 | intel_color_set_csc(crtc->state); |
| 14829 | intel_color_load_luts(crtc->state); |
| 14830 | } |
| 14831 | |
| 14832 | if (to_intel_crtc_state(crtc->state)->update_pipe) |
| 14833 | intel_update_pipe_config(intel_crtc, old_intel_state); |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 14834 | else if (INTEL_GEN(dev_priv) >= 9) { |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14835 | skl_detach_scalers(intel_crtc); |
Lyude | 62e0fb8 | 2016-08-22 12:50:08 -0400 | [diff] [blame] | 14836 | |
| 14837 | I915_WRITE(PIPE_WM_LINETIME(pipe), |
| 14838 | dev_priv->wm.skl_hw.wm_linetime[pipe]); |
| 14839 | } |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 14840 | } |
| 14841 | |
| 14842 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
| 14843 | struct drm_crtc_state *old_crtc_state) |
| 14844 | { |
| 14845 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14846 | |
| 14847 | intel_pipe_update_end(intel_crtc, NULL); |
| 14848 | } |
| 14849 | |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 14850 | /** |
Matt Roper | 4a3b876 | 2014-12-23 10:41:51 -0800 | [diff] [blame] | 14851 | * intel_plane_destroy - destroy a plane |
| 14852 | * @plane: plane to destroy |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 14853 | * |
Matt Roper | 4a3b876 | 2014-12-23 10:41:51 -0800 | [diff] [blame] | 14854 | * Common destruction function for all types of planes (primary, cursor, |
| 14855 | * sprite). |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 14856 | */ |
Matt Roper | 4a3b876 | 2014-12-23 10:41:51 -0800 | [diff] [blame] | 14857 | void intel_plane_destroy(struct drm_plane *plane) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14858 | { |
Ville Syrjälä | 69ae561 | 2016-05-27 20:59:22 +0300 | [diff] [blame] | 14859 | if (!plane) |
| 14860 | return; |
| 14861 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14862 | drm_plane_cleanup(plane); |
Ville Syrjälä | 69ae561 | 2016-05-27 20:59:22 +0300 | [diff] [blame] | 14863 | kfree(to_intel_plane(plane)); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14864 | } |
| 14865 | |
Matt Roper | 65a3fea | 2015-01-21 16:35:42 -0800 | [diff] [blame] | 14866 | const struct drm_plane_funcs intel_plane_funcs = { |
Matt Roper | 70a101f | 2015-04-08 18:56:53 -0700 | [diff] [blame] | 14867 | .update_plane = drm_atomic_helper_update_plane, |
| 14868 | .disable_plane = drm_atomic_helper_disable_plane, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14869 | .destroy = intel_plane_destroy, |
Matt Roper | c196e1d | 2015-01-21 16:35:48 -0800 | [diff] [blame] | 14870 | .set_property = drm_atomic_helper_plane_set_property, |
Matt Roper | a98b343 | 2015-01-21 16:35:43 -0800 | [diff] [blame] | 14871 | .atomic_get_property = intel_plane_atomic_get_property, |
| 14872 | .atomic_set_property = intel_plane_atomic_set_property, |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14873 | .atomic_duplicate_state = intel_plane_duplicate_state, |
| 14874 | .atomic_destroy_state = intel_plane_destroy_state, |
| 14875 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14876 | }; |
| 14877 | |
| 14878 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
| 14879 | int pipe) |
| 14880 | { |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 14881 | struct intel_plane *primary = NULL; |
| 14882 | struct intel_plane_state *state = NULL; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14883 | const uint32_t *intel_primary_formats; |
Thierry Reding | 45e3743 | 2015-08-12 16:54:28 +0200 | [diff] [blame] | 14884 | unsigned int num_formats; |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 14885 | int ret; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14886 | |
| 14887 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 14888 | if (!primary) |
| 14889 | goto fail; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14890 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14891 | state = intel_create_plane_state(&primary->base); |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 14892 | if (!state) |
| 14893 | goto fail; |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14894 | primary->base.state = &state->base; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14895 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14896 | primary->can_scale = false; |
| 14897 | primary->max_downscale = 1; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14898 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14899 | primary->can_scale = true; |
Chandra Konduru | af99ced | 2015-05-11 14:35:47 -0700 | [diff] [blame] | 14900 | state->scaler_id = -1; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14901 | } |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14902 | primary->pipe = pipe; |
| 14903 | primary->plane = pipe; |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 14904 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
Matt Roper | c59cb17 | 2014-12-01 15:40:16 -0800 | [diff] [blame] | 14905 | primary->check_plane = intel_check_primary_plane; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14906 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
| 14907 | primary->plane = !pipe; |
| 14908 | |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 14909 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14910 | intel_primary_formats = skl_primary_formats; |
| 14911 | num_formats = ARRAY_SIZE(skl_primary_formats); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 14912 | |
| 14913 | primary->update_plane = skylake_update_primary_plane; |
| 14914 | primary->disable_plane = skylake_disable_primary_plane; |
| 14915 | } else if (HAS_PCH_SPLIT(dev)) { |
| 14916 | intel_primary_formats = i965_primary_formats; |
| 14917 | num_formats = ARRAY_SIZE(i965_primary_formats); |
| 14918 | |
| 14919 | primary->update_plane = ironlake_update_primary_plane; |
| 14920 | primary->disable_plane = i9xx_disable_primary_plane; |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 14921 | } else if (INTEL_INFO(dev)->gen >= 4) { |
Damien Lespiau | 568db4f | 2015-05-12 16:13:18 +0100 | [diff] [blame] | 14922 | intel_primary_formats = i965_primary_formats; |
| 14923 | num_formats = ARRAY_SIZE(i965_primary_formats); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 14924 | |
| 14925 | primary->update_plane = i9xx_update_primary_plane; |
| 14926 | primary->disable_plane = i9xx_disable_primary_plane; |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 14927 | } else { |
| 14928 | intel_primary_formats = i8xx_primary_formats; |
| 14929 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
Maarten Lankhorst | a8d201a | 2016-01-07 11:54:11 +0100 | [diff] [blame] | 14930 | |
| 14931 | primary->update_plane = i9xx_update_primary_plane; |
| 14932 | primary->disable_plane = i9xx_disable_primary_plane; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14933 | } |
| 14934 | |
Ville Syrjälä | 38573dc | 2016-05-27 20:59:23 +0300 | [diff] [blame] | 14935 | if (INTEL_INFO(dev)->gen >= 9) |
| 14936 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
| 14937 | &intel_plane_funcs, |
| 14938 | intel_primary_formats, num_formats, |
| 14939 | DRM_PLANE_TYPE_PRIMARY, |
| 14940 | "plane 1%c", pipe_name(pipe)); |
| 14941 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 14942 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
| 14943 | &intel_plane_funcs, |
| 14944 | intel_primary_formats, num_formats, |
| 14945 | DRM_PLANE_TYPE_PRIMARY, |
| 14946 | "primary %c", pipe_name(pipe)); |
| 14947 | else |
| 14948 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
| 14949 | &intel_plane_funcs, |
| 14950 | intel_primary_formats, num_formats, |
| 14951 | DRM_PLANE_TYPE_PRIMARY, |
| 14952 | "plane %c", plane_name(primary->plane)); |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 14953 | if (ret) |
| 14954 | goto fail; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 14955 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 14956 | if (INTEL_INFO(dev)->gen >= 4) |
| 14957 | intel_create_rotation_property(dev, primary); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 14958 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14959 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
| 14960 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14961 | return &primary->base; |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 14962 | |
| 14963 | fail: |
| 14964 | kfree(state); |
| 14965 | kfree(primary); |
| 14966 | |
| 14967 | return NULL; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14968 | } |
| 14969 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 14970 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
| 14971 | { |
| 14972 | if (!dev->mode_config.rotation_property) { |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 14973 | unsigned long flags = DRM_ROTATE_0 | |
| 14974 | DRM_ROTATE_180; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 14975 | |
| 14976 | if (INTEL_INFO(dev)->gen >= 9) |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 14977 | flags |= DRM_ROTATE_90 | DRM_ROTATE_270; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 14978 | |
| 14979 | dev->mode_config.rotation_property = |
| 14980 | drm_mode_create_rotation_property(dev, flags); |
| 14981 | } |
| 14982 | if (dev->mode_config.rotation_property) |
| 14983 | drm_object_attach_property(&plane->base.base, |
| 14984 | dev->mode_config.rotation_property, |
| 14985 | plane->base.state->rotation); |
| 14986 | } |
| 14987 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14988 | static int |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14989 | intel_check_cursor_plane(struct drm_plane *plane, |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14990 | struct intel_crtc_state *crtc_state, |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14991 | struct intel_plane_state *state) |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14992 | { |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 14993 | struct drm_framebuffer *fb = state->base.fb; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14994 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Ville Syrjälä | b29ec92 | 2015-12-18 19:24:39 +0200 | [diff] [blame] | 14995 | enum pipe pipe = to_intel_plane(plane)->pipe; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14996 | unsigned stride; |
| 14997 | int ret; |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14998 | |
Ville Syrjälä | f8856a4 | 2016-07-26 19:07:00 +0300 | [diff] [blame] | 14999 | ret = drm_plane_helper_check_state(&state->base, |
| 15000 | &state->clip, |
| 15001 | DRM_PLANE_HELPER_NO_SCALING, |
| 15002 | DRM_PLANE_HELPER_NO_SCALING, |
| 15003 | true, true); |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15004 | if (ret) |
| 15005 | return ret; |
| 15006 | |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15007 | /* if we want to turn off the cursor ignore width and height */ |
| 15008 | if (!obj) |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 15009 | return 0; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15010 | |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15011 | /* Check for which cursor types we support */ |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 15012 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 15013 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
| 15014 | state->base.crtc_w, state->base.crtc_h); |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15015 | return -EINVAL; |
| 15016 | } |
| 15017 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 15018 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
| 15019 | if (obj->base.size < stride * state->base.crtc_h) { |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15020 | DRM_DEBUG_KMS("buffer is too small\n"); |
| 15021 | return -ENOMEM; |
| 15022 | } |
| 15023 | |
Ville Syrjälä | 3a656b5 | 2015-03-09 21:08:37 +0200 | [diff] [blame] | 15024 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15025 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 15026 | return -EINVAL; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15027 | } |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 15028 | |
Ville Syrjälä | b29ec92 | 2015-12-18 19:24:39 +0200 | [diff] [blame] | 15029 | /* |
| 15030 | * There's something wrong with the cursor on CHV pipe C. |
| 15031 | * If it straddles the left edge of the screen then |
| 15032 | * moving it away from the edge or disabling it often |
| 15033 | * results in a pipe underrun, and often that can lead to |
| 15034 | * dead pipe (constant underrun reported, and it scans |
| 15035 | * out just a solid color). To recover from that, the |
| 15036 | * display power well must be turned off and on again. |
| 15037 | * Refuse the put the cursor into that compromised position. |
| 15038 | */ |
| 15039 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 15040 | state->base.visible && state->base.crtc_x < 0) { |
Ville Syrjälä | b29ec92 | 2015-12-18 19:24:39 +0200 | [diff] [blame] | 15041 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
| 15042 | return -EINVAL; |
| 15043 | } |
| 15044 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 15045 | return 0; |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 15046 | } |
| 15047 | |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 15048 | static void |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 15049 | intel_disable_cursor_plane(struct drm_plane *plane, |
Maarten Lankhorst | 7fabf5e | 2015-06-15 12:33:47 +0200 | [diff] [blame] | 15050 | struct drm_crtc *crtc) |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 15051 | { |
Maarten Lankhorst | f285802 | 2016-01-07 11:54:09 +0100 | [diff] [blame] | 15052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 15053 | |
| 15054 | intel_crtc->cursor_addr = 0; |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 15055 | intel_crtc_update_cursor(crtc, NULL); |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 15056 | } |
| 15057 | |
| 15058 | static void |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 15059 | intel_update_cursor_plane(struct drm_plane *plane, |
| 15060 | const struct intel_crtc_state *crtc_state, |
| 15061 | const struct intel_plane_state *state) |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 15062 | { |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 15063 | struct drm_crtc *crtc = crtc_state->base.crtc; |
| 15064 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 15065 | struct drm_device *dev = plane->dev; |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 15066 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 15067 | uint32_t addr; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15068 | |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 15069 | if (!obj) |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 15070 | addr = 0; |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 15071 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 15072 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 15073 | else |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 15074 | addr = obj->phys_handle->busaddr; |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 15075 | |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 15076 | intel_crtc->cursor_addr = addr; |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 15077 | intel_crtc_update_cursor(crtc, state); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15078 | } |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 15079 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15080 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
| 15081 | int pipe) |
| 15082 | { |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 15083 | struct intel_plane *cursor = NULL; |
| 15084 | struct intel_plane_state *state = NULL; |
| 15085 | int ret; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15086 | |
| 15087 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 15088 | if (!cursor) |
| 15089 | goto fail; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15090 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 15091 | state = intel_create_plane_state(&cursor->base); |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 15092 | if (!state) |
| 15093 | goto fail; |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 15094 | cursor->base.state = &state->base; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 15095 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15096 | cursor->can_scale = false; |
| 15097 | cursor->max_downscale = 1; |
| 15098 | cursor->pipe = pipe; |
| 15099 | cursor->plane = pipe; |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 15100 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
Matt Roper | c59cb17 | 2014-12-01 15:40:16 -0800 | [diff] [blame] | 15101 | cursor->check_plane = intel_check_cursor_plane; |
Maarten Lankhorst | 55a08b3f | 2016-01-07 11:54:10 +0100 | [diff] [blame] | 15102 | cursor->update_plane = intel_update_cursor_plane; |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 15103 | cursor->disable_plane = intel_disable_cursor_plane; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15104 | |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 15105 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
| 15106 | &intel_plane_funcs, |
| 15107 | intel_cursor_formats, |
| 15108 | ARRAY_SIZE(intel_cursor_formats), |
Ville Syrjälä | 38573dc | 2016-05-27 20:59:23 +0300 | [diff] [blame] | 15109 | DRM_PLANE_TYPE_CURSOR, |
| 15110 | "cursor %c", pipe_name(pipe)); |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 15111 | if (ret) |
| 15112 | goto fail; |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 15113 | |
| 15114 | if (INTEL_INFO(dev)->gen >= 4) { |
| 15115 | if (!dev->mode_config.rotation_property) |
| 15116 | dev->mode_config.rotation_property = |
| 15117 | drm_mode_create_rotation_property(dev, |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 15118 | DRM_ROTATE_0 | |
| 15119 | DRM_ROTATE_180); |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 15120 | if (dev->mode_config.rotation_property) |
| 15121 | drm_object_attach_property(&cursor->base.base, |
| 15122 | dev->mode_config.rotation_property, |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 15123 | state->base.rotation); |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 15124 | } |
| 15125 | |
Chandra Konduru | af99ced | 2015-05-11 14:35:47 -0700 | [diff] [blame] | 15126 | if (INTEL_INFO(dev)->gen >=9) |
| 15127 | state->scaler_id = -1; |
| 15128 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 15129 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
| 15130 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15131 | return &cursor->base; |
Ville Syrjälä | fca0ce2 | 2016-03-21 14:43:22 +0000 | [diff] [blame] | 15132 | |
| 15133 | fail: |
| 15134 | kfree(state); |
| 15135 | kfree(cursor); |
| 15136 | |
| 15137 | return NULL; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15138 | } |
| 15139 | |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 15140 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
| 15141 | struct intel_crtc_state *crtc_state) |
| 15142 | { |
| 15143 | int i; |
| 15144 | struct intel_scaler *intel_scaler; |
| 15145 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; |
| 15146 | |
| 15147 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
| 15148 | intel_scaler = &scaler_state->scalers[i]; |
| 15149 | intel_scaler->in_use = 0; |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 15150 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
| 15151 | } |
| 15152 | |
| 15153 | scaler_state->scaler_id = -1; |
| 15154 | } |
| 15155 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 15156 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15157 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 15158 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15159 | struct intel_crtc *intel_crtc; |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 15160 | struct intel_crtc_state *crtc_state = NULL; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15161 | struct drm_plane *primary = NULL; |
| 15162 | struct drm_plane *cursor = NULL; |
Lionel Landwerlin | 8563b1e | 2016-03-16 10:57:14 +0000 | [diff] [blame] | 15163 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15164 | |
Daniel Vetter | 955382f | 2013-09-19 14:05:45 +0200 | [diff] [blame] | 15165 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15166 | if (intel_crtc == NULL) |
| 15167 | return; |
| 15168 | |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 15169 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
| 15170 | if (!crtc_state) |
| 15171 | goto fail; |
Ander Conselvan de Oliveira | 550acef | 2015-04-21 17:13:24 +0300 | [diff] [blame] | 15172 | intel_crtc->config = crtc_state; |
| 15173 | intel_crtc->base.state = &crtc_state->base; |
Matt Roper | 0787824 | 2015-02-25 11:43:26 -0800 | [diff] [blame] | 15174 | crtc_state->base.crtc = &intel_crtc->base; |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 15175 | |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 15176 | /* initialize shared scalers */ |
| 15177 | if (INTEL_INFO(dev)->gen >= 9) { |
| 15178 | if (pipe == PIPE_C) |
| 15179 | intel_crtc->num_scalers = 1; |
| 15180 | else |
| 15181 | intel_crtc->num_scalers = SKL_NUM_SCALERS; |
| 15182 | |
| 15183 | skl_init_scalers(dev, intel_crtc, crtc_state); |
| 15184 | } |
| 15185 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 15186 | primary = intel_primary_plane_create(dev, pipe); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15187 | if (!primary) |
| 15188 | goto fail; |
| 15189 | |
| 15190 | cursor = intel_cursor_plane_create(dev, pipe); |
| 15191 | if (!cursor) |
| 15192 | goto fail; |
| 15193 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 15194 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
Ville Syrjälä | 4d5d72b7 | 2016-05-27 20:59:21 +0300 | [diff] [blame] | 15195 | cursor, &intel_crtc_funcs, |
| 15196 | "pipe %c", pipe_name(pipe)); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15197 | if (ret) |
| 15198 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15199 | |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 15200 | /* |
| 15201 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
Daniel Vetter | 8c0f92e | 2014-06-16 02:08:26 +0200 | [diff] [blame] | 15202 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 15203 | */ |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 15204 | intel_crtc->pipe = pipe; |
| 15205 | intel_crtc->plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 15206 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 15207 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 15208 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 15209 | } |
| 15210 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 15211 | intel_crtc->cursor_base = ~0; |
| 15212 | intel_crtc->cursor_cntl = ~0; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 15213 | intel_crtc->cursor_size = ~0; |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 15214 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 15215 | intel_crtc->wm.cxsr_allowed = true; |
| 15216 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 15217 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 15218 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 15219 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 15220 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 15221 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15222 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 15223 | |
Lionel Landwerlin | 8563b1e | 2016-03-16 10:57:14 +0000 | [diff] [blame] | 15224 | intel_color_init(&intel_crtc->base); |
| 15225 | |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 15226 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15227 | return; |
| 15228 | |
| 15229 | fail: |
Ville Syrjälä | 69ae561 | 2016-05-27 20:59:22 +0300 | [diff] [blame] | 15230 | intel_plane_destroy(primary); |
| 15231 | intel_plane_destroy(cursor); |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 15232 | kfree(crtc_state); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 15233 | kfree(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15234 | } |
| 15235 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 15236 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
| 15237 | { |
| 15238 | struct drm_encoder *encoder = connector->base.encoder; |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 15239 | struct drm_device *dev = connector->base.dev; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 15240 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 15241 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 15242 | |
Ville Syrjälä | d3babd3 | 2014-11-07 11:16:01 +0200 | [diff] [blame] | 15243 | if (!encoder || WARN_ON(!encoder->crtc)) |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 15244 | return INVALID_PIPE; |
| 15245 | |
| 15246 | return to_intel_crtc(encoder->crtc)->pipe; |
| 15247 | } |
| 15248 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15249 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 15250 | struct drm_file *file) |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15251 | { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15252 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 15253 | struct drm_crtc *drmmode_crtc; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 15254 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15255 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 15256 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
Chris Wilson | 71240ed | 2016-06-24 14:00:24 +0100 | [diff] [blame] | 15257 | if (!drmmode_crtc) |
Ville Syrjälä | 3f2c205 | 2013-10-17 13:35:03 +0300 | [diff] [blame] | 15258 | return -ENOENT; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15259 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 15260 | crtc = to_intel_crtc(drmmode_crtc); |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 15261 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15262 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 15263 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 15264 | } |
| 15265 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 15266 | static int intel_encoder_clones(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15267 | { |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 15268 | struct drm_device *dev = encoder->base.dev; |
| 15269 | struct intel_encoder *source_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15270 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15271 | int entry = 0; |
| 15272 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 15273 | for_each_intel_encoder(dev, source_encoder) { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 15274 | if (encoders_cloneable(encoder, source_encoder)) |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 15275 | index_mask |= (1 << entry); |
| 15276 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15277 | entry++; |
| 15278 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 15279 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15280 | return index_mask; |
| 15281 | } |
| 15282 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 15283 | static bool has_edp_a(struct drm_device *dev) |
| 15284 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 15285 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 15286 | |
| 15287 | if (!IS_MOBILE(dev)) |
| 15288 | return false; |
| 15289 | |
| 15290 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 15291 | return false; |
| 15292 | |
Damien Lespiau | e358990 | 2014-02-07 19:12:50 +0000 | [diff] [blame] | 15293 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 15294 | return false; |
| 15295 | |
| 15296 | return true; |
| 15297 | } |
| 15298 | |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 15299 | static bool intel_crt_present(struct drm_device *dev) |
| 15300 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 15301 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 15302 | |
Damien Lespiau | 884497e | 2013-12-03 13:56:23 +0000 | [diff] [blame] | 15303 | if (INTEL_INFO(dev)->gen >= 9) |
| 15304 | return false; |
| 15305 | |
Damien Lespiau | cf404ce | 2014-10-01 20:04:15 +0100 | [diff] [blame] | 15306 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 15307 | return false; |
| 15308 | |
| 15309 | if (IS_CHERRYVIEW(dev)) |
| 15310 | return false; |
| 15311 | |
Ville Syrjälä | 65e472e | 2015-12-01 23:28:55 +0200 | [diff] [blame] | 15312 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
| 15313 | return false; |
| 15314 | |
Ville Syrjälä | 70ac54d | 2015-12-01 23:29:56 +0200 | [diff] [blame] | 15315 | /* DDI E can't be used if DDI A requires 4 lanes */ |
| 15316 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
| 15317 | return false; |
| 15318 | |
Ville Syrjälä | e4abb73 | 2015-12-01 23:31:33 +0200 | [diff] [blame] | 15319 | if (!dev_priv->vbt.int_crt_support) |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 15320 | return false; |
| 15321 | |
| 15322 | return true; |
| 15323 | } |
| 15324 | |
Imre Deak | 8090ba8 | 2016-08-10 14:07:33 +0300 | [diff] [blame] | 15325 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
| 15326 | { |
| 15327 | int pps_num; |
| 15328 | int pps_idx; |
| 15329 | |
| 15330 | if (HAS_DDI(dev_priv)) |
| 15331 | return; |
| 15332 | /* |
| 15333 | * This w/a is needed at least on CPT/PPT, but to be sure apply it |
| 15334 | * everywhere where registers can be write protected. |
| 15335 | */ |
| 15336 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 15337 | pps_num = 2; |
| 15338 | else |
| 15339 | pps_num = 1; |
| 15340 | |
| 15341 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { |
| 15342 | u32 val = I915_READ(PP_CONTROL(pps_idx)); |
| 15343 | |
| 15344 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; |
| 15345 | I915_WRITE(PP_CONTROL(pps_idx), val); |
| 15346 | } |
| 15347 | } |
| 15348 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 15349 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
| 15350 | { |
| 15351 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) |
| 15352 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
| 15353 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 15354 | dev_priv->pps_mmio_base = VLV_PPS_BASE; |
| 15355 | else |
| 15356 | dev_priv->pps_mmio_base = PPS_BASE; |
Imre Deak | 8090ba8 | 2016-08-10 14:07:33 +0300 | [diff] [blame] | 15357 | |
| 15358 | intel_pps_unlock_regs_wa(dev_priv); |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 15359 | } |
| 15360 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15361 | static void intel_setup_outputs(struct drm_device *dev) |
| 15362 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 15363 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 15364 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 15365 | bool dpd_is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15366 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 15367 | intel_pps_init(dev_priv); |
| 15368 | |
Imre Deak | 97a824e1 | 2016-06-21 11:51:47 +0300 | [diff] [blame] | 15369 | /* |
| 15370 | * intel_edp_init_connector() depends on this completing first, to |
| 15371 | * prevent the registeration of both eDP and LVDS and the incorrect |
| 15372 | * sharing of the PPS. |
| 15373 | */ |
Daniel Vetter | c909335 | 2013-06-06 22:22:47 +0200 | [diff] [blame] | 15374 | intel_lvds_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15375 | |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 15376 | if (intel_crt_present(dev)) |
Paulo Zanoni | 79935fc | 2012-11-20 13:27:40 -0200 | [diff] [blame] | 15377 | intel_crt_init(dev); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 15378 | |
Vandana Kannan | c776eb2 | 2014-08-19 12:05:01 +0530 | [diff] [blame] | 15379 | if (IS_BROXTON(dev)) { |
| 15380 | /* |
| 15381 | * FIXME: Broxton doesn't support port detection via the |
| 15382 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to |
| 15383 | * detect the ports. |
| 15384 | */ |
| 15385 | intel_ddi_init(dev, PORT_A); |
| 15386 | intel_ddi_init(dev, PORT_B); |
| 15387 | intel_ddi_init(dev, PORT_C); |
Shashank Sharma | c6c794a | 2016-03-22 12:01:50 +0200 | [diff] [blame] | 15388 | |
| 15389 | intel_dsi_init(dev); |
Vandana Kannan | c776eb2 | 2014-08-19 12:05:01 +0530 | [diff] [blame] | 15390 | } else if (HAS_DDI(dev)) { |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 15391 | int found; |
| 15392 | |
Jesse Barnes | de31fac | 2015-03-06 15:53:32 -0800 | [diff] [blame] | 15393 | /* |
| 15394 | * Haswell uses DDI functions to detect digital outputs. |
| 15395 | * On SKL pre-D0 the strap isn't connected, so we assume |
| 15396 | * it's there. |
| 15397 | */ |
Ville Syrjälä | 7717940 | 2015-09-18 20:03:35 +0300 | [diff] [blame] | 15398 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
Jesse Barnes | de31fac | 2015-03-06 15:53:32 -0800 | [diff] [blame] | 15399 | /* WaIgnoreDDIAStrap: skl */ |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 15400 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 15401 | intel_ddi_init(dev, PORT_A); |
| 15402 | |
| 15403 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
| 15404 | * register */ |
| 15405 | found = I915_READ(SFUSE_STRAP); |
| 15406 | |
| 15407 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
| 15408 | intel_ddi_init(dev, PORT_B); |
| 15409 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
| 15410 | intel_ddi_init(dev, PORT_C); |
| 15411 | if (found & SFUSE_STRAP_DDID_DETECTED) |
| 15412 | intel_ddi_init(dev, PORT_D); |
Rodrigo Vivi | 2800e4c | 2015-08-07 17:35:21 -0700 | [diff] [blame] | 15413 | /* |
| 15414 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. |
| 15415 | */ |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 15416 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
Rodrigo Vivi | 2800e4c | 2015-08-07 17:35:21 -0700 | [diff] [blame] | 15417 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
| 15418 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || |
| 15419 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) |
| 15420 | intel_ddi_init(dev, PORT_E); |
| 15421 | |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 15422 | } else if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 15423 | int found; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 15424 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 15425 | |
| 15426 | if (has_edp_a(dev)) |
| 15427 | intel_dp_init(dev, DP_A, PORT_A); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 15428 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 15429 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 15430 | /* PCH SDVOB multiplex with HDMIB */ |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 15431 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 15432 | if (!found) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15433 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 15434 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 15435 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 15436 | } |
| 15437 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 15438 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15439 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 15440 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 15441 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15442 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 15443 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 15444 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 15445 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 15446 | |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 15447 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 15448 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 15449 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15450 | bool has_edp, has_port; |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 15451 | |
Ville Syrjälä | e17ac6d | 2014-10-09 19:37:15 +0300 | [diff] [blame] | 15452 | /* |
| 15453 | * The DP_DETECTED bit is the latched state of the DDC |
| 15454 | * SDA pin at boot. However since eDP doesn't require DDC |
| 15455 | * (no way to plug in a DP->HDMI dongle) the DDC pins for |
| 15456 | * eDP ports may have been muxed to an alternate function. |
| 15457 | * Thus we can't rely on the DP_DETECTED bit alone to detect |
| 15458 | * eDP ports. Consult the VBT as well as DP_DETECTED to |
| 15459 | * detect eDP ports. |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15460 | * |
| 15461 | * Sadly the straps seem to be missing sometimes even for HDMI |
| 15462 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap |
| 15463 | * and VBT for the presence of the port. Additionally we can't |
| 15464 | * trust the port type the VBT declares as we've seen at least |
| 15465 | * HDMI ports that the VBT claim are DP or eDP. |
Ville Syrjälä | e17ac6d | 2014-10-09 19:37:15 +0300 | [diff] [blame] | 15466 | */ |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 15467 | has_edp = intel_dp_is_edp(dev, PORT_B); |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15468 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
| 15469 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 15470 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15471 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 15472 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
Artem Bityutskiy | 585a94b | 2013-10-16 18:10:41 +0300 | [diff] [blame] | 15473 | |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 15474 | has_edp = intel_dp_is_edp(dev, PORT_C); |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15475 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
| 15476 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 15477 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15478 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 15479 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 15480 | |
Ville Syrjälä | 9418c1f | 2014-04-09 13:28:56 +0300 | [diff] [blame] | 15481 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15482 | /* |
| 15483 | * eDP not supported on port D, |
| 15484 | * so no need to worry about it |
| 15485 | */ |
| 15486 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); |
| 15487 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 15488 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
Ville Syrjälä | 22f35042 | 2016-06-03 12:17:43 +0300 | [diff] [blame] | 15489 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
| 15490 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); |
Ville Syrjälä | 9418c1f | 2014-04-09 13:28:56 +0300 | [diff] [blame] | 15491 | } |
| 15492 | |
Jani Nikula | 3cfca97 | 2013-08-27 15:12:26 +0300 | [diff] [blame] | 15493 | intel_dsi_init(dev); |
Daniel Vetter | 09da55d | 2015-07-07 11:44:32 +0200 | [diff] [blame] | 15494 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 15495 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 15496 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15497 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15498 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 15499 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 15500 | if (!found && IS_G4X(dev)) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15501 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15502 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15503 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 15504 | |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 15505 | if (!found && IS_G4X(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 15506 | intel_dp_init(dev, DP_B, PORT_B); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 15507 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 15508 | |
| 15509 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 15510 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15511 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15512 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 15513 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15514 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 15515 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15516 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 15517 | |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 15518 | if (IS_G4X(dev)) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15519 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 15520 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 15521 | } |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 15522 | if (IS_G4X(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 15523 | intel_dp_init(dev, DP_C, PORT_C); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 15524 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 15525 | |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 15526 | if (IS_G4X(dev) && |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 15527 | (I915_READ(DP_D) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 15528 | intel_dp_init(dev, DP_D, PORT_D); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 15529 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15530 | intel_dvo_init(dev); |
| 15531 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 15532 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15533 | intel_tv_init(dev); |
| 15534 | |
Rodrigo Vivi | 0bc12bc | 2014-11-14 08:52:28 -0800 | [diff] [blame] | 15535 | intel_psr_init(dev); |
Rodrigo Vivi | 7c8f8a7 | 2014-06-13 05:10:03 -0700 | [diff] [blame] | 15536 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 15537 | for_each_intel_encoder(dev, encoder) { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 15538 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 15539 | encoder->base.possible_clones = |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 15540 | intel_encoder_clones(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15541 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 15542 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 15543 | intel_init_pch_refclk(dev); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 15544 | |
| 15545 | drm_helper_move_panel_connectors_to_head(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15546 | } |
| 15547 | |
| 15548 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 15549 | { |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 15550 | struct drm_device *dev = fb->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15551 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15552 | |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 15553 | drm_framebuffer_cleanup(fb); |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 15554 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 15555 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
Chris Wilson | f8c417c | 2016-07-20 13:31:53 +0100 | [diff] [blame] | 15556 | i915_gem_object_put(intel_fb->obj); |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 15557 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15558 | kfree(intel_fb); |
| 15559 | } |
| 15560 | |
| 15561 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 15562 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15563 | unsigned int *handle) |
| 15564 | { |
| 15565 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 15566 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15567 | |
Chris Wilson | cc917ab | 2015-10-13 14:22:26 +0100 | [diff] [blame] | 15568 | if (obj->userptr.mm) { |
| 15569 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); |
| 15570 | return -EINVAL; |
| 15571 | } |
| 15572 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 15573 | return drm_gem_handle_create(file, &obj->base, handle); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15574 | } |
| 15575 | |
Rodrigo Vivi | 86c9858 | 2015-07-08 16:22:45 -0700 | [diff] [blame] | 15576 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
| 15577 | struct drm_file *file, |
| 15578 | unsigned flags, unsigned color, |
| 15579 | struct drm_clip_rect *clips, |
| 15580 | unsigned num_clips) |
| 15581 | { |
| 15582 | struct drm_device *dev = fb->dev; |
| 15583 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 15584 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 15585 | |
| 15586 | mutex_lock(&dev->struct_mutex); |
Paulo Zanoni | 74b4ea1 | 2015-07-14 16:29:14 -0300 | [diff] [blame] | 15587 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
Rodrigo Vivi | 86c9858 | 2015-07-08 16:22:45 -0700 | [diff] [blame] | 15588 | mutex_unlock(&dev->struct_mutex); |
| 15589 | |
| 15590 | return 0; |
| 15591 | } |
| 15592 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15593 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 15594 | .destroy = intel_user_framebuffer_destroy, |
| 15595 | .create_handle = intel_user_framebuffer_create_handle, |
Rodrigo Vivi | 86c9858 | 2015-07-08 16:22:45 -0700 | [diff] [blame] | 15596 | .dirty = intel_user_framebuffer_dirty, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15597 | }; |
| 15598 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15599 | static |
| 15600 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, |
| 15601 | uint32_t pixel_format) |
| 15602 | { |
| 15603 | u32 gen = INTEL_INFO(dev)->gen; |
| 15604 | |
| 15605 | if (gen >= 9) { |
Ville Syrjälä | ac48496 | 2016-01-20 21:05:26 +0200 | [diff] [blame] | 15606 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
| 15607 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15608 | /* "The stride in bytes must not exceed the of the size of 8K |
| 15609 | * pixels and 32K bytes." |
| 15610 | */ |
Ville Syrjälä | ac48496 | 2016-01-20 21:05:26 +0200 | [diff] [blame] | 15611 | return min(8192 * cpp, 32768); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 15612 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15613 | return 32*1024; |
| 15614 | } else if (gen >= 4) { |
| 15615 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
| 15616 | return 16*1024; |
| 15617 | else |
| 15618 | return 32*1024; |
| 15619 | } else if (gen >= 3) { |
| 15620 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
| 15621 | return 8*1024; |
| 15622 | else |
| 15623 | return 16*1024; |
| 15624 | } else { |
| 15625 | /* XXX DSPC is limited to 4k tiled */ |
| 15626 | return 8*1024; |
| 15627 | } |
| 15628 | } |
| 15629 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 15630 | static int intel_framebuffer_init(struct drm_device *dev, |
| 15631 | struct intel_framebuffer *intel_fb, |
| 15632 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 15633 | struct drm_i915_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15634 | { |
Ville Syrjälä | 7b49f94 | 2016-01-12 21:08:32 +0200 | [diff] [blame] | 15635 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | c2ff737 | 2016-02-11 19:16:37 +0200 | [diff] [blame] | 15636 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15637 | int ret; |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15638 | u32 pitch_limit, stride_alignment; |
Eric Engestrom | d382814 | 2016-08-15 16:29:55 +0100 | [diff] [blame] | 15639 | char *format_name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15640 | |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 15641 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 15642 | |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 15643 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
Ville Syrjälä | c2ff737 | 2016-02-11 19:16:37 +0200 | [diff] [blame] | 15644 | /* |
| 15645 | * If there's a fence, enforce that |
| 15646 | * the fb modifier and tiling mode match. |
| 15647 | */ |
| 15648 | if (tiling != I915_TILING_NONE && |
| 15649 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 15650 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
| 15651 | return -EINVAL; |
| 15652 | } |
| 15653 | } else { |
Ville Syrjälä | c2ff737 | 2016-02-11 19:16:37 +0200 | [diff] [blame] | 15654 | if (tiling == I915_TILING_X) { |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 15655 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
Ville Syrjälä | c2ff737 | 2016-02-11 19:16:37 +0200 | [diff] [blame] | 15656 | } else if (tiling == I915_TILING_Y) { |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 15657 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
| 15658 | return -EINVAL; |
| 15659 | } |
| 15660 | } |
| 15661 | |
Tvrtko Ursulin | 9a8f0a1 | 2015-02-27 11:15:24 +0000 | [diff] [blame] | 15662 | /* Passed in modifier sanity checking. */ |
| 15663 | switch (mode_cmd->modifier[0]) { |
| 15664 | case I915_FORMAT_MOD_Y_TILED: |
| 15665 | case I915_FORMAT_MOD_Yf_TILED: |
| 15666 | if (INTEL_INFO(dev)->gen < 9) { |
| 15667 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
| 15668 | mode_cmd->modifier[0]); |
| 15669 | return -EINVAL; |
| 15670 | } |
| 15671 | case DRM_FORMAT_MOD_NONE: |
| 15672 | case I915_FORMAT_MOD_X_TILED: |
| 15673 | break; |
| 15674 | default: |
Jesse Barnes | c0f4042 | 2015-03-23 12:43:50 -0700 | [diff] [blame] | 15675 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
| 15676 | mode_cmd->modifier[0]); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 15677 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15678 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 15679 | |
Ville Syrjälä | c2ff737 | 2016-02-11 19:16:37 +0200 | [diff] [blame] | 15680 | /* |
| 15681 | * gen2/3 display engine uses the fence if present, |
| 15682 | * so the tiling mode must match the fb modifier exactly. |
| 15683 | */ |
| 15684 | if (INTEL_INFO(dev_priv)->gen < 4 && |
| 15685 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
| 15686 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); |
| 15687 | return -EINVAL; |
| 15688 | } |
| 15689 | |
Ville Syrjälä | 7b49f94 | 2016-01-12 21:08:32 +0200 | [diff] [blame] | 15690 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
| 15691 | mode_cmd->modifier[0], |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15692 | mode_cmd->pixel_format); |
| 15693 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { |
| 15694 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", |
| 15695 | mode_cmd->pitches[0], stride_alignment); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 15696 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15697 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 15698 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15699 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
| 15700 | mode_cmd->pixel_format); |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 15701 | if (mode_cmd->pitches[0] > pitch_limit) { |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 15702 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
| 15703 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 15704 | "tiled" : "linear", |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 15705 | mode_cmd->pitches[0], pitch_limit); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 15706 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15707 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 15708 | |
Ville Syrjälä | c2ff737 | 2016-02-11 19:16:37 +0200 | [diff] [blame] | 15709 | /* |
| 15710 | * If there's a fence, enforce that |
| 15711 | * the fb pitch and fence stride match. |
| 15712 | */ |
| 15713 | if (tiling != I915_TILING_NONE && |
Chris Wilson | 3e510a8 | 2016-08-05 10:14:23 +0100 | [diff] [blame] | 15714 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15715 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
Chris Wilson | 3e510a8 | 2016-08-05 10:14:23 +0100 | [diff] [blame] | 15716 | mode_cmd->pitches[0], |
| 15717 | i915_gem_object_get_stride(obj)); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 15718 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15719 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 15720 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15721 | /* Reject formats not supported by any plane early. */ |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 15722 | switch (mode_cmd->pixel_format) { |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15723 | case DRM_FORMAT_C8: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 15724 | case DRM_FORMAT_RGB565: |
| 15725 | case DRM_FORMAT_XRGB8888: |
| 15726 | case DRM_FORMAT_ARGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15727 | break; |
| 15728 | case DRM_FORMAT_XRGB1555: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15729 | if (INTEL_INFO(dev)->gen > 3) { |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 15730 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
| 15731 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); |
| 15732 | kfree(format_name); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15733 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15734 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15735 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15736 | case DRM_FORMAT_ABGR8888: |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 15737 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 15738 | INTEL_INFO(dev)->gen < 9) { |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 15739 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
| 15740 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); |
| 15741 | kfree(format_name); |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 15742 | return -EINVAL; |
| 15743 | } |
| 15744 | break; |
| 15745 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 15746 | case DRM_FORMAT_XRGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15747 | case DRM_FORMAT_XBGR2101010: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15748 | if (INTEL_INFO(dev)->gen < 4) { |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 15749 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
| 15750 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); |
| 15751 | kfree(format_name); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15752 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15753 | } |
Jesse Barnes | b562674 | 2011-06-24 12:19:27 -0700 | [diff] [blame] | 15754 | break; |
Damien Lespiau | 7531208 | 2015-05-15 19:06:01 +0100 | [diff] [blame] | 15755 | case DRM_FORMAT_ABGR2101010: |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 15756 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 15757 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
| 15758 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); |
| 15759 | kfree(format_name); |
Damien Lespiau | 7531208 | 2015-05-15 19:06:01 +0100 | [diff] [blame] | 15760 | return -EINVAL; |
| 15761 | } |
| 15762 | break; |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 15763 | case DRM_FORMAT_YUYV: |
| 15764 | case DRM_FORMAT_UYVY: |
| 15765 | case DRM_FORMAT_YVYU: |
| 15766 | case DRM_FORMAT_VYUY: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15767 | if (INTEL_INFO(dev)->gen < 5) { |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 15768 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
| 15769 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); |
| 15770 | kfree(format_name); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 15771 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 15772 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 15773 | break; |
| 15774 | default: |
Eric Engestrom | 90844f0 | 2016-08-15 01:02:38 +0100 | [diff] [blame] | 15775 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
| 15776 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); |
| 15777 | kfree(format_name); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 15778 | return -EINVAL; |
| 15779 | } |
| 15780 | |
Ville Syrjälä | 90f9a33 | 2012-10-31 17:50:19 +0200 | [diff] [blame] | 15781 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 15782 | if (mode_cmd->offsets[0] != 0) |
| 15783 | return -EINVAL; |
| 15784 | |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 15785 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
| 15786 | intel_fb->obj = obj; |
| 15787 | |
Ville Syrjälä | 6687c90 | 2015-09-15 13:16:41 +0300 | [diff] [blame] | 15788 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
| 15789 | if (ret) |
| 15790 | return ret; |
Ville Syrjälä | 2d7a215 | 2016-02-15 22:54:47 +0200 | [diff] [blame] | 15791 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15792 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 15793 | if (ret) { |
| 15794 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 15795 | return ret; |
| 15796 | } |
| 15797 | |
Ville Syrjälä | 0b05e1e | 2016-01-14 15:22:09 +0200 | [diff] [blame] | 15798 | intel_fb->obj->framebuffer_references++; |
| 15799 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15800 | return 0; |
| 15801 | } |
| 15802 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15803 | static struct drm_framebuffer * |
| 15804 | intel_user_framebuffer_create(struct drm_device *dev, |
| 15805 | struct drm_file *filp, |
Ville Syrjälä | 1eb83451 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 15806 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15807 | { |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 15808 | struct drm_framebuffer *fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 15809 | struct drm_i915_gem_object *obj; |
Ville Syrjälä | 76dc376 | 2015-11-11 19:11:28 +0200 | [diff] [blame] | 15810 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15811 | |
Chris Wilson | 03ac064 | 2016-07-20 13:31:51 +0100 | [diff] [blame] | 15812 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
| 15813 | if (!obj) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 15814 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15815 | |
Daniel Vetter | 92907cb | 2015-11-23 09:04:05 +0100 | [diff] [blame] | 15816 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 15817 | if (IS_ERR(fb)) |
Chris Wilson | 34911fd | 2016-07-20 13:31:54 +0100 | [diff] [blame] | 15818 | i915_gem_object_put_unlocked(obj); |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 15819 | |
| 15820 | return fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15821 | } |
| 15822 | |
Daniel Vetter | 0695726 | 2015-08-10 13:34:08 +0200 | [diff] [blame] | 15823 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 15824 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 15825 | { |
| 15826 | } |
| 15827 | #endif |
| 15828 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15829 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15830 | .fb_create = intel_user_framebuffer_create, |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 15831 | .output_poll_changed = intel_fbdev_output_poll_changed, |
Matt Roper | 5ee67f1 | 2015-01-21 16:35:44 -0800 | [diff] [blame] | 15832 | .atomic_check = intel_atomic_check, |
| 15833 | .atomic_commit = intel_atomic_commit, |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 15834 | .atomic_state_alloc = intel_atomic_state_alloc, |
| 15835 | .atomic_state_clear = intel_atomic_state_clear, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15836 | }; |
| 15837 | |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15838 | /** |
| 15839 | * intel_init_display_hooks - initialize the display modesetting hooks |
| 15840 | * @dev_priv: device private |
| 15841 | */ |
| 15842 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15843 | { |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15844 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 15845 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 15846 | dev_priv->display.get_initial_plane_config = |
| 15847 | skylake_get_initial_plane_config; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 15848 | dev_priv->display.crtc_compute_clock = |
| 15849 | haswell_crtc_compute_clock; |
| 15850 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 15851 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15852 | } else if (HAS_DDI(dev_priv)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 15853 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 15854 | dev_priv->display.get_initial_plane_config = |
| 15855 | ironlake_get_initial_plane_config; |
Ander Conselvan de Oliveira | 797d025 | 2014-10-29 11:32:34 +0200 | [diff] [blame] | 15856 | dev_priv->display.crtc_compute_clock = |
| 15857 | haswell_crtc_compute_clock; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 15858 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 15859 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15860 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 15861 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 15862 | dev_priv->display.get_initial_plane_config = |
| 15863 | ironlake_get_initial_plane_config; |
Ander Conselvan de Oliveira | 3fb3770 | 2014-10-29 11:32:35 +0200 | [diff] [blame] | 15864 | dev_priv->display.crtc_compute_clock = |
| 15865 | ironlake_crtc_compute_clock; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 15866 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
| 15867 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 15868 | } else if (IS_CHERRYVIEW(dev_priv)) { |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 15869 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 15870 | dev_priv->display.get_initial_plane_config = |
| 15871 | i9xx_get_initial_plane_config; |
Ander Conselvan de Oliveira | 65b3d6a | 2016-03-21 18:00:13 +0200 | [diff] [blame] | 15872 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
| 15873 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 15874 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 15875 | } else if (IS_VALLEYVIEW(dev_priv)) { |
| 15876 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 15877 | dev_priv->display.get_initial_plane_config = |
| 15878 | i9xx_get_initial_plane_config; |
| 15879 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 15880 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 15881 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Ander Conselvan de Oliveira | 19ec669 | 2016-03-21 18:00:15 +0200 | [diff] [blame] | 15882 | } else if (IS_G4X(dev_priv)) { |
| 15883 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 15884 | dev_priv->display.get_initial_plane_config = |
| 15885 | i9xx_get_initial_plane_config; |
| 15886 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; |
| 15887 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 15888 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Ander Conselvan de Oliveira | 70e8aa2 | 2016-03-21 18:00:16 +0200 | [diff] [blame] | 15889 | } else if (IS_PINEVIEW(dev_priv)) { |
| 15890 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 15891 | dev_priv->display.get_initial_plane_config = |
| 15892 | i9xx_get_initial_plane_config; |
| 15893 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; |
| 15894 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 15895 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 15896 | } else if (!IS_GEN2(dev_priv)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 15897 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 15898 | dev_priv->display.get_initial_plane_config = |
| 15899 | i9xx_get_initial_plane_config; |
Ander Conselvan de Oliveira | d6dfee7 | 2014-10-29 11:32:36 +0200 | [diff] [blame] | 15900 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 15901 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 15902 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Ander Conselvan de Oliveira | 81c97f5 | 2016-03-22 15:35:23 +0200 | [diff] [blame] | 15903 | } else { |
| 15904 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 15905 | dev_priv->display.get_initial_plane_config = |
| 15906 | i9xx_get_initial_plane_config; |
| 15907 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; |
| 15908 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 15909 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 15910 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15911 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15912 | /* Returns the core display clock speed */ |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15913 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 15914 | dev_priv->display.get_display_clock_speed = |
| 15915 | skylake_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15916 | else if (IS_BROXTON(dev_priv)) |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 15917 | dev_priv->display.get_display_clock_speed = |
| 15918 | broxton_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15919 | else if (IS_BROADWELL(dev_priv)) |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 15920 | dev_priv->display.get_display_clock_speed = |
| 15921 | broadwell_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15922 | else if (IS_HASWELL(dev_priv)) |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 15923 | dev_priv->display.get_display_clock_speed = |
| 15924 | haswell_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15925 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 15926 | dev_priv->display.get_display_clock_speed = |
| 15927 | valleyview_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15928 | else if (IS_GEN5(dev_priv)) |
Ville Syrjälä | b37a643 | 2015-03-31 14:11:54 +0300 | [diff] [blame] | 15929 | dev_priv->display.get_display_clock_speed = |
| 15930 | ilk_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15931 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
| 15932 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15933 | dev_priv->display.get_display_clock_speed = |
| 15934 | i945_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15935 | else if (IS_GM45(dev_priv)) |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 15936 | dev_priv->display.get_display_clock_speed = |
| 15937 | gm45_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15938 | else if (IS_CRESTLINE(dev_priv)) |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 15939 | dev_priv->display.get_display_clock_speed = |
| 15940 | i965gm_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15941 | else if (IS_PINEVIEW(dev_priv)) |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 15942 | dev_priv->display.get_display_clock_speed = |
| 15943 | pnv_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15944 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 15945 | dev_priv->display.get_display_clock_speed = |
| 15946 | g33_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15947 | else if (IS_I915G(dev_priv)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15948 | dev_priv->display.get_display_clock_speed = |
| 15949 | i915_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15950 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15951 | dev_priv->display.get_display_clock_speed = |
| 15952 | i9xx_misc_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15953 | else if (IS_I915GM(dev_priv)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15954 | dev_priv->display.get_display_clock_speed = |
| 15955 | i915gm_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15956 | else if (IS_I865G(dev_priv)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15957 | dev_priv->display.get_display_clock_speed = |
| 15958 | i865_get_display_clock_speed; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15959 | else if (IS_I85X(dev_priv)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15960 | dev_priv->display.get_display_clock_speed = |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 15961 | i85x_get_display_clock_speed; |
Ville Syrjälä | 623e01e | 2015-05-22 11:22:34 +0300 | [diff] [blame] | 15962 | else { /* 830 */ |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15963 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15964 | dev_priv->display.get_display_clock_speed = |
| 15965 | i830_get_display_clock_speed; |
Ville Syrjälä | 623e01e | 2015-05-22 11:22:34 +0300 | [diff] [blame] | 15966 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15967 | |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15968 | if (IS_GEN5(dev_priv)) { |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15969 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15970 | } else if (IS_GEN6(dev_priv)) { |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15971 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15972 | } else if (IS_IVYBRIDGE(dev_priv)) { |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15973 | /* FIXME: detect B0+ stepping and use auto training */ |
| 15974 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15975 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15976 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
Ville Syrjälä | 445e780 | 2016-05-11 22:44:42 +0300 | [diff] [blame] | 15977 | } |
| 15978 | |
| 15979 | if (IS_BROADWELL(dev_priv)) { |
| 15980 | dev_priv->display.modeset_commit_cdclk = |
| 15981 | broadwell_modeset_commit_cdclk; |
| 15982 | dev_priv->display.modeset_calc_cdclk = |
| 15983 | broadwell_modeset_calc_cdclk; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15984 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 15985 | dev_priv->display.modeset_commit_cdclk = |
| 15986 | valleyview_modeset_commit_cdclk; |
| 15987 | dev_priv->display.modeset_calc_cdclk = |
| 15988 | valleyview_modeset_calc_cdclk; |
Imre Deak | 8821294 | 2016-03-16 13:38:53 +0200 | [diff] [blame] | 15989 | } else if (IS_BROXTON(dev_priv)) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 15990 | dev_priv->display.modeset_commit_cdclk = |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 15991 | bxt_modeset_commit_cdclk; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 15992 | dev_priv->display.modeset_calc_cdclk = |
Imre Deak | 324513c | 2016-06-13 16:44:36 +0300 | [diff] [blame] | 15993 | bxt_modeset_calc_cdclk; |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 15994 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
| 15995 | dev_priv->display.modeset_commit_cdclk = |
| 15996 | skl_modeset_commit_cdclk; |
| 15997 | dev_priv->display.modeset_calc_cdclk = |
| 15998 | skl_modeset_calc_cdclk; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15999 | } |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 16000 | |
Lyude | 2708249 | 2016-08-24 07:48:10 +0200 | [diff] [blame] | 16001 | if (dev_priv->info.gen >= 9) |
| 16002 | dev_priv->display.update_crtcs = skl_update_crtcs; |
| 16003 | else |
| 16004 | dev_priv->display.update_crtcs = intel_update_crtcs; |
| 16005 | |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 16006 | switch (INTEL_INFO(dev_priv)->gen) { |
| 16007 | case 2: |
| 16008 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 16009 | break; |
| 16010 | |
| 16011 | case 3: |
| 16012 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 16013 | break; |
| 16014 | |
| 16015 | case 4: |
| 16016 | case 5: |
| 16017 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 16018 | break; |
| 16019 | |
| 16020 | case 6: |
| 16021 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 16022 | break; |
| 16023 | case 7: |
| 16024 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
| 16025 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 16026 | break; |
| 16027 | case 9: |
| 16028 | /* Drop through - unsupported since execlist only. */ |
| 16029 | default: |
| 16030 | /* Default just returns -ENODEV to indicate unsupported */ |
| 16031 | dev_priv->display.queue_flip = intel_default_queue_flip; |
| 16032 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 16033 | } |
| 16034 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16035 | /* |
| 16036 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 16037 | * resume, or other times. This quirk makes sure that's the case for |
| 16038 | * affected systems. |
| 16039 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 16040 | static void quirk_pipea_force(struct drm_device *dev) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16041 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16042 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16043 | |
| 16044 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 16045 | DRM_INFO("applying pipe a force quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16046 | } |
| 16047 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 16048 | static void quirk_pipeb_force(struct drm_device *dev) |
| 16049 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16050 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 16051 | |
| 16052 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; |
| 16053 | DRM_INFO("applying pipe b force quirk\n"); |
| 16054 | } |
| 16055 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 16056 | /* |
| 16057 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 16058 | */ |
| 16059 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 16060 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16061 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 16062 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 16063 | DRM_INFO("applying lvds SSC disable quirk\n"); |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 16064 | } |
| 16065 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 16066 | /* |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 16067 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
| 16068 | * brightness value |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 16069 | */ |
| 16070 | static void quirk_invert_brightness(struct drm_device *dev) |
| 16071 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16072 | struct drm_i915_private *dev_priv = to_i915(dev); |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 16073 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 16074 | DRM_INFO("applying inverted panel brightness quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16075 | } |
| 16076 | |
Scot Doyle | 9c72cc6 | 2014-07-03 23:27:50 +0000 | [diff] [blame] | 16077 | /* Some VBT's incorrectly indicate no backlight is present */ |
| 16078 | static void quirk_backlight_present(struct drm_device *dev) |
| 16079 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16080 | struct drm_i915_private *dev_priv = to_i915(dev); |
Scot Doyle | 9c72cc6 | 2014-07-03 23:27:50 +0000 | [diff] [blame] | 16081 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
| 16082 | DRM_INFO("applying backlight present quirk\n"); |
| 16083 | } |
| 16084 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16085 | struct intel_quirk { |
| 16086 | int device; |
| 16087 | int subsystem_vendor; |
| 16088 | int subsystem_device; |
| 16089 | void (*hook)(struct drm_device *dev); |
| 16090 | }; |
| 16091 | |
Egbert Eich | 5f85f17 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 16092 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
| 16093 | struct intel_dmi_quirk { |
| 16094 | void (*hook)(struct drm_device *dev); |
| 16095 | const struct dmi_system_id (*dmi_id_list)[]; |
| 16096 | }; |
| 16097 | |
| 16098 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
| 16099 | { |
| 16100 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
| 16101 | return 1; |
| 16102 | } |
| 16103 | |
| 16104 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
| 16105 | { |
| 16106 | .dmi_id_list = &(const struct dmi_system_id[]) { |
| 16107 | { |
| 16108 | .callback = intel_dmi_reverse_brightness, |
| 16109 | .ident = "NCR Corporation", |
| 16110 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
| 16111 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
| 16112 | }, |
| 16113 | }, |
| 16114 | { } /* terminating entry */ |
| 16115 | }, |
| 16116 | .hook = quirk_invert_brightness, |
| 16117 | }, |
| 16118 | }; |
| 16119 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 16120 | static struct intel_quirk intel_quirks[] = { |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16121 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 16122 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 16123 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16124 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 16125 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 16126 | |
Ville Syrjälä | 5f080c0 | 2014-08-15 01:22:06 +0300 | [diff] [blame] | 16127 | /* 830 needs to leave pipe A & dpll A up */ |
| 16128 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 16129 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 16130 | /* 830 needs to leave pipe B & dpll B up */ |
| 16131 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, |
| 16132 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 16133 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 16134 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Michel Alexandre Salim | 070d329 | 2011-07-28 18:52:06 +0200 | [diff] [blame] | 16135 | |
| 16136 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 16137 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 16138 | |
Alexander van Heukelum | be505f6 | 2013-12-28 21:00:39 +0100 | [diff] [blame] | 16139 | /* Acer Aspire 5734Z must invert backlight brightness */ |
| 16140 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
| 16141 | |
| 16142 | /* Acer/eMachines G725 */ |
| 16143 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
| 16144 | |
| 16145 | /* Acer/eMachines e725 */ |
| 16146 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
| 16147 | |
| 16148 | /* Acer/Packard Bell NCL20 */ |
| 16149 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
| 16150 | |
| 16151 | /* Acer Aspire 4736Z */ |
| 16152 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
Jani Nikula | 0f540c3 | 2014-01-13 17:30:34 +0200 | [diff] [blame] | 16153 | |
| 16154 | /* Acer Aspire 5336 */ |
| 16155 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
Scot Doyle | 2e93a1a | 2014-07-03 23:27:51 +0000 | [diff] [blame] | 16156 | |
| 16157 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
| 16158 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
Scot Doyle | d4967d8 | 2014-07-03 23:27:52 +0000 | [diff] [blame] | 16159 | |
Scot Doyle | dfb3d47b | 2014-08-21 16:08:02 +0000 | [diff] [blame] | 16160 | /* Acer C720 Chromebook (Core i3 4005U) */ |
| 16161 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, |
| 16162 | |
jens stein | b2a9601 | 2014-10-28 20:25:53 +0100 | [diff] [blame] | 16163 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
| 16164 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, |
| 16165 | |
Jani Nikula | 1b9448b0 | 2015-11-05 11:49:59 +0200 | [diff] [blame] | 16166 | /* Apple Macbook 4,1 */ |
| 16167 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, |
| 16168 | |
Scot Doyle | d4967d8 | 2014-07-03 23:27:52 +0000 | [diff] [blame] | 16169 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
| 16170 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
Scot Doyle | 724cb06 | 2014-07-11 22:16:30 +0000 | [diff] [blame] | 16171 | |
| 16172 | /* HP Chromebook 14 (Celeron 2955U) */ |
| 16173 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
Jani Nikula | cf6f0af | 2015-02-19 10:53:39 +0200 | [diff] [blame] | 16174 | |
| 16175 | /* Dell Chromebook 11 */ |
| 16176 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, |
Jani Nikula | 9be64ee | 2015-10-30 14:50:24 +0200 | [diff] [blame] | 16177 | |
| 16178 | /* Dell Chromebook 11 (2015 version) */ |
| 16179 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16180 | }; |
| 16181 | |
| 16182 | static void intel_init_quirks(struct drm_device *dev) |
| 16183 | { |
| 16184 | struct pci_dev *d = dev->pdev; |
| 16185 | int i; |
| 16186 | |
| 16187 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 16188 | struct intel_quirk *q = &intel_quirks[i]; |
| 16189 | |
| 16190 | if (d->device == q->device && |
| 16191 | (d->subsystem_vendor == q->subsystem_vendor || |
| 16192 | q->subsystem_vendor == PCI_ANY_ID) && |
| 16193 | (d->subsystem_device == q->subsystem_device || |
| 16194 | q->subsystem_device == PCI_ANY_ID)) |
| 16195 | q->hook(dev); |
| 16196 | } |
Egbert Eich | 5f85f17 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 16197 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
| 16198 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
| 16199 | intel_dmi_quirks[i].hook(dev); |
| 16200 | } |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16201 | } |
| 16202 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16203 | /* Disable the VGA plane that we never use */ |
| 16204 | static void i915_disable_vga(struct drm_device *dev) |
| 16205 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16206 | struct drm_i915_private *dev_priv = to_i915(dev); |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 16207 | struct pci_dev *pdev = dev_priv->drm.pdev; |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16208 | u8 sr1; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 16209 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16210 | |
Ville Syrjälä | 2b37c61 | 2014-01-22 21:32:38 +0200 | [diff] [blame] | 16211 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 16212 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
Jesse Barnes | 3fdcf43 | 2012-04-06 11:46:27 -0700 | [diff] [blame] | 16213 | outb(SR01, VGA_SR_INDEX); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16214 | sr1 = inb(VGA_SR_DATA); |
| 16215 | outb(sr1 | 1<<5, VGA_SR_DATA); |
David Weinehall | 52a05c3 | 2016-08-22 13:32:44 +0300 | [diff] [blame] | 16216 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16217 | udelay(300); |
| 16218 | |
Ville Syrjälä | 01f5a62 | 2014-12-16 18:38:37 +0200 | [diff] [blame] | 16219 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16220 | POSTING_READ(vga_reg); |
| 16221 | } |
| 16222 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 16223 | void intel_modeset_init_hw(struct drm_device *dev) |
| 16224 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16225 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 16226 | |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 16227 | intel_update_cdclk(dev); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 16228 | |
| 16229 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
| 16230 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 16231 | intel_init_clock_gating(dev); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 16232 | } |
| 16233 | |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16234 | /* |
| 16235 | * Calculate what we think the watermarks should be for the state we've read |
| 16236 | * out of the hardware and then immediately program those watermarks so that |
| 16237 | * we ensure the hardware settings match our internal state. |
| 16238 | * |
| 16239 | * We can calculate what we think WM's should be by creating a duplicate of the |
| 16240 | * current state (which was constructed during hardware readout) and running it |
| 16241 | * through the atomic check code to calculate new watermark values in the |
| 16242 | * state object. |
| 16243 | */ |
| 16244 | static void sanitize_watermarks(struct drm_device *dev) |
| 16245 | { |
| 16246 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 16247 | struct drm_atomic_state *state; |
| 16248 | struct drm_crtc *crtc; |
| 16249 | struct drm_crtc_state *cstate; |
| 16250 | struct drm_modeset_acquire_ctx ctx; |
| 16251 | int ret; |
| 16252 | int i; |
| 16253 | |
| 16254 | /* Only supported on platforms that use atomic watermark design */ |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 16255 | if (!dev_priv->display.optimize_watermarks) |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16256 | return; |
| 16257 | |
| 16258 | /* |
| 16259 | * We need to hold connection_mutex before calling duplicate_state so |
| 16260 | * that the connector loop is protected. |
| 16261 | */ |
| 16262 | drm_modeset_acquire_init(&ctx, 0); |
| 16263 | retry: |
Matt Roper | 0cd1262 | 2016-01-12 07:13:37 -0800 | [diff] [blame] | 16264 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16265 | if (ret == -EDEADLK) { |
| 16266 | drm_modeset_backoff(&ctx); |
| 16267 | goto retry; |
| 16268 | } else if (WARN_ON(ret)) { |
Matt Roper | 0cd1262 | 2016-01-12 07:13:37 -0800 | [diff] [blame] | 16269 | goto fail; |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16270 | } |
| 16271 | |
| 16272 | state = drm_atomic_helper_duplicate_state(dev, &ctx); |
| 16273 | if (WARN_ON(IS_ERR(state))) |
Matt Roper | 0cd1262 | 2016-01-12 07:13:37 -0800 | [diff] [blame] | 16274 | goto fail; |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16275 | |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 16276 | /* |
| 16277 | * Hardware readout is the only time we don't want to calculate |
| 16278 | * intermediate watermarks (since we don't trust the current |
| 16279 | * watermarks). |
| 16280 | */ |
| 16281 | to_intel_atomic_state(state)->skip_intermediate_wm = true; |
| 16282 | |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16283 | ret = intel_atomic_check(dev, state); |
| 16284 | if (ret) { |
| 16285 | /* |
| 16286 | * If we fail here, it means that the hardware appears to be |
| 16287 | * programmed in a way that shouldn't be possible, given our |
| 16288 | * understanding of watermark requirements. This might mean a |
| 16289 | * mistake in the hardware readout code or a mistake in the |
| 16290 | * watermark calculations for a given platform. Raise a WARN |
| 16291 | * so that this is noticeable. |
| 16292 | * |
| 16293 | * If this actually happens, we'll have to just leave the |
| 16294 | * BIOS-programmed watermarks untouched and hope for the best. |
| 16295 | */ |
| 16296 | WARN(true, "Could not determine valid watermarks for inherited state\n"); |
Arnd Bergmann | b9a1b71 | 2016-10-18 17:16:23 +0200 | [diff] [blame^] | 16297 | goto put_state; |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16298 | } |
| 16299 | |
| 16300 | /* Write calculated watermark values back */ |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16301 | for_each_crtc_in_state(state, crtc, cstate, i) { |
| 16302 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
| 16303 | |
Matt Roper | ed4a6a7 | 2016-02-23 17:20:13 -0800 | [diff] [blame] | 16304 | cs->wm.need_postvbl_update = true; |
| 16305 | dev_priv->display.optimize_watermarks(cs); |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16306 | } |
| 16307 | |
Arnd Bergmann | b9a1b71 | 2016-10-18 17:16:23 +0200 | [diff] [blame^] | 16308 | put_state: |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 16309 | drm_atomic_state_put(state); |
Arnd Bergmann | b9a1b71 | 2016-10-18 17:16:23 +0200 | [diff] [blame^] | 16310 | fail: |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16311 | drm_modeset_drop_locks(&ctx); |
| 16312 | drm_modeset_acquire_fini(&ctx); |
| 16313 | } |
| 16314 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16315 | void intel_modeset_init(struct drm_device *dev) |
| 16316 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 16317 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 16318 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 16319 | int sprite, ret; |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 16320 | enum pipe pipe; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 16321 | struct intel_crtc *crtc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16322 | |
| 16323 | drm_mode_config_init(dev); |
| 16324 | |
| 16325 | dev->mode_config.min_width = 0; |
| 16326 | dev->mode_config.min_height = 0; |
| 16327 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 16328 | dev->mode_config.preferred_depth = 24; |
| 16329 | dev->mode_config.prefer_shadow = 1; |
| 16330 | |
Tvrtko Ursulin | 25bab38 | 2015-02-10 17:16:16 +0000 | [diff] [blame] | 16331 | dev->mode_config.allow_fb_modifiers = true; |
| 16332 | |
Laurent Pinchart | e6ecefa | 2012-05-17 13:27:23 +0200 | [diff] [blame] | 16333 | dev->mode_config.funcs = &intel_mode_funcs; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16334 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 16335 | intel_init_quirks(dev); |
| 16336 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 16337 | intel_init_pm(dev); |
| 16338 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 16339 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 16340 | return; |
| 16341 | |
Lukas Wunner | 69f92f6 | 2015-07-15 13:57:35 +0200 | [diff] [blame] | 16342 | /* |
| 16343 | * There may be no VBT; and if the BIOS enabled SSC we can |
| 16344 | * just keep using it to avoid unnecessary flicker. Whereas if the |
| 16345 | * BIOS isn't using it, don't assume it will work even if the VBT |
| 16346 | * indicates as much. |
| 16347 | */ |
| 16348 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 16349 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
| 16350 | DREF_SSC1_ENABLE); |
| 16351 | |
| 16352 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { |
| 16353 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", |
| 16354 | bios_lvds_use_ssc ? "en" : "dis", |
| 16355 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); |
| 16356 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
| 16357 | } |
| 16358 | } |
| 16359 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 16360 | if (IS_GEN2(dev)) { |
| 16361 | dev->mode_config.max_width = 2048; |
| 16362 | dev->mode_config.max_height = 2048; |
| 16363 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 16364 | dev->mode_config.max_width = 4096; |
| 16365 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16366 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 16367 | dev->mode_config.max_width = 8192; |
| 16368 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16369 | } |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 16370 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 16371 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 16372 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; |
| 16373 | dev->mode_config.cursor_height = 1023; |
| 16374 | } else if (IS_GEN2(dev)) { |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 16375 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
| 16376 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; |
| 16377 | } else { |
| 16378 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; |
| 16379 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; |
| 16380 | } |
| 16381 | |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 16382 | dev->mode_config.fb_base = ggtt->mappable_base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16383 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 16384 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 16385 | INTEL_INFO(dev)->num_pipes, |
| 16386 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16387 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 16388 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 16389 | intel_crtc_init(dev, pipe); |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 16390 | for_each_sprite(dev_priv, pipe, sprite) { |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 16391 | ret = intel_plane_init(dev, pipe, sprite); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 16392 | if (ret) |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 16393 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 16394 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 16395 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16396 | } |
| 16397 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 16398 | intel_update_czclk(dev_priv); |
| 16399 | intel_update_cdclk(dev); |
| 16400 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 16401 | intel_shared_dpll_init(dev); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 16402 | |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 16403 | if (dev_priv->max_cdclk_freq == 0) |
| 16404 | intel_update_max_cdclk(dev); |
| 16405 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 16406 | /* Just disable it once at startup */ |
| 16407 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16408 | intel_setup_outputs(dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 16409 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 16410 | drm_modeset_lock_all(dev); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16411 | intel_modeset_setup_hw_state(dev); |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 16412 | drm_modeset_unlock_all(dev); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 16413 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 16414 | for_each_intel_crtc(dev, crtc) { |
Maarten Lankhorst | eeebeac | 2015-07-14 12:33:29 +0200 | [diff] [blame] | 16415 | struct intel_initial_plane_config plane_config = {}; |
| 16416 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 16417 | if (!crtc->active) |
| 16418 | continue; |
| 16419 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 16420 | /* |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 16421 | * Note that reserving the BIOS fb up front prevents us |
| 16422 | * from stuffing other stolen allocations like the ring |
| 16423 | * on top. This prevents some ugliness at boot time, and |
| 16424 | * can even allow for smooth boot transitions if the BIOS |
| 16425 | * fb is large enough for the active pipe configuration. |
| 16426 | */ |
Maarten Lankhorst | eeebeac | 2015-07-14 12:33:29 +0200 | [diff] [blame] | 16427 | dev_priv->display.get_initial_plane_config(crtc, |
| 16428 | &plane_config); |
| 16429 | |
| 16430 | /* |
| 16431 | * If the fb is shared between multiple heads, we'll |
| 16432 | * just get the first one. |
| 16433 | */ |
| 16434 | intel_find_initial_plane_obj(crtc, &plane_config); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 16435 | } |
Matt Roper | d93c037 | 2015-12-03 11:37:41 -0800 | [diff] [blame] | 16436 | |
| 16437 | /* |
| 16438 | * Make sure hardware watermarks really match the state we read out. |
| 16439 | * Note that we need to do this after reconstructing the BIOS fb's |
| 16440 | * since the watermark calculation done here will use pstate->fb. |
| 16441 | */ |
| 16442 | sanitize_watermarks(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 16443 | } |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 16444 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 16445 | static void intel_enable_pipe_a(struct drm_device *dev) |
| 16446 | { |
| 16447 | struct intel_connector *connector; |
| 16448 | struct drm_connector *crt = NULL; |
| 16449 | struct intel_load_detect_pipe load_detect_temp; |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 16450 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 16451 | |
| 16452 | /* We can't just switch on the pipe A, we need to set things up with a |
| 16453 | * proper mode and output configuration. As a gross hack, enable pipe A |
| 16454 | * by enabling the load detect pipe once. */ |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 16455 | for_each_intel_connector(dev, connector) { |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 16456 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
| 16457 | crt = &connector->base; |
| 16458 | break; |
| 16459 | } |
| 16460 | } |
| 16461 | |
| 16462 | if (!crt) |
| 16463 | return; |
| 16464 | |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 16465 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
Ander Conselvan de Oliveira | 49172fe | 2015-03-20 16:18:02 +0200 | [diff] [blame] | 16466 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 16467 | } |
| 16468 | |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 16469 | static bool |
| 16470 | intel_check_plane_mapping(struct intel_crtc *crtc) |
| 16471 | { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 16472 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16473 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 16474 | u32 val; |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 16475 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 16476 | if (INTEL_INFO(dev)->num_pipes == 1) |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 16477 | return true; |
| 16478 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 16479 | val = I915_READ(DSPCNTR(!crtc->plane)); |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 16480 | |
| 16481 | if ((val & DISPLAY_PLANE_ENABLE) && |
| 16482 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
| 16483 | return false; |
| 16484 | |
| 16485 | return true; |
| 16486 | } |
| 16487 | |
Ville Syrjälä | 02e93c3 | 2015-08-26 19:39:19 +0300 | [diff] [blame] | 16488 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
| 16489 | { |
| 16490 | struct drm_device *dev = crtc->base.dev; |
| 16491 | struct intel_encoder *encoder; |
| 16492 | |
| 16493 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
| 16494 | return true; |
| 16495 | |
| 16496 | return false; |
| 16497 | } |
| 16498 | |
Maarten Lankhorst | 496b0fc | 2016-08-23 16:18:07 +0200 | [diff] [blame] | 16499 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
Ville Syrjälä | dd75619 | 2016-02-17 21:28:45 +0200 | [diff] [blame] | 16500 | { |
| 16501 | struct drm_device *dev = encoder->base.dev; |
| 16502 | struct intel_connector *connector; |
| 16503 | |
| 16504 | for_each_connector_on_encoder(dev, &encoder->base, connector) |
Maarten Lankhorst | 496b0fc | 2016-08-23 16:18:07 +0200 | [diff] [blame] | 16505 | return connector; |
Ville Syrjälä | dd75619 | 2016-02-17 21:28:45 +0200 | [diff] [blame] | 16506 | |
Maarten Lankhorst | 496b0fc | 2016-08-23 16:18:07 +0200 | [diff] [blame] | 16507 | return NULL; |
Ville Syrjälä | dd75619 | 2016-02-17 21:28:45 +0200 | [diff] [blame] | 16508 | } |
| 16509 | |
Ville Syrjälä | a168f5b | 2016-08-05 20:00:17 +0300 | [diff] [blame] | 16510 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
| 16511 | enum transcoder pch_transcoder) |
| 16512 | { |
| 16513 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || |
| 16514 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); |
| 16515 | } |
| 16516 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16517 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
| 16518 | { |
| 16519 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16520 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 16521 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16522 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16523 | /* Clear any frame start delays used for debugging left by the BIOS */ |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 16524 | if (!transcoder_is_dsi(cpu_transcoder)) { |
| 16525 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
| 16526 | |
| 16527 | I915_WRITE(reg, |
| 16528 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 16529 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16530 | |
Ville Syrjälä | d3eaf88 | 2014-05-20 17:20:05 +0300 | [diff] [blame] | 16531 | /* restore vblank interrupts to correct state */ |
Daniel Vetter | 9625604 | 2015-02-13 21:03:42 +0100 | [diff] [blame] | 16532 | drm_crtc_vblank_reset(&crtc->base); |
Ville Syrjälä | d297e10 | 2014-08-06 14:50:01 +0300 | [diff] [blame] | 16533 | if (crtc->active) { |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16534 | struct intel_plane *plane; |
| 16535 | |
Daniel Vetter | 9625604 | 2015-02-13 21:03:42 +0100 | [diff] [blame] | 16536 | drm_crtc_vblank_on(&crtc->base); |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16537 | |
| 16538 | /* Disable everything but the primary plane */ |
| 16539 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 16540 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
| 16541 | continue; |
| 16542 | |
| 16543 | plane->disable_plane(&plane->base, &crtc->base); |
| 16544 | } |
Daniel Vetter | 9625604 | 2015-02-13 21:03:42 +0100 | [diff] [blame] | 16545 | } |
Ville Syrjälä | d3eaf88 | 2014-05-20 17:20:05 +0300 | [diff] [blame] | 16546 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16547 | /* We need to sanitize the plane -> pipe mapping first because this will |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 16548 | * disable the crtc (and hence change the state) if it is wrong. Note |
| 16549 | * that gen4+ has a fixed plane -> pipe mapping. */ |
| 16550 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16551 | bool plane; |
| 16552 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 16553 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
| 16554 | crtc->base.base.id, crtc->base.name); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16555 | |
| 16556 | /* Pipe has the wrong plane attached and the plane is active. |
| 16557 | * Temporarily change the plane mapping and disable everything |
| 16558 | * ... */ |
| 16559 | plane = crtc->plane; |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 16560 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16561 | crtc->plane = !plane; |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 16562 | intel_crtc_disable_noatomic(&crtc->base); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16563 | crtc->plane = plane; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16564 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16565 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 16566 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 16567 | crtc->pipe == PIPE_A && !crtc->active) { |
| 16568 | /* BIOS forgot to enable pipe A, this mostly happens after |
| 16569 | * resume. Force-enable the pipe to fix this, the update_dpms |
| 16570 | * call below we restore the pipe to the right state, but leave |
| 16571 | * the required bits on. */ |
| 16572 | intel_enable_pipe_a(dev); |
| 16573 | } |
| 16574 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16575 | /* Adjust the state of the output pipe according to whether we |
| 16576 | * have active connectors/encoders. */ |
Maarten Lankhorst | 842e030 | 2016-03-02 15:48:01 +0100 | [diff] [blame] | 16577 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 16578 | intel_crtc_disable_noatomic(&crtc->base); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16579 | |
Ville Syrjälä | a3ed6aa | 2014-09-03 14:09:52 +0300 | [diff] [blame] | 16580 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 16581 | /* |
| 16582 | * We start out with underrun reporting disabled to avoid races. |
| 16583 | * For correct bookkeeping mark this on active crtcs. |
| 16584 | * |
Daniel Vetter | c5ab3bc | 2014-05-14 15:40:34 +0200 | [diff] [blame] | 16585 | * Also on gmch platforms we dont have any hardware bits to |
| 16586 | * disable the underrun reporting. Which means we need to start |
| 16587 | * out with underrun reporting disabled also on inactive pipes, |
| 16588 | * since otherwise we'll complain about the garbage we read when |
| 16589 | * e.g. coming up after runtime pm. |
| 16590 | * |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 16591 | * No protection against concurrent access is required - at |
| 16592 | * worst a fifo underrun happens which also sets this to false. |
| 16593 | */ |
| 16594 | crtc->cpu_fifo_underrun_disabled = true; |
Ville Syrjälä | a168f5b | 2016-08-05 20:00:17 +0300 | [diff] [blame] | 16595 | /* |
| 16596 | * We track the PCH trancoder underrun reporting state |
| 16597 | * within the crtc. With crtc for pipe A housing the underrun |
| 16598 | * reporting state for PCH transcoder A, crtc for pipe B housing |
| 16599 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, |
| 16600 | * and marking underrun reporting as disabled for the non-existing |
| 16601 | * PCH transcoders B and C would prevent enabling the south |
| 16602 | * error interrupt (see cpt_can_enable_serr_int()). |
| 16603 | */ |
| 16604 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) |
| 16605 | crtc->pch_fifo_underrun_disabled = true; |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 16606 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16607 | } |
| 16608 | |
| 16609 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
| 16610 | { |
| 16611 | struct intel_connector *connector; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16612 | |
| 16613 | /* We need to check both for a crtc link (meaning that the |
| 16614 | * encoder is active and trying to read from a pipe) and the |
| 16615 | * pipe itself being active. */ |
| 16616 | bool has_active_crtc = encoder->base.crtc && |
| 16617 | to_intel_crtc(encoder->base.crtc)->active; |
| 16618 | |
Maarten Lankhorst | 496b0fc | 2016-08-23 16:18:07 +0200 | [diff] [blame] | 16619 | connector = intel_encoder_find_connector(encoder); |
| 16620 | if (connector && !has_active_crtc) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16621 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
| 16622 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 16623 | encoder->base.name); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16624 | |
| 16625 | /* Connector is active, but has no active pipe. This is |
| 16626 | * fallout from our resume register restoring. Disable |
| 16627 | * the encoder manually again. */ |
| 16628 | if (encoder->base.crtc) { |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 16629 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
| 16630 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16631 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
| 16632 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 16633 | encoder->base.name); |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 16634 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
Ville Syrjälä | a62d149 | 2014-06-28 02:04:01 +0300 | [diff] [blame] | 16635 | if (encoder->post_disable) |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 16636 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16637 | } |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 16638 | encoder->base.crtc = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16639 | |
| 16640 | /* Inconsistent output/port/pipe state happens presumably due to |
| 16641 | * a bug in one of the get_hw_state functions. Or someplace else |
| 16642 | * in our code, like the register restore mess on resume. Clamp |
| 16643 | * things to off as a safer default. */ |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 16644 | |
| 16645 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 16646 | connector->base.encoder = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16647 | } |
| 16648 | /* Enabled encoders without active connectors will be fixed in |
| 16649 | * the crtc fixup. */ |
| 16650 | } |
| 16651 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 16652 | void i915_redisable_vga_power_on(struct drm_device *dev) |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 16653 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16654 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 16655 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 16656 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 16657 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
| 16658 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
| 16659 | i915_disable_vga(dev); |
| 16660 | } |
| 16661 | } |
| 16662 | |
| 16663 | void i915_redisable_vga(struct drm_device *dev) |
| 16664 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16665 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 16666 | |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 16667 | /* This function can be called both from intel_modeset_setup_hw_state or |
| 16668 | * at a very early point in our resume sequence, where the power well |
| 16669 | * structures are not yet restored. Since this function is at a very |
| 16670 | * paranoid "someone might have enabled VGA while we were not looking" |
| 16671 | * level, just check if the power well is enabled instead of trying to |
| 16672 | * follow the "don't touch the power well if we don't need it" policy |
| 16673 | * the rest of the driver uses. */ |
Imre Deak | 6392f84 | 2016-02-12 18:55:13 +0200 | [diff] [blame] | 16674 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 16675 | return; |
| 16676 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 16677 | i915_redisable_vga_power_on(dev); |
Imre Deak | 6392f84 | 2016-02-12 18:55:13 +0200 | [diff] [blame] | 16678 | |
| 16679 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 16680 | } |
| 16681 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16682 | static bool primary_get_hw_state(struct intel_plane *plane) |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 16683 | { |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16684 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 16685 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16686 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 16687 | } |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 16688 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16689 | /* FIXME read out full plane state for all planes */ |
| 16690 | static void readout_plane_state(struct intel_crtc *crtc) |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 16691 | { |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 16692 | struct drm_plane *primary = crtc->base.primary; |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16693 | struct intel_plane_state *plane_state = |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 16694 | to_intel_plane_state(primary->state); |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 16695 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 16696 | plane_state->base.visible = crtc->active && |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 16697 | primary_get_hw_state(to_intel_plane(primary)); |
| 16698 | |
Ville Syrjälä | 936e71e | 2016-07-26 19:06:59 +0300 | [diff] [blame] | 16699 | if (plane_state->base.visible) |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 16700 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 16701 | } |
| 16702 | |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 16703 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16704 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16705 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16706 | enum pipe pipe; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16707 | struct intel_crtc *crtc; |
| 16708 | struct intel_encoder *encoder; |
| 16709 | struct intel_connector *connector; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 16710 | int i; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16711 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16712 | dev_priv->active_crtcs = 0; |
| 16713 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 16714 | for_each_intel_crtc(dev, crtc) { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16715 | struct intel_crtc_state *crtc_state = crtc->config; |
| 16716 | int pixclk = 0; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 16717 | |
Daniel Vetter | ec2dc6a | 2016-05-09 16:34:09 +0200 | [diff] [blame] | 16718 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16719 | memset(crtc_state, 0, sizeof(*crtc_state)); |
| 16720 | crtc_state->base.crtc = &crtc->base; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16721 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16722 | crtc_state->base.active = crtc_state->base.enable = |
| 16723 | dev_priv->display.get_pipe_config(crtc, crtc_state); |
| 16724 | |
| 16725 | crtc->base.enabled = crtc_state->base.enable; |
| 16726 | crtc->active = crtc_state->base.active; |
| 16727 | |
| 16728 | if (crtc_state->base.active) { |
| 16729 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
| 16730 | |
Clint Taylor | c89e39f | 2016-05-13 23:41:21 +0300 | [diff] [blame] | 16731 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16732 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
Ville Syrjälä | 9558d15 | 2016-05-13 23:41:20 +0300 | [diff] [blame] | 16733 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16734 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
| 16735 | else |
| 16736 | WARN_ON(dev_priv->display.modeset_calc_cdclk); |
Ville Syrjälä | 9558d15 | 2016-05-13 23:41:20 +0300 | [diff] [blame] | 16737 | |
| 16738 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
| 16739 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
| 16740 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 16741 | } |
| 16742 | |
| 16743 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 16744 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 16745 | readout_plane_state(crtc); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16746 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 16747 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
| 16748 | crtc->base.base.id, crtc->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16749 | crtc->active ? "enabled" : "disabled"); |
| 16750 | } |
| 16751 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 16752 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 16753 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 16754 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 16755 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
| 16756 | &pll->config.hw_state); |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 16757 | pll->config.crtc_mask = 0; |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 16758 | for_each_intel_crtc(dev, crtc) { |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 16759 | if (crtc->active && crtc->config->shared_dpll == pll) |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 16760 | pll->config.crtc_mask |= 1 << crtc->pipe; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 16761 | } |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 16762 | pll->active_mask = pll->config.crtc_mask; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 16763 | |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 16764 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 16765 | pll->name, pll->config.crtc_mask, pll->on); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 16766 | } |
| 16767 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 16768 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16769 | pipe = 0; |
| 16770 | |
| 16771 | if (encoder->get_hw_state(encoder, &pipe)) { |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 16772 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 16773 | encoder->base.crtc = &crtc->base; |
Ville Syrjälä | 253c84c | 2016-06-22 21:57:01 +0300 | [diff] [blame] | 16774 | crtc->config->output_types |= 1 << encoder->type; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 16775 | encoder->get_config(encoder, crtc->config); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16776 | } else { |
| 16777 | encoder->base.crtc = NULL; |
| 16778 | } |
| 16779 | |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 16780 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16781 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 16782 | encoder->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16783 | encoder->base.crtc ? "enabled" : "disabled", |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 16784 | pipe_name(pipe)); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16785 | } |
| 16786 | |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 16787 | for_each_intel_connector(dev, connector) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16788 | if (connector->get_hw_state(connector)) { |
| 16789 | connector->base.dpms = DRM_MODE_DPMS_ON; |
Maarten Lankhorst | 2aa974c | 2016-01-06 14:53:25 +0100 | [diff] [blame] | 16790 | |
| 16791 | encoder = connector->encoder; |
| 16792 | connector->base.encoder = &encoder->base; |
| 16793 | |
| 16794 | if (encoder->base.crtc && |
| 16795 | encoder->base.crtc->state->active) { |
| 16796 | /* |
| 16797 | * This has to be done during hardware readout |
| 16798 | * because anything calling .crtc_disable may |
| 16799 | * rely on the connector_mask being accurate. |
| 16800 | */ |
| 16801 | encoder->base.crtc->state->connector_mask |= |
| 16802 | 1 << drm_connector_index(&connector->base); |
Maarten Lankhorst | e87a52b | 2016-01-28 15:04:58 +0100 | [diff] [blame] | 16803 | encoder->base.crtc->state->encoder_mask |= |
| 16804 | 1 << drm_encoder_index(&encoder->base); |
Maarten Lankhorst | 2aa974c | 2016-01-06 14:53:25 +0100 | [diff] [blame] | 16805 | } |
| 16806 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16807 | } else { |
| 16808 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 16809 | connector->base.encoder = NULL; |
| 16810 | } |
| 16811 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
| 16812 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 16813 | connector->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16814 | connector->base.encoder ? "enabled" : "disabled"); |
| 16815 | } |
Ville Syrjälä | 7f4c628 | 2015-09-10 18:59:07 +0300 | [diff] [blame] | 16816 | |
| 16817 | for_each_intel_crtc(dev, crtc) { |
| 16818 | crtc->base.hwmode = crtc->config->base.adjusted_mode; |
| 16819 | |
| 16820 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
| 16821 | if (crtc->base.state->active) { |
| 16822 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); |
| 16823 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); |
| 16824 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
| 16825 | |
| 16826 | /* |
| 16827 | * The initial mode needs to be set in order to keep |
| 16828 | * the atomic core happy. It wants a valid mode if the |
| 16829 | * crtc's enabled, so we do the above call. |
| 16830 | * |
| 16831 | * At this point some state updated by the connectors |
| 16832 | * in their ->detect() callback has not run yet, so |
| 16833 | * no recalculation can be done yet. |
| 16834 | * |
| 16835 | * Even if we could do a recalculation and modeset |
| 16836 | * right now it would cause a double modeset if |
| 16837 | * fbdev or userspace chooses a different initial mode. |
| 16838 | * |
| 16839 | * If that happens, someone indicated they wanted a |
| 16840 | * mode change, which means it's safe to do a full |
| 16841 | * recalculation. |
| 16842 | */ |
| 16843 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; |
Ville Syrjälä | 9eca6832 | 2015-09-10 18:59:10 +0300 | [diff] [blame] | 16844 | |
| 16845 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
| 16846 | update_scanline_offset(crtc); |
Ville Syrjälä | 7f4c628 | 2015-09-10 18:59:07 +0300 | [diff] [blame] | 16847 | } |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 16848 | |
| 16849 | intel_pipe_config_sanity_check(dev_priv, crtc->config); |
Ville Syrjälä | 7f4c628 | 2015-09-10 18:59:07 +0300 | [diff] [blame] | 16850 | } |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 16851 | } |
| 16852 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16853 | /* Scan out the current hw modeset state, |
| 16854 | * and sanitizes it to the current state |
| 16855 | */ |
| 16856 | static void |
| 16857 | intel_modeset_setup_hw_state(struct drm_device *dev) |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 16858 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 16859 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 16860 | enum pipe pipe; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 16861 | struct intel_crtc *crtc; |
| 16862 | struct intel_encoder *encoder; |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 16863 | int i; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 16864 | |
| 16865 | intel_modeset_readout_hw_state(dev); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16866 | |
| 16867 | /* HW state is read out, now we need to sanitize this mess. */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 16868 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16869 | intel_sanitize_encoder(encoder); |
| 16870 | } |
| 16871 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 16872 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16873 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 16874 | intel_sanitize_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 16875 | intel_dump_pipe_config(crtc, crtc->config, |
| 16876 | "[setup_hw_state]"); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 16877 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 16878 | |
Ander Conselvan de Oliveira | d29b2f9 | 2015-03-20 16:18:05 +0200 | [diff] [blame] | 16879 | intel_modeset_update_connector_atomic_state(dev); |
| 16880 | |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 16881 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 16882 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 16883 | |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 16884 | if (!pll->on || pll->active_mask) |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 16885 | continue; |
| 16886 | |
| 16887 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
| 16888 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 16889 | pll->funcs.disable(dev_priv, pll); |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 16890 | pll->on = false; |
| 16891 | } |
| 16892 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 16893 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 16894 | vlv_wm_get_hw_state(dev); |
| 16895 | else if (IS_GEN9(dev)) |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 16896 | skl_wm_get_hw_state(dev); |
| 16897 | else if (HAS_PCH_SPLIT(dev)) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 16898 | ilk_wm_get_hw_state(dev); |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 16899 | |
| 16900 | for_each_intel_crtc(dev, crtc) { |
| 16901 | unsigned long put_domains; |
| 16902 | |
Maarten Lankhorst | 74bff5f | 2016-02-10 13:49:36 +0100 | [diff] [blame] | 16903 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 16904 | if (WARN_ON(put_domains)) |
| 16905 | modeset_put_power_domains(dev_priv, put_domains); |
| 16906 | } |
| 16907 | intel_display_set_init_power(dev_priv, false); |
Paulo Zanoni | 010cf73 | 2016-01-19 11:35:48 -0200 | [diff] [blame] | 16908 | |
| 16909 | intel_fbc_init_pipe_state(dev_priv); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16910 | } |
Ville Syrjälä | 7d0bc1e | 2013-09-16 17:38:33 +0300 | [diff] [blame] | 16911 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16912 | void intel_display_resume(struct drm_device *dev) |
| 16913 | { |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 16914 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 16915 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; |
| 16916 | struct drm_modeset_acquire_ctx ctx; |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16917 | int ret; |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 16918 | |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 16919 | dev_priv->modeset_restore_state = NULL; |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 16920 | if (state) |
| 16921 | state->acquire_ctx = &ctx; |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16922 | |
Maarten Lankhorst | ea49c9a | 2016-02-16 15:27:42 +0100 | [diff] [blame] | 16923 | /* |
| 16924 | * This is a cludge because with real atomic modeset mode_config.mutex |
| 16925 | * won't be taken. Unfortunately some probed state like |
| 16926 | * audio_codec_enable is still protected by mode_config.mutex, so lock |
| 16927 | * it here for now. |
| 16928 | */ |
| 16929 | mutex_lock(&dev->mode_config.mutex); |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 16930 | drm_modeset_acquire_init(&ctx, 0); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16931 | |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 16932 | while (1) { |
| 16933 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
| 16934 | if (ret != -EDEADLK) |
| 16935 | break; |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16936 | |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 16937 | drm_modeset_backoff(&ctx); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16938 | } |
| 16939 | |
Maarten Lankhorst | 7397489 | 2016-08-05 23:28:27 +0300 | [diff] [blame] | 16940 | if (!ret) |
| 16941 | ret = __intel_display_resume(dev, state); |
| 16942 | |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 16943 | drm_modeset_drop_locks(&ctx); |
| 16944 | drm_modeset_acquire_fini(&ctx); |
Maarten Lankhorst | ea49c9a | 2016-02-16 15:27:42 +0100 | [diff] [blame] | 16945 | mutex_unlock(&dev->mode_config.mutex); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 16946 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 16947 | if (ret) |
Maarten Lankhorst | e2c8b87 | 2016-02-16 10:06:14 +0100 | [diff] [blame] | 16948 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 16949 | drm_atomic_state_put(state); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 16950 | } |
| 16951 | |
| 16952 | void intel_modeset_gem_init(struct drm_device *dev) |
| 16953 | { |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 16954 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 16955 | struct drm_crtc *c; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 16956 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 16957 | |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 16958 | intel_init_gt_powersave(dev_priv); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 16959 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 16960 | intel_modeset_init_hw(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 16961 | |
Chris Wilson | 1ee8da6 | 2016-05-12 12:43:23 +0100 | [diff] [blame] | 16962 | intel_setup_overlay(dev_priv); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 16963 | |
| 16964 | /* |
| 16965 | * Make sure any fbs we allocated at startup are properly |
| 16966 | * pinned & fenced. When we do the allocation it's too early |
| 16967 | * for this. |
| 16968 | */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 16969 | for_each_crtc(dev, c) { |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 16970 | struct i915_vma *vma; |
| 16971 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 16972 | obj = intel_fb_obj(c->primary->fb); |
| 16973 | if (obj == NULL) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 16974 | continue; |
| 16975 | |
Tvrtko Ursulin | e0d6149 | 2015-04-13 16:03:03 +0100 | [diff] [blame] | 16976 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 16977 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
Ville Syrjälä | 3465c58 | 2016-02-15 22:54:43 +0200 | [diff] [blame] | 16978 | c->primary->state->rotation); |
Tvrtko Ursulin | e0d6149 | 2015-04-13 16:03:03 +0100 | [diff] [blame] | 16979 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 058d88c | 2016-08-15 10:49:06 +0100 | [diff] [blame] | 16980 | if (IS_ERR(vma)) { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 16981 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
| 16982 | to_intel_crtc(c)->pipe); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 16983 | drm_framebuffer_unreference(c->primary->fb); |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 16984 | c->primary->fb = NULL; |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 16985 | c->primary->crtc = c->primary->state->crtc = NULL; |
Daniel Vetter | 5a21b66 | 2016-05-24 17:13:53 +0200 | [diff] [blame] | 16986 | update_state_fb(c->primary); |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 16987 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 16988 | } |
| 16989 | } |
Chris Wilson | 1ebaa0b | 2016-06-24 14:00:15 +0100 | [diff] [blame] | 16990 | } |
Ville Syrjälä | 0962c3c | 2014-11-07 15:19:46 +0200 | [diff] [blame] | 16991 | |
Chris Wilson | 1ebaa0b | 2016-06-24 14:00:15 +0100 | [diff] [blame] | 16992 | int intel_connector_register(struct drm_connector *connector) |
| 16993 | { |
| 16994 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 16995 | int ret; |
| 16996 | |
| 16997 | ret = intel_backlight_device_register(intel_connector); |
| 16998 | if (ret) |
| 16999 | goto err; |
| 17000 | |
| 17001 | return 0; |
| 17002 | |
| 17003 | err: |
| 17004 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 17005 | } |
| 17006 | |
Chris Wilson | c191eca | 2016-06-17 11:40:33 +0100 | [diff] [blame] | 17007 | void intel_connector_unregister(struct drm_connector *connector) |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 17008 | { |
Chris Wilson | e63d87c | 2016-06-17 11:40:34 +0100 | [diff] [blame] | 17009 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 17010 | |
Chris Wilson | e63d87c | 2016-06-17 11:40:34 +0100 | [diff] [blame] | 17011 | intel_backlight_device_unregister(intel_connector); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 17012 | intel_panel_destroy_backlight(connector); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 17013 | } |
| 17014 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 17015 | void intel_modeset_cleanup(struct drm_device *dev) |
| 17016 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 17017 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 17018 | |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 17019 | intel_disable_gt_powersave(dev_priv); |
Imre Deak | 2eb5252 | 2014-11-19 15:30:05 +0200 | [diff] [blame] | 17020 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 17021 | /* |
| 17022 | * Interrupts and polling as the first thing to avoid creating havoc. |
Imre Deak | 2eb5252 | 2014-11-19 15:30:05 +0200 | [diff] [blame] | 17023 | * Too much stuff here (turning of connectors, ...) would |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 17024 | * experience fancy races otherwise. |
| 17025 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 17026 | intel_irq_uninstall(dev_priv); |
Jesse Barnes | eb21b92 | 2014-06-20 11:57:33 -0700 | [diff] [blame] | 17027 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 17028 | /* |
| 17029 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
| 17030 | * poll handlers. Hence disable polling after hpd handling is shut down. |
| 17031 | */ |
Keith Packard | f87ea76 | 2010-10-03 19:36:26 -0700 | [diff] [blame] | 17032 | drm_kms_helper_poll_fini(dev); |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 17033 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 17034 | intel_unregister_dsm_handler(); |
| 17035 | |
Paulo Zanoni | c937ab3e5 | 2016-01-19 11:35:46 -0200 | [diff] [blame] | 17036 | intel_fbc_global_disable(dev_priv); |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 17037 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 17038 | /* flush any delayed tasks or pending work */ |
| 17039 | flush_scheduled_work(); |
| 17040 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 17041 | drm_mode_config_cleanup(dev); |
Daniel Vetter | 4d7bb01 | 2012-12-18 15:24:37 +0100 | [diff] [blame] | 17042 | |
Chris Wilson | 1ee8da6 | 2016-05-12 12:43:23 +0100 | [diff] [blame] | 17043 | intel_cleanup_overlay(dev_priv); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 17044 | |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 17045 | intel_cleanup_gt_powersave(dev_priv); |
Daniel Vetter | f594914 | 2016-01-13 11:55:28 +0100 | [diff] [blame] | 17046 | |
| 17047 | intel_teardown_gmbus(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 17048 | } |
| 17049 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 17050 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 17051 | struct intel_encoder *encoder) |
| 17052 | { |
| 17053 | connector->encoder = encoder; |
| 17054 | drm_mode_connector_attach_encoder(&connector->base, |
| 17055 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 17056 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 17057 | |
| 17058 | /* |
| 17059 | * set vga decode state - true == enable VGA decode |
| 17060 | */ |
| 17061 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 17062 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 17063 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | a885b3c | 2013-12-17 14:34:50 +0000 | [diff] [blame] | 17064 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 17065 | u16 gmch_ctrl; |
| 17066 | |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 17067 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
| 17068 | DRM_ERROR("failed to read control word\n"); |
| 17069 | return -EIO; |
| 17070 | } |
| 17071 | |
Chris Wilson | c0cc8a5 | 2014-02-07 18:37:03 -0200 | [diff] [blame] | 17072 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
| 17073 | return 0; |
| 17074 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 17075 | if (state) |
| 17076 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 17077 | else |
| 17078 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 17079 | |
| 17080 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
| 17081 | DRM_ERROR("failed to write control word\n"); |
| 17082 | return -EIO; |
| 17083 | } |
| 17084 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 17085 | return 0; |
| 17086 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17087 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17088 | struct intel_display_error_state { |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 17089 | |
| 17090 | u32 power_well_driver; |
| 17091 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17092 | int num_transcoders; |
| 17093 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17094 | struct intel_cursor_error_state { |
| 17095 | u32 control; |
| 17096 | u32 position; |
| 17097 | u32 base; |
| 17098 | u32 size; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 17099 | } cursor[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17100 | |
| 17101 | struct intel_pipe_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17102 | bool power_domain_on; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17103 | u32 source; |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 17104 | u32 stat; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 17105 | } pipe[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17106 | |
| 17107 | struct intel_plane_error_state { |
| 17108 | u32 control; |
| 17109 | u32 stride; |
| 17110 | u32 size; |
| 17111 | u32 pos; |
| 17112 | u32 addr; |
| 17113 | u32 surface; |
| 17114 | u32 tile_offset; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 17115 | } plane[I915_MAX_PIPES]; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17116 | |
| 17117 | struct intel_transcoder_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17118 | bool power_domain_on; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17119 | enum transcoder cpu_transcoder; |
| 17120 | |
| 17121 | u32 conf; |
| 17122 | |
| 17123 | u32 htotal; |
| 17124 | u32 hblank; |
| 17125 | u32 hsync; |
| 17126 | u32 vtotal; |
| 17127 | u32 vblank; |
| 17128 | u32 vsync; |
| 17129 | } transcoder[4]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17130 | }; |
| 17131 | |
| 17132 | struct intel_display_error_state * |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17133 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17134 | { |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17135 | struct intel_display_error_state *error; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17136 | int transcoders[] = { |
| 17137 | TRANSCODER_A, |
| 17138 | TRANSCODER_B, |
| 17139 | TRANSCODER_C, |
| 17140 | TRANSCODER_EDP, |
| 17141 | }; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17142 | int i; |
| 17143 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17144 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17145 | return NULL; |
| 17146 | |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 17147 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17148 | if (error == NULL) |
| 17149 | return NULL; |
| 17150 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17151 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 17152 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
| 17153 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 17154 | for_each_pipe(dev_priv, i) { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17155 | error->pipe[i].power_domain_on = |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 17156 | __intel_display_power_is_enabled(dev_priv, |
| 17157 | POWER_DOMAIN_PIPE(i)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17158 | if (!error->pipe[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 17159 | continue; |
| 17160 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 17161 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 17162 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 17163 | error->cursor[i].base = I915_READ(CURBASE(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17164 | |
| 17165 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 17166 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17167 | if (INTEL_GEN(dev_priv) <= 3) { |
Paulo Zanoni | 51889b3 | 2013-03-06 20:03:13 -0300 | [diff] [blame] | 17168 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 17169 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
| 17170 | } |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17171 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
Paulo Zanoni | ca29136 | 2013-03-06 20:03:14 -0300 | [diff] [blame] | 17172 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17173 | if (INTEL_GEN(dev_priv) >= 4) { |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17174 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 17175 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 17176 | } |
| 17177 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17178 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 17179 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17180 | if (HAS_GMCH_DISPLAY(dev_priv)) |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 17181 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17182 | } |
| 17183 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 17184 | /* Note: this does not include DSI transcoders. */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 17185 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 17186 | if (HAS_DDI(dev_priv)) |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17187 | error->num_transcoders++; /* Account for eDP. */ |
| 17188 | |
| 17189 | for (i = 0; i < error->num_transcoders; i++) { |
| 17190 | enum transcoder cpu_transcoder = transcoders[i]; |
| 17191 | |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17192 | error->transcoder[i].power_domain_on = |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 17193 | __intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 38cc1da | 2013-12-20 15:09:41 -0200 | [diff] [blame] | 17194 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17195 | if (!error->transcoder[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 17196 | continue; |
| 17197 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17198 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 17199 | |
| 17200 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
| 17201 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
| 17202 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
| 17203 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 17204 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
| 17205 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
| 17206 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17207 | } |
| 17208 | |
| 17209 | return error; |
| 17210 | } |
| 17211 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17212 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 17213 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17214 | void |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17215 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17216 | struct drm_device *dev, |
| 17217 | struct intel_display_error_state *error) |
| 17218 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 17219 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17220 | int i; |
| 17221 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17222 | if (!error) |
| 17223 | return; |
| 17224 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17225 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 17226 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17227 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 17228 | error->power_well_driver); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 17229 | for_each_pipe(dev_priv, i) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17230 | err_printf(m, "Pipe [%d]:\n", i); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17231 | err_printf(m, " Power: %s\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 17232 | onoff(error->pipe[i].power_domain_on)); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17233 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 17234 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17235 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17236 | err_printf(m, "Plane [%d]:\n", i); |
| 17237 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 17238 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 17239 | if (INTEL_INFO(dev)->gen <= 3) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17240 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 17241 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 17242 | } |
Paulo Zanoni | 4b71a57 | 2013-03-22 14:19:21 -0300 | [diff] [blame] | 17243 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17244 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17245 | if (INTEL_INFO(dev)->gen >= 4) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17246 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 17247 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17248 | } |
| 17249 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 17250 | err_printf(m, "Cursor [%d]:\n", i); |
| 17251 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 17252 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 17253 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17254 | } |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17255 | |
| 17256 | for (i = 0; i < error->num_transcoders; i++) { |
Jani Nikula | da20563 | 2016-03-15 21:51:10 +0200 | [diff] [blame] | 17257 | err_printf(m, "CPU transcoder: %s\n", |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17258 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 17259 | err_printf(m, " Power: %s\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 17260 | onoff(error->transcoder[i].power_domain_on)); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 17261 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
| 17262 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
| 17263 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
| 17264 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
| 17265 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
| 17266 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
| 17267 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
| 17268 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 17269 | } |