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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Chon Ming Leeef9348c2014-04-09 13:28:18 +030044#define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
Daniel Vetter3dec0092010-08-20 21:40:52 +020047static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010048static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080049
Jesse Barnesf1f644d2013-06-27 00:39:25 +030050static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030052static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030054
Damien Lespiaue7457a92013-08-08 22:28:59 +010055static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080057static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020061static void intel_dp_set_m_n(struct intel_crtc *crtc);
62static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020064static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65 struct intel_link_m_n *m_n);
66static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020067static void haswell_set_pipeconf(struct drm_crtc *crtc);
68static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +020069static void vlv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +010070
Jesse Barnes79e53942008-11-07 14:24:08 -080071typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040072 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080073} intel_range_t;
74
75typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040076 int dot_limit;
77 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080078} intel_p2_t;
79
Ma Lingd4906092009-03-18 20:13:27 +080080typedef struct intel_limit intel_limit_t;
81struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040082 intel_range_t dot, vco, n, m, m1, m2, p, p1;
83 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080084};
Jesse Barnes79e53942008-11-07 14:24:08 -080085
Daniel Vetterd2acd212012-10-20 20:57:43 +020086int
87intel_pch_rawclk(struct drm_device *dev)
88{
89 struct drm_i915_private *dev_priv = dev->dev_private;
90
91 WARN_ON(!HAS_PCH_SPLIT(dev));
92
93 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94}
95
Chris Wilson021357a2010-09-07 20:54:59 +010096static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
Chris Wilson8b99e682010-10-13 09:59:17 +010099 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100104}
105
Daniel Vetter5d536e22013-07-06 12:52:06 +0200106static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400107 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200108 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200109 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700117};
118
Daniel Vetter5d536e22013-07-06 12:52:06 +0200119static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200121 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200122 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 4 },
130};
131
Keith Packarde4b36692009-06-05 19:22:17 -0700132static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400133 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200134 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200135 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700143};
Eric Anholt273e27c2011-03-30 13:01:10 -0700144
Keith Packarde4b36692009-06-05 19:22:17 -0700145static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400146 .dot = { .min = 20000, .max = 400000 },
147 .vco = { .min = 1400000, .max = 2800000 },
148 .n = { .min = 1, .max = 6 },
149 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100150 .m1 = { .min = 8, .max = 18 },
151 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400152 .p = { .min = 5, .max = 80 },
153 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700154 .p2 = { .dot_limit = 200000,
155 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100163 .m1 = { .min = 8, .max = 18 },
164 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700169};
170
Eric Anholt273e27c2011-03-30 13:01:10 -0700171
Keith Packarde4b36692009-06-05 19:22:17 -0700172static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700173 .dot = { .min = 25000, .max = 270000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 17, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 10, .max = 30 },
180 .p1 = { .min = 1, .max = 3},
181 .p2 = { .dot_limit = 270000,
182 .p2_slow = 10,
183 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800184 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
186
187static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700188 .dot = { .min = 22000, .max = 400000 },
189 .vco = { .min = 1750000, .max = 3500000},
190 .n = { .min = 1, .max = 4 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 16, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8},
196 .p2 = { .dot_limit = 165000,
197 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700198};
199
200static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700201 .dot = { .min = 20000, .max = 115000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 28, .max = 112 },
208 .p1 = { .min = 2, .max = 8 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800211 },
Keith Packarde4b36692009-06-05 19:22:17 -0700212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800225 },
Keith Packarde4b36692009-06-05 19:22:17 -0700226};
227
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500228static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400229 .dot = { .min = 20000, .max = 400000},
230 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700231 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700234 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400235 .m1 = { .min = 0, .max = 0 },
236 .m2 = { .min = 0, .max = 254 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700239 .p2 = { .dot_limit = 200000,
240 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700241};
242
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500243static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1700000, .max = 3500000 },
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 .m1 = { .min = 0, .max = 0 },
249 .m2 = { .min = 0, .max = 254 },
250 .p = { .min = 7, .max = 112 },
251 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700252 .p2 = { .dot_limit = 112000,
253 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700254};
255
Eric Anholt273e27c2011-03-30 13:01:10 -0700256/* Ironlake / Sandybridge
257 *
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
260 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800261static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 1760000, .max = 3510000 },
264 .n = { .min = 1, .max = 5 },
265 .m = { .min = 79, .max = 127 },
266 .m1 = { .min = 12, .max = 22 },
267 .m2 = { .min = 5, .max = 9 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
270 .p2 = { .dot_limit = 225000,
271 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700272};
273
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800274static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 3 },
278 .m = { .min = 79, .max = 118 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 127 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 56 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800298};
299
Eric Anholt273e27c2011-03-30 13:01:10 -0700300/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800301static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 2 },
305 .m = { .min = 79, .max = 126 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400309 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800312};
313
314static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 3 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400322 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800325};
326
Ville Syrjälädc730512013-09-24 21:26:30 +0300327static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300328 /*
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
333 */
334 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200335 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700336 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700337 .m1 = { .min = 2, .max = 3 },
338 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300339 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300340 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700341};
342
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300343static const intel_limit_t intel_limits_chv = {
344 /*
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
349 */
350 .dot = { .min = 25000 * 5, .max = 540000 * 5},
351 .vco = { .min = 4860000, .max = 6700000 },
352 .n = { .min = 1, .max = 1 },
353 .m1 = { .min = 2, .max = 2 },
354 .m2 = { .min = 24 << 22, .max = 175 << 22 },
355 .p1 = { .min = 2, .max = 4 },
356 .p2 = { .p2_slow = 1, .p2_fast = 14 },
357};
358
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300359static void vlv_clock(int refclk, intel_clock_t *clock)
360{
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200363 if (WARN_ON(clock->n == 0 || clock->p == 0))
364 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300365 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300367}
368
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300369/**
370 * Returns whether any output on the specified pipe is of the specified type
371 */
372static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373{
374 struct drm_device *dev = crtc->dev;
375 struct intel_encoder *encoder;
376
377 for_each_encoder_on_crtc(dev, crtc, encoder)
378 if (encoder->type == type)
379 return true;
380
381 return false;
382}
383
Chris Wilson1b894b52010-12-14 20:04:54 +0000384static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800386{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800387 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800388 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100391 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000392 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000397 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200402 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800403 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800404
405 return limit;
406}
407
Ma Ling044c7c42009-03-18 20:13:23 +0800408static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409{
410 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100414 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700415 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800416 else
Keith Packarde4b36692009-06-05 19:22:17 -0700417 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700420 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700422 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800423 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700424 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800425
426 return limit;
427}
428
Chris Wilson1b894b52010-12-14 20:04:54 +0000429static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800430{
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
Eric Anholtbad720f2009-10-22 16:11:14 -0700434 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000435 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800436 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800437 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500438 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500440 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800441 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500442 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300443 } else if (IS_CHERRYVIEW(dev)) {
444 limit = &intel_limits_chv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700445 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300446 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100447 } else if (!IS_GEN2(dev)) {
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i9xx_lvds;
450 else
451 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800452 } else {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700454 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200455 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700456 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200457 else
458 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800459 }
460 return limit;
461}
462
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500463/* m1 is reserved as 0 in Pineview, n is a ring counter */
464static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800465{
Shaohua Li21778322009-02-23 15:19:16 +0800466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200468 if (WARN_ON(clock->n == 0 || clock->p == 0))
469 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300470 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800472}
473
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200474static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475{
476 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477}
478
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200479static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800480{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200481 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800482 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200483 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800487}
488
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300489static void chv_clock(int refclk, intel_clock_t *clock)
490{
491 clock->m = clock->m1 * clock->m2;
492 clock->p = clock->p1 * clock->p2;
493 if (WARN_ON(clock->n == 0 || clock->p == 0))
494 return;
495 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496 clock->n << 22);
497 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498}
499
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800500#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800501/**
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
504 */
505
Chris Wilson1b894b52010-12-14 20:04:54 +0000506static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800509{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300510 if (clock->n < limit->n.min || limit->n.max < clock->n)
511 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800512 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400513 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400515 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400517 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300518
519 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520 if (clock->m1 <= clock->m2)
521 INTELPllInvalid("m1 <= m2\n");
522
523 if (!IS_VALLEYVIEW(dev)) {
524 if (clock->p < limit->p.min || limit->p.max < clock->p)
525 INTELPllInvalid("p out of range\n");
526 if (clock->m < limit->m.min || limit->m.max < clock->m)
527 INTELPllInvalid("m out of range\n");
528 }
529
Jesse Barnes79e53942008-11-07 14:24:08 -0800530 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400531 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
534 */
535 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400536 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800537
538 return true;
539}
540
Ma Lingd4906092009-03-18 20:13:27 +0800541static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200542i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800543 int target, int refclk, intel_clock_t *match_clock,
544 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800545{
546 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800547 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800548 int err = target;
549
Daniel Vettera210b022012-11-26 17:22:08 +0100550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800551 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800555 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100556 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
Akshay Joshi0206e352011-08-16 15:34:10 -0400567 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800568
Zhao Yakui42158662009-11-20 11:24:18 +0800569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200573 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800574 break;
575 for (clock.n = limit->n.min;
576 clock.n <= limit->n.max; clock.n++) {
577 for (clock.p1 = limit->p1.min;
578 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800579 int this_err;
580
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200581 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000582 if (!intel_PLL_is_valid(dev, limit,
583 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800584 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800585 if (match_clock &&
586 clock.p != match_clock->p)
587 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800588
589 this_err = abs(clock.dot - target);
590 if (this_err < err) {
591 *best_clock = clock;
592 err = this_err;
593 }
594 }
595 }
596 }
597 }
598
599 return (err != target);
600}
601
Ma Lingd4906092009-03-18 20:13:27 +0800602static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200603pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200606{
607 struct drm_device *dev = crtc->dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659}
660
Ma Lingd4906092009-03-18 20:13:27 +0800661static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200662g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800665{
666 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800667 intel_clock_t clock;
668 int max_n;
669 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400670 /* approximately equals target * 0.00585 */
671 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800672 found = false;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100675 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800676 clock.p2 = limit->p2.p2_fast;
677 else
678 clock.p2 = limit->p2.p2_slow;
679 } else {
680 if (target < limit->p2.dot_limit)
681 clock.p2 = limit->p2.p2_slow;
682 else
683 clock.p2 = limit->p2.p2_fast;
684 }
685
686 memset(best_clock, 0, sizeof(*best_clock));
687 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200688 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800689 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200690 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800691 for (clock.m1 = limit->m1.max;
692 clock.m1 >= limit->m1.min; clock.m1--) {
693 for (clock.m2 = limit->m2.max;
694 clock.m2 >= limit->m2.min; clock.m2--) {
695 for (clock.p1 = limit->p1.max;
696 clock.p1 >= limit->p1.min; clock.p1--) {
697 int this_err;
698
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200699 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800702 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000703
704 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800705 if (this_err < err_most) {
706 *best_clock = clock;
707 err_most = this_err;
708 max_n = clock.n;
709 found = true;
710 }
711 }
712 }
713 }
714 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800715 return found;
716}
Ma Lingd4906092009-03-18 20:13:27 +0800717
Zhenyu Wang2c072452009-06-05 15:38:42 +0800718static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200719vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700722{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300723 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300724 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300725 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300726 /* min update 19.2 MHz */
727 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300728 bool found = false;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700729
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300730 target *= 5; /* fast clock */
731
732 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700733
734 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300736 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300737 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300738 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300739 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700740 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300741 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300742 unsigned int ppm, diff;
743
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300744 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300746
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300747 vlv_clock(refclk, &clock);
748
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300751 continue;
752
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300753 diff = abs(clock.dot - target);
754 ppm = div_u64(1000000ULL * diff, target);
755
756 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300757 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300758 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300759 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300760 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300761
Ville Syrjäläc6861222013-09-24 21:26:21 +0300762 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300763 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300764 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300765 found = true;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700766 }
767 }
768 }
769 }
770 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700771
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300772 return found;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700773}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700774
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300775static bool
776chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779{
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 uint64_t m2;
783 int found = false;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 /*
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
791 */
792 clock.n = 1, clock.m1 = 2;
793 target *= 5; /* fast clock */
794
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast;
797 clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800 clock.p = clock.p1 * clock.p2;
801
802 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803 clock.n) << 22, refclk * clock.m1);
804
805 if (m2 > INT_MAX/clock.m1)
806 continue;
807
808 clock.m2 = m2;
809
810 chv_clock(refclk, &clock);
811
812 if (!intel_PLL_is_valid(dev, limit, &clock))
813 continue;
814
815 /* based on hardware requirement, prefer bigger p
816 */
817 if (clock.p > best_clock->p) {
818 *best_clock = clock;
819 found = true;
820 }
821 }
822 }
823
824 return found;
825}
826
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300827bool intel_crtc_active(struct drm_crtc *crtc)
828{
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
833 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100834 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300835 * as Haswell has gained clock readout/fastboot support.
836 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000837 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300838 * properly reconstruct framebuffers.
839 */
Matt Roperf4510a22014-04-01 15:22:40 -0700840 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100841 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300842}
843
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200844enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845 enum pipe pipe)
846{
847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
Daniel Vetter3b117c82013-04-17 20:15:07 +0200850 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200851}
852
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200853static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200856 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300857
858 frame = I915_READ(frame_reg);
859
860 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Jesse Barnes93937072014-04-04 16:12:09 -0700861 WARN(1, "vblank wait timed out\n");
Paulo Zanonia928d532012-05-04 17:18:15 -0300862}
863
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700864/**
865 * intel_wait_for_vblank - wait for vblank on a given pipe
866 * @dev: drm device
867 * @pipe: pipe to wait for
868 *
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
870 * mode setting code.
871 */
872void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800873{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700874 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800875 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700876
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200877 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300879 return;
880 }
881
Chris Wilson300387c2010-09-05 20:25:43 +0100882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
884 *
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
891 * vblanks...
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
894 */
895 I915_WRITE(pipestat_reg,
896 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700898 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100899 if (wait_for(I915_READ(pipestat_reg) &
900 PIPE_VBLANK_INTERRUPT_STATUS,
901 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700902 DRM_DEBUG_KMS("vblank wait timed out\n");
903}
904
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300905static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906{
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 reg = PIPEDSL(pipe);
909 u32 line1, line2;
910 u32 line_mask;
911
912 if (IS_GEN2(dev))
913 line_mask = DSL_LINEMASK_GEN2;
914 else
915 line_mask = DSL_LINEMASK_GEN3;
916
917 line1 = I915_READ(reg) & line_mask;
918 mdelay(5);
919 line2 = I915_READ(reg) & line_mask;
920
921 return line1 == line2;
922}
923
Keith Packardab7ad7f2010-10-03 00:33:06 -0700924/*
925 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700926 * @dev: drm device
927 * @pipe: pipe to wait for
928 *
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
932 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700933 * On Gen4 and above:
934 * wait for the pipe register state bit to turn off
935 *
936 * Otherwise:
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100939 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700940 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100941void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700942{
943 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200944 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700946
Keith Packardab7ad7f2010-10-03 00:33:06 -0700947 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200948 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700949
Keith Packardab7ad7f2010-10-03 00:33:06 -0700950 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100951 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200953 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700954 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700955 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300956 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200957 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700958 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800959}
960
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000961/*
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
965 *
966 * Returns true if @port is connected, false otherwise.
967 */
968bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969 struct intel_digital_port *port)
970{
971 u32 bit;
972
Damien Lespiauc36346e2012-12-13 16:09:03 +0000973 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +0200974 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000975 case PORT_B:
976 bit = SDE_PORTB_HOTPLUG;
977 break;
978 case PORT_C:
979 bit = SDE_PORTC_HOTPLUG;
980 break;
981 case PORT_D:
982 bit = SDE_PORTD_HOTPLUG;
983 break;
984 default:
985 return true;
986 }
987 } else {
Robin Schroereba905b2014-05-18 02:24:50 +0200988 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000989 case PORT_B:
990 bit = SDE_PORTB_HOTPLUG_CPT;
991 break;
992 case PORT_C:
993 bit = SDE_PORTC_HOTPLUG_CPT;
994 break;
995 case PORT_D:
996 bit = SDE_PORTD_HOTPLUG_CPT;
997 break;
998 default:
999 return true;
1000 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001001 }
1002
1003 return I915_READ(SDEISR) & bit;
1004}
1005
Jesse Barnesb24e7172011-01-04 15:09:30 -08001006static const char *state_string(bool enabled)
1007{
1008 return enabled ? "on" : "off";
1009}
1010
1011/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001012void assert_pll(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001014{
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = DPLL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & DPLL_VCO_ENABLE);
1022 WARN(cur_state != state,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001026
Jani Nikula23538ef2013-08-27 15:12:22 +03001027/* XXX: the dsi pll is shared between MIPI DSI ports */
1028static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029{
1030 u32 val;
1031 bool cur_state;
1032
1033 mutex_lock(&dev_priv->dpio_lock);
1034 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035 mutex_unlock(&dev_priv->dpio_lock);
1036
1037 cur_state = val & DSI_PLL_VCO_EN;
1038 WARN(cur_state != state,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041}
1042#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
Daniel Vetter55607e82013-06-16 21:42:39 +02001045struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001046intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001047{
Daniel Vettere2b78262013-06-07 23:10:03 +02001048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
Daniel Vettera43f6e02013-06-07 23:10:32 +02001050 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001051 return NULL;
1052
Daniel Vettera43f6e02013-06-07 23:10:32 +02001053 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001054}
1055
Jesse Barnesb24e7172011-01-04 15:09:30 -08001056/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001057void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058 struct intel_shared_dpll *pll,
1059 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001060{
Jesse Barnes040484a2011-01-03 12:14:26 -08001061 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001062 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001063
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001064 if (HAS_PCH_LPT(dev_priv->dev)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066 return;
1067 }
1068
Chris Wilson92b27b02012-05-20 18:10:50 +01001069 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001070 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001072
Daniel Vetter53589012013-06-05 13:34:16 +02001073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001074 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001077}
Jesse Barnes040484a2011-01-03 12:14:26 -08001078
1079static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081{
1082 int reg;
1083 u32 val;
1084 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001087
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001091 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101}
1102#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107{
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001130 return;
1131
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001133 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 return;
1135
Jesse Barnes040484a2011-01-03 12:14:26 -08001136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139}
1140
Daniel Vetter55607e82013-06-16 21:42:39 +02001141void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001143{
1144 int reg;
1145 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001146 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001154}
1155
Jesse Barnesea0760c2011-01-04 15:09:32 -08001156static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158{
1159 int pp_reg, lvds_reg;
1160 u32 val;
1161 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001162 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001163
1164 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165 pp_reg = PCH_PP_CONTROL;
1166 lvds_reg = PCH_LVDS;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 lvds_reg = LVDS;
1170 }
1171
1172 val = I915_READ(pp_reg);
1173 if (!(val & PANEL_POWER_ON) ||
1174 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175 locked = false;
1176
1177 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179
1180 WARN(panel_pipe == pipe && locked,
1181 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001182 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001183}
1184
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001185static void assert_cursor(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 struct drm_device *dev = dev_priv->dev;
1189 bool cur_state;
1190
Paulo Zanonid9d82082014-02-27 16:30:56 -03001191 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001192 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001193 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001194 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001195
1196 WARN(cur_state != state,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe), state_string(state), state_string(cur_state));
1199}
1200#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001203void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001205{
1206 int reg;
1207 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001208 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001209 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001211
Daniel Vetter8e636782012-01-22 01:36:48 +01001212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214 state = true;
1215
Imre Deakda7e29b2014-02-18 00:02:02 +02001216 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001217 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001218 cur_state = false;
1219 } else {
1220 reg = PIPECONF(cpu_transcoder);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 }
1224
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001225 WARN(cur_state != state,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001227 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001228}
1229
Chris Wilson931872f2012-01-16 23:01:13 +00001230static void assert_plane(struct drm_i915_private *dev_priv,
1231 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001232{
1233 int reg;
1234 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001235 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001236
1237 reg = DSPCNTR(plane);
1238 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001239 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240 WARN(cur_state != state,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001243}
1244
Chris Wilson931872f2012-01-16 23:01:13 +00001245#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
Jesse Barnesb24e7172011-01-04 15:09:30 -08001248static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249 enum pipe pipe)
1250{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001251 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
Ville Syrjälä653e1022013-06-04 13:49:05 +03001256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001260 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001263 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001264 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001265
Jesse Barnesb24e7172011-01-04 15:09:30 -08001266 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001267 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001275 }
1276}
1277
Jesse Barnes19332d72013-03-28 09:55:38 -07001278static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001281 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001282 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001283 u32 val;
1284
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001285 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001286 for_each_sprite(pipe, sprite) {
1287 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001288 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001289 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001291 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001292 }
1293 } else if (INTEL_INFO(dev)->gen >= 7) {
1294 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001295 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001296 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001298 plane_name(pipe), pipe_name(pipe));
1299 } else if (INTEL_INFO(dev)->gen >= 5) {
1300 reg = DVSCNTR(pipe);
1301 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001302 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001305 }
1306}
1307
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001308static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001309{
1310 u32 val;
1311 bool enabled;
1312
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001313 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001314
Jesse Barnes92f25842011-01-04 15:09:34 -08001315 val = I915_READ(PCH_DREF_CONTROL);
1316 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317 DREF_SUPERSPREAD_SOURCE_MASK));
1318 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319}
1320
Daniel Vetterab9412b2013-05-03 11:49:46 +02001321static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001323{
1324 int reg;
1325 u32 val;
1326 bool enabled;
1327
Daniel Vetterab9412b2013-05-03 11:49:46 +02001328 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001329 val = I915_READ(reg);
1330 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001331 WARN(enabled,
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001334}
1335
Keith Packard4e634382011-08-06 10:39:45 -07001336static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001338{
1339 if ((val & DP_PORT_EN) == 0)
1340 return false;
1341
1342 if (HAS_PCH_CPT(dev_priv->dev)) {
1343 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001347 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001350 } else {
1351 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352 return false;
1353 }
1354 return true;
1355}
1356
Keith Packard1519b992011-08-06 10:35:34 -07001357static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001360 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001361 return false;
1362
1363 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001364 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001365 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001366 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001369 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001370 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001371 return false;
1372 }
1373 return true;
1374}
1375
1376static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, u32 val)
1378{
1379 if ((val & LVDS_PORT_EN) == 0)
1380 return false;
1381
1382 if (HAS_PCH_CPT(dev_priv->dev)) {
1383 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 return false;
1385 } else {
1386 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387 return false;
1388 }
1389 return true;
1390}
1391
1392static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394{
1395 if ((val & ADPA_DAC_ENABLE) == 0)
1396 return false;
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399 return false;
1400 } else {
1401 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402 return false;
1403 }
1404 return true;
1405}
1406
Jesse Barnes291906f2011-02-02 12:28:03 -08001407static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001408 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001409{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001410 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001411 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001413 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001414
Daniel Vetter75c5da22012-09-10 21:58:29 +02001415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001417 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001418}
1419
1420static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, int reg)
1422{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001423 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001424 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001426 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001427
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001428 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001429 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001430 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001431}
1432
1433static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001438
Keith Packardf0575e92011-07-25 22:12:43 -07001439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001442
1443 reg = PCH_ADPA;
1444 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001445 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001446 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001447 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001448
1449 reg = PCH_LVDS;
1450 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001451 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001453 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001454
Paulo Zanonie2debe92013-02-18 19:00:27 -03001455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001458}
1459
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001460static void intel_init_dpio(struct drm_device *dev)
1461{
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001467 /*
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471 */
1472 if (IS_CHERRYVIEW(dev)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475 } else {
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001478}
1479
1480static void intel_reset_dpio(struct drm_device *dev)
1481{
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484 if (!IS_VALLEYVIEW(dev))
1485 return;
1486
Imre Deake5cbfbf2014-01-09 17:08:16 +02001487 /*
1488 * Enable the CRI clock source so we can get at the display and the
1489 * reference clock for VGA hotplug / manual detection.
1490 */
Imre Deak404faab2014-01-09 17:08:15 +02001491 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
Imre Deake5cbfbf2014-01-09 17:08:16 +02001492 DPLL_REFA_CLK_ENABLE_VLV |
Imre Deak404faab2014-01-09 17:08:15 +02001493 DPLL_INTEGRATED_CRI_CLK_VLV);
1494
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001495 if (IS_CHERRYVIEW(dev)) {
1496 enum dpio_phy phy;
1497 u32 val;
1498
1499 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1500 /* Poll for phypwrgood signal */
1501 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1502 PHY_POWERGOOD(phy), 1))
1503 DRM_ERROR("Display PHY %d is not power up\n", phy);
1504
1505 /*
1506 * Deassert common lane reset for PHY.
1507 *
1508 * This should only be done on init and resume from S3
1509 * with both PLLs disabled, or we risk losing DPIO and
1510 * PLL synchronization.
1511 */
1512 val = I915_READ(DISPLAY_PHY_CONTROL);
1513 I915_WRITE(DISPLAY_PHY_CONTROL,
1514 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1515 }
1516
1517 } else {
1518 /*
1519 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1520 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1521 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1522 * b. The other bits such as sfr settings / modesel may all
1523 * be set to 0.
1524 *
1525 * This should only be done on init and resume from S3 with
1526 * both PLLs disabled, or we risk losing DPIO and PLL
1527 * synchronization.
1528 */
1529 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1530 }
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001531}
1532
Daniel Vetter426115c2013-07-11 22:13:42 +02001533static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001534{
Daniel Vetter426115c2013-07-11 22:13:42 +02001535 struct drm_device *dev = crtc->base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 int reg = DPLL(crtc->pipe);
1538 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001539
Daniel Vetter426115c2013-07-11 22:13:42 +02001540 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001541
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001542 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001543 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1544
1545 /* PLL is protected by panel, make sure we can write it */
1546 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001547 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001548
Daniel Vetter426115c2013-07-11 22:13:42 +02001549 I915_WRITE(reg, dpll);
1550 POSTING_READ(reg);
1551 udelay(150);
1552
1553 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1555
1556 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1557 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001558
1559 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001560 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001561 POSTING_READ(reg);
1562 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001563 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001566 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569}
1570
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001571static void chv_enable_pll(struct intel_crtc *crtc)
1572{
1573 struct drm_device *dev = crtc->base.dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int pipe = crtc->pipe;
1576 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001577 u32 tmp;
1578
1579 assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1582
1583 mutex_lock(&dev_priv->dpio_lock);
1584
1585 /* Enable back the 10bit clock to display controller */
1586 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 tmp |= DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590 /*
1591 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1592 */
1593 udelay(1);
1594
1595 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001596 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001597
1598 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001599 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001600 DRM_ERROR("PLL %d failed to lock\n", pipe);
1601
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001602 /* not sure when this should be written */
1603 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1604 POSTING_READ(DPLL_MD(pipe));
1605
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001606 mutex_unlock(&dev_priv->dpio_lock);
1607}
1608
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001609static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001610{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001615
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001616 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001617
1618 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001619 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001620
1621 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001624
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001625 I915_WRITE(reg, dpll);
1626
1627 /* Wait for the clocks to stabilize. */
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (INTEL_INFO(dev)->gen >= 4) {
1632 I915_WRITE(DPLL_MD(crtc->pipe),
1633 crtc->config.dpll_hw_state.dpll_md);
1634 } else {
1635 /* The pixel multiplier can only be updated once the
1636 * DPLL is enabled and the clocks are stable.
1637 *
1638 * So write it again.
1639 */
1640 I915_WRITE(reg, dpll);
1641 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001642
1643 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001644 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001647 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001650 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653}
1654
1655/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001656 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001657 * @dev_priv: i915 private structure
1658 * @pipe: pipe PLL to disable
1659 *
1660 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 *
1662 * Note! This is for pre-ILK only.
1663 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001664static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001665{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001666 /* Don't disable pipe A or pipe A PLLs if needed */
1667 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1668 return;
1669
1670 /* Make sure the pipe isn't still relying on us */
1671 assert_pipe_disabled(dev_priv, pipe);
1672
Daniel Vetter50b44a42013-06-05 13:34:33 +02001673 I915_WRITE(DPLL(pipe), 0);
1674 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001675}
1676
Jesse Barnesf6071162013-10-01 10:41:38 -07001677static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1678{
1679 u32 val = 0;
1680
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv, pipe);
1683
Imre Deake5cbfbf2014-01-09 17:08:16 +02001684 /*
1685 * Leave integrated clock source and reference clock enabled for pipe B.
1686 * The latter is needed for VGA hotplug / manual detection.
1687 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001688 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001689 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001690 I915_WRITE(DPLL(pipe), val);
1691 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001692
1693}
1694
1695static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001697 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001698 u32 val;
1699
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001700 /* Make sure the pipe isn't still relying on us */
1701 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001702
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001703 /* Set PLL en = 0 */
1704 val = DPLL_SSC_REF_CLOCK_CHV;
1705 if (pipe != PIPE_A)
1706 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001709
1710 mutex_lock(&dev_priv->dpio_lock);
1711
1712 /* Disable 10bit clock to display controller */
1713 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1714 val &= ~DPIO_DCLKP_EN;
1715 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1716
1717 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001718}
1719
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001720void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1721 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001722{
1723 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001724 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001725
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001726 switch (dport->port) {
1727 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001728 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001729 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001730 break;
1731 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001732 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001733 dpll_reg = DPLL(0);
1734 break;
1735 case PORT_D:
1736 port_mask = DPLL_PORTD_READY_MASK;
1737 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001738 break;
1739 default:
1740 BUG();
1741 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001742
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001743 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001744 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001745 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001746}
1747
Daniel Vetterb14b1052014-04-24 23:55:13 +02001748static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1749{
1750 struct drm_device *dev = crtc->base.dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1753
1754 WARN_ON(!pll->refcount);
1755 if (pll->active == 0) {
1756 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1757 WARN_ON(pll->on);
1758 assert_shared_dpll_disabled(dev_priv, pll);
1759
1760 pll->mode_set(dev_priv, pll);
1761 }
1762}
1763
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001764/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001765 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to enable
1768 *
1769 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1770 * drives the transcoder clock.
1771 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001772static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001773{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001774 struct drm_device *dev = crtc->base.dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001776 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001777
Daniel Vetter87a875b2013-06-05 13:34:19 +02001778 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001779 return;
1780
1781 if (WARN_ON(pll->refcount == 0))
1782 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001783
Daniel Vetter46edb022013-06-05 13:34:12 +02001784 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1785 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001786 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001787
Daniel Vettercdbd2312013-06-05 13:34:03 +02001788 if (pll->active++) {
1789 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001790 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001791 return;
1792 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001793 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001794
Daniel Vetter46edb022013-06-05 13:34:12 +02001795 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001796 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001797 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001798}
1799
Daniel Vettere2b78262013-06-07 23:10:03 +02001800static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001805
Jesse Barnes92f25842011-01-04 15:09:34 -08001806 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001807 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001808 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001809 return;
1810
Chris Wilson48da64a2012-05-13 20:16:12 +01001811 if (WARN_ON(pll->refcount == 0))
1812 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001813
Daniel Vetter46edb022013-06-05 13:34:12 +02001814 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001816 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001817
Chris Wilson48da64a2012-05-13 20:16:12 +01001818 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001819 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001820 return;
1821 }
1822
Daniel Vettere9d69442013-06-05 13:34:15 +02001823 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001824 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001825 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001826 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827
Daniel Vetter46edb022013-06-05 13:34:12 +02001828 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001829 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001830 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001831}
1832
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001833static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001835{
Daniel Vetter23670b322012-11-01 09:15:30 +01001836 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001837 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001839 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001840
1841 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001842 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001843
1844 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001845 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001846 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001847
1848 /* FDI must be feeding us bits for PCH ports */
1849 assert_fdi_tx_enabled(dev_priv, pipe);
1850 assert_fdi_rx_enabled(dev_priv, pipe);
1851
Daniel Vetter23670b322012-11-01 09:15:30 +01001852 if (HAS_PCH_CPT(dev)) {
1853 /* Workaround: Set the timing override bit before enabling the
1854 * pch transcoder. */
1855 reg = TRANS_CHICKEN2(pipe);
1856 val = I915_READ(reg);
1857 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001859 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001860
Daniel Vetterab9412b2013-05-03 11:49:46 +02001861 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001862 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001863 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001864
1865 if (HAS_PCH_IBX(dev_priv->dev)) {
1866 /*
1867 * make the BPC in transcoder be consistent with
1868 * that in pipeconf reg.
1869 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001870 val &= ~PIPECONF_BPC_MASK;
1871 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001872 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001873
1874 val &= ~TRANS_INTERLACE_MASK;
1875 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001876 if (HAS_PCH_IBX(dev_priv->dev) &&
1877 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1878 val |= TRANS_LEGACY_INTERLACED_ILK;
1879 else
1880 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001881 else
1882 val |= TRANS_PROGRESSIVE;
1883
Jesse Barnes040484a2011-01-03 12:14:26 -08001884 I915_WRITE(reg, val | TRANS_ENABLE);
1885 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001886 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001887}
1888
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001889static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001890 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001891{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001892 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001893
1894 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001895 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001896
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001897 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001898 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001899 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001900
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001901 /* Workaround: set timing override bit. */
1902 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001903 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001904 I915_WRITE(_TRANSA_CHICKEN2, val);
1905
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001906 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001907 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001908
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001909 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1910 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001911 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001912 else
1913 val |= TRANS_PROGRESSIVE;
1914
Daniel Vetterab9412b2013-05-03 11:49:46 +02001915 I915_WRITE(LPT_TRANSCONF, val);
1916 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001917 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001918}
1919
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001920static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1921 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001922{
Daniel Vetter23670b322012-11-01 09:15:30 +01001923 struct drm_device *dev = dev_priv->dev;
1924 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001925
1926 /* FDI relies on the transcoder */
1927 assert_fdi_tx_disabled(dev_priv, pipe);
1928 assert_fdi_rx_disabled(dev_priv, pipe);
1929
Jesse Barnes291906f2011-02-02 12:28:03 -08001930 /* Ports must be off as well */
1931 assert_pch_ports_disabled(dev_priv, pipe);
1932
Daniel Vetterab9412b2013-05-03 11:49:46 +02001933 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001934 val = I915_READ(reg);
1935 val &= ~TRANS_ENABLE;
1936 I915_WRITE(reg, val);
1937 /* wait for PCH transcoder off, transcoder state */
1938 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001939 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001940
1941 if (!HAS_PCH_IBX(dev)) {
1942 /* Workaround: Clear the timing override chicken bit again. */
1943 reg = TRANS_CHICKEN2(pipe);
1944 val = I915_READ(reg);
1945 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946 I915_WRITE(reg, val);
1947 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001948}
1949
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001950static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001951{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001952 u32 val;
1953
Daniel Vetterab9412b2013-05-03 11:49:46 +02001954 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001955 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001956 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001957 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001958 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001959 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001960
1961 /* Workaround: clear timing override bit. */
1962 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001963 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001964 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001965}
1966
1967/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001968 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001969 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001970 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001971 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001972 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001973 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001974static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001975{
Paulo Zanoni03722642014-01-17 13:51:09 -02001976 struct drm_device *dev = crtc->base.dev;
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1978 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001979 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1980 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001981 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001982 int reg;
1983 u32 val;
1984
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001985 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001986 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001987 assert_sprites_disabled(dev_priv, pipe);
1988
Paulo Zanoni681e5812012-12-06 11:12:38 -02001989 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001990 pch_transcoder = TRANSCODER_A;
1991 else
1992 pch_transcoder = pipe;
1993
Jesse Barnesb24e7172011-01-04 15:09:30 -08001994 /*
1995 * A pipe without a PLL won't actually be able to drive bits from
1996 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1997 * need the check.
1998 */
1999 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002000 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002001 assert_dsi_pll_enabled(dev_priv);
2002 else
2003 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002004 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002005 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002006 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002007 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002008 assert_fdi_tx_pll_enabled(dev_priv,
2009 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002010 }
2011 /* FIXME: assert CPU port conditions for SNB+ */
2012 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002013
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002014 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002015 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002016 if (val & PIPECONF_ENABLE) {
2017 WARN_ON(!(pipe == PIPE_A &&
2018 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002019 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002020 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002021
2022 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002023 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002024}
2025
2026/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002027 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002028 * @dev_priv: i915 private structure
2029 * @pipe: pipe to disable
2030 *
2031 * Disable @pipe, making sure that various hardware specific requirements
2032 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2033 *
2034 * @pipe should be %PIPE_A or %PIPE_B.
2035 *
2036 * Will wait until the pipe has shut down before returning.
2037 */
2038static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2039 enum pipe pipe)
2040{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002041 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2042 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002043 int reg;
2044 u32 val;
2045
2046 /*
2047 * Make sure planes won't keep trying to pump pixels to us,
2048 * or we might hang the display.
2049 */
2050 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002051 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002052 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002053
2054 /* Don't disable pipe A or pipe A PLLs if needed */
2055 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2056 return;
2057
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002058 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002059 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002060 if ((val & PIPECONF_ENABLE) == 0)
2061 return;
2062
2063 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002064 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2065}
2066
Keith Packardd74362c2011-07-28 14:47:14 -07002067/*
2068 * Plane regs are double buffered, going from enabled->disabled needs a
2069 * trigger in order to latch. The display address reg provides this.
2070 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002071void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2072 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002073{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002074 struct drm_device *dev = dev_priv->dev;
2075 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002076
2077 I915_WRITE(reg, I915_READ(reg));
2078 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002079}
2080
Jesse Barnesb24e7172011-01-04 15:09:30 -08002081/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002082 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083 * @dev_priv: i915 private structure
2084 * @plane: plane to enable
2085 * @pipe: pipe being fed
2086 *
2087 * Enable @plane on @pipe, making sure that @pipe is running first.
2088 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002089static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2090 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002091{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002092 struct intel_crtc *intel_crtc =
2093 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002094 int reg;
2095 u32 val;
2096
2097 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2098 assert_pipe_enabled(dev_priv, pipe);
2099
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002100 if (intel_crtc->primary_enabled)
2101 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002102
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002103 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002104
Jesse Barnesb24e7172011-01-04 15:09:30 -08002105 reg = DSPCNTR(plane);
2106 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002107 WARN_ON(val & DISPLAY_PLANE_ENABLE);
Chris Wilson00d70b12011-03-17 07:18:29 +00002108
2109 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002110 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002111}
2112
Jesse Barnesb24e7172011-01-04 15:09:30 -08002113/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002114 * intel_disable_primary_hw_plane - disable the primary hardware plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002115 * @dev_priv: i915 private structure
2116 * @plane: plane to disable
2117 * @pipe: pipe consuming the data
2118 *
2119 * Disable @plane; should be an independent operation.
2120 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002121static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2122 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002123{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002124 struct intel_crtc *intel_crtc =
2125 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 int reg;
2127 u32 val;
2128
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002129 if (!intel_crtc->primary_enabled)
2130 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002131
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002132 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002133
Jesse Barnesb24e7172011-01-04 15:09:30 -08002134 reg = DSPCNTR(plane);
2135 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002136 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
Chris Wilson00d70b12011-03-17 07:18:29 +00002137
2138 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002139 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002140}
2141
Chris Wilson693db182013-03-05 14:52:39 +00002142static bool need_vtd_wa(struct drm_device *dev)
2143{
2144#ifdef CONFIG_INTEL_IOMMU
2145 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146 return true;
2147#endif
2148 return false;
2149}
2150
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002151static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2152{
2153 int tile_height;
2154
2155 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2156 return ALIGN(height, tile_height);
2157}
2158
Chris Wilson127bd2a2010-07-23 23:32:05 +01002159int
Chris Wilson48b956c2010-09-14 12:50:34 +01002160intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002161 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002162 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002163{
Chris Wilsonce453d82011-02-21 14:43:56 +00002164 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002165 u32 alignment;
2166 int ret;
2167
Chris Wilson05394f32010-11-08 19:18:58 +00002168 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002169 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002170 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2171 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002172 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002173 alignment = 4 * 1024;
2174 else
2175 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002176 break;
2177 case I915_TILING_X:
2178 /* pin() will align the object as required by fence */
2179 alignment = 0;
2180 break;
2181 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002182 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002183 return -EINVAL;
2184 default:
2185 BUG();
2186 }
2187
Chris Wilson693db182013-03-05 14:52:39 +00002188 /* Note that the w/a also requires 64 PTE of padding following the
2189 * bo. We currently fill all unused PTE with the shadow page and so
2190 * we should always have valid PTE following the scanout preventing
2191 * the VT-d warning.
2192 */
2193 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2194 alignment = 256 * 1024;
2195
Chris Wilsonce453d82011-02-21 14:43:56 +00002196 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002197 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002198 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002199 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002200
2201 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2202 * fence, whereas 965+ only requires a fence if using
2203 * framebuffer compression. For simplicity, we always install
2204 * a fence as the cost is not that onerous.
2205 */
Chris Wilson06d98132012-04-17 15:31:24 +01002206 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002207 if (ret)
2208 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002209
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002210 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002211
Chris Wilsonce453d82011-02-21 14:43:56 +00002212 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002213 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002214
2215err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002216 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002217err_interruptible:
2218 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002219 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002220}
2221
Chris Wilson1690e1e2011-12-14 13:57:08 +01002222void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2223{
2224 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002225 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002226}
2227
Daniel Vetterc2c75132012-07-05 12:17:30 +02002228/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2229 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002230unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2231 unsigned int tiling_mode,
2232 unsigned int cpp,
2233 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002234{
Chris Wilsonbc752862013-02-21 20:04:31 +00002235 if (tiling_mode != I915_TILING_NONE) {
2236 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002237
Chris Wilsonbc752862013-02-21 20:04:31 +00002238 tile_rows = *y / 8;
2239 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002240
Chris Wilsonbc752862013-02-21 20:04:31 +00002241 tiles = *x / (512/cpp);
2242 *x %= 512/cpp;
2243
2244 return tile_rows * pitch * 8 + tiles * 4096;
2245 } else {
2246 unsigned int offset;
2247
2248 offset = *y * pitch + *x * cpp;
2249 *y = 0;
2250 *x = (offset & 4095) / cpp;
2251 return offset & -4096;
2252 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002253}
2254
Jesse Barnes46f297f2014-03-07 08:57:48 -08002255int intel_format_to_fourcc(int format)
2256{
2257 switch (format) {
2258 case DISPPLANE_8BPP:
2259 return DRM_FORMAT_C8;
2260 case DISPPLANE_BGRX555:
2261 return DRM_FORMAT_XRGB1555;
2262 case DISPPLANE_BGRX565:
2263 return DRM_FORMAT_RGB565;
2264 default:
2265 case DISPPLANE_BGRX888:
2266 return DRM_FORMAT_XRGB8888;
2267 case DISPPLANE_RGBX888:
2268 return DRM_FORMAT_XBGR8888;
2269 case DISPPLANE_BGRX101010:
2270 return DRM_FORMAT_XRGB2101010;
2271 case DISPPLANE_RGBX101010:
2272 return DRM_FORMAT_XBGR2101010;
2273 }
2274}
2275
Jesse Barnes484b41d2014-03-07 08:57:55 -08002276static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002277 struct intel_plane_config *plane_config)
2278{
2279 struct drm_device *dev = crtc->base.dev;
2280 struct drm_i915_gem_object *obj = NULL;
2281 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2282 u32 base = plane_config->base;
2283
Chris Wilsonff2652e2014-03-10 08:07:02 +00002284 if (plane_config->size == 0)
2285 return false;
2286
Jesse Barnes46f297f2014-03-07 08:57:48 -08002287 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2288 plane_config->size);
2289 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002290 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002291
2292 if (plane_config->tiled) {
2293 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002294 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002295 }
2296
Dave Airlie66e514c2014-04-03 07:51:54 +10002297 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2298 mode_cmd.width = crtc->base.primary->fb->width;
2299 mode_cmd.height = crtc->base.primary->fb->height;
2300 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002301
2302 mutex_lock(&dev->struct_mutex);
2303
Dave Airlie66e514c2014-04-03 07:51:54 +10002304 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002305 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002306 DRM_DEBUG_KMS("intel fb init failed\n");
2307 goto out_unref_obj;
2308 }
2309
2310 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002311
2312 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2313 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002314
2315out_unref_obj:
2316 drm_gem_object_unreference(&obj->base);
2317 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002318 return false;
2319}
2320
2321static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2322 struct intel_plane_config *plane_config)
2323{
2324 struct drm_device *dev = intel_crtc->base.dev;
2325 struct drm_crtc *c;
2326 struct intel_crtc *i;
2327 struct intel_framebuffer *fb;
2328
Dave Airlie66e514c2014-04-03 07:51:54 +10002329 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002330 return;
2331
2332 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2333 return;
2334
Dave Airlie66e514c2014-04-03 07:51:54 +10002335 kfree(intel_crtc->base.primary->fb);
2336 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002337
2338 /*
2339 * Failed to alloc the obj, check to see if we should share
2340 * an fb with another CRTC instead
2341 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002342 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002343 i = to_intel_crtc(c);
2344
2345 if (c == &intel_crtc->base)
2346 continue;
2347
Dave Airlie66e514c2014-04-03 07:51:54 +10002348 if (!i->active || !c->primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002349 continue;
2350
Dave Airlie66e514c2014-04-03 07:51:54 +10002351 fb = to_intel_framebuffer(c->primary->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002352 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002353 drm_framebuffer_reference(c->primary->fb);
2354 intel_crtc->base.primary->fb = c->primary->fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002355 break;
2356 }
2357 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002358}
2359
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002360static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2361 struct drm_framebuffer *fb,
2362 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002363{
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002368 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002369 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002370 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002371 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002372 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002373
Jesse Barnes81255562010-08-02 12:07:50 -07002374 intel_fb = to_intel_framebuffer(fb);
2375 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002376
Chris Wilson5eddb702010-09-11 13:48:45 +01002377 reg = DSPCNTR(plane);
2378 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002379 /* Mask out pixel format bits in case we change it */
2380 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002381 switch (fb->pixel_format) {
2382 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002383 dspcntr |= DISPPLANE_8BPP;
2384 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002385 case DRM_FORMAT_XRGB1555:
2386 case DRM_FORMAT_ARGB1555:
2387 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002388 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002389 case DRM_FORMAT_RGB565:
2390 dspcntr |= DISPPLANE_BGRX565;
2391 break;
2392 case DRM_FORMAT_XRGB8888:
2393 case DRM_FORMAT_ARGB8888:
2394 dspcntr |= DISPPLANE_BGRX888;
2395 break;
2396 case DRM_FORMAT_XBGR8888:
2397 case DRM_FORMAT_ABGR8888:
2398 dspcntr |= DISPPLANE_RGBX888;
2399 break;
2400 case DRM_FORMAT_XRGB2101010:
2401 case DRM_FORMAT_ARGB2101010:
2402 dspcntr |= DISPPLANE_BGRX101010;
2403 break;
2404 case DRM_FORMAT_XBGR2101010:
2405 case DRM_FORMAT_ABGR2101010:
2406 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002407 break;
2408 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002409 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002410 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002411
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002412 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002413 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002414 dspcntr |= DISPPLANE_TILED;
2415 else
2416 dspcntr &= ~DISPPLANE_TILED;
2417 }
2418
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002419 if (IS_G4X(dev))
2420 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2421
Chris Wilson5eddb702010-09-11 13:48:45 +01002422 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002423
Daniel Vettere506a0c2012-07-05 12:17:29 +02002424 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002425
Daniel Vetterc2c75132012-07-05 12:17:30 +02002426 if (INTEL_INFO(dev)->gen >= 4) {
2427 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002428 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2429 fb->bits_per_pixel / 8,
2430 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002431 linear_offset -= intel_crtc->dspaddr_offset;
2432 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002433 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002434 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002435
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002436 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2437 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2438 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002439 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002440 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002441 I915_WRITE(DSPSURF(plane),
2442 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002443 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002444 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002445 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002446 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002447 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002448}
2449
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002450static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2451 struct drm_framebuffer *fb,
2452 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002453{
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 struct intel_framebuffer *intel_fb;
2458 struct drm_i915_gem_object *obj;
2459 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002460 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002461 u32 dspcntr;
2462 u32 reg;
2463
Jesse Barnes17638cd2011-06-24 12:19:23 -07002464 intel_fb = to_intel_framebuffer(fb);
2465 obj = intel_fb->obj;
2466
2467 reg = DSPCNTR(plane);
2468 dspcntr = I915_READ(reg);
2469 /* Mask out pixel format bits in case we change it */
2470 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002471 switch (fb->pixel_format) {
2472 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002473 dspcntr |= DISPPLANE_8BPP;
2474 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002475 case DRM_FORMAT_RGB565:
2476 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002477 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002478 case DRM_FORMAT_XRGB8888:
2479 case DRM_FORMAT_ARGB8888:
2480 dspcntr |= DISPPLANE_BGRX888;
2481 break;
2482 case DRM_FORMAT_XBGR8888:
2483 case DRM_FORMAT_ABGR8888:
2484 dspcntr |= DISPPLANE_RGBX888;
2485 break;
2486 case DRM_FORMAT_XRGB2101010:
2487 case DRM_FORMAT_ARGB2101010:
2488 dspcntr |= DISPPLANE_BGRX101010;
2489 break;
2490 case DRM_FORMAT_XBGR2101010:
2491 case DRM_FORMAT_ABGR2101010:
2492 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002493 break;
2494 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002495 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002496 }
2497
2498 if (obj->tiling_mode != I915_TILING_NONE)
2499 dspcntr |= DISPPLANE_TILED;
2500 else
2501 dspcntr &= ~DISPPLANE_TILED;
2502
Ville Syrjäläb42c6002013-11-03 13:47:27 +02002503 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002504 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2505 else
2506 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002507
2508 I915_WRITE(reg, dspcntr);
2509
Daniel Vettere506a0c2012-07-05 12:17:29 +02002510 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002511 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002512 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2513 fb->bits_per_pixel / 8,
2514 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002515 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002516
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002517 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2518 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2519 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002520 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002521 I915_WRITE(DSPSURF(plane),
2522 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002523 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002524 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2525 } else {
2526 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2527 I915_WRITE(DSPLINOFF(plane), linear_offset);
2528 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002529 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002530}
2531
2532/* Assume fb object is pinned & idle & fenced and just update base pointers */
2533static int
2534intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2535 int x, int y, enum mode_set_atomic state)
2536{
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002539
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002540 if (dev_priv->display.disable_fbc)
2541 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002542 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002543
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002544 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2545
2546 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002547}
2548
Ville Syrjälä96a02912013-02-18 19:08:49 +02002549void intel_display_handle_reset(struct drm_device *dev)
2550{
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 struct drm_crtc *crtc;
2553
2554 /*
2555 * Flips in the rings have been nuked by the reset,
2556 * so complete all pending flips so that user space
2557 * will get its events and not get stuck.
2558 *
2559 * Also update the base address of all primary
2560 * planes to the the last fb to make sure we're
2561 * showing the correct fb after a reset.
2562 *
2563 * Need to make two loops over the crtcs so that we
2564 * don't try to grab a crtc mutex before the
2565 * pending_flip_queue really got woken up.
2566 */
2567
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002568 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570 enum plane plane = intel_crtc->plane;
2571
2572 intel_prepare_page_flip(dev, plane);
2573 intel_finish_page_flip_plane(dev, plane);
2574 }
2575
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002576 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578
2579 mutex_lock(&crtc->mutex);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002580 /*
2581 * FIXME: Once we have proper support for primary planes (and
2582 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002583 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002584 */
Matt Roperf4510a22014-04-01 15:22:40 -07002585 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002586 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002587 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002588 crtc->x,
2589 crtc->y);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002590 mutex_unlock(&crtc->mutex);
2591 }
2592}
2593
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002594static int
Chris Wilson14667a42012-04-03 17:58:35 +01002595intel_finish_fb(struct drm_framebuffer *old_fb)
2596{
2597 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2598 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2599 bool was_interruptible = dev_priv->mm.interruptible;
2600 int ret;
2601
Chris Wilson14667a42012-04-03 17:58:35 +01002602 /* Big Hammer, we also need to ensure that any pending
2603 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2604 * current scanout is retired before unpinning the old
2605 * framebuffer.
2606 *
2607 * This should only fail upon a hung GPU, in which case we
2608 * can safely continue.
2609 */
2610 dev_priv->mm.interruptible = false;
2611 ret = i915_gem_object_finish_gpu(obj);
2612 dev_priv->mm.interruptible = was_interruptible;
2613
2614 return ret;
2615}
2616
Chris Wilson7d5e3792014-03-04 13:15:08 +00002617static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2618{
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 unsigned long flags;
2623 bool pending;
2624
2625 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2626 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2627 return false;
2628
2629 spin_lock_irqsave(&dev->event_lock, flags);
2630 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2631 spin_unlock_irqrestore(&dev->event_lock, flags);
2632
2633 return pending;
2634}
2635
Chris Wilson14667a42012-04-03 17:58:35 +01002636static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002637intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002638 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002639{
2640 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002641 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002643 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002644 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002645
Chris Wilson7d5e3792014-03-04 13:15:08 +00002646 if (intel_crtc_has_pending_flip(crtc)) {
2647 DRM_ERROR("pipe is still busy with an old pageflip\n");
2648 return -EBUSY;
2649 }
2650
Jesse Barnes79e53942008-11-07 14:24:08 -08002651 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002652 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002653 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002654 return 0;
2655 }
2656
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002657 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002658 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2659 plane_name(intel_crtc->plane),
2660 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002661 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002662 }
2663
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002664 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002665 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002666 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002667 NULL);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002668 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002669 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002670 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002671 return ret;
2672 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002673
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002674 /*
2675 * Update pipe size and adjust fitter if needed: the reason for this is
2676 * that in compute_mode_changes we check the native mode (not the pfit
2677 * mode) to see if we can flip rather than do a full mode set. In the
2678 * fastboot case, we'll flip, but if we don't update the pipesrc and
2679 * pfit state, we'll end up with a big fb scanned out into the wrong
2680 * sized surface.
2681 *
2682 * To fix this properly, we need to hoist the checks up into
2683 * compute_mode_changes (or above), check the actual pfit state and
2684 * whether the platform allows pfit disable with pipe active, and only
2685 * then update the pipesrc and pfit state, even on the flip path.
2686 */
Jani Nikulad330a952014-01-21 11:24:25 +02002687 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002688 const struct drm_display_mode *adjusted_mode =
2689 &intel_crtc->config.adjusted_mode;
2690
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002691 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002692 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2693 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002694 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002695 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2696 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2697 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2698 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2699 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2700 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002701 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2702 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002703 }
2704
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002705 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002706
Matt Roperf4510a22014-04-01 15:22:40 -07002707 old_fb = crtc->primary->fb;
2708 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002709 crtc->x = x;
2710 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002711
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002712 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002713 if (intel_crtc->active && old_fb != fb)
2714 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002715 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002716 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002717 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002718 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002719
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002720 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002721 intel_update_fbc(dev);
Rodrigo Vivi49065572013-07-11 18:45:05 -03002722 intel_edp_psr_update(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002723 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002724
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002725 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002726}
2727
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002728static void intel_fdi_normal_train(struct drm_crtc *crtc)
2729{
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp;
2735
2736 /* enable normal train */
2737 reg = FDI_TX_CTL(pipe);
2738 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002739 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002740 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2741 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002745 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002746 I915_WRITE(reg, temp);
2747
2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 if (HAS_PCH_CPT(dev)) {
2751 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2752 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2753 } else {
2754 temp &= ~FDI_LINK_TRAIN_NONE;
2755 temp |= FDI_LINK_TRAIN_NONE;
2756 }
2757 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2758
2759 /* wait one idle pattern time */
2760 POSTING_READ(reg);
2761 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002762
2763 /* IVB wants error correction enabled */
2764 if (IS_IVYBRIDGE(dev))
2765 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2766 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002767}
2768
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002769static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002770{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002771 return crtc->base.enabled && crtc->active &&
2772 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002773}
2774
Daniel Vetter01a415f2012-10-27 15:58:40 +02002775static void ivb_modeset_global_resources(struct drm_device *dev)
2776{
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_crtc *pipe_B_crtc =
2779 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2780 struct intel_crtc *pipe_C_crtc =
2781 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2782 uint32_t temp;
2783
Daniel Vetter1e833f42013-02-19 22:31:57 +01002784 /*
2785 * When everything is off disable fdi C so that we could enable fdi B
2786 * with all lanes. Note that we don't care about enabled pipes without
2787 * an enabled pch encoder.
2788 */
2789 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2790 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002791 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2792 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2793
2794 temp = I915_READ(SOUTH_CHICKEN1);
2795 temp &= ~FDI_BC_BIFURCATION_SELECT;
2796 DRM_DEBUG_KMS("disabling fdi C rx\n");
2797 I915_WRITE(SOUTH_CHICKEN1, temp);
2798 }
2799}
2800
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002801/* The FDI link training functions for ILK/Ibexpeak. */
2802static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2803{
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002808 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002809
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002810 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002811 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002812
Adam Jacksone1a44742010-06-25 15:32:14 -04002813 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2814 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002815 reg = FDI_RX_IMR(pipe);
2816 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002817 temp &= ~FDI_RX_SYMBOL_LOCK;
2818 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002819 I915_WRITE(reg, temp);
2820 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002821 udelay(150);
2822
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002823 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002826 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2827 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002828 temp &= ~FDI_LINK_TRAIN_NONE;
2829 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002830 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002831
Chris Wilson5eddb702010-09-11 13:48:45 +01002832 reg = FDI_RX_CTL(pipe);
2833 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002834 temp &= ~FDI_LINK_TRAIN_NONE;
2835 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002836 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2837
2838 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002839 udelay(150);
2840
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002841 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002842 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2843 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2844 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002845
Chris Wilson5eddb702010-09-11 13:48:45 +01002846 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002847 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002848 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002849 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2850
2851 if ((temp & FDI_RX_BIT_LOCK)) {
2852 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002853 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002854 break;
2855 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002856 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002857 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002858 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002859
2860 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002861 reg = FDI_TX_CTL(pipe);
2862 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002865 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002866
Chris Wilson5eddb702010-09-11 13:48:45 +01002867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002869 temp &= ~FDI_LINK_TRAIN_NONE;
2870 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002871 I915_WRITE(reg, temp);
2872
2873 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002874 udelay(150);
2875
Chris Wilson5eddb702010-09-11 13:48:45 +01002876 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002877 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002878 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002879 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2880
2881 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002882 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002883 DRM_DEBUG_KMS("FDI train 2 done.\n");
2884 break;
2885 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002886 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002887 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002888 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002889
2890 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002891
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002892}
2893
Akshay Joshi0206e352011-08-16 15:34:10 -04002894static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002895 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2896 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2897 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2898 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2899};
2900
2901/* The FDI link training functions for SNB/Cougarpoint. */
2902static void gen6_fdi_link_train(struct drm_crtc *crtc)
2903{
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002908 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002909
Adam Jacksone1a44742010-06-25 15:32:14 -04002910 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2911 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002912 reg = FDI_RX_IMR(pipe);
2913 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002914 temp &= ~FDI_RX_SYMBOL_LOCK;
2915 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002916 I915_WRITE(reg, temp);
2917
2918 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002919 udelay(150);
2920
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002921 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002922 reg = FDI_TX_CTL(pipe);
2923 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002924 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2925 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002926 temp &= ~FDI_LINK_TRAIN_NONE;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1;
2928 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2929 /* SNB-B */
2930 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002931 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002932
Daniel Vetterd74cf322012-10-26 10:58:13 +02002933 I915_WRITE(FDI_RX_MISC(pipe),
2934 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2935
Chris Wilson5eddb702010-09-11 13:48:45 +01002936 reg = FDI_RX_CTL(pipe);
2937 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002938 if (HAS_PCH_CPT(dev)) {
2939 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2941 } else {
2942 temp &= ~FDI_LINK_TRAIN_NONE;
2943 temp |= FDI_LINK_TRAIN_PATTERN_1;
2944 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002945 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2946
2947 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002948 udelay(150);
2949
Akshay Joshi0206e352011-08-16 15:34:10 -04002950 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002951 reg = FDI_TX_CTL(pipe);
2952 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002953 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2954 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002958 udelay(500);
2959
Sean Paulfa37d392012-03-02 12:53:39 -05002960 for (retry = 0; retry < 5; retry++) {
2961 reg = FDI_RX_IIR(pipe);
2962 temp = I915_READ(reg);
2963 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2964 if (temp & FDI_RX_BIT_LOCK) {
2965 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2966 DRM_DEBUG_KMS("FDI train 1 done.\n");
2967 break;
2968 }
2969 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002970 }
Sean Paulfa37d392012-03-02 12:53:39 -05002971 if (retry < 5)
2972 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002973 }
2974 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002975 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002976
2977 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002978 reg = FDI_TX_CTL(pipe);
2979 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002980 temp &= ~FDI_LINK_TRAIN_NONE;
2981 temp |= FDI_LINK_TRAIN_PATTERN_2;
2982 if (IS_GEN6(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2984 /* SNB-B */
2985 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2986 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002987 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002988
Chris Wilson5eddb702010-09-11 13:48:45 +01002989 reg = FDI_RX_CTL(pipe);
2990 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002991 if (HAS_PCH_CPT(dev)) {
2992 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2993 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2994 } else {
2995 temp &= ~FDI_LINK_TRAIN_NONE;
2996 temp |= FDI_LINK_TRAIN_PATTERN_2;
2997 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002998 I915_WRITE(reg, temp);
2999
3000 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003001 udelay(150);
3002
Akshay Joshi0206e352011-08-16 15:34:10 -04003003 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003004 reg = FDI_TX_CTL(pipe);
3005 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003006 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3007 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003008 I915_WRITE(reg, temp);
3009
3010 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003011 udelay(500);
3012
Sean Paulfa37d392012-03-02 12:53:39 -05003013 for (retry = 0; retry < 5; retry++) {
3014 reg = FDI_RX_IIR(pipe);
3015 temp = I915_READ(reg);
3016 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3017 if (temp & FDI_RX_SYMBOL_LOCK) {
3018 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3019 DRM_DEBUG_KMS("FDI train 2 done.\n");
3020 break;
3021 }
3022 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003023 }
Sean Paulfa37d392012-03-02 12:53:39 -05003024 if (retry < 5)
3025 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003026 }
3027 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003028 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003029
3030 DRM_DEBUG_KMS("FDI train done.\n");
3031}
3032
Jesse Barnes357555c2011-04-28 15:09:55 -07003033/* Manual link training for Ivy Bridge A0 parts */
3034static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3035{
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003040 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003041
3042 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3043 for train result */
3044 reg = FDI_RX_IMR(pipe);
3045 temp = I915_READ(reg);
3046 temp &= ~FDI_RX_SYMBOL_LOCK;
3047 temp &= ~FDI_RX_BIT_LOCK;
3048 I915_WRITE(reg, temp);
3049
3050 POSTING_READ(reg);
3051 udelay(150);
3052
Daniel Vetter01a415f2012-10-27 15:58:40 +02003053 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3054 I915_READ(FDI_RX_IIR(pipe)));
3055
Jesse Barnes139ccd32013-08-19 11:04:55 -07003056 /* Try each vswing and preemphasis setting twice before moving on */
3057 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3058 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003059 reg = FDI_TX_CTL(pipe);
3060 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003061 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3062 temp &= ~FDI_TX_ENABLE;
3063 I915_WRITE(reg, temp);
3064
3065 reg = FDI_RX_CTL(pipe);
3066 temp = I915_READ(reg);
3067 temp &= ~FDI_LINK_TRAIN_AUTO;
3068 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3069 temp &= ~FDI_RX_ENABLE;
3070 I915_WRITE(reg, temp);
3071
3072 /* enable CPU FDI TX and PCH FDI RX */
3073 reg = FDI_TX_CTL(pipe);
3074 temp = I915_READ(reg);
3075 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3076 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3077 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003078 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003079 temp |= snb_b_fdi_train_param[j/2];
3080 temp |= FDI_COMPOSITE_SYNC;
3081 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3082
3083 I915_WRITE(FDI_RX_MISC(pipe),
3084 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3085
3086 reg = FDI_RX_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3089 temp |= FDI_COMPOSITE_SYNC;
3090 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3091
3092 POSTING_READ(reg);
3093 udelay(1); /* should be 0.5us */
3094
3095 for (i = 0; i < 4; i++) {
3096 reg = FDI_RX_IIR(pipe);
3097 temp = I915_READ(reg);
3098 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3099
3100 if (temp & FDI_RX_BIT_LOCK ||
3101 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3102 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3103 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3104 i);
3105 break;
3106 }
3107 udelay(1); /* should be 0.5us */
3108 }
3109 if (i == 4) {
3110 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3111 continue;
3112 }
3113
3114 /* Train 2 */
3115 reg = FDI_TX_CTL(pipe);
3116 temp = I915_READ(reg);
3117 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3118 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3119 I915_WRITE(reg, temp);
3120
3121 reg = FDI_RX_CTL(pipe);
3122 temp = I915_READ(reg);
3123 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3124 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003125 I915_WRITE(reg, temp);
3126
3127 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003128 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003129
Jesse Barnes139ccd32013-08-19 11:04:55 -07003130 for (i = 0; i < 4; i++) {
3131 reg = FDI_RX_IIR(pipe);
3132 temp = I915_READ(reg);
3133 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003134
Jesse Barnes139ccd32013-08-19 11:04:55 -07003135 if (temp & FDI_RX_SYMBOL_LOCK ||
3136 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3137 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3138 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3139 i);
3140 goto train_done;
3141 }
3142 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003143 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003144 if (i == 4)
3145 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003146 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003147
Jesse Barnes139ccd32013-08-19 11:04:55 -07003148train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003149 DRM_DEBUG_KMS("FDI train done.\n");
3150}
3151
Daniel Vetter88cefb62012-08-12 19:27:14 +02003152static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003153{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003154 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003155 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003156 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003157 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003158
Jesse Barnesc64e3112010-09-10 11:27:03 -07003159
Jesse Barnes0e23b992010-09-10 11:10:00 -07003160 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003161 reg = FDI_RX_CTL(pipe);
3162 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003163 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3164 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003165 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003166 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3167
3168 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003169 udelay(200);
3170
3171 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003172 temp = I915_READ(reg);
3173 I915_WRITE(reg, temp | FDI_PCDCLK);
3174
3175 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003176 udelay(200);
3177
Paulo Zanoni20749732012-11-23 15:30:38 -02003178 /* Enable CPU FDI TX PLL, always on for Ironlake */
3179 reg = FDI_TX_CTL(pipe);
3180 temp = I915_READ(reg);
3181 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3182 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003183
Paulo Zanoni20749732012-11-23 15:30:38 -02003184 POSTING_READ(reg);
3185 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003186 }
3187}
3188
Daniel Vetter88cefb62012-08-12 19:27:14 +02003189static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3190{
3191 struct drm_device *dev = intel_crtc->base.dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp;
3195
3196 /* Switch from PCDclk to Rawclk */
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3200
3201 /* Disable CPU FDI TX PLL */
3202 reg = FDI_TX_CTL(pipe);
3203 temp = I915_READ(reg);
3204 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3205
3206 POSTING_READ(reg);
3207 udelay(100);
3208
3209 reg = FDI_RX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3212
3213 /* Wait for the clocks to turn off. */
3214 POSTING_READ(reg);
3215 udelay(100);
3216}
3217
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003218static void ironlake_fdi_disable(struct drm_crtc *crtc)
3219{
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223 int pipe = intel_crtc->pipe;
3224 u32 reg, temp;
3225
3226 /* disable CPU FDI tx and PCH FDI rx */
3227 reg = FDI_TX_CTL(pipe);
3228 temp = I915_READ(reg);
3229 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3230 POSTING_READ(reg);
3231
3232 reg = FDI_RX_CTL(pipe);
3233 temp = I915_READ(reg);
3234 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003235 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003236 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3237
3238 POSTING_READ(reg);
3239 udelay(100);
3240
3241 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003242 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003243 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003244
3245 /* still set train pattern 1 */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 temp &= ~FDI_LINK_TRAIN_NONE;
3249 temp |= FDI_LINK_TRAIN_PATTERN_1;
3250 I915_WRITE(reg, temp);
3251
3252 reg = FDI_RX_CTL(pipe);
3253 temp = I915_READ(reg);
3254 if (HAS_PCH_CPT(dev)) {
3255 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3256 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3257 } else {
3258 temp &= ~FDI_LINK_TRAIN_NONE;
3259 temp |= FDI_LINK_TRAIN_PATTERN_1;
3260 }
3261 /* BPC in FDI rx is consistent with that in PIPECONF */
3262 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003263 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003264 I915_WRITE(reg, temp);
3265
3266 POSTING_READ(reg);
3267 udelay(100);
3268}
3269
Chris Wilson5dce5b932014-01-20 10:17:36 +00003270bool intel_has_pending_fb_unpin(struct drm_device *dev)
3271{
3272 struct intel_crtc *crtc;
3273
3274 /* Note that we don't need to be called with mode_config.lock here
3275 * as our list of CRTC objects is static for the lifetime of the
3276 * device and so cannot disappear as we iterate. Similarly, we can
3277 * happily treat the predicates as racy, atomic checks as userspace
3278 * cannot claim and pin a new fb without at least acquring the
3279 * struct_mutex and so serialising with us.
3280 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003281 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003282 if (atomic_read(&crtc->unpin_work_count) == 0)
3283 continue;
3284
3285 if (crtc->unpin_work)
3286 intel_wait_for_vblank(dev, crtc->pipe);
3287
3288 return true;
3289 }
3290
3291 return false;
3292}
3293
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003294static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3295{
Chris Wilson0f911282012-04-17 10:05:38 +01003296 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003297 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003298
Matt Roperf4510a22014-04-01 15:22:40 -07003299 if (crtc->primary->fb == NULL)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003300 return;
3301
Daniel Vetter2c10d572012-12-20 21:24:07 +01003302 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3303
Daniel Vettereed6d672014-05-19 16:09:35 +02003304 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3305 !intel_crtc_has_pending_flip(crtc),
3306 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003307
Chris Wilson0f911282012-04-17 10:05:38 +01003308 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07003309 intel_finish_fb(crtc->primary->fb);
Chris Wilson0f911282012-04-17 10:05:38 +01003310 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003311}
3312
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003313/* Program iCLKIP clock to the desired frequency */
3314static void lpt_program_iclkip(struct drm_crtc *crtc)
3315{
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003318 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003319 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3320 u32 temp;
3321
Daniel Vetter09153002012-12-12 14:06:44 +01003322 mutex_lock(&dev_priv->dpio_lock);
3323
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003324 /* It is necessary to ungate the pixclk gate prior to programming
3325 * the divisors, and gate it back when it is done.
3326 */
3327 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3328
3329 /* Disable SSCCTL */
3330 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003331 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3332 SBI_SSCCTL_DISABLE,
3333 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003334
3335 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003336 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003337 auxdiv = 1;
3338 divsel = 0x41;
3339 phaseinc = 0x20;
3340 } else {
3341 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003342 * but the adjusted_mode->crtc_clock in in KHz. To get the
3343 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003344 * convert the virtual clock precision to KHz here for higher
3345 * precision.
3346 */
3347 u32 iclk_virtual_root_freq = 172800 * 1000;
3348 u32 iclk_pi_range = 64;
3349 u32 desired_divisor, msb_divisor_value, pi_value;
3350
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003351 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003352 msb_divisor_value = desired_divisor / iclk_pi_range;
3353 pi_value = desired_divisor % iclk_pi_range;
3354
3355 auxdiv = 0;
3356 divsel = msb_divisor_value - 2;
3357 phaseinc = pi_value;
3358 }
3359
3360 /* This should not happen with any sane values */
3361 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3362 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3363 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3364 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3365
3366 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003367 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003368 auxdiv,
3369 divsel,
3370 phasedir,
3371 phaseinc);
3372
3373 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003374 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003375 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3376 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3377 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3378 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3379 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3380 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003381 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003382
3383 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003384 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003385 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3386 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003387 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003388
3389 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003390 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003391 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003392 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003393
3394 /* Wait for initialization time */
3395 udelay(24);
3396
3397 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003398
3399 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003400}
3401
Daniel Vetter275f01b22013-05-03 11:49:47 +02003402static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3403 enum pipe pch_transcoder)
3404{
3405 struct drm_device *dev = crtc->base.dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3408
3409 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3410 I915_READ(HTOTAL(cpu_transcoder)));
3411 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3412 I915_READ(HBLANK(cpu_transcoder)));
3413 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3414 I915_READ(HSYNC(cpu_transcoder)));
3415
3416 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3417 I915_READ(VTOTAL(cpu_transcoder)));
3418 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3419 I915_READ(VBLANK(cpu_transcoder)));
3420 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3421 I915_READ(VSYNC(cpu_transcoder)));
3422 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3423 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3424}
3425
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003426static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3427{
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 uint32_t temp;
3430
3431 temp = I915_READ(SOUTH_CHICKEN1);
3432 if (temp & FDI_BC_BIFURCATION_SELECT)
3433 return;
3434
3435 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3436 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3437
3438 temp |= FDI_BC_BIFURCATION_SELECT;
3439 DRM_DEBUG_KMS("enabling fdi C rx\n");
3440 I915_WRITE(SOUTH_CHICKEN1, temp);
3441 POSTING_READ(SOUTH_CHICKEN1);
3442}
3443
3444static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3445{
3446 struct drm_device *dev = intel_crtc->base.dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448
3449 switch (intel_crtc->pipe) {
3450 case PIPE_A:
3451 break;
3452 case PIPE_B:
3453 if (intel_crtc->config.fdi_lanes > 2)
3454 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3455 else
3456 cpt_enable_fdi_bc_bifurcation(dev);
3457
3458 break;
3459 case PIPE_C:
3460 cpt_enable_fdi_bc_bifurcation(dev);
3461
3462 break;
3463 default:
3464 BUG();
3465 }
3466}
3467
Jesse Barnesf67a5592011-01-05 10:31:48 -08003468/*
3469 * Enable PCH resources required for PCH ports:
3470 * - PCH PLLs
3471 * - FDI training & RX/TX
3472 * - update transcoder timings
3473 * - DP transcoding bits
3474 * - transcoder
3475 */
3476static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003477{
3478 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003482 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003483
Daniel Vetterab9412b2013-05-03 11:49:46 +02003484 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003485
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003486 if (IS_IVYBRIDGE(dev))
3487 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3488
Daniel Vettercd986ab2012-10-26 10:58:12 +02003489 /* Write the TU size bits before fdi link training, so that error
3490 * detection works. */
3491 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3492 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3493
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003494 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003495 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003496
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003497 /* We need to program the right clock selection before writing the pixel
3498 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003499 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003500 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003501
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003502 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003503 temp |= TRANS_DPLL_ENABLE(pipe);
3504 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003505 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003506 temp |= sel;
3507 else
3508 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003509 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003510 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003511
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003512 /* XXX: pch pll's can be enabled any time before we enable the PCH
3513 * transcoder, and we actually should do this to not upset any PCH
3514 * transcoder that already use the clock when we share it.
3515 *
3516 * Note that enable_shared_dpll tries to do the right thing, but
3517 * get_shared_dpll unconditionally resets the pll - we need that to have
3518 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003519 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003520
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003521 /* set transcoder timing, panel must allow it */
3522 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003523 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003524
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003525 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003526
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003527 /* For PCH DP, enable TRANS_DP_CTL */
3528 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003529 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3530 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003531 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003532 reg = TRANS_DP_CTL(pipe);
3533 temp = I915_READ(reg);
3534 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003535 TRANS_DP_SYNC_MASK |
3536 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003537 temp |= (TRANS_DP_OUTPUT_ENABLE |
3538 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003539 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003540
3541 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003542 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003543 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003544 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003545
3546 switch (intel_trans_dp_port_sel(crtc)) {
3547 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003548 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003549 break;
3550 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003551 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003552 break;
3553 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003554 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003555 break;
3556 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003557 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003558 }
3559
Chris Wilson5eddb702010-09-11 13:48:45 +01003560 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003561 }
3562
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003563 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003564}
3565
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003566static void lpt_pch_enable(struct drm_crtc *crtc)
3567{
3568 struct drm_device *dev = crtc->dev;
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003571 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003572
Daniel Vetterab9412b2013-05-03 11:49:46 +02003573 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003574
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003575 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003576
Paulo Zanoni0540e482012-10-31 18:12:40 -02003577 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003578 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003579
Paulo Zanoni937bb612012-10-31 18:12:47 -02003580 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003581}
3582
Daniel Vettere2b78262013-06-07 23:10:03 +02003583static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003584{
Daniel Vettere2b78262013-06-07 23:10:03 +02003585 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003586
3587 if (pll == NULL)
3588 return;
3589
3590 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003591 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003592 return;
3593 }
3594
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003595 if (--pll->refcount == 0) {
3596 WARN_ON(pll->on);
3597 WARN_ON(pll->active);
3598 }
3599
Daniel Vettera43f6e02013-06-07 23:10:32 +02003600 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003601}
3602
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003603static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003604{
Daniel Vettere2b78262013-06-07 23:10:03 +02003605 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3606 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3607 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003608
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003609 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003610 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3611 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003612 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003613 }
3614
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003615 if (HAS_PCH_IBX(dev_priv->dev)) {
3616 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003617 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003618 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003619
Daniel Vetter46edb022013-06-05 13:34:12 +02003620 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3621 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003622
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003623 WARN_ON(pll->refcount);
3624
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003625 goto found;
3626 }
3627
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003628 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3629 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003630
3631 /* Only want to check enabled timings first */
3632 if (pll->refcount == 0)
3633 continue;
3634
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003635 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3636 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003637 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003638 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003639 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003640
3641 goto found;
3642 }
3643 }
3644
3645 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003646 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3647 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003648 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003649 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3650 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003651 goto found;
3652 }
3653 }
3654
3655 return NULL;
3656
3657found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003658 if (pll->refcount == 0)
3659 pll->hw_state = crtc->config.dpll_hw_state;
3660
Daniel Vettera43f6e02013-06-07 23:10:32 +02003661 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003662 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3663 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003664
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003665 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003666
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003667 return pll;
3668}
3669
Daniel Vettera1520312013-05-03 11:49:50 +02003670static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003671{
3672 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003673 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003674 u32 temp;
3675
3676 temp = I915_READ(dslreg);
3677 udelay(500);
3678 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003679 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003680 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003681 }
3682}
3683
Jesse Barnesb074cec2013-04-25 12:55:02 -07003684static void ironlake_pfit_enable(struct intel_crtc *crtc)
3685{
3686 struct drm_device *dev = crtc->base.dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 int pipe = crtc->pipe;
3689
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003690 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003691 /* Force use of hard-coded filter coefficients
3692 * as some pre-programmed values are broken,
3693 * e.g. x201.
3694 */
3695 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3696 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3697 PF_PIPE_SEL_IVB(pipe));
3698 else
3699 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3700 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3701 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003702 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003703}
3704
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003705static void intel_enable_planes(struct drm_crtc *crtc)
3706{
3707 struct drm_device *dev = crtc->dev;
3708 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003709 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003710 struct intel_plane *intel_plane;
3711
Matt Roperaf2b6532014-04-01 15:22:32 -07003712 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3713 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003714 if (intel_plane->pipe == pipe)
3715 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003716 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003717}
3718
3719static void intel_disable_planes(struct drm_crtc *crtc)
3720{
3721 struct drm_device *dev = crtc->dev;
3722 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003723 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003724 struct intel_plane *intel_plane;
3725
Matt Roperaf2b6532014-04-01 15:22:32 -07003726 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3727 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003728 if (intel_plane->pipe == pipe)
3729 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003730 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003731}
3732
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003733void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003734{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003737
3738 if (!crtc->config.ips_enabled)
3739 return;
3740
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003741 /* We can only enable IPS after we enable a plane and wait for a vblank */
3742 intel_wait_for_vblank(dev, crtc->pipe);
3743
Paulo Zanonid77e4532013-09-24 13:52:55 -03003744 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003745 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003746 mutex_lock(&dev_priv->rps.hw_lock);
3747 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3748 mutex_unlock(&dev_priv->rps.hw_lock);
3749 /* Quoting Art Runyan: "its not safe to expect any particular
3750 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003751 * mailbox." Moreover, the mailbox may return a bogus state,
3752 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003753 */
3754 } else {
3755 I915_WRITE(IPS_CTL, IPS_ENABLE);
3756 /* The bit only becomes 1 in the next vblank, so this wait here
3757 * is essentially intel_wait_for_vblank. If we don't have this
3758 * and don't wait for vblanks until the end of crtc_enable, then
3759 * the HW state readout code will complain that the expected
3760 * IPS_CTL value is not the one we read. */
3761 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3762 DRM_ERROR("Timed out waiting for IPS enable\n");
3763 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003764}
3765
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003766void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003767{
3768 struct drm_device *dev = crtc->base.dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770
3771 if (!crtc->config.ips_enabled)
3772 return;
3773
3774 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003775 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003776 mutex_lock(&dev_priv->rps.hw_lock);
3777 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3778 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003779 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3780 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3781 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003782 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003783 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003784 POSTING_READ(IPS_CTL);
3785 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003786
3787 /* We need to wait for a vblank before we can disable the plane. */
3788 intel_wait_for_vblank(dev, crtc->pipe);
3789}
3790
3791/** Loads the palette/gamma unit for the CRTC with the prepared values */
3792static void intel_crtc_load_lut(struct drm_crtc *crtc)
3793{
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 enum pipe pipe = intel_crtc->pipe;
3798 int palreg = PALETTE(pipe);
3799 int i;
3800 bool reenable_ips = false;
3801
3802 /* The clocks have to be on to load the palette. */
3803 if (!crtc->enabled || !intel_crtc->active)
3804 return;
3805
3806 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3807 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3808 assert_dsi_pll_enabled(dev_priv);
3809 else
3810 assert_pll_enabled(dev_priv, pipe);
3811 }
3812
3813 /* use legacy palette for Ironlake */
3814 if (HAS_PCH_SPLIT(dev))
3815 palreg = LGC_PALETTE(pipe);
3816
3817 /* Workaround : Do not read or write the pipe palette/gamma data while
3818 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3819 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003820 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003821 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3822 GAMMA_MODE_MODE_SPLIT)) {
3823 hsw_disable_ips(intel_crtc);
3824 reenable_ips = true;
3825 }
3826
3827 for (i = 0; i < 256; i++) {
3828 I915_WRITE(palreg + 4 * i,
3829 (intel_crtc->lut_r[i] << 16) |
3830 (intel_crtc->lut_g[i] << 8) |
3831 intel_crtc->lut_b[i]);
3832 }
3833
3834 if (reenable_ips)
3835 hsw_enable_ips(intel_crtc);
3836}
3837
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003838static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3839{
3840 if (!enable && intel_crtc->overlay) {
3841 struct drm_device *dev = intel_crtc->base.dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843
3844 mutex_lock(&dev->struct_mutex);
3845 dev_priv->mm.interruptible = false;
3846 (void) intel_overlay_switch_off(intel_crtc->overlay);
3847 dev_priv->mm.interruptible = true;
3848 mutex_unlock(&dev->struct_mutex);
3849 }
3850
3851 /* Let userspace switch the overlay on again. In most cases userspace
3852 * has to recompute where to put it anyway.
3853 */
3854}
3855
3856/**
3857 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3858 * cursor plane briefly if not already running after enabling the display
3859 * plane.
3860 * This workaround avoids occasional blank screens when self refresh is
3861 * enabled.
3862 */
3863static void
3864g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3865{
3866 u32 cntl = I915_READ(CURCNTR(pipe));
3867
3868 if ((cntl & CURSOR_MODE) == 0) {
3869 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3870
3871 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3872 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3873 intel_wait_for_vblank(dev_priv->dev, pipe);
3874 I915_WRITE(CURCNTR(pipe), cntl);
3875 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3876 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3877 }
3878}
3879
3880static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003881{
3882 struct drm_device *dev = crtc->dev;
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3885 int pipe = intel_crtc->pipe;
3886 int plane = intel_crtc->plane;
3887
3888 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3889 intel_enable_planes(crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003890 /* The fixup needs to happen before cursor is enabled */
3891 if (IS_G4X(dev))
3892 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003893 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003894 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003895
3896 hsw_enable_ips(intel_crtc);
3897
3898 mutex_lock(&dev->struct_mutex);
3899 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02003900 intel_edp_psr_update(dev);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003901 mutex_unlock(&dev->struct_mutex);
3902}
3903
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003904static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003905{
3906 struct drm_device *dev = crtc->dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909 int pipe = intel_crtc->pipe;
3910 int plane = intel_crtc->plane;
3911
3912 intel_crtc_wait_for_pending_flips(crtc);
Daniel Vetter87b6b102014-05-15 15:33:46 +02003913 drm_crtc_vblank_off(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003914
3915 if (dev_priv->fbc.plane == plane)
3916 intel_disable_fbc(dev);
3917
3918 hsw_disable_ips(intel_crtc);
3919
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003920 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003921 intel_crtc_update_cursor(crtc, false);
3922 intel_disable_planes(crtc);
3923 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3924}
3925
Jesse Barnesf67a5592011-01-05 10:31:48 -08003926static void ironlake_crtc_enable(struct drm_crtc *crtc)
3927{
3928 struct drm_device *dev = crtc->dev;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003931 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003932 int pipe = intel_crtc->pipe;
Daniel Vetter29407aa2014-04-24 23:55:08 +02003933 enum plane plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003934
Daniel Vetter08a48462012-07-02 11:43:47 +02003935 WARN_ON(!crtc->enabled);
3936
Jesse Barnesf67a5592011-01-05 10:31:48 -08003937 if (intel_crtc->active)
3938 return;
3939
Daniel Vetterb14b1052014-04-24 23:55:13 +02003940 if (intel_crtc->config.has_pch_encoder)
3941 intel_prepare_shared_dpll(intel_crtc);
3942
Daniel Vetter29407aa2014-04-24 23:55:08 +02003943 if (intel_crtc->config.has_dp_encoder)
3944 intel_dp_set_m_n(intel_crtc);
3945
3946 intel_set_pipe_timings(intel_crtc);
3947
3948 if (intel_crtc->config.has_pch_encoder) {
3949 intel_cpu_transcoder_set_m_n(intel_crtc,
3950 &intel_crtc->config.fdi_m_n);
3951 }
3952
3953 ironlake_set_pipeconf(crtc);
3954
3955 /* Set up the display plane register */
3956 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3957 POSTING_READ(DSPCNTR(plane));
3958
3959 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3960 crtc->x, crtc->y);
3961
Jesse Barnesf67a5592011-01-05 10:31:48 -08003962 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003963
3964 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3965 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3966
Daniel Vetterf6736a12013-06-05 13:34:30 +02003967 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003968 if (encoder->pre_enable)
3969 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003970
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003971 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003972 /* Note: FDI PLL enabling _must_ be done before we enable the
3973 * cpu pipes, hence this is separate from all the other fdi/pch
3974 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003975 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003976 } else {
3977 assert_fdi_tx_disabled(dev_priv, pipe);
3978 assert_fdi_rx_disabled(dev_priv, pipe);
3979 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003980
Jesse Barnesb074cec2013-04-25 12:55:02 -07003981 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003982
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003983 /*
3984 * On ILK+ LUT must be loaded before the pipe is running but with
3985 * clocks enabled
3986 */
3987 intel_crtc_load_lut(crtc);
3988
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003989 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02003990 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003991
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003992 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003993 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003994
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003995 for_each_encoder_on_crtc(dev, crtc, encoder)
3996 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003997
3998 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02003999 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004000
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004001 intel_crtc_enable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004002
Daniel Vetter87b6b102014-05-15 15:33:46 +02004003 drm_crtc_vblank_on(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004004}
4005
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004006/* IPS only exists on ULT machines and is tied to pipe A. */
4007static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4008{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004009 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004010}
4011
Paulo Zanonie4916942013-09-20 16:21:19 -03004012/*
4013 * This implements the workaround described in the "notes" section of the mode
4014 * set sequence documentation. When going from no pipes or single pipe to
4015 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4016 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4017 */
4018static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4019{
4020 struct drm_device *dev = crtc->base.dev;
4021 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4022
4023 /* We want to get the other_active_crtc only if there's only 1 other
4024 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004025 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004026 if (!crtc_it->active || crtc_it == crtc)
4027 continue;
4028
4029 if (other_active_crtc)
4030 return;
4031
4032 other_active_crtc = crtc_it;
4033 }
4034 if (!other_active_crtc)
4035 return;
4036
4037 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4038 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4039}
4040
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004041static void haswell_crtc_enable(struct drm_crtc *crtc)
4042{
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046 struct intel_encoder *encoder;
4047 int pipe = intel_crtc->pipe;
Daniel Vetter229fca92014-04-24 23:55:09 +02004048 enum plane plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004049
4050 WARN_ON(!crtc->enabled);
4051
4052 if (intel_crtc->active)
4053 return;
4054
Daniel Vetter229fca92014-04-24 23:55:09 +02004055 if (intel_crtc->config.has_dp_encoder)
4056 intel_dp_set_m_n(intel_crtc);
4057
4058 intel_set_pipe_timings(intel_crtc);
4059
4060 if (intel_crtc->config.has_pch_encoder) {
4061 intel_cpu_transcoder_set_m_n(intel_crtc,
4062 &intel_crtc->config.fdi_m_n);
4063 }
4064
4065 haswell_set_pipeconf(crtc);
4066
4067 intel_set_pipe_csc(crtc);
4068
4069 /* Set up the display plane register */
4070 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4071 POSTING_READ(DSPCNTR(plane));
4072
4073 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4074 crtc->x, crtc->y);
4075
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004076 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004077
4078 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4079 if (intel_crtc->config.has_pch_encoder)
4080 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4081
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004082 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02004083 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004084
4085 for_each_encoder_on_crtc(dev, crtc, encoder)
4086 if (encoder->pre_enable)
4087 encoder->pre_enable(encoder);
4088
Paulo Zanoni1f544382012-10-24 11:32:00 -02004089 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004090
Jesse Barnesb074cec2013-04-25 12:55:02 -07004091 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004092
4093 /*
4094 * On ILK+ LUT must be loaded before the pipe is running but with
4095 * clocks enabled
4096 */
4097 intel_crtc_load_lut(crtc);
4098
Paulo Zanoni1f544382012-10-24 11:32:00 -02004099 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004100 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004101
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004102 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004103 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004104
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004105 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004106 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004107
Jani Nikula8807e552013-08-30 19:40:32 +03004108 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004109 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004110 intel_opregion_notify_encoder(encoder, true);
4111 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004112
Paulo Zanonie4916942013-09-20 16:21:19 -03004113 /* If we change the relative order between pipe/planes enabling, we need
4114 * to change the workaround. */
4115 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004116 intel_crtc_enable_planes(crtc);
Ville Syrjäläf2752282014-02-19 21:29:49 +02004117
Daniel Vetter87b6b102014-05-15 15:33:46 +02004118 drm_crtc_vblank_on(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004119}
4120
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004121static void ironlake_pfit_disable(struct intel_crtc *crtc)
4122{
4123 struct drm_device *dev = crtc->base.dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 int pipe = crtc->pipe;
4126
4127 /* To avoid upsetting the power well on haswell only disable the pfit if
4128 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004129 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004130 I915_WRITE(PF_CTL(pipe), 0);
4131 I915_WRITE(PF_WIN_POS(pipe), 0);
4132 I915_WRITE(PF_WIN_SZ(pipe), 0);
4133 }
4134}
4135
Jesse Barnes6be4a602010-09-10 10:26:01 -07004136static void ironlake_crtc_disable(struct drm_crtc *crtc)
4137{
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004141 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004142 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004143 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004144
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004145 if (!intel_crtc->active)
4146 return;
4147
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004148 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004149
Daniel Vetterea9d7582012-07-10 10:42:52 +02004150 for_each_encoder_on_crtc(dev, crtc, encoder)
4151 encoder->disable(encoder);
4152
Daniel Vetterd925c592013-06-05 13:34:04 +02004153 if (intel_crtc->config.has_pch_encoder)
4154 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4155
Jesse Barnesb24e7172011-01-04 15:09:30 -08004156 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004157
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004158 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004159
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004160 for_each_encoder_on_crtc(dev, crtc, encoder)
4161 if (encoder->post_disable)
4162 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004163
Daniel Vetterd925c592013-06-05 13:34:04 +02004164 if (intel_crtc->config.has_pch_encoder) {
4165 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004166
Daniel Vetterd925c592013-06-05 13:34:04 +02004167 ironlake_disable_pch_transcoder(dev_priv, pipe);
4168 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004169
Daniel Vetterd925c592013-06-05 13:34:04 +02004170 if (HAS_PCH_CPT(dev)) {
4171 /* disable TRANS_DP_CTL */
4172 reg = TRANS_DP_CTL(pipe);
4173 temp = I915_READ(reg);
4174 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4175 TRANS_DP_PORT_SEL_MASK);
4176 temp |= TRANS_DP_PORT_SEL_NONE;
4177 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004178
Daniel Vetterd925c592013-06-05 13:34:04 +02004179 /* disable DPLL_SEL */
4180 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004181 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004182 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004183 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004184
4185 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004186 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004187
4188 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004189 }
4190
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004191 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004192 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004193
4194 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004195 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004196 intel_edp_psr_update(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004197 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004198}
4199
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004200static void haswell_crtc_disable(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205 struct intel_encoder *encoder;
4206 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004207 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004208
4209 if (!intel_crtc->active)
4210 return;
4211
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004212 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004213
Jani Nikula8807e552013-08-30 19:40:32 +03004214 for_each_encoder_on_crtc(dev, crtc, encoder) {
4215 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004216 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004217 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004218
Paulo Zanoni86642812013-04-12 17:57:57 -03004219 if (intel_crtc->config.has_pch_encoder)
4220 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004221 intel_disable_pipe(dev_priv, pipe);
4222
Paulo Zanoniad80a812012-10-24 16:06:19 -02004223 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004224
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004225 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004226
Paulo Zanoni1f544382012-10-24 11:32:00 -02004227 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004228
4229 for_each_encoder_on_crtc(dev, crtc, encoder)
4230 if (encoder->post_disable)
4231 encoder->post_disable(encoder);
4232
Daniel Vetter88adfff2013-03-28 10:42:01 +01004233 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004234 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004235 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004236 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004237 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004238
4239 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004240 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004241
4242 mutex_lock(&dev->struct_mutex);
4243 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004244 intel_edp_psr_update(dev);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004245 mutex_unlock(&dev->struct_mutex);
4246}
4247
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004248static void ironlake_crtc_off(struct drm_crtc *crtc)
4249{
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004251 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004252}
4253
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004254static void haswell_crtc_off(struct drm_crtc *crtc)
4255{
4256 intel_ddi_put_crtc_pll(crtc);
4257}
4258
Jesse Barnes2dd24552013-04-25 12:55:01 -07004259static void i9xx_pfit_enable(struct intel_crtc *crtc)
4260{
4261 struct drm_device *dev = crtc->base.dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_crtc_config *pipe_config = &crtc->config;
4264
Daniel Vetter328d8e82013-05-08 10:36:31 +02004265 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004266 return;
4267
Daniel Vetterc0b03412013-05-28 12:05:54 +02004268 /*
4269 * The panel fitter should only be adjusted whilst the pipe is disabled,
4270 * according to register description and PRM.
4271 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004272 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4273 assert_pipe_disabled(dev_priv, crtc->pipe);
4274
Jesse Barnesb074cec2013-04-25 12:55:02 -07004275 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4276 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004277
4278 /* Border color in case we don't scale up to the full screen. Black by
4279 * default, change to something else for debugging. */
4280 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004281}
4282
Imre Deak77d22dc2014-03-05 16:20:52 +02004283#define for_each_power_domain(domain, mask) \
4284 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4285 if ((1 << (domain)) & (mask))
4286
Imre Deak319be8a2014-03-04 19:22:57 +02004287enum intel_display_power_domain
4288intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004289{
Imre Deak319be8a2014-03-04 19:22:57 +02004290 struct drm_device *dev = intel_encoder->base.dev;
4291 struct intel_digital_port *intel_dig_port;
4292
4293 switch (intel_encoder->type) {
4294 case INTEL_OUTPUT_UNKNOWN:
4295 /* Only DDI platforms should ever use this output type */
4296 WARN_ON_ONCE(!HAS_DDI(dev));
4297 case INTEL_OUTPUT_DISPLAYPORT:
4298 case INTEL_OUTPUT_HDMI:
4299 case INTEL_OUTPUT_EDP:
4300 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4301 switch (intel_dig_port->port) {
4302 case PORT_A:
4303 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4304 case PORT_B:
4305 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4306 case PORT_C:
4307 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4308 case PORT_D:
4309 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4310 default:
4311 WARN_ON_ONCE(1);
4312 return POWER_DOMAIN_PORT_OTHER;
4313 }
4314 case INTEL_OUTPUT_ANALOG:
4315 return POWER_DOMAIN_PORT_CRT;
4316 case INTEL_OUTPUT_DSI:
4317 return POWER_DOMAIN_PORT_DSI;
4318 default:
4319 return POWER_DOMAIN_PORT_OTHER;
4320 }
4321}
4322
4323static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4324{
4325 struct drm_device *dev = crtc->dev;
4326 struct intel_encoder *intel_encoder;
4327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4328 enum pipe pipe = intel_crtc->pipe;
4329 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
Imre Deak77d22dc2014-03-05 16:20:52 +02004330 unsigned long mask;
4331 enum transcoder transcoder;
4332
4333 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4334
4335 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4336 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4337 if (pfit_enabled)
4338 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4339
Imre Deak319be8a2014-03-04 19:22:57 +02004340 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4341 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4342
Imre Deak77d22dc2014-03-05 16:20:52 +02004343 return mask;
4344}
4345
4346void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4347 bool enable)
4348{
4349 if (dev_priv->power_domains.init_power_on == enable)
4350 return;
4351
4352 if (enable)
4353 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4354 else
4355 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4356
4357 dev_priv->power_domains.init_power_on = enable;
4358}
4359
4360static void modeset_update_crtc_power_domains(struct drm_device *dev)
4361{
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4364 struct intel_crtc *crtc;
4365
4366 /*
4367 * First get all needed power domains, then put all unneeded, to avoid
4368 * any unnecessary toggling of the power wells.
4369 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004370 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004371 enum intel_display_power_domain domain;
4372
4373 if (!crtc->base.enabled)
4374 continue;
4375
Imre Deak319be8a2014-03-04 19:22:57 +02004376 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004377
4378 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4379 intel_display_power_get(dev_priv, domain);
4380 }
4381
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004382 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004383 enum intel_display_power_domain domain;
4384
4385 for_each_power_domain(domain, crtc->enabled_power_domains)
4386 intel_display_power_put(dev_priv, domain);
4387
4388 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4389 }
4390
4391 intel_display_set_init_power(dev_priv, false);
4392}
4393
Jesse Barnes586f49d2013-11-04 16:06:59 -08004394int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004395{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004396 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004397
Jesse Barnes586f49d2013-11-04 16:06:59 -08004398 /* Obtain SKU information */
4399 mutex_lock(&dev_priv->dpio_lock);
4400 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4401 CCK_FUSE_HPLL_FREQ_MASK;
4402 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004403
Jesse Barnes586f49d2013-11-04 16:06:59 -08004404 return vco_freq[hpll_freq];
Jesse Barnes30a970c2013-11-04 13:48:12 -08004405}
4406
4407/* Adjust CDclk dividers to allow high res or save power if possible */
4408static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4409{
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 u32 val, cmd;
4412
Imre Deakd60c4472014-03-27 17:45:10 +02004413 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4414 dev_priv->vlv_cdclk_freq = cdclk;
4415
Jesse Barnes30a970c2013-11-04 13:48:12 -08004416 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4417 cmd = 2;
4418 else if (cdclk == 266)
4419 cmd = 1;
4420 else
4421 cmd = 0;
4422
4423 mutex_lock(&dev_priv->rps.hw_lock);
4424 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4425 val &= ~DSPFREQGUAR_MASK;
4426 val |= (cmd << DSPFREQGUAR_SHIFT);
4427 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4428 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4429 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4430 50)) {
4431 DRM_ERROR("timed out waiting for CDclk change\n");
4432 }
4433 mutex_unlock(&dev_priv->rps.hw_lock);
4434
4435 if (cdclk == 400) {
4436 u32 divider, vco;
4437
4438 vco = valleyview_get_vco(dev_priv);
4439 divider = ((vco << 1) / cdclk) - 1;
4440
4441 mutex_lock(&dev_priv->dpio_lock);
4442 /* adjust cdclk divider */
4443 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4444 val &= ~0xf;
4445 val |= divider;
4446 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4447 mutex_unlock(&dev_priv->dpio_lock);
4448 }
4449
4450 mutex_lock(&dev_priv->dpio_lock);
4451 /* adjust self-refresh exit latency value */
4452 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4453 val &= ~0x7f;
4454
4455 /*
4456 * For high bandwidth configs, we set a higher latency in the bunit
4457 * so that the core display fetch happens in time to avoid underruns.
4458 */
4459 if (cdclk == 400)
4460 val |= 4500 / 250; /* 4.5 usec */
4461 else
4462 val |= 3000 / 250; /* 3.0 usec */
4463 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4464 mutex_unlock(&dev_priv->dpio_lock);
4465
4466 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4467 intel_i2c_reset(dev);
4468}
4469
Imre Deakd60c4472014-03-27 17:45:10 +02004470int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004471{
4472 int cur_cdclk, vco;
4473 int divider;
4474
4475 vco = valleyview_get_vco(dev_priv);
4476
4477 mutex_lock(&dev_priv->dpio_lock);
4478 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4479 mutex_unlock(&dev_priv->dpio_lock);
4480
4481 divider &= 0xf;
4482
4483 cur_cdclk = (vco << 1) / (divider + 1);
4484
4485 return cur_cdclk;
4486}
4487
4488static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4489 int max_pixclk)
4490{
Jesse Barnes30a970c2013-11-04 13:48:12 -08004491 /*
4492 * Really only a few cases to deal with, as only 4 CDclks are supported:
4493 * 200MHz
4494 * 267MHz
4495 * 320MHz
4496 * 400MHz
4497 * So we check to see whether we're above 90% of the lower bin and
4498 * adjust if needed.
4499 */
4500 if (max_pixclk > 288000) {
4501 return 400;
4502 } else if (max_pixclk > 240000) {
4503 return 320;
4504 } else
4505 return 266;
4506 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4507}
4508
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004509/* compute the max pixel clock for new configuration */
4510static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004511{
4512 struct drm_device *dev = dev_priv->dev;
4513 struct intel_crtc *intel_crtc;
4514 int max_pixclk = 0;
4515
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004516 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004517 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004518 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004519 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004520 }
4521
4522 return max_pixclk;
4523}
4524
4525static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004526 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004527{
4528 struct drm_i915_private *dev_priv = dev->dev_private;
4529 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004530 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004531
Imre Deakd60c4472014-03-27 17:45:10 +02004532 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4533 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004534 return;
4535
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004536 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004537 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004538 if (intel_crtc->base.enabled)
4539 *prepare_pipes |= (1 << intel_crtc->pipe);
4540}
4541
4542static void valleyview_modeset_global_resources(struct drm_device *dev)
4543{
4544 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004545 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004546 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4547
Imre Deakd60c4472014-03-27 17:45:10 +02004548 if (req_cdclk != dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004549 valleyview_set_cdclk(dev, req_cdclk);
Imre Deak77961eb2014-03-05 16:20:56 +02004550 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004551}
4552
Jesse Barnes89b667f2013-04-18 14:51:36 -07004553static void valleyview_crtc_enable(struct drm_crtc *crtc)
4554{
4555 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004556 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 struct intel_encoder *encoder;
4559 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004560 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004561 bool is_dsi;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004562 u32 dspcntr;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004563
4564 WARN_ON(!crtc->enabled);
4565
4566 if (intel_crtc->active)
4567 return;
4568
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004569 vlv_prepare_pll(intel_crtc);
4570
Daniel Vetter5b18e572014-04-24 23:55:06 +02004571 /* Set up the display plane register */
4572 dspcntr = DISPPLANE_GAMMA_ENABLE;
4573
4574 if (intel_crtc->config.has_dp_encoder)
4575 intel_dp_set_m_n(intel_crtc);
4576
4577 intel_set_pipe_timings(intel_crtc);
4578
4579 /* pipesrc and dspsize control the size that is scaled from,
4580 * which should always be the user's requested size.
4581 */
4582 I915_WRITE(DSPSIZE(plane),
4583 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4584 (intel_crtc->config.pipe_src_w - 1));
4585 I915_WRITE(DSPPOS(plane), 0);
4586
4587 i9xx_set_pipeconf(intel_crtc);
4588
4589 I915_WRITE(DSPCNTR(plane), dspcntr);
4590 POSTING_READ(DSPCNTR(plane));
4591
4592 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4593 crtc->x, crtc->y);
4594
Jesse Barnes89b667f2013-04-18 14:51:36 -07004595 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004596
Jesse Barnes89b667f2013-04-18 14:51:36 -07004597 for_each_encoder_on_crtc(dev, crtc, encoder)
4598 if (encoder->pre_pll_enable)
4599 encoder->pre_pll_enable(encoder);
4600
Jani Nikula23538ef2013-08-27 15:12:22 +03004601 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4602
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004603 if (!is_dsi) {
4604 if (IS_CHERRYVIEW(dev))
4605 chv_enable_pll(intel_crtc);
4606 else
4607 vlv_enable_pll(intel_crtc);
4608 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004609
4610 for_each_encoder_on_crtc(dev, crtc, encoder)
4611 if (encoder->pre_enable)
4612 encoder->pre_enable(encoder);
4613
Jesse Barnes2dd24552013-04-25 12:55:01 -07004614 i9xx_pfit_enable(intel_crtc);
4615
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004616 intel_crtc_load_lut(crtc);
4617
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004618 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004619 intel_enable_pipe(intel_crtc);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004620 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004621
Jani Nikula50049452013-07-30 12:20:32 +03004622 for_each_encoder_on_crtc(dev, crtc, encoder)
4623 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004624
4625 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004626
Daniel Vetter87b6b102014-05-15 15:33:46 +02004627 drm_crtc_vblank_on(crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004628}
4629
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004630static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4631{
4632 struct drm_device *dev = crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4636 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4637}
4638
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004639static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004640{
4641 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004642 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004644 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004645 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004646 int plane = intel_crtc->plane;
4647 u32 dspcntr;
Jesse Barnes79e53942008-11-07 14:24:08 -08004648
Daniel Vetter08a48462012-07-02 11:43:47 +02004649 WARN_ON(!crtc->enabled);
4650
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004651 if (intel_crtc->active)
4652 return;
4653
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004654 i9xx_set_pll_dividers(intel_crtc);
4655
Daniel Vetter5b18e572014-04-24 23:55:06 +02004656 /* Set up the display plane register */
4657 dspcntr = DISPPLANE_GAMMA_ENABLE;
4658
4659 if (pipe == 0)
4660 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4661 else
4662 dspcntr |= DISPPLANE_SEL_PIPE_B;
4663
4664 if (intel_crtc->config.has_dp_encoder)
4665 intel_dp_set_m_n(intel_crtc);
4666
4667 intel_set_pipe_timings(intel_crtc);
4668
4669 /* pipesrc and dspsize control the size that is scaled from,
4670 * which should always be the user's requested size.
4671 */
4672 I915_WRITE(DSPSIZE(plane),
4673 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4674 (intel_crtc->config.pipe_src_w - 1));
4675 I915_WRITE(DSPPOS(plane), 0);
4676
4677 i9xx_set_pipeconf(intel_crtc);
4678
4679 I915_WRITE(DSPCNTR(plane), dspcntr);
4680 POSTING_READ(DSPCNTR(plane));
4681
4682 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4683 crtc->x, crtc->y);
4684
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004685 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004686
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004687 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004688 if (encoder->pre_enable)
4689 encoder->pre_enable(encoder);
4690
Daniel Vetterf6736a12013-06-05 13:34:30 +02004691 i9xx_enable_pll(intel_crtc);
4692
Jesse Barnes2dd24552013-04-25 12:55:01 -07004693 i9xx_pfit_enable(intel_crtc);
4694
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004695 intel_crtc_load_lut(crtc);
4696
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004697 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004698 intel_enable_pipe(intel_crtc);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004699 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004700
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004701 for_each_encoder_on_crtc(dev, crtc, encoder)
4702 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004703
4704 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004705
Daniel Vetter87b6b102014-05-15 15:33:46 +02004706 drm_crtc_vblank_on(crtc);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004707}
4708
Daniel Vetter87476d62013-04-11 16:29:06 +02004709static void i9xx_pfit_disable(struct intel_crtc *crtc)
4710{
4711 struct drm_device *dev = crtc->base.dev;
4712 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004713
4714 if (!crtc->config.gmch_pfit.control)
4715 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004716
4717 assert_pipe_disabled(dev_priv, crtc->pipe);
4718
Daniel Vetter328d8e82013-05-08 10:36:31 +02004719 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4720 I915_READ(PFIT_CONTROL));
4721 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004722}
4723
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004724static void i9xx_crtc_disable(struct drm_crtc *crtc)
4725{
4726 struct drm_device *dev = crtc->dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004729 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004730 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004731
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004732 if (!intel_crtc->active)
4733 return;
4734
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004735 intel_crtc_disable_planes(crtc);
4736
Daniel Vetterea9d7582012-07-10 10:42:52 +02004737 for_each_encoder_on_crtc(dev, crtc, encoder)
4738 encoder->disable(encoder);
4739
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004740 /*
4741 * On gen2 planes are double buffered but the pipe isn't, so we must
4742 * wait for planes to fully turn off before disabling the pipe.
4743 */
4744 if (IS_GEN2(dev))
4745 intel_wait_for_vblank(dev, pipe);
4746
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004747 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08004748 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004749
Daniel Vetter87476d62013-04-11 16:29:06 +02004750 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004751
Jesse Barnes89b667f2013-04-18 14:51:36 -07004752 for_each_encoder_on_crtc(dev, crtc, encoder)
4753 if (encoder->post_disable)
4754 encoder->post_disable(encoder);
4755
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004756 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4757 if (IS_CHERRYVIEW(dev))
4758 chv_disable_pll(dev_priv, pipe);
4759 else if (IS_VALLEYVIEW(dev))
4760 vlv_disable_pll(dev_priv, pipe);
4761 else
4762 i9xx_disable_pll(dev_priv, pipe);
4763 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004764
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004765 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004766 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004767
Daniel Vetterefa96242014-04-24 23:55:02 +02004768 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004769 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004770 intel_edp_psr_update(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004771 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004772}
4773
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004774static void i9xx_crtc_off(struct drm_crtc *crtc)
4775{
4776}
4777
Daniel Vetter976f8a22012-07-08 22:34:21 +02004778static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4779 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004780{
4781 struct drm_device *dev = crtc->dev;
4782 struct drm_i915_master_private *master_priv;
4783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4784 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004785
4786 if (!dev->primary->master)
4787 return;
4788
4789 master_priv = dev->primary->master->driver_priv;
4790 if (!master_priv->sarea_priv)
4791 return;
4792
Jesse Barnes79e53942008-11-07 14:24:08 -08004793 switch (pipe) {
4794 case 0:
4795 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4796 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4797 break;
4798 case 1:
4799 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4800 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4801 break;
4802 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004803 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004804 break;
4805 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004806}
4807
Daniel Vetter976f8a22012-07-08 22:34:21 +02004808/**
4809 * Sets the power management mode of the pipe and plane.
4810 */
4811void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004812{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004813 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004814 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004815 struct intel_encoder *intel_encoder;
4816 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004817
Daniel Vetter976f8a22012-07-08 22:34:21 +02004818 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4819 enable |= intel_encoder->connectors_active;
4820
4821 if (enable)
4822 dev_priv->display.crtc_enable(crtc);
4823 else
4824 dev_priv->display.crtc_disable(crtc);
4825
4826 intel_crtc_update_sarea(crtc, enable);
4827}
4828
Daniel Vetter976f8a22012-07-08 22:34:21 +02004829static void intel_crtc_disable(struct drm_crtc *crtc)
4830{
4831 struct drm_device *dev = crtc->dev;
4832 struct drm_connector *connector;
4833 struct drm_i915_private *dev_priv = dev->dev_private;
4834
4835 /* crtc should still be enabled when we disable it. */
4836 WARN_ON(!crtc->enabled);
4837
4838 dev_priv->display.crtc_disable(crtc);
4839 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004840 dev_priv->display.off(crtc);
4841
Chris Wilson931872f2012-01-16 23:01:13 +00004842 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03004843 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Chris Wilson931872f2012-01-16 23:01:13 +00004844 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004845
Matt Roperf4510a22014-04-01 15:22:40 -07004846 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004847 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004848 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004849 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004850 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004851 }
4852
4853 /* Update computed state. */
4854 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4855 if (!connector->encoder || !connector->encoder->crtc)
4856 continue;
4857
4858 if (connector->encoder->crtc != crtc)
4859 continue;
4860
4861 connector->dpms = DRM_MODE_DPMS_OFF;
4862 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004863 }
4864}
4865
Chris Wilsonea5b2132010-08-04 13:50:23 +01004866void intel_encoder_destroy(struct drm_encoder *encoder)
4867{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004868 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004869
Chris Wilsonea5b2132010-08-04 13:50:23 +01004870 drm_encoder_cleanup(encoder);
4871 kfree(intel_encoder);
4872}
4873
Damien Lespiau92373292013-08-08 22:28:57 +01004874/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004875 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4876 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01004877static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004878{
4879 if (mode == DRM_MODE_DPMS_ON) {
4880 encoder->connectors_active = true;
4881
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004882 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004883 } else {
4884 encoder->connectors_active = false;
4885
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004886 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004887 }
4888}
4889
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004890/* Cross check the actual hw state with our own modeset state tracking (and it's
4891 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02004892static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004893{
4894 if (connector->get_hw_state(connector)) {
4895 struct intel_encoder *encoder = connector->encoder;
4896 struct drm_crtc *crtc;
4897 bool encoder_enabled;
4898 enum pipe pipe;
4899
4900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4901 connector->base.base.id,
4902 drm_get_connector_name(&connector->base));
4903
4904 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4905 "wrong connector dpms state\n");
4906 WARN(connector->base.encoder != &encoder->base,
4907 "active connector not linked to encoder\n");
4908 WARN(!encoder->connectors_active,
4909 "encoder->connectors_active not set\n");
4910
4911 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4912 WARN(!encoder_enabled, "encoder not enabled\n");
4913 if (WARN_ON(!encoder->base.crtc))
4914 return;
4915
4916 crtc = encoder->base.crtc;
4917
4918 WARN(!crtc->enabled, "crtc not enabled\n");
4919 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4920 WARN(pipe != to_intel_crtc(crtc)->pipe,
4921 "encoder active on the wrong pipe\n");
4922 }
4923}
4924
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004925/* Even simpler default implementation, if there's really no special case to
4926 * consider. */
4927void intel_connector_dpms(struct drm_connector *connector, int mode)
4928{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004929 /* All the simple cases only support two dpms states. */
4930 if (mode != DRM_MODE_DPMS_ON)
4931 mode = DRM_MODE_DPMS_OFF;
4932
4933 if (mode == connector->dpms)
4934 return;
4935
4936 connector->dpms = mode;
4937
4938 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01004939 if (connector->encoder)
4940 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004941
Daniel Vetterb9805142012-08-31 17:37:33 +02004942 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004943}
4944
Daniel Vetterf0947c32012-07-02 13:10:34 +02004945/* Simple connector->get_hw_state implementation for encoders that support only
4946 * one connector and no cloning and hence the encoder state determines the state
4947 * of the connector. */
4948bool intel_connector_get_hw_state(struct intel_connector *connector)
4949{
Daniel Vetter24929352012-07-02 20:28:59 +02004950 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02004951 struct intel_encoder *encoder = connector->encoder;
4952
4953 return encoder->get_hw_state(encoder, &pipe);
4954}
4955
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004956static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4957 struct intel_crtc_config *pipe_config)
4958{
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960 struct intel_crtc *pipe_B_crtc =
4961 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4962
4963 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4964 pipe_name(pipe), pipe_config->fdi_lanes);
4965 if (pipe_config->fdi_lanes > 4) {
4966 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4967 pipe_name(pipe), pipe_config->fdi_lanes);
4968 return false;
4969 }
4970
Paulo Zanonibafb6552013-11-02 21:07:44 -07004971 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004972 if (pipe_config->fdi_lanes > 2) {
4973 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4974 pipe_config->fdi_lanes);
4975 return false;
4976 } else {
4977 return true;
4978 }
4979 }
4980
4981 if (INTEL_INFO(dev)->num_pipes == 2)
4982 return true;
4983
4984 /* Ivybridge 3 pipe is really complicated */
4985 switch (pipe) {
4986 case PIPE_A:
4987 return true;
4988 case PIPE_B:
4989 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4990 pipe_config->fdi_lanes > 2) {
4991 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4992 pipe_name(pipe), pipe_config->fdi_lanes);
4993 return false;
4994 }
4995 return true;
4996 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01004997 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004998 pipe_B_crtc->config.fdi_lanes <= 2) {
4999 if (pipe_config->fdi_lanes > 2) {
5000 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5001 pipe_name(pipe), pipe_config->fdi_lanes);
5002 return false;
5003 }
5004 } else {
5005 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5006 return false;
5007 }
5008 return true;
5009 default:
5010 BUG();
5011 }
5012}
5013
Daniel Vettere29c22c2013-02-21 00:00:16 +01005014#define RETRY 1
5015static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5016 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005017{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005018 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005019 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005020 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005021 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005022
Daniel Vettere29c22c2013-02-21 00:00:16 +01005023retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005024 /* FDI is a binary signal running at ~2.7GHz, encoding
5025 * each output octet as 10 bits. The actual frequency
5026 * is stored as a divider into a 100MHz clock, and the
5027 * mode pixel clock is stored in units of 1KHz.
5028 * Hence the bw of each lane in terms of the mode signal
5029 * is:
5030 */
5031 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5032
Damien Lespiau241bfc32013-09-25 16:45:37 +01005033 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005034
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005035 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005036 pipe_config->pipe_bpp);
5037
5038 pipe_config->fdi_lanes = lane;
5039
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005040 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005041 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005042
Daniel Vettere29c22c2013-02-21 00:00:16 +01005043 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5044 intel_crtc->pipe, pipe_config);
5045 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5046 pipe_config->pipe_bpp -= 2*3;
5047 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5048 pipe_config->pipe_bpp);
5049 needs_recompute = true;
5050 pipe_config->bw_constrained = true;
5051
5052 goto retry;
5053 }
5054
5055 if (needs_recompute)
5056 return RETRY;
5057
5058 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005059}
5060
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005061static void hsw_compute_ips_config(struct intel_crtc *crtc,
5062 struct intel_crtc_config *pipe_config)
5063{
Jani Nikulad330a952014-01-21 11:24:25 +02005064 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005065 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005066 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005067}
5068
Daniel Vettera43f6e02013-06-07 23:10:32 +02005069static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005070 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005071{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005072 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005073 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005074
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005075 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005076 if (INTEL_INFO(dev)->gen < 4) {
5077 struct drm_i915_private *dev_priv = dev->dev_private;
5078 int clock_limit =
5079 dev_priv->display.get_display_clock_speed(dev);
5080
5081 /*
5082 * Enable pixel doubling when the dot clock
5083 * is > 90% of the (display) core speed.
5084 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005085 * GDG double wide on either pipe,
5086 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005087 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005088 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005089 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005090 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005091 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005092 }
5093
Damien Lespiau241bfc32013-09-25 16:45:37 +01005094 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005095 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005096 }
Chris Wilson89749352010-09-12 18:25:19 +01005097
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005098 /*
5099 * Pipe horizontal size must be even in:
5100 * - DVO ganged mode
5101 * - LVDS dual channel mode
5102 * - Double wide pipe
5103 */
5104 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5105 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5106 pipe_config->pipe_src_w &= ~1;
5107
Damien Lespiau8693a822013-05-03 18:48:11 +01005108 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5109 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005110 */
5111 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5112 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005113 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005114
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005115 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005116 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005117 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005118 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5119 * for lvds. */
5120 pipe_config->pipe_bpp = 8*3;
5121 }
5122
Damien Lespiauf5adf942013-06-24 18:29:34 +01005123 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005124 hsw_compute_ips_config(crtc, pipe_config);
5125
5126 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5127 * clock survives for now. */
5128 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5129 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005130
Daniel Vetter877d48d2013-04-19 11:24:43 +02005131 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005132 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005133
Daniel Vettere29c22c2013-02-21 00:00:16 +01005134 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005135}
5136
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005137static int valleyview_get_display_clock_speed(struct drm_device *dev)
5138{
5139 return 400000; /* FIXME */
5140}
5141
Jesse Barnese70236a2009-09-21 10:42:27 -07005142static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005143{
Jesse Barnese70236a2009-09-21 10:42:27 -07005144 return 400000;
5145}
Jesse Barnes79e53942008-11-07 14:24:08 -08005146
Jesse Barnese70236a2009-09-21 10:42:27 -07005147static int i915_get_display_clock_speed(struct drm_device *dev)
5148{
5149 return 333000;
5150}
Jesse Barnes79e53942008-11-07 14:24:08 -08005151
Jesse Barnese70236a2009-09-21 10:42:27 -07005152static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5153{
5154 return 200000;
5155}
Jesse Barnes79e53942008-11-07 14:24:08 -08005156
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005157static int pnv_get_display_clock_speed(struct drm_device *dev)
5158{
5159 u16 gcfgc = 0;
5160
5161 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5162
5163 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5164 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5165 return 267000;
5166 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5167 return 333000;
5168 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5169 return 444000;
5170 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5171 return 200000;
5172 default:
5173 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5174 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5175 return 133000;
5176 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5177 return 167000;
5178 }
5179}
5180
Jesse Barnese70236a2009-09-21 10:42:27 -07005181static int i915gm_get_display_clock_speed(struct drm_device *dev)
5182{
5183 u16 gcfgc = 0;
5184
5185 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5186
5187 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005188 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005189 else {
5190 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5191 case GC_DISPLAY_CLOCK_333_MHZ:
5192 return 333000;
5193 default:
5194 case GC_DISPLAY_CLOCK_190_200_MHZ:
5195 return 190000;
5196 }
5197 }
5198}
Jesse Barnes79e53942008-11-07 14:24:08 -08005199
Jesse Barnese70236a2009-09-21 10:42:27 -07005200static int i865_get_display_clock_speed(struct drm_device *dev)
5201{
5202 return 266000;
5203}
5204
5205static int i855_get_display_clock_speed(struct drm_device *dev)
5206{
5207 u16 hpllcc = 0;
5208 /* Assume that the hardware is in the high speed state. This
5209 * should be the default.
5210 */
5211 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5212 case GC_CLOCK_133_200:
5213 case GC_CLOCK_100_200:
5214 return 200000;
5215 case GC_CLOCK_166_250:
5216 return 250000;
5217 case GC_CLOCK_100_133:
5218 return 133000;
5219 }
5220
5221 /* Shouldn't happen */
5222 return 0;
5223}
5224
5225static int i830_get_display_clock_speed(struct drm_device *dev)
5226{
5227 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005228}
5229
Zhenyu Wang2c072452009-06-05 15:38:42 +08005230static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005231intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005232{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005233 while (*num > DATA_LINK_M_N_MASK ||
5234 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005235 *num >>= 1;
5236 *den >>= 1;
5237 }
5238}
5239
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005240static void compute_m_n(unsigned int m, unsigned int n,
5241 uint32_t *ret_m, uint32_t *ret_n)
5242{
5243 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5244 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5245 intel_reduce_m_n_ratio(ret_m, ret_n);
5246}
5247
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005248void
5249intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5250 int pixel_clock, int link_clock,
5251 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005252{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005253 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005254
5255 compute_m_n(bits_per_pixel * pixel_clock,
5256 link_clock * nlanes * 8,
5257 &m_n->gmch_m, &m_n->gmch_n);
5258
5259 compute_m_n(pixel_clock, link_clock,
5260 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005261}
5262
Chris Wilsona7615032011-01-12 17:04:08 +00005263static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5264{
Jani Nikulad330a952014-01-21 11:24:25 +02005265 if (i915.panel_use_ssc >= 0)
5266 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005267 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005268 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005269}
5270
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005271static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5272{
5273 struct drm_device *dev = crtc->dev;
5274 struct drm_i915_private *dev_priv = dev->dev_private;
5275 int refclk;
5276
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005277 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005278 refclk = 100000;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005279 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005280 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005281 refclk = dev_priv->vbt.lvds_ssc_freq;
5282 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005283 } else if (!IS_GEN2(dev)) {
5284 refclk = 96000;
5285 } else {
5286 refclk = 48000;
5287 }
5288
5289 return refclk;
5290}
5291
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005292static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005293{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005294 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005295}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005296
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005297static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5298{
5299 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005300}
5301
Daniel Vetterf47709a2013-03-28 10:42:02 +01005302static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005303 intel_clock_t *reduced_clock)
5304{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005305 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005306 u32 fp, fp2 = 0;
5307
5308 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005309 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005310 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005311 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005312 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005313 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005314 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005315 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005316 }
5317
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005318 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005319
Daniel Vetterf47709a2013-03-28 10:42:02 +01005320 crtc->lowfreq_avail = false;
5321 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005322 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005323 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005324 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005325 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005326 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005327 }
5328}
5329
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005330static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5331 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005332{
5333 u32 reg_val;
5334
5335 /*
5336 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5337 * and set it to a reasonable value instead.
5338 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005339 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005340 reg_val &= 0xffffff00;
5341 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005343
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005344 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005345 reg_val &= 0x8cffffff;
5346 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005347 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005348
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005349 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005350 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005352
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005354 reg_val &= 0x00ffffff;
5355 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005356 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005357}
5358
Daniel Vetterb5518422013-05-03 11:49:48 +02005359static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5360 struct intel_link_m_n *m_n)
5361{
5362 struct drm_device *dev = crtc->base.dev;
5363 struct drm_i915_private *dev_priv = dev->dev_private;
5364 int pipe = crtc->pipe;
5365
Daniel Vettere3b95f12013-05-03 11:49:49 +02005366 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5367 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5368 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5369 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005370}
5371
5372static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5373 struct intel_link_m_n *m_n)
5374{
5375 struct drm_device *dev = crtc->base.dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 int pipe = crtc->pipe;
5378 enum transcoder transcoder = crtc->config.cpu_transcoder;
5379
5380 if (INTEL_INFO(dev)->gen >= 5) {
5381 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5382 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5383 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5384 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5385 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005386 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5387 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5388 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5389 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005390 }
5391}
5392
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005393static void intel_dp_set_m_n(struct intel_crtc *crtc)
5394{
5395 if (crtc->config.has_pch_encoder)
5396 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5397 else
5398 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5399}
5400
Daniel Vetterf47709a2013-03-28 10:42:02 +01005401static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005402{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005403 u32 dpll, dpll_md;
5404
5405 /*
5406 * Enable DPIO clock input. We should never disable the reference
5407 * clock for pipe B, since VGA hotplug / manual detection depends
5408 * on it.
5409 */
5410 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5411 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5412 /* We should never disable this, set it here for state tracking */
5413 if (crtc->pipe == PIPE_B)
5414 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5415 dpll |= DPLL_VCO_ENABLE;
5416 crtc->config.dpll_hw_state.dpll = dpll;
5417
5418 dpll_md = (crtc->config.pixel_multiplier - 1)
5419 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5420 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5421}
5422
5423static void vlv_prepare_pll(struct intel_crtc *crtc)
5424{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005425 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005426 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005427 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005428 u32 mdiv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005429 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005430 u32 coreclk, reg_val;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005431
Daniel Vetter09153002012-12-12 14:06:44 +01005432 mutex_lock(&dev_priv->dpio_lock);
5433
Daniel Vetterf47709a2013-03-28 10:42:02 +01005434 bestn = crtc->config.dpll.n;
5435 bestm1 = crtc->config.dpll.m1;
5436 bestm2 = crtc->config.dpll.m2;
5437 bestp1 = crtc->config.dpll.p1;
5438 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005439
Jesse Barnes89b667f2013-04-18 14:51:36 -07005440 /* See eDP HDMI DPIO driver vbios notes doc */
5441
5442 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005443 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005444 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005445
5446 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005447 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005448
5449 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005450 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005451 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005452 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005453
5454 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005455 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005456
5457 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005458 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5459 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5460 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005461 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005462
5463 /*
5464 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5465 * but we don't support that).
5466 * Note: don't use the DAC post divider as it seems unstable.
5467 */
5468 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005469 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005470
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005471 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005472 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005473
Jesse Barnes89b667f2013-04-18 14:51:36 -07005474 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005475 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005476 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005477 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005478 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b01202013-07-05 19:21:38 +03005479 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005480 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005482 0x00d0000f);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005483
Jesse Barnes89b667f2013-04-18 14:51:36 -07005484 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5485 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5486 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005487 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005488 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005489 0x0df40000);
5490 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005491 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005492 0x0df70000);
5493 } else { /* HDMI or VGA */
5494 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005495 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005496 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005497 0x0df70000);
5498 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005499 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005500 0x0df40000);
5501 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005502
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005503 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005504 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5505 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5506 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5507 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005508 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005509
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005510 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005511 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005512}
5513
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005514static void chv_update_pll(struct intel_crtc *crtc)
5515{
5516 struct drm_device *dev = crtc->base.dev;
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 int pipe = crtc->pipe;
5519 int dpll_reg = DPLL(crtc->pipe);
5520 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005521 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005522 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5523 int refclk;
5524
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005525 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5526 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5527 DPLL_VCO_ENABLE;
5528 if (pipe != PIPE_A)
5529 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5530
5531 crtc->config.dpll_hw_state.dpll_md =
5532 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005533
5534 bestn = crtc->config.dpll.n;
5535 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5536 bestm1 = crtc->config.dpll.m1;
5537 bestm2 = crtc->config.dpll.m2 >> 22;
5538 bestp1 = crtc->config.dpll.p1;
5539 bestp2 = crtc->config.dpll.p2;
5540
5541 /*
5542 * Enable Refclk and SSC
5543 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005544 I915_WRITE(dpll_reg,
5545 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5546
5547 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005548
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005549 /* p1 and p2 divider */
5550 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5551 5 << DPIO_CHV_S1_DIV_SHIFT |
5552 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5553 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5554 1 << DPIO_CHV_K_DIV_SHIFT);
5555
5556 /* Feedback post-divider - m2 */
5557 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5558
5559 /* Feedback refclk divider - n and m1 */
5560 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5561 DPIO_CHV_M1_DIV_BY_2 |
5562 1 << DPIO_CHV_N_DIV_SHIFT);
5563
5564 /* M2 fraction division */
5565 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5566
5567 /* M2 fraction division enable */
5568 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5569 DPIO_CHV_FRAC_DIV_EN |
5570 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5571
5572 /* Loop filter */
5573 refclk = i9xx_get_refclk(&crtc->base, 0);
5574 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5575 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5576 if (refclk == 100000)
5577 intcoeff = 11;
5578 else if (refclk == 38400)
5579 intcoeff = 10;
5580 else
5581 intcoeff = 9;
5582 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5583 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5584
5585 /* AFC Recal */
5586 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5587 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5588 DPIO_AFC_RECAL);
5589
5590 mutex_unlock(&dev_priv->dpio_lock);
5591}
5592
Daniel Vetterf47709a2013-03-28 10:42:02 +01005593static void i9xx_update_pll(struct intel_crtc *crtc,
5594 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005595 int num_connectors)
5596{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005597 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005598 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005599 u32 dpll;
5600 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005601 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005602
Daniel Vetterf47709a2013-03-28 10:42:02 +01005603 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305604
Daniel Vetterf47709a2013-03-28 10:42:02 +01005605 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5606 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005607
5608 dpll = DPLL_VGA_MODE_DIS;
5609
Daniel Vetterf47709a2013-03-28 10:42:02 +01005610 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005611 dpll |= DPLLB_MODE_LVDS;
5612 else
5613 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005614
Daniel Vetteref1b4602013-06-01 17:17:04 +02005615 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005616 dpll |= (crtc->config.pixel_multiplier - 1)
5617 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005618 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005619
5620 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005621 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005622
Daniel Vetterf47709a2013-03-28 10:42:02 +01005623 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005624 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005625
5626 /* compute bitmask from p1 value */
5627 if (IS_PINEVIEW(dev))
5628 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5629 else {
5630 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5631 if (IS_G4X(dev) && reduced_clock)
5632 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5633 }
5634 switch (clock->p2) {
5635 case 5:
5636 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5637 break;
5638 case 7:
5639 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5640 break;
5641 case 10:
5642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5643 break;
5644 case 14:
5645 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5646 break;
5647 }
5648 if (INTEL_INFO(dev)->gen >= 4)
5649 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5650
Daniel Vetter09ede542013-04-30 14:01:45 +02005651 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005652 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005653 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005654 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5655 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5656 else
5657 dpll |= PLL_REF_INPUT_DREFCLK;
5658
5659 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005660 crtc->config.dpll_hw_state.dpll = dpll;
5661
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005662 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005663 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5664 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005665 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005666 }
5667}
5668
Daniel Vetterf47709a2013-03-28 10:42:02 +01005669static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005670 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005671 int num_connectors)
5672{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005673 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005674 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005675 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005676 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005677
Daniel Vetterf47709a2013-03-28 10:42:02 +01005678 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305679
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005680 dpll = DPLL_VGA_MODE_DIS;
5681
Daniel Vetterf47709a2013-03-28 10:42:02 +01005682 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005683 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5684 } else {
5685 if (clock->p1 == 2)
5686 dpll |= PLL_P1_DIVIDE_BY_TWO;
5687 else
5688 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5689 if (clock->p2 == 4)
5690 dpll |= PLL_P2_DIVIDE_BY_4;
5691 }
5692
Daniel Vetter4a33e482013-07-06 12:52:05 +02005693 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5694 dpll |= DPLL_DVO_2X_MODE;
5695
Daniel Vetterf47709a2013-03-28 10:42:02 +01005696 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005697 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5698 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5699 else
5700 dpll |= PLL_REF_INPUT_DREFCLK;
5701
5702 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005703 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005704}
5705
Daniel Vetter8a654f32013-06-01 17:16:22 +02005706static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005707{
5708 struct drm_device *dev = intel_crtc->base.dev;
5709 struct drm_i915_private *dev_priv = dev->dev_private;
5710 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005711 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005712 struct drm_display_mode *adjusted_mode =
5713 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005714 uint32_t crtc_vtotal, crtc_vblank_end;
5715 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005716
5717 /* We need to be careful not to changed the adjusted mode, for otherwise
5718 * the hw state checker will get angry at the mismatch. */
5719 crtc_vtotal = adjusted_mode->crtc_vtotal;
5720 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005721
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005722 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005723 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005724 crtc_vtotal -= 1;
5725 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005726
5727 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5728 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5729 else
5730 vsyncshift = adjusted_mode->crtc_hsync_start -
5731 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005732 if (vsyncshift < 0)
5733 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005734 }
5735
5736 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005737 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005738
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005739 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005740 (adjusted_mode->crtc_hdisplay - 1) |
5741 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005742 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005743 (adjusted_mode->crtc_hblank_start - 1) |
5744 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005745 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005746 (adjusted_mode->crtc_hsync_start - 1) |
5747 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5748
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005749 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005750 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005751 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005752 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005753 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005754 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005755 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005756 (adjusted_mode->crtc_vsync_start - 1) |
5757 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5758
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005759 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5760 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5761 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5762 * bits. */
5763 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5764 (pipe == PIPE_B || pipe == PIPE_C))
5765 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5766
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005767 /* pipesrc controls the size that is scaled from, which should
5768 * always be the user's requested size.
5769 */
5770 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005771 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5772 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005773}
5774
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005775static void intel_get_pipe_timings(struct intel_crtc *crtc,
5776 struct intel_crtc_config *pipe_config)
5777{
5778 struct drm_device *dev = crtc->base.dev;
5779 struct drm_i915_private *dev_priv = dev->dev_private;
5780 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5781 uint32_t tmp;
5782
5783 tmp = I915_READ(HTOTAL(cpu_transcoder));
5784 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5785 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5786 tmp = I915_READ(HBLANK(cpu_transcoder));
5787 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5788 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5789 tmp = I915_READ(HSYNC(cpu_transcoder));
5790 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5791 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5792
5793 tmp = I915_READ(VTOTAL(cpu_transcoder));
5794 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5795 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5796 tmp = I915_READ(VBLANK(cpu_transcoder));
5797 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5798 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5799 tmp = I915_READ(VSYNC(cpu_transcoder));
5800 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5801 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5802
5803 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5804 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5805 pipe_config->adjusted_mode.crtc_vtotal += 1;
5806 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5807 }
5808
5809 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005810 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5811 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5812
5813 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5814 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005815}
5816
Daniel Vetterf6a83282014-02-11 15:28:57 -08005817void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5818 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03005819{
Daniel Vetterf6a83282014-02-11 15:28:57 -08005820 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5821 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5822 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5823 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005824
Daniel Vetterf6a83282014-02-11 15:28:57 -08005825 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5826 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5827 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5828 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005829
Daniel Vetterf6a83282014-02-11 15:28:57 -08005830 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005831
Daniel Vetterf6a83282014-02-11 15:28:57 -08005832 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5833 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005834}
5835
Daniel Vetter84b046f2013-02-19 18:48:54 +01005836static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5837{
5838 struct drm_device *dev = intel_crtc->base.dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 uint32_t pipeconf;
5841
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005842 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005843
Daniel Vetter67c72a12013-09-24 11:46:14 +02005844 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5845 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5846 pipeconf |= PIPECONF_ENABLE;
5847
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005848 if (intel_crtc->config.double_wide)
5849 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005850
Daniel Vetterff9ce462013-04-24 14:57:17 +02005851 /* only g4x and later have fancy bpc/dither controls */
5852 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02005853 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5854 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5855 pipeconf |= PIPECONF_DITHER_EN |
5856 PIPECONF_DITHER_TYPE_SP;
5857
5858 switch (intel_crtc->config.pipe_bpp) {
5859 case 18:
5860 pipeconf |= PIPECONF_6BPC;
5861 break;
5862 case 24:
5863 pipeconf |= PIPECONF_8BPC;
5864 break;
5865 case 30:
5866 pipeconf |= PIPECONF_10BPC;
5867 break;
5868 default:
5869 /* Case prevented by intel_choose_pipe_bpp_dither. */
5870 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01005871 }
5872 }
5873
5874 if (HAS_PIPE_CXSR(dev)) {
5875 if (intel_crtc->lowfreq_avail) {
5876 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5877 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5878 } else {
5879 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01005880 }
5881 }
5882
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02005883 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5884 if (INTEL_INFO(dev)->gen < 4 ||
5885 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5886 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5887 else
5888 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5889 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01005890 pipeconf |= PIPECONF_PROGRESSIVE;
5891
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005892 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5893 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03005894
Daniel Vetter84b046f2013-02-19 18:48:54 +01005895 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5896 POSTING_READ(PIPECONF(intel_crtc->pipe));
5897}
5898
Eric Anholtf564048e2011-03-30 13:01:02 -07005899static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005900 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005901 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005902{
5903 struct drm_device *dev = crtc->dev;
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07005906 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07005907 intel_clock_t clock, reduced_clock;
Daniel Vettera16af722013-04-30 14:01:44 +02005908 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005909 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01005910 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08005911 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08005912
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02005913 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005914 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005915 case INTEL_OUTPUT_LVDS:
5916 is_lvds = true;
5917 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005918 case INTEL_OUTPUT_DSI:
5919 is_dsi = true;
5920 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005921 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005922
Eric Anholtc751ce42010-03-25 11:48:48 -07005923 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08005924 }
5925
Jani Nikulaf2335332013-09-13 11:03:09 +03005926 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02005927 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005928
Jani Nikulaf2335332013-09-13 11:03:09 +03005929 if (!intel_crtc->config.clock_set) {
5930 refclk = i9xx_get_refclk(crtc, num_connectors);
5931
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005932 /*
5933 * Returns a set of divisors for the desired target clock with
5934 * the given refclk, or FALSE. The returned values represent
5935 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5936 * 2) / p1 / p2.
5937 */
5938 limit = intel_limit(crtc, refclk);
5939 ok = dev_priv->display.find_dpll(limit, crtc,
5940 intel_crtc->config.port_clock,
5941 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03005942 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005943 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5944 return -EINVAL;
5945 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005946
Jani Nikulaf2335332013-09-13 11:03:09 +03005947 if (is_lvds && dev_priv->lvds_downclock_avail) {
5948 /*
5949 * Ensure we match the reduced clock's P to the target
5950 * clock. If the clocks don't match, we can't switch
5951 * the display clock by using the FP0/FP1. In such case
5952 * we will disable the LVDS downclock feature.
5953 */
5954 has_reduced_clock =
5955 dev_priv->display.find_dpll(limit, crtc,
5956 dev_priv->lvds_downclock,
5957 refclk, &clock,
5958 &reduced_clock);
5959 }
5960 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01005961 intel_crtc->config.dpll.n = clock.n;
5962 intel_crtc->config.dpll.m1 = clock.m1;
5963 intel_crtc->config.dpll.m2 = clock.m2;
5964 intel_crtc->config.dpll.p1 = clock.p1;
5965 intel_crtc->config.dpll.p2 = clock.p2;
5966 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005967
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005968 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02005969 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305970 has_reduced_clock ? &reduced_clock : NULL,
5971 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005972 } else if (IS_CHERRYVIEW(dev)) {
5973 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005974 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03005975 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005976 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01005977 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005978 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02005979 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005980 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005981
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02005982 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07005983}
5984
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005985static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5986 struct intel_crtc_config *pipe_config)
5987{
5988 struct drm_device *dev = crtc->base.dev;
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990 uint32_t tmp;
5991
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02005992 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5993 return;
5994
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005995 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02005996 if (!(tmp & PFIT_ENABLE))
5997 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005998
Daniel Vetter06922822013-07-11 13:35:40 +02005999 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006000 if (INTEL_INFO(dev)->gen < 4) {
6001 if (crtc->pipe != PIPE_B)
6002 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006003 } else {
6004 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6005 return;
6006 }
6007
Daniel Vetter06922822013-07-11 13:35:40 +02006008 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006009 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6010 if (INTEL_INFO(dev)->gen < 5)
6011 pipe_config->gmch_pfit.lvds_border_bits =
6012 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6013}
6014
Jesse Barnesacbec812013-09-20 11:29:32 -07006015static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6016 struct intel_crtc_config *pipe_config)
6017{
6018 struct drm_device *dev = crtc->base.dev;
6019 struct drm_i915_private *dev_priv = dev->dev_private;
6020 int pipe = pipe_config->cpu_transcoder;
6021 intel_clock_t clock;
6022 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006023 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006024
6025 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006026 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006027 mutex_unlock(&dev_priv->dpio_lock);
6028
6029 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6030 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6031 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6032 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6033 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6034
Ville Syrjäläf6466282013-10-14 14:50:31 +03006035 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006036
Ville Syrjäläf6466282013-10-14 14:50:31 +03006037 /* clock.dot is the fast clock */
6038 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006039}
6040
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006041static void i9xx_get_plane_config(struct intel_crtc *crtc,
6042 struct intel_plane_config *plane_config)
6043{
6044 struct drm_device *dev = crtc->base.dev;
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 u32 val, base, offset;
6047 int pipe = crtc->pipe, plane = crtc->plane;
6048 int fourcc, pixel_format;
6049 int aligned_height;
6050
Dave Airlie66e514c2014-04-03 07:51:54 +10006051 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6052 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006053 DRM_DEBUG_KMS("failed to alloc fb\n");
6054 return;
6055 }
6056
6057 val = I915_READ(DSPCNTR(plane));
6058
6059 if (INTEL_INFO(dev)->gen >= 4)
6060 if (val & DISPPLANE_TILED)
6061 plane_config->tiled = true;
6062
6063 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6064 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006065 crtc->base.primary->fb->pixel_format = fourcc;
6066 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006067 drm_format_plane_cpp(fourcc, 0) * 8;
6068
6069 if (INTEL_INFO(dev)->gen >= 4) {
6070 if (plane_config->tiled)
6071 offset = I915_READ(DSPTILEOFF(plane));
6072 else
6073 offset = I915_READ(DSPLINOFF(plane));
6074 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6075 } else {
6076 base = I915_READ(DSPADDR(plane));
6077 }
6078 plane_config->base = base;
6079
6080 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006081 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6082 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006083
6084 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006085 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006086
Dave Airlie66e514c2014-04-03 07:51:54 +10006087 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006088 plane_config->tiled);
6089
Dave Airlie66e514c2014-04-03 07:51:54 +10006090 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006091 aligned_height, PAGE_SIZE);
6092
6093 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006094 pipe, plane, crtc->base.primary->fb->width,
6095 crtc->base.primary->fb->height,
6096 crtc->base.primary->fb->bits_per_pixel, base,
6097 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006098 plane_config->size);
6099
6100}
6101
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006102static void chv_crtc_clock_get(struct intel_crtc *crtc,
6103 struct intel_crtc_config *pipe_config)
6104{
6105 struct drm_device *dev = crtc->base.dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107 int pipe = pipe_config->cpu_transcoder;
6108 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6109 intel_clock_t clock;
6110 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6111 int refclk = 100000;
6112
6113 mutex_lock(&dev_priv->dpio_lock);
6114 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6115 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6116 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6117 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6118 mutex_unlock(&dev_priv->dpio_lock);
6119
6120 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6121 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6122 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6123 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6124 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6125
6126 chv_clock(refclk, &clock);
6127
6128 /* clock.dot is the fast clock */
6129 pipe_config->port_clock = clock.dot / 5;
6130}
6131
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006132static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6133 struct intel_crtc_config *pipe_config)
6134{
6135 struct drm_device *dev = crtc->base.dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 uint32_t tmp;
6138
Imre Deakb5482bd2014-03-05 16:20:55 +02006139 if (!intel_display_power_enabled(dev_priv,
6140 POWER_DOMAIN_PIPE(crtc->pipe)))
6141 return false;
6142
Daniel Vettere143a212013-07-04 12:01:15 +02006143 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006144 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006145
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006146 tmp = I915_READ(PIPECONF(crtc->pipe));
6147 if (!(tmp & PIPECONF_ENABLE))
6148 return false;
6149
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006150 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6151 switch (tmp & PIPECONF_BPC_MASK) {
6152 case PIPECONF_6BPC:
6153 pipe_config->pipe_bpp = 18;
6154 break;
6155 case PIPECONF_8BPC:
6156 pipe_config->pipe_bpp = 24;
6157 break;
6158 case PIPECONF_10BPC:
6159 pipe_config->pipe_bpp = 30;
6160 break;
6161 default:
6162 break;
6163 }
6164 }
6165
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006166 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6167 pipe_config->limited_color_range = true;
6168
Ville Syrjälä282740f2013-09-04 18:30:03 +03006169 if (INTEL_INFO(dev)->gen < 4)
6170 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6171
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006172 intel_get_pipe_timings(crtc, pipe_config);
6173
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006174 i9xx_get_pfit_config(crtc, pipe_config);
6175
Daniel Vetter6c49f242013-06-06 12:45:25 +02006176 if (INTEL_INFO(dev)->gen >= 4) {
6177 tmp = I915_READ(DPLL_MD(crtc->pipe));
6178 pipe_config->pixel_multiplier =
6179 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6180 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006181 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006182 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6183 tmp = I915_READ(DPLL(crtc->pipe));
6184 pipe_config->pixel_multiplier =
6185 ((tmp & SDVO_MULTIPLIER_MASK)
6186 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6187 } else {
6188 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6189 * port and will be fixed up in the encoder->get_config
6190 * function. */
6191 pipe_config->pixel_multiplier = 1;
6192 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006193 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6194 if (!IS_VALLEYVIEW(dev)) {
6195 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6196 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006197 } else {
6198 /* Mask out read-only status bits. */
6199 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6200 DPLL_PORTC_READY_MASK |
6201 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006202 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006203
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006204 if (IS_CHERRYVIEW(dev))
6205 chv_crtc_clock_get(crtc, pipe_config);
6206 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006207 vlv_crtc_clock_get(crtc, pipe_config);
6208 else
6209 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006210
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006211 return true;
6212}
6213
Paulo Zanonidde86e22012-12-01 12:04:25 -02006214static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006215{
6216 struct drm_i915_private *dev_priv = dev->dev_private;
6217 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006218 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006219 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006220 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006221 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006222 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006223 bool has_ck505 = false;
6224 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006225
6226 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07006227 list_for_each_entry(encoder, &mode_config->encoder_list,
6228 base.head) {
6229 switch (encoder->type) {
6230 case INTEL_OUTPUT_LVDS:
6231 has_panel = true;
6232 has_lvds = true;
6233 break;
6234 case INTEL_OUTPUT_EDP:
6235 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006236 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006237 has_cpu_edp = true;
6238 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006239 }
6240 }
6241
Keith Packard99eb6a02011-09-26 14:29:12 -07006242 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006243 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006244 can_ssc = has_ck505;
6245 } else {
6246 has_ck505 = false;
6247 can_ssc = true;
6248 }
6249
Imre Deak2de69052013-05-08 13:14:04 +03006250 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6251 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006252
6253 /* Ironlake: try to setup display ref clock before DPLL
6254 * enabling. This is only under driver's control after
6255 * PCH B stepping, previous chipset stepping should be
6256 * ignoring this setting.
6257 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006258 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006259
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006260 /* As we must carefully and slowly disable/enable each source in turn,
6261 * compute the final state we want first and check if we need to
6262 * make any changes at all.
6263 */
6264 final = val;
6265 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006266 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006267 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006268 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006269 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6270
6271 final &= ~DREF_SSC_SOURCE_MASK;
6272 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6273 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006274
Keith Packard199e5d72011-09-22 12:01:57 -07006275 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006276 final |= DREF_SSC_SOURCE_ENABLE;
6277
6278 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6279 final |= DREF_SSC1_ENABLE;
6280
6281 if (has_cpu_edp) {
6282 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6283 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6284 else
6285 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6286 } else
6287 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6288 } else {
6289 final |= DREF_SSC_SOURCE_DISABLE;
6290 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6291 }
6292
6293 if (final == val)
6294 return;
6295
6296 /* Always enable nonspread source */
6297 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6298
6299 if (has_ck505)
6300 val |= DREF_NONSPREAD_CK505_ENABLE;
6301 else
6302 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6303
6304 if (has_panel) {
6305 val &= ~DREF_SSC_SOURCE_MASK;
6306 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006307
Keith Packard199e5d72011-09-22 12:01:57 -07006308 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006309 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006310 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006311 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006312 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006313 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006314
6315 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006316 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006317 POSTING_READ(PCH_DREF_CONTROL);
6318 udelay(200);
6319
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006320 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006321
6322 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006323 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006324 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006325 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006326 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006327 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006328 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006329 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006330 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006331
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006332 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006333 POSTING_READ(PCH_DREF_CONTROL);
6334 udelay(200);
6335 } else {
6336 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6337
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006338 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006339
6340 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006341 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006342
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006343 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006344 POSTING_READ(PCH_DREF_CONTROL);
6345 udelay(200);
6346
6347 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006348 val &= ~DREF_SSC_SOURCE_MASK;
6349 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006350
6351 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006352 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006353
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006354 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006355 POSTING_READ(PCH_DREF_CONTROL);
6356 udelay(200);
6357 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006358
6359 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006360}
6361
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006362static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006363{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006364 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006365
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006366 tmp = I915_READ(SOUTH_CHICKEN2);
6367 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6368 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006369
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006370 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6371 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6372 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006373
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006374 tmp = I915_READ(SOUTH_CHICKEN2);
6375 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6376 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006377
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006378 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6379 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6380 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006381}
6382
6383/* WaMPhyProgramming:hsw */
6384static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6385{
6386 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006387
6388 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6389 tmp &= ~(0xFF << 24);
6390 tmp |= (0x12 << 24);
6391 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6392
Paulo Zanonidde86e22012-12-01 12:04:25 -02006393 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6394 tmp |= (1 << 11);
6395 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6396
6397 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6398 tmp |= (1 << 11);
6399 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6400
Paulo Zanonidde86e22012-12-01 12:04:25 -02006401 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6402 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6403 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6404
6405 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6406 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6407 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6408
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006409 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6410 tmp &= ~(7 << 13);
6411 tmp |= (5 << 13);
6412 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006413
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006414 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6415 tmp &= ~(7 << 13);
6416 tmp |= (5 << 13);
6417 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006418
6419 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6420 tmp &= ~0xFF;
6421 tmp |= 0x1C;
6422 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6423
6424 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6425 tmp &= ~0xFF;
6426 tmp |= 0x1C;
6427 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6428
6429 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6430 tmp &= ~(0xFF << 16);
6431 tmp |= (0x1C << 16);
6432 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6433
6434 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6435 tmp &= ~(0xFF << 16);
6436 tmp |= (0x1C << 16);
6437 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6438
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006439 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6440 tmp |= (1 << 27);
6441 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006442
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006443 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6444 tmp |= (1 << 27);
6445 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006446
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006447 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6448 tmp &= ~(0xF << 28);
6449 tmp |= (4 << 28);
6450 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006451
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006452 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6453 tmp &= ~(0xF << 28);
6454 tmp |= (4 << 28);
6455 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006456}
6457
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006458/* Implements 3 different sequences from BSpec chapter "Display iCLK
6459 * Programming" based on the parameters passed:
6460 * - Sequence to enable CLKOUT_DP
6461 * - Sequence to enable CLKOUT_DP without spread
6462 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6463 */
6464static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6465 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006466{
6467 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006468 uint32_t reg, tmp;
6469
6470 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6471 with_spread = true;
6472 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6473 with_fdi, "LP PCH doesn't have FDI\n"))
6474 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006475
6476 mutex_lock(&dev_priv->dpio_lock);
6477
6478 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6479 tmp &= ~SBI_SSCCTL_DISABLE;
6480 tmp |= SBI_SSCCTL_PATHALT;
6481 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6482
6483 udelay(24);
6484
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006485 if (with_spread) {
6486 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6487 tmp &= ~SBI_SSCCTL_PATHALT;
6488 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006489
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006490 if (with_fdi) {
6491 lpt_reset_fdi_mphy(dev_priv);
6492 lpt_program_fdi_mphy(dev_priv);
6493 }
6494 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006495
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006496 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6497 SBI_GEN0 : SBI_DBUFF0;
6498 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6499 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6500 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006501
6502 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006503}
6504
Paulo Zanoni47701c32013-07-23 11:19:25 -03006505/* Sequence to disable CLKOUT_DP */
6506static void lpt_disable_clkout_dp(struct drm_device *dev)
6507{
6508 struct drm_i915_private *dev_priv = dev->dev_private;
6509 uint32_t reg, tmp;
6510
6511 mutex_lock(&dev_priv->dpio_lock);
6512
6513 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6514 SBI_GEN0 : SBI_DBUFF0;
6515 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6516 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6517 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6518
6519 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6520 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6521 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6522 tmp |= SBI_SSCCTL_PATHALT;
6523 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6524 udelay(32);
6525 }
6526 tmp |= SBI_SSCCTL_DISABLE;
6527 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6528 }
6529
6530 mutex_unlock(&dev_priv->dpio_lock);
6531}
6532
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006533static void lpt_init_pch_refclk(struct drm_device *dev)
6534{
6535 struct drm_mode_config *mode_config = &dev->mode_config;
6536 struct intel_encoder *encoder;
6537 bool has_vga = false;
6538
6539 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6540 switch (encoder->type) {
6541 case INTEL_OUTPUT_ANALOG:
6542 has_vga = true;
6543 break;
6544 }
6545 }
6546
Paulo Zanoni47701c32013-07-23 11:19:25 -03006547 if (has_vga)
6548 lpt_enable_clkout_dp(dev, true, true);
6549 else
6550 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006551}
6552
Paulo Zanonidde86e22012-12-01 12:04:25 -02006553/*
6554 * Initialize reference clocks when the driver loads
6555 */
6556void intel_init_pch_refclk(struct drm_device *dev)
6557{
6558 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6559 ironlake_init_pch_refclk(dev);
6560 else if (HAS_PCH_LPT(dev))
6561 lpt_init_pch_refclk(dev);
6562}
6563
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006564static int ironlake_get_refclk(struct drm_crtc *crtc)
6565{
6566 struct drm_device *dev = crtc->dev;
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006569 int num_connectors = 0;
6570 bool is_lvds = false;
6571
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02006572 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006573 switch (encoder->type) {
6574 case INTEL_OUTPUT_LVDS:
6575 is_lvds = true;
6576 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006577 }
6578 num_connectors++;
6579 }
6580
6581 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006582 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006583 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006584 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006585 }
6586
6587 return 120000;
6588}
6589
Daniel Vetter6ff93602013-04-19 11:24:36 +02006590static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006591{
6592 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6594 int pipe = intel_crtc->pipe;
6595 uint32_t val;
6596
Daniel Vetter78114072013-06-13 00:54:57 +02006597 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006598
Daniel Vetter965e0c42013-03-27 00:44:57 +01006599 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006600 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006601 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006602 break;
6603 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006604 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006605 break;
6606 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006607 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006608 break;
6609 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006610 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006611 break;
6612 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006613 /* Case prevented by intel_choose_pipe_bpp_dither. */
6614 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006615 }
6616
Daniel Vetterd8b32242013-04-25 17:54:44 +02006617 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006618 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6619
Daniel Vetter6ff93602013-04-19 11:24:36 +02006620 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006621 val |= PIPECONF_INTERLACED_ILK;
6622 else
6623 val |= PIPECONF_PROGRESSIVE;
6624
Daniel Vetter50f3b012013-03-27 00:44:56 +01006625 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006626 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006627
Paulo Zanonic8203562012-09-12 10:06:29 -03006628 I915_WRITE(PIPECONF(pipe), val);
6629 POSTING_READ(PIPECONF(pipe));
6630}
6631
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006632/*
6633 * Set up the pipe CSC unit.
6634 *
6635 * Currently only full range RGB to limited range RGB conversion
6636 * is supported, but eventually this should handle various
6637 * RGB<->YCbCr scenarios as well.
6638 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006639static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006640{
6641 struct drm_device *dev = crtc->dev;
6642 struct drm_i915_private *dev_priv = dev->dev_private;
6643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644 int pipe = intel_crtc->pipe;
6645 uint16_t coeff = 0x7800; /* 1.0 */
6646
6647 /*
6648 * TODO: Check what kind of values actually come out of the pipe
6649 * with these coeff/postoff values and adjust to get the best
6650 * accuracy. Perhaps we even need to take the bpc value into
6651 * consideration.
6652 */
6653
Daniel Vetter50f3b012013-03-27 00:44:56 +01006654 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006655 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6656
6657 /*
6658 * GY/GU and RY/RU should be the other way around according
6659 * to BSpec, but reality doesn't agree. Just set them up in
6660 * a way that results in the correct picture.
6661 */
6662 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6663 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6664
6665 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6666 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6667
6668 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6669 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6670
6671 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6672 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6673 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6674
6675 if (INTEL_INFO(dev)->gen > 6) {
6676 uint16_t postoff = 0;
6677
Daniel Vetter50f3b012013-03-27 00:44:56 +01006678 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006679 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006680
6681 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6682 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6683 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6684
6685 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6686 } else {
6687 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6688
Daniel Vetter50f3b012013-03-27 00:44:56 +01006689 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006690 mode |= CSC_BLACK_SCREEN_OFFSET;
6691
6692 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6693 }
6694}
6695
Daniel Vetter6ff93602013-04-19 11:24:36 +02006696static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006697{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006698 struct drm_device *dev = crtc->dev;
6699 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006701 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006702 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006703 uint32_t val;
6704
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006705 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006706
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006707 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006708 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6709
Daniel Vetter6ff93602013-04-19 11:24:36 +02006710 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006711 val |= PIPECONF_INTERLACED_ILK;
6712 else
6713 val |= PIPECONF_PROGRESSIVE;
6714
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006715 I915_WRITE(PIPECONF(cpu_transcoder), val);
6716 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006717
6718 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6719 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006720
6721 if (IS_BROADWELL(dev)) {
6722 val = 0;
6723
6724 switch (intel_crtc->config.pipe_bpp) {
6725 case 18:
6726 val |= PIPEMISC_DITHER_6_BPC;
6727 break;
6728 case 24:
6729 val |= PIPEMISC_DITHER_8_BPC;
6730 break;
6731 case 30:
6732 val |= PIPEMISC_DITHER_10_BPC;
6733 break;
6734 case 36:
6735 val |= PIPEMISC_DITHER_12_BPC;
6736 break;
6737 default:
6738 /* Case prevented by pipe_config_set_bpp. */
6739 BUG();
6740 }
6741
6742 if (intel_crtc->config.dither)
6743 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6744
6745 I915_WRITE(PIPEMISC(pipe), val);
6746 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006747}
6748
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006749static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006750 intel_clock_t *clock,
6751 bool *has_reduced_clock,
6752 intel_clock_t *reduced_clock)
6753{
6754 struct drm_device *dev = crtc->dev;
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 struct intel_encoder *intel_encoder;
6757 int refclk;
6758 const intel_limit_t *limit;
Daniel Vettera16af722013-04-30 14:01:44 +02006759 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006760
6761 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6762 switch (intel_encoder->type) {
6763 case INTEL_OUTPUT_LVDS:
6764 is_lvds = true;
6765 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006766 }
6767 }
6768
6769 refclk = ironlake_get_refclk(crtc);
6770
6771 /*
6772 * Returns a set of divisors for the desired target clock with the given
6773 * refclk, or FALSE. The returned values represent the clock equation:
6774 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6775 */
6776 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006777 ret = dev_priv->display.find_dpll(limit, crtc,
6778 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006779 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006780 if (!ret)
6781 return false;
6782
6783 if (is_lvds && dev_priv->lvds_downclock_avail) {
6784 /*
6785 * Ensure we match the reduced clock's P to the target clock.
6786 * If the clocks don't match, we can't switch the display clock
6787 * by using the FP0/FP1. In such case we will disable the LVDS
6788 * downclock feature.
6789 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006790 *has_reduced_clock =
6791 dev_priv->display.find_dpll(limit, crtc,
6792 dev_priv->lvds_downclock,
6793 refclk, clock,
6794 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006795 }
6796
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006797 return true;
6798}
6799
Paulo Zanonid4b19312012-11-29 11:29:32 -02006800int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6801{
6802 /*
6803 * Account for spread spectrum to avoid
6804 * oversubscribing the link. Max center spread
6805 * is 2.5%; use 5% for safety's sake.
6806 */
6807 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02006808 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02006809}
6810
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006811static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006812{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006813 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006814}
6815
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006816static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006817 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006818 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006819{
6820 struct drm_crtc *crtc = &intel_crtc->base;
6821 struct drm_device *dev = crtc->dev;
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 struct intel_encoder *intel_encoder;
6824 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006825 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006826 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006827
6828 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6829 switch (intel_encoder->type) {
6830 case INTEL_OUTPUT_LVDS:
6831 is_lvds = true;
6832 break;
6833 case INTEL_OUTPUT_SDVO:
6834 case INTEL_OUTPUT_HDMI:
6835 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006836 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006837 }
6838
6839 num_connectors++;
6840 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006841
Chris Wilsonc1858122010-12-03 21:35:48 +00006842 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07006843 factor = 21;
6844 if (is_lvds) {
6845 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006846 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02006847 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07006848 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02006849 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07006850 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00006851
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006852 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02006853 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00006854
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006855 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6856 *fp2 |= FP_CB_TUNE;
6857
Chris Wilson5eddb702010-09-11 13:48:45 +01006858 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006859
Eric Anholta07d6782011-03-30 13:01:08 -07006860 if (is_lvds)
6861 dpll |= DPLLB_MODE_LVDS;
6862 else
6863 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006864
Daniel Vetteref1b4602013-06-01 17:17:04 +02006865 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6866 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006867
6868 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006869 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02006870 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006871 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08006872
Eric Anholta07d6782011-03-30 13:01:08 -07006873 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006874 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006875 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006876 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006877
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006878 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07006879 case 5:
6880 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6881 break;
6882 case 7:
6883 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6884 break;
6885 case 10:
6886 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6887 break;
6888 case 14:
6889 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6890 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006891 }
6892
Daniel Vetterb4c09f32013-04-30 14:01:42 +02006893 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006894 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08006895 else
6896 dpll |= PLL_REF_INPUT_DREFCLK;
6897
Daniel Vetter959e16d2013-06-05 13:34:21 +02006898 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006899}
6900
Jesse Barnes79e53942008-11-07 14:24:08 -08006901static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08006902 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006903 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006904{
6905 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006907 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006908 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006909 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03006910 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01006911 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006912 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02006913 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08006914
6915 for_each_encoder_on_crtc(dev, crtc, encoder) {
6916 switch (encoder->type) {
6917 case INTEL_OUTPUT_LVDS:
6918 is_lvds = true;
6919 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006920 }
6921
6922 num_connectors++;
6923 }
6924
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006925 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6926 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6927
Daniel Vetterff9a6752013-06-01 17:16:21 +02006928 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006929 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02006930 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006931 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6932 return -EINVAL;
6933 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01006934 /* Compat-code for transition, will disappear. */
6935 if (!intel_crtc->config.clock_set) {
6936 intel_crtc->config.dpll.n = clock.n;
6937 intel_crtc->config.dpll.m1 = clock.m1;
6938 intel_crtc->config.dpll.m2 = clock.m2;
6939 intel_crtc->config.dpll.p1 = clock.p1;
6940 intel_crtc->config.dpll.p2 = clock.p2;
6941 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006942
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006943 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01006944 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006945 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006946 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006947 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006948
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006949 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006950 &fp, &reduced_clock,
6951 has_reduced_clock ? &fp2 : NULL);
6952
Daniel Vetter959e16d2013-06-05 13:34:21 +02006953 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02006954 intel_crtc->config.dpll_hw_state.fp0 = fp;
6955 if (has_reduced_clock)
6956 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6957 else
6958 intel_crtc->config.dpll_hw_state.fp1 = fp;
6959
Daniel Vetterb89a1d32013-06-05 13:34:24 +02006960 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006961 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03006962 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02006963 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07006964 return -EINVAL;
6965 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006966 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02006967 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006968
Jani Nikulad330a952014-01-21 11:24:25 +02006969 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02006970 intel_crtc->lowfreq_avail = true;
6971 else
6972 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02006973
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006974 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006975}
6976
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006977static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6978 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02006979{
6980 struct drm_device *dev = crtc->base.dev;
6981 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006982 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02006983
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006984 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6985 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6986 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6987 & ~TU_SIZE_MASK;
6988 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6989 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6990 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6991}
6992
6993static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6994 enum transcoder transcoder,
6995 struct intel_link_m_n *m_n)
6996{
6997 struct drm_device *dev = crtc->base.dev;
6998 struct drm_i915_private *dev_priv = dev->dev_private;
6999 enum pipe pipe = crtc->pipe;
7000
7001 if (INTEL_INFO(dev)->gen >= 5) {
7002 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7003 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7004 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7005 & ~TU_SIZE_MASK;
7006 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7007 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7008 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7009 } else {
7010 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7011 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7012 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7013 & ~TU_SIZE_MASK;
7014 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7015 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7016 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7017 }
7018}
7019
7020void intel_dp_get_m_n(struct intel_crtc *crtc,
7021 struct intel_crtc_config *pipe_config)
7022{
7023 if (crtc->config.has_pch_encoder)
7024 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7025 else
7026 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7027 &pipe_config->dp_m_n);
7028}
7029
Daniel Vetter72419202013-04-04 13:28:53 +02007030static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7031 struct intel_crtc_config *pipe_config)
7032{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007033 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7034 &pipe_config->fdi_m_n);
Daniel Vetter72419202013-04-04 13:28:53 +02007035}
7036
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007037static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7038 struct intel_crtc_config *pipe_config)
7039{
7040 struct drm_device *dev = crtc->base.dev;
7041 struct drm_i915_private *dev_priv = dev->dev_private;
7042 uint32_t tmp;
7043
7044 tmp = I915_READ(PF_CTL(crtc->pipe));
7045
7046 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007047 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007048 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7049 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007050
7051 /* We currently do not free assignements of panel fitters on
7052 * ivb/hsw (since we don't use the higher upscaling modes which
7053 * differentiates them) so just WARN about this case for now. */
7054 if (IS_GEN7(dev)) {
7055 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7056 PF_PIPE_SEL_IVB(crtc->pipe));
7057 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007058 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007059}
7060
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007061static void ironlake_get_plane_config(struct intel_crtc *crtc,
7062 struct intel_plane_config *plane_config)
7063{
7064 struct drm_device *dev = crtc->base.dev;
7065 struct drm_i915_private *dev_priv = dev->dev_private;
7066 u32 val, base, offset;
7067 int pipe = crtc->pipe, plane = crtc->plane;
7068 int fourcc, pixel_format;
7069 int aligned_height;
7070
Dave Airlie66e514c2014-04-03 07:51:54 +10007071 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7072 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007073 DRM_DEBUG_KMS("failed to alloc fb\n");
7074 return;
7075 }
7076
7077 val = I915_READ(DSPCNTR(plane));
7078
7079 if (INTEL_INFO(dev)->gen >= 4)
7080 if (val & DISPPLANE_TILED)
7081 plane_config->tiled = true;
7082
7083 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7084 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007085 crtc->base.primary->fb->pixel_format = fourcc;
7086 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007087 drm_format_plane_cpp(fourcc, 0) * 8;
7088
7089 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7090 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7091 offset = I915_READ(DSPOFFSET(plane));
7092 } else {
7093 if (plane_config->tiled)
7094 offset = I915_READ(DSPTILEOFF(plane));
7095 else
7096 offset = I915_READ(DSPLINOFF(plane));
7097 }
7098 plane_config->base = base;
7099
7100 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007101 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7102 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007103
7104 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007105 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007106
Dave Airlie66e514c2014-04-03 07:51:54 +10007107 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007108 plane_config->tiled);
7109
Dave Airlie66e514c2014-04-03 07:51:54 +10007110 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007111 aligned_height, PAGE_SIZE);
7112
7113 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007114 pipe, plane, crtc->base.primary->fb->width,
7115 crtc->base.primary->fb->height,
7116 crtc->base.primary->fb->bits_per_pixel, base,
7117 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007118 plane_config->size);
7119}
7120
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007121static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7122 struct intel_crtc_config *pipe_config)
7123{
7124 struct drm_device *dev = crtc->base.dev;
7125 struct drm_i915_private *dev_priv = dev->dev_private;
7126 uint32_t tmp;
7127
Daniel Vettere143a212013-07-04 12:01:15 +02007128 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007129 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007130
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007131 tmp = I915_READ(PIPECONF(crtc->pipe));
7132 if (!(tmp & PIPECONF_ENABLE))
7133 return false;
7134
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007135 switch (tmp & PIPECONF_BPC_MASK) {
7136 case PIPECONF_6BPC:
7137 pipe_config->pipe_bpp = 18;
7138 break;
7139 case PIPECONF_8BPC:
7140 pipe_config->pipe_bpp = 24;
7141 break;
7142 case PIPECONF_10BPC:
7143 pipe_config->pipe_bpp = 30;
7144 break;
7145 case PIPECONF_12BPC:
7146 pipe_config->pipe_bpp = 36;
7147 break;
7148 default:
7149 break;
7150 }
7151
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007152 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7153 pipe_config->limited_color_range = true;
7154
Daniel Vetterab9412b2013-05-03 11:49:46 +02007155 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007156 struct intel_shared_dpll *pll;
7157
Daniel Vetter88adfff2013-03-28 10:42:01 +01007158 pipe_config->has_pch_encoder = true;
7159
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007160 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7161 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7162 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007163
7164 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007165
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007166 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007167 pipe_config->shared_dpll =
7168 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007169 } else {
7170 tmp = I915_READ(PCH_DPLL_SEL);
7171 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7172 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7173 else
7174 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7175 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007176
7177 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7178
7179 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7180 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007181
7182 tmp = pipe_config->dpll_hw_state.dpll;
7183 pipe_config->pixel_multiplier =
7184 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7185 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007186
7187 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007188 } else {
7189 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007190 }
7191
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007192 intel_get_pipe_timings(crtc, pipe_config);
7193
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007194 ironlake_get_pfit_config(crtc, pipe_config);
7195
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007196 return true;
7197}
7198
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007199static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7200{
7201 struct drm_device *dev = dev_priv->dev;
7202 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7203 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007204
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007205 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007206 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007207 pipe_name(crtc->pipe));
7208
7209 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7210 WARN(plls->spll_refcount, "SPLL enabled\n");
7211 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7212 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7213 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7214 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7215 "CPU PWM1 enabled\n");
7216 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7217 "CPU PWM2 enabled\n");
7218 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7219 "PCH PWM1 enabled\n");
7220 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7221 "Utility pin enabled\n");
7222 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7223
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007224 /*
7225 * In theory we can still leave IRQs enabled, as long as only the HPD
7226 * interrupts remain enabled. We used to check for that, but since it's
7227 * gen-specific and since we only disable LCPLL after we fully disable
7228 * the interrupts, the check below should be enough.
7229 */
7230 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007231}
7232
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007233static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7234{
7235 struct drm_device *dev = dev_priv->dev;
7236
7237 if (IS_HASWELL(dev)) {
7238 mutex_lock(&dev_priv->rps.hw_lock);
7239 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7240 val))
7241 DRM_ERROR("Failed to disable D_COMP\n");
7242 mutex_unlock(&dev_priv->rps.hw_lock);
7243 } else {
7244 I915_WRITE(D_COMP, val);
7245 }
7246 POSTING_READ(D_COMP);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007247}
7248
7249/*
7250 * This function implements pieces of two sequences from BSpec:
7251 * - Sequence for display software to disable LCPLL
7252 * - Sequence for display software to allow package C8+
7253 * The steps implemented here are just the steps that actually touch the LCPLL
7254 * register. Callers should take care of disabling all the display engine
7255 * functions, doing the mode unset, fixing interrupts, etc.
7256 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007257static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7258 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007259{
7260 uint32_t val;
7261
7262 assert_can_disable_lcpll(dev_priv);
7263
7264 val = I915_READ(LCPLL_CTL);
7265
7266 if (switch_to_fclk) {
7267 val |= LCPLL_CD_SOURCE_FCLK;
7268 I915_WRITE(LCPLL_CTL, val);
7269
7270 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7271 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7272 DRM_ERROR("Switching to FCLK failed\n");
7273
7274 val = I915_READ(LCPLL_CTL);
7275 }
7276
7277 val |= LCPLL_PLL_DISABLE;
7278 I915_WRITE(LCPLL_CTL, val);
7279 POSTING_READ(LCPLL_CTL);
7280
7281 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7282 DRM_ERROR("LCPLL still locked\n");
7283
7284 val = I915_READ(D_COMP);
7285 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007286 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007287 ndelay(100);
7288
7289 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7290 DRM_ERROR("D_COMP RCOMP still in progress\n");
7291
7292 if (allow_power_down) {
7293 val = I915_READ(LCPLL_CTL);
7294 val |= LCPLL_POWER_DOWN_ALLOW;
7295 I915_WRITE(LCPLL_CTL, val);
7296 POSTING_READ(LCPLL_CTL);
7297 }
7298}
7299
7300/*
7301 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7302 * source.
7303 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007304static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007305{
7306 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007307 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007308
7309 val = I915_READ(LCPLL_CTL);
7310
7311 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7312 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7313 return;
7314
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007315 /*
7316 * Make sure we're not on PC8 state before disabling PC8, otherwise
7317 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7318 *
7319 * The other problem is that hsw_restore_lcpll() is called as part of
7320 * the runtime PM resume sequence, so we can't just call
7321 * gen6_gt_force_wake_get() because that function calls
7322 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7323 * while we are on the resume sequence. So to solve this problem we have
7324 * to call special forcewake code that doesn't touch runtime PM and
7325 * doesn't enable the forcewake delayed work.
7326 */
7327 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7328 if (dev_priv->uncore.forcewake_count++ == 0)
7329 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7330 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007331
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007332 if (val & LCPLL_POWER_DOWN_ALLOW) {
7333 val &= ~LCPLL_POWER_DOWN_ALLOW;
7334 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007335 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007336 }
7337
7338 val = I915_READ(D_COMP);
7339 val |= D_COMP_COMP_FORCE;
7340 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007341 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007342
7343 val = I915_READ(LCPLL_CTL);
7344 val &= ~LCPLL_PLL_DISABLE;
7345 I915_WRITE(LCPLL_CTL, val);
7346
7347 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7348 DRM_ERROR("LCPLL not locked yet\n");
7349
7350 if (val & LCPLL_CD_SOURCE_FCLK) {
7351 val = I915_READ(LCPLL_CTL);
7352 val &= ~LCPLL_CD_SOURCE_FCLK;
7353 I915_WRITE(LCPLL_CTL, val);
7354
7355 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7356 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7357 DRM_ERROR("Switching back to LCPLL failed\n");
7358 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007359
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007360 /* See the big comment above. */
7361 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7362 if (--dev_priv->uncore.forcewake_count == 0)
7363 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7364 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007365}
7366
Paulo Zanoni765dab672014-03-07 20:08:18 -03007367/*
7368 * Package states C8 and deeper are really deep PC states that can only be
7369 * reached when all the devices on the system allow it, so even if the graphics
7370 * device allows PC8+, it doesn't mean the system will actually get to these
7371 * states. Our driver only allows PC8+ when going into runtime PM.
7372 *
7373 * The requirements for PC8+ are that all the outputs are disabled, the power
7374 * well is disabled and most interrupts are disabled, and these are also
7375 * requirements for runtime PM. When these conditions are met, we manually do
7376 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7377 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7378 * hang the machine.
7379 *
7380 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7381 * the state of some registers, so when we come back from PC8+ we need to
7382 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7383 * need to take care of the registers kept by RC6. Notice that this happens even
7384 * if we don't put the device in PCI D3 state (which is what currently happens
7385 * because of the runtime PM support).
7386 *
7387 * For more, read "Display Sequences for Package C8" on the hardware
7388 * documentation.
7389 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007390void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007391{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007392 struct drm_device *dev = dev_priv->dev;
7393 uint32_t val;
7394
Paulo Zanonic67a4702013-08-19 13:18:09 -03007395 DRM_DEBUG_KMS("Enabling package C8+\n");
7396
Paulo Zanonic67a4702013-08-19 13:18:09 -03007397 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7398 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7399 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7400 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7401 }
7402
7403 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007404 hsw_disable_lcpll(dev_priv, true, true);
7405}
7406
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007407void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007408{
7409 struct drm_device *dev = dev_priv->dev;
7410 uint32_t val;
7411
Paulo Zanonic67a4702013-08-19 13:18:09 -03007412 DRM_DEBUG_KMS("Disabling package C8+\n");
7413
7414 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007415 lpt_init_pch_refclk(dev);
7416
7417 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7418 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7419 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7420 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7421 }
7422
7423 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007424}
7425
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007426static void snb_modeset_global_resources(struct drm_device *dev)
7427{
7428 modeset_update_crtc_power_domains(dev);
7429}
7430
Imre Deak4f074122013-10-16 17:25:51 +03007431static void haswell_modeset_global_resources(struct drm_device *dev)
7432{
Paulo Zanonida723562013-12-19 11:54:51 -02007433 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007434}
7435
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007436static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007437 int x, int y,
7438 struct drm_framebuffer *fb)
7439{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007441
Paulo Zanoni566b7342013-11-25 15:27:08 -02007442 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007443 return -EINVAL;
Paulo Zanoni566b7342013-11-25 15:27:08 -02007444 intel_ddi_pll_enable(intel_crtc);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007445
Daniel Vetter644cef32014-04-24 23:55:07 +02007446 intel_crtc->lowfreq_avail = false;
7447
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007448 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007449}
7450
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007451static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7452 struct intel_crtc_config *pipe_config)
7453{
7454 struct drm_device *dev = crtc->base.dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007456 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007457 uint32_t tmp;
7458
Imre Deakb5482bd2014-03-05 16:20:55 +02007459 if (!intel_display_power_enabled(dev_priv,
7460 POWER_DOMAIN_PIPE(crtc->pipe)))
7461 return false;
7462
Daniel Vettere143a212013-07-04 12:01:15 +02007463 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007464 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7465
Daniel Vettereccb1402013-05-22 00:50:22 +02007466 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7467 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7468 enum pipe trans_edp_pipe;
7469 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7470 default:
7471 WARN(1, "unknown pipe linked to edp transcoder\n");
7472 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7473 case TRANS_DDI_EDP_INPUT_A_ON:
7474 trans_edp_pipe = PIPE_A;
7475 break;
7476 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7477 trans_edp_pipe = PIPE_B;
7478 break;
7479 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7480 trans_edp_pipe = PIPE_C;
7481 break;
7482 }
7483
7484 if (trans_edp_pipe == crtc->pipe)
7485 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7486 }
7487
Imre Deakda7e29b2014-02-18 00:02:02 +02007488 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007489 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007490 return false;
7491
Daniel Vettereccb1402013-05-22 00:50:22 +02007492 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007493 if (!(tmp & PIPECONF_ENABLE))
7494 return false;
7495
Daniel Vetter88adfff2013-03-28 10:42:01 +01007496 /*
Paulo Zanonif196e6b2013-04-18 16:35:41 -03007497 * Haswell has only FDI/PCH transcoder A. It is which is connected to
Daniel Vetter88adfff2013-03-28 10:42:01 +01007498 * DDI E. So just check whether this pipe is wired to DDI E and whether
7499 * the PCH transcoder is on.
7500 */
Daniel Vettereccb1402013-05-22 00:50:22 +02007501 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
Daniel Vetter88adfff2013-03-28 10:42:01 +01007502 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
Daniel Vetterab9412b2013-05-03 11:49:46 +02007503 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01007504 pipe_config->has_pch_encoder = true;
7505
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007506 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7507 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7508 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007509
7510 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007511 }
7512
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007513 intel_get_pipe_timings(crtc, pipe_config);
7514
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007515 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007516 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007517 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007518
Jesse Barnese59150d2014-01-07 13:30:45 -08007519 if (IS_HASWELL(dev))
7520 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7521 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007522
Daniel Vetter6c49f242013-06-06 12:45:25 +02007523 pipe_config->pixel_multiplier = 1;
7524
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007525 return true;
7526}
7527
Jani Nikula1a915102013-10-16 12:34:48 +03007528static struct {
7529 int clock;
7530 u32 config;
7531} hdmi_audio_clock[] = {
7532 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7533 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7534 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7535 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7536 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7537 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7538 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7539 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7540 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7541 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7542};
7543
7544/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7545static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7546{
7547 int i;
7548
7549 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7550 if (mode->clock == hdmi_audio_clock[i].clock)
7551 break;
7552 }
7553
7554 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7555 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7556 i = 1;
7557 }
7558
7559 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7560 hdmi_audio_clock[i].clock,
7561 hdmi_audio_clock[i].config);
7562
7563 return hdmi_audio_clock[i].config;
7564}
7565
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007566static bool intel_eld_uptodate(struct drm_connector *connector,
7567 int reg_eldv, uint32_t bits_eldv,
7568 int reg_elda, uint32_t bits_elda,
7569 int reg_edid)
7570{
7571 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7572 uint8_t *eld = connector->eld;
7573 uint32_t i;
7574
7575 i = I915_READ(reg_eldv);
7576 i &= bits_eldv;
7577
7578 if (!eld[0])
7579 return !i;
7580
7581 if (!i)
7582 return false;
7583
7584 i = I915_READ(reg_elda);
7585 i &= ~bits_elda;
7586 I915_WRITE(reg_elda, i);
7587
7588 for (i = 0; i < eld[2]; i++)
7589 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7590 return false;
7591
7592 return true;
7593}
7594
Wu Fengguange0dac652011-09-05 14:25:34 +08007595static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007596 struct drm_crtc *crtc,
7597 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007598{
7599 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7600 uint8_t *eld = connector->eld;
7601 uint32_t eldv;
7602 uint32_t len;
7603 uint32_t i;
7604
7605 i = I915_READ(G4X_AUD_VID_DID);
7606
7607 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7608 eldv = G4X_ELDV_DEVCL_DEVBLC;
7609 else
7610 eldv = G4X_ELDV_DEVCTG;
7611
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007612 if (intel_eld_uptodate(connector,
7613 G4X_AUD_CNTL_ST, eldv,
7614 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7615 G4X_HDMIW_HDMIEDID))
7616 return;
7617
Wu Fengguange0dac652011-09-05 14:25:34 +08007618 i = I915_READ(G4X_AUD_CNTL_ST);
7619 i &= ~(eldv | G4X_ELD_ADDR);
7620 len = (i >> 9) & 0x1f; /* ELD buffer size */
7621 I915_WRITE(G4X_AUD_CNTL_ST, i);
7622
7623 if (!eld[0])
7624 return;
7625
7626 len = min_t(uint8_t, eld[2], len);
7627 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7628 for (i = 0; i < len; i++)
7629 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7630
7631 i = I915_READ(G4X_AUD_CNTL_ST);
7632 i |= eldv;
7633 I915_WRITE(G4X_AUD_CNTL_ST, i);
7634}
7635
Wang Xingchao83358c852012-08-16 22:43:37 +08007636static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007637 struct drm_crtc *crtc,
7638 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007639{
7640 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7641 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007642 uint32_t eldv;
7643 uint32_t i;
7644 int len;
7645 int pipe = to_intel_crtc(crtc)->pipe;
7646 int tmp;
7647
7648 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7649 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7650 int aud_config = HSW_AUD_CFG(pipe);
7651 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7652
Wang Xingchao83358c852012-08-16 22:43:37 +08007653 /* Audio output enable */
7654 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7655 tmp = I915_READ(aud_cntrl_st2);
7656 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7657 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007658 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007659
Daniel Vetterc7905792014-04-16 16:56:09 +02007660 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007661
7662 /* Set ELD valid state */
7663 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007664 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007665 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7666 I915_WRITE(aud_cntrl_st2, tmp);
7667 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007668 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007669
7670 /* Enable HDMI mode */
7671 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007672 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007673 /* clear N_programing_enable and N_value_index */
7674 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7675 I915_WRITE(aud_config, tmp);
7676
7677 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7678
7679 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7680
7681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7682 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7683 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7684 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007685 } else {
7686 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7687 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007688
7689 if (intel_eld_uptodate(connector,
7690 aud_cntrl_st2, eldv,
7691 aud_cntl_st, IBX_ELD_ADDRESS,
7692 hdmiw_hdmiedid))
7693 return;
7694
7695 i = I915_READ(aud_cntrl_st2);
7696 i &= ~eldv;
7697 I915_WRITE(aud_cntrl_st2, i);
7698
7699 if (!eld[0])
7700 return;
7701
7702 i = I915_READ(aud_cntl_st);
7703 i &= ~IBX_ELD_ADDRESS;
7704 I915_WRITE(aud_cntl_st, i);
7705 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7706 DRM_DEBUG_DRIVER("port num:%d\n", i);
7707
7708 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7709 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7710 for (i = 0; i < len; i++)
7711 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7712
7713 i = I915_READ(aud_cntrl_st2);
7714 i |= eldv;
7715 I915_WRITE(aud_cntrl_st2, i);
7716
7717}
7718
Wu Fengguange0dac652011-09-05 14:25:34 +08007719static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007720 struct drm_crtc *crtc,
7721 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007722{
7723 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7724 uint8_t *eld = connector->eld;
7725 uint32_t eldv;
7726 uint32_t i;
7727 int len;
7728 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007729 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007730 int aud_cntl_st;
7731 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007732 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007733
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007734 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007735 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7736 aud_config = IBX_AUD_CFG(pipe);
7737 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007738 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007739 } else if (IS_VALLEYVIEW(connector->dev)) {
7740 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7741 aud_config = VLV_AUD_CFG(pipe);
7742 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7743 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007744 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007745 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7746 aud_config = CPT_AUD_CFG(pipe);
7747 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007748 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007749 }
7750
Wang Xingchao9b138a82012-08-09 16:52:18 +08007751 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007752
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007753 if (IS_VALLEYVIEW(connector->dev)) {
7754 struct intel_encoder *intel_encoder;
7755 struct intel_digital_port *intel_dig_port;
7756
7757 intel_encoder = intel_attached_encoder(connector);
7758 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7759 i = intel_dig_port->port;
7760 } else {
7761 i = I915_READ(aud_cntl_st);
7762 i = (i >> 29) & DIP_PORT_SEL_MASK;
7763 /* DIP_Port_Select, 0x1 = PortB */
7764 }
7765
Wu Fengguange0dac652011-09-05 14:25:34 +08007766 if (!i) {
7767 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7768 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007769 eldv = IBX_ELD_VALIDB;
7770 eldv |= IBX_ELD_VALIDB << 4;
7771 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08007772 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03007773 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007774 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08007775 }
7776
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007777 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7778 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7779 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06007780 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007781 } else {
7782 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7783 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007784
7785 if (intel_eld_uptodate(connector,
7786 aud_cntrl_st2, eldv,
7787 aud_cntl_st, IBX_ELD_ADDRESS,
7788 hdmiw_hdmiedid))
7789 return;
7790
Wu Fengguange0dac652011-09-05 14:25:34 +08007791 i = I915_READ(aud_cntrl_st2);
7792 i &= ~eldv;
7793 I915_WRITE(aud_cntrl_st2, i);
7794
7795 if (!eld[0])
7796 return;
7797
Wu Fengguange0dac652011-09-05 14:25:34 +08007798 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007799 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08007800 I915_WRITE(aud_cntl_st, i);
7801
7802 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7803 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7804 for (i = 0; i < len; i++)
7805 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7806
7807 i = I915_READ(aud_cntrl_st2);
7808 i |= eldv;
7809 I915_WRITE(aud_cntrl_st2, i);
7810}
7811
7812void intel_write_eld(struct drm_encoder *encoder,
7813 struct drm_display_mode *mode)
7814{
7815 struct drm_crtc *crtc = encoder->crtc;
7816 struct drm_connector *connector;
7817 struct drm_device *dev = encoder->dev;
7818 struct drm_i915_private *dev_priv = dev->dev_private;
7819
7820 connector = drm_select_eld(encoder, mode);
7821 if (!connector)
7822 return;
7823
7824 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7825 connector->base.id,
7826 drm_get_connector_name(connector),
7827 connector->encoder->base.id,
7828 drm_get_encoder_name(connector->encoder));
7829
7830 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7831
7832 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03007833 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08007834}
7835
Chris Wilson560b85b2010-08-07 11:01:38 +01007836static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7837{
7838 struct drm_device *dev = crtc->dev;
7839 struct drm_i915_private *dev_priv = dev->dev_private;
7840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7841 bool visible = base != 0;
7842 u32 cntl;
7843
7844 if (intel_crtc->cursor_visible == visible)
7845 return;
7846
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007847 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01007848 if (visible) {
7849 /* On these chipsets we can only modify the base whilst
7850 * the cursor is disabled.
7851 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007852 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01007853
7854 cntl &= ~(CURSOR_FORMAT_MASK);
7855 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7856 cntl |= CURSOR_ENABLE |
7857 CURSOR_GAMMA_ENABLE |
7858 CURSOR_FORMAT_ARGB;
7859 } else
7860 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007861 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01007862
7863 intel_crtc->cursor_visible = visible;
7864}
7865
7866static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7867{
7868 struct drm_device *dev = crtc->dev;
7869 struct drm_i915_private *dev_priv = dev->dev_private;
7870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7871 int pipe = intel_crtc->pipe;
7872 bool visible = base != 0;
7873
7874 if (intel_crtc->cursor_visible != visible) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307875 int16_t width = intel_crtc->cursor_width;
Jesse Barnes548f2452011-02-17 10:40:53 -08007876 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01007877 if (base) {
7878 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307879 cntl |= MCURSOR_GAMMA_ENABLE;
7880
7881 switch (width) {
7882 case 64:
7883 cntl |= CURSOR_MODE_64_ARGB_AX;
7884 break;
7885 case 128:
7886 cntl |= CURSOR_MODE_128_ARGB_AX;
7887 break;
7888 case 256:
7889 cntl |= CURSOR_MODE_256_ARGB_AX;
7890 break;
7891 default:
7892 WARN_ON(1);
7893 return;
7894 }
Chris Wilson560b85b2010-08-07 11:01:38 +01007895 cntl |= pipe << 28; /* Connect to correct pipe */
7896 } else {
7897 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7898 cntl |= CURSOR_MODE_DISABLE;
7899 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007900 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01007901
7902 intel_crtc->cursor_visible = visible;
7903 }
7904 /* and commit changes on next vblank */
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007905 POSTING_READ(CURCNTR(pipe));
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007906 I915_WRITE(CURBASE(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007907 POSTING_READ(CURBASE(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01007908}
7909
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007910static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7911{
7912 struct drm_device *dev = crtc->dev;
7913 struct drm_i915_private *dev_priv = dev->dev_private;
7914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7915 int pipe = intel_crtc->pipe;
7916 bool visible = base != 0;
7917
7918 if (intel_crtc->cursor_visible != visible) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307919 int16_t width = intel_crtc->cursor_width;
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007920 uint32_t cntl = I915_READ(CURCNTR(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007921 if (base) {
7922 cntl &= ~CURSOR_MODE;
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307923 cntl |= MCURSOR_GAMMA_ENABLE;
7924 switch (width) {
7925 case 64:
7926 cntl |= CURSOR_MODE_64_ARGB_AX;
7927 break;
7928 case 128:
7929 cntl |= CURSOR_MODE_128_ARGB_AX;
7930 break;
7931 case 256:
7932 cntl |= CURSOR_MODE_256_ARGB_AX;
7933 break;
7934 default:
7935 WARN_ON(1);
7936 return;
7937 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007938 } else {
7939 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7940 cntl |= CURSOR_MODE_DISABLE;
7941 }
Ville Syrjälä6bbfa1c2013-11-02 21:07:39 -07007942 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007943 cntl |= CURSOR_PIPE_CSC_ENABLE;
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03007944 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7945 }
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007946 I915_WRITE(CURCNTR(pipe), cntl);
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007947
7948 intel_crtc->cursor_visible = visible;
7949 }
7950 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007951 POSTING_READ(CURCNTR(pipe));
7952 I915_WRITE(CURBASE(pipe), base);
7953 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007954}
7955
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007956/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01007957static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7958 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007959{
7960 struct drm_device *dev = crtc->dev;
7961 struct drm_i915_private *dev_priv = dev->dev_private;
7962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7963 int pipe = intel_crtc->pipe;
7964 int x = intel_crtc->cursor_x;
7965 int y = intel_crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007966 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007967 bool visible;
7968
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007969 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007970 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007971
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007972 if (x >= intel_crtc->config.pipe_src_w)
7973 base = 0;
7974
7975 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007976 base = 0;
7977
7978 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03007979 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007980 base = 0;
7981
7982 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7983 x = -x;
7984 }
7985 pos |= x << CURSOR_X_SHIFT;
7986
7987 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03007988 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007989 base = 0;
7990
7991 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7992 y = -y;
7993 }
7994 pos |= y << CURSOR_Y_SHIFT;
7995
7996 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01007997 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007998 return;
7999
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008000 I915_WRITE(CURPOS(pipe), pos);
8001
8002 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008003 ivb_update_cursor(crtc, base);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008004 else if (IS_845G(dev) || IS_I865G(dev))
8005 i845_update_cursor(crtc, base);
8006 else
8007 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008008}
8009
Jesse Barnes79e53942008-11-07 14:24:08 -08008010static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00008011 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08008012 uint32_t handle,
8013 uint32_t width, uint32_t height)
8014{
8015 struct drm_device *dev = crtc->dev;
8016 struct drm_i915_private *dev_priv = dev->dev_private;
8017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00008018 struct drm_i915_gem_object *obj;
Chris Wilson64f962e2014-03-26 12:38:15 +00008019 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008020 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008021 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008022
Jesse Barnes79e53942008-11-07 14:24:08 -08008023 /* if we want to turn off the cursor ignore width and height */
8024 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008025 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008026 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008027 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008028 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008029 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008030 }
8031
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308032 /* Check for which cursor types we support */
8033 if (!((width == 64 && height == 64) ||
8034 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8035 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8036 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008037 return -EINVAL;
8038 }
8039
Chris Wilson05394f32010-11-08 19:18:58 +00008040 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00008041 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08008042 return -ENOENT;
8043
Chris Wilson05394f32010-11-08 19:18:58 +00008044 if (obj->base.size < width * height * 4) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008045 DRM_DEBUG_KMS("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008046 ret = -ENOMEM;
8047 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008048 }
8049
Dave Airlie71acb5e2008-12-30 20:31:46 +10008050 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008051 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008052 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008053 unsigned alignment;
8054
Chris Wilsond9e86c02010-11-10 16:40:20 +00008055 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008056 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008057 ret = -EINVAL;
8058 goto fail_locked;
8059 }
8060
Chris Wilson693db182013-03-05 14:52:39 +00008061 /* Note that the w/a also requires 2 PTE of padding following
8062 * the bo. We currently fill all unused PTE with the shadow
8063 * page and so we should always have valid PTE following the
8064 * cursor preventing the VT-d warning.
8065 */
8066 alignment = 0;
8067 if (need_vtd_wa(dev))
8068 alignment = 64*1024;
8069
8070 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008071 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008072 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008073 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008074 }
8075
Chris Wilsond9e86c02010-11-10 16:40:20 +00008076 ret = i915_gem_object_put_fence(obj);
8077 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008078 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008079 goto fail_unpin;
8080 }
8081
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008082 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008083 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008084 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00008085 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008086 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8087 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008088 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008089 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008090 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008091 }
Chris Wilson05394f32010-11-08 19:18:58 +00008092 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008093 }
8094
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008095 if (IS_GEN2(dev))
Jesse Barnes14b603912009-05-20 16:47:08 -04008096 I915_WRITE(CURSIZE, (height << 12) | width);
8097
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008098 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008099 if (intel_crtc->cursor_bo) {
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008100 if (INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00008101 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10008102 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8103 } else
Chris Wilsoncc98b412013-08-09 12:25:09 +01008104 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00008105 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008106 }
Jesse Barnes80824002009-09-10 15:28:06 -07008107
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008108 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008109
Chris Wilson64f962e2014-03-26 12:38:15 +00008110 old_width = intel_crtc->cursor_width;
8111
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008112 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008113 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008114 intel_crtc->cursor_width = width;
8115 intel_crtc->cursor_height = height;
8116
Chris Wilson64f962e2014-03-26 12:38:15 +00008117 if (intel_crtc->active) {
8118 if (old_width != width)
8119 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f7712013-09-17 18:33:44 +03008120 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008121 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008122
Jesse Barnes79e53942008-11-07 14:24:08 -08008123 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008124fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008125 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008126fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008127 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008128fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008129 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008130 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008131}
8132
8133static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8134{
Jesse Barnes79e53942008-11-07 14:24:08 -08008135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008136
Ville Syrjälä92e76c82013-10-21 19:01:58 +03008137 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8138 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
Jesse Barnes652c3932009-08-17 13:31:43 -07008139
Ville Syrjäläf2f5f7712013-09-17 18:33:44 +03008140 if (intel_crtc->active)
8141 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08008142
8143 return 0;
8144}
8145
Jesse Barnes79e53942008-11-07 14:24:08 -08008146static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008147 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008148{
James Simmons72034252010-08-03 01:33:19 +01008149 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008151
James Simmons72034252010-08-03 01:33:19 +01008152 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008153 intel_crtc->lut_r[i] = red[i] >> 8;
8154 intel_crtc->lut_g[i] = green[i] >> 8;
8155 intel_crtc->lut_b[i] = blue[i] >> 8;
8156 }
8157
8158 intel_crtc_load_lut(crtc);
8159}
8160
Jesse Barnes79e53942008-11-07 14:24:08 -08008161/* VESA 640x480x72Hz mode to set on the pipe */
8162static struct drm_display_mode load_detect_mode = {
8163 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8164 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8165};
8166
Daniel Vettera8bb6812014-02-10 18:00:39 +01008167struct drm_framebuffer *
8168__intel_framebuffer_create(struct drm_device *dev,
8169 struct drm_mode_fb_cmd2 *mode_cmd,
8170 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008171{
8172 struct intel_framebuffer *intel_fb;
8173 int ret;
8174
8175 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8176 if (!intel_fb) {
8177 drm_gem_object_unreference_unlocked(&obj->base);
8178 return ERR_PTR(-ENOMEM);
8179 }
8180
8181 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008182 if (ret)
8183 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008184
8185 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008186err:
8187 drm_gem_object_unreference_unlocked(&obj->base);
8188 kfree(intel_fb);
8189
8190 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008191}
8192
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008193static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008194intel_framebuffer_create(struct drm_device *dev,
8195 struct drm_mode_fb_cmd2 *mode_cmd,
8196 struct drm_i915_gem_object *obj)
8197{
8198 struct drm_framebuffer *fb;
8199 int ret;
8200
8201 ret = i915_mutex_lock_interruptible(dev);
8202 if (ret)
8203 return ERR_PTR(ret);
8204 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8205 mutex_unlock(&dev->struct_mutex);
8206
8207 return fb;
8208}
8209
Chris Wilsond2dff872011-04-19 08:36:26 +01008210static u32
8211intel_framebuffer_pitch_for_width(int width, int bpp)
8212{
8213 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8214 return ALIGN(pitch, 64);
8215}
8216
8217static u32
8218intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8219{
8220 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8221 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8222}
8223
8224static struct drm_framebuffer *
8225intel_framebuffer_create_for_mode(struct drm_device *dev,
8226 struct drm_display_mode *mode,
8227 int depth, int bpp)
8228{
8229 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008230 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008231
8232 obj = i915_gem_alloc_object(dev,
8233 intel_framebuffer_size_for_mode(mode, bpp));
8234 if (obj == NULL)
8235 return ERR_PTR(-ENOMEM);
8236
8237 mode_cmd.width = mode->hdisplay;
8238 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008239 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8240 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008241 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008242
8243 return intel_framebuffer_create(dev, &mode_cmd, obj);
8244}
8245
8246static struct drm_framebuffer *
8247mode_fits_in_fbdev(struct drm_device *dev,
8248 struct drm_display_mode *mode)
8249{
Daniel Vetter4520f532013-10-09 09:18:51 +02008250#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008251 struct drm_i915_private *dev_priv = dev->dev_private;
8252 struct drm_i915_gem_object *obj;
8253 struct drm_framebuffer *fb;
8254
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008255 if (!dev_priv->fbdev)
8256 return NULL;
8257
8258 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008259 return NULL;
8260
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008261 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008262 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008263
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008264 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008265 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8266 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008267 return NULL;
8268
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008269 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008270 return NULL;
8271
8272 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008273#else
8274 return NULL;
8275#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008276}
8277
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008278bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008279 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01008280 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008281{
8282 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008283 struct intel_encoder *intel_encoder =
8284 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008285 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008286 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008287 struct drm_crtc *crtc = NULL;
8288 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008289 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08008290 int i = -1;
8291
Chris Wilsond2dff872011-04-19 08:36:26 +01008292 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8293 connector->base.id, drm_get_connector_name(connector),
8294 encoder->base.id, drm_get_encoder_name(encoder));
8295
Jesse Barnes79e53942008-11-07 14:24:08 -08008296 /*
8297 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008298 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008299 * - if the connector already has an assigned crtc, use it (but make
8300 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008301 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008302 * - try to find the first unused crtc that can drive this connector,
8303 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008304 */
8305
8306 /* See if we already have a CRTC for this connector */
8307 if (encoder->crtc) {
8308 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008309
Daniel Vetter7b240562012-12-12 00:35:33 +01008310 mutex_lock(&crtc->mutex);
8311
Daniel Vetter24218aa2012-08-12 19:27:11 +02008312 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008313 old->load_detect_temp = false;
8314
8315 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008316 if (connector->dpms != DRM_MODE_DPMS_ON)
8317 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008318
Chris Wilson71731882011-04-19 23:10:58 +01008319 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008320 }
8321
8322 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008323 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008324 i++;
8325 if (!(encoder->possible_crtcs & (1 << i)))
8326 continue;
8327 if (!possible_crtc->enabled) {
8328 crtc = possible_crtc;
8329 break;
8330 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008331 }
8332
8333 /*
8334 * If we didn't find an unused CRTC, don't use any.
8335 */
8336 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008337 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8338 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008339 }
8340
Daniel Vetter7b240562012-12-12 00:35:33 +01008341 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02008342 intel_encoder->new_crtc = to_intel_crtc(crtc);
8343 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008344
8345 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008346 intel_crtc->new_enabled = true;
8347 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008348 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008349 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008350 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008351
Chris Wilson64927112011-04-20 07:25:26 +01008352 if (!mode)
8353 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008354
Chris Wilsond2dff872011-04-19 08:36:26 +01008355 /* We need a framebuffer large enough to accommodate all accesses
8356 * that the plane may generate whilst we perform load detection.
8357 * We can not rely on the fbcon either being present (we get called
8358 * during its initialisation to detect all boot displays, or it may
8359 * not even exist) or that it is large enough to satisfy the
8360 * requested mode.
8361 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008362 fb = mode_fits_in_fbdev(dev, mode);
8363 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008364 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008365 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8366 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008367 } else
8368 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008369 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008370 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008371 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008372 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008373
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008374 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008375 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008376 if (old->release_fb)
8377 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008378 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008379 }
Chris Wilson71731882011-04-19 23:10:58 +01008380
Jesse Barnes79e53942008-11-07 14:24:08 -08008381 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008382 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008383 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008384
8385 fail:
8386 intel_crtc->new_enabled = crtc->enabled;
8387 if (intel_crtc->new_enabled)
8388 intel_crtc->new_config = &intel_crtc->config;
8389 else
8390 intel_crtc->new_config = NULL;
8391 mutex_unlock(&crtc->mutex);
8392 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008393}
8394
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008395void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01008396 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008397{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008398 struct intel_encoder *intel_encoder =
8399 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008400 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008401 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008403
Chris Wilsond2dff872011-04-19 08:36:26 +01008404 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8405 connector->base.id, drm_get_connector_name(connector),
8406 encoder->base.id, drm_get_encoder_name(encoder));
8407
Chris Wilson8261b192011-04-19 23:18:09 +01008408 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008409 to_intel_connector(connector)->new_encoder = NULL;
8410 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008411 intel_crtc->new_enabled = false;
8412 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008413 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008414
Daniel Vetter36206362012-12-10 20:42:17 +01008415 if (old->release_fb) {
8416 drm_framebuffer_unregister_private(old->release_fb);
8417 drm_framebuffer_unreference(old->release_fb);
8418 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008419
Daniel Vetter67c96402013-01-23 16:25:09 +00008420 mutex_unlock(&crtc->mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01008421 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008422 }
8423
Eric Anholtc751ce42010-03-25 11:48:48 -07008424 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008425 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8426 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01008427
8428 mutex_unlock(&crtc->mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08008429}
8430
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008431static int i9xx_pll_refclk(struct drm_device *dev,
8432 const struct intel_crtc_config *pipe_config)
8433{
8434 struct drm_i915_private *dev_priv = dev->dev_private;
8435 u32 dpll = pipe_config->dpll_hw_state.dpll;
8436
8437 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008438 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008439 else if (HAS_PCH_SPLIT(dev))
8440 return 120000;
8441 else if (!IS_GEN2(dev))
8442 return 96000;
8443 else
8444 return 48000;
8445}
8446
Jesse Barnes79e53942008-11-07 14:24:08 -08008447/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008448static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8449 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008450{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008451 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008452 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008453 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008454 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008455 u32 fp;
8456 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008457 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008458
8459 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008460 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008461 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008462 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008463
8464 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008465 if (IS_PINEVIEW(dev)) {
8466 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8467 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008468 } else {
8469 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8470 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8471 }
8472
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008473 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008474 if (IS_PINEVIEW(dev))
8475 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8476 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008477 else
8478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008479 DPLL_FPA01_P1_POST_DIV_SHIFT);
8480
8481 switch (dpll & DPLL_MODE_MASK) {
8482 case DPLLB_MODE_DAC_SERIAL:
8483 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8484 5 : 10;
8485 break;
8486 case DPLLB_MODE_LVDS:
8487 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8488 7 : 14;
8489 break;
8490 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008491 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008492 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008493 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008494 }
8495
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008496 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008497 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008498 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008499 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008500 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008501 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008502 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008503
8504 if (is_lvds) {
8505 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8506 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008507
8508 if (lvds & LVDS_CLKB_POWER_UP)
8509 clock.p2 = 7;
8510 else
8511 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008512 } else {
8513 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8514 clock.p1 = 2;
8515 else {
8516 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8517 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8518 }
8519 if (dpll & PLL_P2_DIVIDE_BY_4)
8520 clock.p2 = 4;
8521 else
8522 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008523 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008524
8525 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008526 }
8527
Ville Syrjälä18442d02013-09-13 16:00:08 +03008528 /*
8529 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008530 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008531 * encoder's get_config() function.
8532 */
8533 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008534}
8535
Ville Syrjälä6878da02013-09-13 15:59:11 +03008536int intel_dotclock_calculate(int link_freq,
8537 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008538{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008539 /*
8540 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008541 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008542 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008543 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008544 *
8545 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008546 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008547 */
8548
Ville Syrjälä6878da02013-09-13 15:59:11 +03008549 if (!m_n->link_n)
8550 return 0;
8551
8552 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8553}
8554
Ville Syrjälä18442d02013-09-13 16:00:08 +03008555static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8556 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008557{
8558 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008559
8560 /* read out port_clock from the DPLL */
8561 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008562
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008563 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008564 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008565 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008566 * agree once we know their relationship in the encoder's
8567 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008568 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008569 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008570 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8571 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008572}
8573
8574/** Returns the currently programmed mode of the given pipe. */
8575struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8576 struct drm_crtc *crtc)
8577{
Jesse Barnes548f2452011-02-17 10:40:53 -08008578 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008580 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008581 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008582 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008583 int htot = I915_READ(HTOTAL(cpu_transcoder));
8584 int hsync = I915_READ(HSYNC(cpu_transcoder));
8585 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8586 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008587 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008588
8589 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8590 if (!mode)
8591 return NULL;
8592
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008593 /*
8594 * Construct a pipe_config sufficient for getting the clock info
8595 * back out of crtc_clock_get.
8596 *
8597 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8598 * to use a real value here instead.
8599 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008600 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008601 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008602 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8603 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8604 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008605 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8606
Ville Syrjälä773ae032013-09-23 17:48:20 +03008607 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008608 mode->hdisplay = (htot & 0xffff) + 1;
8609 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8610 mode->hsync_start = (hsync & 0xffff) + 1;
8611 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8612 mode->vdisplay = (vtot & 0xffff) + 1;
8613 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8614 mode->vsync_start = (vsync & 0xffff) + 1;
8615 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8616
8617 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008618
8619 return mode;
8620}
8621
Daniel Vetter3dec0092010-08-20 21:40:52 +02008622static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07008623{
8624 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008625 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8627 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008628 int dpll_reg = DPLL(pipe);
8629 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008630
Eric Anholtbad720f2009-10-22 16:11:14 -07008631 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008632 return;
8633
8634 if (!dev_priv->lvds_downclock_avail)
8635 return;
8636
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008637 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008638 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008639 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008640
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008641 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008642
8643 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8644 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008645 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008646
Jesse Barnes652c3932009-08-17 13:31:43 -07008647 dpll = I915_READ(dpll_reg);
8648 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008649 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008650 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008651}
8652
8653static void intel_decrease_pllclock(struct drm_crtc *crtc)
8654{
8655 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008656 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008658
Eric Anholtbad720f2009-10-22 16:11:14 -07008659 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008660 return;
8661
8662 if (!dev_priv->lvds_downclock_avail)
8663 return;
8664
8665 /*
8666 * Since this is called by a timer, we should never get here in
8667 * the manual case.
8668 */
8669 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008670 int pipe = intel_crtc->pipe;
8671 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008672 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008673
Zhao Yakui44d98a62009-10-09 11:39:40 +08008674 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008675
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008676 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008677
Chris Wilson074b5e12012-05-02 12:07:06 +01008678 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008679 dpll |= DISPLAY_RATE_SELECT_FPA1;
8680 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008681 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008682 dpll = I915_READ(dpll_reg);
8683 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008684 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008685 }
8686
8687}
8688
Chris Wilsonf047e392012-07-21 12:31:41 +01008689void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008690{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008691 struct drm_i915_private *dev_priv = dev->dev_private;
8692
Chris Wilsonf62a0072014-02-21 17:55:39 +00008693 if (dev_priv->mm.busy)
8694 return;
8695
Paulo Zanoni43694d62014-03-07 20:08:08 -03008696 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008697 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008698 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008699}
8700
8701void intel_mark_idle(struct drm_device *dev)
8702{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008703 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008704 struct drm_crtc *crtc;
8705
Chris Wilsonf62a0072014-02-21 17:55:39 +00008706 if (!dev_priv->mm.busy)
8707 return;
8708
8709 dev_priv->mm.busy = false;
8710
Jani Nikulad330a952014-01-21 11:24:25 +02008711 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008712 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008713
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008714 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008715 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008716 continue;
8717
8718 intel_decrease_pllclock(crtc);
8719 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008720
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008721 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008722 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008723
8724out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008725 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008726}
8727
Chris Wilsonc65355b2013-06-06 16:53:41 -03008728void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8729 struct intel_ring_buffer *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008730{
8731 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07008732 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07008733
Jani Nikulad330a952014-01-21 11:24:25 +02008734 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07008735 return;
8736
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008737 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008738 if (!crtc->primary->fb)
Jesse Barnes652c3932009-08-17 13:31:43 -07008739 continue;
8740
Matt Roperf4510a22014-04-01 15:22:40 -07008741 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
Chris Wilsonc65355b2013-06-06 16:53:41 -03008742 continue;
8743
8744 intel_increase_pllclock(crtc);
8745 if (ring && intel_fbc_enabled(dev))
8746 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07008747 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008748}
8749
Jesse Barnes79e53942008-11-07 14:24:08 -08008750static void intel_crtc_destroy(struct drm_crtc *crtc)
8751{
8752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008753 struct drm_device *dev = crtc->dev;
8754 struct intel_unpin_work *work;
8755 unsigned long flags;
8756
8757 spin_lock_irqsave(&dev->event_lock, flags);
8758 work = intel_crtc->unpin_work;
8759 intel_crtc->unpin_work = NULL;
8760 spin_unlock_irqrestore(&dev->event_lock, flags);
8761
8762 if (work) {
8763 cancel_work_sync(&work->work);
8764 kfree(work);
8765 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008766
Mika Kuoppala40ccc722013-04-23 17:27:08 +03008767 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8768
Jesse Barnes79e53942008-11-07 14:24:08 -08008769 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008770
Jesse Barnes79e53942008-11-07 14:24:08 -08008771 kfree(intel_crtc);
8772}
8773
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008774static void intel_unpin_work_fn(struct work_struct *__work)
8775{
8776 struct intel_unpin_work *work =
8777 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008778 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008779
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008780 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008781 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008782 drm_gem_object_unreference(&work->pending_flip_obj->base);
8783 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008784
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008785 intel_update_fbc(dev);
8786 mutex_unlock(&dev->struct_mutex);
8787
8788 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8789 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8790
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008791 kfree(work);
8792}
8793
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008794static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01008795 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008796{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008797 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8799 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008800 unsigned long flags;
8801
8802 /* Ignore early vblank irqs */
8803 if (intel_crtc == NULL)
8804 return;
8805
8806 spin_lock_irqsave(&dev->event_lock, flags);
8807 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00008808
8809 /* Ensure we don't miss a work->pending update ... */
8810 smp_rmb();
8811
8812 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008813 spin_unlock_irqrestore(&dev->event_lock, flags);
8814 return;
8815 }
8816
Chris Wilsone7d841c2012-12-03 11:36:30 +00008817 /* and that the unpin work is consistent wrt ->pending. */
8818 smp_rmb();
8819
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008820 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008821
Rob Clark45a066e2012-10-08 14:50:40 -05008822 if (work->event)
8823 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008824
Daniel Vetter87b6b102014-05-15 15:33:46 +02008825 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01008826
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008827 spin_unlock_irqrestore(&dev->event_lock, flags);
8828
Daniel Vetter2c10d572012-12-20 21:24:07 +01008829 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008830
8831 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07008832
8833 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008834}
8835
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008836void intel_finish_page_flip(struct drm_device *dev, int pipe)
8837{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008838 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008839 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8840
Mario Kleiner49b14a52010-12-09 07:00:07 +01008841 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008842}
8843
8844void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8845{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008846 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008847 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8848
Mario Kleiner49b14a52010-12-09 07:00:07 +01008849 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008850}
8851
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008852/* Is 'a' after or equal to 'b'? */
8853static bool g4x_flip_count_after_eq(u32 a, u32 b)
8854{
8855 return !((a - b) & 0x80000000);
8856}
8857
8858static bool page_flip_finished(struct intel_crtc *crtc)
8859{
8860 struct drm_device *dev = crtc->base.dev;
8861 struct drm_i915_private *dev_priv = dev->dev_private;
8862
8863 /*
8864 * The relevant registers doen't exist on pre-ctg.
8865 * As the flip done interrupt doesn't trigger for mmio
8866 * flips on gmch platforms, a flip count check isn't
8867 * really needed there. But since ctg has the registers,
8868 * include it in the check anyway.
8869 */
8870 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8871 return true;
8872
8873 /*
8874 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8875 * used the same base address. In that case the mmio flip might
8876 * have completed, but the CS hasn't even executed the flip yet.
8877 *
8878 * A flip count check isn't enough as the CS might have updated
8879 * the base address just after start of vblank, but before we
8880 * managed to process the interrupt. This means we'd complete the
8881 * CS flip too soon.
8882 *
8883 * Combining both checks should get us a good enough result. It may
8884 * still happen that the CS flip has been executed, but has not
8885 * yet actually completed. But in case the base address is the same
8886 * anyway, we don't really care.
8887 */
8888 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8889 crtc->unpin_work->gtt_offset &&
8890 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8891 crtc->unpin_work->flip_count);
8892}
8893
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008894void intel_prepare_page_flip(struct drm_device *dev, int plane)
8895{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008896 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008897 struct intel_crtc *intel_crtc =
8898 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8899 unsigned long flags;
8900
Chris Wilsone7d841c2012-12-03 11:36:30 +00008901 /* NB: An MMIO update of the plane base pointer will also
8902 * generate a page-flip completion irq, i.e. every modeset
8903 * is also accompanied by a spurious intel_prepare_page_flip().
8904 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008905 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008906 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00008907 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008908 spin_unlock_irqrestore(&dev->event_lock, flags);
8909}
8910
Robin Schroereba905b2014-05-18 02:24:50 +02008911static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00008912{
8913 /* Ensure that the work item is consistent when activating it ... */
8914 smp_wmb();
8915 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8916 /* and that it is marked active as soon as the irq could fire. */
8917 smp_wmb();
8918}
8919
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008920static int intel_gen2_queue_flip(struct drm_device *dev,
8921 struct drm_crtc *crtc,
8922 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008923 struct drm_i915_gem_object *obj,
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008924 struct intel_ring_buffer *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07008925 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008926{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008928 u32 flip_mask;
8929 int ret;
8930
Daniel Vetter6d90c952012-04-26 23:28:05 +02008931 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008932 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008933 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008934
8935 /* Can't queue multiple flips, so wait for the previous
8936 * one to finish before executing the next.
8937 */
8938 if (intel_crtc->plane)
8939 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8940 else
8941 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008942 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8943 intel_ring_emit(ring, MI_NOOP);
8944 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8945 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8946 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008947 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008948 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00008949
8950 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008951 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008952 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008953}
8954
8955static int intel_gen3_queue_flip(struct drm_device *dev,
8956 struct drm_crtc *crtc,
8957 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008958 struct drm_i915_gem_object *obj,
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008959 struct intel_ring_buffer *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07008960 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008961{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008963 u32 flip_mask;
8964 int ret;
8965
Daniel Vetter6d90c952012-04-26 23:28:05 +02008966 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008967 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008968 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008969
8970 if (intel_crtc->plane)
8971 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8972 else
8973 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008974 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8975 intel_ring_emit(ring, MI_NOOP);
8976 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8977 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8978 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008979 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008980 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008981
Chris Wilsone7d841c2012-12-03 11:36:30 +00008982 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008983 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008984 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008985}
8986
8987static int intel_gen4_queue_flip(struct drm_device *dev,
8988 struct drm_crtc *crtc,
8989 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008990 struct drm_i915_gem_object *obj,
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008991 struct intel_ring_buffer *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07008992 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008993{
8994 struct drm_i915_private *dev_priv = dev->dev_private;
8995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8996 uint32_t pf, pipesrc;
8997 int ret;
8998
Daniel Vetter6d90c952012-04-26 23:28:05 +02008999 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009000 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009001 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009002
9003 /* i965+ uses the linear or tiled offsets from the
9004 * Display Registers (which do not change across a page-flip)
9005 * so we need only reprogram the base address.
9006 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009007 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9008 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9009 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009010 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009011 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009012
9013 /* XXX Enabling the panel-fitter across page-flip is so far
9014 * untested on non-native modes, so ignore it for now.
9015 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9016 */
9017 pf = 0;
9018 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009019 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009020
9021 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009022 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009023 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009024}
9025
9026static int intel_gen6_queue_flip(struct drm_device *dev,
9027 struct drm_crtc *crtc,
9028 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009029 struct drm_i915_gem_object *obj,
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009030 struct intel_ring_buffer *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009031 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009032{
9033 struct drm_i915_private *dev_priv = dev->dev_private;
9034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9035 uint32_t pf, pipesrc;
9036 int ret;
9037
Daniel Vetter6d90c952012-04-26 23:28:05 +02009038 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009039 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009040 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009041
Daniel Vetter6d90c952012-04-26 23:28:05 +02009042 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9043 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9044 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009045 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009046
Chris Wilson99d9acd2012-04-17 20:37:00 +01009047 /* Contrary to the suggestions in the documentation,
9048 * "Enable Panel Fitter" does not seem to be required when page
9049 * flipping with a non-native mode, and worse causes a normal
9050 * modeset to fail.
9051 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9052 */
9053 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009054 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009055 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009056
9057 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009058 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009059 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009060}
9061
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009062static int intel_gen7_queue_flip(struct drm_device *dev,
9063 struct drm_crtc *crtc,
9064 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009065 struct drm_i915_gem_object *obj,
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009066 struct intel_ring_buffer *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009067 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009068{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009070 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009071 int len, ret;
9072
Robin Schroereba905b2014-05-18 02:24:50 +02009073 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009074 case PLANE_A:
9075 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9076 break;
9077 case PLANE_B:
9078 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9079 break;
9080 case PLANE_C:
9081 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9082 break;
9083 default:
9084 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009085 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009086 }
9087
Chris Wilsonffe74d72013-08-26 20:58:12 +01009088 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009089 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009090 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009091 /*
9092 * On Gen 8, SRM is now taking an extra dword to accommodate
9093 * 48bits addresses, and we need a NOOP for the batch size to
9094 * stay even.
9095 */
9096 if (IS_GEN8(dev))
9097 len += 2;
9098 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009099
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009100 /*
9101 * BSpec MI_DISPLAY_FLIP for IVB:
9102 * "The full packet must be contained within the same cache line."
9103 *
9104 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9105 * cacheline, if we ever start emitting more commands before
9106 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9107 * then do the cacheline alignment, and finally emit the
9108 * MI_DISPLAY_FLIP.
9109 */
9110 ret = intel_ring_cacheline_align(ring);
9111 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009112 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009113
Chris Wilsonffe74d72013-08-26 20:58:12 +01009114 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009115 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009116 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009117
Chris Wilsonffe74d72013-08-26 20:58:12 +01009118 /* Unmask the flip-done completion message. Note that the bspec says that
9119 * we should do this for both the BCS and RCS, and that we must not unmask
9120 * more than one flip event at any time (or ensure that one flip message
9121 * can be sent by waiting for flip-done prior to queueing new flips).
9122 * Experimentation says that BCS works despite DERRMR masking all
9123 * flip-done completion events and that unmasking all planes at once
9124 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9125 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9126 */
9127 if (ring->id == RCS) {
9128 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9129 intel_ring_emit(ring, DERRMR);
9130 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9131 DERRMR_PIPEB_PRI_FLIP_DONE |
9132 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009133 if (IS_GEN8(dev))
9134 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9135 MI_SRM_LRM_GLOBAL_GTT);
9136 else
9137 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9138 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009139 intel_ring_emit(ring, DERRMR);
9140 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009141 if (IS_GEN8(dev)) {
9142 intel_ring_emit(ring, 0);
9143 intel_ring_emit(ring, MI_NOOP);
9144 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009145 }
9146
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009147 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009148 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009149 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009150 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009151
9152 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009153 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009154 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009155}
9156
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009157static int intel_default_queue_flip(struct drm_device *dev,
9158 struct drm_crtc *crtc,
9159 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009160 struct drm_i915_gem_object *obj,
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009161 struct intel_ring_buffer *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009162 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009163{
9164 return -ENODEV;
9165}
9166
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009167static int intel_crtc_page_flip(struct drm_crtc *crtc,
9168 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009169 struct drm_pending_vblank_event *event,
9170 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009171{
9172 struct drm_device *dev = crtc->dev;
9173 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009174 struct drm_framebuffer *old_fb = crtc->primary->fb;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02009175 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9177 struct intel_unpin_work *work;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009178 struct intel_ring_buffer *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009179 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009180 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009181
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009182 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009183 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009184 return -EINVAL;
9185
9186 /*
9187 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9188 * Note that pitch changes could also affect these register.
9189 */
9190 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009191 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9192 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009193 return -EINVAL;
9194
Chris Wilsonf900db42014-02-20 09:26:13 +00009195 if (i915_terminally_wedged(&dev_priv->gpu_error))
9196 goto out_hang;
9197
Daniel Vetterb14c5672013-09-19 12:18:32 +02009198 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009199 if (work == NULL)
9200 return -ENOMEM;
9201
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009202 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009203 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02009204 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009205 INIT_WORK(&work->work, intel_unpin_work_fn);
9206
Daniel Vetter87b6b102014-05-15 15:33:46 +02009207 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009208 if (ret)
9209 goto free_work;
9210
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009211 /* We borrow the event spin lock for protecting unpin_work */
9212 spin_lock_irqsave(&dev->event_lock, flags);
9213 if (intel_crtc->unpin_work) {
9214 spin_unlock_irqrestore(&dev->event_lock, flags);
9215 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009216 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009217
9218 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009219 return -EBUSY;
9220 }
9221 intel_crtc->unpin_work = work;
9222 spin_unlock_irqrestore(&dev->event_lock, flags);
9223
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009224 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9225 flush_workqueue(dev_priv->wq);
9226
Chris Wilson79158102012-05-23 11:13:58 +01009227 ret = i915_mutex_lock_interruptible(dev);
9228 if (ret)
9229 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009230
Jesse Barnes75dfca82010-02-10 15:09:44 -08009231 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009232 drm_gem_object_reference(&work->old_fb_obj->base);
9233 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009234
Matt Roperf4510a22014-04-01 15:22:40 -07009235 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009236
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009237 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009238
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009239 work->enable_stall_check = true;
9240
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009241 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009242 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009243
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009244 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9245 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9246
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009247 if (IS_VALLEYVIEW(dev)) {
9248 ring = &dev_priv->ring[BCS];
9249 } else if (INTEL_INFO(dev)->gen >= 7) {
9250 ring = obj->ring;
9251 if (ring == NULL || ring->id != RCS)
9252 ring = &dev_priv->ring[BCS];
9253 } else {
9254 ring = &dev_priv->ring[RCS];
9255 }
9256
9257 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009258 if (ret)
9259 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009260
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009261 work->gtt_offset =
9262 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9263
9264 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9265 if (ret)
9266 goto cleanup_unpin;
9267
Chris Wilson7782de32011-07-08 12:22:41 +01009268 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03009269 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009270 mutex_unlock(&dev->struct_mutex);
9271
Jesse Barnese5510fa2010-07-01 16:48:37 -07009272 trace_i915_flip_request(intel_crtc->plane, obj);
9273
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009274 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009275
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009276cleanup_unpin:
9277 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009278cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009279 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009280 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009281 drm_gem_object_unreference(&work->old_fb_obj->base);
9282 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009283 mutex_unlock(&dev->struct_mutex);
9284
Chris Wilson79158102012-05-23 11:13:58 +01009285cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009286 spin_lock_irqsave(&dev->event_lock, flags);
9287 intel_crtc->unpin_work = NULL;
9288 spin_unlock_irqrestore(&dev->event_lock, flags);
9289
Daniel Vetter87b6b102014-05-15 15:33:46 +02009290 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009291free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009292 kfree(work);
9293
Chris Wilsonf900db42014-02-20 09:26:13 +00009294 if (ret == -EIO) {
9295out_hang:
9296 intel_crtc_wait_for_pending_flips(crtc);
9297 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9298 if (ret == 0 && event)
9299 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9300 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009301 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009302}
9303
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009304static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009305 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9306 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009307};
9308
Daniel Vetter9a935852012-07-05 22:34:27 +02009309/**
9310 * intel_modeset_update_staged_output_state
9311 *
9312 * Updates the staged output configuration state, e.g. after we've read out the
9313 * current hw state.
9314 */
9315static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9316{
Ville Syrjälä76688512014-01-10 11:28:06 +02009317 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009318 struct intel_encoder *encoder;
9319 struct intel_connector *connector;
9320
9321 list_for_each_entry(connector, &dev->mode_config.connector_list,
9322 base.head) {
9323 connector->new_encoder =
9324 to_intel_encoder(connector->base.encoder);
9325 }
9326
9327 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9328 base.head) {
9329 encoder->new_crtc =
9330 to_intel_crtc(encoder->base.crtc);
9331 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009332
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009333 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009334 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009335
9336 if (crtc->new_enabled)
9337 crtc->new_config = &crtc->config;
9338 else
9339 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009340 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009341}
9342
9343/**
9344 * intel_modeset_commit_output_state
9345 *
9346 * This function copies the stage display pipe configuration to the real one.
9347 */
9348static void intel_modeset_commit_output_state(struct drm_device *dev)
9349{
Ville Syrjälä76688512014-01-10 11:28:06 +02009350 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009351 struct intel_encoder *encoder;
9352 struct intel_connector *connector;
9353
9354 list_for_each_entry(connector, &dev->mode_config.connector_list,
9355 base.head) {
9356 connector->base.encoder = &connector->new_encoder->base;
9357 }
9358
9359 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9360 base.head) {
9361 encoder->base.crtc = &encoder->new_crtc->base;
9362 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009363
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009364 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009365 crtc->base.enabled = crtc->new_enabled;
9366 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009367}
9368
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009369static void
Robin Schroereba905b2014-05-18 02:24:50 +02009370connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009371 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009372{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009373 int bpp = pipe_config->pipe_bpp;
9374
9375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9376 connector->base.base.id,
9377 drm_get_connector_name(&connector->base));
9378
9379 /* Don't use an invalid EDID bpc value */
9380 if (connector->base.display_info.bpc &&
9381 connector->base.display_info.bpc * 3 < bpp) {
9382 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9383 bpp, connector->base.display_info.bpc*3);
9384 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9385 }
9386
9387 /* Clamp bpp to 8 on screens without EDID 1.4 */
9388 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9389 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9390 bpp);
9391 pipe_config->pipe_bpp = 24;
9392 }
9393}
9394
9395static int
9396compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9397 struct drm_framebuffer *fb,
9398 struct intel_crtc_config *pipe_config)
9399{
9400 struct drm_device *dev = crtc->base.dev;
9401 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009402 int bpp;
9403
Daniel Vetterd42264b2013-03-28 16:38:08 +01009404 switch (fb->pixel_format) {
9405 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009406 bpp = 8*3; /* since we go through a colormap */
9407 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009408 case DRM_FORMAT_XRGB1555:
9409 case DRM_FORMAT_ARGB1555:
9410 /* checked in intel_framebuffer_init already */
9411 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9412 return -EINVAL;
9413 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009414 bpp = 6*3; /* min is 18bpp */
9415 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009416 case DRM_FORMAT_XBGR8888:
9417 case DRM_FORMAT_ABGR8888:
9418 /* checked in intel_framebuffer_init already */
9419 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9420 return -EINVAL;
9421 case DRM_FORMAT_XRGB8888:
9422 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009423 bpp = 8*3;
9424 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009425 case DRM_FORMAT_XRGB2101010:
9426 case DRM_FORMAT_ARGB2101010:
9427 case DRM_FORMAT_XBGR2101010:
9428 case DRM_FORMAT_ABGR2101010:
9429 /* checked in intel_framebuffer_init already */
9430 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009431 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009432 bpp = 10*3;
9433 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009434 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009435 default:
9436 DRM_DEBUG_KMS("unsupported depth\n");
9437 return -EINVAL;
9438 }
9439
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009440 pipe_config->pipe_bpp = bpp;
9441
9442 /* Clamp display bpp to EDID value */
9443 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009444 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009445 if (!connector->new_encoder ||
9446 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009447 continue;
9448
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009449 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009450 }
9451
9452 return bpp;
9453}
9454
Daniel Vetter644db712013-09-19 14:53:58 +02009455static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9456{
9457 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9458 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01009459 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02009460 mode->crtc_hdisplay, mode->crtc_hsync_start,
9461 mode->crtc_hsync_end, mode->crtc_htotal,
9462 mode->crtc_vdisplay, mode->crtc_vsync_start,
9463 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9464}
9465
Daniel Vetterc0b03412013-05-28 12:05:54 +02009466static void intel_dump_pipe_config(struct intel_crtc *crtc,
9467 struct intel_crtc_config *pipe_config,
9468 const char *context)
9469{
9470 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9471 context, pipe_name(crtc->pipe));
9472
9473 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9474 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9475 pipe_config->pipe_bpp, pipe_config->dither);
9476 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9477 pipe_config->has_pch_encoder,
9478 pipe_config->fdi_lanes,
9479 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9480 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9481 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009482 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9483 pipe_config->has_dp_encoder,
9484 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9485 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9486 pipe_config->dp_m_n.tu);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009487 DRM_DEBUG_KMS("requested mode:\n");
9488 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9489 DRM_DEBUG_KMS("adjusted mode:\n");
9490 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02009491 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009492 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009493 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9494 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009495 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9496 pipe_config->gmch_pfit.control,
9497 pipe_config->gmch_pfit.pgm_ratios,
9498 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009499 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02009500 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009501 pipe_config->pch_pfit.size,
9502 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009503 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03009504 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009505}
9506
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009507static bool encoders_cloneable(const struct intel_encoder *a,
9508 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009509{
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009510 /* masks could be asymmetric, so check both ways */
9511 return a == b || (a->cloneable & (1 << b->type) &&
9512 b->cloneable & (1 << a->type));
9513}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009514
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009515static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9516 struct intel_encoder *encoder)
9517{
9518 struct drm_device *dev = crtc->base.dev;
9519 struct intel_encoder *source_encoder;
9520
9521 list_for_each_entry(source_encoder,
9522 &dev->mode_config.encoder_list, base.head) {
9523 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009524 continue;
9525
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009526 if (!encoders_cloneable(encoder, source_encoder))
9527 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009528 }
9529
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009530 return true;
9531}
9532
9533static bool check_encoder_cloning(struct intel_crtc *crtc)
9534{
9535 struct drm_device *dev = crtc->base.dev;
9536 struct intel_encoder *encoder;
9537
9538 list_for_each_entry(encoder,
9539 &dev->mode_config.encoder_list, base.head) {
9540 if (encoder->new_crtc != crtc)
9541 continue;
9542
9543 if (!check_single_encoder_cloning(crtc, encoder))
9544 return false;
9545 }
9546
9547 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009548}
9549
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009550static struct intel_crtc_config *
9551intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009552 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009553 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02009554{
9555 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02009556 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009557 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01009558 int plane_bpp, ret = -EINVAL;
9559 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02009560
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009561 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009562 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9563 return ERR_PTR(-EINVAL);
9564 }
9565
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009566 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9567 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02009568 return ERR_PTR(-ENOMEM);
9569
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009570 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9571 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009572
Daniel Vettere143a212013-07-04 12:01:15 +02009573 pipe_config->cpu_transcoder =
9574 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009575 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009576
Imre Deak2960bc92013-07-30 13:36:32 +03009577 /*
9578 * Sanitize sync polarity flags based on requested ones. If neither
9579 * positive or negative polarity is requested, treat this as meaning
9580 * negative polarity.
9581 */
9582 if (!(pipe_config->adjusted_mode.flags &
9583 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9584 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9585
9586 if (!(pipe_config->adjusted_mode.flags &
9587 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9588 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9589
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009590 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9591 * plane pixel format and any sink constraints into account. Returns the
9592 * source plane bpp so that dithering can be selected on mismatches
9593 * after encoders and crtc also have had their say. */
9594 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9595 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009596 if (plane_bpp < 0)
9597 goto fail;
9598
Ville Syrjäläe41a56b2013-10-01 22:52:14 +03009599 /*
9600 * Determine the real pipe dimensions. Note that stereo modes can
9601 * increase the actual pipe size due to the frame doubling and
9602 * insertion of additional space for blanks between the frame. This
9603 * is stored in the crtc timings. We use the requested mode to do this
9604 * computation to clearly distinguish it from the adjusted mode, which
9605 * can be changed by the connectors in the below retry loop.
9606 */
9607 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9608 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9609 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9610
Daniel Vettere29c22c2013-02-21 00:00:16 +01009611encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02009612 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02009613 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02009614 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009615
Daniel Vetter135c81b2013-07-21 21:37:09 +02009616 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +01009617 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +02009618
Daniel Vetter7758a112012-07-08 19:40:39 +02009619 /* Pass our mode to the connectors and the CRTC to give them a chance to
9620 * adjust it according to limitations or connector properties, and also
9621 * a chance to reject the mode entirely.
9622 */
9623 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9624 base.head) {
9625
9626 if (&encoder->new_crtc->base != crtc)
9627 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01009628
Daniel Vetterefea6e82013-07-21 21:36:59 +02009629 if (!(encoder->compute_config(encoder, pipe_config))) {
9630 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +02009631 goto fail;
9632 }
9633 }
9634
Daniel Vetterff9a6752013-06-01 17:16:21 +02009635 /* Set default port clock if not overwritten by the encoder. Needs to be
9636 * done afterwards in case the encoder adjusts the mode. */
9637 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +01009638 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9639 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009640
Daniel Vettera43f6e02013-06-07 23:10:32 +02009641 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009642 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02009643 DRM_DEBUG_KMS("CRTC fixup failed\n");
9644 goto fail;
9645 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01009646
9647 if (ret == RETRY) {
9648 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9649 ret = -EINVAL;
9650 goto fail;
9651 }
9652
9653 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9654 retry = false;
9655 goto encoder_retry;
9656 }
9657
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009658 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9659 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9660 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9661
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009662 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02009663fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009664 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009665 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02009666}
9667
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009668/* Computes which crtcs are affected and sets the relevant bits in the mask. For
9669 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9670static void
9671intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9672 unsigned *prepare_pipes, unsigned *disable_pipes)
9673{
9674 struct intel_crtc *intel_crtc;
9675 struct drm_device *dev = crtc->dev;
9676 struct intel_encoder *encoder;
9677 struct intel_connector *connector;
9678 struct drm_crtc *tmp_crtc;
9679
9680 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9681
9682 /* Check which crtcs have changed outputs connected to them, these need
9683 * to be part of the prepare_pipes mask. We don't (yet) support global
9684 * modeset across multiple crtcs, so modeset_pipes will only have one
9685 * bit set at most. */
9686 list_for_each_entry(connector, &dev->mode_config.connector_list,
9687 base.head) {
9688 if (connector->base.encoder == &connector->new_encoder->base)
9689 continue;
9690
9691 if (connector->base.encoder) {
9692 tmp_crtc = connector->base.encoder->crtc;
9693
9694 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9695 }
9696
9697 if (connector->new_encoder)
9698 *prepare_pipes |=
9699 1 << connector->new_encoder->new_crtc->pipe;
9700 }
9701
9702 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9703 base.head) {
9704 if (encoder->base.crtc == &encoder->new_crtc->base)
9705 continue;
9706
9707 if (encoder->base.crtc) {
9708 tmp_crtc = encoder->base.crtc;
9709
9710 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9711 }
9712
9713 if (encoder->new_crtc)
9714 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9715 }
9716
Ville Syrjälä76688512014-01-10 11:28:06 +02009717 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009718 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009719 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009720 continue;
9721
Ville Syrjälä76688512014-01-10 11:28:06 +02009722 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009723 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +02009724 else
9725 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009726 }
9727
9728
9729 /* set_mode is also used to update properties on life display pipes. */
9730 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +02009731 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009732 *prepare_pipes |= 1 << intel_crtc->pipe;
9733
Daniel Vetterb6c51642013-04-12 18:48:43 +02009734 /*
9735 * For simplicity do a full modeset on any pipe where the output routing
9736 * changed. We could be more clever, but that would require us to be
9737 * more careful with calling the relevant encoder->mode_set functions.
9738 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009739 if (*prepare_pipes)
9740 *modeset_pipes = *prepare_pipes;
9741
9742 /* ... and mask these out. */
9743 *modeset_pipes &= ~(*disable_pipes);
9744 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02009745
9746 /*
9747 * HACK: We don't (yet) fully support global modesets. intel_set_config
9748 * obies this rule, but the modeset restore mode of
9749 * intel_modeset_setup_hw_state does not.
9750 */
9751 *modeset_pipes &= 1 << intel_crtc->pipe;
9752 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02009753
9754 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9755 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009756}
9757
Daniel Vetterea9d7582012-07-10 10:42:52 +02009758static bool intel_crtc_in_use(struct drm_crtc *crtc)
9759{
9760 struct drm_encoder *encoder;
9761 struct drm_device *dev = crtc->dev;
9762
9763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9764 if (encoder->crtc == crtc)
9765 return true;
9766
9767 return false;
9768}
9769
9770static void
9771intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9772{
9773 struct intel_encoder *intel_encoder;
9774 struct intel_crtc *intel_crtc;
9775 struct drm_connector *connector;
9776
9777 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9778 base.head) {
9779 if (!intel_encoder->base.crtc)
9780 continue;
9781
9782 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9783
9784 if (prepare_pipes & (1 << intel_crtc->pipe))
9785 intel_encoder->connectors_active = false;
9786 }
9787
9788 intel_modeset_commit_output_state(dev);
9789
Ville Syrjälä76688512014-01-10 11:28:06 +02009790 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009791 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009792 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009793 WARN_ON(intel_crtc->new_config &&
9794 intel_crtc->new_config != &intel_crtc->config);
9795 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009796 }
9797
9798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9799 if (!connector->encoder || !connector->encoder->crtc)
9800 continue;
9801
9802 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9803
9804 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02009805 struct drm_property *dpms_property =
9806 dev->mode_config.dpms_property;
9807
Daniel Vetterea9d7582012-07-10 10:42:52 +02009808 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05009809 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02009810 dpms_property,
9811 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009812
9813 intel_encoder = to_intel_encoder(connector->encoder);
9814 intel_encoder->connectors_active = true;
9815 }
9816 }
9817
9818}
9819
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009820static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009821{
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009822 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009823
9824 if (clock1 == clock2)
9825 return true;
9826
9827 if (!clock1 || !clock2)
9828 return false;
9829
9830 diff = abs(clock1 - clock2);
9831
9832 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9833 return true;
9834
9835 return false;
9836}
9837
Daniel Vetter25c5b262012-07-08 22:08:04 +02009838#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9839 list_for_each_entry((intel_crtc), \
9840 &(dev)->mode_config.crtc_list, \
9841 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02009842 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02009843
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009844static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009845intel_pipe_config_compare(struct drm_device *dev,
9846 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009847 struct intel_crtc_config *pipe_config)
9848{
Daniel Vetter66e985c2013-06-05 13:34:20 +02009849#define PIPE_CONF_CHECK_X(name) \
9850 if (current_config->name != pipe_config->name) { \
9851 DRM_ERROR("mismatch in " #name " " \
9852 "(expected 0x%08x, found 0x%08x)\n", \
9853 current_config->name, \
9854 pipe_config->name); \
9855 return false; \
9856 }
9857
Daniel Vetter08a24032013-04-19 11:25:34 +02009858#define PIPE_CONF_CHECK_I(name) \
9859 if (current_config->name != pipe_config->name) { \
9860 DRM_ERROR("mismatch in " #name " " \
9861 "(expected %i, found %i)\n", \
9862 current_config->name, \
9863 pipe_config->name); \
9864 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01009865 }
9866
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009867#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9868 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -07009869 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009870 "(expected %i, found %i)\n", \
9871 current_config->name & (mask), \
9872 pipe_config->name & (mask)); \
9873 return false; \
9874 }
9875
Ville Syrjälä5e550652013-09-06 23:29:07 +03009876#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9877 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9878 DRM_ERROR("mismatch in " #name " " \
9879 "(expected %i, found %i)\n", \
9880 current_config->name, \
9881 pipe_config->name); \
9882 return false; \
9883 }
9884
Daniel Vetterbb760062013-06-06 14:55:52 +02009885#define PIPE_CONF_QUIRK(quirk) \
9886 ((current_config->quirks | pipe_config->quirks) & (quirk))
9887
Daniel Vettereccb1402013-05-22 00:50:22 +02009888 PIPE_CONF_CHECK_I(cpu_transcoder);
9889
Daniel Vetter08a24032013-04-19 11:25:34 +02009890 PIPE_CONF_CHECK_I(has_pch_encoder);
9891 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02009892 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9893 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9894 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9895 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9896 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02009897
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009898 PIPE_CONF_CHECK_I(has_dp_encoder);
9899 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9900 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9901 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9902 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9903 PIPE_CONF_CHECK_I(dp_m_n.tu);
9904
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009905 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9906 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9907 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9908 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9909 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9910 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9911
9912 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9913 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9914 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9915 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9916 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9917 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9918
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009919 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b52014-04-24 23:54:47 +02009920 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02009921 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9922 IS_VALLEYVIEW(dev))
9923 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009924
Daniel Vetter9ed109a2014-04-24 23:54:52 +02009925 PIPE_CONF_CHECK_I(has_audio);
9926
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009927 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9928 DRM_MODE_FLAG_INTERLACE);
9929
Daniel Vetterbb760062013-06-06 14:55:52 +02009930 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9931 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9932 DRM_MODE_FLAG_PHSYNC);
9933 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9934 DRM_MODE_FLAG_NHSYNC);
9935 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9936 DRM_MODE_FLAG_PVSYNC);
9937 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9938 DRM_MODE_FLAG_NVSYNC);
9939 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009940
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009941 PIPE_CONF_CHECK_I(pipe_src_w);
9942 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009943
Daniel Vetter99535992014-04-13 12:00:33 +02009944 /*
9945 * FIXME: BIOS likes to set up a cloned config with lvds+external
9946 * screen. Since we don't yet re-compute the pipe config when moving
9947 * just the lvds port away to another pipe the sw tracking won't match.
9948 *
9949 * Proper atomic modesets with recomputed global state will fix this.
9950 * Until then just don't check gmch state for inherited modes.
9951 */
9952 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9953 PIPE_CONF_CHECK_I(gmch_pfit.control);
9954 /* pfit ratios are autocomputed by the hw on gen4+ */
9955 if (INTEL_INFO(dev)->gen < 4)
9956 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9957 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9958 }
9959
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009960 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9961 if (current_config->pch_pfit.enabled) {
9962 PIPE_CONF_CHECK_I(pch_pfit.pos);
9963 PIPE_CONF_CHECK_I(pch_pfit.size);
9964 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009965
Jesse Barnese59150d2014-01-07 13:30:45 -08009966 /* BDW+ don't expose a synchronous way to read the state */
9967 if (IS_HASWELL(dev))
9968 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009969
Ville Syrjälä282740f2013-09-04 18:30:03 +03009970 PIPE_CONF_CHECK_I(double_wide);
9971
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009972 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009973 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02009974 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009975 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9976 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009977
Ville Syrjälä42571ae2013-09-06 23:29:00 +03009978 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9979 PIPE_CONF_CHECK_I(pipe_bpp);
9980
Jesse Barnesa9a7e982014-01-20 14:18:04 -08009981 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9982 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +03009983
Daniel Vetter66e985c2013-06-05 13:34:20 +02009984#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +02009985#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009986#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +03009987#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +02009988#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009989
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009990 return true;
9991}
9992
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009993static void
9994check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009995{
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009996 struct intel_connector *connector;
9997
9998 list_for_each_entry(connector, &dev->mode_config.connector_list,
9999 base.head) {
10000 /* This also checks the encoder/connector hw state with the
10001 * ->get_hw_state callbacks. */
10002 intel_connector_check_state(connector);
10003
10004 WARN(&connector->new_encoder->base != connector->base.encoder,
10005 "connector's staged encoder doesn't match current encoder\n");
10006 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010007}
10008
10009static void
10010check_encoder_state(struct drm_device *dev)
10011{
10012 struct intel_encoder *encoder;
10013 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010014
10015 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10016 base.head) {
10017 bool enabled = false;
10018 bool active = false;
10019 enum pipe pipe, tracked_pipe;
10020
10021 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10022 encoder->base.base.id,
10023 drm_get_encoder_name(&encoder->base));
10024
10025 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10026 "encoder's stage crtc doesn't match current crtc\n");
10027 WARN(encoder->connectors_active && !encoder->base.crtc,
10028 "encoder's active_connectors set, but no crtc\n");
10029
10030 list_for_each_entry(connector, &dev->mode_config.connector_list,
10031 base.head) {
10032 if (connector->base.encoder != &encoder->base)
10033 continue;
10034 enabled = true;
10035 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10036 active = true;
10037 }
10038 WARN(!!encoder->base.crtc != enabled,
10039 "encoder's enabled state mismatch "
10040 "(expected %i, found %i)\n",
10041 !!encoder->base.crtc, enabled);
10042 WARN(active && !encoder->base.crtc,
10043 "active encoder with no crtc\n");
10044
10045 WARN(encoder->connectors_active != active,
10046 "encoder's computed active state doesn't match tracked active state "
10047 "(expected %i, found %i)\n", active, encoder->connectors_active);
10048
10049 active = encoder->get_hw_state(encoder, &pipe);
10050 WARN(active != encoder->connectors_active,
10051 "encoder's hw state doesn't match sw tracking "
10052 "(expected %i, found %i)\n",
10053 encoder->connectors_active, active);
10054
10055 if (!encoder->base.crtc)
10056 continue;
10057
10058 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10059 WARN(active && pipe != tracked_pipe,
10060 "active encoder's pipe doesn't match"
10061 "(expected %i, found %i)\n",
10062 tracked_pipe, pipe);
10063
10064 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010065}
10066
10067static void
10068check_crtc_state(struct drm_device *dev)
10069{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010070 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010071 struct intel_crtc *crtc;
10072 struct intel_encoder *encoder;
10073 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010074
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010075 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010076 bool enabled = false;
10077 bool active = false;
10078
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010079 memset(&pipe_config, 0, sizeof(pipe_config));
10080
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010081 DRM_DEBUG_KMS("[CRTC:%d]\n",
10082 crtc->base.base.id);
10083
10084 WARN(crtc->active && !crtc->base.enabled,
10085 "active crtc, but not enabled in sw tracking\n");
10086
10087 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10088 base.head) {
10089 if (encoder->base.crtc != &crtc->base)
10090 continue;
10091 enabled = true;
10092 if (encoder->connectors_active)
10093 active = true;
10094 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010095
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010096 WARN(active != crtc->active,
10097 "crtc's computed active state doesn't match tracked active state "
10098 "(expected %i, found %i)\n", active, crtc->active);
10099 WARN(enabled != crtc->base.enabled,
10100 "crtc's computed enabled state doesn't match tracked enabled state "
10101 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10102
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010103 active = dev_priv->display.get_pipe_config(crtc,
10104 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010105
10106 /* hw state is inconsistent with the pipe A quirk */
10107 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10108 active = crtc->active;
10109
Daniel Vetter6c49f242013-06-06 12:45:25 +020010110 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10111 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010112 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010113 if (encoder->base.crtc != &crtc->base)
10114 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010115 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010116 encoder->get_config(encoder, &pipe_config);
10117 }
10118
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010119 WARN(crtc->active != active,
10120 "crtc active state doesn't match with hw state "
10121 "(expected %i, found %i)\n", crtc->active, active);
10122
Daniel Vetterc0b03412013-05-28 12:05:54 +020010123 if (active &&
10124 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10125 WARN(1, "pipe state doesn't match!\n");
10126 intel_dump_pipe_config(crtc, &pipe_config,
10127 "[hw state]");
10128 intel_dump_pipe_config(crtc, &crtc->config,
10129 "[sw state]");
10130 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010131 }
10132}
10133
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010134static void
10135check_shared_dpll_state(struct drm_device *dev)
10136{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010137 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010138 struct intel_crtc *crtc;
10139 struct intel_dpll_hw_state dpll_hw_state;
10140 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010141
10142 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10143 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10144 int enabled_crtcs = 0, active_crtcs = 0;
10145 bool active;
10146
10147 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10148
10149 DRM_DEBUG_KMS("%s\n", pll->name);
10150
10151 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10152
10153 WARN(pll->active > pll->refcount,
10154 "more active pll users than references: %i vs %i\n",
10155 pll->active, pll->refcount);
10156 WARN(pll->active && !pll->on,
10157 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010158 WARN(pll->on && !pll->active,
10159 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010160 WARN(pll->on != active,
10161 "pll on state mismatch (expected %i, found %i)\n",
10162 pll->on, active);
10163
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010164 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010165 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10166 enabled_crtcs++;
10167 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10168 active_crtcs++;
10169 }
10170 WARN(pll->active != active_crtcs,
10171 "pll active crtcs mismatch (expected %i, found %i)\n",
10172 pll->active, active_crtcs);
10173 WARN(pll->refcount != enabled_crtcs,
10174 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10175 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010176
10177 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10178 sizeof(dpll_hw_state)),
10179 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010180 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010181}
10182
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010183void
10184intel_modeset_check_state(struct drm_device *dev)
10185{
10186 check_connector_state(dev);
10187 check_encoder_state(dev);
10188 check_crtc_state(dev);
10189 check_shared_dpll_state(dev);
10190}
10191
Ville Syrjälä18442d02013-09-13 16:00:08 +030010192void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10193 int dotclock)
10194{
10195 /*
10196 * FDI already provided one idea for the dotclock.
10197 * Yell if the encoder disagrees.
10198 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010199 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010200 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010201 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010202}
10203
Daniel Vetterf30da182013-04-11 20:22:50 +020010204static int __intel_set_mode(struct drm_crtc *crtc,
10205 struct drm_display_mode *mode,
10206 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010207{
10208 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010209 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010210 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010211 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010212 struct intel_crtc *intel_crtc;
10213 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010214 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010215
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010216 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010217 if (!saved_mode)
10218 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010219
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010220 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010221 &prepare_pipes, &disable_pipes);
10222
Tim Gardner3ac18232012-12-07 07:54:26 -070010223 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010224
Daniel Vetter25c5b262012-07-08 22:08:04 +020010225 /* Hack: Because we don't (yet) support global modeset on multiple
10226 * crtcs, we don't keep track of the new mode for more than one crtc.
10227 * Hence simply check whether any bit is set in modeset_pipes in all the
10228 * pieces of code that are not yet converted to deal with mutliple crtcs
10229 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010230 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010231 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010232 if (IS_ERR(pipe_config)) {
10233 ret = PTR_ERR(pipe_config);
10234 pipe_config = NULL;
10235
Tim Gardner3ac18232012-12-07 07:54:26 -070010236 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010237 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010238 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10239 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010240 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010241 }
10242
Jesse Barnes30a970c2013-11-04 13:48:12 -080010243 /*
10244 * See if the config requires any additional preparation, e.g.
10245 * to adjust global state with pipes off. We need to do this
10246 * here so we can get the modeset_pipe updated config for the new
10247 * mode set on this crtc. For other crtcs we need to use the
10248 * adjusted_mode bits in the crtc directly.
10249 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010250 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010251 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010252
Ville Syrjäläc164f832013-11-05 22:34:12 +020010253 /* may have added more to prepare_pipes than we should */
10254 prepare_pipes &= ~disable_pipes;
10255 }
10256
Daniel Vetter460da9162013-03-27 00:44:51 +010010257 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10258 intel_crtc_disable(&intel_crtc->base);
10259
Daniel Vetterea9d7582012-07-10 10:42:52 +020010260 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10261 if (intel_crtc->base.enabled)
10262 dev_priv->display.crtc_disable(&intel_crtc->base);
10263 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010264
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010265 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10266 * to set it here already despite that we pass it down the callchain.
10267 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010268 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010269 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010270 /* mode_set/enable/disable functions rely on a correct pipe
10271 * config. */
10272 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010273 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010274
10275 /*
10276 * Calculate and store various constants which
10277 * are later needed by vblank and swap-completion
10278 * timestamping. They are derived from true hwmode.
10279 */
10280 drm_calc_timestamping_constants(crtc,
10281 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010282 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010283
Daniel Vetterea9d7582012-07-10 10:42:52 +020010284 /* Only after disabling all output pipelines that will be changed can we
10285 * update the the output configuration. */
10286 intel_modeset_update_state(dev, prepare_pipes);
10287
Daniel Vetter47fab732012-10-26 10:58:18 +020010288 if (dev_priv->display.modeset_global_resources)
10289 dev_priv->display.modeset_global_resources(dev);
10290
Daniel Vettera6778b32012-07-02 09:56:42 +020010291 /* Set up the DPLL and any encoders state that needs to adjust or depend
10292 * on the DPLL.
10293 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010294 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Daniel Vetter4c107942014-04-24 23:55:05 +020010295 struct drm_framebuffer *old_fb;
10296
10297 mutex_lock(&dev->struct_mutex);
10298 ret = intel_pin_and_fence_fb_obj(dev,
10299 to_intel_framebuffer(fb)->obj,
10300 NULL);
10301 if (ret != 0) {
10302 DRM_ERROR("pin & fence failed\n");
10303 mutex_unlock(&dev->struct_mutex);
10304 goto done;
10305 }
10306 old_fb = crtc->primary->fb;
10307 if (old_fb)
10308 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10309 mutex_unlock(&dev->struct_mutex);
10310
10311 crtc->primary->fb = fb;
10312 crtc->x = x;
10313 crtc->y = y;
10314
Daniel Vetter4271b752014-04-24 23:55:00 +020010315 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10316 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010317 if (ret)
10318 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020010319 }
10320
10321 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010322 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10323 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +020010324
Daniel Vettera6778b32012-07-02 09:56:42 +020010325 /* FIXME: add subpixel order */
10326done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010327 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010328 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010329
Tim Gardner3ac18232012-12-07 07:54:26 -070010330out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010331 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010332 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010333 return ret;
10334}
10335
Damien Lespiaue7457a92013-08-08 22:28:59 +010010336static int intel_set_mode(struct drm_crtc *crtc,
10337 struct drm_display_mode *mode,
10338 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020010339{
10340 int ret;
10341
10342 ret = __intel_set_mode(crtc, mode, x, y, fb);
10343
10344 if (ret == 0)
10345 intel_modeset_check_state(crtc->dev);
10346
10347 return ret;
10348}
10349
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010350void intel_crtc_restore_mode(struct drm_crtc *crtc)
10351{
Matt Roperf4510a22014-04-01 15:22:40 -070010352 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010353}
10354
Daniel Vetter25c5b262012-07-08 22:08:04 +020010355#undef for_each_intel_crtc_masked
10356
Daniel Vetterd9e55602012-07-04 22:16:09 +020010357static void intel_set_config_free(struct intel_set_config *config)
10358{
10359 if (!config)
10360 return;
10361
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010362 kfree(config->save_connector_encoders);
10363 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020010364 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020010365 kfree(config);
10366}
10367
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010368static int intel_set_config_save_state(struct drm_device *dev,
10369 struct intel_set_config *config)
10370{
Ville Syrjälä76688512014-01-10 11:28:06 +020010371 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010372 struct drm_encoder *encoder;
10373 struct drm_connector *connector;
10374 int count;
10375
Ville Syrjälä76688512014-01-10 11:28:06 +020010376 config->save_crtc_enabled =
10377 kcalloc(dev->mode_config.num_crtc,
10378 sizeof(bool), GFP_KERNEL);
10379 if (!config->save_crtc_enabled)
10380 return -ENOMEM;
10381
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010382 config->save_encoder_crtcs =
10383 kcalloc(dev->mode_config.num_encoder,
10384 sizeof(struct drm_crtc *), GFP_KERNEL);
10385 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010386 return -ENOMEM;
10387
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010388 config->save_connector_encoders =
10389 kcalloc(dev->mode_config.num_connector,
10390 sizeof(struct drm_encoder *), GFP_KERNEL);
10391 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010392 return -ENOMEM;
10393
10394 /* Copy data. Note that driver private data is not affected.
10395 * Should anything bad happen only the expected state is
10396 * restored, not the drivers personal bookkeeping.
10397 */
10398 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010399 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010400 config->save_crtc_enabled[count++] = crtc->enabled;
10401 }
10402
10403 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010404 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010405 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010406 }
10407
10408 count = 0;
10409 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010410 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010411 }
10412
10413 return 0;
10414}
10415
10416static void intel_set_config_restore_state(struct drm_device *dev,
10417 struct intel_set_config *config)
10418{
Ville Syrjälä76688512014-01-10 11:28:06 +020010419 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020010420 struct intel_encoder *encoder;
10421 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010422 int count;
10423
10424 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010425 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010426 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010427
10428 if (crtc->new_enabled)
10429 crtc->new_config = &crtc->config;
10430 else
10431 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010432 }
10433
10434 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010435 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10436 encoder->new_crtc =
10437 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010438 }
10439
10440 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010441 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10442 connector->new_encoder =
10443 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010444 }
10445}
10446
Imre Deake3de42b2013-05-03 19:44:07 +020010447static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010010448is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020010449{
10450 int i;
10451
Chris Wilson2e57f472013-07-17 12:14:40 +010010452 if (set->num_connectors == 0)
10453 return false;
10454
10455 if (WARN_ON(set->connectors == NULL))
10456 return false;
10457
10458 for (i = 0; i < set->num_connectors; i++)
10459 if (set->connectors[i]->encoder &&
10460 set->connectors[i]->encoder->crtc == set->crtc &&
10461 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020010462 return true;
10463
10464 return false;
10465}
10466
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010467static void
10468intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10469 struct intel_set_config *config)
10470{
10471
10472 /* We should be able to check here if the fb has the same properties
10473 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010010474 if (is_crtc_connector_off(set)) {
10475 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070010476 } else if (set->crtc->primary->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010477 /* If we have no fb then treat it as a full mode set */
Matt Roperf4510a22014-04-01 15:22:40 -070010478 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030010479 struct intel_crtc *intel_crtc =
10480 to_intel_crtc(set->crtc);
10481
Jani Nikulad330a952014-01-21 11:24:25 +020010482 if (intel_crtc->active && i915.fastboot) {
Jesse Barnes319d9822013-06-26 01:38:19 +030010483 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10484 config->fb_changed = true;
10485 } else {
10486 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10487 config->mode_changed = true;
10488 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010489 } else if (set->fb == NULL) {
10490 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010010491 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070010492 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010493 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020010494 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010495 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020010496 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010497 }
10498
Daniel Vetter835c5872012-07-10 18:11:08 +020010499 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010500 config->fb_changed = true;
10501
10502 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10503 DRM_DEBUG_KMS("modes are different, full mode set\n");
10504 drm_mode_debug_printmodeline(&set->crtc->mode);
10505 drm_mode_debug_printmodeline(set->mode);
10506 config->mode_changed = true;
10507 }
Chris Wilsona1d95702013-08-13 18:48:47 +010010508
10509 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10510 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010511}
10512
Daniel Vetter2e431052012-07-04 22:42:15 +020010513static int
Daniel Vetter9a935852012-07-05 22:34:27 +020010514intel_modeset_stage_output_state(struct drm_device *dev,
10515 struct drm_mode_set *set,
10516 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020010517{
Daniel Vetter9a935852012-07-05 22:34:27 +020010518 struct intel_connector *connector;
10519 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020010520 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030010521 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020010522
Damien Lespiau9abdda72013-02-13 13:29:23 +000010523 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020010524 * of connectors. For paranoia, double-check this. */
10525 WARN_ON(!set->fb && (set->num_connectors != 0));
10526 WARN_ON(set->fb && (set->num_connectors == 0));
10527
Daniel Vetter9a935852012-07-05 22:34:27 +020010528 list_for_each_entry(connector, &dev->mode_config.connector_list,
10529 base.head) {
10530 /* Otherwise traverse passed in connector list and get encoders
10531 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020010532 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010533 if (set->connectors[ro] == &connector->base) {
10534 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +020010535 break;
10536 }
10537 }
10538
Daniel Vetter9a935852012-07-05 22:34:27 +020010539 /* If we disable the crtc, disable all its connectors. Also, if
10540 * the connector is on the changing crtc but not on the new
10541 * connector list, disable it. */
10542 if ((!set->fb || ro == set->num_connectors) &&
10543 connector->base.encoder &&
10544 connector->base.encoder->crtc == set->crtc) {
10545 connector->new_encoder = NULL;
10546
10547 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10548 connector->base.base.id,
10549 drm_get_connector_name(&connector->base));
10550 }
10551
10552
10553 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020010554 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010555 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020010556 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010557 }
10558 /* connector->new_encoder is now updated for all connectors. */
10559
10560 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020010561 list_for_each_entry(connector, &dev->mode_config.connector_list,
10562 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010563 struct drm_crtc *new_crtc;
10564
Daniel Vetter9a935852012-07-05 22:34:27 +020010565 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020010566 continue;
10567
Daniel Vetter9a935852012-07-05 22:34:27 +020010568 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020010569
10570 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010571 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020010572 new_crtc = set->crtc;
10573 }
10574
10575 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010010576 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10577 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010578 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020010579 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010580 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10581
10582 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10583 connector->base.base.id,
10584 drm_get_connector_name(&connector->base),
10585 new_crtc->base.id);
10586 }
10587
10588 /* Check for any encoders that needs to be disabled. */
10589 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10590 base.head) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010591 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010592 list_for_each_entry(connector,
10593 &dev->mode_config.connector_list,
10594 base.head) {
10595 if (connector->new_encoder == encoder) {
10596 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010597 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020010598 }
10599 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010600
10601 if (num_connectors == 0)
10602 encoder->new_crtc = NULL;
10603 else if (num_connectors > 1)
10604 return -EINVAL;
10605
Daniel Vetter9a935852012-07-05 22:34:27 +020010606 /* Only now check for crtc changes so we don't miss encoders
10607 * that will be disabled. */
10608 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020010609 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010610 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020010611 }
10612 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010613 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +020010614
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010615 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010616 crtc->new_enabled = false;
10617
10618 list_for_each_entry(encoder,
10619 &dev->mode_config.encoder_list,
10620 base.head) {
10621 if (encoder->new_crtc == crtc) {
10622 crtc->new_enabled = true;
10623 break;
10624 }
10625 }
10626
10627 if (crtc->new_enabled != crtc->base.enabled) {
10628 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10629 crtc->new_enabled ? "en" : "dis");
10630 config->mode_changed = true;
10631 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010632
10633 if (crtc->new_enabled)
10634 crtc->new_config = &crtc->config;
10635 else
10636 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010637 }
10638
Daniel Vetter2e431052012-07-04 22:42:15 +020010639 return 0;
10640}
10641
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010642static void disable_crtc_nofb(struct intel_crtc *crtc)
10643{
10644 struct drm_device *dev = crtc->base.dev;
10645 struct intel_encoder *encoder;
10646 struct intel_connector *connector;
10647
10648 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10649 pipe_name(crtc->pipe));
10650
10651 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10652 if (connector->new_encoder &&
10653 connector->new_encoder->new_crtc == crtc)
10654 connector->new_encoder = NULL;
10655 }
10656
10657 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10658 if (encoder->new_crtc == crtc)
10659 encoder->new_crtc = NULL;
10660 }
10661
10662 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010663 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010664}
10665
Daniel Vetter2e431052012-07-04 22:42:15 +020010666static int intel_crtc_set_config(struct drm_mode_set *set)
10667{
10668 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020010669 struct drm_mode_set save_set;
10670 struct intel_set_config *config;
10671 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020010672
Daniel Vetter8d3e3752012-07-05 16:09:09 +020010673 BUG_ON(!set);
10674 BUG_ON(!set->crtc);
10675 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020010676
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010010677 /* Enforce sane interface api - has been abused by the fb helper. */
10678 BUG_ON(!set->mode && set->fb);
10679 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020010680
Daniel Vetter2e431052012-07-04 22:42:15 +020010681 if (set->fb) {
10682 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10683 set->crtc->base.id, set->fb->base.id,
10684 (int)set->num_connectors, set->x, set->y);
10685 } else {
10686 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020010687 }
10688
10689 dev = set->crtc->dev;
10690
10691 ret = -ENOMEM;
10692 config = kzalloc(sizeof(*config), GFP_KERNEL);
10693 if (!config)
10694 goto out_config;
10695
10696 ret = intel_set_config_save_state(dev, config);
10697 if (ret)
10698 goto out_config;
10699
10700 save_set.crtc = set->crtc;
10701 save_set.mode = &set->crtc->mode;
10702 save_set.x = set->crtc->x;
10703 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070010704 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020010705
10706 /* Compute whether we need a full modeset, only an fb base update or no
10707 * change at all. In the future we might also check whether only the
10708 * mode changed, e.g. for LVDS where we only change the panel fitter in
10709 * such cases. */
10710 intel_set_config_compute_mode_changes(set, config);
10711
Daniel Vetter9a935852012-07-05 22:34:27 +020010712 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020010713 if (ret)
10714 goto fail;
10715
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010716 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010717 ret = intel_set_mode(set->crtc, set->mode,
10718 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010719 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +020010720 intel_crtc_wait_for_pending_flips(set->crtc);
10721
Daniel Vetter4f660f42012-07-02 09:47:37 +020010722 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020010723 set->x, set->y, set->fb);
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010724 /*
10725 * In the fastboot case this may be our only check of the
10726 * state after boot. It would be better to only do it on
10727 * the first update, but we don't have a nice way of doing that
10728 * (and really, set_config isn't used much for high freq page
10729 * flipping, so increasing its cost here shouldn't be a big
10730 * deal).
10731 */
Jani Nikulad330a952014-01-21 11:24:25 +020010732 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010733 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020010734 }
10735
Chris Wilson2d05eae2013-05-03 17:36:25 +010010736 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020010737 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10738 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020010739fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010010740 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010741
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010742 /*
10743 * HACK: if the pipe was on, but we didn't have a framebuffer,
10744 * force the pipe off to avoid oopsing in the modeset code
10745 * due to fb==NULL. This should only happen during boot since
10746 * we don't yet reconstruct the FB from the hardware state.
10747 */
10748 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10749 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10750
Chris Wilson2d05eae2013-05-03 17:36:25 +010010751 /* Try to restore the config */
10752 if (config->mode_changed &&
10753 intel_set_mode(save_set.crtc, save_set.mode,
10754 save_set.x, save_set.y, save_set.fb))
10755 DRM_ERROR("failed to restore config after modeset failure\n");
10756 }
Daniel Vetter50f56112012-07-02 09:35:43 +020010757
Daniel Vetterd9e55602012-07-04 22:16:09 +020010758out_config:
10759 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010760 return ret;
10761}
10762
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010763static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010764 .cursor_set = intel_crtc_cursor_set,
10765 .cursor_move = intel_crtc_cursor_move,
10766 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020010767 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010768 .destroy = intel_crtc_destroy,
10769 .page_flip = intel_crtc_page_flip,
10770};
10771
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010772static void intel_cpu_pll_init(struct drm_device *dev)
10773{
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010774 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010775 intel_ddi_pll_init(dev);
10776}
10777
Daniel Vetter53589012013-06-05 13:34:16 +020010778static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10779 struct intel_shared_dpll *pll,
10780 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010781{
Daniel Vetter53589012013-06-05 13:34:16 +020010782 uint32_t val;
10783
10784 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020010785 hw_state->dpll = val;
10786 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10787 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020010788
10789 return val & DPLL_VCO_ENABLE;
10790}
10791
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010792static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10793 struct intel_shared_dpll *pll)
10794{
10795 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10796 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10797}
10798
Daniel Vettere7b903d2013-06-05 13:34:14 +020010799static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10800 struct intel_shared_dpll *pll)
10801{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010802 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020010803 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020010804
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010805 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10806
10807 /* Wait for the clocks to stabilize. */
10808 POSTING_READ(PCH_DPLL(pll->id));
10809 udelay(150);
10810
10811 /* The pixel multiplier can only be updated once the
10812 * DPLL is enabled and the clocks are stable.
10813 *
10814 * So write it again.
10815 */
10816 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10817 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010818 udelay(200);
10819}
10820
10821static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10822 struct intel_shared_dpll *pll)
10823{
10824 struct drm_device *dev = dev_priv->dev;
10825 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010826
10827 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010828 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020010829 if (intel_crtc_to_shared_dpll(crtc) == pll)
10830 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10831 }
10832
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010833 I915_WRITE(PCH_DPLL(pll->id), 0);
10834 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010835 udelay(200);
10836}
10837
Daniel Vetter46edb022013-06-05 13:34:12 +020010838static char *ibx_pch_dpll_names[] = {
10839 "PCH DPLL A",
10840 "PCH DPLL B",
10841};
10842
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010843static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010844{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010845 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010846 int i;
10847
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010848 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010849
Daniel Vettere72f9fb2013-06-05 13:34:06 +020010850 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020010851 dev_priv->shared_dplls[i].id = i;
10852 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010853 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010854 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10855 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020010856 dev_priv->shared_dplls[i].get_hw_state =
10857 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010858 }
10859}
10860
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010861static void intel_shared_dpll_init(struct drm_device *dev)
10862{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010863 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010864
10865 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10866 ibx_pch_dpll_init(dev);
10867 else
10868 dev_priv->num_shared_dpll = 0;
10869
10870 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010871}
10872
Hannes Ederb358d0a2008-12-18 21:18:47 +010010873static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080010874{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010875 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010876 struct intel_crtc *intel_crtc;
10877 int i;
10878
Daniel Vetter955382f2013-09-19 14:05:45 +020010879 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080010880 if (intel_crtc == NULL)
10881 return;
10882
10883 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10884
10885 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080010886 for (i = 0; i < 256; i++) {
10887 intel_crtc->lut_r[i] = i;
10888 intel_crtc->lut_g[i] = i;
10889 intel_crtc->lut_b[i] = i;
10890 }
10891
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020010892 /*
10893 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10894 * is hooked to plane B. Hence we want plane A feeding pipe B.
10895 */
Jesse Barnes80824002009-09-10 15:28:06 -070010896 intel_crtc->pipe = pipe;
10897 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010010898 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080010899 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010010900 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070010901 }
10902
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030010903 init_waitqueue_head(&intel_crtc->vbl_wait);
10904
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010905 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10906 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10907 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10908 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10909
Jesse Barnes79e53942008-11-07 14:24:08 -080010910 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020010911
10912 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -080010913}
10914
Jesse Barnes752aa882013-10-31 18:55:49 +020010915enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10916{
10917 struct drm_encoder *encoder = connector->base.encoder;
10918
10919 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10920
10921 if (!encoder)
10922 return INVALID_PIPE;
10923
10924 return to_intel_crtc(encoder->crtc)->pipe;
10925}
10926
Carl Worth08d7b3d2009-04-29 14:43:54 -070010927int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000010928 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070010929{
Carl Worth08d7b3d2009-04-29 14:43:54 -070010930 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +020010931 struct drm_mode_object *drmmode_obj;
10932 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010933
Daniel Vetter1cff8f62012-04-24 09:55:08 +020010934 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10935 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010936
Daniel Vetterc05422d2009-08-11 16:05:30 +020010937 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10938 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -070010939
Daniel Vetterc05422d2009-08-11 16:05:30 +020010940 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070010941 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030010942 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010943 }
10944
Daniel Vetterc05422d2009-08-11 16:05:30 +020010945 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10946 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010947
Daniel Vetterc05422d2009-08-11 16:05:30 +020010948 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010949}
10950
Daniel Vetter66a92782012-07-12 20:08:18 +020010951static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080010952{
Daniel Vetter66a92782012-07-12 20:08:18 +020010953 struct drm_device *dev = encoder->base.dev;
10954 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080010955 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080010956 int entry = 0;
10957
Daniel Vetter66a92782012-07-12 20:08:18 +020010958 list_for_each_entry(source_encoder,
10959 &dev->mode_config.encoder_list, base.head) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010960 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020010961 index_mask |= (1 << entry);
10962
Jesse Barnes79e53942008-11-07 14:24:08 -080010963 entry++;
10964 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010010965
Jesse Barnes79e53942008-11-07 14:24:08 -080010966 return index_mask;
10967}
10968
Chris Wilson4d302442010-12-14 19:21:29 +000010969static bool has_edp_a(struct drm_device *dev)
10970{
10971 struct drm_i915_private *dev_priv = dev->dev_private;
10972
10973 if (!IS_MOBILE(dev))
10974 return false;
10975
10976 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10977 return false;
10978
Damien Lespiaue3589902014-02-07 19:12:50 +000010979 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000010980 return false;
10981
10982 return true;
10983}
10984
Damien Lespiauba0fbca2014-01-08 14:18:23 +000010985const char *intel_output_name(int output)
10986{
10987 static const char *names[] = {
10988 [INTEL_OUTPUT_UNUSED] = "Unused",
10989 [INTEL_OUTPUT_ANALOG] = "Analog",
10990 [INTEL_OUTPUT_DVO] = "DVO",
10991 [INTEL_OUTPUT_SDVO] = "SDVO",
10992 [INTEL_OUTPUT_LVDS] = "LVDS",
10993 [INTEL_OUTPUT_TVOUT] = "TV",
10994 [INTEL_OUTPUT_HDMI] = "HDMI",
10995 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10996 [INTEL_OUTPUT_EDP] = "eDP",
10997 [INTEL_OUTPUT_DSI] = "DSI",
10998 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10999 };
11000
11001 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11002 return "Invalid";
11003
11004 return names[output];
11005}
11006
Jesse Barnes79e53942008-11-07 14:24:08 -080011007static void intel_setup_outputs(struct drm_device *dev)
11008{
Eric Anholt725e30a2009-01-22 13:01:02 -080011009 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010011010 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011011 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080011012
Daniel Vetterc9093352013-06-06 22:22:47 +020011013 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011014
Ville Syrjälä7895a812014-04-09 13:28:23 +030011015 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020011016 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011017
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011018 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030011019 int found;
11020
11021 /* Haswell uses DDI functions to detect digital outputs */
11022 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11023 /* DDI A only supports eDP */
11024 if (found)
11025 intel_ddi_init(dev, PORT_A);
11026
11027 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11028 * register */
11029 found = I915_READ(SFUSE_STRAP);
11030
11031 if (found & SFUSE_STRAP_DDIB_DETECTED)
11032 intel_ddi_init(dev, PORT_B);
11033 if (found & SFUSE_STRAP_DDIC_DETECTED)
11034 intel_ddi_init(dev, PORT_C);
11035 if (found & SFUSE_STRAP_DDID_DETECTED)
11036 intel_ddi_init(dev, PORT_D);
11037 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011038 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011039 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020011040
11041 if (has_edp_a(dev))
11042 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011043
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011044 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080011045 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010011046 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011047 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011048 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011049 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011050 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011051 }
11052
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011053 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011054 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011055
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011056 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011057 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011058
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011059 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011060 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011061
Daniel Vetter270b3042012-10-27 15:52:05 +020011062 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011063 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070011064 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030011065 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11066 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11067 PORT_B);
11068 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11069 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11070 }
11071
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011072 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11073 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11074 PORT_C);
11075 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011076 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011077 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053011078
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030011079 if (IS_CHERRYVIEW(dev)) {
11080 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11081 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11082 PORT_D);
11083 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11084 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11085 }
11086 }
11087
Jani Nikula3cfca972013-08-27 15:12:26 +030011088 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080011089 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011090 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080011091
Paulo Zanonie2debe92013-02-18 19:00:27 -030011092 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011093 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011094 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011095 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11096 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011097 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011098 }
Ma Ling27185ae2009-08-24 13:50:23 +080011099
Imre Deake7281ea2013-05-08 13:14:08 +030011100 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011101 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080011102 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011103
11104 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011105
Paulo Zanonie2debe92013-02-18 19:00:27 -030011106 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011107 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011108 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011109 }
Ma Ling27185ae2009-08-24 13:50:23 +080011110
Paulo Zanonie2debe92013-02-18 19:00:27 -030011111 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011112
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011113 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11114 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011115 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011116 }
Imre Deake7281ea2013-05-08 13:14:08 +030011117 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011118 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080011119 }
Ma Ling27185ae2009-08-24 13:50:23 +080011120
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011121 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030011122 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011123 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070011124 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011125 intel_dvo_init(dev);
11126
Zhenyu Wang103a1962009-11-27 11:44:36 +080011127 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011128 intel_tv_init(dev);
11129
Chris Wilson4ef69c72010-09-09 15:14:28 +010011130 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11131 encoder->base.possible_crtcs = encoder->crtc_mask;
11132 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020011133 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080011134 }
Chris Wilson47356eb2011-01-11 17:06:04 +000011135
Paulo Zanonidde86e22012-12-01 12:04:25 -020011136 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020011137
11138 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011139}
11140
11141static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11142{
11143 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080011144
Daniel Vetteref2d6332014-02-10 18:00:38 +010011145 drm_framebuffer_cleanup(fb);
11146 WARN_ON(!intel_fb->obj->framebuffer_references--);
11147 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080011148 kfree(intel_fb);
11149}
11150
11151static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000011152 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080011153 unsigned int *handle)
11154{
11155 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000011156 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080011157
Chris Wilson05394f32010-11-08 19:18:58 +000011158 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080011159}
11160
11161static const struct drm_framebuffer_funcs intel_fb_funcs = {
11162 .destroy = intel_user_framebuffer_destroy,
11163 .create_handle = intel_user_framebuffer_create_handle,
11164};
11165
Daniel Vetterb5ea6422014-03-02 21:18:00 +010011166static int intel_framebuffer_init(struct drm_device *dev,
11167 struct intel_framebuffer *intel_fb,
11168 struct drm_mode_fb_cmd2 *mode_cmd,
11169 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080011170{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080011171 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010011172 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080011173 int ret;
11174
Daniel Vetterdd4916c2013-10-09 21:23:51 +020011175 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11176
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011177 if (obj->tiling_mode == I915_TILING_Y) {
11178 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010011179 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011180 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011181
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011182 if (mode_cmd->pitches[0] & 63) {
11183 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11184 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010011185 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011186 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011187
Chris Wilsona35cdaa2013-06-25 17:26:45 +010011188 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11189 pitch_limit = 32*1024;
11190 } else if (INTEL_INFO(dev)->gen >= 4) {
11191 if (obj->tiling_mode)
11192 pitch_limit = 16*1024;
11193 else
11194 pitch_limit = 32*1024;
11195 } else if (INTEL_INFO(dev)->gen >= 3) {
11196 if (obj->tiling_mode)
11197 pitch_limit = 8*1024;
11198 else
11199 pitch_limit = 16*1024;
11200 } else
11201 /* XXX DSPC is limited to 4k tiled */
11202 pitch_limit = 8*1024;
11203
11204 if (mode_cmd->pitches[0] > pitch_limit) {
11205 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11206 obj->tiling_mode ? "tiled" : "linear",
11207 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011208 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011209 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011210
11211 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011212 mode_cmd->pitches[0] != obj->stride) {
11213 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11214 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011215 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011216 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011217
Ville Syrjälä57779d02012-10-31 17:50:14 +020011218 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011219 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020011220 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020011221 case DRM_FORMAT_RGB565:
11222 case DRM_FORMAT_XRGB8888:
11223 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020011224 break;
11225 case DRM_FORMAT_XRGB1555:
11226 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011227 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011228 DRM_DEBUG("unsupported pixel format: %s\n",
11229 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011230 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011231 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020011232 break;
11233 case DRM_FORMAT_XBGR8888:
11234 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020011235 case DRM_FORMAT_XRGB2101010:
11236 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020011237 case DRM_FORMAT_XBGR2101010:
11238 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011239 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011240 DRM_DEBUG("unsupported pixel format: %s\n",
11241 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011242 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011243 }
Jesse Barnesb5626742011-06-24 12:19:27 -070011244 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020011245 case DRM_FORMAT_YUYV:
11246 case DRM_FORMAT_UYVY:
11247 case DRM_FORMAT_YVYU:
11248 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011249 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011250 DRM_DEBUG("unsupported pixel format: %s\n",
11251 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011252 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011253 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011254 break;
11255 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011256 DRM_DEBUG("unsupported pixel format: %s\n",
11257 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010011258 return -EINVAL;
11259 }
11260
Ville Syrjälä90f9a332012-10-31 17:50:19 +020011261 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11262 if (mode_cmd->offsets[0] != 0)
11263 return -EINVAL;
11264
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080011265 aligned_height = intel_align_height(dev, mode_cmd->height,
11266 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020011267 /* FIXME drm helper for size checks (especially planar formats)? */
11268 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11269 return -EINVAL;
11270
Daniel Vetterc7d73f62012-12-13 23:38:38 +010011271 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11272 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020011273 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010011274
Jesse Barnes79e53942008-11-07 14:24:08 -080011275 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11276 if (ret) {
11277 DRM_ERROR("framebuffer init failed %d\n", ret);
11278 return ret;
11279 }
11280
Jesse Barnes79e53942008-11-07 14:24:08 -080011281 return 0;
11282}
11283
Jesse Barnes79e53942008-11-07 14:24:08 -080011284static struct drm_framebuffer *
11285intel_user_framebuffer_create(struct drm_device *dev,
11286 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011287 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080011288{
Chris Wilson05394f32010-11-08 19:18:58 +000011289 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080011290
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011291 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11292 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000011293 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010011294 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080011295
Chris Wilsond2dff872011-04-19 08:36:26 +010011296 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080011297}
11298
Daniel Vetter4520f532013-10-09 09:18:51 +020011299#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020011300static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020011301{
11302}
11303#endif
11304
Jesse Barnes79e53942008-11-07 14:24:08 -080011305static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080011306 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020011307 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080011308};
11309
Jesse Barnese70236a2009-09-21 10:42:27 -070011310/* Set up chip specific display functions */
11311static void intel_init_display(struct drm_device *dev)
11312{
11313 struct drm_i915_private *dev_priv = dev->dev_private;
11314
Daniel Vetteree9300b2013-06-03 22:40:22 +020011315 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11316 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030011317 else if (IS_CHERRYVIEW(dev))
11318 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020011319 else if (IS_VALLEYVIEW(dev))
11320 dev_priv->display.find_dpll = vlv_find_best_dpll;
11321 else if (IS_PINEVIEW(dev))
11322 dev_priv->display.find_dpll = pnv_find_best_dpll;
11323 else
11324 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11325
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011326 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011327 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080011328 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030011329 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020011330 dev_priv->display.crtc_enable = haswell_crtc_enable;
11331 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -030011332 dev_priv->display.off = haswell_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011333 dev_priv->display.update_primary_plane =
11334 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030011335 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011336 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080011337 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070011338 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020011339 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11340 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011341 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011342 dev_priv->display.update_primary_plane =
11343 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070011344 } else if (IS_VALLEYVIEW(dev)) {
11345 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080011346 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070011347 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11348 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11349 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11350 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011351 dev_priv->display.update_primary_plane =
11352 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070011353 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011354 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080011355 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070011356 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020011357 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11358 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011359 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011360 dev_priv->display.update_primary_plane =
11361 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070011362 }
Jesse Barnese70236a2009-09-21 10:42:27 -070011363
Jesse Barnese70236a2009-09-21 10:42:27 -070011364 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070011365 if (IS_VALLEYVIEW(dev))
11366 dev_priv->display.get_display_clock_speed =
11367 valleyview_get_display_clock_speed;
11368 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070011369 dev_priv->display.get_display_clock_speed =
11370 i945_get_display_clock_speed;
11371 else if (IS_I915G(dev))
11372 dev_priv->display.get_display_clock_speed =
11373 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020011374 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070011375 dev_priv->display.get_display_clock_speed =
11376 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020011377 else if (IS_PINEVIEW(dev))
11378 dev_priv->display.get_display_clock_speed =
11379 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070011380 else if (IS_I915GM(dev))
11381 dev_priv->display.get_display_clock_speed =
11382 i915gm_get_display_clock_speed;
11383 else if (IS_I865G(dev))
11384 dev_priv->display.get_display_clock_speed =
11385 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020011386 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070011387 dev_priv->display.get_display_clock_speed =
11388 i855_get_display_clock_speed;
11389 else /* 852, 830 */
11390 dev_priv->display.get_display_clock_speed =
11391 i830_get_display_clock_speed;
11392
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080011393 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010011394 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070011395 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011396 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080011397 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070011398 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011399 dev_priv->display.write_eld = ironlake_write_eld;
Paulo Zanoni9a952a02014-03-07 20:12:34 -030011400 dev_priv->display.modeset_global_resources =
11401 snb_modeset_global_resources;
Jesse Barnes357555c2011-04-28 15:09:55 -070011402 } else if (IS_IVYBRIDGE(dev)) {
11403 /* FIXME: detect B0+ stepping and use auto training */
11404 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011405 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020011406 dev_priv->display.modeset_global_resources =
11407 ivb_modeset_global_resources;
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070011408 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030011409 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080011410 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020011411 dev_priv->display.modeset_global_resources =
11412 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020011413 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070011414 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080011415 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080011416 } else if (IS_VALLEYVIEW(dev)) {
11417 dev_priv->display.modeset_global_resources =
11418 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040011419 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070011420 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011421
11422 /* Default just returns -ENODEV to indicate unsupported */
11423 dev_priv->display.queue_flip = intel_default_queue_flip;
11424
11425 switch (INTEL_INFO(dev)->gen) {
11426 case 2:
11427 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11428 break;
11429
11430 case 3:
11431 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11432 break;
11433
11434 case 4:
11435 case 5:
11436 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11437 break;
11438
11439 case 6:
11440 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11441 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011442 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070011443 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011444 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11445 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011446 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020011447
11448 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070011449}
11450
Jesse Barnesb690e962010-07-19 13:53:12 -070011451/*
11452 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11453 * resume, or other times. This quirk makes sure that's the case for
11454 * affected systems.
11455 */
Akshay Joshi0206e352011-08-16 15:34:10 -040011456static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070011457{
11458 struct drm_i915_private *dev_priv = dev->dev_private;
11459
11460 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011461 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070011462}
11463
Keith Packard435793d2011-07-12 14:56:22 -070011464/*
11465 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11466 */
11467static void quirk_ssc_force_disable(struct drm_device *dev)
11468{
11469 struct drm_i915_private *dev_priv = dev->dev_private;
11470 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011471 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070011472}
11473
Carsten Emde4dca20e2012-03-15 15:56:26 +010011474/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010011475 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11476 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010011477 */
11478static void quirk_invert_brightness(struct drm_device *dev)
11479{
11480 struct drm_i915_private *dev_priv = dev->dev_private;
11481 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011482 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070011483}
11484
11485struct intel_quirk {
11486 int device;
11487 int subsystem_vendor;
11488 int subsystem_device;
11489 void (*hook)(struct drm_device *dev);
11490};
11491
Egbert Eich5f85f172012-10-14 15:46:38 +020011492/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11493struct intel_dmi_quirk {
11494 void (*hook)(struct drm_device *dev);
11495 const struct dmi_system_id (*dmi_id_list)[];
11496};
11497
11498static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11499{
11500 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11501 return 1;
11502}
11503
11504static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11505 {
11506 .dmi_id_list = &(const struct dmi_system_id[]) {
11507 {
11508 .callback = intel_dmi_reverse_brightness,
11509 .ident = "NCR Corporation",
11510 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11511 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11512 },
11513 },
11514 { } /* terminating entry */
11515 },
11516 .hook = quirk_invert_brightness,
11517 },
11518};
11519
Ben Widawskyc43b5632012-04-16 14:07:40 -070011520static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070011521 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040011522 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070011523
Jesse Barnesb690e962010-07-19 13:53:12 -070011524 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11525 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11526
Jesse Barnesb690e962010-07-19 13:53:12 -070011527 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11528 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11529
Chris Wilsona4945f92013-10-08 11:16:59 +010011530 /* 830 needs to leave pipe A & dpll A up */
Daniel Vetterdcdaed62012-08-12 21:19:34 +020011531 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -070011532
11533 /* Lenovo U160 cannot use SSC on LVDS */
11534 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020011535
11536 /* Sony Vaio Y cannot use SSC on LVDS */
11537 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010011538
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010011539 /* Acer Aspire 5734Z must invert backlight brightness */
11540 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11541
11542 /* Acer/eMachines G725 */
11543 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11544
11545 /* Acer/eMachines e725 */
11546 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11547
11548 /* Acer/Packard Bell NCL20 */
11549 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11550
11551 /* Acer Aspire 4736Z */
11552 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020011553
11554 /* Acer Aspire 5336 */
11555 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -070011556};
11557
11558static void intel_init_quirks(struct drm_device *dev)
11559{
11560 struct pci_dev *d = dev->pdev;
11561 int i;
11562
11563 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11564 struct intel_quirk *q = &intel_quirks[i];
11565
11566 if (d->device == q->device &&
11567 (d->subsystem_vendor == q->subsystem_vendor ||
11568 q->subsystem_vendor == PCI_ANY_ID) &&
11569 (d->subsystem_device == q->subsystem_device ||
11570 q->subsystem_device == PCI_ANY_ID))
11571 q->hook(dev);
11572 }
Egbert Eich5f85f172012-10-14 15:46:38 +020011573 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11574 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11575 intel_dmi_quirks[i].hook(dev);
11576 }
Jesse Barnesb690e962010-07-19 13:53:12 -070011577}
11578
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011579/* Disable the VGA plane that we never use */
11580static void i915_disable_vga(struct drm_device *dev)
11581{
11582 struct drm_i915_private *dev_priv = dev->dev_private;
11583 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020011584 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011585
Ville Syrjälä2b37c612014-01-22 21:32:38 +020011586 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011587 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070011588 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011589 sr1 = inb(VGA_SR_DATA);
11590 outb(sr1 | 1<<5, VGA_SR_DATA);
11591 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11592 udelay(300);
11593
11594 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11595 POSTING_READ(vga_reg);
11596}
11597
Daniel Vetterf8175862012-04-10 15:50:11 +020011598void intel_modeset_init_hw(struct drm_device *dev)
11599{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030011600 intel_prepare_ddi(dev);
11601
Daniel Vetterf8175862012-04-10 15:50:11 +020011602 intel_init_clock_gating(dev);
11603
Jesse Barnes5382f5f352013-12-16 16:34:24 -080011604 intel_reset_dpio(dev);
Jesse Barnes40e9cf62013-10-03 11:35:46 -070011605
Daniel Vetter8090c6b2012-06-24 16:42:32 +020011606 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020011607}
11608
Imre Deak7d708ee2013-04-17 14:04:50 +030011609void intel_modeset_suspend_hw(struct drm_device *dev)
11610{
11611 intel_suspend_hw(dev);
11612}
11613
Jesse Barnes79e53942008-11-07 14:24:08 -080011614void intel_modeset_init(struct drm_device *dev)
11615{
Jesse Barnes652c3932009-08-17 13:31:43 -070011616 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000011617 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000011618 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080011619 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080011620
11621 drm_mode_config_init(dev);
11622
11623 dev->mode_config.min_width = 0;
11624 dev->mode_config.min_height = 0;
11625
Dave Airlie019d96c2011-09-29 16:20:42 +010011626 dev->mode_config.preferred_depth = 24;
11627 dev->mode_config.prefer_shadow = 1;
11628
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020011629 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080011630
Jesse Barnesb690e962010-07-19 13:53:12 -070011631 intel_init_quirks(dev);
11632
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030011633 intel_init_pm(dev);
11634
Ben Widawskye3c74752013-04-05 13:12:39 -070011635 if (INTEL_INFO(dev)->num_pipes == 0)
11636 return;
11637
Jesse Barnese70236a2009-09-21 10:42:27 -070011638 intel_init_display(dev);
11639
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011640 if (IS_GEN2(dev)) {
11641 dev->mode_config.max_width = 2048;
11642 dev->mode_config.max_height = 2048;
11643 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070011644 dev->mode_config.max_width = 4096;
11645 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080011646 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011647 dev->mode_config.max_width = 8192;
11648 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080011649 }
Damien Lespiau068be562014-03-28 14:17:49 +000011650
11651 if (IS_GEN2(dev)) {
11652 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11653 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11654 } else {
11655 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11656 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11657 }
11658
Ben Widawsky5d4545a2013-01-17 12:45:15 -080011659 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080011660
Zhao Yakui28c97732009-10-09 11:39:41 +080011661 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011662 INTEL_INFO(dev)->num_pipes,
11663 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080011664
Damien Lespiau8cc87b72014-03-03 17:31:44 +000011665 for_each_pipe(pipe) {
11666 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000011667 for_each_sprite(pipe, sprite) {
11668 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070011669 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030011670 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000011671 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070011672 }
Jesse Barnes79e53942008-11-07 14:24:08 -080011673 }
11674
Jesse Barnesf42bb702013-12-16 16:34:23 -080011675 intel_init_dpio(dev);
Jesse Barnes5382f5f352013-12-16 16:34:24 -080011676 intel_reset_dpio(dev);
Jesse Barnesf42bb702013-12-16 16:34:23 -080011677
Paulo Zanoni79f689a2012-10-05 12:05:52 -030011678 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011679 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011680
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011681 /* Just disable it once at startup */
11682 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011683 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000011684
11685 /* Just in case the BIOS is doing something questionable. */
11686 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080011687
Jesse Barnes8b687df2014-02-21 13:13:39 -080011688 mutex_lock(&dev->mode_config.mutex);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080011689 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes8b687df2014-02-21 13:13:39 -080011690 mutex_unlock(&dev->mode_config.mutex);
Jesse Barnes46f297f2014-03-07 08:57:48 -080011691
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011692 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080011693 if (!crtc->active)
11694 continue;
11695
Jesse Barnes46f297f2014-03-07 08:57:48 -080011696 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080011697 * Note that reserving the BIOS fb up front prevents us
11698 * from stuffing other stolen allocations like the ring
11699 * on top. This prevents some ugliness at boot time, and
11700 * can even allow for smooth boot transitions if the BIOS
11701 * fb is large enough for the active pipe configuration.
11702 */
11703 if (dev_priv->display.get_plane_config) {
11704 dev_priv->display.get_plane_config(crtc,
11705 &crtc->plane_config);
11706 /*
11707 * If the fb is shared between multiple heads, we'll
11708 * just get the first one.
11709 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080011710 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080011711 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080011712 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010011713}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080011714
Daniel Vetter24929352012-07-02 20:28:59 +020011715static void
11716intel_connector_break_all_links(struct intel_connector *connector)
11717{
11718 connector->base.dpms = DRM_MODE_DPMS_OFF;
11719 connector->base.encoder = NULL;
11720 connector->encoder->connectors_active = false;
11721 connector->encoder->base.crtc = NULL;
11722}
11723
Daniel Vetter7fad7982012-07-04 17:51:47 +020011724static void intel_enable_pipe_a(struct drm_device *dev)
11725{
11726 struct intel_connector *connector;
11727 struct drm_connector *crt = NULL;
11728 struct intel_load_detect_pipe load_detect_temp;
11729
11730 /* We can't just switch on the pipe A, we need to set things up with a
11731 * proper mode and output configuration. As a gross hack, enable pipe A
11732 * by enabling the load detect pipe once. */
11733 list_for_each_entry(connector,
11734 &dev->mode_config.connector_list,
11735 base.head) {
11736 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11737 crt = &connector->base;
11738 break;
11739 }
11740 }
11741
11742 if (!crt)
11743 return;
11744
11745 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11746 intel_release_load_detect_pipe(crt, &load_detect_temp);
11747
11748
11749}
11750
Daniel Vetterfa555832012-10-10 23:14:00 +020011751static bool
11752intel_check_plane_mapping(struct intel_crtc *crtc)
11753{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011754 struct drm_device *dev = crtc->base.dev;
11755 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011756 u32 reg, val;
11757
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011758 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020011759 return true;
11760
11761 reg = DSPCNTR(!crtc->plane);
11762 val = I915_READ(reg);
11763
11764 if ((val & DISPLAY_PLANE_ENABLE) &&
11765 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11766 return false;
11767
11768 return true;
11769}
11770
Daniel Vetter24929352012-07-02 20:28:59 +020011771static void intel_sanitize_crtc(struct intel_crtc *crtc)
11772{
11773 struct drm_device *dev = crtc->base.dev;
11774 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011775 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020011776
Daniel Vetter24929352012-07-02 20:28:59 +020011777 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020011778 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020011779 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11780
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030011781 /* restore vblank interrupts to correct state */
11782 if (crtc->active)
11783 drm_vblank_on(dev, crtc->pipe);
11784 else
11785 drm_vblank_off(dev, crtc->pipe);
11786
Daniel Vetter24929352012-07-02 20:28:59 +020011787 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020011788 * disable the crtc (and hence change the state) if it is wrong. Note
11789 * that gen4+ has a fixed plane -> pipe mapping. */
11790 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020011791 struct intel_connector *connector;
11792 bool plane;
11793
Daniel Vetter24929352012-07-02 20:28:59 +020011794 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11795 crtc->base.base.id);
11796
11797 /* Pipe has the wrong plane attached and the plane is active.
11798 * Temporarily change the plane mapping and disable everything
11799 * ... */
11800 plane = crtc->plane;
11801 crtc->plane = !plane;
11802 dev_priv->display.crtc_disable(&crtc->base);
11803 crtc->plane = plane;
11804
11805 /* ... and break all links. */
11806 list_for_each_entry(connector, &dev->mode_config.connector_list,
11807 base.head) {
11808 if (connector->encoder->base.crtc != &crtc->base)
11809 continue;
11810
11811 intel_connector_break_all_links(connector);
11812 }
11813
11814 WARN_ON(crtc->active);
11815 crtc->base.enabled = false;
11816 }
Daniel Vetter24929352012-07-02 20:28:59 +020011817
Daniel Vetter7fad7982012-07-04 17:51:47 +020011818 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11819 crtc->pipe == PIPE_A && !crtc->active) {
11820 /* BIOS forgot to enable pipe A, this mostly happens after
11821 * resume. Force-enable the pipe to fix this, the update_dpms
11822 * call below we restore the pipe to the right state, but leave
11823 * the required bits on. */
11824 intel_enable_pipe_a(dev);
11825 }
11826
Daniel Vetter24929352012-07-02 20:28:59 +020011827 /* Adjust the state of the output pipe according to whether we
11828 * have active connectors/encoders. */
11829 intel_crtc_update_dpms(&crtc->base);
11830
11831 if (crtc->active != crtc->base.enabled) {
11832 struct intel_encoder *encoder;
11833
11834 /* This can happen either due to bugs in the get_hw_state
11835 * functions or because the pipe is force-enabled due to the
11836 * pipe A quirk. */
11837 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11838 crtc->base.base.id,
11839 crtc->base.enabled ? "enabled" : "disabled",
11840 crtc->active ? "enabled" : "disabled");
11841
11842 crtc->base.enabled = crtc->active;
11843
11844 /* Because we only establish the connector -> encoder ->
11845 * crtc links if something is active, this means the
11846 * crtc is now deactivated. Break the links. connector
11847 * -> encoder links are only establish when things are
11848 * actually up, hence no need to break them. */
11849 WARN_ON(crtc->active);
11850
11851 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11852 WARN_ON(encoder->connectors_active);
11853 encoder->base.crtc = NULL;
11854 }
11855 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020011856
11857 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010011858 /*
11859 * We start out with underrun reporting disabled to avoid races.
11860 * For correct bookkeeping mark this on active crtcs.
11861 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020011862 * Also on gmch platforms we dont have any hardware bits to
11863 * disable the underrun reporting. Which means we need to start
11864 * out with underrun reporting disabled also on inactive pipes,
11865 * since otherwise we'll complain about the garbage we read when
11866 * e.g. coming up after runtime pm.
11867 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010011868 * No protection against concurrent access is required - at
11869 * worst a fifo underrun happens which also sets this to false.
11870 */
11871 crtc->cpu_fifo_underrun_disabled = true;
11872 crtc->pch_fifo_underrun_disabled = true;
11873 }
Daniel Vetter24929352012-07-02 20:28:59 +020011874}
11875
11876static void intel_sanitize_encoder(struct intel_encoder *encoder)
11877{
11878 struct intel_connector *connector;
11879 struct drm_device *dev = encoder->base.dev;
11880
11881 /* We need to check both for a crtc link (meaning that the
11882 * encoder is active and trying to read from a pipe) and the
11883 * pipe itself being active. */
11884 bool has_active_crtc = encoder->base.crtc &&
11885 to_intel_crtc(encoder->base.crtc)->active;
11886
11887 if (encoder->connectors_active && !has_active_crtc) {
11888 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11889 encoder->base.base.id,
11890 drm_get_encoder_name(&encoder->base));
11891
11892 /* Connector is active, but has no active pipe. This is
11893 * fallout from our resume register restoring. Disable
11894 * the encoder manually again. */
11895 if (encoder->base.crtc) {
11896 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11897 encoder->base.base.id,
11898 drm_get_encoder_name(&encoder->base));
11899 encoder->disable(encoder);
11900 }
11901
11902 /* Inconsistent output/port/pipe state happens presumably due to
11903 * a bug in one of the get_hw_state functions. Or someplace else
11904 * in our code, like the register restore mess on resume. Clamp
11905 * things to off as a safer default. */
11906 list_for_each_entry(connector,
11907 &dev->mode_config.connector_list,
11908 base.head) {
11909 if (connector->encoder != encoder)
11910 continue;
11911
11912 intel_connector_break_all_links(connector);
11913 }
11914 }
11915 /* Enabled encoders without active connectors will be fixed in
11916 * the crtc fixup. */
11917}
11918
Imre Deak04098752014-02-18 00:02:16 +020011919void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011920{
11921 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020011922 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011923
Imre Deak04098752014-02-18 00:02:16 +020011924 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11925 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11926 i915_disable_vga(dev);
11927 }
11928}
11929
11930void i915_redisable_vga(struct drm_device *dev)
11931{
11932 struct drm_i915_private *dev_priv = dev->dev_private;
11933
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030011934 /* This function can be called both from intel_modeset_setup_hw_state or
11935 * at a very early point in our resume sequence, where the power well
11936 * structures are not yet restored. Since this function is at a very
11937 * paranoid "someone might have enabled VGA while we were not looking"
11938 * level, just check if the power well is enabled instead of trying to
11939 * follow the "don't touch the power well if we don't need it" policy
11940 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020011941 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030011942 return;
11943
Imre Deak04098752014-02-18 00:02:16 +020011944 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011945}
11946
Ville Syrjälä98ec7732014-04-30 17:43:01 +030011947static bool primary_get_hw_state(struct intel_crtc *crtc)
11948{
11949 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11950
11951 if (!crtc->active)
11952 return false;
11953
11954 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11955}
11956
Daniel Vetter30e984d2013-06-05 13:34:17 +020011957static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020011958{
11959 struct drm_i915_private *dev_priv = dev->dev_private;
11960 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020011961 struct intel_crtc *crtc;
11962 struct intel_encoder *encoder;
11963 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020011964 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020011965
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011966 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010011967 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020011968
Daniel Vetter99535992014-04-13 12:00:33 +020011969 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11970
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011971 crtc->active = dev_priv->display.get_pipe_config(crtc,
11972 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020011973
11974 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030011975 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020011976
11977 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11978 crtc->base.base.id,
11979 crtc->active ? "enabled" : "disabled");
11980 }
11981
Daniel Vetter53589012013-06-05 13:34:16 +020011982 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011983 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -030011984 intel_ddi_setup_hw_pll_state(dev);
11985
Daniel Vetter53589012013-06-05 13:34:16 +020011986 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11987 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11988
11989 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11990 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011991 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020011992 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11993 pll->active++;
11994 }
11995 pll->refcount = pll->active;
11996
Daniel Vetter35c95372013-07-17 06:55:04 +020011997 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11998 pll->name, pll->refcount, pll->on);
Daniel Vetter53589012013-06-05 13:34:16 +020011999 }
12000
Daniel Vetter24929352012-07-02 20:28:59 +020012001 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12002 base.head) {
12003 pipe = 0;
12004
12005 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070012006 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12007 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010012008 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012009 } else {
12010 encoder->base.crtc = NULL;
12011 }
12012
12013 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012014 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020012015 encoder->base.base.id,
12016 drm_get_encoder_name(&encoder->base),
12017 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012018 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020012019 }
12020
12021 list_for_each_entry(connector, &dev->mode_config.connector_list,
12022 base.head) {
12023 if (connector->get_hw_state(connector)) {
12024 connector->base.dpms = DRM_MODE_DPMS_ON;
12025 connector->encoder->connectors_active = true;
12026 connector->base.encoder = &connector->encoder->base;
12027 } else {
12028 connector->base.dpms = DRM_MODE_DPMS_OFF;
12029 connector->base.encoder = NULL;
12030 }
12031 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12032 connector->base.base.id,
12033 drm_get_connector_name(&connector->base),
12034 connector->base.encoder ? "enabled" : "disabled");
12035 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020012036}
12037
12038/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12039 * and i915 state tracking structures. */
12040void intel_modeset_setup_hw_state(struct drm_device *dev,
12041 bool force_restore)
12042{
12043 struct drm_i915_private *dev_priv = dev->dev_private;
12044 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012045 struct intel_crtc *crtc;
12046 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020012047 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012048
12049 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020012050
Jesse Barnesbabea612013-06-26 18:57:38 +030012051 /*
12052 * Now that we have the config, copy it to each CRTC struct
12053 * Note that this could go away if we move to using crtc_config
12054 * checking everywhere.
12055 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012056 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020012057 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080012058 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030012059 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12060 crtc->base.base.id);
12061 drm_mode_debug_printmodeline(&crtc->base.mode);
12062 }
12063 }
12064
Daniel Vetter24929352012-07-02 20:28:59 +020012065 /* HW state is read out, now we need to sanitize this mess. */
12066 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12067 base.head) {
12068 intel_sanitize_encoder(encoder);
12069 }
12070
12071 for_each_pipe(pipe) {
12072 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12073 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012074 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020012075 }
Daniel Vetter9a935852012-07-05 22:34:27 +020012076
Daniel Vetter35c95372013-07-17 06:55:04 +020012077 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12078 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12079
12080 if (!pll->on || pll->active)
12081 continue;
12082
12083 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12084
12085 pll->disable(dev_priv, pll);
12086 pll->on = false;
12087 }
12088
Ville Syrjälä96f90c52013-12-05 15:51:38 +020012089 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030012090 ilk_wm_get_hw_state(dev);
12091
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012092 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030012093 i915_redisable_vga(dev);
12094
Daniel Vetterf30da182013-04-11 20:22:50 +020012095 /*
12096 * We need to use raw interfaces for restoring state to avoid
12097 * checking (bogus) intermediate states.
12098 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012099 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070012100 struct drm_crtc *crtc =
12101 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020012102
12103 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070012104 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012105 }
12106 } else {
12107 intel_modeset_update_staged_output_state(dev);
12108 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012109
12110 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010012111}
12112
12113void intel_modeset_gem_init(struct drm_device *dev)
12114{
Jesse Barnes484b41d2014-03-07 08:57:55 -080012115 struct drm_crtc *c;
12116 struct intel_framebuffer *fb;
12117
Imre Deakae484342014-03-31 15:10:44 +030012118 mutex_lock(&dev->struct_mutex);
12119 intel_init_gt_powersave(dev);
12120 mutex_unlock(&dev->struct_mutex);
12121
Chris Wilson1833b132012-05-09 11:56:28 +010012122 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020012123
12124 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080012125
12126 /*
12127 * Make sure any fbs we allocated at startup are properly
12128 * pinned & fenced. When we do the allocation it's too early
12129 * for this.
12130 */
12131 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010012132 for_each_crtc(dev, c) {
Dave Airlie66e514c2014-04-03 07:51:54 +100012133 if (!c->primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -080012134 continue;
12135
Dave Airlie66e514c2014-04-03 07:51:54 +100012136 fb = to_intel_framebuffer(c->primary->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -080012137 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12138 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12139 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100012140 drm_framebuffer_unreference(c->primary->fb);
12141 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080012142 }
12143 }
12144 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012145}
12146
Imre Deak4932e2c2014-02-11 17:12:48 +020012147void intel_connector_unregister(struct intel_connector *intel_connector)
12148{
12149 struct drm_connector *connector = &intel_connector->base;
12150
12151 intel_panel_destroy_backlight(connector);
12152 drm_sysfs_connector_remove(connector);
12153}
12154
Jesse Barnes79e53942008-11-07 14:24:08 -080012155void intel_modeset_cleanup(struct drm_device *dev)
12156{
Jesse Barnes652c3932009-08-17 13:31:43 -070012157 struct drm_i915_private *dev_priv = dev->dev_private;
12158 struct drm_crtc *crtc;
Paulo Zanonid9255d52013-09-26 20:05:59 -030012159 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070012160
Daniel Vetterfd0c0642013-04-24 11:13:35 +020012161 /*
12162 * Interrupts and polling as the first thing to avoid creating havoc.
12163 * Too much stuff here (turning of rps, connectors, ...) would
12164 * experience fancy races otherwise.
12165 */
12166 drm_irq_uninstall(dev);
12167 cancel_work_sync(&dev_priv->hotplug_work);
12168 /*
12169 * Due to the hpd irq storm handling the hotplug work can re-arm the
12170 * poll handlers. Hence disable polling after hpd handling is shut down.
12171 */
Keith Packardf87ea762010-10-03 19:36:26 -070012172 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020012173
Jesse Barnes652c3932009-08-17 13:31:43 -070012174 mutex_lock(&dev->struct_mutex);
12175
Jesse Barnes723bfd72010-10-07 16:01:13 -070012176 intel_unregister_dsm_handler();
12177
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010012178 for_each_crtc(dev, crtc) {
Jesse Barnes652c3932009-08-17 13:31:43 -070012179 /* Skip inactive CRTCs */
Matt Roperf4510a22014-04-01 15:22:40 -070012180 if (!crtc->primary->fb)
Jesse Barnes652c3932009-08-17 13:31:43 -070012181 continue;
12182
Daniel Vetter3dec0092010-08-20 21:40:52 +020012183 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070012184 }
12185
Chris Wilson973d04f2011-07-08 12:22:37 +010012186 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012187
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012188 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000012189
Daniel Vetter930ebb42012-06-29 23:32:16 +020012190 ironlake_teardown_rc6(dev);
12191
Kristian Høgsberg69341a52009-11-11 12:19:17 -050012192 mutex_unlock(&dev->struct_mutex);
12193
Chris Wilson1630fe72011-07-08 12:22:42 +010012194 /* flush any delayed tasks or pending work */
12195 flush_scheduled_work();
12196
Jani Nikuladb31af1d2013-11-08 16:48:53 +020012197 /* destroy the backlight and sysfs files before encoders/connectors */
12198 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020012199 struct intel_connector *intel_connector;
12200
12201 intel_connector = to_intel_connector(connector);
12202 intel_connector->unregister(intel_connector);
Jani Nikuladb31af1d2013-11-08 16:48:53 +020012203 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030012204
Jesse Barnes79e53942008-11-07 14:24:08 -080012205 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010012206
12207 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030012208
12209 mutex_lock(&dev->struct_mutex);
12210 intel_cleanup_gt_powersave(dev);
12211 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012212}
12213
Dave Airlie28d52042009-09-21 14:33:58 +100012214/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080012215 * Return which encoder is currently attached for connector.
12216 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010012217struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080012218{
Chris Wilsondf0e9242010-09-09 16:20:55 +010012219 return &intel_attached_encoder(connector)->base;
12220}
Jesse Barnes79e53942008-11-07 14:24:08 -080012221
Chris Wilsondf0e9242010-09-09 16:20:55 +010012222void intel_connector_attach_encoder(struct intel_connector *connector,
12223 struct intel_encoder *encoder)
12224{
12225 connector->encoder = encoder;
12226 drm_mode_connector_attach_encoder(&connector->base,
12227 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080012228}
Dave Airlie28d52042009-09-21 14:33:58 +100012229
12230/*
12231 * set vga decode state - true == enable VGA decode
12232 */
12233int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12234{
12235 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000012236 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100012237 u16 gmch_ctrl;
12238
Chris Wilson75fa0412014-02-07 18:37:02 -020012239 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12240 DRM_ERROR("failed to read control word\n");
12241 return -EIO;
12242 }
12243
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020012244 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12245 return 0;
12246
Dave Airlie28d52042009-09-21 14:33:58 +100012247 if (state)
12248 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12249 else
12250 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020012251
12252 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12253 DRM_ERROR("failed to write control word\n");
12254 return -EIO;
12255 }
12256
Dave Airlie28d52042009-09-21 14:33:58 +100012257 return 0;
12258}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012259
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012260struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012261
12262 u32 power_well_driver;
12263
Chris Wilson63b66e52013-08-08 15:12:06 +020012264 int num_transcoders;
12265
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012266 struct intel_cursor_error_state {
12267 u32 control;
12268 u32 position;
12269 u32 base;
12270 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010012271 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012272
12273 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020012274 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012275 u32 source;
Imre Deakf301b1e12014-04-18 15:55:04 +030012276 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010012277 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012278
12279 struct intel_plane_error_state {
12280 u32 control;
12281 u32 stride;
12282 u32 size;
12283 u32 pos;
12284 u32 addr;
12285 u32 surface;
12286 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010012287 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020012288
12289 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020012290 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020012291 enum transcoder cpu_transcoder;
12292
12293 u32 conf;
12294
12295 u32 htotal;
12296 u32 hblank;
12297 u32 hsync;
12298 u32 vtotal;
12299 u32 vblank;
12300 u32 vsync;
12301 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012302};
12303
12304struct intel_display_error_state *
12305intel_display_capture_error_state(struct drm_device *dev)
12306{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012307 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012308 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020012309 int transcoders[] = {
12310 TRANSCODER_A,
12311 TRANSCODER_B,
12312 TRANSCODER_C,
12313 TRANSCODER_EDP,
12314 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012315 int i;
12316
Chris Wilson63b66e52013-08-08 15:12:06 +020012317 if (INTEL_INFO(dev)->num_pipes == 0)
12318 return NULL;
12319
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012320 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012321 if (error == NULL)
12322 return NULL;
12323
Imre Deak190be112013-11-25 17:15:31 +020012324 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012325 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12326
Damien Lespiau52331302012-08-15 19:23:25 +010012327 for_each_pipe(i) {
Imre Deakddf9c532013-11-27 22:02:02 +020012328 error->pipe[i].power_domain_on =
Imre Deakda7e29b2014-02-18 00:02:02 +020012329 intel_display_power_enabled_sw(dev_priv,
12330 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020012331 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012332 continue;
12333
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030012334 error->cursor[i].control = I915_READ(CURCNTR(i));
12335 error->cursor[i].position = I915_READ(CURPOS(i));
12336 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012337
12338 error->plane[i].control = I915_READ(DSPCNTR(i));
12339 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012340 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030012341 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012342 error->plane[i].pos = I915_READ(DSPPOS(i));
12343 }
Paulo Zanonica291362013-03-06 20:03:14 -030012344 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12345 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012346 if (INTEL_INFO(dev)->gen >= 4) {
12347 error->plane[i].surface = I915_READ(DSPSURF(i));
12348 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12349 }
12350
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012351 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e12014-04-18 15:55:04 +030012352
12353 if (!HAS_PCH_SPLIT(dev))
12354 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020012355 }
12356
12357 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12358 if (HAS_DDI(dev_priv->dev))
12359 error->num_transcoders++; /* Account for eDP. */
12360
12361 for (i = 0; i < error->num_transcoders; i++) {
12362 enum transcoder cpu_transcoder = transcoders[i];
12363
Imre Deakddf9c532013-11-27 22:02:02 +020012364 error->transcoder[i].power_domain_on =
Imre Deakda7e29b2014-02-18 00:02:02 +020012365 intel_display_power_enabled_sw(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020012366 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020012367 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012368 continue;
12369
Chris Wilson63b66e52013-08-08 15:12:06 +020012370 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12371
12372 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12373 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12374 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12375 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12376 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12377 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12378 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012379 }
12380
12381 return error;
12382}
12383
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012384#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12385
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012386void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012387intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012388 struct drm_device *dev,
12389 struct intel_display_error_state *error)
12390{
12391 int i;
12392
Chris Wilson63b66e52013-08-08 15:12:06 +020012393 if (!error)
12394 return;
12395
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012396 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020012397 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012398 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012399 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010012400 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012401 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020012402 err_printf(m, " Power: %s\n",
12403 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012404 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e12014-04-18 15:55:04 +030012405 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012406
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012407 err_printf(m, "Plane [%d]:\n", i);
12408 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12409 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012410 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012411 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12412 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012413 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030012414 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012415 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012416 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012417 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12418 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012419 }
12420
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012421 err_printf(m, "Cursor [%d]:\n", i);
12422 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12423 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12424 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012425 }
Chris Wilson63b66e52013-08-08 15:12:06 +020012426
12427 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010012428 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020012429 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020012430 err_printf(m, " Power: %s\n",
12431 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020012432 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12433 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12434 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12435 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12436 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12437 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12438 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12439 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012440}