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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chon Ming Leeef9348c2014-04-09 13:28:18 +030076#define DIV_ROUND_CLOSEST_ULL(ll, d) \
Matt Roper465c1202014-05-29 08:06:54 -070077({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
Chon Ming Leeef9348c2014-04-09 13:28:18 +030078
Daniel Vettercc365132014-06-18 13:59:13 +020079static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +010081static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080082
Jesse Barnesf1f644d2013-06-27 00:39:25 +030083static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030085static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030087
Damien Lespiaue7457a92013-08-08 22:28:59 +010088static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080090static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020094static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020096static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070097 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020099static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +0200100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +0200102static void vlv_prepare_pll(struct intel_crtc *crtc);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +0300103static void chv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100104
Dave Airlie0e32b392014-05-02 14:02:48 +1000105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106{
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111}
112
Jesse Barnes79e53942008-11-07 14:24:08 -0800113typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400114 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800115} intel_range_t;
116
117typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400118 int dot_limit;
119 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800120} intel_p2_t;
121
Ma Lingd4906092009-03-18 20:13:27 +0800122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800126};
Jesse Barnes79e53942008-11-07 14:24:08 -0800127
Daniel Vetterd2acd212012-10-20 20:57:43 +0200128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
Chris Wilson021357a2010-09-07 20:54:59 +0100138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
Chris Wilson8b99e682010-10-13 09:59:17 +0100141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100146}
147
Daniel Vetter5d536e22013-07-06 12:52:06 +0200148static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400149 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200150 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200151 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700159};
160
Daniel Vetter5d536e22013-07-06 12:52:06 +0200161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200163 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200164 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
Keith Packarde4b36692009-06-05 19:22:17 -0700174static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200176 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200177 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
Eric Anholt273e27c2011-03-30 13:01:10 -0700186
Keith Packarde4b36692009-06-05 19:22:17 -0700187static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700211};
212
Eric Anholt273e27c2011-03-30 13:01:10 -0700213
Keith Packarde4b36692009-06-05 19:22:17 -0700214static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800226 },
Keith Packarde4b36692009-06-05 19:22:17 -0700227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800253 },
Keith Packarde4b36692009-06-05 19:22:17 -0700254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800267 },
Keith Packarde4b36692009-06-05 19:22:17 -0700268};
269
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500270static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700276 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700283};
284
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500285static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700296};
297
Eric Anholt273e27c2011-03-30 13:01:10 -0700298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800303static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700314};
315
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800316static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800340};
341
Eric Anholt273e27c2011-03-30 13:01:10 -0700342/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400351 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800367};
368
Ville Syrjälädc730512013-09-24 21:26:30 +0300369static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200377 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700378 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300381 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700383};
384
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300401static void vlv_clock(int refclk, intel_clock_t *clock)
402{
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300409}
410
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300411/**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415{
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424}
425
Chris Wilson1b894b52010-12-14 20:04:54 +0000426static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800428{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800429 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800430 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100433 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000434 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000439 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200444 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800445 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800446
447 return limit;
448}
449
Ma Ling044c7c42009-03-18 20:13:23 +0800450static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451{
452 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100456 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700457 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800458 else
Keith Packarde4b36692009-06-05 19:22:17 -0700459 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700462 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700464 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800465 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700466 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800467
468 return limit;
469}
470
Chris Wilson1b894b52010-12-14 20:04:54 +0000471static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800472{
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
Eric Anholtbad720f2009-10-22 16:11:14 -0700476 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000477 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800478 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800479 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500480 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500482 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800483 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500484 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700487 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300488 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700496 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700498 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200499 else
500 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 }
502 return limit;
503}
504
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500505/* m1 is reserved as 0 in Pineview, n is a ring counter */
506static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800507{
Shaohua Li21778322009-02-23 15:19:16 +0800508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800514}
515
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200516static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517{
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519}
520
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200521static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800522{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200523 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800524 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800529}
530
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300531static void chv_clock(int refclk, intel_clock_t *clock)
532{
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540}
541
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
Chris Wilson1b894b52010-12-14 20:04:54 +0000548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800551{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400555 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400557 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400559 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
Jesse Barnes79e53942008-11-07 14:24:08 -0800572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400573 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400578 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800579
580 return true;
581}
582
Ma Lingd4906092009-03-18 20:13:27 +0800583static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200584i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800587{
588 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800589 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800590 int err = target;
591
Daniel Vettera210b022012-11-26 17:22:08 +0100592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800593 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100598 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
Akshay Joshi0206e352011-08-16 15:34:10 -0400609 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800610
Zhao Yakui42158662009-11-20 11:24:18 +0800611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200615 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800621 int this_err;
622
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200623 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800626 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642}
643
Ma Lingd4906092009-03-18 20:13:27 +0800644static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200645pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200648{
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701}
702
Ma Lingd4906092009-03-18 20:13:27 +0800703static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200704g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800707{
708 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800709 intel_clock_t clock;
710 int max_n;
711 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100717 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200730 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200732 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200741 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800744 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000745
746 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800757 return found;
758}
Ma Lingd4906092009-03-18 20:13:27 +0800759
Zhenyu Wang2c072452009-06-05 15:38:42 +0800760static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200761vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700764{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300765 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300766 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300767 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300770 bool found = false;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700771
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700775
776 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300781 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700782 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300784 unsigned int ppm, diff;
785
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300788
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300789 vlv_clock(refclk, &clock);
790
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300793 continue;
794
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300799 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300800 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300801 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300802 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300803
Ville Syrjäläc6861222013-09-24 21:26:21 +0300804 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300805 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300806 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300807 found = true;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700808 }
809 }
810 }
811 }
812 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700813
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300814 return found;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700815}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700816
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300817static bool
818chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821{
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867}
868
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300869bool intel_crtc_active(struct drm_crtc *crtc)
870{
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100876 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300877 * as Haswell has gained clock readout/fastboot support.
878 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000879 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300880 * properly reconstruct framebuffers.
881 */
Matt Roperf4510a22014-04-01 15:22:40 -0700882 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100883 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300884}
885
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200886enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888{
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
Daniel Vetter3b117c82013-04-17 20:15:07 +0200892 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200893}
894
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200895static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300896{
897 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Damien Lespiau31e4b892014-08-18 13:51:00 +0100903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
Paulo Zanonia928d532012-05-04 17:18:15 -0300905}
906
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700907/**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800916{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700917 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800918 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700919
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300922 return;
923 }
924
Chris Wilson300387c2010-09-05 20:25:43 +0100925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700941 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
Damien Lespiau31e4b892014-08-18 13:51:00 +0100945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700947}
948
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300949static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966}
967
Keith Packardab7ad7f2010-10-03 00:33:06 -0700968/*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700970 * @dev: drm device
971 * @pipe: pipe to wait for
972 *
973 * After disabling a pipe, we can't wait for vblank in the usual way,
974 * spinning on the vblank interrupt status bit, since we won't actually
975 * see an interrupt when the pipe is disabled.
976 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700977 * On Gen4 and above:
978 * wait for the pipe register state bit to turn off
979 *
980 * Otherwise:
981 * wait for the display line value to settle (it usually
982 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100983 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700984 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100985void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700986{
987 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200988 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
989 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700990
Keith Packardab7ad7f2010-10-03 00:33:06 -0700991 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200992 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700993
Keith Packardab7ad7f2010-10-03 00:33:06 -0700994 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200997 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700998 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700999 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001001 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001002 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001003}
1004
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001005/*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014{
1015 u32 bit;
1016
Damien Lespiauc36346e2012-12-13 16:09:03 +00001017 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +02001018 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
Robin Schroereba905b2014-05-18 02:24:50 +02001032 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048}
1049
Jesse Barnesb24e7172011-01-04 15:09:30 -08001050static const char *state_string(bool enabled)
1051{
1052 return enabled ? "on" : "off";
1053}
1054
1055/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001056void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001058{
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001070
Jani Nikula23538ef2013-08-27 15:12:22 +03001071/* XXX: the dsi pll is shared between MIPI DSI ports */
1072static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073{
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085}
1086#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
Daniel Vetter55607e82013-06-16 21:42:39 +02001089struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001090intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001091{
Daniel Vettere2b78262013-06-07 23:10:03 +02001092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
Daniel Vettera43f6e02013-06-07 23:10:32 +02001094 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001095 return NULL;
1096
Daniel Vettera43f6e02013-06-07 23:10:32 +02001097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001098}
1099
Jesse Barnesb24e7172011-01-04 15:09:30 -08001100/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001101void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001104{
Jesse Barnes040484a2011-01-03 12:14:26 -08001105 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001106 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001107
Chris Wilson92b27b02012-05-20 18:10:50 +01001108 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001109 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001110 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001111
Daniel Vetter53589012013-06-05 13:34:16 +02001112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001113 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001116}
Jesse Barnes040484a2011-01-03 12:14:26 -08001117
1118static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120{
1121 int reg;
1122 u32 val;
1123 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001126
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001130 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140}
1141#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146{
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157}
1158#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163{
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001169 return;
1170
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001172 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001173 return;
1174
Jesse Barnes040484a2011-01-03 12:14:26 -08001175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178}
1179
Daniel Vetter55607e82013-06-16 21:42:39 +02001180void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001182{
1183 int reg;
1184 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001185 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001193}
1194
Jesse Barnesea0760c2011-01-04 15:09:32 -08001195static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197{
Jani Nikulabedd4db2014-08-22 15:04:13 +03001198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001202 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001203
Jani Nikulabedd4db2014-08-22 15:04:13 +03001204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
Jesse Barnesea0760c2011-01-04 15:09:32 -08001210 pp_reg = PCH_PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001221 } else {
1222 pp_reg = PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001230 locked = false;
1231
Jesse Barnesea0760c2011-01-04 15:09:32 -08001232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001234 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001235}
1236
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001237static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239{
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
Paulo Zanonid9d82082014-02-27 16:30:56 -03001243 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001245 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251}
1252#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001255void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001257{
1258 int reg;
1259 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001260 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001263
Daniel Vetter8e636782012-01-22 01:36:48 +01001264 /* if we need the pipe A quirk it must be always on */
1265 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1266 state = true;
1267
Imre Deakda7e29b2014-02-18 00:02:02 +02001268 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001269 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001270 cur_state = false;
1271 } else {
1272 reg = PIPECONF(cpu_transcoder);
1273 val = I915_READ(reg);
1274 cur_state = !!(val & PIPECONF_ENABLE);
1275 }
1276
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001277 WARN(cur_state != state,
1278 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001279 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280}
1281
Chris Wilson931872f2012-01-16 23:01:13 +00001282static void assert_plane(struct drm_i915_private *dev_priv,
1283 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001284{
1285 int reg;
1286 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001287 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001288
1289 reg = DSPCNTR(plane);
1290 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001291 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1292 WARN(cur_state != state,
1293 "plane %c assertion failure (expected %s, current %s)\n",
1294 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001295}
1296
Chris Wilson931872f2012-01-16 23:01:13 +00001297#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1298#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1299
Jesse Barnesb24e7172011-01-04 15:09:30 -08001300static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1301 enum pipe pipe)
1302{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001303 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001304 int reg, i;
1305 u32 val;
1306 int cur_pipe;
1307
Ville Syrjälä653e1022013-06-04 13:49:05 +03001308 /* Primary planes are fixed to pipes on gen4+ */
1309 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001310 reg = DSPCNTR(pipe);
1311 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001312 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001313 "plane %c assertion failure, should be disabled but not\n",
1314 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001315 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001316 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001317
Jesse Barnesb24e7172011-01-04 15:09:30 -08001318 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001319 for_each_pipe(dev_priv, i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001320 reg = DSPCNTR(i);
1321 val = I915_READ(reg);
1322 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1323 DISPPLANE_SEL_PIPE_SHIFT;
1324 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001325 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001327 }
1328}
1329
Jesse Barnes19332d72013-03-28 09:55:38 -07001330static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001333 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001334 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001335 u32 val;
1336
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001337 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001338 for_each_sprite(pipe, sprite) {
1339 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001340 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001341 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001343 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001344 }
1345 } else if (INTEL_INFO(dev)->gen >= 7) {
1346 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001347 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001348 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001349 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001350 plane_name(pipe), pipe_name(pipe));
1351 } else if (INTEL_INFO(dev)->gen >= 5) {
1352 reg = DVSCNTR(pipe);
1353 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001354 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001355 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001357 }
1358}
1359
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001360static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001361{
1362 u32 val;
1363 bool enabled;
1364
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001365 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001366
Jesse Barnes92f25842011-01-04 15:09:34 -08001367 val = I915_READ(PCH_DREF_CONTROL);
1368 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1369 DREF_SUPERSPREAD_SOURCE_MASK));
1370 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1371}
1372
Daniel Vetterab9412b2013-05-03 11:49:46 +02001373static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001375{
1376 int reg;
1377 u32 val;
1378 bool enabled;
1379
Daniel Vetterab9412b2013-05-03 11:49:46 +02001380 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001381 val = I915_READ(reg);
1382 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001383 WARN(enabled,
1384 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1385 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001386}
1387
Keith Packard4e634382011-08-06 10:39:45 -07001388static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1389 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001390{
1391 if ((val & DP_PORT_EN) == 0)
1392 return false;
1393
1394 if (HAS_PCH_CPT(dev_priv->dev)) {
1395 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1396 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1397 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1398 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1401 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001402 } else {
1403 if ((val & DP_PIPE_MASK) != (pipe << 30))
1404 return false;
1405 }
1406 return true;
1407}
1408
Keith Packard1519b992011-08-06 10:35:34 -07001409static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001412 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001416 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001417 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001418 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1419 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1420 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001421 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001422 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001423 return false;
1424 }
1425 return true;
1426}
1427
1428static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe, u32 val)
1430{
1431 if ((val & LVDS_PORT_EN) == 0)
1432 return false;
1433
1434 if (HAS_PCH_CPT(dev_priv->dev)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1439 return false;
1440 }
1441 return true;
1442}
1443
1444static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, u32 val)
1446{
1447 if ((val & ADPA_DAC_ENABLE) == 0)
1448 return false;
1449 if (HAS_PCH_CPT(dev_priv->dev)) {
1450 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1451 return false;
1452 } else {
1453 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1454 return false;
1455 }
1456 return true;
1457}
1458
Jesse Barnes291906f2011-02-02 12:28:03 -08001459static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001460 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001461{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001462 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001463 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001464 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001465 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001466
Daniel Vetter75c5da22012-09-10 21:58:29 +02001467 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1468 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001469 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001470}
1471
1472static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, int reg)
1474{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001475 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001476 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001477 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001478 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001479
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001480 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001481 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001482 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001483}
1484
1485static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487{
1488 int reg;
1489 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001490
Keith Packardf0575e92011-07-25 22:12:43 -07001491 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1492 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1493 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001494
1495 reg = PCH_ADPA;
1496 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001497 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001498 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001499 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001500
1501 reg = PCH_LVDS;
1502 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001503 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001504 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001505 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001506
Paulo Zanonie2debe92013-02-18 19:00:27 -03001507 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1508 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1509 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001510}
1511
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001512static void intel_init_dpio(struct drm_device *dev)
1513{
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (!IS_VALLEYVIEW(dev))
1517 return;
1518
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001519 /*
1520 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1521 * CHV x1 PHY (DP/HDMI D)
1522 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1523 */
1524 if (IS_CHERRYVIEW(dev)) {
1525 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1527 } else {
1528 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1529 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001530}
1531
Daniel Vetter426115c2013-07-11 22:13:42 +02001532static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001533{
Daniel Vetter426115c2013-07-11 22:13:42 +02001534 struct drm_device *dev = crtc->base.dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 int reg = DPLL(crtc->pipe);
1537 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001538
Daniel Vetter426115c2013-07-11 22:13:42 +02001539 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001540
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001541 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001542 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1543
1544 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001545 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001546 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001547
Daniel Vetter426115c2013-07-11 22:13:42 +02001548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150);
1551
1552 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1553 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1554
1555 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1556 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001557
1558 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001559 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001560 POSTING_READ(reg);
1561 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001562 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001563 POSTING_READ(reg);
1564 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001565 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001566 POSTING_READ(reg);
1567 udelay(150); /* wait for warmup */
1568}
1569
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001570static void chv_enable_pll(struct intel_crtc *crtc)
1571{
1572 struct drm_device *dev = crtc->base.dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 int pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001576 u32 tmp;
1577
1578 assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1581
1582 mutex_lock(&dev_priv->dpio_lock);
1583
1584 /* Enable back the 10bit clock to display controller */
1585 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1586 tmp |= DPIO_DCLKP_EN;
1587 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1588
1589 /*
1590 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1591 */
1592 udelay(1);
1593
1594 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001595 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001596
1597 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001598 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001599 DRM_ERROR("PLL %d failed to lock\n", pipe);
1600
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001601 /* not sure when this should be written */
1602 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1603 POSTING_READ(DPLL_MD(pipe));
1604
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001605 mutex_unlock(&dev_priv->dpio_lock);
1606}
1607
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001608static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001609{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001610 struct drm_device *dev = crtc->base.dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int reg = DPLL(crtc->pipe);
1613 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001614
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001615 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001616
1617 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001618 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001619
1620 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001621 if (IS_MOBILE(dev) && !IS_I830(dev))
1622 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001623
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001624 I915_WRITE(reg, dpll);
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001641
1642 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001643 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001646 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001649 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652}
1653
1654/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001655 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001663static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001664{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001665 /* Don't disable pipe A or pipe A PLLs if needed */
1666 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1667 return;
1668
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv, pipe);
1671
Daniel Vetter50b44a42013-06-05 13:34:33 +02001672 I915_WRITE(DPLL(pipe), 0);
1673 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001674}
1675
Jesse Barnesf6071162013-10-01 10:41:38 -07001676static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1677{
1678 u32 val = 0;
1679
1680 /* Make sure the pipe isn't still relying on us */
1681 assert_pipe_disabled(dev_priv, pipe);
1682
Imre Deake5cbfbf2014-01-09 17:08:16 +02001683 /*
1684 * Leave integrated clock source and reference clock enabled for pipe B.
1685 * The latter is needed for VGA hotplug / manual detection.
1686 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001687 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001688 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001689 I915_WRITE(DPLL(pipe), val);
1690 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001691
1692}
1693
1694static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001696 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001697 u32 val;
1698
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001701
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001702 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001703 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001704 if (pipe != PIPE_A)
1705 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1706 I915_WRITE(DPLL(pipe), val);
1707 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001708
1709 mutex_lock(&dev_priv->dpio_lock);
1710
1711 /* Disable 10bit clock to display controller */
1712 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1713 val &= ~DPIO_DCLKP_EN;
1714 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1715
Ville Syrjälä61407f62014-05-27 16:32:55 +03001716 /* disable left/right clock distribution */
1717 if (pipe != PIPE_B) {
1718 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1719 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1720 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1721 } else {
1722 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1723 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1725 }
1726
Ville Syrjäläd7520482014-04-09 13:28:59 +03001727 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001728}
1729
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001730void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1731 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001732{
1733 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001734 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001735
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001736 switch (dport->port) {
1737 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001738 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001739 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001740 break;
1741 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001742 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001743 dpll_reg = DPLL(0);
1744 break;
1745 case PORT_D:
1746 port_mask = DPLL_PORTD_READY_MASK;
1747 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001748 break;
1749 default:
1750 BUG();
1751 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001752
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001753 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001754 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001755 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001756}
1757
Daniel Vetterb14b1052014-04-24 23:55:13 +02001758static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1759{
1760 struct drm_device *dev = crtc->base.dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1763
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001764 if (WARN_ON(pll == NULL))
1765 return;
1766
Daniel Vetterb14b1052014-04-24 23:55:13 +02001767 WARN_ON(!pll->refcount);
1768 if (pll->active == 0) {
1769 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1770 WARN_ON(pll->on);
1771 assert_shared_dpll_disabled(dev_priv, pll);
1772
1773 pll->mode_set(dev_priv, pll);
1774 }
1775}
1776
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001777/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001778 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001779 * @dev_priv: i915 private structure
1780 * @pipe: pipe PLL to enable
1781 *
1782 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1783 * drives the transcoder clock.
1784 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001785static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001786{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001787 struct drm_device *dev = crtc->base.dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001789 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001790
Daniel Vetter87a875b2013-06-05 13:34:19 +02001791 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001792 return;
1793
1794 if (WARN_ON(pll->refcount == 0))
1795 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001796
Damien Lespiau74dd6922014-07-29 18:06:17 +01001797 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001798 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001799 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001800
Daniel Vettercdbd2312013-06-05 13:34:03 +02001801 if (pll->active++) {
1802 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001803 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001804 return;
1805 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001806 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001807
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001808 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1809
Daniel Vetter46edb022013-06-05 13:34:12 +02001810 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001811 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001812 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001813}
1814
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001815static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001816{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001817 struct drm_device *dev = crtc->base.dev;
1818 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001819 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001820
Jesse Barnes92f25842011-01-04 15:09:34 -08001821 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001822 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001823 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001824 return;
1825
Chris Wilson48da64a2012-05-13 20:16:12 +01001826 if (WARN_ON(pll->refcount == 0))
1827 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001828
Daniel Vetter46edb022013-06-05 13:34:12 +02001829 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1830 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001831 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001832
Chris Wilson48da64a2012-05-13 20:16:12 +01001833 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001834 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001835 return;
1836 }
1837
Daniel Vettere9d69442013-06-05 13:34:15 +02001838 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001839 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001840 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001841 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001842
Daniel Vetter46edb022013-06-05 13:34:12 +02001843 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001844 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001845 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001846
1847 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001848}
1849
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001850static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1851 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001852{
Daniel Vetter23670b322012-11-01 09:15:30 +01001853 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001854 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001856 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001857
1858 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001859 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001860
1861 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001862 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001863 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001864
1865 /* FDI must be feeding us bits for PCH ports */
1866 assert_fdi_tx_enabled(dev_priv, pipe);
1867 assert_fdi_rx_enabled(dev_priv, pipe);
1868
Daniel Vetter23670b322012-11-01 09:15:30 +01001869 if (HAS_PCH_CPT(dev)) {
1870 /* Workaround: Set the timing override bit before enabling the
1871 * pch transcoder. */
1872 reg = TRANS_CHICKEN2(pipe);
1873 val = I915_READ(reg);
1874 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001876 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001877
Daniel Vetterab9412b2013-05-03 11:49:46 +02001878 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001879 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001880 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001881
1882 if (HAS_PCH_IBX(dev_priv->dev)) {
1883 /*
1884 * make the BPC in transcoder be consistent with
1885 * that in pipeconf reg.
1886 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001887 val &= ~PIPECONF_BPC_MASK;
1888 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001889 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001890
1891 val &= ~TRANS_INTERLACE_MASK;
1892 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001893 if (HAS_PCH_IBX(dev_priv->dev) &&
1894 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1895 val |= TRANS_LEGACY_INTERLACED_ILK;
1896 else
1897 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001898 else
1899 val |= TRANS_PROGRESSIVE;
1900
Jesse Barnes040484a2011-01-03 12:14:26 -08001901 I915_WRITE(reg, val | TRANS_ENABLE);
1902 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001903 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001904}
1905
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001906static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001907 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001908{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001909 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001910
1911 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001912 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001913
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001914 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001915 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001916 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001917
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001918 /* Workaround: set timing override bit. */
1919 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001920 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001921 I915_WRITE(_TRANSA_CHICKEN2, val);
1922
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001923 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001924 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001925
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001926 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1927 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001928 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001929 else
1930 val |= TRANS_PROGRESSIVE;
1931
Daniel Vetterab9412b2013-05-03 11:49:46 +02001932 I915_WRITE(LPT_TRANSCONF, val);
1933 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001934 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001935}
1936
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001937static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1938 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001939{
Daniel Vetter23670b322012-11-01 09:15:30 +01001940 struct drm_device *dev = dev_priv->dev;
1941 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001942
1943 /* FDI relies on the transcoder */
1944 assert_fdi_tx_disabled(dev_priv, pipe);
1945 assert_fdi_rx_disabled(dev_priv, pipe);
1946
Jesse Barnes291906f2011-02-02 12:28:03 -08001947 /* Ports must be off as well */
1948 assert_pch_ports_disabled(dev_priv, pipe);
1949
Daniel Vetterab9412b2013-05-03 11:49:46 +02001950 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001951 val = I915_READ(reg);
1952 val &= ~TRANS_ENABLE;
1953 I915_WRITE(reg, val);
1954 /* wait for PCH transcoder off, transcoder state */
1955 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001956 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001957
1958 if (!HAS_PCH_IBX(dev)) {
1959 /* Workaround: Clear the timing override chicken bit again. */
1960 reg = TRANS_CHICKEN2(pipe);
1961 val = I915_READ(reg);
1962 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1963 I915_WRITE(reg, val);
1964 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001965}
1966
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001967static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001968{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001969 u32 val;
1970
Daniel Vetterab9412b2013-05-03 11:49:46 +02001971 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001972 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001973 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001974 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001975 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001976 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001977
1978 /* Workaround: clear timing override bit. */
1979 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001981 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001982}
1983
1984/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001985 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001986 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001987 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001988 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001989 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001990 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001991static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001992{
Paulo Zanoni03722642014-01-17 13:51:09 -02001993 struct drm_device *dev = crtc->base.dev;
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001996 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1997 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001998 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001999 int reg;
2000 u32 val;
2001
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002002 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002003 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002004 assert_sprites_disabled(dev_priv, pipe);
2005
Paulo Zanoni681e5812012-12-06 11:12:38 -02002006 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002007 pch_transcoder = TRANSCODER_A;
2008 else
2009 pch_transcoder = pipe;
2010
Jesse Barnesb24e7172011-01-04 15:09:30 -08002011 /*
2012 * A pipe without a PLL won't actually be able to drive bits from
2013 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2014 * need the check.
2015 */
2016 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002017 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002018 assert_dsi_pll_enabled(dev_priv);
2019 else
2020 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002021 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002022 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002023 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002024 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002025 assert_fdi_tx_pll_enabled(dev_priv,
2026 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002027 }
2028 /* FIXME: assert CPU port conditions for SNB+ */
2029 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002030
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002031 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002032 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002033 if (val & PIPECONF_ENABLE) {
2034 WARN_ON(!(pipe == PIPE_A &&
2035 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002036 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002037 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002038
2039 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002040 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002041}
2042
2043/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002044 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045 * @dev_priv: i915 private structure
2046 * @pipe: pipe to disable
2047 *
2048 * Disable @pipe, making sure that various hardware specific requirements
2049 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2050 *
2051 * @pipe should be %PIPE_A or %PIPE_B.
2052 *
2053 * Will wait until the pipe has shut down before returning.
2054 */
2055static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
2057{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002060 int reg;
2061 u32 val;
2062
2063 /*
2064 * Make sure planes won't keep trying to pump pixels to us,
2065 * or we might hang the display.
2066 */
2067 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002068 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002069 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002070
2071 /* Don't disable pipe A or pipe A PLLs if needed */
2072 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2073 return;
2074
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002075 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002076 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002077 if ((val & PIPECONF_ENABLE) == 0)
2078 return;
2079
2080 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002081 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2082}
2083
Keith Packardd74362c2011-07-28 14:47:14 -07002084/*
2085 * Plane regs are double buffered, going from enabled->disabled needs a
2086 * trigger in order to latch. The display address reg provides this.
2087 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002088void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2089 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002090{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002091 struct drm_device *dev = dev_priv->dev;
2092 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002093
2094 I915_WRITE(reg, I915_READ(reg));
2095 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002096}
2097
Jesse Barnesb24e7172011-01-04 15:09:30 -08002098/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002099 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002100 * @plane: plane to be enabled
2101 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002102 *
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002103 * Enable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002104 */
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002105static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002107{
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002108 struct drm_device *dev = plane->dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002111
2112 /* If the pipe isn't enabled, we can't pump pixels and may hang */
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002113 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002114
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002115 if (intel_crtc->primary_enabled)
2116 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002117
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002118 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002119
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002120 dev_priv->display.update_primary_plane(crtc, plane->fb,
2121 crtc->x, crtc->y);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002122
2123 /*
2124 * BDW signals flip done immediately if the plane
2125 * is disabled, even if the plane enable is already
2126 * armed to occur at the next vblank :(
2127 */
2128 if (IS_BROADWELL(dev))
2129 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002130}
2131
Jesse Barnesb24e7172011-01-04 15:09:30 -08002132/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002133 * intel_disable_primary_hw_plane - disable the primary hardware plane
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002134 * @plane: plane to be disabled
2135 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002136 *
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002137 * Disable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002138 */
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002139static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002141{
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002142 struct drm_device *dev = plane->dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145
2146 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002147
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002148 if (!intel_crtc->primary_enabled)
2149 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002150
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002151 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002152
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002153 dev_priv->display.update_primary_plane(crtc, plane->fb,
2154 crtc->x, crtc->y);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002155}
2156
Chris Wilson693db182013-03-05 14:52:39 +00002157static bool need_vtd_wa(struct drm_device *dev)
2158{
2159#ifdef CONFIG_INTEL_IOMMU
2160 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2161 return true;
2162#endif
2163 return false;
2164}
2165
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002166static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2167{
2168 int tile_height;
2169
2170 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171 return ALIGN(height, tile_height);
2172}
2173
Chris Wilson127bd2a2010-07-23 23:32:05 +01002174int
Chris Wilson48b956c2010-09-14 12:50:34 +01002175intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002176 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002177 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002178{
Chris Wilsonce453d82011-02-21 14:43:56 +00002179 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002180 u32 alignment;
2181 int ret;
2182
Matt Roperebcdd392014-07-09 16:22:11 -07002183 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2184
Chris Wilson05394f32010-11-08 19:18:58 +00002185 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002186 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002187 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2188 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002189 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002190 alignment = 4 * 1024;
2191 else
2192 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002193 break;
2194 case I915_TILING_X:
2195 /* pin() will align the object as required by fence */
2196 alignment = 0;
2197 break;
2198 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002199 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002200 return -EINVAL;
2201 default:
2202 BUG();
2203 }
2204
Chris Wilson693db182013-03-05 14:52:39 +00002205 /* Note that the w/a also requires 64 PTE of padding following the
2206 * bo. We currently fill all unused PTE with the shadow page and so
2207 * we should always have valid PTE following the scanout preventing
2208 * the VT-d warning.
2209 */
2210 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2211 alignment = 256 * 1024;
2212
Chris Wilsonce453d82011-02-21 14:43:56 +00002213 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002214 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002215 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002216 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002217
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always install
2221 * a fence as the cost is not that onerous.
2222 */
Chris Wilson06d98132012-04-17 15:31:24 +01002223 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002224 if (ret)
2225 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002226
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002227 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002228
Chris Wilsonce453d82011-02-21 14:43:56 +00002229 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002230 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002231
2232err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002233 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002234err_interruptible:
2235 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002236 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002237}
2238
Chris Wilson1690e1e2011-12-14 13:57:08 +01002239void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2240{
Matt Roperebcdd392014-07-09 16:22:11 -07002241 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2242
Chris Wilson1690e1e2011-12-14 13:57:08 +01002243 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002244 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002245}
2246
Daniel Vetterc2c75132012-07-05 12:17:30 +02002247/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2248 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002249unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2250 unsigned int tiling_mode,
2251 unsigned int cpp,
2252 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002253{
Chris Wilsonbc752862013-02-21 20:04:31 +00002254 if (tiling_mode != I915_TILING_NONE) {
2255 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002256
Chris Wilsonbc752862013-02-21 20:04:31 +00002257 tile_rows = *y / 8;
2258 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002259
Chris Wilsonbc752862013-02-21 20:04:31 +00002260 tiles = *x / (512/cpp);
2261 *x %= 512/cpp;
2262
2263 return tile_rows * pitch * 8 + tiles * 4096;
2264 } else {
2265 unsigned int offset;
2266
2267 offset = *y * pitch + *x * cpp;
2268 *y = 0;
2269 *x = (offset & 4095) / cpp;
2270 return offset & -4096;
2271 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002272}
2273
Jesse Barnes46f297f2014-03-07 08:57:48 -08002274int intel_format_to_fourcc(int format)
2275{
2276 switch (format) {
2277 case DISPPLANE_8BPP:
2278 return DRM_FORMAT_C8;
2279 case DISPPLANE_BGRX555:
2280 return DRM_FORMAT_XRGB1555;
2281 case DISPPLANE_BGRX565:
2282 return DRM_FORMAT_RGB565;
2283 default:
2284 case DISPPLANE_BGRX888:
2285 return DRM_FORMAT_XRGB8888;
2286 case DISPPLANE_RGBX888:
2287 return DRM_FORMAT_XBGR8888;
2288 case DISPPLANE_BGRX101010:
2289 return DRM_FORMAT_XRGB2101010;
2290 case DISPPLANE_RGBX101010:
2291 return DRM_FORMAT_XBGR2101010;
2292 }
2293}
2294
Jesse Barnes484b41d2014-03-07 08:57:55 -08002295static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002296 struct intel_plane_config *plane_config)
2297{
2298 struct drm_device *dev = crtc->base.dev;
2299 struct drm_i915_gem_object *obj = NULL;
2300 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2301 u32 base = plane_config->base;
2302
Chris Wilsonff2652e2014-03-10 08:07:02 +00002303 if (plane_config->size == 0)
2304 return false;
2305
Jesse Barnes46f297f2014-03-07 08:57:48 -08002306 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2307 plane_config->size);
2308 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002309 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002310
2311 if (plane_config->tiled) {
2312 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002313 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002314 }
2315
Dave Airlie66e514c2014-04-03 07:51:54 +10002316 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2317 mode_cmd.width = crtc->base.primary->fb->width;
2318 mode_cmd.height = crtc->base.primary->fb->height;
2319 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002320
2321 mutex_lock(&dev->struct_mutex);
2322
Dave Airlie66e514c2014-04-03 07:51:54 +10002323 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002324 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002325 DRM_DEBUG_KMS("intel fb init failed\n");
2326 goto out_unref_obj;
2327 }
2328
Daniel Vettera071fa02014-06-18 23:28:09 +02002329 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002330 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002331
2332 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2333 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002334
2335out_unref_obj:
2336 drm_gem_object_unreference(&obj->base);
2337 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002338 return false;
2339}
2340
2341static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2342 struct intel_plane_config *plane_config)
2343{
2344 struct drm_device *dev = intel_crtc->base.dev;
2345 struct drm_crtc *c;
2346 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002347 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002348
Dave Airlie66e514c2014-04-03 07:51:54 +10002349 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002350 return;
2351
2352 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2353 return;
2354
Dave Airlie66e514c2014-04-03 07:51:54 +10002355 kfree(intel_crtc->base.primary->fb);
2356 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002357
2358 /*
2359 * Failed to alloc the obj, check to see if we should share
2360 * an fb with another CRTC instead
2361 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002362 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002363 i = to_intel_crtc(c);
2364
2365 if (c == &intel_crtc->base)
2366 continue;
2367
Matt Roper2ff8fde2014-07-08 07:50:07 -07002368 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002369 continue;
2370
Matt Roper2ff8fde2014-07-08 07:50:07 -07002371 obj = intel_fb_obj(c->primary->fb);
2372 if (obj == NULL)
2373 continue;
2374
2375 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002376 drm_framebuffer_reference(c->primary->fb);
2377 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002378 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002379 break;
2380 }
2381 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002382}
2383
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002384static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2385 struct drm_framebuffer *fb,
2386 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002387{
2388 struct drm_device *dev = crtc->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002391 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002392 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002393 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002394 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002395 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302396 int pixel_size;
2397
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002398 if (!intel_crtc->primary_enabled) {
2399 I915_WRITE(reg, 0);
2400 if (INTEL_INFO(dev)->gen >= 4)
2401 I915_WRITE(DSPSURF(plane), 0);
2402 else
2403 I915_WRITE(DSPADDR(plane), 0);
2404 POSTING_READ(reg);
2405 return;
2406 }
2407
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002408 obj = intel_fb_obj(fb);
2409 if (WARN_ON(obj == NULL))
2410 return;
2411
2412 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2413
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002414 dspcntr = DISPPLANE_GAMMA_ENABLE;
2415
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002416 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002417
2418 if (INTEL_INFO(dev)->gen < 4) {
2419 if (intel_crtc->pipe == PIPE_B)
2420 dspcntr |= DISPPLANE_SEL_PIPE_B;
2421
2422 /* pipesrc and dspsize control the size that is scaled from,
2423 * which should always be the user's requested size.
2424 */
2425 I915_WRITE(DSPSIZE(plane),
2426 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2427 (intel_crtc->config.pipe_src_w - 1));
2428 I915_WRITE(DSPPOS(plane), 0);
2429 }
2430
Ville Syrjälä57779d02012-10-31 17:50:14 +02002431 switch (fb->pixel_format) {
2432 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002433 dspcntr |= DISPPLANE_8BPP;
2434 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002435 case DRM_FORMAT_XRGB1555:
2436 case DRM_FORMAT_ARGB1555:
2437 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002438 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002439 case DRM_FORMAT_RGB565:
2440 dspcntr |= DISPPLANE_BGRX565;
2441 break;
2442 case DRM_FORMAT_XRGB8888:
2443 case DRM_FORMAT_ARGB8888:
2444 dspcntr |= DISPPLANE_BGRX888;
2445 break;
2446 case DRM_FORMAT_XBGR8888:
2447 case DRM_FORMAT_ABGR8888:
2448 dspcntr |= DISPPLANE_RGBX888;
2449 break;
2450 case DRM_FORMAT_XRGB2101010:
2451 case DRM_FORMAT_ARGB2101010:
2452 dspcntr |= DISPPLANE_BGRX101010;
2453 break;
2454 case DRM_FORMAT_XBGR2101010:
2455 case DRM_FORMAT_ABGR2101010:
2456 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002457 break;
2458 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002459 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002460 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002461
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002462 if (INTEL_INFO(dev)->gen >= 4 &&
2463 obj->tiling_mode != I915_TILING_NONE)
2464 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002465
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002466 if (IS_G4X(dev))
2467 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2468
Daniel Vettere506a0c2012-07-05 12:17:29 +02002469 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002470
Daniel Vetterc2c75132012-07-05 12:17:30 +02002471 if (INTEL_INFO(dev)->gen >= 4) {
2472 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002473 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2474 fb->bits_per_pixel / 8,
2475 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002476 linear_offset -= intel_crtc->dspaddr_offset;
2477 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002478 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002479 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002480
Sonika Jindal48404c12014-08-22 14:06:04 +05302481 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2482 dspcntr |= DISPPLANE_ROTATE_180;
2483
2484 x += (intel_crtc->config.pipe_src_w - 1);
2485 y += (intel_crtc->config.pipe_src_h - 1);
2486
2487 /* Finding the last pixel of the last line of the display
2488 data and adding to linear_offset*/
2489 linear_offset +=
2490 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2491 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2492 }
2493
2494 I915_WRITE(reg, dspcntr);
2495
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002496 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2497 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2498 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002499 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002500 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002501 I915_WRITE(DSPSURF(plane),
2502 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002503 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002504 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002505 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002506 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002507 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002508}
2509
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002510static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2511 struct drm_framebuffer *fb,
2512 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002513{
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002517 struct drm_i915_gem_object *obj;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002518 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002519 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002520 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002521 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302522 int pixel_size;
2523
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002524 if (!intel_crtc->primary_enabled) {
2525 I915_WRITE(reg, 0);
2526 I915_WRITE(DSPSURF(plane), 0);
2527 POSTING_READ(reg);
2528 return;
2529 }
2530
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002531 obj = intel_fb_obj(fb);
2532 if (WARN_ON(obj == NULL))
2533 return;
2534
2535 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2536
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002537 dspcntr = DISPPLANE_GAMMA_ENABLE;
2538
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002539 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002540
2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2543
Ville Syrjälä57779d02012-10-31 17:50:14 +02002544 switch (fb->pixel_format) {
2545 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002546 dspcntr |= DISPPLANE_8BPP;
2547 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002548 case DRM_FORMAT_RGB565:
2549 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002550 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002551 case DRM_FORMAT_XRGB8888:
2552 case DRM_FORMAT_ARGB8888:
2553 dspcntr |= DISPPLANE_BGRX888;
2554 break;
2555 case DRM_FORMAT_XBGR8888:
2556 case DRM_FORMAT_ABGR8888:
2557 dspcntr |= DISPPLANE_RGBX888;
2558 break;
2559 case DRM_FORMAT_XRGB2101010:
2560 case DRM_FORMAT_ARGB2101010:
2561 dspcntr |= DISPPLANE_BGRX101010;
2562 break;
2563 case DRM_FORMAT_XBGR2101010:
2564 case DRM_FORMAT_ABGR2101010:
2565 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002566 break;
2567 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002568 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002569 }
2570
2571 if (obj->tiling_mode != I915_TILING_NONE)
2572 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002573
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002574 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002575 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002576
Daniel Vettere506a0c2012-07-05 12:17:29 +02002577 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002578 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002579 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2580 fb->bits_per_pixel / 8,
2581 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002582 linear_offset -= intel_crtc->dspaddr_offset;
Sonika Jindal48404c12014-08-22 14:06:04 +05302583 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2584 dspcntr |= DISPPLANE_ROTATE_180;
2585
2586 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2587 x += (intel_crtc->config.pipe_src_w - 1);
2588 y += (intel_crtc->config.pipe_src_h - 1);
2589
2590 /* Finding the last pixel of the last line of the display
2591 data and adding to linear_offset*/
2592 linear_offset +=
2593 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2594 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2595 }
2596 }
2597
2598 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002599
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002600 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2601 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2602 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002603 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002604 I915_WRITE(DSPSURF(plane),
2605 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002606 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002607 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2608 } else {
2609 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2610 I915_WRITE(DSPLINOFF(plane), linear_offset);
2611 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002612 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002613}
2614
2615/* Assume fb object is pinned & idle & fenced and just update base pointers */
2616static int
2617intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2618 int x, int y, enum mode_set_atomic state)
2619{
2620 struct drm_device *dev = crtc->dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002622
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002623 if (dev_priv->display.disable_fbc)
2624 dev_priv->display.disable_fbc(dev);
Daniel Vettercc365132014-06-18 13:59:13 +02002625 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
Jesse Barnes81255562010-08-02 12:07:50 -07002626
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002627 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2628
2629 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002630}
2631
Ville Syrjälä96a02912013-02-18 19:08:49 +02002632void intel_display_handle_reset(struct drm_device *dev)
2633{
2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 struct drm_crtc *crtc;
2636
2637 /*
2638 * Flips in the rings have been nuked by the reset,
2639 * so complete all pending flips so that user space
2640 * will get its events and not get stuck.
2641 *
2642 * Also update the base address of all primary
2643 * planes to the the last fb to make sure we're
2644 * showing the correct fb after a reset.
2645 *
2646 * Need to make two loops over the crtcs so that we
2647 * don't try to grab a crtc mutex before the
2648 * pending_flip_queue really got woken up.
2649 */
2650
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002651 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653 enum plane plane = intel_crtc->plane;
2654
2655 intel_prepare_page_flip(dev, plane);
2656 intel_finish_page_flip_plane(dev, plane);
2657 }
2658
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002659 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661
Rob Clark51fd3712013-11-19 12:10:12 -05002662 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002663 /*
2664 * FIXME: Once we have proper support for primary planes (and
2665 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002666 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002667 */
Matt Roperf4510a22014-04-01 15:22:40 -07002668 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002669 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002670 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002671 crtc->x,
2672 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002673 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002674 }
2675}
2676
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002677static int
Chris Wilson14667a42012-04-03 17:58:35 +01002678intel_finish_fb(struct drm_framebuffer *old_fb)
2679{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002680 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002681 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2682 bool was_interruptible = dev_priv->mm.interruptible;
2683 int ret;
2684
Chris Wilson14667a42012-04-03 17:58:35 +01002685 /* Big Hammer, we also need to ensure that any pending
2686 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2687 * current scanout is retired before unpinning the old
2688 * framebuffer.
2689 *
2690 * This should only fail upon a hung GPU, in which case we
2691 * can safely continue.
2692 */
2693 dev_priv->mm.interruptible = false;
2694 ret = i915_gem_object_finish_gpu(obj);
2695 dev_priv->mm.interruptible = was_interruptible;
2696
2697 return ret;
2698}
2699
Chris Wilson7d5e3792014-03-04 13:15:08 +00002700static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2701{
2702 struct drm_device *dev = crtc->dev;
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2705 unsigned long flags;
2706 bool pending;
2707
2708 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2709 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2710 return false;
2711
2712 spin_lock_irqsave(&dev->event_lock, flags);
2713 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2714 spin_unlock_irqrestore(&dev->event_lock, flags);
2715
2716 return pending;
2717}
2718
Chris Wilson14667a42012-04-03 17:58:35 +01002719static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002720intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002721 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002722{
2723 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002724 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002726 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002727 struct drm_framebuffer *old_fb = crtc->primary->fb;
2728 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2729 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002730 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002731
Chris Wilson7d5e3792014-03-04 13:15:08 +00002732 if (intel_crtc_has_pending_flip(crtc)) {
2733 DRM_ERROR("pipe is still busy with an old pageflip\n");
2734 return -EBUSY;
2735 }
2736
Jesse Barnes79e53942008-11-07 14:24:08 -08002737 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002738 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002739 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002740 return 0;
2741 }
2742
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002743 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002744 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2745 plane_name(intel_crtc->plane),
2746 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002747 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002748 }
2749
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002750 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02002751 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2752 if (ret == 0)
Matt Roper91565c852014-06-24 17:05:02 -07002753 i915_gem_track_fb(old_obj, obj,
Daniel Vettera071fa02014-06-18 23:28:09 +02002754 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002755 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002756 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002757 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002758 return ret;
2759 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002760
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002761 /*
2762 * Update pipe size and adjust fitter if needed: the reason for this is
2763 * that in compute_mode_changes we check the native mode (not the pfit
2764 * mode) to see if we can flip rather than do a full mode set. In the
2765 * fastboot case, we'll flip, but if we don't update the pipesrc and
2766 * pfit state, we'll end up with a big fb scanned out into the wrong
2767 * sized surface.
2768 *
2769 * To fix this properly, we need to hoist the checks up into
2770 * compute_mode_changes (or above), check the actual pfit state and
2771 * whether the platform allows pfit disable with pipe active, and only
2772 * then update the pipesrc and pfit state, even on the flip path.
2773 */
Jani Nikulad330a952014-01-21 11:24:25 +02002774 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002775 const struct drm_display_mode *adjusted_mode =
2776 &intel_crtc->config.adjusted_mode;
2777
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002778 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002779 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2780 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002781 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002782 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2783 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2784 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2785 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2786 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2787 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002788 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2789 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002790 }
2791
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002792 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002793
Daniel Vetterf99d7062014-06-19 16:01:59 +02002794 if (intel_crtc->active)
2795 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2796
Matt Roperf4510a22014-04-01 15:22:40 -07002797 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002798 crtc->x = x;
2799 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002800
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002801 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002802 if (intel_crtc->active && old_fb != fb)
2803 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002804 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002805 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002806 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002807 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002808
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002809 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002810 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002811 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002812
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002813 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002814}
2815
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002816static void intel_fdi_normal_train(struct drm_crtc *crtc)
2817{
2818 struct drm_device *dev = crtc->dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 int pipe = intel_crtc->pipe;
2822 u32 reg, temp;
2823
2824 /* enable normal train */
2825 reg = FDI_TX_CTL(pipe);
2826 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002827 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002828 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2829 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002830 } else {
2831 temp &= ~FDI_LINK_TRAIN_NONE;
2832 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002833 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_NONE;
2844 }
2845 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2846
2847 /* wait one idle pattern time */
2848 POSTING_READ(reg);
2849 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002850
2851 /* IVB wants error correction enabled */
2852 if (IS_IVYBRIDGE(dev))
2853 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2854 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002855}
2856
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002857static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002858{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002859 return crtc->base.enabled && crtc->active &&
2860 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002861}
2862
Daniel Vetter01a415f2012-10-27 15:58:40 +02002863static void ivb_modeset_global_resources(struct drm_device *dev)
2864{
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 struct intel_crtc *pipe_B_crtc =
2867 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2868 struct intel_crtc *pipe_C_crtc =
2869 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2870 uint32_t temp;
2871
Daniel Vetter1e833f42013-02-19 22:31:57 +01002872 /*
2873 * When everything is off disable fdi C so that we could enable fdi B
2874 * with all lanes. Note that we don't care about enabled pipes without
2875 * an enabled pch encoder.
2876 */
2877 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2878 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002879 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2880 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2881
2882 temp = I915_READ(SOUTH_CHICKEN1);
2883 temp &= ~FDI_BC_BIFURCATION_SELECT;
2884 DRM_DEBUG_KMS("disabling fdi C rx\n");
2885 I915_WRITE(SOUTH_CHICKEN1, temp);
2886 }
2887}
2888
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002889/* The FDI link training functions for ILK/Ibexpeak. */
2890static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002896 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002897
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002898 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002899 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002900
Adam Jacksone1a44742010-06-25 15:32:14 -04002901 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2902 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002903 reg = FDI_RX_IMR(pipe);
2904 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002905 temp &= ~FDI_RX_SYMBOL_LOCK;
2906 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002907 I915_WRITE(reg, temp);
2908 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002909 udelay(150);
2910
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002911 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002912 reg = FDI_TX_CTL(pipe);
2913 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002914 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2915 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002918 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002919
Chris Wilson5eddb702010-09-11 13:48:45 +01002920 reg = FDI_RX_CTL(pipe);
2921 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002922 temp &= ~FDI_LINK_TRAIN_NONE;
2923 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002924 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2925
2926 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002927 udelay(150);
2928
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002929 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002930 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2931 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2932 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002933
Chris Wilson5eddb702010-09-11 13:48:45 +01002934 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002935 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002936 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002937 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2938
2939 if ((temp & FDI_RX_BIT_LOCK)) {
2940 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002941 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002942 break;
2943 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002944 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002945 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002946 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002947
2948 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002949 reg = FDI_TX_CTL(pipe);
2950 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002953 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002954
Chris Wilson5eddb702010-09-11 13:48:45 +01002955 reg = FDI_RX_CTL(pipe);
2956 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002957 temp &= ~FDI_LINK_TRAIN_NONE;
2958 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002959 I915_WRITE(reg, temp);
2960
2961 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002962 udelay(150);
2963
Chris Wilson5eddb702010-09-11 13:48:45 +01002964 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002965 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002966 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002967 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2968
2969 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002970 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002971 DRM_DEBUG_KMS("FDI train 2 done.\n");
2972 break;
2973 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002974 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002975 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002976 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002977
2978 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002979
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002980}
2981
Akshay Joshi0206e352011-08-16 15:34:10 -04002982static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002983 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2984 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2985 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2986 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2987};
2988
2989/* The FDI link training functions for SNB/Cougarpoint. */
2990static void gen6_fdi_link_train(struct drm_crtc *crtc)
2991{
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002996 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002997
Adam Jacksone1a44742010-06-25 15:32:14 -04002998 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2999 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003000 reg = FDI_RX_IMR(pipe);
3001 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003002 temp &= ~FDI_RX_SYMBOL_LOCK;
3003 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003004 I915_WRITE(reg, temp);
3005
3006 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003007 udelay(150);
3008
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003009 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003010 reg = FDI_TX_CTL(pipe);
3011 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003012 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3013 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003014 temp &= ~FDI_LINK_TRAIN_NONE;
3015 temp |= FDI_LINK_TRAIN_PATTERN_1;
3016 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3017 /* SNB-B */
3018 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003019 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003020
Daniel Vetterd74cf322012-10-26 10:58:13 +02003021 I915_WRITE(FDI_RX_MISC(pipe),
3022 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3023
Chris Wilson5eddb702010-09-11 13:48:45 +01003024 reg = FDI_RX_CTL(pipe);
3025 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003026 if (HAS_PCH_CPT(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3028 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3029 } else {
3030 temp &= ~FDI_LINK_TRAIN_NONE;
3031 temp |= FDI_LINK_TRAIN_PATTERN_1;
3032 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003033 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3034
3035 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003036 udelay(150);
3037
Akshay Joshi0206e352011-08-16 15:34:10 -04003038 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003039 reg = FDI_TX_CTL(pipe);
3040 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003041 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3042 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003043 I915_WRITE(reg, temp);
3044
3045 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003046 udelay(500);
3047
Sean Paulfa37d392012-03-02 12:53:39 -05003048 for (retry = 0; retry < 5; retry++) {
3049 reg = FDI_RX_IIR(pipe);
3050 temp = I915_READ(reg);
3051 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3052 if (temp & FDI_RX_BIT_LOCK) {
3053 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3054 DRM_DEBUG_KMS("FDI train 1 done.\n");
3055 break;
3056 }
3057 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003058 }
Sean Paulfa37d392012-03-02 12:53:39 -05003059 if (retry < 5)
3060 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003061 }
3062 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003063 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003064
3065 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003066 reg = FDI_TX_CTL(pipe);
3067 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003068 temp &= ~FDI_LINK_TRAIN_NONE;
3069 temp |= FDI_LINK_TRAIN_PATTERN_2;
3070 if (IS_GEN6(dev)) {
3071 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3072 /* SNB-B */
3073 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3074 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003075 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003076
Chris Wilson5eddb702010-09-11 13:48:45 +01003077 reg = FDI_RX_CTL(pipe);
3078 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003079 if (HAS_PCH_CPT(dev)) {
3080 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3081 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3082 } else {
3083 temp &= ~FDI_LINK_TRAIN_NONE;
3084 temp |= FDI_LINK_TRAIN_PATTERN_2;
3085 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003086 I915_WRITE(reg, temp);
3087
3088 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003089 udelay(150);
3090
Akshay Joshi0206e352011-08-16 15:34:10 -04003091 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003092 reg = FDI_TX_CTL(pipe);
3093 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003094 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3095 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003096 I915_WRITE(reg, temp);
3097
3098 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003099 udelay(500);
3100
Sean Paulfa37d392012-03-02 12:53:39 -05003101 for (retry = 0; retry < 5; retry++) {
3102 reg = FDI_RX_IIR(pipe);
3103 temp = I915_READ(reg);
3104 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3105 if (temp & FDI_RX_SYMBOL_LOCK) {
3106 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3107 DRM_DEBUG_KMS("FDI train 2 done.\n");
3108 break;
3109 }
3110 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003111 }
Sean Paulfa37d392012-03-02 12:53:39 -05003112 if (retry < 5)
3113 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003114 }
3115 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003116 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003117
3118 DRM_DEBUG_KMS("FDI train done.\n");
3119}
3120
Jesse Barnes357555c2011-04-28 15:09:55 -07003121/* Manual link training for Ivy Bridge A0 parts */
3122static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3123{
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003128 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003129
3130 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3131 for train result */
3132 reg = FDI_RX_IMR(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~FDI_RX_SYMBOL_LOCK;
3135 temp &= ~FDI_RX_BIT_LOCK;
3136 I915_WRITE(reg, temp);
3137
3138 POSTING_READ(reg);
3139 udelay(150);
3140
Daniel Vetter01a415f2012-10-27 15:58:40 +02003141 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3142 I915_READ(FDI_RX_IIR(pipe)));
3143
Jesse Barnes139ccd32013-08-19 11:04:55 -07003144 /* Try each vswing and preemphasis setting twice before moving on */
3145 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3146 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003147 reg = FDI_TX_CTL(pipe);
3148 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003149 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3150 temp &= ~FDI_TX_ENABLE;
3151 I915_WRITE(reg, temp);
3152
3153 reg = FDI_RX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 temp &= ~FDI_LINK_TRAIN_AUTO;
3156 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3157 temp &= ~FDI_RX_ENABLE;
3158 I915_WRITE(reg, temp);
3159
3160 /* enable CPU FDI TX and PCH FDI RX */
3161 reg = FDI_TX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3164 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3165 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003166 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003167 temp |= snb_b_fdi_train_param[j/2];
3168 temp |= FDI_COMPOSITE_SYNC;
3169 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3170
3171 I915_WRITE(FDI_RX_MISC(pipe),
3172 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3173
3174 reg = FDI_RX_CTL(pipe);
3175 temp = I915_READ(reg);
3176 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3177 temp |= FDI_COMPOSITE_SYNC;
3178 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3179
3180 POSTING_READ(reg);
3181 udelay(1); /* should be 0.5us */
3182
3183 for (i = 0; i < 4; i++) {
3184 reg = FDI_RX_IIR(pipe);
3185 temp = I915_READ(reg);
3186 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3187
3188 if (temp & FDI_RX_BIT_LOCK ||
3189 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3190 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3191 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3192 i);
3193 break;
3194 }
3195 udelay(1); /* should be 0.5us */
3196 }
3197 if (i == 4) {
3198 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3199 continue;
3200 }
3201
3202 /* Train 2 */
3203 reg = FDI_TX_CTL(pipe);
3204 temp = I915_READ(reg);
3205 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3206 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3207 I915_WRITE(reg, temp);
3208
3209 reg = FDI_RX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3212 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003213 I915_WRITE(reg, temp);
3214
3215 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003216 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003217
Jesse Barnes139ccd32013-08-19 11:04:55 -07003218 for (i = 0; i < 4; i++) {
3219 reg = FDI_RX_IIR(pipe);
3220 temp = I915_READ(reg);
3221 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003222
Jesse Barnes139ccd32013-08-19 11:04:55 -07003223 if (temp & FDI_RX_SYMBOL_LOCK ||
3224 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3225 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3226 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3227 i);
3228 goto train_done;
3229 }
3230 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003231 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003232 if (i == 4)
3233 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003234 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003235
Jesse Barnes139ccd32013-08-19 11:04:55 -07003236train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003237 DRM_DEBUG_KMS("FDI train done.\n");
3238}
3239
Daniel Vetter88cefb62012-08-12 19:27:14 +02003240static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003241{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003242 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003243 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003244 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003245 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003246
Jesse Barnesc64e3112010-09-10 11:27:03 -07003247
Jesse Barnes0e23b992010-09-10 11:10:00 -07003248 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003251 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3252 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003253 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003254 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3255
3256 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003257 udelay(200);
3258
3259 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003260 temp = I915_READ(reg);
3261 I915_WRITE(reg, temp | FDI_PCDCLK);
3262
3263 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003264 udelay(200);
3265
Paulo Zanoni20749732012-11-23 15:30:38 -02003266 /* Enable CPU FDI TX PLL, always on for Ironlake */
3267 reg = FDI_TX_CTL(pipe);
3268 temp = I915_READ(reg);
3269 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3270 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003271
Paulo Zanoni20749732012-11-23 15:30:38 -02003272 POSTING_READ(reg);
3273 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003274 }
3275}
3276
Daniel Vetter88cefb62012-08-12 19:27:14 +02003277static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3278{
3279 struct drm_device *dev = intel_crtc->base.dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 int pipe = intel_crtc->pipe;
3282 u32 reg, temp;
3283
3284 /* Switch from PCDclk to Rawclk */
3285 reg = FDI_RX_CTL(pipe);
3286 temp = I915_READ(reg);
3287 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3288
3289 /* Disable CPU FDI TX PLL */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3293
3294 POSTING_READ(reg);
3295 udelay(100);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3300
3301 /* Wait for the clocks to turn off. */
3302 POSTING_READ(reg);
3303 udelay(100);
3304}
3305
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003306static void ironlake_fdi_disable(struct drm_crtc *crtc)
3307{
3308 struct drm_device *dev = crtc->dev;
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3311 int pipe = intel_crtc->pipe;
3312 u32 reg, temp;
3313
3314 /* disable CPU FDI tx and PCH FDI rx */
3315 reg = FDI_TX_CTL(pipe);
3316 temp = I915_READ(reg);
3317 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3318 POSTING_READ(reg);
3319
3320 reg = FDI_RX_CTL(pipe);
3321 temp = I915_READ(reg);
3322 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003323 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003324 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3325
3326 POSTING_READ(reg);
3327 udelay(100);
3328
3329 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003330 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003331 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003332
3333 /* still set train pattern 1 */
3334 reg = FDI_TX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_PATTERN_1;
3338 I915_WRITE(reg, temp);
3339
3340 reg = FDI_RX_CTL(pipe);
3341 temp = I915_READ(reg);
3342 if (HAS_PCH_CPT(dev)) {
3343 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3344 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3345 } else {
3346 temp &= ~FDI_LINK_TRAIN_NONE;
3347 temp |= FDI_LINK_TRAIN_PATTERN_1;
3348 }
3349 /* BPC in FDI rx is consistent with that in PIPECONF */
3350 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003351 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003352 I915_WRITE(reg, temp);
3353
3354 POSTING_READ(reg);
3355 udelay(100);
3356}
3357
Chris Wilson5dce5b932014-01-20 10:17:36 +00003358bool intel_has_pending_fb_unpin(struct drm_device *dev)
3359{
3360 struct intel_crtc *crtc;
3361
3362 /* Note that we don't need to be called with mode_config.lock here
3363 * as our list of CRTC objects is static for the lifetime of the
3364 * device and so cannot disappear as we iterate. Similarly, we can
3365 * happily treat the predicates as racy, atomic checks as userspace
3366 * cannot claim and pin a new fb without at least acquring the
3367 * struct_mutex and so serialising with us.
3368 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003369 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003370 if (atomic_read(&crtc->unpin_work_count) == 0)
3371 continue;
3372
3373 if (crtc->unpin_work)
3374 intel_wait_for_vblank(dev, crtc->pipe);
3375
3376 return true;
3377 }
3378
3379 return false;
3380}
3381
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003382void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003383{
Chris Wilson0f911282012-04-17 10:05:38 +01003384 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003385 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003386
Daniel Vetter2c10d572012-12-20 21:24:07 +01003387 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Daniel Vettereed6d672014-05-19 16:09:35 +02003388 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3389 !intel_crtc_has_pending_flip(crtc),
3390 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003391
Chris Wilson975d5682014-08-20 13:13:34 +01003392 if (crtc->primary->fb) {
3393 mutex_lock(&dev->struct_mutex);
3394 intel_finish_fb(crtc->primary->fb);
3395 mutex_unlock(&dev->struct_mutex);
3396 }
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003397}
3398
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003399/* Program iCLKIP clock to the desired frequency */
3400static void lpt_program_iclkip(struct drm_crtc *crtc)
3401{
3402 struct drm_device *dev = crtc->dev;
3403 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003404 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003405 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3406 u32 temp;
3407
Daniel Vetter09153002012-12-12 14:06:44 +01003408 mutex_lock(&dev_priv->dpio_lock);
3409
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003410 /* It is necessary to ungate the pixclk gate prior to programming
3411 * the divisors, and gate it back when it is done.
3412 */
3413 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3414
3415 /* Disable SSCCTL */
3416 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003417 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3418 SBI_SSCCTL_DISABLE,
3419 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003420
3421 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003422 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003423 auxdiv = 1;
3424 divsel = 0x41;
3425 phaseinc = 0x20;
3426 } else {
3427 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003428 * but the adjusted_mode->crtc_clock in in KHz. To get the
3429 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003430 * convert the virtual clock precision to KHz here for higher
3431 * precision.
3432 */
3433 u32 iclk_virtual_root_freq = 172800 * 1000;
3434 u32 iclk_pi_range = 64;
3435 u32 desired_divisor, msb_divisor_value, pi_value;
3436
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003437 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003438 msb_divisor_value = desired_divisor / iclk_pi_range;
3439 pi_value = desired_divisor % iclk_pi_range;
3440
3441 auxdiv = 0;
3442 divsel = msb_divisor_value - 2;
3443 phaseinc = pi_value;
3444 }
3445
3446 /* This should not happen with any sane values */
3447 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3448 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3449 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3450 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3451
3452 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003453 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003454 auxdiv,
3455 divsel,
3456 phasedir,
3457 phaseinc);
3458
3459 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003460 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003461 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3462 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3463 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3464 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3465 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3466 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003467 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003468
3469 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003470 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003471 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3472 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003473 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003474
3475 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003476 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003477 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003478 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003479
3480 /* Wait for initialization time */
3481 udelay(24);
3482
3483 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003484
3485 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003486}
3487
Daniel Vetter275f01b22013-05-03 11:49:47 +02003488static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3489 enum pipe pch_transcoder)
3490{
3491 struct drm_device *dev = crtc->base.dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3494
3495 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3496 I915_READ(HTOTAL(cpu_transcoder)));
3497 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3498 I915_READ(HBLANK(cpu_transcoder)));
3499 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3500 I915_READ(HSYNC(cpu_transcoder)));
3501
3502 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3503 I915_READ(VTOTAL(cpu_transcoder)));
3504 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3505 I915_READ(VBLANK(cpu_transcoder)));
3506 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3507 I915_READ(VSYNC(cpu_transcoder)));
3508 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3509 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3510}
3511
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003512static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3513{
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 uint32_t temp;
3516
3517 temp = I915_READ(SOUTH_CHICKEN1);
3518 if (temp & FDI_BC_BIFURCATION_SELECT)
3519 return;
3520
3521 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3522 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3523
3524 temp |= FDI_BC_BIFURCATION_SELECT;
3525 DRM_DEBUG_KMS("enabling fdi C rx\n");
3526 I915_WRITE(SOUTH_CHICKEN1, temp);
3527 POSTING_READ(SOUTH_CHICKEN1);
3528}
3529
3530static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3531{
3532 struct drm_device *dev = intel_crtc->base.dev;
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534
3535 switch (intel_crtc->pipe) {
3536 case PIPE_A:
3537 break;
3538 case PIPE_B:
3539 if (intel_crtc->config.fdi_lanes > 2)
3540 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3541 else
3542 cpt_enable_fdi_bc_bifurcation(dev);
3543
3544 break;
3545 case PIPE_C:
3546 cpt_enable_fdi_bc_bifurcation(dev);
3547
3548 break;
3549 default:
3550 BUG();
3551 }
3552}
3553
Jesse Barnesf67a5592011-01-05 10:31:48 -08003554/*
3555 * Enable PCH resources required for PCH ports:
3556 * - PCH PLLs
3557 * - FDI training & RX/TX
3558 * - update transcoder timings
3559 * - DP transcoding bits
3560 * - transcoder
3561 */
3562static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003563{
3564 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003565 struct drm_i915_private *dev_priv = dev->dev_private;
3566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003568 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003569
Daniel Vetterab9412b2013-05-03 11:49:46 +02003570 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003571
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003572 if (IS_IVYBRIDGE(dev))
3573 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3574
Daniel Vettercd986ab2012-10-26 10:58:12 +02003575 /* Write the TU size bits before fdi link training, so that error
3576 * detection works. */
3577 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3578 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3579
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003580 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003581 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003582
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003583 /* We need to program the right clock selection before writing the pixel
3584 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003585 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003586 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003587
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003588 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003589 temp |= TRANS_DPLL_ENABLE(pipe);
3590 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003591 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003592 temp |= sel;
3593 else
3594 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003595 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003596 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003597
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003598 /* XXX: pch pll's can be enabled any time before we enable the PCH
3599 * transcoder, and we actually should do this to not upset any PCH
3600 * transcoder that already use the clock when we share it.
3601 *
3602 * Note that enable_shared_dpll tries to do the right thing, but
3603 * get_shared_dpll unconditionally resets the pll - we need that to have
3604 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003605 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003606
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003607 /* set transcoder timing, panel must allow it */
3608 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003609 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003610
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003611 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003612
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003613 /* For PCH DP, enable TRANS_DP_CTL */
3614 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003615 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3616 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003617 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003618 reg = TRANS_DP_CTL(pipe);
3619 temp = I915_READ(reg);
3620 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003621 TRANS_DP_SYNC_MASK |
3622 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003623 temp |= (TRANS_DP_OUTPUT_ENABLE |
3624 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003625 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003626
3627 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003628 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003629 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003630 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003631
3632 switch (intel_trans_dp_port_sel(crtc)) {
3633 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003634 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003635 break;
3636 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003637 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003638 break;
3639 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003640 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003641 break;
3642 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003643 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003644 }
3645
Chris Wilson5eddb702010-09-11 13:48:45 +01003646 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003647 }
3648
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003649 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003650}
3651
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003652static void lpt_pch_enable(struct drm_crtc *crtc)
3653{
3654 struct drm_device *dev = crtc->dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003657 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003658
Daniel Vetterab9412b2013-05-03 11:49:46 +02003659 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003660
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003661 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003662
Paulo Zanoni0540e482012-10-31 18:12:40 -02003663 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003664 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003665
Paulo Zanoni937bb612012-10-31 18:12:47 -02003666 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003667}
3668
Daniel Vetter716c2e52014-06-25 22:02:02 +03003669void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003670{
Daniel Vettere2b78262013-06-07 23:10:03 +02003671 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003672
3673 if (pll == NULL)
3674 return;
3675
3676 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003677 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003678 return;
3679 }
3680
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003681 if (--pll->refcount == 0) {
3682 WARN_ON(pll->on);
3683 WARN_ON(pll->active);
3684 }
3685
Daniel Vettera43f6e02013-06-07 23:10:32 +02003686 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003687}
3688
Daniel Vetter716c2e52014-06-25 22:02:02 +03003689struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003690{
Daniel Vettere2b78262013-06-07 23:10:03 +02003691 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3692 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3693 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003694
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003695 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003696 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3697 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003698 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003699 }
3700
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003701 if (HAS_PCH_IBX(dev_priv->dev)) {
3702 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003703 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003704 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003705
Daniel Vetter46edb022013-06-05 13:34:12 +02003706 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3707 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003708
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003709 WARN_ON(pll->refcount);
3710
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003711 goto found;
3712 }
3713
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003714 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3715 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003716
3717 /* Only want to check enabled timings first */
3718 if (pll->refcount == 0)
3719 continue;
3720
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003721 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3722 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003723 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003724 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003725 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003726
3727 goto found;
3728 }
3729 }
3730
3731 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003732 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3733 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003734 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003735 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3736 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003737 goto found;
3738 }
3739 }
3740
3741 return NULL;
3742
3743found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003744 if (pll->refcount == 0)
3745 pll->hw_state = crtc->config.dpll_hw_state;
3746
Daniel Vettera43f6e02013-06-07 23:10:32 +02003747 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003748 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3749 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003750
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003751 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003752
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003753 return pll;
3754}
3755
Daniel Vettera1520312013-05-03 11:49:50 +02003756static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003757{
3758 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003759 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003760 u32 temp;
3761
3762 temp = I915_READ(dslreg);
3763 udelay(500);
3764 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003765 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003766 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003767 }
3768}
3769
Jesse Barnesb074cec2013-04-25 12:55:02 -07003770static void ironlake_pfit_enable(struct intel_crtc *crtc)
3771{
3772 struct drm_device *dev = crtc->base.dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 int pipe = crtc->pipe;
3775
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003776 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003777 /* Force use of hard-coded filter coefficients
3778 * as some pre-programmed values are broken,
3779 * e.g. x201.
3780 */
3781 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3782 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3783 PF_PIPE_SEL_IVB(pipe));
3784 else
3785 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3786 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3787 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003788 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003789}
3790
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003791static void intel_enable_planes(struct drm_crtc *crtc)
3792{
3793 struct drm_device *dev = crtc->dev;
3794 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003795 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003796 struct intel_plane *intel_plane;
3797
Matt Roperaf2b6532014-04-01 15:22:32 -07003798 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3799 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003800 if (intel_plane->pipe == pipe)
3801 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003802 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003803}
3804
3805static void intel_disable_planes(struct drm_crtc *crtc)
3806{
3807 struct drm_device *dev = crtc->dev;
3808 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003809 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003810 struct intel_plane *intel_plane;
3811
Matt Roperaf2b6532014-04-01 15:22:32 -07003812 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3813 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003814 if (intel_plane->pipe == pipe)
3815 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003816 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003817}
3818
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003819void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003820{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003821 struct drm_device *dev = crtc->base.dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003823
3824 if (!crtc->config.ips_enabled)
3825 return;
3826
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003827 /* We can only enable IPS after we enable a plane and wait for a vblank */
3828 intel_wait_for_vblank(dev, crtc->pipe);
3829
Paulo Zanonid77e4532013-09-24 13:52:55 -03003830 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003831 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003832 mutex_lock(&dev_priv->rps.hw_lock);
3833 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3834 mutex_unlock(&dev_priv->rps.hw_lock);
3835 /* Quoting Art Runyan: "its not safe to expect any particular
3836 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003837 * mailbox." Moreover, the mailbox may return a bogus state,
3838 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003839 */
3840 } else {
3841 I915_WRITE(IPS_CTL, IPS_ENABLE);
3842 /* The bit only becomes 1 in the next vblank, so this wait here
3843 * is essentially intel_wait_for_vblank. If we don't have this
3844 * and don't wait for vblanks until the end of crtc_enable, then
3845 * the HW state readout code will complain that the expected
3846 * IPS_CTL value is not the one we read. */
3847 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3848 DRM_ERROR("Timed out waiting for IPS enable\n");
3849 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003850}
3851
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003852void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003853{
3854 struct drm_device *dev = crtc->base.dev;
3855 struct drm_i915_private *dev_priv = dev->dev_private;
3856
3857 if (!crtc->config.ips_enabled)
3858 return;
3859
3860 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003861 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003862 mutex_lock(&dev_priv->rps.hw_lock);
3863 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3864 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003865 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3866 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3867 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003868 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003869 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003870 POSTING_READ(IPS_CTL);
3871 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003872
3873 /* We need to wait for a vblank before we can disable the plane. */
3874 intel_wait_for_vblank(dev, crtc->pipe);
3875}
3876
3877/** Loads the palette/gamma unit for the CRTC with the prepared values */
3878static void intel_crtc_load_lut(struct drm_crtc *crtc)
3879{
3880 struct drm_device *dev = crtc->dev;
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3883 enum pipe pipe = intel_crtc->pipe;
3884 int palreg = PALETTE(pipe);
3885 int i;
3886 bool reenable_ips = false;
3887
3888 /* The clocks have to be on to load the palette. */
3889 if (!crtc->enabled || !intel_crtc->active)
3890 return;
3891
3892 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3893 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3894 assert_dsi_pll_enabled(dev_priv);
3895 else
3896 assert_pll_enabled(dev_priv, pipe);
3897 }
3898
3899 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05303900 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03003901 palreg = LGC_PALETTE(pipe);
3902
3903 /* Workaround : Do not read or write the pipe palette/gamma data while
3904 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3905 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003906 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003907 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3908 GAMMA_MODE_MODE_SPLIT)) {
3909 hsw_disable_ips(intel_crtc);
3910 reenable_ips = true;
3911 }
3912
3913 for (i = 0; i < 256; i++) {
3914 I915_WRITE(palreg + 4 * i,
3915 (intel_crtc->lut_r[i] << 16) |
3916 (intel_crtc->lut_g[i] << 8) |
3917 intel_crtc->lut_b[i]);
3918 }
3919
3920 if (reenable_ips)
3921 hsw_enable_ips(intel_crtc);
3922}
3923
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003924static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3925{
3926 if (!enable && intel_crtc->overlay) {
3927 struct drm_device *dev = intel_crtc->base.dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929
3930 mutex_lock(&dev->struct_mutex);
3931 dev_priv->mm.interruptible = false;
3932 (void) intel_overlay_switch_off(intel_crtc->overlay);
3933 dev_priv->mm.interruptible = true;
3934 mutex_unlock(&dev->struct_mutex);
3935 }
3936
3937 /* Let userspace switch the overlay on again. In most cases userspace
3938 * has to recompute where to put it anyway.
3939 */
3940}
3941
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003942static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003943{
3944 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3946 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003947
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003948 drm_vblank_on(dev, pipe);
3949
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03003950 intel_enable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003951 intel_enable_planes(crtc);
3952 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003953 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003954
3955 hsw_enable_ips(intel_crtc);
3956
3957 mutex_lock(&dev->struct_mutex);
3958 intel_update_fbc(dev);
3959 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02003960
3961 /*
3962 * FIXME: Once we grow proper nuclear flip support out of this we need
3963 * to compute the mask of flip planes precisely. For the time being
3964 * consider this a flip from a NULL plane.
3965 */
3966 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003967}
3968
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003969static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003970{
3971 struct drm_device *dev = crtc->dev;
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974 int pipe = intel_crtc->pipe;
3975 int plane = intel_crtc->plane;
3976
3977 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003978
3979 if (dev_priv->fbc.plane == plane)
3980 intel_disable_fbc(dev);
3981
3982 hsw_disable_ips(intel_crtc);
3983
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003984 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003985 intel_crtc_update_cursor(crtc, false);
3986 intel_disable_planes(crtc);
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03003987 intel_disable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003988
Daniel Vetterf99d7062014-06-19 16:01:59 +02003989 /*
3990 * FIXME: Once we grow proper nuclear flip support out of this we need
3991 * to compute the mask of flip planes precisely. For the time being
3992 * consider this a flip to a NULL plane.
3993 */
3994 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3995
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003996 drm_vblank_off(dev, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003997}
3998
Jesse Barnesf67a5592011-01-05 10:31:48 -08003999static void ironlake_crtc_enable(struct drm_crtc *crtc)
4000{
4001 struct drm_device *dev = crtc->dev;
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004004 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004005 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004006
Daniel Vetter08a48462012-07-02 11:43:47 +02004007 WARN_ON(!crtc->enabled);
4008
Jesse Barnesf67a5592011-01-05 10:31:48 -08004009 if (intel_crtc->active)
4010 return;
4011
Daniel Vetterb14b1052014-04-24 23:55:13 +02004012 if (intel_crtc->config.has_pch_encoder)
4013 intel_prepare_shared_dpll(intel_crtc);
4014
Daniel Vetter29407aa2014-04-24 23:55:08 +02004015 if (intel_crtc->config.has_dp_encoder)
4016 intel_dp_set_m_n(intel_crtc);
4017
4018 intel_set_pipe_timings(intel_crtc);
4019
4020 if (intel_crtc->config.has_pch_encoder) {
4021 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004022 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004023 }
4024
4025 ironlake_set_pipeconf(crtc);
4026
Jesse Barnesf67a5592011-01-05 10:31:48 -08004027 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004028
4029 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4030 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4031
Daniel Vetterf6736a12013-06-05 13:34:30 +02004032 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004033 if (encoder->pre_enable)
4034 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004035
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004036 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004037 /* Note: FDI PLL enabling _must_ be done before we enable the
4038 * cpu pipes, hence this is separate from all the other fdi/pch
4039 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004040 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004041 } else {
4042 assert_fdi_tx_disabled(dev_priv, pipe);
4043 assert_fdi_rx_disabled(dev_priv, pipe);
4044 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004045
Jesse Barnesb074cec2013-04-25 12:55:02 -07004046 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004047
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004048 /*
4049 * On ILK+ LUT must be loaded before the pipe is running but with
4050 * clocks enabled
4051 */
4052 intel_crtc_load_lut(crtc);
4053
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004054 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004055 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004056
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004057 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004058 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004059
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004060 for_each_encoder_on_crtc(dev, crtc, encoder)
4061 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004062
4063 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004064 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004065
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004066 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004067}
4068
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004069/* IPS only exists on ULT machines and is tied to pipe A. */
4070static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4071{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004072 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004073}
4074
Paulo Zanonie4916942013-09-20 16:21:19 -03004075/*
4076 * This implements the workaround described in the "notes" section of the mode
4077 * set sequence documentation. When going from no pipes or single pipe to
4078 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4079 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4080 */
4081static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4082{
4083 struct drm_device *dev = crtc->base.dev;
4084 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4085
4086 /* We want to get the other_active_crtc only if there's only 1 other
4087 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004088 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004089 if (!crtc_it->active || crtc_it == crtc)
4090 continue;
4091
4092 if (other_active_crtc)
4093 return;
4094
4095 other_active_crtc = crtc_it;
4096 }
4097 if (!other_active_crtc)
4098 return;
4099
4100 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4101 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4102}
4103
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004104static void haswell_crtc_enable(struct drm_crtc *crtc)
4105{
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109 struct intel_encoder *encoder;
4110 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004111
4112 WARN_ON(!crtc->enabled);
4113
4114 if (intel_crtc->active)
4115 return;
4116
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004117 if (intel_crtc_to_shared_dpll(intel_crtc))
4118 intel_enable_shared_dpll(intel_crtc);
4119
Daniel Vetter229fca92014-04-24 23:55:09 +02004120 if (intel_crtc->config.has_dp_encoder)
4121 intel_dp_set_m_n(intel_crtc);
4122
4123 intel_set_pipe_timings(intel_crtc);
4124
4125 if (intel_crtc->config.has_pch_encoder) {
4126 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004127 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004128 }
4129
4130 haswell_set_pipeconf(crtc);
4131
4132 intel_set_pipe_csc(crtc);
4133
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004134 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004135
4136 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004137 for_each_encoder_on_crtc(dev, crtc, encoder)
4138 if (encoder->pre_enable)
4139 encoder->pre_enable(encoder);
4140
Imre Deak4fe94672014-06-25 22:01:49 +03004141 if (intel_crtc->config.has_pch_encoder) {
4142 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4143 dev_priv->display.fdi_link_train(crtc);
4144 }
4145
Paulo Zanoni1f544382012-10-24 11:32:00 -02004146 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004147
Jesse Barnesb074cec2013-04-25 12:55:02 -07004148 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004149
4150 /*
4151 * On ILK+ LUT must be loaded before the pipe is running but with
4152 * clocks enabled
4153 */
4154 intel_crtc_load_lut(crtc);
4155
Paulo Zanoni1f544382012-10-24 11:32:00 -02004156 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004157 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004158
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004159 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004160 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004161
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004162 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004163 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004164
Dave Airlie0e32b392014-05-02 14:02:48 +10004165 if (intel_crtc->config.dp_encoder_is_mst)
4166 intel_ddi_set_vc_payload_alloc(crtc, true);
4167
Jani Nikula8807e552013-08-30 19:40:32 +03004168 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004169 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004170 intel_opregion_notify_encoder(encoder, true);
4171 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004172
Paulo Zanonie4916942013-09-20 16:21:19 -03004173 /* If we change the relative order between pipe/planes enabling, we need
4174 * to change the workaround. */
4175 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004176 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004177}
4178
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004179static void ironlake_pfit_disable(struct intel_crtc *crtc)
4180{
4181 struct drm_device *dev = crtc->base.dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 int pipe = crtc->pipe;
4184
4185 /* To avoid upsetting the power well on haswell only disable the pfit if
4186 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004187 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004188 I915_WRITE(PF_CTL(pipe), 0);
4189 I915_WRITE(PF_WIN_POS(pipe), 0);
4190 I915_WRITE(PF_WIN_SZ(pipe), 0);
4191 }
4192}
4193
Jesse Barnes6be4a602010-09-10 10:26:01 -07004194static void ironlake_crtc_disable(struct drm_crtc *crtc)
4195{
4196 struct drm_device *dev = crtc->dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004199 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004200 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004201 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004202
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004203 if (!intel_crtc->active)
4204 return;
4205
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004206 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004207
Daniel Vetterea9d7582012-07-10 10:42:52 +02004208 for_each_encoder_on_crtc(dev, crtc, encoder)
4209 encoder->disable(encoder);
4210
Daniel Vetterd925c592013-06-05 13:34:04 +02004211 if (intel_crtc->config.has_pch_encoder)
4212 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4213
Jesse Barnesb24e7172011-01-04 15:09:30 -08004214 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004215
Dave Airlie0e32b392014-05-02 14:02:48 +10004216 if (intel_crtc->config.dp_encoder_is_mst)
4217 intel_ddi_set_vc_payload_alloc(crtc, false);
4218
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004219 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004220
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004221 for_each_encoder_on_crtc(dev, crtc, encoder)
4222 if (encoder->post_disable)
4223 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004224
Daniel Vetterd925c592013-06-05 13:34:04 +02004225 if (intel_crtc->config.has_pch_encoder) {
4226 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004227
Daniel Vetterd925c592013-06-05 13:34:04 +02004228 ironlake_disable_pch_transcoder(dev_priv, pipe);
4229 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004230
Daniel Vetterd925c592013-06-05 13:34:04 +02004231 if (HAS_PCH_CPT(dev)) {
4232 /* disable TRANS_DP_CTL */
4233 reg = TRANS_DP_CTL(pipe);
4234 temp = I915_READ(reg);
4235 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4236 TRANS_DP_PORT_SEL_MASK);
4237 temp |= TRANS_DP_PORT_SEL_NONE;
4238 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004239
Daniel Vetterd925c592013-06-05 13:34:04 +02004240 /* disable DPLL_SEL */
4241 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004242 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004243 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004244 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004245
4246 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004247 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004248
4249 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004250 }
4251
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004252 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004253 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004254
4255 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004256 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004257 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004258}
4259
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004260static void haswell_crtc_disable(struct drm_crtc *crtc)
4261{
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 struct intel_encoder *encoder;
4266 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004267 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004268
4269 if (!intel_crtc->active)
4270 return;
4271
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004272 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004273
Jani Nikula8807e552013-08-30 19:40:32 +03004274 for_each_encoder_on_crtc(dev, crtc, encoder) {
4275 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004276 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004277 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004278
Paulo Zanoni86642812013-04-12 17:57:57 -03004279 if (intel_crtc->config.has_pch_encoder)
4280 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004281 intel_disable_pipe(dev_priv, pipe);
4282
Paulo Zanoniad80a812012-10-24 16:06:19 -02004283 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004284
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004285 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004286
Paulo Zanoni1f544382012-10-24 11:32:00 -02004287 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004288
Daniel Vetter88adfff2013-03-28 10:42:01 +01004289 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004290 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004291 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004292 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004293 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004294
Imre Deak97b040a2014-06-25 22:01:50 +03004295 for_each_encoder_on_crtc(dev, crtc, encoder)
4296 if (encoder->post_disable)
4297 encoder->post_disable(encoder);
4298
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004299 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004300 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004301
4302 mutex_lock(&dev->struct_mutex);
4303 intel_update_fbc(dev);
4304 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004305
4306 if (intel_crtc_to_shared_dpll(intel_crtc))
4307 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004308}
4309
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004310static void ironlake_crtc_off(struct drm_crtc *crtc)
4311{
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004313 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004314}
4315
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004316
Jesse Barnes2dd24552013-04-25 12:55:01 -07004317static void i9xx_pfit_enable(struct intel_crtc *crtc)
4318{
4319 struct drm_device *dev = crtc->base.dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc_config *pipe_config = &crtc->config;
4322
Daniel Vetter328d8e82013-05-08 10:36:31 +02004323 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004324 return;
4325
Daniel Vetterc0b03412013-05-28 12:05:54 +02004326 /*
4327 * The panel fitter should only be adjusted whilst the pipe is disabled,
4328 * according to register description and PRM.
4329 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004330 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4331 assert_pipe_disabled(dev_priv, crtc->pipe);
4332
Jesse Barnesb074cec2013-04-25 12:55:02 -07004333 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4334 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004335
4336 /* Border color in case we don't scale up to the full screen. Black by
4337 * default, change to something else for debugging. */
4338 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004339}
4340
Dave Airlied05410f2014-06-05 13:22:59 +10004341static enum intel_display_power_domain port_to_power_domain(enum port port)
4342{
4343 switch (port) {
4344 case PORT_A:
4345 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4346 case PORT_B:
4347 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4348 case PORT_C:
4349 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4350 case PORT_D:
4351 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4352 default:
4353 WARN_ON_ONCE(1);
4354 return POWER_DOMAIN_PORT_OTHER;
4355 }
4356}
4357
Imre Deak77d22dc2014-03-05 16:20:52 +02004358#define for_each_power_domain(domain, mask) \
4359 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4360 if ((1 << (domain)) & (mask))
4361
Imre Deak319be8a2014-03-04 19:22:57 +02004362enum intel_display_power_domain
4363intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004364{
Imre Deak319be8a2014-03-04 19:22:57 +02004365 struct drm_device *dev = intel_encoder->base.dev;
4366 struct intel_digital_port *intel_dig_port;
4367
4368 switch (intel_encoder->type) {
4369 case INTEL_OUTPUT_UNKNOWN:
4370 /* Only DDI platforms should ever use this output type */
4371 WARN_ON_ONCE(!HAS_DDI(dev));
4372 case INTEL_OUTPUT_DISPLAYPORT:
4373 case INTEL_OUTPUT_HDMI:
4374 case INTEL_OUTPUT_EDP:
4375 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10004376 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10004377 case INTEL_OUTPUT_DP_MST:
4378 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4379 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02004380 case INTEL_OUTPUT_ANALOG:
4381 return POWER_DOMAIN_PORT_CRT;
4382 case INTEL_OUTPUT_DSI:
4383 return POWER_DOMAIN_PORT_DSI;
4384 default:
4385 return POWER_DOMAIN_PORT_OTHER;
4386 }
4387}
4388
4389static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4390{
4391 struct drm_device *dev = crtc->dev;
4392 struct intel_encoder *intel_encoder;
4393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4394 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004395 unsigned long mask;
4396 enum transcoder transcoder;
4397
4398 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4399
4400 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4401 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004402 if (intel_crtc->config.pch_pfit.enabled ||
4403 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004404 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4405
Imre Deak319be8a2014-03-04 19:22:57 +02004406 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4407 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4408
Imre Deak77d22dc2014-03-05 16:20:52 +02004409 return mask;
4410}
4411
4412void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4413 bool enable)
4414{
4415 if (dev_priv->power_domains.init_power_on == enable)
4416 return;
4417
4418 if (enable)
4419 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4420 else
4421 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4422
4423 dev_priv->power_domains.init_power_on = enable;
4424}
4425
4426static void modeset_update_crtc_power_domains(struct drm_device *dev)
4427{
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4429 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4430 struct intel_crtc *crtc;
4431
4432 /*
4433 * First get all needed power domains, then put all unneeded, to avoid
4434 * any unnecessary toggling of the power wells.
4435 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004436 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004437 enum intel_display_power_domain domain;
4438
4439 if (!crtc->base.enabled)
4440 continue;
4441
Imre Deak319be8a2014-03-04 19:22:57 +02004442 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004443
4444 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4445 intel_display_power_get(dev_priv, domain);
4446 }
4447
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004448 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004449 enum intel_display_power_domain domain;
4450
4451 for_each_power_domain(domain, crtc->enabled_power_domains)
4452 intel_display_power_put(dev_priv, domain);
4453
4454 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4455 }
4456
4457 intel_display_set_init_power(dev_priv, false);
4458}
4459
Ville Syrjälädfcab172014-06-13 13:37:47 +03004460/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004461static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004462{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004463 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004464
Jesse Barnes586f49d2013-11-04 16:06:59 -08004465 /* Obtain SKU information */
4466 mutex_lock(&dev_priv->dpio_lock);
4467 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4468 CCK_FUSE_HPLL_FREQ_MASK;
4469 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004470
Ville Syrjälädfcab172014-06-13 13:37:47 +03004471 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004472}
4473
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004474static void vlv_update_cdclk(struct drm_device *dev)
4475{
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477
4478 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4479 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4480 dev_priv->vlv_cdclk_freq);
4481
4482 /*
4483 * Program the gmbus_freq based on the cdclk frequency.
4484 * BSpec erroneously claims we should aim for 4MHz, but
4485 * in fact 1MHz is the correct frequency.
4486 */
4487 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4488}
4489
Jesse Barnes30a970c2013-11-04 13:48:12 -08004490/* Adjust CDclk dividers to allow high res or save power if possible */
4491static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4492{
4493 struct drm_i915_private *dev_priv = dev->dev_private;
4494 u32 val, cmd;
4495
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004496 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004497
Ville Syrjälädfcab172014-06-13 13:37:47 +03004498 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004499 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004500 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004501 cmd = 1;
4502 else
4503 cmd = 0;
4504
4505 mutex_lock(&dev_priv->rps.hw_lock);
4506 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4507 val &= ~DSPFREQGUAR_MASK;
4508 val |= (cmd << DSPFREQGUAR_SHIFT);
4509 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4510 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4511 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4512 50)) {
4513 DRM_ERROR("timed out waiting for CDclk change\n");
4514 }
4515 mutex_unlock(&dev_priv->rps.hw_lock);
4516
Ville Syrjälädfcab172014-06-13 13:37:47 +03004517 if (cdclk == 400000) {
Jesse Barnes30a970c2013-11-04 13:48:12 -08004518 u32 divider, vco;
4519
4520 vco = valleyview_get_vco(dev_priv);
Ville Syrjälädfcab172014-06-13 13:37:47 +03004521 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004522
4523 mutex_lock(&dev_priv->dpio_lock);
4524 /* adjust cdclk divider */
4525 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004526 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004527 val |= divider;
4528 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004529
4530 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4531 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4532 50))
4533 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004534 mutex_unlock(&dev_priv->dpio_lock);
4535 }
4536
4537 mutex_lock(&dev_priv->dpio_lock);
4538 /* adjust self-refresh exit latency value */
4539 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4540 val &= ~0x7f;
4541
4542 /*
4543 * For high bandwidth configs, we set a higher latency in the bunit
4544 * so that the core display fetch happens in time to avoid underruns.
4545 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004546 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004547 val |= 4500 / 250; /* 4.5 usec */
4548 else
4549 val |= 3000 / 250; /* 3.0 usec */
4550 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4551 mutex_unlock(&dev_priv->dpio_lock);
4552
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004553 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004554}
4555
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004556static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4557{
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 u32 val, cmd;
4560
4561 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4562
4563 switch (cdclk) {
4564 case 400000:
4565 cmd = 3;
4566 break;
4567 case 333333:
4568 case 320000:
4569 cmd = 2;
4570 break;
4571 case 266667:
4572 cmd = 1;
4573 break;
4574 case 200000:
4575 cmd = 0;
4576 break;
4577 default:
4578 WARN_ON(1);
4579 return;
4580 }
4581
4582 mutex_lock(&dev_priv->rps.hw_lock);
4583 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4584 val &= ~DSPFREQGUAR_MASK_CHV;
4585 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4586 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4587 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4588 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4589 50)) {
4590 DRM_ERROR("timed out waiting for CDclk change\n");
4591 }
4592 mutex_unlock(&dev_priv->rps.hw_lock);
4593
4594 vlv_update_cdclk(dev);
4595}
4596
Jesse Barnes30a970c2013-11-04 13:48:12 -08004597static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4598 int max_pixclk)
4599{
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004600 int vco = valleyview_get_vco(dev_priv);
4601 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4602
Ville Syrjäläd49a3402014-06-28 02:03:58 +03004603 /* FIXME: Punit isn't quite ready yet */
4604 if (IS_CHERRYVIEW(dev_priv->dev))
4605 return 400000;
4606
Jesse Barnes30a970c2013-11-04 13:48:12 -08004607 /*
4608 * Really only a few cases to deal with, as only 4 CDclks are supported:
4609 * 200MHz
4610 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004611 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004612 * 400MHz
4613 * So we check to see whether we're above 90% of the lower bin and
4614 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004615 *
4616 * We seem to get an unstable or solid color picture at 200MHz.
4617 * Not sure what's wrong. For now use 200MHz only when all pipes
4618 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004619 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004620 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004621 return 400000;
4622 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004623 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004624 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004625 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004626 else
4627 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004628}
4629
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004630/* compute the max pixel clock for new configuration */
4631static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004632{
4633 struct drm_device *dev = dev_priv->dev;
4634 struct intel_crtc *intel_crtc;
4635 int max_pixclk = 0;
4636
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004637 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004638 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004639 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004640 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004641 }
4642
4643 return max_pixclk;
4644}
4645
4646static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004647 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004648{
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004651 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004652
Imre Deakd60c4472014-03-27 17:45:10 +02004653 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4654 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004655 return;
4656
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004657 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004658 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004659 if (intel_crtc->base.enabled)
4660 *prepare_pipes |= (1 << intel_crtc->pipe);
4661}
4662
4663static void valleyview_modeset_global_resources(struct drm_device *dev)
4664{
4665 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004666 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004667 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4668
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004669 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4670 if (IS_CHERRYVIEW(dev))
4671 cherryview_set_cdclk(dev, req_cdclk);
4672 else
4673 valleyview_set_cdclk(dev, req_cdclk);
4674 }
4675
Imre Deak77961eb2014-03-05 16:20:56 +02004676 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004677}
4678
Jesse Barnes89b667f2013-04-18 14:51:36 -07004679static void valleyview_crtc_enable(struct drm_crtc *crtc)
4680{
4681 struct drm_device *dev = crtc->dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4683 struct intel_encoder *encoder;
4684 int pipe = intel_crtc->pipe;
Jani Nikula23538ef2013-08-27 15:12:22 +03004685 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004686
4687 WARN_ON(!crtc->enabled);
4688
4689 if (intel_crtc->active)
4690 return;
4691
Shobhit Kumar8525a232014-06-25 12:20:39 +05304692 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4693
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004694 if (!is_dsi) {
4695 if (IS_CHERRYVIEW(dev))
4696 chv_prepare_pll(intel_crtc);
4697 else
4698 vlv_prepare_pll(intel_crtc);
4699 }
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004700
Daniel Vetter5b18e572014-04-24 23:55:06 +02004701 if (intel_crtc->config.has_dp_encoder)
4702 intel_dp_set_m_n(intel_crtc);
4703
4704 intel_set_pipe_timings(intel_crtc);
4705
Daniel Vetter5b18e572014-04-24 23:55:06 +02004706 i9xx_set_pipeconf(intel_crtc);
4707
Jesse Barnes89b667f2013-04-18 14:51:36 -07004708 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004709
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004710 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4711
Jesse Barnes89b667f2013-04-18 14:51:36 -07004712 for_each_encoder_on_crtc(dev, crtc, encoder)
4713 if (encoder->pre_pll_enable)
4714 encoder->pre_pll_enable(encoder);
4715
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004716 if (!is_dsi) {
4717 if (IS_CHERRYVIEW(dev))
4718 chv_enable_pll(intel_crtc);
4719 else
4720 vlv_enable_pll(intel_crtc);
4721 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004722
4723 for_each_encoder_on_crtc(dev, crtc, encoder)
4724 if (encoder->pre_enable)
4725 encoder->pre_enable(encoder);
4726
Jesse Barnes2dd24552013-04-25 12:55:01 -07004727 i9xx_pfit_enable(intel_crtc);
4728
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004729 intel_crtc_load_lut(crtc);
4730
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004731 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004732 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004733
Jani Nikula50049452013-07-30 12:20:32 +03004734 for_each_encoder_on_crtc(dev, crtc, encoder)
4735 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004736
4737 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004738
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004739 /* Underruns don't raise interrupts, so check manually. */
4740 i9xx_check_fifo_underruns(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004741}
4742
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004743static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4744{
4745 struct drm_device *dev = crtc->base.dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747
4748 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4749 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4750}
4751
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004752static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004753{
4754 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08004755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004756 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004757 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004758
Daniel Vetter08a48462012-07-02 11:43:47 +02004759 WARN_ON(!crtc->enabled);
4760
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004761 if (intel_crtc->active)
4762 return;
4763
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004764 i9xx_set_pll_dividers(intel_crtc);
4765
Daniel Vetter5b18e572014-04-24 23:55:06 +02004766 if (intel_crtc->config.has_dp_encoder)
4767 intel_dp_set_m_n(intel_crtc);
4768
4769 intel_set_pipe_timings(intel_crtc);
4770
Daniel Vetter5b18e572014-04-24 23:55:06 +02004771 i9xx_set_pipeconf(intel_crtc);
4772
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004773 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004774
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004775 if (!IS_GEN2(dev))
4776 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4777
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004778 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004779 if (encoder->pre_enable)
4780 encoder->pre_enable(encoder);
4781
Daniel Vetterf6736a12013-06-05 13:34:30 +02004782 i9xx_enable_pll(intel_crtc);
4783
Jesse Barnes2dd24552013-04-25 12:55:01 -07004784 i9xx_pfit_enable(intel_crtc);
4785
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004786 intel_crtc_load_lut(crtc);
4787
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004788 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004789 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004790
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004791 for_each_encoder_on_crtc(dev, crtc, encoder)
4792 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004793
4794 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004795
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004796 /*
4797 * Gen2 reports pipe underruns whenever all planes are disabled.
4798 * So don't enable underrun reporting before at least some planes
4799 * are enabled.
4800 * FIXME: Need to fix the logic to work when we turn off all planes
4801 * but leave the pipe running.
4802 */
4803 if (IS_GEN2(dev))
4804 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4805
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004806 /* Underruns don't raise interrupts, so check manually. */
4807 i9xx_check_fifo_underruns(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004808}
4809
Daniel Vetter87476d62013-04-11 16:29:06 +02004810static void i9xx_pfit_disable(struct intel_crtc *crtc)
4811{
4812 struct drm_device *dev = crtc->base.dev;
4813 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004814
4815 if (!crtc->config.gmch_pfit.control)
4816 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004817
4818 assert_pipe_disabled(dev_priv, crtc->pipe);
4819
Daniel Vetter328d8e82013-05-08 10:36:31 +02004820 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4821 I915_READ(PFIT_CONTROL));
4822 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004823}
4824
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004825static void i9xx_crtc_disable(struct drm_crtc *crtc)
4826{
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004830 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004831 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004832
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004833 if (!intel_crtc->active)
4834 return;
4835
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004836 /*
4837 * Gen2 reports pipe underruns whenever all planes are disabled.
4838 * So diasble underrun reporting before all the planes get disabled.
4839 * FIXME: Need to fix the logic to work when we turn off all planes
4840 * but leave the pipe running.
4841 */
4842 if (IS_GEN2(dev))
4843 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4844
Imre Deak564ed192014-06-13 14:54:21 +03004845 /*
4846 * Vblank time updates from the shadow to live plane control register
4847 * are blocked if the memory self-refresh mode is active at that
4848 * moment. So to make sure the plane gets truly disabled, disable
4849 * first the self-refresh mode. The self-refresh enable bit in turn
4850 * will be checked/applied by the HW only at the next frame start
4851 * event which is after the vblank start event, so we need to have a
4852 * wait-for-vblank between disabling the plane and the pipe.
4853 */
4854 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004855 intel_crtc_disable_planes(crtc);
4856
Daniel Vetterea9d7582012-07-10 10:42:52 +02004857 for_each_encoder_on_crtc(dev, crtc, encoder)
4858 encoder->disable(encoder);
4859
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004860 /*
4861 * On gen2 planes are double buffered but the pipe isn't, so we must
4862 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03004863 * We also need to wait on all gmch platforms because of the
4864 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004865 */
Imre Deak564ed192014-06-13 14:54:21 +03004866 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004867
Jesse Barnesb24e7172011-01-04 15:09:30 -08004868 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004869
Daniel Vetter87476d62013-04-11 16:29:06 +02004870 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004871
Jesse Barnes89b667f2013-04-18 14:51:36 -07004872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->post_disable)
4874 encoder->post_disable(encoder);
4875
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004876 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4877 if (IS_CHERRYVIEW(dev))
4878 chv_disable_pll(dev_priv, pipe);
4879 else if (IS_VALLEYVIEW(dev))
4880 vlv_disable_pll(dev_priv, pipe);
4881 else
4882 i9xx_disable_pll(dev_priv, pipe);
4883 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004884
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004885 if (!IS_GEN2(dev))
4886 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4887
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004888 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004889 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004890
Daniel Vetterefa96242014-04-24 23:55:02 +02004891 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004892 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004893 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004894}
4895
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004896static void i9xx_crtc_off(struct drm_crtc *crtc)
4897{
4898}
4899
Daniel Vetter976f8a22012-07-08 22:34:21 +02004900static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4901 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004902{
4903 struct drm_device *dev = crtc->dev;
4904 struct drm_i915_master_private *master_priv;
4905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4906 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004907
4908 if (!dev->primary->master)
4909 return;
4910
4911 master_priv = dev->primary->master->driver_priv;
4912 if (!master_priv->sarea_priv)
4913 return;
4914
Jesse Barnes79e53942008-11-07 14:24:08 -08004915 switch (pipe) {
4916 case 0:
4917 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4918 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4919 break;
4920 case 1:
4921 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4922 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4923 break;
4924 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004925 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004926 break;
4927 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004928}
4929
Borun Fub04c5bd2014-07-12 10:02:27 +05304930/* Master function to enable/disable CRTC and corresponding power wells */
4931void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004932{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004933 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004934 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004936 enum intel_display_power_domain domain;
4937 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004938
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004939 if (enable) {
4940 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004941 domains = get_crtc_power_domains(crtc);
4942 for_each_power_domain(domain, domains)
4943 intel_display_power_get(dev_priv, domain);
4944 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004945
4946 dev_priv->display.crtc_enable(crtc);
4947 }
4948 } else {
4949 if (intel_crtc->active) {
4950 dev_priv->display.crtc_disable(crtc);
4951
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004952 domains = intel_crtc->enabled_power_domains;
4953 for_each_power_domain(domain, domains)
4954 intel_display_power_put(dev_priv, domain);
4955 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004956 }
4957 }
Borun Fub04c5bd2014-07-12 10:02:27 +05304958}
4959
4960/**
4961 * Sets the power management mode of the pipe and plane.
4962 */
4963void intel_crtc_update_dpms(struct drm_crtc *crtc)
4964{
4965 struct drm_device *dev = crtc->dev;
4966 struct intel_encoder *intel_encoder;
4967 bool enable = false;
4968
4969 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4970 enable |= intel_encoder->connectors_active;
4971
4972 intel_crtc_control(crtc, enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004973
4974 intel_crtc_update_sarea(crtc, enable);
4975}
4976
Daniel Vetter976f8a22012-07-08 22:34:21 +02004977static void intel_crtc_disable(struct drm_crtc *crtc)
4978{
4979 struct drm_device *dev = crtc->dev;
4980 struct drm_connector *connector;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07004982 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02004983 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004984
4985 /* crtc should still be enabled when we disable it. */
4986 WARN_ON(!crtc->enabled);
4987
4988 dev_priv->display.crtc_disable(crtc);
4989 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004990 dev_priv->display.off(crtc);
4991
Matt Roperf4510a22014-04-01 15:22:40 -07004992 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004993 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02004994 intel_unpin_fb_obj(old_obj);
4995 i915_gem_track_fb(old_obj, NULL,
4996 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01004997 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004998 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004999 }
5000
5001 /* Update computed state. */
5002 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5003 if (!connector->encoder || !connector->encoder->crtc)
5004 continue;
5005
5006 if (connector->encoder->crtc != crtc)
5007 continue;
5008
5009 connector->dpms = DRM_MODE_DPMS_OFF;
5010 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01005011 }
5012}
5013
Chris Wilsonea5b2132010-08-04 13:50:23 +01005014void intel_encoder_destroy(struct drm_encoder *encoder)
5015{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005016 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01005017
Chris Wilsonea5b2132010-08-04 13:50:23 +01005018 drm_encoder_cleanup(encoder);
5019 kfree(intel_encoder);
5020}
5021
Damien Lespiau92373292013-08-08 22:28:57 +01005022/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005023 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5024 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01005025static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005026{
5027 if (mode == DRM_MODE_DPMS_ON) {
5028 encoder->connectors_active = true;
5029
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005030 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005031 } else {
5032 encoder->connectors_active = false;
5033
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005034 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005035 }
5036}
5037
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005038/* Cross check the actual hw state with our own modeset state tracking (and it's
5039 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02005040static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005041{
5042 if (connector->get_hw_state(connector)) {
5043 struct intel_encoder *encoder = connector->encoder;
5044 struct drm_crtc *crtc;
5045 bool encoder_enabled;
5046 enum pipe pipe;
5047
5048 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5049 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03005050 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005051
Dave Airlie0e32b392014-05-02 14:02:48 +10005052 /* there is no real hw state for MST connectors */
5053 if (connector->mst_port)
5054 return;
5055
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005056 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5057 "wrong connector dpms state\n");
5058 WARN(connector->base.encoder != &encoder->base,
5059 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005060
Dave Airlie36cd7442014-05-02 13:44:18 +10005061 if (encoder) {
5062 WARN(!encoder->connectors_active,
5063 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005064
Dave Airlie36cd7442014-05-02 13:44:18 +10005065 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5066 WARN(!encoder_enabled, "encoder not enabled\n");
5067 if (WARN_ON(!encoder->base.crtc))
5068 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005069
Dave Airlie36cd7442014-05-02 13:44:18 +10005070 crtc = encoder->base.crtc;
5071
5072 WARN(!crtc->enabled, "crtc not enabled\n");
5073 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5074 WARN(pipe != to_intel_crtc(crtc)->pipe,
5075 "encoder active on the wrong pipe\n");
5076 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005077 }
5078}
5079
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005080/* Even simpler default implementation, if there's really no special case to
5081 * consider. */
5082void intel_connector_dpms(struct drm_connector *connector, int mode)
5083{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005084 /* All the simple cases only support two dpms states. */
5085 if (mode != DRM_MODE_DPMS_ON)
5086 mode = DRM_MODE_DPMS_OFF;
5087
5088 if (mode == connector->dpms)
5089 return;
5090
5091 connector->dpms = mode;
5092
5093 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005094 if (connector->encoder)
5095 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005096
Daniel Vetterb9805142012-08-31 17:37:33 +02005097 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005098}
5099
Daniel Vetterf0947c32012-07-02 13:10:34 +02005100/* Simple connector->get_hw_state implementation for encoders that support only
5101 * one connector and no cloning and hence the encoder state determines the state
5102 * of the connector. */
5103bool intel_connector_get_hw_state(struct intel_connector *connector)
5104{
Daniel Vetter24929352012-07-02 20:28:59 +02005105 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005106 struct intel_encoder *encoder = connector->encoder;
5107
5108 return encoder->get_hw_state(encoder, &pipe);
5109}
5110
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005111static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5112 struct intel_crtc_config *pipe_config)
5113{
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc *pipe_B_crtc =
5116 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5117
5118 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5119 pipe_name(pipe), pipe_config->fdi_lanes);
5120 if (pipe_config->fdi_lanes > 4) {
5121 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5122 pipe_name(pipe), pipe_config->fdi_lanes);
5123 return false;
5124 }
5125
Paulo Zanonibafb6552013-11-02 21:07:44 -07005126 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005127 if (pipe_config->fdi_lanes > 2) {
5128 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5129 pipe_config->fdi_lanes);
5130 return false;
5131 } else {
5132 return true;
5133 }
5134 }
5135
5136 if (INTEL_INFO(dev)->num_pipes == 2)
5137 return true;
5138
5139 /* Ivybridge 3 pipe is really complicated */
5140 switch (pipe) {
5141 case PIPE_A:
5142 return true;
5143 case PIPE_B:
5144 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5145 pipe_config->fdi_lanes > 2) {
5146 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5147 pipe_name(pipe), pipe_config->fdi_lanes);
5148 return false;
5149 }
5150 return true;
5151 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005152 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005153 pipe_B_crtc->config.fdi_lanes <= 2) {
5154 if (pipe_config->fdi_lanes > 2) {
5155 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5156 pipe_name(pipe), pipe_config->fdi_lanes);
5157 return false;
5158 }
5159 } else {
5160 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5161 return false;
5162 }
5163 return true;
5164 default:
5165 BUG();
5166 }
5167}
5168
Daniel Vettere29c22c2013-02-21 00:00:16 +01005169#define RETRY 1
5170static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5171 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005172{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005173 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005174 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005175 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005176 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005177
Daniel Vettere29c22c2013-02-21 00:00:16 +01005178retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005179 /* FDI is a binary signal running at ~2.7GHz, encoding
5180 * each output octet as 10 bits. The actual frequency
5181 * is stored as a divider into a 100MHz clock, and the
5182 * mode pixel clock is stored in units of 1KHz.
5183 * Hence the bw of each lane in terms of the mode signal
5184 * is:
5185 */
5186 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5187
Damien Lespiau241bfc32013-09-25 16:45:37 +01005188 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005189
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005190 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005191 pipe_config->pipe_bpp);
5192
5193 pipe_config->fdi_lanes = lane;
5194
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005195 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005196 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005197
Daniel Vettere29c22c2013-02-21 00:00:16 +01005198 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5199 intel_crtc->pipe, pipe_config);
5200 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5201 pipe_config->pipe_bpp -= 2*3;
5202 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5203 pipe_config->pipe_bpp);
5204 needs_recompute = true;
5205 pipe_config->bw_constrained = true;
5206
5207 goto retry;
5208 }
5209
5210 if (needs_recompute)
5211 return RETRY;
5212
5213 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005214}
5215
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005216static void hsw_compute_ips_config(struct intel_crtc *crtc,
5217 struct intel_crtc_config *pipe_config)
5218{
Jani Nikulad330a952014-01-21 11:24:25 +02005219 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005220 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005221 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005222}
5223
Daniel Vettera43f6e02013-06-07 23:10:32 +02005224static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005225 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005226{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005227 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005228 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005229
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005230 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005231 if (INTEL_INFO(dev)->gen < 4) {
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233 int clock_limit =
5234 dev_priv->display.get_display_clock_speed(dev);
5235
5236 /*
5237 * Enable pixel doubling when the dot clock
5238 * is > 90% of the (display) core speed.
5239 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005240 * GDG double wide on either pipe,
5241 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005242 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005243 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005244 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005245 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005246 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005247 }
5248
Damien Lespiau241bfc32013-09-25 16:45:37 +01005249 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005250 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005251 }
Chris Wilson89749352010-09-12 18:25:19 +01005252
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005253 /*
5254 * Pipe horizontal size must be even in:
5255 * - DVO ganged mode
5256 * - LVDS dual channel mode
5257 * - Double wide pipe
5258 */
5259 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5260 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5261 pipe_config->pipe_src_w &= ~1;
5262
Damien Lespiau8693a822013-05-03 18:48:11 +01005263 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5264 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005265 */
5266 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5267 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005268 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005269
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005270 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005271 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005272 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005273 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5274 * for lvds. */
5275 pipe_config->pipe_bpp = 8*3;
5276 }
5277
Damien Lespiauf5adf942013-06-24 18:29:34 +01005278 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005279 hsw_compute_ips_config(crtc, pipe_config);
5280
Daniel Vetter12030432014-06-25 22:02:00 +03005281 /*
5282 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5283 * old clock survives for now.
5284 */
5285 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005286 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005287
Daniel Vetter877d48d2013-04-19 11:24:43 +02005288 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005289 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005290
Daniel Vettere29c22c2013-02-21 00:00:16 +01005291 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005292}
5293
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005294static int valleyview_get_display_clock_speed(struct drm_device *dev)
5295{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005296 struct drm_i915_private *dev_priv = dev->dev_private;
5297 int vco = valleyview_get_vco(dev_priv);
5298 u32 val;
5299 int divider;
5300
Ville Syrjäläd49a3402014-06-28 02:03:58 +03005301 /* FIXME: Punit isn't quite ready yet */
5302 if (IS_CHERRYVIEW(dev))
5303 return 400000;
5304
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005305 mutex_lock(&dev_priv->dpio_lock);
5306 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5307 mutex_unlock(&dev_priv->dpio_lock);
5308
5309 divider = val & DISPLAY_FREQUENCY_VALUES;
5310
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005311 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5312 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5313 "cdclk change in progress\n");
5314
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005315 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005316}
5317
Jesse Barnese70236a2009-09-21 10:42:27 -07005318static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005319{
Jesse Barnese70236a2009-09-21 10:42:27 -07005320 return 400000;
5321}
Jesse Barnes79e53942008-11-07 14:24:08 -08005322
Jesse Barnese70236a2009-09-21 10:42:27 -07005323static int i915_get_display_clock_speed(struct drm_device *dev)
5324{
5325 return 333000;
5326}
Jesse Barnes79e53942008-11-07 14:24:08 -08005327
Jesse Barnese70236a2009-09-21 10:42:27 -07005328static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5329{
5330 return 200000;
5331}
Jesse Barnes79e53942008-11-07 14:24:08 -08005332
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005333static int pnv_get_display_clock_speed(struct drm_device *dev)
5334{
5335 u16 gcfgc = 0;
5336
5337 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5338
5339 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5340 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5341 return 267000;
5342 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5343 return 333000;
5344 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5345 return 444000;
5346 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5347 return 200000;
5348 default:
5349 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5350 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5351 return 133000;
5352 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5353 return 167000;
5354 }
5355}
5356
Jesse Barnese70236a2009-09-21 10:42:27 -07005357static int i915gm_get_display_clock_speed(struct drm_device *dev)
5358{
5359 u16 gcfgc = 0;
5360
5361 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5362
5363 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005364 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005365 else {
5366 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5367 case GC_DISPLAY_CLOCK_333_MHZ:
5368 return 333000;
5369 default:
5370 case GC_DISPLAY_CLOCK_190_200_MHZ:
5371 return 190000;
5372 }
5373 }
5374}
Jesse Barnes79e53942008-11-07 14:24:08 -08005375
Jesse Barnese70236a2009-09-21 10:42:27 -07005376static int i865_get_display_clock_speed(struct drm_device *dev)
5377{
5378 return 266000;
5379}
5380
5381static int i855_get_display_clock_speed(struct drm_device *dev)
5382{
5383 u16 hpllcc = 0;
5384 /* Assume that the hardware is in the high speed state. This
5385 * should be the default.
5386 */
5387 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5388 case GC_CLOCK_133_200:
5389 case GC_CLOCK_100_200:
5390 return 200000;
5391 case GC_CLOCK_166_250:
5392 return 250000;
5393 case GC_CLOCK_100_133:
5394 return 133000;
5395 }
5396
5397 /* Shouldn't happen */
5398 return 0;
5399}
5400
5401static int i830_get_display_clock_speed(struct drm_device *dev)
5402{
5403 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005404}
5405
Zhenyu Wang2c072452009-06-05 15:38:42 +08005406static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005407intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005408{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005409 while (*num > DATA_LINK_M_N_MASK ||
5410 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005411 *num >>= 1;
5412 *den >>= 1;
5413 }
5414}
5415
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005416static void compute_m_n(unsigned int m, unsigned int n,
5417 uint32_t *ret_m, uint32_t *ret_n)
5418{
5419 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5420 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5421 intel_reduce_m_n_ratio(ret_m, ret_n);
5422}
5423
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005424void
5425intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5426 int pixel_clock, int link_clock,
5427 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005428{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005429 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005430
5431 compute_m_n(bits_per_pixel * pixel_clock,
5432 link_clock * nlanes * 8,
5433 &m_n->gmch_m, &m_n->gmch_n);
5434
5435 compute_m_n(pixel_clock, link_clock,
5436 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005437}
5438
Chris Wilsona7615032011-01-12 17:04:08 +00005439static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5440{
Jani Nikulad330a952014-01-21 11:24:25 +02005441 if (i915.panel_use_ssc >= 0)
5442 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005443 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005444 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005445}
5446
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005447static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5448{
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 int refclk;
5452
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005453 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005454 refclk = 100000;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005456 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005457 refclk = dev_priv->vbt.lvds_ssc_freq;
5458 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005459 } else if (!IS_GEN2(dev)) {
5460 refclk = 96000;
5461 } else {
5462 refclk = 48000;
5463 }
5464
5465 return refclk;
5466}
5467
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005468static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005469{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005470 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005471}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005472
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005473static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5474{
5475 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005476}
5477
Daniel Vetterf47709a2013-03-28 10:42:02 +01005478static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005479 intel_clock_t *reduced_clock)
5480{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005481 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005482 u32 fp, fp2 = 0;
5483
5484 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005485 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005486 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005487 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005488 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005489 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005490 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005491 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005492 }
5493
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005494 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005495
Daniel Vetterf47709a2013-03-28 10:42:02 +01005496 crtc->lowfreq_avail = false;
5497 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005498 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005499 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005500 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005501 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005502 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005503 }
5504}
5505
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005506static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5507 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005508{
5509 u32 reg_val;
5510
5511 /*
5512 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5513 * and set it to a reasonable value instead.
5514 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005515 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005516 reg_val &= 0xffffff00;
5517 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005518 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005519
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005520 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005521 reg_val &= 0x8cffffff;
5522 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005523 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005524
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005525 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005526 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005527 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005528
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005529 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005530 reg_val &= 0x00ffffff;
5531 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005532 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005533}
5534
Daniel Vetterb5518422013-05-03 11:49:48 +02005535static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5536 struct intel_link_m_n *m_n)
5537{
5538 struct drm_device *dev = crtc->base.dev;
5539 struct drm_i915_private *dev_priv = dev->dev_private;
5540 int pipe = crtc->pipe;
5541
Daniel Vettere3b95f12013-05-03 11:49:49 +02005542 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5543 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5544 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5545 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005546}
5547
5548static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07005549 struct intel_link_m_n *m_n,
5550 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02005551{
5552 struct drm_device *dev = crtc->base.dev;
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 int pipe = crtc->pipe;
5555 enum transcoder transcoder = crtc->config.cpu_transcoder;
5556
5557 if (INTEL_INFO(dev)->gen >= 5) {
5558 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5559 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5560 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5561 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07005562 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5563 * for gen < 8) and if DRRS is supported (to make sure the
5564 * registers are not unnecessarily accessed).
5565 */
5566 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5567 crtc->config.has_drrs) {
5568 I915_WRITE(PIPE_DATA_M2(transcoder),
5569 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5570 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5571 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5572 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5573 }
Daniel Vetterb5518422013-05-03 11:49:48 +02005574 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005575 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5576 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5577 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5578 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005579 }
5580}
5581
Vandana Kannanf769cd22014-08-05 07:51:22 -07005582void intel_dp_set_m_n(struct intel_crtc *crtc)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005583{
5584 if (crtc->config.has_pch_encoder)
5585 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5586 else
Vandana Kannanf769cd22014-08-05 07:51:22 -07005587 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5588 &crtc->config.dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005589}
5590
Daniel Vetterf47709a2013-03-28 10:42:02 +01005591static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005592{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005593 u32 dpll, dpll_md;
5594
5595 /*
5596 * Enable DPIO clock input. We should never disable the reference
5597 * clock for pipe B, since VGA hotplug / manual detection depends
5598 * on it.
5599 */
5600 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5601 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5602 /* We should never disable this, set it here for state tracking */
5603 if (crtc->pipe == PIPE_B)
5604 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5605 dpll |= DPLL_VCO_ENABLE;
5606 crtc->config.dpll_hw_state.dpll = dpll;
5607
5608 dpll_md = (crtc->config.pixel_multiplier - 1)
5609 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5610 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5611}
5612
5613static void vlv_prepare_pll(struct intel_crtc *crtc)
5614{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005615 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005616 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005617 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005618 u32 mdiv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005619 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005620 u32 coreclk, reg_val;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005621
Daniel Vetter09153002012-12-12 14:06:44 +01005622 mutex_lock(&dev_priv->dpio_lock);
5623
Daniel Vetterf47709a2013-03-28 10:42:02 +01005624 bestn = crtc->config.dpll.n;
5625 bestm1 = crtc->config.dpll.m1;
5626 bestm2 = crtc->config.dpll.m2;
5627 bestp1 = crtc->config.dpll.p1;
5628 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005629
Jesse Barnes89b667f2013-04-18 14:51:36 -07005630 /* See eDP HDMI DPIO driver vbios notes doc */
5631
5632 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005633 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005634 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005635
5636 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005637 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005638
5639 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005640 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005641 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005642 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005643
5644 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005645 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005646
5647 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005648 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5649 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5650 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005651 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005652
5653 /*
5654 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5655 * but we don't support that).
5656 * Note: don't use the DAC post divider as it seems unstable.
5657 */
5658 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005660
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005661 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005662 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005663
Jesse Barnes89b667f2013-04-18 14:51:36 -07005664 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005665 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005666 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005667 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005668 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b01202013-07-05 19:21:38 +03005669 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005670 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005671 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005672 0x00d0000f);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005673
Jesse Barnes89b667f2013-04-18 14:51:36 -07005674 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5675 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5676 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005677 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005678 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005679 0x0df40000);
5680 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005681 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005682 0x0df70000);
5683 } else { /* HDMI or VGA */
5684 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005685 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005687 0x0df70000);
5688 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005689 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005690 0x0df40000);
5691 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005692
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005693 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005694 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5695 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5696 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5697 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005698 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005699
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005700 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005701 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07005702}
5703
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005704static void chv_update_pll(struct intel_crtc *crtc)
5705{
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005706 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5707 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5708 DPLL_VCO_ENABLE;
5709 if (crtc->pipe != PIPE_A)
5710 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5711
5712 crtc->config.dpll_hw_state.dpll_md =
5713 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5714}
5715
5716static void chv_prepare_pll(struct intel_crtc *crtc)
5717{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005718 struct drm_device *dev = crtc->base.dev;
5719 struct drm_i915_private *dev_priv = dev->dev_private;
5720 int pipe = crtc->pipe;
5721 int dpll_reg = DPLL(crtc->pipe);
5722 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005723 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005724 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5725 int refclk;
5726
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005727 bestn = crtc->config.dpll.n;
5728 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5729 bestm1 = crtc->config.dpll.m1;
5730 bestm2 = crtc->config.dpll.m2 >> 22;
5731 bestp1 = crtc->config.dpll.p1;
5732 bestp2 = crtc->config.dpll.p2;
5733
5734 /*
5735 * Enable Refclk and SSC
5736 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005737 I915_WRITE(dpll_reg,
5738 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5739
5740 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005741
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005742 /* p1 and p2 divider */
5743 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5744 5 << DPIO_CHV_S1_DIV_SHIFT |
5745 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5746 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5747 1 << DPIO_CHV_K_DIV_SHIFT);
5748
5749 /* Feedback post-divider - m2 */
5750 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5751
5752 /* Feedback refclk divider - n and m1 */
5753 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5754 DPIO_CHV_M1_DIV_BY_2 |
5755 1 << DPIO_CHV_N_DIV_SHIFT);
5756
5757 /* M2 fraction division */
5758 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5759
5760 /* M2 fraction division enable */
5761 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5762 DPIO_CHV_FRAC_DIV_EN |
5763 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5764
5765 /* Loop filter */
5766 refclk = i9xx_get_refclk(&crtc->base, 0);
5767 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5768 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5769 if (refclk == 100000)
5770 intcoeff = 11;
5771 else if (refclk == 38400)
5772 intcoeff = 10;
5773 else
5774 intcoeff = 9;
5775 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5776 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5777
5778 /* AFC Recal */
5779 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5780 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5781 DPIO_AFC_RECAL);
5782
5783 mutex_unlock(&dev_priv->dpio_lock);
5784}
5785
Daniel Vetterf47709a2013-03-28 10:42:02 +01005786static void i9xx_update_pll(struct intel_crtc *crtc,
5787 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005788 int num_connectors)
5789{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005790 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005791 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005792 u32 dpll;
5793 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005794 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005795
Daniel Vetterf47709a2013-03-28 10:42:02 +01005796 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305797
Daniel Vetterf47709a2013-03-28 10:42:02 +01005798 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5799 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005800
5801 dpll = DPLL_VGA_MODE_DIS;
5802
Daniel Vetterf47709a2013-03-28 10:42:02 +01005803 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005804 dpll |= DPLLB_MODE_LVDS;
5805 else
5806 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005807
Daniel Vetteref1b4602013-06-01 17:17:04 +02005808 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005809 dpll |= (crtc->config.pixel_multiplier - 1)
5810 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005811 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005812
5813 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005814 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005815
Daniel Vetterf47709a2013-03-28 10:42:02 +01005816 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005817 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005818
5819 /* compute bitmask from p1 value */
5820 if (IS_PINEVIEW(dev))
5821 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5822 else {
5823 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5824 if (IS_G4X(dev) && reduced_clock)
5825 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5826 }
5827 switch (clock->p2) {
5828 case 5:
5829 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5830 break;
5831 case 7:
5832 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5833 break;
5834 case 10:
5835 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5836 break;
5837 case 14:
5838 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5839 break;
5840 }
5841 if (INTEL_INFO(dev)->gen >= 4)
5842 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5843
Daniel Vetter09ede542013-04-30 14:01:45 +02005844 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005845 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005846 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005847 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5848 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5849 else
5850 dpll |= PLL_REF_INPUT_DREFCLK;
5851
5852 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005853 crtc->config.dpll_hw_state.dpll = dpll;
5854
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005855 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005856 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5857 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005858 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005859 }
5860}
5861
Daniel Vetterf47709a2013-03-28 10:42:02 +01005862static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005863 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005864 int num_connectors)
5865{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005866 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005867 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005868 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005869 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005870
Daniel Vetterf47709a2013-03-28 10:42:02 +01005871 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305872
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005873 dpll = DPLL_VGA_MODE_DIS;
5874
Daniel Vetterf47709a2013-03-28 10:42:02 +01005875 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005876 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5877 } else {
5878 if (clock->p1 == 2)
5879 dpll |= PLL_P1_DIVIDE_BY_TWO;
5880 else
5881 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5882 if (clock->p2 == 4)
5883 dpll |= PLL_P2_DIVIDE_BY_4;
5884 }
5885
Daniel Vetter4a33e482013-07-06 12:52:05 +02005886 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5887 dpll |= DPLL_DVO_2X_MODE;
5888
Daniel Vetterf47709a2013-03-28 10:42:02 +01005889 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005890 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5891 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5892 else
5893 dpll |= PLL_REF_INPUT_DREFCLK;
5894
5895 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005896 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005897}
5898
Daniel Vetter8a654f32013-06-01 17:16:22 +02005899static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005900{
5901 struct drm_device *dev = intel_crtc->base.dev;
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005904 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005905 struct drm_display_mode *adjusted_mode =
5906 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005907 uint32_t crtc_vtotal, crtc_vblank_end;
5908 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005909
5910 /* We need to be careful not to changed the adjusted mode, for otherwise
5911 * the hw state checker will get angry at the mismatch. */
5912 crtc_vtotal = adjusted_mode->crtc_vtotal;
5913 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005914
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005915 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005916 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005917 crtc_vtotal -= 1;
5918 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005919
5920 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5921 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5922 else
5923 vsyncshift = adjusted_mode->crtc_hsync_start -
5924 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005925 if (vsyncshift < 0)
5926 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005927 }
5928
5929 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005930 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005931
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005932 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005933 (adjusted_mode->crtc_hdisplay - 1) |
5934 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005935 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005936 (adjusted_mode->crtc_hblank_start - 1) |
5937 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005938 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005939 (adjusted_mode->crtc_hsync_start - 1) |
5940 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5941
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005942 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005943 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005944 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005945 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005946 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005947 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005948 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005949 (adjusted_mode->crtc_vsync_start - 1) |
5950 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5951
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005952 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5953 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5954 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5955 * bits. */
5956 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5957 (pipe == PIPE_B || pipe == PIPE_C))
5958 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5959
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005960 /* pipesrc controls the size that is scaled from, which should
5961 * always be the user's requested size.
5962 */
5963 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005964 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5965 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005966}
5967
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005968static void intel_get_pipe_timings(struct intel_crtc *crtc,
5969 struct intel_crtc_config *pipe_config)
5970{
5971 struct drm_device *dev = crtc->base.dev;
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5974 uint32_t tmp;
5975
5976 tmp = I915_READ(HTOTAL(cpu_transcoder));
5977 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5978 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5979 tmp = I915_READ(HBLANK(cpu_transcoder));
5980 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5981 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5982 tmp = I915_READ(HSYNC(cpu_transcoder));
5983 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5984 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5985
5986 tmp = I915_READ(VTOTAL(cpu_transcoder));
5987 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5988 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5989 tmp = I915_READ(VBLANK(cpu_transcoder));
5990 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5991 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5992 tmp = I915_READ(VSYNC(cpu_transcoder));
5993 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5994 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5995
5996 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5997 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5998 pipe_config->adjusted_mode.crtc_vtotal += 1;
5999 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6000 }
6001
6002 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006003 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6004 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6005
6006 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6007 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006008}
6009
Daniel Vetterf6a83282014-02-11 15:28:57 -08006010void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6011 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03006012{
Daniel Vetterf6a83282014-02-11 15:28:57 -08006013 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6014 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6015 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6016 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006017
Daniel Vetterf6a83282014-02-11 15:28:57 -08006018 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6019 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6020 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6021 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006022
Daniel Vetterf6a83282014-02-11 15:28:57 -08006023 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006024
Daniel Vetterf6a83282014-02-11 15:28:57 -08006025 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6026 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006027}
6028
Daniel Vetter84b046f2013-02-19 18:48:54 +01006029static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6030{
6031 struct drm_device *dev = intel_crtc->base.dev;
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033 uint32_t pipeconf;
6034
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006035 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006036
Daniel Vetter67c72a12013-09-24 11:46:14 +02006037 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6038 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6039 pipeconf |= PIPECONF_ENABLE;
6040
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006041 if (intel_crtc->config.double_wide)
6042 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006043
Daniel Vetterff9ce462013-04-24 14:57:17 +02006044 /* only g4x and later have fancy bpc/dither controls */
6045 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02006046 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6047 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6048 pipeconf |= PIPECONF_DITHER_EN |
6049 PIPECONF_DITHER_TYPE_SP;
6050
6051 switch (intel_crtc->config.pipe_bpp) {
6052 case 18:
6053 pipeconf |= PIPECONF_6BPC;
6054 break;
6055 case 24:
6056 pipeconf |= PIPECONF_8BPC;
6057 break;
6058 case 30:
6059 pipeconf |= PIPECONF_10BPC;
6060 break;
6061 default:
6062 /* Case prevented by intel_choose_pipe_bpp_dither. */
6063 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01006064 }
6065 }
6066
6067 if (HAS_PIPE_CXSR(dev)) {
6068 if (intel_crtc->lowfreq_avail) {
6069 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6070 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6071 } else {
6072 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01006073 }
6074 }
6075
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006076 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6077 if (INTEL_INFO(dev)->gen < 4 ||
6078 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6079 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6080 else
6081 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6082 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01006083 pipeconf |= PIPECONF_PROGRESSIVE;
6084
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006085 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6086 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006087
Daniel Vetter84b046f2013-02-19 18:48:54 +01006088 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6089 POSTING_READ(PIPECONF(intel_crtc->pipe));
6090}
6091
Eric Anholtf564048e2011-03-30 13:01:02 -07006092static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07006093 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006094 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006095{
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07006099 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006100 intel_clock_t clock, reduced_clock;
Daniel Vettera16af722013-04-30 14:01:44 +02006101 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006102 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006103 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006104 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006105
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02006106 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01006107 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006108 case INTEL_OUTPUT_LVDS:
6109 is_lvds = true;
6110 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006111 case INTEL_OUTPUT_DSI:
6112 is_dsi = true;
6113 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006114 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006115
Eric Anholtc751ce42010-03-25 11:48:48 -07006116 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006117 }
6118
Jani Nikulaf2335332013-09-13 11:03:09 +03006119 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006120 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006121
Jani Nikulaf2335332013-09-13 11:03:09 +03006122 if (!intel_crtc->config.clock_set) {
6123 refclk = i9xx_get_refclk(crtc, num_connectors);
6124
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006125 /*
6126 * Returns a set of divisors for the desired target clock with
6127 * the given refclk, or FALSE. The returned values represent
6128 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6129 * 2) / p1 / p2.
6130 */
6131 limit = intel_limit(crtc, refclk);
6132 ok = dev_priv->display.find_dpll(limit, crtc,
6133 intel_crtc->config.port_clock,
6134 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006135 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006136 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6137 return -EINVAL;
6138 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006139
Jani Nikulaf2335332013-09-13 11:03:09 +03006140 if (is_lvds && dev_priv->lvds_downclock_avail) {
6141 /*
6142 * Ensure we match the reduced clock's P to the target
6143 * clock. If the clocks don't match, we can't switch
6144 * the display clock by using the FP0/FP1. In such case
6145 * we will disable the LVDS downclock feature.
6146 */
6147 has_reduced_clock =
6148 dev_priv->display.find_dpll(limit, crtc,
6149 dev_priv->lvds_downclock,
6150 refclk, &clock,
6151 &reduced_clock);
6152 }
6153 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01006154 intel_crtc->config.dpll.n = clock.n;
6155 intel_crtc->config.dpll.m1 = clock.m1;
6156 intel_crtc->config.dpll.m2 = clock.m2;
6157 intel_crtc->config.dpll.p1 = clock.p1;
6158 intel_crtc->config.dpll.p2 = clock.p2;
6159 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006160
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006161 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02006162 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306163 has_reduced_clock ? &reduced_clock : NULL,
6164 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006165 } else if (IS_CHERRYVIEW(dev)) {
6166 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006167 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03006168 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006169 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01006170 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006171 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006172 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006173 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006174
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006175 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006176}
6177
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006178static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6179 struct intel_crtc_config *pipe_config)
6180{
6181 struct drm_device *dev = crtc->base.dev;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183 uint32_t tmp;
6184
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006185 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6186 return;
6187
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006188 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006189 if (!(tmp & PFIT_ENABLE))
6190 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006191
Daniel Vetter06922822013-07-11 13:35:40 +02006192 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006193 if (INTEL_INFO(dev)->gen < 4) {
6194 if (crtc->pipe != PIPE_B)
6195 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006196 } else {
6197 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6198 return;
6199 }
6200
Daniel Vetter06922822013-07-11 13:35:40 +02006201 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006202 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6203 if (INTEL_INFO(dev)->gen < 5)
6204 pipe_config->gmch_pfit.lvds_border_bits =
6205 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6206}
6207
Jesse Barnesacbec812013-09-20 11:29:32 -07006208static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6209 struct intel_crtc_config *pipe_config)
6210{
6211 struct drm_device *dev = crtc->base.dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 int pipe = pipe_config->cpu_transcoder;
6214 intel_clock_t clock;
6215 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006216 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006217
Shobhit Kumarf573de52014-07-30 20:32:37 +05306218 /* In case of MIPI DPLL will not even be used */
6219 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6220 return;
6221
Jesse Barnesacbec812013-09-20 11:29:32 -07006222 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006223 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006224 mutex_unlock(&dev_priv->dpio_lock);
6225
6226 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6227 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6228 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6229 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6230 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6231
Ville Syrjäläf6466282013-10-14 14:50:31 +03006232 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006233
Ville Syrjäläf6466282013-10-14 14:50:31 +03006234 /* clock.dot is the fast clock */
6235 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006236}
6237
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006238static void i9xx_get_plane_config(struct intel_crtc *crtc,
6239 struct intel_plane_config *plane_config)
6240{
6241 struct drm_device *dev = crtc->base.dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 u32 val, base, offset;
6244 int pipe = crtc->pipe, plane = crtc->plane;
6245 int fourcc, pixel_format;
6246 int aligned_height;
6247
Dave Airlie66e514c2014-04-03 07:51:54 +10006248 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6249 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006250 DRM_DEBUG_KMS("failed to alloc fb\n");
6251 return;
6252 }
6253
6254 val = I915_READ(DSPCNTR(plane));
6255
6256 if (INTEL_INFO(dev)->gen >= 4)
6257 if (val & DISPPLANE_TILED)
6258 plane_config->tiled = true;
6259
6260 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6261 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006262 crtc->base.primary->fb->pixel_format = fourcc;
6263 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006264 drm_format_plane_cpp(fourcc, 0) * 8;
6265
6266 if (INTEL_INFO(dev)->gen >= 4) {
6267 if (plane_config->tiled)
6268 offset = I915_READ(DSPTILEOFF(plane));
6269 else
6270 offset = I915_READ(DSPLINOFF(plane));
6271 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6272 } else {
6273 base = I915_READ(DSPADDR(plane));
6274 }
6275 plane_config->base = base;
6276
6277 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006278 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6279 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006280
6281 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01006282 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006283
Dave Airlie66e514c2014-04-03 07:51:54 +10006284 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006285 plane_config->tiled);
6286
Fabian Frederick1267a262014-07-01 20:39:41 +02006287 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6288 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006289
6290 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006291 pipe, plane, crtc->base.primary->fb->width,
6292 crtc->base.primary->fb->height,
6293 crtc->base.primary->fb->bits_per_pixel, base,
6294 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006295 plane_config->size);
6296
6297}
6298
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006299static void chv_crtc_clock_get(struct intel_crtc *crtc,
6300 struct intel_crtc_config *pipe_config)
6301{
6302 struct drm_device *dev = crtc->base.dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 int pipe = pipe_config->cpu_transcoder;
6305 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6306 intel_clock_t clock;
6307 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6308 int refclk = 100000;
6309
6310 mutex_lock(&dev_priv->dpio_lock);
6311 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6312 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6313 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6314 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6315 mutex_unlock(&dev_priv->dpio_lock);
6316
6317 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6318 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6319 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6320 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6321 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6322
6323 chv_clock(refclk, &clock);
6324
6325 /* clock.dot is the fast clock */
6326 pipe_config->port_clock = clock.dot / 5;
6327}
6328
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006329static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6330 struct intel_crtc_config *pipe_config)
6331{
6332 struct drm_device *dev = crtc->base.dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 uint32_t tmp;
6335
Imre Deakb5482bd2014-03-05 16:20:55 +02006336 if (!intel_display_power_enabled(dev_priv,
6337 POWER_DOMAIN_PIPE(crtc->pipe)))
6338 return false;
6339
Daniel Vettere143a212013-07-04 12:01:15 +02006340 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006341 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006342
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006343 tmp = I915_READ(PIPECONF(crtc->pipe));
6344 if (!(tmp & PIPECONF_ENABLE))
6345 return false;
6346
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006347 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6348 switch (tmp & PIPECONF_BPC_MASK) {
6349 case PIPECONF_6BPC:
6350 pipe_config->pipe_bpp = 18;
6351 break;
6352 case PIPECONF_8BPC:
6353 pipe_config->pipe_bpp = 24;
6354 break;
6355 case PIPECONF_10BPC:
6356 pipe_config->pipe_bpp = 30;
6357 break;
6358 default:
6359 break;
6360 }
6361 }
6362
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006363 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6364 pipe_config->limited_color_range = true;
6365
Ville Syrjälä282740f2013-09-04 18:30:03 +03006366 if (INTEL_INFO(dev)->gen < 4)
6367 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6368
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006369 intel_get_pipe_timings(crtc, pipe_config);
6370
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006371 i9xx_get_pfit_config(crtc, pipe_config);
6372
Daniel Vetter6c49f242013-06-06 12:45:25 +02006373 if (INTEL_INFO(dev)->gen >= 4) {
6374 tmp = I915_READ(DPLL_MD(crtc->pipe));
6375 pipe_config->pixel_multiplier =
6376 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6377 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006378 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006379 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6380 tmp = I915_READ(DPLL(crtc->pipe));
6381 pipe_config->pixel_multiplier =
6382 ((tmp & SDVO_MULTIPLIER_MASK)
6383 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6384 } else {
6385 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6386 * port and will be fixed up in the encoder->get_config
6387 * function. */
6388 pipe_config->pixel_multiplier = 1;
6389 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006390 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6391 if (!IS_VALLEYVIEW(dev)) {
6392 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6393 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006394 } else {
6395 /* Mask out read-only status bits. */
6396 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6397 DPLL_PORTC_READY_MASK |
6398 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006399 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006400
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006401 if (IS_CHERRYVIEW(dev))
6402 chv_crtc_clock_get(crtc, pipe_config);
6403 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006404 vlv_crtc_clock_get(crtc, pipe_config);
6405 else
6406 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006407
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006408 return true;
6409}
6410
Paulo Zanonidde86e22012-12-01 12:04:25 -02006411static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006412{
6413 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006414 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006415 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006416 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006417 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006418 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006419 bool has_ck505 = false;
6420 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006421
6422 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01006423 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07006424 switch (encoder->type) {
6425 case INTEL_OUTPUT_LVDS:
6426 has_panel = true;
6427 has_lvds = true;
6428 break;
6429 case INTEL_OUTPUT_EDP:
6430 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006431 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006432 has_cpu_edp = true;
6433 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006434 }
6435 }
6436
Keith Packard99eb6a02011-09-26 14:29:12 -07006437 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006438 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006439 can_ssc = has_ck505;
6440 } else {
6441 has_ck505 = false;
6442 can_ssc = true;
6443 }
6444
Imre Deak2de69052013-05-08 13:14:04 +03006445 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6446 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006447
6448 /* Ironlake: try to setup display ref clock before DPLL
6449 * enabling. This is only under driver's control after
6450 * PCH B stepping, previous chipset stepping should be
6451 * ignoring this setting.
6452 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006453 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006454
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006455 /* As we must carefully and slowly disable/enable each source in turn,
6456 * compute the final state we want first and check if we need to
6457 * make any changes at all.
6458 */
6459 final = val;
6460 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006461 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006462 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006463 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006464 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6465
6466 final &= ~DREF_SSC_SOURCE_MASK;
6467 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6468 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006469
Keith Packard199e5d72011-09-22 12:01:57 -07006470 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006471 final |= DREF_SSC_SOURCE_ENABLE;
6472
6473 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6474 final |= DREF_SSC1_ENABLE;
6475
6476 if (has_cpu_edp) {
6477 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6478 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6479 else
6480 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6481 } else
6482 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6483 } else {
6484 final |= DREF_SSC_SOURCE_DISABLE;
6485 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6486 }
6487
6488 if (final == val)
6489 return;
6490
6491 /* Always enable nonspread source */
6492 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6493
6494 if (has_ck505)
6495 val |= DREF_NONSPREAD_CK505_ENABLE;
6496 else
6497 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6498
6499 if (has_panel) {
6500 val &= ~DREF_SSC_SOURCE_MASK;
6501 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006502
Keith Packard199e5d72011-09-22 12:01:57 -07006503 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006504 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006505 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006506 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006507 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006508 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006509
6510 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006511 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006512 POSTING_READ(PCH_DREF_CONTROL);
6513 udelay(200);
6514
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006515 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006516
6517 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006518 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006519 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006520 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006521 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006522 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006523 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006524 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006525 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006526
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006527 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006528 POSTING_READ(PCH_DREF_CONTROL);
6529 udelay(200);
6530 } else {
6531 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6532
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006533 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006534
6535 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006536 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006537
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006538 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006539 POSTING_READ(PCH_DREF_CONTROL);
6540 udelay(200);
6541
6542 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006543 val &= ~DREF_SSC_SOURCE_MASK;
6544 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006545
6546 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006547 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006548
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006549 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006550 POSTING_READ(PCH_DREF_CONTROL);
6551 udelay(200);
6552 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006553
6554 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006555}
6556
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006557static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006558{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006559 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006560
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006561 tmp = I915_READ(SOUTH_CHICKEN2);
6562 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6563 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006564
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006565 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6566 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6567 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006568
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006569 tmp = I915_READ(SOUTH_CHICKEN2);
6570 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6571 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006572
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006573 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6574 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6575 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006576}
6577
6578/* WaMPhyProgramming:hsw */
6579static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6580{
6581 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006582
6583 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6584 tmp &= ~(0xFF << 24);
6585 tmp |= (0x12 << 24);
6586 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6587
Paulo Zanonidde86e22012-12-01 12:04:25 -02006588 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6589 tmp |= (1 << 11);
6590 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6591
6592 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6593 tmp |= (1 << 11);
6594 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6595
Paulo Zanonidde86e22012-12-01 12:04:25 -02006596 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6597 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6598 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6599
6600 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6601 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6602 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6603
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006604 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6605 tmp &= ~(7 << 13);
6606 tmp |= (5 << 13);
6607 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006608
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006609 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6610 tmp &= ~(7 << 13);
6611 tmp |= (5 << 13);
6612 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006613
6614 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6615 tmp &= ~0xFF;
6616 tmp |= 0x1C;
6617 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6618
6619 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6620 tmp &= ~0xFF;
6621 tmp |= 0x1C;
6622 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6623
6624 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6625 tmp &= ~(0xFF << 16);
6626 tmp |= (0x1C << 16);
6627 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6628
6629 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6630 tmp &= ~(0xFF << 16);
6631 tmp |= (0x1C << 16);
6632 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6633
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006634 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6635 tmp |= (1 << 27);
6636 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006637
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006638 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6639 tmp |= (1 << 27);
6640 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006641
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006642 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6643 tmp &= ~(0xF << 28);
6644 tmp |= (4 << 28);
6645 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006646
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006647 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6648 tmp &= ~(0xF << 28);
6649 tmp |= (4 << 28);
6650 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006651}
6652
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006653/* Implements 3 different sequences from BSpec chapter "Display iCLK
6654 * Programming" based on the parameters passed:
6655 * - Sequence to enable CLKOUT_DP
6656 * - Sequence to enable CLKOUT_DP without spread
6657 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6658 */
6659static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6660 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006661{
6662 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006663 uint32_t reg, tmp;
6664
6665 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6666 with_spread = true;
6667 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6668 with_fdi, "LP PCH doesn't have FDI\n"))
6669 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006670
6671 mutex_lock(&dev_priv->dpio_lock);
6672
6673 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6674 tmp &= ~SBI_SSCCTL_DISABLE;
6675 tmp |= SBI_SSCCTL_PATHALT;
6676 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6677
6678 udelay(24);
6679
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006680 if (with_spread) {
6681 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6682 tmp &= ~SBI_SSCCTL_PATHALT;
6683 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006684
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006685 if (with_fdi) {
6686 lpt_reset_fdi_mphy(dev_priv);
6687 lpt_program_fdi_mphy(dev_priv);
6688 }
6689 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006690
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006691 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6692 SBI_GEN0 : SBI_DBUFF0;
6693 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6694 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6695 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006696
6697 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006698}
6699
Paulo Zanoni47701c32013-07-23 11:19:25 -03006700/* Sequence to disable CLKOUT_DP */
6701static void lpt_disable_clkout_dp(struct drm_device *dev)
6702{
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 uint32_t reg, tmp;
6705
6706 mutex_lock(&dev_priv->dpio_lock);
6707
6708 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6709 SBI_GEN0 : SBI_DBUFF0;
6710 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6711 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6712 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6713
6714 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6715 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6716 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6717 tmp |= SBI_SSCCTL_PATHALT;
6718 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6719 udelay(32);
6720 }
6721 tmp |= SBI_SSCCTL_DISABLE;
6722 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6723 }
6724
6725 mutex_unlock(&dev_priv->dpio_lock);
6726}
6727
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006728static void lpt_init_pch_refclk(struct drm_device *dev)
6729{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006730 struct intel_encoder *encoder;
6731 bool has_vga = false;
6732
Damien Lespiaub2784e12014-08-05 11:29:37 +01006733 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006734 switch (encoder->type) {
6735 case INTEL_OUTPUT_ANALOG:
6736 has_vga = true;
6737 break;
6738 }
6739 }
6740
Paulo Zanoni47701c32013-07-23 11:19:25 -03006741 if (has_vga)
6742 lpt_enable_clkout_dp(dev, true, true);
6743 else
6744 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006745}
6746
Paulo Zanonidde86e22012-12-01 12:04:25 -02006747/*
6748 * Initialize reference clocks when the driver loads
6749 */
6750void intel_init_pch_refclk(struct drm_device *dev)
6751{
6752 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6753 ironlake_init_pch_refclk(dev);
6754 else if (HAS_PCH_LPT(dev))
6755 lpt_init_pch_refclk(dev);
6756}
6757
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006758static int ironlake_get_refclk(struct drm_crtc *crtc)
6759{
6760 struct drm_device *dev = crtc->dev;
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006763 int num_connectors = 0;
6764 bool is_lvds = false;
6765
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02006766 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006767 switch (encoder->type) {
6768 case INTEL_OUTPUT_LVDS:
6769 is_lvds = true;
6770 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006771 }
6772 num_connectors++;
6773 }
6774
6775 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006776 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006777 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006778 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006779 }
6780
6781 return 120000;
6782}
6783
Daniel Vetter6ff93602013-04-19 11:24:36 +02006784static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006785{
6786 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788 int pipe = intel_crtc->pipe;
6789 uint32_t val;
6790
Daniel Vetter78114072013-06-13 00:54:57 +02006791 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006792
Daniel Vetter965e0c42013-03-27 00:44:57 +01006793 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006794 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006795 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006796 break;
6797 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006798 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006799 break;
6800 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006801 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006802 break;
6803 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006804 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006805 break;
6806 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006807 /* Case prevented by intel_choose_pipe_bpp_dither. */
6808 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006809 }
6810
Daniel Vetterd8b32242013-04-25 17:54:44 +02006811 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006812 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6813
Daniel Vetter6ff93602013-04-19 11:24:36 +02006814 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006815 val |= PIPECONF_INTERLACED_ILK;
6816 else
6817 val |= PIPECONF_PROGRESSIVE;
6818
Daniel Vetter50f3b012013-03-27 00:44:56 +01006819 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006820 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006821
Paulo Zanonic8203562012-09-12 10:06:29 -03006822 I915_WRITE(PIPECONF(pipe), val);
6823 POSTING_READ(PIPECONF(pipe));
6824}
6825
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006826/*
6827 * Set up the pipe CSC unit.
6828 *
6829 * Currently only full range RGB to limited range RGB conversion
6830 * is supported, but eventually this should handle various
6831 * RGB<->YCbCr scenarios as well.
6832 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006833static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006834{
6835 struct drm_device *dev = crtc->dev;
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838 int pipe = intel_crtc->pipe;
6839 uint16_t coeff = 0x7800; /* 1.0 */
6840
6841 /*
6842 * TODO: Check what kind of values actually come out of the pipe
6843 * with these coeff/postoff values and adjust to get the best
6844 * accuracy. Perhaps we even need to take the bpc value into
6845 * consideration.
6846 */
6847
Daniel Vetter50f3b012013-03-27 00:44:56 +01006848 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006849 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6850
6851 /*
6852 * GY/GU and RY/RU should be the other way around according
6853 * to BSpec, but reality doesn't agree. Just set them up in
6854 * a way that results in the correct picture.
6855 */
6856 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6857 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6858
6859 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6860 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6861
6862 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6863 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6864
6865 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6866 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6867 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6868
6869 if (INTEL_INFO(dev)->gen > 6) {
6870 uint16_t postoff = 0;
6871
Daniel Vetter50f3b012013-03-27 00:44:56 +01006872 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006873 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006874
6875 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6876 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6877 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6878
6879 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6880 } else {
6881 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6882
Daniel Vetter50f3b012013-03-27 00:44:56 +01006883 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006884 mode |= CSC_BLACK_SCREEN_OFFSET;
6885
6886 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6887 }
6888}
6889
Daniel Vetter6ff93602013-04-19 11:24:36 +02006890static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006891{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006892 struct drm_device *dev = crtc->dev;
6893 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006895 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006896 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006897 uint32_t val;
6898
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006899 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006900
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006901 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006902 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6903
Daniel Vetter6ff93602013-04-19 11:24:36 +02006904 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006905 val |= PIPECONF_INTERLACED_ILK;
6906 else
6907 val |= PIPECONF_PROGRESSIVE;
6908
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006909 I915_WRITE(PIPECONF(cpu_transcoder), val);
6910 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006911
6912 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6913 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006914
6915 if (IS_BROADWELL(dev)) {
6916 val = 0;
6917
6918 switch (intel_crtc->config.pipe_bpp) {
6919 case 18:
6920 val |= PIPEMISC_DITHER_6_BPC;
6921 break;
6922 case 24:
6923 val |= PIPEMISC_DITHER_8_BPC;
6924 break;
6925 case 30:
6926 val |= PIPEMISC_DITHER_10_BPC;
6927 break;
6928 case 36:
6929 val |= PIPEMISC_DITHER_12_BPC;
6930 break;
6931 default:
6932 /* Case prevented by pipe_config_set_bpp. */
6933 BUG();
6934 }
6935
6936 if (intel_crtc->config.dither)
6937 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6938
6939 I915_WRITE(PIPEMISC(pipe), val);
6940 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006941}
6942
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006943static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006944 intel_clock_t *clock,
6945 bool *has_reduced_clock,
6946 intel_clock_t *reduced_clock)
6947{
6948 struct drm_device *dev = crtc->dev;
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950 struct intel_encoder *intel_encoder;
6951 int refclk;
6952 const intel_limit_t *limit;
Daniel Vettera16af722013-04-30 14:01:44 +02006953 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006954
6955 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6956 switch (intel_encoder->type) {
6957 case INTEL_OUTPUT_LVDS:
6958 is_lvds = true;
6959 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006960 }
6961 }
6962
6963 refclk = ironlake_get_refclk(crtc);
6964
6965 /*
6966 * Returns a set of divisors for the desired target clock with the given
6967 * refclk, or FALSE. The returned values represent the clock equation:
6968 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6969 */
6970 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006971 ret = dev_priv->display.find_dpll(limit, crtc,
6972 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006973 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006974 if (!ret)
6975 return false;
6976
6977 if (is_lvds && dev_priv->lvds_downclock_avail) {
6978 /*
6979 * Ensure we match the reduced clock's P to the target clock.
6980 * If the clocks don't match, we can't switch the display clock
6981 * by using the FP0/FP1. In such case we will disable the LVDS
6982 * downclock feature.
6983 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006984 *has_reduced_clock =
6985 dev_priv->display.find_dpll(limit, crtc,
6986 dev_priv->lvds_downclock,
6987 refclk, clock,
6988 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006989 }
6990
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006991 return true;
6992}
6993
Paulo Zanonid4b19312012-11-29 11:29:32 -02006994int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6995{
6996 /*
6997 * Account for spread spectrum to avoid
6998 * oversubscribing the link. Max center spread
6999 * is 2.5%; use 5% for safety's sake.
7000 */
7001 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02007002 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02007003}
7004
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007005static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02007006{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007007 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007008}
7009
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007010static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007011 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007012 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007013{
7014 struct drm_crtc *crtc = &intel_crtc->base;
7015 struct drm_device *dev = crtc->dev;
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 struct intel_encoder *intel_encoder;
7018 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007019 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02007020 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007021
7022 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7023 switch (intel_encoder->type) {
7024 case INTEL_OUTPUT_LVDS:
7025 is_lvds = true;
7026 break;
7027 case INTEL_OUTPUT_SDVO:
7028 case INTEL_OUTPUT_HDMI:
7029 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007030 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007031 }
7032
7033 num_connectors++;
7034 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007035
Chris Wilsonc1858122010-12-03 21:35:48 +00007036 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07007037 factor = 21;
7038 if (is_lvds) {
7039 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007040 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02007041 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07007042 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02007043 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07007044 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00007045
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007046 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02007047 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00007048
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007049 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7050 *fp2 |= FP_CB_TUNE;
7051
Chris Wilson5eddb702010-09-11 13:48:45 +01007052 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007053
Eric Anholta07d6782011-03-30 13:01:08 -07007054 if (is_lvds)
7055 dpll |= DPLLB_MODE_LVDS;
7056 else
7057 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007058
Daniel Vetteref1b4602013-06-01 17:17:04 +02007059 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7060 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007061
7062 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007063 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02007064 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007065 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08007066
Eric Anholta07d6782011-03-30 13:01:08 -07007067 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007068 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007069 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007070 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007071
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007072 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07007073 case 5:
7074 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7075 break;
7076 case 7:
7077 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7078 break;
7079 case 10:
7080 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7081 break;
7082 case 14:
7083 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7084 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007085 }
7086
Daniel Vetterb4c09f32013-04-30 14:01:42 +02007087 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007088 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007089 else
7090 dpll |= PLL_REF_INPUT_DREFCLK;
7091
Daniel Vetter959e16d2013-06-05 13:34:21 +02007092 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007093}
7094
Jesse Barnes79e53942008-11-07 14:24:08 -08007095static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08007096 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007097 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08007098{
7099 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007101 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007102 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007103 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007104 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007105 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007106 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02007107 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007108
7109 for_each_encoder_on_crtc(dev, crtc, encoder) {
7110 switch (encoder->type) {
7111 case INTEL_OUTPUT_LVDS:
7112 is_lvds = true;
7113 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007114 }
7115
7116 num_connectors++;
7117 }
7118
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007119 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7120 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7121
Daniel Vetterff9a6752013-06-01 17:16:21 +02007122 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007123 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02007124 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007125 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7126 return -EINVAL;
7127 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007128 /* Compat-code for transition, will disappear. */
7129 if (!intel_crtc->config.clock_set) {
7130 intel_crtc->config.dpll.n = clock.n;
7131 intel_crtc->config.dpll.m1 = clock.m1;
7132 intel_crtc->config.dpll.m2 = clock.m2;
7133 intel_crtc->config.dpll.p1 = clock.p1;
7134 intel_crtc->config.dpll.p2 = clock.p2;
7135 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007136
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007137 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01007138 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007139 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007140 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007141 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007142
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007143 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007144 &fp, &reduced_clock,
7145 has_reduced_clock ? &fp2 : NULL);
7146
Daniel Vetter959e16d2013-06-05 13:34:21 +02007147 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007148 intel_crtc->config.dpll_hw_state.fp0 = fp;
7149 if (has_reduced_clock)
7150 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7151 else
7152 intel_crtc->config.dpll_hw_state.fp1 = fp;
7153
Daniel Vetterb89a1d32013-06-05 13:34:24 +02007154 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007155 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007156 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02007157 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007158 return -EINVAL;
7159 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007160 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02007161 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007162
Jani Nikulad330a952014-01-21 11:24:25 +02007163 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007164 intel_crtc->lowfreq_avail = true;
7165 else
7166 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007167
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007168 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007169}
7170
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007171static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7172 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007173{
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007176 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007177
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007178 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7179 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7180 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7181 & ~TU_SIZE_MASK;
7182 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7183 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7184 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7185}
7186
7187static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7188 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007189 struct intel_link_m_n *m_n,
7190 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007191{
7192 struct drm_device *dev = crtc->base.dev;
7193 struct drm_i915_private *dev_priv = dev->dev_private;
7194 enum pipe pipe = crtc->pipe;
7195
7196 if (INTEL_INFO(dev)->gen >= 5) {
7197 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7198 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7199 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7200 & ~TU_SIZE_MASK;
7201 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7202 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7203 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007204 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7205 * gen < 8) and if DRRS is supported (to make sure the
7206 * registers are not unnecessarily read).
7207 */
7208 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7209 crtc->config.has_drrs) {
7210 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7211 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7212 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7213 & ~TU_SIZE_MASK;
7214 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7215 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7216 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7217 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007218 } else {
7219 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7220 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7221 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7222 & ~TU_SIZE_MASK;
7223 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7224 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7225 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7226 }
7227}
7228
7229void intel_dp_get_m_n(struct intel_crtc *crtc,
7230 struct intel_crtc_config *pipe_config)
7231{
7232 if (crtc->config.has_pch_encoder)
7233 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7234 else
7235 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007236 &pipe_config->dp_m_n,
7237 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007238}
7239
Daniel Vetter72419202013-04-04 13:28:53 +02007240static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7241 struct intel_crtc_config *pipe_config)
7242{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007243 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007244 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02007245}
7246
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007247static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7248 struct intel_crtc_config *pipe_config)
7249{
7250 struct drm_device *dev = crtc->base.dev;
7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252 uint32_t tmp;
7253
7254 tmp = I915_READ(PF_CTL(crtc->pipe));
7255
7256 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007257 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007258 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7259 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007260
7261 /* We currently do not free assignements of panel fitters on
7262 * ivb/hsw (since we don't use the higher upscaling modes which
7263 * differentiates them) so just WARN about this case for now. */
7264 if (IS_GEN7(dev)) {
7265 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7266 PF_PIPE_SEL_IVB(crtc->pipe));
7267 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007268 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007269}
7270
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007271static void ironlake_get_plane_config(struct intel_crtc *crtc,
7272 struct intel_plane_config *plane_config)
7273{
7274 struct drm_device *dev = crtc->base.dev;
7275 struct drm_i915_private *dev_priv = dev->dev_private;
7276 u32 val, base, offset;
7277 int pipe = crtc->pipe, plane = crtc->plane;
7278 int fourcc, pixel_format;
7279 int aligned_height;
7280
Dave Airlie66e514c2014-04-03 07:51:54 +10007281 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7282 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007283 DRM_DEBUG_KMS("failed to alloc fb\n");
7284 return;
7285 }
7286
7287 val = I915_READ(DSPCNTR(plane));
7288
7289 if (INTEL_INFO(dev)->gen >= 4)
7290 if (val & DISPPLANE_TILED)
7291 plane_config->tiled = true;
7292
7293 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7294 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007295 crtc->base.primary->fb->pixel_format = fourcc;
7296 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007297 drm_format_plane_cpp(fourcc, 0) * 8;
7298
7299 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7300 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7301 offset = I915_READ(DSPOFFSET(plane));
7302 } else {
7303 if (plane_config->tiled)
7304 offset = I915_READ(DSPTILEOFF(plane));
7305 else
7306 offset = I915_READ(DSPLINOFF(plane));
7307 }
7308 plane_config->base = base;
7309
7310 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007311 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7312 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007313
7314 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01007315 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007316
Dave Airlie66e514c2014-04-03 07:51:54 +10007317 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007318 plane_config->tiled);
7319
Fabian Frederick1267a262014-07-01 20:39:41 +02007320 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7321 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007322
7323 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007324 pipe, plane, crtc->base.primary->fb->width,
7325 crtc->base.primary->fb->height,
7326 crtc->base.primary->fb->bits_per_pixel, base,
7327 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007328 plane_config->size);
7329}
7330
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007331static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7332 struct intel_crtc_config *pipe_config)
7333{
7334 struct drm_device *dev = crtc->base.dev;
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 uint32_t tmp;
7337
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007338 if (!intel_display_power_enabled(dev_priv,
7339 POWER_DOMAIN_PIPE(crtc->pipe)))
7340 return false;
7341
Daniel Vettere143a212013-07-04 12:01:15 +02007342 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007343 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007344
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007345 tmp = I915_READ(PIPECONF(crtc->pipe));
7346 if (!(tmp & PIPECONF_ENABLE))
7347 return false;
7348
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007349 switch (tmp & PIPECONF_BPC_MASK) {
7350 case PIPECONF_6BPC:
7351 pipe_config->pipe_bpp = 18;
7352 break;
7353 case PIPECONF_8BPC:
7354 pipe_config->pipe_bpp = 24;
7355 break;
7356 case PIPECONF_10BPC:
7357 pipe_config->pipe_bpp = 30;
7358 break;
7359 case PIPECONF_12BPC:
7360 pipe_config->pipe_bpp = 36;
7361 break;
7362 default:
7363 break;
7364 }
7365
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007366 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7367 pipe_config->limited_color_range = true;
7368
Daniel Vetterab9412b2013-05-03 11:49:46 +02007369 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007370 struct intel_shared_dpll *pll;
7371
Daniel Vetter88adfff2013-03-28 10:42:01 +01007372 pipe_config->has_pch_encoder = true;
7373
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007374 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7375 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7376 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007377
7378 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007379
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007380 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007381 pipe_config->shared_dpll =
7382 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007383 } else {
7384 tmp = I915_READ(PCH_DPLL_SEL);
7385 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7386 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7387 else
7388 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7389 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007390
7391 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7392
7393 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7394 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007395
7396 tmp = pipe_config->dpll_hw_state.dpll;
7397 pipe_config->pixel_multiplier =
7398 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7399 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007400
7401 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007402 } else {
7403 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007404 }
7405
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007406 intel_get_pipe_timings(crtc, pipe_config);
7407
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007408 ironlake_get_pfit_config(crtc, pipe_config);
7409
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007410 return true;
7411}
7412
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007413static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7414{
7415 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007416 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007417
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007418 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007419 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007420 pipe_name(crtc->pipe));
7421
7422 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007423 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7424 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7425 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007426 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7427 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7428 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03007429 if (IS_HASWELL(dev))
7430 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7431 "CPU PWM2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007432 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7433 "PCH PWM1 enabled\n");
7434 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7435 "Utility pin enabled\n");
7436 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7437
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007438 /*
7439 * In theory we can still leave IRQs enabled, as long as only the HPD
7440 * interrupts remain enabled. We used to check for that, but since it's
7441 * gen-specific and since we only disable LCPLL after we fully disable
7442 * the interrupts, the check below should be enough.
7443 */
Jesse Barnes9df7575f2014-06-20 09:29:20 -07007444 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007445}
7446
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007447static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7448{
7449 struct drm_device *dev = dev_priv->dev;
7450
7451 if (IS_HASWELL(dev))
7452 return I915_READ(D_COMP_HSW);
7453 else
7454 return I915_READ(D_COMP_BDW);
7455}
7456
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007457static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7458{
7459 struct drm_device *dev = dev_priv->dev;
7460
7461 if (IS_HASWELL(dev)) {
7462 mutex_lock(&dev_priv->rps.hw_lock);
7463 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7464 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007465 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007466 mutex_unlock(&dev_priv->rps.hw_lock);
7467 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007468 I915_WRITE(D_COMP_BDW, val);
7469 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007470 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007471}
7472
7473/*
7474 * This function implements pieces of two sequences from BSpec:
7475 * - Sequence for display software to disable LCPLL
7476 * - Sequence for display software to allow package C8+
7477 * The steps implemented here are just the steps that actually touch the LCPLL
7478 * register. Callers should take care of disabling all the display engine
7479 * functions, doing the mode unset, fixing interrupts, etc.
7480 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007481static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7482 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007483{
7484 uint32_t val;
7485
7486 assert_can_disable_lcpll(dev_priv);
7487
7488 val = I915_READ(LCPLL_CTL);
7489
7490 if (switch_to_fclk) {
7491 val |= LCPLL_CD_SOURCE_FCLK;
7492 I915_WRITE(LCPLL_CTL, val);
7493
7494 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7495 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7496 DRM_ERROR("Switching to FCLK failed\n");
7497
7498 val = I915_READ(LCPLL_CTL);
7499 }
7500
7501 val |= LCPLL_PLL_DISABLE;
7502 I915_WRITE(LCPLL_CTL, val);
7503 POSTING_READ(LCPLL_CTL);
7504
7505 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7506 DRM_ERROR("LCPLL still locked\n");
7507
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007508 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007509 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007510 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007511 ndelay(100);
7512
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007513 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7514 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007515 DRM_ERROR("D_COMP RCOMP still in progress\n");
7516
7517 if (allow_power_down) {
7518 val = I915_READ(LCPLL_CTL);
7519 val |= LCPLL_POWER_DOWN_ALLOW;
7520 I915_WRITE(LCPLL_CTL, val);
7521 POSTING_READ(LCPLL_CTL);
7522 }
7523}
7524
7525/*
7526 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7527 * source.
7528 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007529static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007530{
7531 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007532 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007533
7534 val = I915_READ(LCPLL_CTL);
7535
7536 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7537 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7538 return;
7539
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007540 /*
7541 * Make sure we're not on PC8 state before disabling PC8, otherwise
7542 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7543 *
7544 * The other problem is that hsw_restore_lcpll() is called as part of
7545 * the runtime PM resume sequence, so we can't just call
7546 * gen6_gt_force_wake_get() because that function calls
7547 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7548 * while we are on the resume sequence. So to solve this problem we have
7549 * to call special forcewake code that doesn't touch runtime PM and
7550 * doesn't enable the forcewake delayed work.
7551 */
7552 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7553 if (dev_priv->uncore.forcewake_count++ == 0)
7554 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7555 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007556
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007557 if (val & LCPLL_POWER_DOWN_ALLOW) {
7558 val &= ~LCPLL_POWER_DOWN_ALLOW;
7559 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007560 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007561 }
7562
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007563 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007564 val |= D_COMP_COMP_FORCE;
7565 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007566 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007567
7568 val = I915_READ(LCPLL_CTL);
7569 val &= ~LCPLL_PLL_DISABLE;
7570 I915_WRITE(LCPLL_CTL, val);
7571
7572 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7573 DRM_ERROR("LCPLL not locked yet\n");
7574
7575 if (val & LCPLL_CD_SOURCE_FCLK) {
7576 val = I915_READ(LCPLL_CTL);
7577 val &= ~LCPLL_CD_SOURCE_FCLK;
7578 I915_WRITE(LCPLL_CTL, val);
7579
7580 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7581 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7582 DRM_ERROR("Switching back to LCPLL failed\n");
7583 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007584
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007585 /* See the big comment above. */
7586 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7587 if (--dev_priv->uncore.forcewake_count == 0)
7588 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7589 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007590}
7591
Paulo Zanoni765dab672014-03-07 20:08:18 -03007592/*
7593 * Package states C8 and deeper are really deep PC states that can only be
7594 * reached when all the devices on the system allow it, so even if the graphics
7595 * device allows PC8+, it doesn't mean the system will actually get to these
7596 * states. Our driver only allows PC8+ when going into runtime PM.
7597 *
7598 * The requirements for PC8+ are that all the outputs are disabled, the power
7599 * well is disabled and most interrupts are disabled, and these are also
7600 * requirements for runtime PM. When these conditions are met, we manually do
7601 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7602 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7603 * hang the machine.
7604 *
7605 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7606 * the state of some registers, so when we come back from PC8+ we need to
7607 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7608 * need to take care of the registers kept by RC6. Notice that this happens even
7609 * if we don't put the device in PCI D3 state (which is what currently happens
7610 * because of the runtime PM support).
7611 *
7612 * For more, read "Display Sequences for Package C8" on the hardware
7613 * documentation.
7614 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007615void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007616{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007617 struct drm_device *dev = dev_priv->dev;
7618 uint32_t val;
7619
Paulo Zanonic67a4702013-08-19 13:18:09 -03007620 DRM_DEBUG_KMS("Enabling package C8+\n");
7621
Paulo Zanonic67a4702013-08-19 13:18:09 -03007622 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7623 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7624 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7625 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7626 }
7627
7628 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007629 hsw_disable_lcpll(dev_priv, true, true);
7630}
7631
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007632void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007633{
7634 struct drm_device *dev = dev_priv->dev;
7635 uint32_t val;
7636
Paulo Zanonic67a4702013-08-19 13:18:09 -03007637 DRM_DEBUG_KMS("Disabling package C8+\n");
7638
7639 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007640 lpt_init_pch_refclk(dev);
7641
7642 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7643 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7644 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7645 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7646 }
7647
7648 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007649}
7650
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007651static void snb_modeset_global_resources(struct drm_device *dev)
7652{
7653 modeset_update_crtc_power_domains(dev);
7654}
7655
Imre Deak4f074122013-10-16 17:25:51 +03007656static void haswell_modeset_global_resources(struct drm_device *dev)
7657{
Paulo Zanonida723562013-12-19 11:54:51 -02007658 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007659}
7660
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007661static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007662 int x, int y,
7663 struct drm_framebuffer *fb)
7664{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007666
Paulo Zanoni566b7342013-11-25 15:27:08 -02007667 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007668 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03007669
Daniel Vetter644cef32014-04-24 23:55:07 +02007670 intel_crtc->lowfreq_avail = false;
7671
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007672 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007673}
7674
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007675static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7676 enum port port,
7677 struct intel_crtc_config *pipe_config)
7678{
7679 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7680
7681 switch (pipe_config->ddi_pll_sel) {
7682 case PORT_CLK_SEL_WRPLL1:
7683 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7684 break;
7685 case PORT_CLK_SEL_WRPLL2:
7686 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7687 break;
7688 }
7689}
7690
Daniel Vetter26804af2014-06-25 22:01:55 +03007691static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7692 struct intel_crtc_config *pipe_config)
7693{
7694 struct drm_device *dev = crtc->base.dev;
7695 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007696 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03007697 enum port port;
7698 uint32_t tmp;
7699
7700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7701
7702 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7703
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007704 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03007705
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007706 if (pipe_config->shared_dpll >= 0) {
7707 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7708
7709 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7710 &pipe_config->dpll_hw_state));
7711 }
7712
Daniel Vetter26804af2014-06-25 22:01:55 +03007713 /*
7714 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7715 * DDI E. So just check whether this pipe is wired to DDI E and whether
7716 * the PCH transcoder is on.
7717 */
7718 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7719 pipe_config->has_pch_encoder = true;
7720
7721 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7722 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7723 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7724
7725 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7726 }
7727}
7728
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007729static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7730 struct intel_crtc_config *pipe_config)
7731{
7732 struct drm_device *dev = crtc->base.dev;
7733 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007734 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007735 uint32_t tmp;
7736
Imre Deakb5482bd2014-03-05 16:20:55 +02007737 if (!intel_display_power_enabled(dev_priv,
7738 POWER_DOMAIN_PIPE(crtc->pipe)))
7739 return false;
7740
Daniel Vettere143a212013-07-04 12:01:15 +02007741 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007742 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7743
Daniel Vettereccb1402013-05-22 00:50:22 +02007744 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7745 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7746 enum pipe trans_edp_pipe;
7747 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7748 default:
7749 WARN(1, "unknown pipe linked to edp transcoder\n");
7750 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7751 case TRANS_DDI_EDP_INPUT_A_ON:
7752 trans_edp_pipe = PIPE_A;
7753 break;
7754 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7755 trans_edp_pipe = PIPE_B;
7756 break;
7757 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7758 trans_edp_pipe = PIPE_C;
7759 break;
7760 }
7761
7762 if (trans_edp_pipe == crtc->pipe)
7763 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7764 }
7765
Imre Deakda7e29b2014-02-18 00:02:02 +02007766 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007767 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007768 return false;
7769
Daniel Vettereccb1402013-05-22 00:50:22 +02007770 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007771 if (!(tmp & PIPECONF_ENABLE))
7772 return false;
7773
Daniel Vetter26804af2014-06-25 22:01:55 +03007774 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007775
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007776 intel_get_pipe_timings(crtc, pipe_config);
7777
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007778 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007779 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007780 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007781
Jesse Barnese59150d2014-01-07 13:30:45 -08007782 if (IS_HASWELL(dev))
7783 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7784 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007785
Daniel Vetter6c49f242013-06-06 12:45:25 +02007786 pipe_config->pixel_multiplier = 1;
7787
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007788 return true;
7789}
7790
Jani Nikula1a915102013-10-16 12:34:48 +03007791static struct {
7792 int clock;
7793 u32 config;
7794} hdmi_audio_clock[] = {
7795 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7796 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7797 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7798 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7799 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7800 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7801 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7802 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7803 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7804 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7805};
7806
7807/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7808static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7809{
7810 int i;
7811
7812 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7813 if (mode->clock == hdmi_audio_clock[i].clock)
7814 break;
7815 }
7816
7817 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7818 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7819 i = 1;
7820 }
7821
7822 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7823 hdmi_audio_clock[i].clock,
7824 hdmi_audio_clock[i].config);
7825
7826 return hdmi_audio_clock[i].config;
7827}
7828
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007829static bool intel_eld_uptodate(struct drm_connector *connector,
7830 int reg_eldv, uint32_t bits_eldv,
7831 int reg_elda, uint32_t bits_elda,
7832 int reg_edid)
7833{
7834 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7835 uint8_t *eld = connector->eld;
7836 uint32_t i;
7837
7838 i = I915_READ(reg_eldv);
7839 i &= bits_eldv;
7840
7841 if (!eld[0])
7842 return !i;
7843
7844 if (!i)
7845 return false;
7846
7847 i = I915_READ(reg_elda);
7848 i &= ~bits_elda;
7849 I915_WRITE(reg_elda, i);
7850
7851 for (i = 0; i < eld[2]; i++)
7852 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7853 return false;
7854
7855 return true;
7856}
7857
Wu Fengguange0dac652011-09-05 14:25:34 +08007858static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007859 struct drm_crtc *crtc,
7860 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007861{
7862 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7863 uint8_t *eld = connector->eld;
7864 uint32_t eldv;
7865 uint32_t len;
7866 uint32_t i;
7867
7868 i = I915_READ(G4X_AUD_VID_DID);
7869
7870 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7871 eldv = G4X_ELDV_DEVCL_DEVBLC;
7872 else
7873 eldv = G4X_ELDV_DEVCTG;
7874
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007875 if (intel_eld_uptodate(connector,
7876 G4X_AUD_CNTL_ST, eldv,
7877 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7878 G4X_HDMIW_HDMIEDID))
7879 return;
7880
Wu Fengguange0dac652011-09-05 14:25:34 +08007881 i = I915_READ(G4X_AUD_CNTL_ST);
7882 i &= ~(eldv | G4X_ELD_ADDR);
7883 len = (i >> 9) & 0x1f; /* ELD buffer size */
7884 I915_WRITE(G4X_AUD_CNTL_ST, i);
7885
7886 if (!eld[0])
7887 return;
7888
7889 len = min_t(uint8_t, eld[2], len);
7890 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7891 for (i = 0; i < len; i++)
7892 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7893
7894 i = I915_READ(G4X_AUD_CNTL_ST);
7895 i |= eldv;
7896 I915_WRITE(G4X_AUD_CNTL_ST, i);
7897}
7898
Wang Xingchao83358c852012-08-16 22:43:37 +08007899static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007900 struct drm_crtc *crtc,
7901 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007902{
7903 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7904 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007905 uint32_t eldv;
7906 uint32_t i;
7907 int len;
7908 int pipe = to_intel_crtc(crtc)->pipe;
7909 int tmp;
7910
7911 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7912 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7913 int aud_config = HSW_AUD_CFG(pipe);
7914 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7915
Wang Xingchao83358c852012-08-16 22:43:37 +08007916 /* Audio output enable */
7917 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7918 tmp = I915_READ(aud_cntrl_st2);
7919 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7920 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007921 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007922
Daniel Vetterc7905792014-04-16 16:56:09 +02007923 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007924
7925 /* Set ELD valid state */
7926 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007927 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007928 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7929 I915_WRITE(aud_cntrl_st2, tmp);
7930 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007931 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007932
7933 /* Enable HDMI mode */
7934 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007935 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007936 /* clear N_programing_enable and N_value_index */
7937 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7938 I915_WRITE(aud_config, tmp);
7939
7940 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7941
7942 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7943
7944 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7945 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7946 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7947 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007948 } else {
7949 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7950 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007951
7952 if (intel_eld_uptodate(connector,
7953 aud_cntrl_st2, eldv,
7954 aud_cntl_st, IBX_ELD_ADDRESS,
7955 hdmiw_hdmiedid))
7956 return;
7957
7958 i = I915_READ(aud_cntrl_st2);
7959 i &= ~eldv;
7960 I915_WRITE(aud_cntrl_st2, i);
7961
7962 if (!eld[0])
7963 return;
7964
7965 i = I915_READ(aud_cntl_st);
7966 i &= ~IBX_ELD_ADDRESS;
7967 I915_WRITE(aud_cntl_st, i);
7968 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7969 DRM_DEBUG_DRIVER("port num:%d\n", i);
7970
7971 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7972 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7973 for (i = 0; i < len; i++)
7974 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7975
7976 i = I915_READ(aud_cntrl_st2);
7977 i |= eldv;
7978 I915_WRITE(aud_cntrl_st2, i);
7979
7980}
7981
Wu Fengguange0dac652011-09-05 14:25:34 +08007982static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007983 struct drm_crtc *crtc,
7984 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007985{
7986 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7987 uint8_t *eld = connector->eld;
7988 uint32_t eldv;
7989 uint32_t i;
7990 int len;
7991 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007992 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007993 int aud_cntl_st;
7994 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007995 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007996
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007997 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007998 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7999 aud_config = IBX_AUD_CFG(pipe);
8000 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008001 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04008002 } else if (IS_VALLEYVIEW(connector->dev)) {
8003 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8004 aud_config = VLV_AUD_CFG(pipe);
8005 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8006 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08008007 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08008008 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8009 aud_config = CPT_AUD_CFG(pipe);
8010 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008011 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08008012 }
8013
Wang Xingchao9b138a82012-08-09 16:52:18 +08008014 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08008015
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04008016 if (IS_VALLEYVIEW(connector->dev)) {
8017 struct intel_encoder *intel_encoder;
8018 struct intel_digital_port *intel_dig_port;
8019
8020 intel_encoder = intel_attached_encoder(connector);
8021 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8022 i = intel_dig_port->port;
8023 } else {
8024 i = I915_READ(aud_cntl_st);
8025 i = (i >> 29) & DIP_PORT_SEL_MASK;
8026 /* DIP_Port_Select, 0x1 = PortB */
8027 }
8028
Wu Fengguange0dac652011-09-05 14:25:34 +08008029 if (!i) {
8030 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8031 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008032 eldv = IBX_ELD_VALIDB;
8033 eldv |= IBX_ELD_VALIDB << 4;
8034 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08008035 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03008036 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008037 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08008038 }
8039
Wu Fengguang3a9627f2011-12-09 20:42:19 +08008040 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8041 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8042 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06008043 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03008044 } else {
8045 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8046 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08008047
8048 if (intel_eld_uptodate(connector,
8049 aud_cntrl_st2, eldv,
8050 aud_cntl_st, IBX_ELD_ADDRESS,
8051 hdmiw_hdmiedid))
8052 return;
8053
Wu Fengguange0dac652011-09-05 14:25:34 +08008054 i = I915_READ(aud_cntrl_st2);
8055 i &= ~eldv;
8056 I915_WRITE(aud_cntrl_st2, i);
8057
8058 if (!eld[0])
8059 return;
8060
Wu Fengguange0dac652011-09-05 14:25:34 +08008061 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008062 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08008063 I915_WRITE(aud_cntl_st, i);
8064
8065 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8066 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8067 for (i = 0; i < len; i++)
8068 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8069
8070 i = I915_READ(aud_cntrl_st2);
8071 i |= eldv;
8072 I915_WRITE(aud_cntrl_st2, i);
8073}
8074
8075void intel_write_eld(struct drm_encoder *encoder,
8076 struct drm_display_mode *mode)
8077{
8078 struct drm_crtc *crtc = encoder->crtc;
8079 struct drm_connector *connector;
8080 struct drm_device *dev = encoder->dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082
8083 connector = drm_select_eld(encoder, mode);
8084 if (!connector)
8085 return;
8086
8087 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8088 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03008089 connector->name,
Wu Fengguange0dac652011-09-05 14:25:34 +08008090 connector->encoder->base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +03008091 connector->encoder->name);
Wu Fengguange0dac652011-09-05 14:25:34 +08008092
8093 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8094
8095 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03008096 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08008097}
8098
Chris Wilson560b85b2010-08-07 11:01:38 +01008099static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8100{
8101 struct drm_device *dev = crtc->dev;
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +03008104 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01008105
Ville Syrjälädc41c152014-08-13 11:57:05 +03008106 if (base) {
8107 unsigned int width = intel_crtc->cursor_width;
8108 unsigned int height = intel_crtc->cursor_height;
8109 unsigned int stride = roundup_pow_of_two(width) * 4;
8110
8111 switch (stride) {
8112 default:
8113 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8114 width, stride);
8115 stride = 256;
8116 /* fallthrough */
8117 case 256:
8118 case 512:
8119 case 1024:
8120 case 2048:
8121 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008122 }
8123
Ville Syrjälädc41c152014-08-13 11:57:05 +03008124 cntl |= CURSOR_ENABLE |
8125 CURSOR_GAMMA_ENABLE |
8126 CURSOR_FORMAT_ARGB |
8127 CURSOR_STRIDE(stride);
8128
8129 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008130 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008131
Ville Syrjälädc41c152014-08-13 11:57:05 +03008132 if (intel_crtc->cursor_cntl != 0 &&
8133 (intel_crtc->cursor_base != base ||
8134 intel_crtc->cursor_size != size ||
8135 intel_crtc->cursor_cntl != cntl)) {
8136 /* On these chipsets we can only modify the base/size/stride
8137 * whilst the cursor is disabled.
8138 */
8139 I915_WRITE(_CURACNTR, 0);
8140 POSTING_READ(_CURACNTR);
8141 intel_crtc->cursor_cntl = 0;
8142 }
8143
8144 if (intel_crtc->cursor_base != base)
8145 I915_WRITE(_CURABASE, base);
8146
8147 if (intel_crtc->cursor_size != size) {
8148 I915_WRITE(CURSIZE, size);
8149 intel_crtc->cursor_size = size;
8150 }
8151
Chris Wilson4b0e3332014-05-30 16:35:26 +03008152 if (intel_crtc->cursor_cntl != cntl) {
8153 I915_WRITE(_CURACNTR, cntl);
8154 POSTING_READ(_CURACNTR);
8155 intel_crtc->cursor_cntl = cntl;
8156 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008157}
8158
8159static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8160{
8161 struct drm_device *dev = crtc->dev;
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8164 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008165 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008166
Chris Wilson4b0e3332014-05-30 16:35:26 +03008167 cntl = 0;
8168 if (base) {
8169 cntl = MCURSOR_GAMMA_ENABLE;
8170 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308171 case 64:
8172 cntl |= CURSOR_MODE_64_ARGB_AX;
8173 break;
8174 case 128:
8175 cntl |= CURSOR_MODE_128_ARGB_AX;
8176 break;
8177 case 256:
8178 cntl |= CURSOR_MODE_256_ARGB_AX;
8179 break;
8180 default:
8181 WARN_ON(1);
8182 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008183 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008184 cntl |= pipe << 28; /* Connect to correct pipe */
Chris Wilson560b85b2010-08-07 11:01:38 +01008185 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008186 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8187 cntl |= CURSOR_PIPE_CSC_ENABLE;
8188
8189 if (intel_crtc->cursor_cntl != cntl) {
8190 I915_WRITE(CURCNTR(pipe), cntl);
8191 POSTING_READ(CURCNTR(pipe));
8192 intel_crtc->cursor_cntl = cntl;
8193 }
8194
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008195 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008196 I915_WRITE(CURBASE(pipe), base);
8197 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008198}
8199
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008200/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008201static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8202 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008203{
8204 struct drm_device *dev = crtc->dev;
8205 struct drm_i915_private *dev_priv = dev->dev_private;
8206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8207 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008208 int x = crtc->cursor_x;
8209 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008210 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008211
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008212 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008213 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008214
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008215 if (x >= intel_crtc->config.pipe_src_w)
8216 base = 0;
8217
8218 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008219 base = 0;
8220
8221 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008222 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008223 base = 0;
8224
8225 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8226 x = -x;
8227 }
8228 pos |= x << CURSOR_X_SHIFT;
8229
8230 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008231 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008232 base = 0;
8233
8234 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8235 y = -y;
8236 }
8237 pos |= y << CURSOR_Y_SHIFT;
8238
Chris Wilson4b0e3332014-05-30 16:35:26 +03008239 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008240 return;
8241
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008242 I915_WRITE(CURPOS(pipe), pos);
8243
Ville Syrjälä8ac54662014-08-12 19:39:54 +03008244 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008245 i845_update_cursor(crtc, base);
8246 else
8247 i9xx_update_cursor(crtc, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008248 intel_crtc->cursor_base = base;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008249}
8250
Ville Syrjälädc41c152014-08-13 11:57:05 +03008251static bool cursor_size_ok(struct drm_device *dev,
8252 uint32_t width, uint32_t height)
8253{
8254 if (width == 0 || height == 0)
8255 return false;
8256
8257 /*
8258 * 845g/865g are special in that they are only limited by
8259 * the width of their cursors, the height is arbitrary up to
8260 * the precision of the register. Everything else requires
8261 * square cursors, limited to a few power-of-two sizes.
8262 */
8263 if (IS_845G(dev) || IS_I865G(dev)) {
8264 if ((width & 63) != 0)
8265 return false;
8266
8267 if (width > (IS_845G(dev) ? 64 : 512))
8268 return false;
8269
8270 if (height > 1023)
8271 return false;
8272 } else {
8273 switch (width | height) {
8274 case 256:
8275 case 128:
8276 if (IS_GEN2(dev))
8277 return false;
8278 case 64:
8279 break;
8280 default:
8281 return false;
8282 }
8283 }
8284
8285 return true;
8286}
8287
Matt Ropere3287952014-06-10 08:28:12 -07008288/*
8289 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8290 *
8291 * Note that the object's reference will be consumed if the update fails. If
8292 * the update succeeds, the reference of the old object (if any) will be
8293 * consumed.
8294 */
8295static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8296 struct drm_i915_gem_object *obj,
8297 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008298{
8299 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008301 enum pipe pipe = intel_crtc->pipe;
Ville Syrjälädc41c152014-08-13 11:57:05 +03008302 unsigned old_width, stride;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008303 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008304 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008305
Jesse Barnes79e53942008-11-07 14:24:08 -08008306 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008307 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008308 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008309 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008310 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008311 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008312 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008313 }
8314
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308315 /* Check for which cursor types we support */
Ville Syrjälädc41c152014-08-13 11:57:05 +03008316 if (!cursor_size_ok(dev, width, height)) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308317 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008318 return -EINVAL;
8319 }
8320
Ville Syrjälädc41c152014-08-13 11:57:05 +03008321 stride = roundup_pow_of_two(width) * 4;
8322 if (obj->base.size < stride * height) {
Matt Ropere3287952014-06-10 08:28:12 -07008323 DRM_DEBUG_KMS("buffer is too small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008324 ret = -ENOMEM;
8325 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008326 }
8327
Dave Airlie71acb5e2008-12-30 20:31:46 +10008328 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008329 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008330 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008331 unsigned alignment;
8332
Chris Wilsond9e86c02010-11-10 16:40:20 +00008333 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008334 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008335 ret = -EINVAL;
8336 goto fail_locked;
8337 }
8338
Chris Wilson693db182013-03-05 14:52:39 +00008339 /* Note that the w/a also requires 2 PTE of padding following
8340 * the bo. We currently fill all unused PTE with the shadow
8341 * page and so we should always have valid PTE following the
8342 * cursor preventing the VT-d warning.
8343 */
8344 alignment = 0;
8345 if (need_vtd_wa(dev))
8346 alignment = 64*1024;
8347
8348 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008349 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008350 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008351 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008352 }
8353
Chris Wilsond9e86c02010-11-10 16:40:20 +00008354 ret = i915_gem_object_put_fence(obj);
8355 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008356 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008357 goto fail_unpin;
8358 }
8359
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008360 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008361 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008362 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008363 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008364 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008365 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008366 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008367 }
Chris Wilson00731152014-05-21 12:42:56 +01008368 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008369 }
8370
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008371 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008372 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008373 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008374 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008375 }
Jesse Barnes80824002009-09-10 15:28:06 -07008376
Daniel Vettera071fa02014-06-18 23:28:09 +02008377 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8378 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008379 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008380
Chris Wilson64f962e2014-03-26 12:38:15 +00008381 old_width = intel_crtc->cursor_width;
8382
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008383 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008384 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008385 intel_crtc->cursor_width = width;
8386 intel_crtc->cursor_height = height;
8387
Chris Wilson64f962e2014-03-26 12:38:15 +00008388 if (intel_crtc->active) {
8389 if (old_width != width)
8390 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f7712013-09-17 18:33:44 +03008391 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008392 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008393
Daniel Vetterf99d7062014-06-19 16:01:59 +02008394 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8395
Jesse Barnes79e53942008-11-07 14:24:08 -08008396 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008397fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008398 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008399fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008400 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008401fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008402 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008403 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008404}
8405
Jesse Barnes79e53942008-11-07 14:24:08 -08008406static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008407 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008408{
James Simmons72034252010-08-03 01:33:19 +01008409 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008411
James Simmons72034252010-08-03 01:33:19 +01008412 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008413 intel_crtc->lut_r[i] = red[i] >> 8;
8414 intel_crtc->lut_g[i] = green[i] >> 8;
8415 intel_crtc->lut_b[i] = blue[i] >> 8;
8416 }
8417
8418 intel_crtc_load_lut(crtc);
8419}
8420
Jesse Barnes79e53942008-11-07 14:24:08 -08008421/* VESA 640x480x72Hz mode to set on the pipe */
8422static struct drm_display_mode load_detect_mode = {
8423 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8424 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8425};
8426
Daniel Vettera8bb6812014-02-10 18:00:39 +01008427struct drm_framebuffer *
8428__intel_framebuffer_create(struct drm_device *dev,
8429 struct drm_mode_fb_cmd2 *mode_cmd,
8430 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008431{
8432 struct intel_framebuffer *intel_fb;
8433 int ret;
8434
8435 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8436 if (!intel_fb) {
8437 drm_gem_object_unreference_unlocked(&obj->base);
8438 return ERR_PTR(-ENOMEM);
8439 }
8440
8441 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008442 if (ret)
8443 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008444
8445 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008446err:
8447 drm_gem_object_unreference_unlocked(&obj->base);
8448 kfree(intel_fb);
8449
8450 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008451}
8452
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008453static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008454intel_framebuffer_create(struct drm_device *dev,
8455 struct drm_mode_fb_cmd2 *mode_cmd,
8456 struct drm_i915_gem_object *obj)
8457{
8458 struct drm_framebuffer *fb;
8459 int ret;
8460
8461 ret = i915_mutex_lock_interruptible(dev);
8462 if (ret)
8463 return ERR_PTR(ret);
8464 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8465 mutex_unlock(&dev->struct_mutex);
8466
8467 return fb;
8468}
8469
Chris Wilsond2dff872011-04-19 08:36:26 +01008470static u32
8471intel_framebuffer_pitch_for_width(int width, int bpp)
8472{
8473 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8474 return ALIGN(pitch, 64);
8475}
8476
8477static u32
8478intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8479{
8480 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008481 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008482}
8483
8484static struct drm_framebuffer *
8485intel_framebuffer_create_for_mode(struct drm_device *dev,
8486 struct drm_display_mode *mode,
8487 int depth, int bpp)
8488{
8489 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008490 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008491
8492 obj = i915_gem_alloc_object(dev,
8493 intel_framebuffer_size_for_mode(mode, bpp));
8494 if (obj == NULL)
8495 return ERR_PTR(-ENOMEM);
8496
8497 mode_cmd.width = mode->hdisplay;
8498 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008499 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8500 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008501 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008502
8503 return intel_framebuffer_create(dev, &mode_cmd, obj);
8504}
8505
8506static struct drm_framebuffer *
8507mode_fits_in_fbdev(struct drm_device *dev,
8508 struct drm_display_mode *mode)
8509{
Daniel Vetter4520f532013-10-09 09:18:51 +02008510#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008511 struct drm_i915_private *dev_priv = dev->dev_private;
8512 struct drm_i915_gem_object *obj;
8513 struct drm_framebuffer *fb;
8514
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008515 if (!dev_priv->fbdev)
8516 return NULL;
8517
8518 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008519 return NULL;
8520
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008521 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008522 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008523
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008524 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008525 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8526 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008527 return NULL;
8528
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008529 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008530 return NULL;
8531
8532 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008533#else
8534 return NULL;
8535#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008536}
8537
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008538bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008539 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008540 struct intel_load_detect_pipe *old,
8541 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008542{
8543 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008544 struct intel_encoder *intel_encoder =
8545 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008546 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008547 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008548 struct drm_crtc *crtc = NULL;
8549 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008550 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008551 struct drm_mode_config *config = &dev->mode_config;
8552 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008553
Chris Wilsond2dff872011-04-19 08:36:26 +01008554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008555 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +03008556 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008557
Rob Clark51fd3712013-11-19 12:10:12 -05008558retry:
8559 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8560 if (ret)
8561 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008562
Jesse Barnes79e53942008-11-07 14:24:08 -08008563 /*
8564 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008565 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008566 * - if the connector already has an assigned crtc, use it (but make
8567 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008568 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008569 * - try to find the first unused crtc that can drive this connector,
8570 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008571 */
8572
8573 /* See if we already have a CRTC for this connector */
8574 if (encoder->crtc) {
8575 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008576
Rob Clark51fd3712013-11-19 12:10:12 -05008577 ret = drm_modeset_lock(&crtc->mutex, ctx);
8578 if (ret)
8579 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008580
Daniel Vetter24218aa2012-08-12 19:27:11 +02008581 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008582 old->load_detect_temp = false;
8583
8584 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008585 if (connector->dpms != DRM_MODE_DPMS_ON)
8586 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008587
Chris Wilson71731882011-04-19 23:10:58 +01008588 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008589 }
8590
8591 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008592 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008593 i++;
8594 if (!(encoder->possible_crtcs & (1 << i)))
8595 continue;
Ville Syrjäläa4592492014-08-11 13:15:36 +03008596 if (possible_crtc->enabled)
8597 continue;
8598 /* This can occur when applying the pipe A quirk on resume. */
8599 if (to_intel_crtc(possible_crtc)->new_enabled)
8600 continue;
8601
8602 crtc = possible_crtc;
8603 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08008604 }
8605
8606 /*
8607 * If we didn't find an unused CRTC, don't use any.
8608 */
8609 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008610 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008611 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008612 }
8613
Rob Clark51fd3712013-11-19 12:10:12 -05008614 ret = drm_modeset_lock(&crtc->mutex, ctx);
8615 if (ret)
8616 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008617 intel_encoder->new_crtc = to_intel_crtc(crtc);
8618 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008619
8620 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008621 intel_crtc->new_enabled = true;
8622 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008623 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008624 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008625 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008626
Chris Wilson64927112011-04-20 07:25:26 +01008627 if (!mode)
8628 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008629
Chris Wilsond2dff872011-04-19 08:36:26 +01008630 /* We need a framebuffer large enough to accommodate all accesses
8631 * that the plane may generate whilst we perform load detection.
8632 * We can not rely on the fbcon either being present (we get called
8633 * during its initialisation to detect all boot displays, or it may
8634 * not even exist) or that it is large enough to satisfy the
8635 * requested mode.
8636 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008637 fb = mode_fits_in_fbdev(dev, mode);
8638 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008639 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008640 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8641 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008642 } else
8643 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008644 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008645 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008646 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008647 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008648
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008649 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008650 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008651 if (old->release_fb)
8652 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008653 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008654 }
Chris Wilson71731882011-04-19 23:10:58 +01008655
Jesse Barnes79e53942008-11-07 14:24:08 -08008656 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008657 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008658 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008659
8660 fail:
8661 intel_crtc->new_enabled = crtc->enabled;
8662 if (intel_crtc->new_enabled)
8663 intel_crtc->new_config = &intel_crtc->config;
8664 else
8665 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008666fail_unlock:
8667 if (ret == -EDEADLK) {
8668 drm_modeset_backoff(ctx);
8669 goto retry;
8670 }
8671
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008672 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008673}
8674
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008675void intel_release_load_detect_pipe(struct drm_connector *connector,
Ville Syrjälä208bf9f2014-08-11 13:15:35 +03008676 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008677{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008678 struct intel_encoder *intel_encoder =
8679 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008680 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008681 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008683
Chris Wilsond2dff872011-04-19 08:36:26 +01008684 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008685 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +03008686 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008687
Chris Wilson8261b192011-04-19 23:18:09 +01008688 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008689 to_intel_connector(connector)->new_encoder = NULL;
8690 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008691 intel_crtc->new_enabled = false;
8692 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008693 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008694
Daniel Vetter36206362012-12-10 20:42:17 +01008695 if (old->release_fb) {
8696 drm_framebuffer_unregister_private(old->release_fb);
8697 drm_framebuffer_unreference(old->release_fb);
8698 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008699
Chris Wilson0622a532011-04-21 09:32:11 +01008700 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008701 }
8702
Eric Anholtc751ce42010-03-25 11:48:48 -07008703 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008704 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8705 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008706}
8707
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008708static int i9xx_pll_refclk(struct drm_device *dev,
8709 const struct intel_crtc_config *pipe_config)
8710{
8711 struct drm_i915_private *dev_priv = dev->dev_private;
8712 u32 dpll = pipe_config->dpll_hw_state.dpll;
8713
8714 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008715 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008716 else if (HAS_PCH_SPLIT(dev))
8717 return 120000;
8718 else if (!IS_GEN2(dev))
8719 return 96000;
8720 else
8721 return 48000;
8722}
8723
Jesse Barnes79e53942008-11-07 14:24:08 -08008724/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008725static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8726 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008727{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008728 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008729 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008730 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008731 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008732 u32 fp;
8733 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008734 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008735
8736 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008737 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008738 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008739 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008740
8741 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008742 if (IS_PINEVIEW(dev)) {
8743 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8744 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008745 } else {
8746 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8747 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8748 }
8749
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008750 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008751 if (IS_PINEVIEW(dev))
8752 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8753 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008754 else
8755 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008756 DPLL_FPA01_P1_POST_DIV_SHIFT);
8757
8758 switch (dpll & DPLL_MODE_MASK) {
8759 case DPLLB_MODE_DAC_SERIAL:
8760 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8761 5 : 10;
8762 break;
8763 case DPLLB_MODE_LVDS:
8764 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8765 7 : 14;
8766 break;
8767 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008768 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008769 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008770 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008771 }
8772
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008773 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008774 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008775 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008776 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008777 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008778 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008779 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008780
8781 if (is_lvds) {
8782 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8783 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008784
8785 if (lvds & LVDS_CLKB_POWER_UP)
8786 clock.p2 = 7;
8787 else
8788 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008789 } else {
8790 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8791 clock.p1 = 2;
8792 else {
8793 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8794 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8795 }
8796 if (dpll & PLL_P2_DIVIDE_BY_4)
8797 clock.p2 = 4;
8798 else
8799 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008800 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008801
8802 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008803 }
8804
Ville Syrjälä18442d02013-09-13 16:00:08 +03008805 /*
8806 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008807 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008808 * encoder's get_config() function.
8809 */
8810 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008811}
8812
Ville Syrjälä6878da02013-09-13 15:59:11 +03008813int intel_dotclock_calculate(int link_freq,
8814 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008815{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008816 /*
8817 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008818 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008819 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008820 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008821 *
8822 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008823 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008824 */
8825
Ville Syrjälä6878da02013-09-13 15:59:11 +03008826 if (!m_n->link_n)
8827 return 0;
8828
8829 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8830}
8831
Ville Syrjälä18442d02013-09-13 16:00:08 +03008832static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8833 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008834{
8835 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008836
8837 /* read out port_clock from the DPLL */
8838 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008839
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008840 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008841 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008842 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008843 * agree once we know their relationship in the encoder's
8844 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008845 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008846 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008847 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8848 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008849}
8850
8851/** Returns the currently programmed mode of the given pipe. */
8852struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8853 struct drm_crtc *crtc)
8854{
Jesse Barnes548f2452011-02-17 10:40:53 -08008855 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008857 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008858 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008859 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008860 int htot = I915_READ(HTOTAL(cpu_transcoder));
8861 int hsync = I915_READ(HSYNC(cpu_transcoder));
8862 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8863 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008864 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008865
8866 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8867 if (!mode)
8868 return NULL;
8869
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008870 /*
8871 * Construct a pipe_config sufficient for getting the clock info
8872 * back out of crtc_clock_get.
8873 *
8874 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8875 * to use a real value here instead.
8876 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008877 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008878 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008879 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8880 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8881 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008882 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8883
Ville Syrjälä773ae032013-09-23 17:48:20 +03008884 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008885 mode->hdisplay = (htot & 0xffff) + 1;
8886 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8887 mode->hsync_start = (hsync & 0xffff) + 1;
8888 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8889 mode->vdisplay = (vtot & 0xffff) + 1;
8890 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8891 mode->vsync_start = (vsync & 0xffff) + 1;
8892 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8893
8894 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008895
8896 return mode;
8897}
8898
Daniel Vettercc365132014-06-18 13:59:13 +02008899static void intel_increase_pllclock(struct drm_device *dev,
8900 enum pipe pipe)
Jesse Barnes652c3932009-08-17 13:31:43 -07008901{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008902 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008903 int dpll_reg = DPLL(pipe);
8904 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008905
Sonika Jindalbaff2962014-07-22 11:16:35 +05308906 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008907 return;
8908
8909 if (!dev_priv->lvds_downclock_avail)
8910 return;
8911
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008912 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008913 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008914 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008915
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008916 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008917
8918 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8919 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008920 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008921
Jesse Barnes652c3932009-08-17 13:31:43 -07008922 dpll = I915_READ(dpll_reg);
8923 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008924 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008925 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008926}
8927
8928static void intel_decrease_pllclock(struct drm_crtc *crtc)
8929{
8930 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008931 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008933
Sonika Jindalbaff2962014-07-22 11:16:35 +05308934 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008935 return;
8936
8937 if (!dev_priv->lvds_downclock_avail)
8938 return;
8939
8940 /*
8941 * Since this is called by a timer, we should never get here in
8942 * the manual case.
8943 */
8944 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008945 int pipe = intel_crtc->pipe;
8946 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008947 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008948
Zhao Yakui44d98a62009-10-09 11:39:40 +08008949 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008950
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008951 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008952
Chris Wilson074b5e12012-05-02 12:07:06 +01008953 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008954 dpll |= DISPLAY_RATE_SELECT_FPA1;
8955 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008956 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008957 dpll = I915_READ(dpll_reg);
8958 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008959 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008960 }
8961
8962}
8963
Chris Wilsonf047e392012-07-21 12:31:41 +01008964void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008965{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008966 struct drm_i915_private *dev_priv = dev->dev_private;
8967
Chris Wilsonf62a0072014-02-21 17:55:39 +00008968 if (dev_priv->mm.busy)
8969 return;
8970
Paulo Zanoni43694d62014-03-07 20:08:08 -03008971 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008972 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008973 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008974}
8975
8976void intel_mark_idle(struct drm_device *dev)
8977{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008978 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008979 struct drm_crtc *crtc;
8980
Chris Wilsonf62a0072014-02-21 17:55:39 +00008981 if (!dev_priv->mm.busy)
8982 return;
8983
8984 dev_priv->mm.busy = false;
8985
Jani Nikulad330a952014-01-21 11:24:25 +02008986 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008987 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008988
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008989 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008990 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008991 continue;
8992
8993 intel_decrease_pllclock(crtc);
8994 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008995
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008996 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008997 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008998
8999out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03009000 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01009001}
9002
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07009003
Daniel Vetterf99d7062014-06-19 16:01:59 +02009004/**
9005 * intel_mark_fb_busy - mark given planes as busy
9006 * @dev: DRM device
9007 * @frontbuffer_bits: bits for the affected planes
9008 * @ring: optional ring for asynchronous commands
9009 *
9010 * This function gets called every time the screen contents change. It can be
9011 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9012 */
9013static void intel_mark_fb_busy(struct drm_device *dev,
9014 unsigned frontbuffer_bits,
9015 struct intel_engine_cs *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01009016{
Damien Lespiau055e3932014-08-18 13:49:10 +01009017 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettercc365132014-06-18 13:59:13 +02009018 enum pipe pipe;
Jesse Barnes652c3932009-08-17 13:31:43 -07009019
Jani Nikulad330a952014-01-21 11:24:25 +02009020 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07009021 return;
9022
Damien Lespiau055e3932014-08-18 13:49:10 +01009023 for_each_pipe(dev_priv, pipe) {
Daniel Vetterf99d7062014-06-19 16:01:59 +02009024 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
Jesse Barnes652c3932009-08-17 13:31:43 -07009025 continue;
9026
Daniel Vettercc365132014-06-18 13:59:13 +02009027 intel_increase_pllclock(dev, pipe);
Chris Wilsonc65355b2013-06-06 16:53:41 -03009028 if (ring && intel_fbc_enabled(dev))
9029 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07009030 }
Jesse Barnes652c3932009-08-17 13:31:43 -07009031}
9032
Daniel Vetterf99d7062014-06-19 16:01:59 +02009033/**
9034 * intel_fb_obj_invalidate - invalidate frontbuffer object
9035 * @obj: GEM object to invalidate
9036 * @ring: set for asynchronous rendering
9037 *
9038 * This function gets called every time rendering on the given object starts and
9039 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9040 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9041 * until the rendering completes or a flip on this frontbuffer plane is
9042 * scheduled.
9043 */
9044void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9045 struct intel_engine_cs *ring)
9046{
9047 struct drm_device *dev = obj->base.dev;
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049
9050 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9051
9052 if (!obj->frontbuffer_bits)
9053 return;
9054
9055 if (ring) {
9056 mutex_lock(&dev_priv->fb_tracking.lock);
9057 dev_priv->fb_tracking.busy_bits
9058 |= obj->frontbuffer_bits;
9059 dev_priv->fb_tracking.flip_bits
9060 &= ~obj->frontbuffer_bits;
9061 mutex_unlock(&dev_priv->fb_tracking.lock);
9062 }
9063
9064 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9065
Daniel Vetter9ca15302014-07-11 10:30:16 -07009066 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009067}
9068
9069/**
9070 * intel_frontbuffer_flush - flush frontbuffer
9071 * @dev: DRM device
9072 * @frontbuffer_bits: frontbuffer plane tracking bits
9073 *
9074 * This function gets called every time rendering on the given planes has
9075 * completed and frontbuffer caching can be started again. Flushes will get
9076 * delayed if they're blocked by some oustanding asynchronous rendering.
9077 *
9078 * Can be called without any locks held.
9079 */
9080void intel_frontbuffer_flush(struct drm_device *dev,
9081 unsigned frontbuffer_bits)
9082{
9083 struct drm_i915_private *dev_priv = dev->dev_private;
9084
9085 /* Delay flushing when rings are still busy.*/
9086 mutex_lock(&dev_priv->fb_tracking.lock);
9087 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9088 mutex_unlock(&dev_priv->fb_tracking.lock);
9089
9090 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9091
Daniel Vetter9ca15302014-07-11 10:30:16 -07009092 intel_edp_psr_flush(dev, frontbuffer_bits);
Rodrigo Vivic5ad0112014-08-04 03:51:38 -07009093
9094 if (IS_GEN8(dev))
9095 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009096}
9097
9098/**
9099 * intel_fb_obj_flush - flush frontbuffer object
9100 * @obj: GEM object to flush
9101 * @retire: set when retiring asynchronous rendering
9102 *
9103 * This function gets called every time rendering on the given object has
9104 * completed and frontbuffer caching can be started again. If @retire is true
9105 * then any delayed flushes will be unblocked.
9106 */
9107void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9108 bool retire)
9109{
9110 struct drm_device *dev = obj->base.dev;
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112 unsigned frontbuffer_bits;
9113
9114 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9115
9116 if (!obj->frontbuffer_bits)
9117 return;
9118
9119 frontbuffer_bits = obj->frontbuffer_bits;
9120
9121 if (retire) {
9122 mutex_lock(&dev_priv->fb_tracking.lock);
9123 /* Filter out new bits since rendering started. */
9124 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9125
9126 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9127 mutex_unlock(&dev_priv->fb_tracking.lock);
9128 }
9129
9130 intel_frontbuffer_flush(dev, frontbuffer_bits);
9131}
9132
9133/**
9134 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9135 * @dev: DRM device
9136 * @frontbuffer_bits: frontbuffer plane tracking bits
9137 *
9138 * This function gets called after scheduling a flip on @obj. The actual
9139 * frontbuffer flushing will be delayed until completion is signalled with
9140 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9141 * flush will be cancelled.
9142 *
9143 * Can be called without any locks held.
9144 */
9145void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9146 unsigned frontbuffer_bits)
9147{
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9149
9150 mutex_lock(&dev_priv->fb_tracking.lock);
9151 dev_priv->fb_tracking.flip_bits
9152 |= frontbuffer_bits;
9153 mutex_unlock(&dev_priv->fb_tracking.lock);
9154}
9155
9156/**
9157 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9158 * @dev: DRM device
9159 * @frontbuffer_bits: frontbuffer plane tracking bits
9160 *
9161 * This function gets called after the flip has been latched and will complete
9162 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9163 *
9164 * Can be called without any locks held.
9165 */
9166void intel_frontbuffer_flip_complete(struct drm_device *dev,
9167 unsigned frontbuffer_bits)
9168{
9169 struct drm_i915_private *dev_priv = dev->dev_private;
9170
9171 mutex_lock(&dev_priv->fb_tracking.lock);
9172 /* Mask any cancelled flips. */
9173 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9174 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9175 mutex_unlock(&dev_priv->fb_tracking.lock);
9176
9177 intel_frontbuffer_flush(dev, frontbuffer_bits);
9178}
9179
Jesse Barnes79e53942008-11-07 14:24:08 -08009180static void intel_crtc_destroy(struct drm_crtc *crtc)
9181{
9182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009183 struct drm_device *dev = crtc->dev;
9184 struct intel_unpin_work *work;
9185 unsigned long flags;
9186
9187 spin_lock_irqsave(&dev->event_lock, flags);
9188 work = intel_crtc->unpin_work;
9189 intel_crtc->unpin_work = NULL;
9190 spin_unlock_irqrestore(&dev->event_lock, flags);
9191
9192 if (work) {
9193 cancel_work_sync(&work->work);
9194 kfree(work);
9195 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009196
9197 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009198
Jesse Barnes79e53942008-11-07 14:24:08 -08009199 kfree(intel_crtc);
9200}
9201
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009202static void intel_unpin_work_fn(struct work_struct *__work)
9203{
9204 struct intel_unpin_work *work =
9205 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009206 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02009207 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009208
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009209 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01009210 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00009211 drm_gem_object_unreference(&work->pending_flip_obj->base);
9212 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00009213
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009214 intel_update_fbc(dev);
9215 mutex_unlock(&dev->struct_mutex);
9216
Daniel Vetterf99d7062014-06-19 16:01:59 +02009217 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9218
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009219 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9220 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9221
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009222 kfree(work);
9223}
9224
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009225static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009226 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009227{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009228 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9230 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009231 unsigned long flags;
9232
9233 /* Ignore early vblank irqs */
9234 if (intel_crtc == NULL)
9235 return;
9236
9237 spin_lock_irqsave(&dev->event_lock, flags);
9238 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009239
9240 /* Ensure we don't miss a work->pending update ... */
9241 smp_rmb();
9242
9243 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009244 spin_unlock_irqrestore(&dev->event_lock, flags);
9245 return;
9246 }
9247
Chris Wilsone7d841c2012-12-03 11:36:30 +00009248 /* and that the unpin work is consistent wrt ->pending. */
9249 smp_rmb();
9250
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009251 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009252
Rob Clark45a066e2012-10-08 14:50:40 -05009253 if (work->event)
9254 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009255
Daniel Vetter87b6b102014-05-15 15:33:46 +02009256 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009257
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009258 spin_unlock_irqrestore(&dev->event_lock, flags);
9259
Daniel Vetter2c10d572012-12-20 21:24:07 +01009260 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009261
9262 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07009263
9264 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009265}
9266
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009267void intel_finish_page_flip(struct drm_device *dev, int pipe)
9268{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009269 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009270 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9271
Mario Kleiner49b14a52010-12-09 07:00:07 +01009272 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009273}
9274
9275void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9276{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009277 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009278 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9279
Mario Kleiner49b14a52010-12-09 07:00:07 +01009280 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009281}
9282
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009283/* Is 'a' after or equal to 'b'? */
9284static bool g4x_flip_count_after_eq(u32 a, u32 b)
9285{
9286 return !((a - b) & 0x80000000);
9287}
9288
9289static bool page_flip_finished(struct intel_crtc *crtc)
9290{
9291 struct drm_device *dev = crtc->base.dev;
9292 struct drm_i915_private *dev_priv = dev->dev_private;
9293
9294 /*
9295 * The relevant registers doen't exist on pre-ctg.
9296 * As the flip done interrupt doesn't trigger for mmio
9297 * flips on gmch platforms, a flip count check isn't
9298 * really needed there. But since ctg has the registers,
9299 * include it in the check anyway.
9300 */
9301 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9302 return true;
9303
9304 /*
9305 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9306 * used the same base address. In that case the mmio flip might
9307 * have completed, but the CS hasn't even executed the flip yet.
9308 *
9309 * A flip count check isn't enough as the CS might have updated
9310 * the base address just after start of vblank, but before we
9311 * managed to process the interrupt. This means we'd complete the
9312 * CS flip too soon.
9313 *
9314 * Combining both checks should get us a good enough result. It may
9315 * still happen that the CS flip has been executed, but has not
9316 * yet actually completed. But in case the base address is the same
9317 * anyway, we don't really care.
9318 */
9319 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9320 crtc->unpin_work->gtt_offset &&
9321 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9322 crtc->unpin_work->flip_count);
9323}
9324
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009325void intel_prepare_page_flip(struct drm_device *dev, int plane)
9326{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009327 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009328 struct intel_crtc *intel_crtc =
9329 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9330 unsigned long flags;
9331
Chris Wilsone7d841c2012-12-03 11:36:30 +00009332 /* NB: An MMIO update of the plane base pointer will also
9333 * generate a page-flip completion irq, i.e. every modeset
9334 * is also accompanied by a spurious intel_prepare_page_flip().
9335 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009336 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009337 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009338 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009339 spin_unlock_irqrestore(&dev->event_lock, flags);
9340}
9341
Robin Schroereba905b2014-05-18 02:24:50 +02009342static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009343{
9344 /* Ensure that the work item is consistent when activating it ... */
9345 smp_wmb();
9346 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9347 /* and that it is marked active as soon as the irq could fire. */
9348 smp_wmb();
9349}
9350
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009351static int intel_gen2_queue_flip(struct drm_device *dev,
9352 struct drm_crtc *crtc,
9353 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009354 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009355 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009356 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009357{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009359 u32 flip_mask;
9360 int ret;
9361
Daniel Vetter6d90c952012-04-26 23:28:05 +02009362 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009363 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009364 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009365
9366 /* Can't queue multiple flips, so wait for the previous
9367 * one to finish before executing the next.
9368 */
9369 if (intel_crtc->plane)
9370 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9371 else
9372 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009373 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9374 intel_ring_emit(ring, MI_NOOP);
9375 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9376 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9377 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009378 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009379 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009380
9381 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009382 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009383 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009384}
9385
9386static int intel_gen3_queue_flip(struct drm_device *dev,
9387 struct drm_crtc *crtc,
9388 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009389 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009390 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009391 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009392{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009394 u32 flip_mask;
9395 int ret;
9396
Daniel Vetter6d90c952012-04-26 23:28:05 +02009397 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009398 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009399 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009400
9401 if (intel_crtc->plane)
9402 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9403 else
9404 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009405 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9406 intel_ring_emit(ring, MI_NOOP);
9407 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9408 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9409 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009410 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009411 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009412
Chris Wilsone7d841c2012-12-03 11:36:30 +00009413 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009414 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009415 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009416}
9417
9418static int intel_gen4_queue_flip(struct drm_device *dev,
9419 struct drm_crtc *crtc,
9420 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009421 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009422 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009423 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009424{
9425 struct drm_i915_private *dev_priv = dev->dev_private;
9426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9427 uint32_t pf, pipesrc;
9428 int ret;
9429
Daniel Vetter6d90c952012-04-26 23:28:05 +02009430 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009431 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009432 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009433
9434 /* i965+ uses the linear or tiled offsets from the
9435 * Display Registers (which do not change across a page-flip)
9436 * so we need only reprogram the base address.
9437 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009438 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9439 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9440 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009441 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009442 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009443
9444 /* XXX Enabling the panel-fitter across page-flip is so far
9445 * untested on non-native modes, so ignore it for now.
9446 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9447 */
9448 pf = 0;
9449 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009450 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009451
9452 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009453 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009454 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009455}
9456
9457static int intel_gen6_queue_flip(struct drm_device *dev,
9458 struct drm_crtc *crtc,
9459 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009460 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009461 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009462 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009463{
9464 struct drm_i915_private *dev_priv = dev->dev_private;
9465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9466 uint32_t pf, pipesrc;
9467 int ret;
9468
Daniel Vetter6d90c952012-04-26 23:28:05 +02009469 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009470 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009471 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009472
Daniel Vetter6d90c952012-04-26 23:28:05 +02009473 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9474 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9475 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009476 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009477
Chris Wilson99d9acd2012-04-17 20:37:00 +01009478 /* Contrary to the suggestions in the documentation,
9479 * "Enable Panel Fitter" does not seem to be required when page
9480 * flipping with a non-native mode, and worse causes a normal
9481 * modeset to fail.
9482 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9483 */
9484 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009485 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009486 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009487
9488 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009489 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009490 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009491}
9492
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009493static int intel_gen7_queue_flip(struct drm_device *dev,
9494 struct drm_crtc *crtc,
9495 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009496 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009497 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009498 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009499{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009501 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009502 int len, ret;
9503
Robin Schroereba905b2014-05-18 02:24:50 +02009504 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009505 case PLANE_A:
9506 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9507 break;
9508 case PLANE_B:
9509 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9510 break;
9511 case PLANE_C:
9512 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9513 break;
9514 default:
9515 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009516 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009517 }
9518
Chris Wilsonffe74d72013-08-26 20:58:12 +01009519 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009520 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009521 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009522 /*
9523 * On Gen 8, SRM is now taking an extra dword to accommodate
9524 * 48bits addresses, and we need a NOOP for the batch size to
9525 * stay even.
9526 */
9527 if (IS_GEN8(dev))
9528 len += 2;
9529 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009530
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009531 /*
9532 * BSpec MI_DISPLAY_FLIP for IVB:
9533 * "The full packet must be contained within the same cache line."
9534 *
9535 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9536 * cacheline, if we ever start emitting more commands before
9537 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9538 * then do the cacheline alignment, and finally emit the
9539 * MI_DISPLAY_FLIP.
9540 */
9541 ret = intel_ring_cacheline_align(ring);
9542 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009543 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009544
Chris Wilsonffe74d72013-08-26 20:58:12 +01009545 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009546 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009547 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009548
Chris Wilsonffe74d72013-08-26 20:58:12 +01009549 /* Unmask the flip-done completion message. Note that the bspec says that
9550 * we should do this for both the BCS and RCS, and that we must not unmask
9551 * more than one flip event at any time (or ensure that one flip message
9552 * can be sent by waiting for flip-done prior to queueing new flips).
9553 * Experimentation says that BCS works despite DERRMR masking all
9554 * flip-done completion events and that unmasking all planes at once
9555 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9556 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9557 */
9558 if (ring->id == RCS) {
9559 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9560 intel_ring_emit(ring, DERRMR);
9561 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9562 DERRMR_PIPEB_PRI_FLIP_DONE |
9563 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009564 if (IS_GEN8(dev))
9565 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9566 MI_SRM_LRM_GLOBAL_GTT);
9567 else
9568 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9569 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009570 intel_ring_emit(ring, DERRMR);
9571 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009572 if (IS_GEN8(dev)) {
9573 intel_ring_emit(ring, 0);
9574 intel_ring_emit(ring, MI_NOOP);
9575 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009576 }
9577
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009578 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009579 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009580 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009581 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009582
9583 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009584 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009585 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009586}
9587
Sourab Gupta84c33a62014-06-02 16:47:17 +05309588static bool use_mmio_flip(struct intel_engine_cs *ring,
9589 struct drm_i915_gem_object *obj)
9590{
9591 /*
9592 * This is not being used for older platforms, because
9593 * non-availability of flip done interrupt forces us to use
9594 * CS flips. Older platforms derive flip done using some clever
9595 * tricks involving the flip_pending status bits and vblank irqs.
9596 * So using MMIO flips there would disrupt this mechanism.
9597 */
9598
Chris Wilson8e09bf82014-07-08 10:40:30 +01009599 if (ring == NULL)
9600 return true;
9601
Sourab Gupta84c33a62014-06-02 16:47:17 +05309602 if (INTEL_INFO(ring->dev)->gen < 5)
9603 return false;
9604
9605 if (i915.use_mmio_flip < 0)
9606 return false;
9607 else if (i915.use_mmio_flip > 0)
9608 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +01009609 else if (i915.enable_execlists)
9610 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309611 else
9612 return ring != obj->ring;
9613}
9614
9615static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9616{
9617 struct drm_device *dev = intel_crtc->base.dev;
9618 struct drm_i915_private *dev_priv = dev->dev_private;
9619 struct intel_framebuffer *intel_fb =
9620 to_intel_framebuffer(intel_crtc->base.primary->fb);
9621 struct drm_i915_gem_object *obj = intel_fb->obj;
9622 u32 dspcntr;
9623 u32 reg;
9624
9625 intel_mark_page_flip_active(intel_crtc);
9626
9627 reg = DSPCNTR(intel_crtc->plane);
9628 dspcntr = I915_READ(reg);
9629
9630 if (INTEL_INFO(dev)->gen >= 4) {
9631 if (obj->tiling_mode != I915_TILING_NONE)
9632 dspcntr |= DISPPLANE_TILED;
9633 else
9634 dspcntr &= ~DISPPLANE_TILED;
9635 }
9636 I915_WRITE(reg, dspcntr);
9637
9638 I915_WRITE(DSPSURF(intel_crtc->plane),
9639 intel_crtc->unpin_work->gtt_offset);
9640 POSTING_READ(DSPSURF(intel_crtc->plane));
9641}
9642
9643static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9644{
9645 struct intel_engine_cs *ring;
9646 int ret;
9647
9648 lockdep_assert_held(&obj->base.dev->struct_mutex);
9649
9650 if (!obj->last_write_seqno)
9651 return 0;
9652
9653 ring = obj->ring;
9654
9655 if (i915_seqno_passed(ring->get_seqno(ring, true),
9656 obj->last_write_seqno))
9657 return 0;
9658
9659 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9660 if (ret)
9661 return ret;
9662
9663 if (WARN_ON(!ring->irq_get(ring)))
9664 return 0;
9665
9666 return 1;
9667}
9668
9669void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9670{
9671 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9672 struct intel_crtc *intel_crtc;
9673 unsigned long irq_flags;
9674 u32 seqno;
9675
9676 seqno = ring->get_seqno(ring, false);
9677
9678 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9679 for_each_intel_crtc(ring->dev, intel_crtc) {
9680 struct intel_mmio_flip *mmio_flip;
9681
9682 mmio_flip = &intel_crtc->mmio_flip;
9683 if (mmio_flip->seqno == 0)
9684 continue;
9685
9686 if (ring->id != mmio_flip->ring_id)
9687 continue;
9688
9689 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9690 intel_do_mmio_flip(intel_crtc);
9691 mmio_flip->seqno = 0;
9692 ring->irq_put(ring);
9693 }
9694 }
9695 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9696}
9697
9698static int intel_queue_mmio_flip(struct drm_device *dev,
9699 struct drm_crtc *crtc,
9700 struct drm_framebuffer *fb,
9701 struct drm_i915_gem_object *obj,
9702 struct intel_engine_cs *ring,
9703 uint32_t flags)
9704{
9705 struct drm_i915_private *dev_priv = dev->dev_private;
9706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9707 unsigned long irq_flags;
9708 int ret;
9709
9710 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9711 return -EBUSY;
9712
9713 ret = intel_postpone_flip(obj);
9714 if (ret < 0)
9715 return ret;
9716 if (ret == 0) {
9717 intel_do_mmio_flip(intel_crtc);
9718 return 0;
9719 }
9720
9721 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9722 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9723 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9724 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9725
9726 /*
9727 * Double check to catch cases where irq fired before
9728 * mmio flip data was ready
9729 */
9730 intel_notify_mmio_flip(obj->ring);
9731 return 0;
9732}
9733
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009734static int intel_default_queue_flip(struct drm_device *dev,
9735 struct drm_crtc *crtc,
9736 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009737 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009738 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009739 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009740{
9741 return -ENODEV;
9742}
9743
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009744static int intel_crtc_page_flip(struct drm_crtc *crtc,
9745 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009746 struct drm_pending_vblank_event *event,
9747 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009748{
9749 struct drm_device *dev = crtc->dev;
9750 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009751 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009752 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009754 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009755 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009756 struct intel_engine_cs *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009757 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009758 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009759
Matt Roper2ff8fde2014-07-08 07:50:07 -07009760 /*
9761 * drm_mode_page_flip_ioctl() should already catch this, but double
9762 * check to be safe. In the future we may enable pageflipping from
9763 * a disabled primary plane.
9764 */
9765 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9766 return -EBUSY;
9767
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009768 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009769 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009770 return -EINVAL;
9771
9772 /*
9773 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9774 * Note that pitch changes could also affect these register.
9775 */
9776 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009777 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9778 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009779 return -EINVAL;
9780
Chris Wilsonf900db42014-02-20 09:26:13 +00009781 if (i915_terminally_wedged(&dev_priv->gpu_error))
9782 goto out_hang;
9783
Daniel Vetterb14c5672013-09-19 12:18:32 +02009784 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009785 if (work == NULL)
9786 return -ENOMEM;
9787
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009788 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009789 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009790 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009791 INIT_WORK(&work->work, intel_unpin_work_fn);
9792
Daniel Vetter87b6b102014-05-15 15:33:46 +02009793 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009794 if (ret)
9795 goto free_work;
9796
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009797 /* We borrow the event spin lock for protecting unpin_work */
9798 spin_lock_irqsave(&dev->event_lock, flags);
9799 if (intel_crtc->unpin_work) {
9800 spin_unlock_irqrestore(&dev->event_lock, flags);
9801 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009802 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009803
9804 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009805 return -EBUSY;
9806 }
9807 intel_crtc->unpin_work = work;
9808 spin_unlock_irqrestore(&dev->event_lock, flags);
9809
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009810 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9811 flush_workqueue(dev_priv->wq);
9812
Chris Wilson79158102012-05-23 11:13:58 +01009813 ret = i915_mutex_lock_interruptible(dev);
9814 if (ret)
9815 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009816
Jesse Barnes75dfca82010-02-10 15:09:44 -08009817 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009818 drm_gem_object_reference(&work->old_fb_obj->base);
9819 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009820
Matt Roperf4510a22014-04-01 15:22:40 -07009821 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009822
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009823 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009824
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009825 work->enable_stall_check = true;
9826
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009827 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009828 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009829
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009830 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009831 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009832
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009833 if (IS_VALLEYVIEW(dev)) {
9834 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009835 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9836 /* vlv: DISPLAY_FLIP fails to change tiling */
9837 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009838 } else if (IS_IVYBRIDGE(dev)) {
9839 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009840 } else if (INTEL_INFO(dev)->gen >= 7) {
9841 ring = obj->ring;
9842 if (ring == NULL || ring->id != RCS)
9843 ring = &dev_priv->ring[BCS];
9844 } else {
9845 ring = &dev_priv->ring[RCS];
9846 }
9847
9848 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009849 if (ret)
9850 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009851
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009852 work->gtt_offset =
9853 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9854
Sourab Gupta84c33a62014-06-02 16:47:17 +05309855 if (use_mmio_flip(ring, obj))
9856 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9857 page_flip_flags);
9858 else
9859 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9860 page_flip_flags);
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009861 if (ret)
9862 goto cleanup_unpin;
9863
Daniel Vettera071fa02014-06-18 23:28:09 +02009864 i915_gem_track_fb(work->old_fb_obj, obj,
9865 INTEL_FRONTBUFFER_PRIMARY(pipe));
9866
Chris Wilson7782de32011-07-08 12:22:41 +01009867 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009868 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009869 mutex_unlock(&dev->struct_mutex);
9870
Jesse Barnese5510fa2010-07-01 16:48:37 -07009871 trace_i915_flip_request(intel_crtc->plane, obj);
9872
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009873 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009874
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009875cleanup_unpin:
9876 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009877cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009878 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009879 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009880 drm_gem_object_unreference(&work->old_fb_obj->base);
9881 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009882 mutex_unlock(&dev->struct_mutex);
9883
Chris Wilson79158102012-05-23 11:13:58 +01009884cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009885 spin_lock_irqsave(&dev->event_lock, flags);
9886 intel_crtc->unpin_work = NULL;
9887 spin_unlock_irqrestore(&dev->event_lock, flags);
9888
Daniel Vetter87b6b102014-05-15 15:33:46 +02009889 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009890free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009891 kfree(work);
9892
Chris Wilsonf900db42014-02-20 09:26:13 +00009893 if (ret == -EIO) {
9894out_hang:
9895 intel_crtc_wait_for_pending_flips(crtc);
9896 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9897 if (ret == 0 && event)
Daniel Vettera071fa02014-06-18 23:28:09 +02009898 drm_send_vblank_event(dev, pipe, event);
Chris Wilsonf900db42014-02-20 09:26:13 +00009899 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009900 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009901}
9902
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009903static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009904 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9905 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009906};
9907
Daniel Vetter9a935852012-07-05 22:34:27 +02009908/**
9909 * intel_modeset_update_staged_output_state
9910 *
9911 * Updates the staged output configuration state, e.g. after we've read out the
9912 * current hw state.
9913 */
9914static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9915{
Ville Syrjälä76688512014-01-10 11:28:06 +02009916 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009917 struct intel_encoder *encoder;
9918 struct intel_connector *connector;
9919
9920 list_for_each_entry(connector, &dev->mode_config.connector_list,
9921 base.head) {
9922 connector->new_encoder =
9923 to_intel_encoder(connector->base.encoder);
9924 }
9925
Damien Lespiaub2784e12014-08-05 11:29:37 +01009926 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009927 encoder->new_crtc =
9928 to_intel_crtc(encoder->base.crtc);
9929 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009930
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009931 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009932 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009933
9934 if (crtc->new_enabled)
9935 crtc->new_config = &crtc->config;
9936 else
9937 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009938 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009939}
9940
9941/**
9942 * intel_modeset_commit_output_state
9943 *
9944 * This function copies the stage display pipe configuration to the real one.
9945 */
9946static void intel_modeset_commit_output_state(struct drm_device *dev)
9947{
Ville Syrjälä76688512014-01-10 11:28:06 +02009948 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009949 struct intel_encoder *encoder;
9950 struct intel_connector *connector;
9951
9952 list_for_each_entry(connector, &dev->mode_config.connector_list,
9953 base.head) {
9954 connector->base.encoder = &connector->new_encoder->base;
9955 }
9956
Damien Lespiaub2784e12014-08-05 11:29:37 +01009957 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009958 encoder->base.crtc = &encoder->new_crtc->base;
9959 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009960
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009961 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009962 crtc->base.enabled = crtc->new_enabled;
9963 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009964}
9965
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009966static void
Robin Schroereba905b2014-05-18 02:24:50 +02009967connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009968 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009969{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009970 int bpp = pipe_config->pipe_bpp;
9971
9972 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9973 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009974 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009975
9976 /* Don't use an invalid EDID bpc value */
9977 if (connector->base.display_info.bpc &&
9978 connector->base.display_info.bpc * 3 < bpp) {
9979 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9980 bpp, connector->base.display_info.bpc*3);
9981 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9982 }
9983
9984 /* Clamp bpp to 8 on screens without EDID 1.4 */
9985 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9986 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9987 bpp);
9988 pipe_config->pipe_bpp = 24;
9989 }
9990}
9991
9992static int
9993compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9994 struct drm_framebuffer *fb,
9995 struct intel_crtc_config *pipe_config)
9996{
9997 struct drm_device *dev = crtc->base.dev;
9998 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009999 int bpp;
10000
Daniel Vetterd42264b2013-03-28 16:38:08 +010010001 switch (fb->pixel_format) {
10002 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010003 bpp = 8*3; /* since we go through a colormap */
10004 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +010010005 case DRM_FORMAT_XRGB1555:
10006 case DRM_FORMAT_ARGB1555:
10007 /* checked in intel_framebuffer_init already */
10008 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10009 return -EINVAL;
10010 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010011 bpp = 6*3; /* min is 18bpp */
10012 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +010010013 case DRM_FORMAT_XBGR8888:
10014 case DRM_FORMAT_ABGR8888:
10015 /* checked in intel_framebuffer_init already */
10016 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10017 return -EINVAL;
10018 case DRM_FORMAT_XRGB8888:
10019 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010020 bpp = 8*3;
10021 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +010010022 case DRM_FORMAT_XRGB2101010:
10023 case DRM_FORMAT_ARGB2101010:
10024 case DRM_FORMAT_XBGR2101010:
10025 case DRM_FORMAT_ABGR2101010:
10026 /* checked in intel_framebuffer_init already */
10027 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +010010028 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010029 bpp = 10*3;
10030 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +010010031 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010032 default:
10033 DRM_DEBUG_KMS("unsupported depth\n");
10034 return -EINVAL;
10035 }
10036
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010037 pipe_config->pipe_bpp = bpp;
10038
10039 /* Clamp display bpp to EDID value */
10040 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010041 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +020010042 if (!connector->new_encoder ||
10043 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010044 continue;
10045
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010046 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010047 }
10048
10049 return bpp;
10050}
10051
Daniel Vetter644db712013-09-19 14:53:58 +020010052static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10053{
10054 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10055 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010010056 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020010057 mode->crtc_hdisplay, mode->crtc_hsync_start,
10058 mode->crtc_hsync_end, mode->crtc_htotal,
10059 mode->crtc_vdisplay, mode->crtc_vsync_start,
10060 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10061}
10062
Daniel Vetterc0b03412013-05-28 12:05:54 +020010063static void intel_dump_pipe_config(struct intel_crtc *crtc,
10064 struct intel_crtc_config *pipe_config,
10065 const char *context)
10066{
10067 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10068 context, pipe_name(crtc->pipe));
10069
10070 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10071 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10072 pipe_config->pipe_bpp, pipe_config->dither);
10073 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10074 pipe_config->has_pch_encoder,
10075 pipe_config->fdi_lanes,
10076 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10077 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10078 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010079 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10080 pipe_config->has_dp_encoder,
10081 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10082 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10083 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010084
10085 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10086 pipe_config->has_dp_encoder,
10087 pipe_config->dp_m2_n2.gmch_m,
10088 pipe_config->dp_m2_n2.gmch_n,
10089 pipe_config->dp_m2_n2.link_m,
10090 pipe_config->dp_m2_n2.link_n,
10091 pipe_config->dp_m2_n2.tu);
10092
Daniel Vetterc0b03412013-05-28 12:05:54 +020010093 DRM_DEBUG_KMS("requested mode:\n");
10094 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10095 DRM_DEBUG_KMS("adjusted mode:\n");
10096 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +020010097 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030010098 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010099 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10100 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010101 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10102 pipe_config->gmch_pfit.control,
10103 pipe_config->gmch_pfit.pgm_ratios,
10104 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010105 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020010106 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010107 pipe_config->pch_pfit.size,
10108 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010109 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030010110 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010111}
10112
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010113static bool encoders_cloneable(const struct intel_encoder *a,
10114 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010115{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010116 /* masks could be asymmetric, so check both ways */
10117 return a == b || (a->cloneable & (1 << b->type) &&
10118 b->cloneable & (1 << a->type));
10119}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010120
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010121static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10122 struct intel_encoder *encoder)
10123{
10124 struct drm_device *dev = crtc->base.dev;
10125 struct intel_encoder *source_encoder;
10126
Damien Lespiaub2784e12014-08-05 11:29:37 +010010127 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010128 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010129 continue;
10130
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010131 if (!encoders_cloneable(encoder, source_encoder))
10132 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010133 }
10134
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010135 return true;
10136}
10137
10138static bool check_encoder_cloning(struct intel_crtc *crtc)
10139{
10140 struct drm_device *dev = crtc->base.dev;
10141 struct intel_encoder *encoder;
10142
Damien Lespiaub2784e12014-08-05 11:29:37 +010010143 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010144 if (encoder->new_crtc != crtc)
10145 continue;
10146
10147 if (!check_single_encoder_cloning(crtc, encoder))
10148 return false;
10149 }
10150
10151 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010152}
10153
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010154static struct intel_crtc_config *
10155intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010156 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010157 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +020010158{
10159 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +020010160 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010161 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +010010162 int plane_bpp, ret = -EINVAL;
10163 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020010164
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010165 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010166 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10167 return ERR_PTR(-EINVAL);
10168 }
10169
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010170 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10171 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020010172 return ERR_PTR(-ENOMEM);
10173
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010174 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10175 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010176
Daniel Vettere143a212013-07-04 12:01:15 +020010177 pipe_config->cpu_transcoder =
10178 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010179 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010180
Imre Deak2960bc92013-07-30 13:36:32 +030010181 /*
10182 * Sanitize sync polarity flags based on requested ones. If neither
10183 * positive or negative polarity is requested, treat this as meaning
10184 * negative polarity.
10185 */
10186 if (!(pipe_config->adjusted_mode.flags &
10187 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10188 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10189
10190 if (!(pipe_config->adjusted_mode.flags &
10191 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10192 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10193
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010194 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10195 * plane pixel format and any sink constraints into account. Returns the
10196 * source plane bpp so that dithering can be selected on mismatches
10197 * after encoders and crtc also have had their say. */
10198 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10199 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010200 if (plane_bpp < 0)
10201 goto fail;
10202
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010203 /*
10204 * Determine the real pipe dimensions. Note that stereo modes can
10205 * increase the actual pipe size due to the frame doubling and
10206 * insertion of additional space for blanks between the frame. This
10207 * is stored in the crtc timings. We use the requested mode to do this
10208 * computation to clearly distinguish it from the adjusted mode, which
10209 * can be changed by the connectors in the below retry loop.
10210 */
10211 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10212 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10213 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10214
Daniel Vettere29c22c2013-02-21 00:00:16 +010010215encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010216 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010217 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010218 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010219
Daniel Vetter135c81b2013-07-21 21:37:09 +020010220 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010221 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010222
Daniel Vetter7758a112012-07-08 19:40:39 +020010223 /* Pass our mode to the connectors and the CRTC to give them a chance to
10224 * adjust it according to limitations or connector properties, and also
10225 * a chance to reject the mode entirely.
10226 */
Damien Lespiaub2784e12014-08-05 11:29:37 +010010227 for_each_intel_encoder(dev, encoder) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010228
10229 if (&encoder->new_crtc->base != crtc)
10230 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010231
Daniel Vetterefea6e82013-07-21 21:36:59 +020010232 if (!(encoder->compute_config(encoder, pipe_config))) {
10233 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010234 goto fail;
10235 }
10236 }
10237
Daniel Vetterff9a6752013-06-01 17:16:21 +020010238 /* Set default port clock if not overwritten by the encoder. Needs to be
10239 * done afterwards in case the encoder adjusts the mode. */
10240 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010241 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10242 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010243
Daniel Vettera43f6e02013-06-07 23:10:32 +020010244 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010245 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010246 DRM_DEBUG_KMS("CRTC fixup failed\n");
10247 goto fail;
10248 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010249
10250 if (ret == RETRY) {
10251 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10252 ret = -EINVAL;
10253 goto fail;
10254 }
10255
10256 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10257 retry = false;
10258 goto encoder_retry;
10259 }
10260
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010261 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10262 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10263 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10264
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010265 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010266fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010267 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010268 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010269}
10270
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010271/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10272 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10273static void
10274intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10275 unsigned *prepare_pipes, unsigned *disable_pipes)
10276{
10277 struct intel_crtc *intel_crtc;
10278 struct drm_device *dev = crtc->dev;
10279 struct intel_encoder *encoder;
10280 struct intel_connector *connector;
10281 struct drm_crtc *tmp_crtc;
10282
10283 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10284
10285 /* Check which crtcs have changed outputs connected to them, these need
10286 * to be part of the prepare_pipes mask. We don't (yet) support global
10287 * modeset across multiple crtcs, so modeset_pipes will only have one
10288 * bit set at most. */
10289 list_for_each_entry(connector, &dev->mode_config.connector_list,
10290 base.head) {
10291 if (connector->base.encoder == &connector->new_encoder->base)
10292 continue;
10293
10294 if (connector->base.encoder) {
10295 tmp_crtc = connector->base.encoder->crtc;
10296
10297 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10298 }
10299
10300 if (connector->new_encoder)
10301 *prepare_pipes |=
10302 1 << connector->new_encoder->new_crtc->pipe;
10303 }
10304
Damien Lespiaub2784e12014-08-05 11:29:37 +010010305 for_each_intel_encoder(dev, encoder) {
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010306 if (encoder->base.crtc == &encoder->new_crtc->base)
10307 continue;
10308
10309 if (encoder->base.crtc) {
10310 tmp_crtc = encoder->base.crtc;
10311
10312 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10313 }
10314
10315 if (encoder->new_crtc)
10316 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10317 }
10318
Ville Syrjälä76688512014-01-10 11:28:06 +020010319 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010320 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010321 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010322 continue;
10323
Ville Syrjälä76688512014-01-10 11:28:06 +020010324 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010325 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010326 else
10327 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010328 }
10329
10330
10331 /* set_mode is also used to update properties on life display pipes. */
10332 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010333 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010334 *prepare_pipes |= 1 << intel_crtc->pipe;
10335
Daniel Vetterb6c51642013-04-12 18:48:43 +020010336 /*
10337 * For simplicity do a full modeset on any pipe where the output routing
10338 * changed. We could be more clever, but that would require us to be
10339 * more careful with calling the relevant encoder->mode_set functions.
10340 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010341 if (*prepare_pipes)
10342 *modeset_pipes = *prepare_pipes;
10343
10344 /* ... and mask these out. */
10345 *modeset_pipes &= ~(*disable_pipes);
10346 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010347
10348 /*
10349 * HACK: We don't (yet) fully support global modesets. intel_set_config
10350 * obies this rule, but the modeset restore mode of
10351 * intel_modeset_setup_hw_state does not.
10352 */
10353 *modeset_pipes &= 1 << intel_crtc->pipe;
10354 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010355
10356 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10357 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010358}
10359
Daniel Vetterea9d7582012-07-10 10:42:52 +020010360static bool intel_crtc_in_use(struct drm_crtc *crtc)
10361{
10362 struct drm_encoder *encoder;
10363 struct drm_device *dev = crtc->dev;
10364
10365 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10366 if (encoder->crtc == crtc)
10367 return true;
10368
10369 return false;
10370}
10371
10372static void
10373intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10374{
10375 struct intel_encoder *intel_encoder;
10376 struct intel_crtc *intel_crtc;
10377 struct drm_connector *connector;
10378
Damien Lespiaub2784e12014-08-05 11:29:37 +010010379 for_each_intel_encoder(dev, intel_encoder) {
Daniel Vetterea9d7582012-07-10 10:42:52 +020010380 if (!intel_encoder->base.crtc)
10381 continue;
10382
10383 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10384
10385 if (prepare_pipes & (1 << intel_crtc->pipe))
10386 intel_encoder->connectors_active = false;
10387 }
10388
10389 intel_modeset_commit_output_state(dev);
10390
Ville Syrjälä76688512014-01-10 11:28:06 +020010391 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010392 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010393 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010394 WARN_ON(intel_crtc->new_config &&
10395 intel_crtc->new_config != &intel_crtc->config);
10396 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010397 }
10398
10399 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10400 if (!connector->encoder || !connector->encoder->crtc)
10401 continue;
10402
10403 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10404
10405 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010406 struct drm_property *dpms_property =
10407 dev->mode_config.dpms_property;
10408
Daniel Vetterea9d7582012-07-10 10:42:52 +020010409 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010410 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010411 dpms_property,
10412 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010413
10414 intel_encoder = to_intel_encoder(connector->encoder);
10415 intel_encoder->connectors_active = true;
10416 }
10417 }
10418
10419}
10420
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010421static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010422{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010423 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010424
10425 if (clock1 == clock2)
10426 return true;
10427
10428 if (!clock1 || !clock2)
10429 return false;
10430
10431 diff = abs(clock1 - clock2);
10432
10433 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10434 return true;
10435
10436 return false;
10437}
10438
Daniel Vetter25c5b262012-07-08 22:08:04 +020010439#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10440 list_for_each_entry((intel_crtc), \
10441 &(dev)->mode_config.crtc_list, \
10442 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010443 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010444
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010445static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010446intel_pipe_config_compare(struct drm_device *dev,
10447 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010448 struct intel_crtc_config *pipe_config)
10449{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010450#define PIPE_CONF_CHECK_X(name) \
10451 if (current_config->name != pipe_config->name) { \
10452 DRM_ERROR("mismatch in " #name " " \
10453 "(expected 0x%08x, found 0x%08x)\n", \
10454 current_config->name, \
10455 pipe_config->name); \
10456 return false; \
10457 }
10458
Daniel Vetter08a24032013-04-19 11:25:34 +020010459#define PIPE_CONF_CHECK_I(name) \
10460 if (current_config->name != pipe_config->name) { \
10461 DRM_ERROR("mismatch in " #name " " \
10462 "(expected %i, found %i)\n", \
10463 current_config->name, \
10464 pipe_config->name); \
10465 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010466 }
10467
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010468/* This is required for BDW+ where there is only one set of registers for
10469 * switching between high and low RR.
10470 * This macro can be used whenever a comparison has to be made between one
10471 * hw state and multiple sw state variables.
10472 */
10473#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10474 if ((current_config->name != pipe_config->name) && \
10475 (current_config->alt_name != pipe_config->name)) { \
10476 DRM_ERROR("mismatch in " #name " " \
10477 "(expected %i or %i, found %i)\n", \
10478 current_config->name, \
10479 current_config->alt_name, \
10480 pipe_config->name); \
10481 return false; \
10482 }
10483
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010484#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10485 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010486 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010487 "(expected %i, found %i)\n", \
10488 current_config->name & (mask), \
10489 pipe_config->name & (mask)); \
10490 return false; \
10491 }
10492
Ville Syrjälä5e550652013-09-06 23:29:07 +030010493#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10494 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10495 DRM_ERROR("mismatch in " #name " " \
10496 "(expected %i, found %i)\n", \
10497 current_config->name, \
10498 pipe_config->name); \
10499 return false; \
10500 }
10501
Daniel Vetterbb760062013-06-06 14:55:52 +020010502#define PIPE_CONF_QUIRK(quirk) \
10503 ((current_config->quirks | pipe_config->quirks) & (quirk))
10504
Daniel Vettereccb1402013-05-22 00:50:22 +020010505 PIPE_CONF_CHECK_I(cpu_transcoder);
10506
Daniel Vetter08a24032013-04-19 11:25:34 +020010507 PIPE_CONF_CHECK_I(has_pch_encoder);
10508 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010509 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10510 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10511 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10512 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10513 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010514
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010515 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010516
10517 if (INTEL_INFO(dev)->gen < 8) {
10518 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10519 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10520 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10521 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10522 PIPE_CONF_CHECK_I(dp_m_n.tu);
10523
10524 if (current_config->has_drrs) {
10525 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10526 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10527 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10528 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10529 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10530 }
10531 } else {
10532 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10533 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10534 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10535 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10536 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10537 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010538
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010539 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10540 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10541 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10542 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10543 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10544 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10545
10546 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10547 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10548 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10549 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10550 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10551 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10552
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010553 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b52014-04-24 23:54:47 +020010554 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010555 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10556 IS_VALLEYVIEW(dev))
10557 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010558
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010559 PIPE_CONF_CHECK_I(has_audio);
10560
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010561 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10562 DRM_MODE_FLAG_INTERLACE);
10563
Daniel Vetterbb760062013-06-06 14:55:52 +020010564 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10565 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10566 DRM_MODE_FLAG_PHSYNC);
10567 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10568 DRM_MODE_FLAG_NHSYNC);
10569 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10570 DRM_MODE_FLAG_PVSYNC);
10571 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10572 DRM_MODE_FLAG_NVSYNC);
10573 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010574
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010575 PIPE_CONF_CHECK_I(pipe_src_w);
10576 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010577
Daniel Vetter99535992014-04-13 12:00:33 +020010578 /*
10579 * FIXME: BIOS likes to set up a cloned config with lvds+external
10580 * screen. Since we don't yet re-compute the pipe config when moving
10581 * just the lvds port away to another pipe the sw tracking won't match.
10582 *
10583 * Proper atomic modesets with recomputed global state will fix this.
10584 * Until then just don't check gmch state for inherited modes.
10585 */
10586 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10587 PIPE_CONF_CHECK_I(gmch_pfit.control);
10588 /* pfit ratios are autocomputed by the hw on gen4+ */
10589 if (INTEL_INFO(dev)->gen < 4)
10590 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10591 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10592 }
10593
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010594 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10595 if (current_config->pch_pfit.enabled) {
10596 PIPE_CONF_CHECK_I(pch_pfit.pos);
10597 PIPE_CONF_CHECK_I(pch_pfit.size);
10598 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010599
Jesse Barnese59150d2014-01-07 13:30:45 -080010600 /* BDW+ don't expose a synchronous way to read the state */
10601 if (IS_HASWELL(dev))
10602 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010603
Ville Syrjälä282740f2013-09-04 18:30:03 +030010604 PIPE_CONF_CHECK_I(double_wide);
10605
Daniel Vetter26804af2014-06-25 22:01:55 +030010606 PIPE_CONF_CHECK_X(ddi_pll_sel);
10607
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010608 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010609 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010610 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010611 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10612 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010613 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010614
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010615 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10616 PIPE_CONF_CHECK_I(pipe_bpp);
10617
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010618 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10619 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010620
Daniel Vetter66e985c2013-06-05 13:34:20 +020010621#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010622#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010623#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010624#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010625#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010626#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010627
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010628 return true;
10629}
10630
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010631static void
10632check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010633{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010634 struct intel_connector *connector;
10635
10636 list_for_each_entry(connector, &dev->mode_config.connector_list,
10637 base.head) {
10638 /* This also checks the encoder/connector hw state with the
10639 * ->get_hw_state callbacks. */
10640 intel_connector_check_state(connector);
10641
10642 WARN(&connector->new_encoder->base != connector->base.encoder,
10643 "connector's staged encoder doesn't match current encoder\n");
10644 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010645}
10646
10647static void
10648check_encoder_state(struct drm_device *dev)
10649{
10650 struct intel_encoder *encoder;
10651 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010652
Damien Lespiaub2784e12014-08-05 11:29:37 +010010653 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010654 bool enabled = false;
10655 bool active = false;
10656 enum pipe pipe, tracked_pipe;
10657
10658 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10659 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030010660 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010661
10662 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10663 "encoder's stage crtc doesn't match current crtc\n");
10664 WARN(encoder->connectors_active && !encoder->base.crtc,
10665 "encoder's active_connectors set, but no crtc\n");
10666
10667 list_for_each_entry(connector, &dev->mode_config.connector_list,
10668 base.head) {
10669 if (connector->base.encoder != &encoder->base)
10670 continue;
10671 enabled = true;
10672 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10673 active = true;
10674 }
Dave Airlie0e32b392014-05-02 14:02:48 +100010675 /*
10676 * for MST connectors if we unplug the connector is gone
10677 * away but the encoder is still connected to a crtc
10678 * until a modeset happens in response to the hotplug.
10679 */
10680 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10681 continue;
10682
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010683 WARN(!!encoder->base.crtc != enabled,
10684 "encoder's enabled state mismatch "
10685 "(expected %i, found %i)\n",
10686 !!encoder->base.crtc, enabled);
10687 WARN(active && !encoder->base.crtc,
10688 "active encoder with no crtc\n");
10689
10690 WARN(encoder->connectors_active != active,
10691 "encoder's computed active state doesn't match tracked active state "
10692 "(expected %i, found %i)\n", active, encoder->connectors_active);
10693
10694 active = encoder->get_hw_state(encoder, &pipe);
10695 WARN(active != encoder->connectors_active,
10696 "encoder's hw state doesn't match sw tracking "
10697 "(expected %i, found %i)\n",
10698 encoder->connectors_active, active);
10699
10700 if (!encoder->base.crtc)
10701 continue;
10702
10703 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10704 WARN(active && pipe != tracked_pipe,
10705 "active encoder's pipe doesn't match"
10706 "(expected %i, found %i)\n",
10707 tracked_pipe, pipe);
10708
10709 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010710}
10711
10712static void
10713check_crtc_state(struct drm_device *dev)
10714{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010715 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010716 struct intel_crtc *crtc;
10717 struct intel_encoder *encoder;
10718 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010719
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010720 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010721 bool enabled = false;
10722 bool active = false;
10723
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010724 memset(&pipe_config, 0, sizeof(pipe_config));
10725
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010726 DRM_DEBUG_KMS("[CRTC:%d]\n",
10727 crtc->base.base.id);
10728
10729 WARN(crtc->active && !crtc->base.enabled,
10730 "active crtc, but not enabled in sw tracking\n");
10731
Damien Lespiaub2784e12014-08-05 11:29:37 +010010732 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010733 if (encoder->base.crtc != &crtc->base)
10734 continue;
10735 enabled = true;
10736 if (encoder->connectors_active)
10737 active = true;
10738 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010739
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010740 WARN(active != crtc->active,
10741 "crtc's computed active state doesn't match tracked active state "
10742 "(expected %i, found %i)\n", active, crtc->active);
10743 WARN(enabled != crtc->base.enabled,
10744 "crtc's computed enabled state doesn't match tracked enabled state "
10745 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10746
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010747 active = dev_priv->display.get_pipe_config(crtc,
10748 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010749
10750 /* hw state is inconsistent with the pipe A quirk */
10751 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10752 active = crtc->active;
10753
Damien Lespiaub2784e12014-08-05 11:29:37 +010010754 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010755 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010756 if (encoder->base.crtc != &crtc->base)
10757 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010758 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010759 encoder->get_config(encoder, &pipe_config);
10760 }
10761
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010762 WARN(crtc->active != active,
10763 "crtc active state doesn't match with hw state "
10764 "(expected %i, found %i)\n", crtc->active, active);
10765
Daniel Vetterc0b03412013-05-28 12:05:54 +020010766 if (active &&
10767 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10768 WARN(1, "pipe state doesn't match!\n");
10769 intel_dump_pipe_config(crtc, &pipe_config,
10770 "[hw state]");
10771 intel_dump_pipe_config(crtc, &crtc->config,
10772 "[sw state]");
10773 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010774 }
10775}
10776
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010777static void
10778check_shared_dpll_state(struct drm_device *dev)
10779{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010780 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010781 struct intel_crtc *crtc;
10782 struct intel_dpll_hw_state dpll_hw_state;
10783 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010784
10785 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10786 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10787 int enabled_crtcs = 0, active_crtcs = 0;
10788 bool active;
10789
10790 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10791
10792 DRM_DEBUG_KMS("%s\n", pll->name);
10793
10794 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10795
10796 WARN(pll->active > pll->refcount,
10797 "more active pll users than references: %i vs %i\n",
10798 pll->active, pll->refcount);
10799 WARN(pll->active && !pll->on,
10800 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010801 WARN(pll->on && !pll->active,
10802 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010803 WARN(pll->on != active,
10804 "pll on state mismatch (expected %i, found %i)\n",
10805 pll->on, active);
10806
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010807 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010808 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10809 enabled_crtcs++;
10810 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10811 active_crtcs++;
10812 }
10813 WARN(pll->active != active_crtcs,
10814 "pll active crtcs mismatch (expected %i, found %i)\n",
10815 pll->active, active_crtcs);
10816 WARN(pll->refcount != enabled_crtcs,
10817 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10818 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010819
10820 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10821 sizeof(dpll_hw_state)),
10822 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010823 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010824}
10825
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010826void
10827intel_modeset_check_state(struct drm_device *dev)
10828{
10829 check_connector_state(dev);
10830 check_encoder_state(dev);
10831 check_crtc_state(dev);
10832 check_shared_dpll_state(dev);
10833}
10834
Ville Syrjälä18442d02013-09-13 16:00:08 +030010835void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10836 int dotclock)
10837{
10838 /*
10839 * FDI already provided one idea for the dotclock.
10840 * Yell if the encoder disagrees.
10841 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010842 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010843 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010844 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010845}
10846
Ville Syrjälä80715b22014-05-15 20:23:23 +030010847static void update_scanline_offset(struct intel_crtc *crtc)
10848{
10849 struct drm_device *dev = crtc->base.dev;
10850
10851 /*
10852 * The scanline counter increments at the leading edge of hsync.
10853 *
10854 * On most platforms it starts counting from vtotal-1 on the
10855 * first active line. That means the scanline counter value is
10856 * always one less than what we would expect. Ie. just after
10857 * start of vblank, which also occurs at start of hsync (on the
10858 * last active line), the scanline counter will read vblank_start-1.
10859 *
10860 * On gen2 the scanline counter starts counting from 1 instead
10861 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10862 * to keep the value positive), instead of adding one.
10863 *
10864 * On HSW+ the behaviour of the scanline counter depends on the output
10865 * type. For DP ports it behaves like most other platforms, but on HDMI
10866 * there's an extra 1 line difference. So we need to add two instead of
10867 * one to the value.
10868 */
10869 if (IS_GEN2(dev)) {
10870 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10871 int vtotal;
10872
10873 vtotal = mode->crtc_vtotal;
10874 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10875 vtotal /= 2;
10876
10877 crtc->scanline_offset = vtotal - 1;
10878 } else if (HAS_DDI(dev) &&
10879 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10880 crtc->scanline_offset = 2;
10881 } else
10882 crtc->scanline_offset = 1;
10883}
10884
Daniel Vetterf30da182013-04-11 20:22:50 +020010885static int __intel_set_mode(struct drm_crtc *crtc,
10886 struct drm_display_mode *mode,
10887 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010888{
10889 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010890 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010891 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010892 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010893 struct intel_crtc *intel_crtc;
10894 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010895 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010896
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010897 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010898 if (!saved_mode)
10899 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010900
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010901 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010902 &prepare_pipes, &disable_pipes);
10903
Tim Gardner3ac18232012-12-07 07:54:26 -070010904 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010905
Daniel Vetter25c5b262012-07-08 22:08:04 +020010906 /* Hack: Because we don't (yet) support global modeset on multiple
10907 * crtcs, we don't keep track of the new mode for more than one crtc.
10908 * Hence simply check whether any bit is set in modeset_pipes in all the
10909 * pieces of code that are not yet converted to deal with mutliple crtcs
10910 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010911 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010912 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010913 if (IS_ERR(pipe_config)) {
10914 ret = PTR_ERR(pipe_config);
10915 pipe_config = NULL;
10916
Tim Gardner3ac18232012-12-07 07:54:26 -070010917 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010918 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010919 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10920 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010921 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010922 }
10923
Jesse Barnes30a970c2013-11-04 13:48:12 -080010924 /*
10925 * See if the config requires any additional preparation, e.g.
10926 * to adjust global state with pipes off. We need to do this
10927 * here so we can get the modeset_pipe updated config for the new
10928 * mode set on this crtc. For other crtcs we need to use the
10929 * adjusted_mode bits in the crtc directly.
10930 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010931 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010932 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010933
Ville Syrjäläc164f832013-11-05 22:34:12 +020010934 /* may have added more to prepare_pipes than we should */
10935 prepare_pipes &= ~disable_pipes;
10936 }
10937
Daniel Vetter460da9162013-03-27 00:44:51 +010010938 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10939 intel_crtc_disable(&intel_crtc->base);
10940
Daniel Vetterea9d7582012-07-10 10:42:52 +020010941 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10942 if (intel_crtc->base.enabled)
10943 dev_priv->display.crtc_disable(&intel_crtc->base);
10944 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010945
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010946 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10947 * to set it here already despite that we pass it down the callchain.
10948 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010949 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010950 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010951 /* mode_set/enable/disable functions rely on a correct pipe
10952 * config. */
10953 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010954 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010955
10956 /*
10957 * Calculate and store various constants which
10958 * are later needed by vblank and swap-completion
10959 * timestamping. They are derived from true hwmode.
10960 */
10961 drm_calc_timestamping_constants(crtc,
10962 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010963 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010964
Daniel Vetterea9d7582012-07-10 10:42:52 +020010965 /* Only after disabling all output pipelines that will be changed can we
10966 * update the the output configuration. */
10967 intel_modeset_update_state(dev, prepare_pipes);
10968
Daniel Vetter47fab732012-10-26 10:58:18 +020010969 if (dev_priv->display.modeset_global_resources)
10970 dev_priv->display.modeset_global_resources(dev);
10971
Daniel Vettera6778b32012-07-02 09:56:42 +020010972 /* Set up the DPLL and any encoders state that needs to adjust or depend
10973 * on the DPLL.
10974 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010975 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070010976 struct drm_framebuffer *old_fb = crtc->primary->fb;
10977 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10978 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020010979
10980 mutex_lock(&dev->struct_mutex);
10981 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vettera071fa02014-06-18 23:28:09 +020010982 obj,
Daniel Vetter4c107942014-04-24 23:55:05 +020010983 NULL);
10984 if (ret != 0) {
10985 DRM_ERROR("pin & fence failed\n");
10986 mutex_unlock(&dev->struct_mutex);
10987 goto done;
10988 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070010989 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020010990 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020010991 i915_gem_track_fb(old_obj, obj,
10992 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020010993 mutex_unlock(&dev->struct_mutex);
10994
10995 crtc->primary->fb = fb;
10996 crtc->x = x;
10997 crtc->y = y;
10998
Daniel Vetter4271b752014-04-24 23:55:00 +020010999 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11000 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011001 if (ret)
11002 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020011003 }
11004
11005 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030011006 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11007 update_scanline_offset(intel_crtc);
11008
Daniel Vetter25c5b262012-07-08 22:08:04 +020011009 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030011010 }
Daniel Vettera6778b32012-07-02 09:56:42 +020011011
Daniel Vettera6778b32012-07-02 09:56:42 +020011012 /* FIXME: add subpixel order */
11013done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030011014 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070011015 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020011016
Tim Gardner3ac18232012-12-07 07:54:26 -070011017out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010011018 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070011019 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020011020 return ret;
11021}
11022
Damien Lespiaue7457a92013-08-08 22:28:59 +010011023static int intel_set_mode(struct drm_crtc *crtc,
11024 struct drm_display_mode *mode,
11025 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020011026{
11027 int ret;
11028
11029 ret = __intel_set_mode(crtc, mode, x, y, fb);
11030
11031 if (ret == 0)
11032 intel_modeset_check_state(crtc->dev);
11033
11034 return ret;
11035}
11036
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011037void intel_crtc_restore_mode(struct drm_crtc *crtc)
11038{
Matt Roperf4510a22014-04-01 15:22:40 -070011039 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011040}
11041
Daniel Vetter25c5b262012-07-08 22:08:04 +020011042#undef for_each_intel_crtc_masked
11043
Daniel Vetterd9e55602012-07-04 22:16:09 +020011044static void intel_set_config_free(struct intel_set_config *config)
11045{
11046 if (!config)
11047 return;
11048
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011049 kfree(config->save_connector_encoders);
11050 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020011051 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020011052 kfree(config);
11053}
11054
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011055static int intel_set_config_save_state(struct drm_device *dev,
11056 struct intel_set_config *config)
11057{
Ville Syrjälä76688512014-01-10 11:28:06 +020011058 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011059 struct drm_encoder *encoder;
11060 struct drm_connector *connector;
11061 int count;
11062
Ville Syrjälä76688512014-01-10 11:28:06 +020011063 config->save_crtc_enabled =
11064 kcalloc(dev->mode_config.num_crtc,
11065 sizeof(bool), GFP_KERNEL);
11066 if (!config->save_crtc_enabled)
11067 return -ENOMEM;
11068
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011069 config->save_encoder_crtcs =
11070 kcalloc(dev->mode_config.num_encoder,
11071 sizeof(struct drm_crtc *), GFP_KERNEL);
11072 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011073 return -ENOMEM;
11074
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011075 config->save_connector_encoders =
11076 kcalloc(dev->mode_config.num_connector,
11077 sizeof(struct drm_encoder *), GFP_KERNEL);
11078 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011079 return -ENOMEM;
11080
11081 /* Copy data. Note that driver private data is not affected.
11082 * Should anything bad happen only the expected state is
11083 * restored, not the drivers personal bookkeeping.
11084 */
11085 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010011086 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011087 config->save_crtc_enabled[count++] = crtc->enabled;
11088 }
11089
11090 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011091 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011092 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011093 }
11094
11095 count = 0;
11096 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011097 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011098 }
11099
11100 return 0;
11101}
11102
11103static void intel_set_config_restore_state(struct drm_device *dev,
11104 struct intel_set_config *config)
11105{
Ville Syrjälä76688512014-01-10 11:28:06 +020011106 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011107 struct intel_encoder *encoder;
11108 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011109 int count;
11110
11111 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011112 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011113 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011114
11115 if (crtc->new_enabled)
11116 crtc->new_config = &crtc->config;
11117 else
11118 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011119 }
11120
11121 count = 0;
Damien Lespiaub2784e12014-08-05 11:29:37 +010011122 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011123 encoder->new_crtc =
11124 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011125 }
11126
11127 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011128 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11129 connector->new_encoder =
11130 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011131 }
11132}
11133
Imre Deake3de42b2013-05-03 19:44:07 +020011134static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010011135is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020011136{
11137 int i;
11138
Chris Wilson2e57f472013-07-17 12:14:40 +010011139 if (set->num_connectors == 0)
11140 return false;
11141
11142 if (WARN_ON(set->connectors == NULL))
11143 return false;
11144
11145 for (i = 0; i < set->num_connectors; i++)
11146 if (set->connectors[i]->encoder &&
11147 set->connectors[i]->encoder->crtc == set->crtc &&
11148 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020011149 return true;
11150
11151 return false;
11152}
11153
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011154static void
11155intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11156 struct intel_set_config *config)
11157{
11158
11159 /* We should be able to check here if the fb has the same properties
11160 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010011161 if (is_crtc_connector_off(set)) {
11162 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070011163 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070011164 /*
11165 * If we have no fb, we can only flip as long as the crtc is
11166 * active, otherwise we need a full mode set. The crtc may
11167 * be active if we've only disabled the primary plane, or
11168 * in fastboot situations.
11169 */
Matt Roperf4510a22014-04-01 15:22:40 -070011170 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011171 struct intel_crtc *intel_crtc =
11172 to_intel_crtc(set->crtc);
11173
Matt Roper3b150f02014-05-29 08:06:53 -070011174 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011175 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11176 config->fb_changed = true;
11177 } else {
11178 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11179 config->mode_changed = true;
11180 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011181 } else if (set->fb == NULL) {
11182 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011183 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011184 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011185 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011186 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011187 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011188 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011189 }
11190
Daniel Vetter835c5872012-07-10 18:11:08 +020011191 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011192 config->fb_changed = true;
11193
11194 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11195 DRM_DEBUG_KMS("modes are different, full mode set\n");
11196 drm_mode_debug_printmodeline(&set->crtc->mode);
11197 drm_mode_debug_printmodeline(set->mode);
11198 config->mode_changed = true;
11199 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011200
11201 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11202 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011203}
11204
Daniel Vetter2e431052012-07-04 22:42:15 +020011205static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011206intel_modeset_stage_output_state(struct drm_device *dev,
11207 struct drm_mode_set *set,
11208 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011209{
Daniel Vetter9a935852012-07-05 22:34:27 +020011210 struct intel_connector *connector;
11211 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011212 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011213 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011214
Damien Lespiau9abdda72013-02-13 13:29:23 +000011215 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011216 * of connectors. For paranoia, double-check this. */
11217 WARN_ON(!set->fb && (set->num_connectors != 0));
11218 WARN_ON(set->fb && (set->num_connectors == 0));
11219
Daniel Vetter9a935852012-07-05 22:34:27 +020011220 list_for_each_entry(connector, &dev->mode_config.connector_list,
11221 base.head) {
11222 /* Otherwise traverse passed in connector list and get encoders
11223 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011224 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011225 if (set->connectors[ro] == &connector->base) {
Dave Airlie0e32b392014-05-02 14:02:48 +100011226 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
Daniel Vetter50f56112012-07-02 09:35:43 +020011227 break;
11228 }
11229 }
11230
Daniel Vetter9a935852012-07-05 22:34:27 +020011231 /* If we disable the crtc, disable all its connectors. Also, if
11232 * the connector is on the changing crtc but not on the new
11233 * connector list, disable it. */
11234 if ((!set->fb || ro == set->num_connectors) &&
11235 connector->base.encoder &&
11236 connector->base.encoder->crtc == set->crtc) {
11237 connector->new_encoder = NULL;
11238
11239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11240 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011241 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011242 }
11243
11244
11245 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011246 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011247 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011248 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011249 }
11250 /* connector->new_encoder is now updated for all connectors. */
11251
11252 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011253 list_for_each_entry(connector, &dev->mode_config.connector_list,
11254 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011255 struct drm_crtc *new_crtc;
11256
Daniel Vetter9a935852012-07-05 22:34:27 +020011257 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011258 continue;
11259
Daniel Vetter9a935852012-07-05 22:34:27 +020011260 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011261
11262 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011263 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011264 new_crtc = set->crtc;
11265 }
11266
11267 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011268 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11269 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011270 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011271 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011272 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
Daniel Vetter9a935852012-07-05 22:34:27 +020011273
11274 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11275 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011276 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011277 new_crtc->base.id);
11278 }
11279
11280 /* Check for any encoders that needs to be disabled. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010011281 for_each_intel_encoder(dev, encoder) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011282 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011283 list_for_each_entry(connector,
11284 &dev->mode_config.connector_list,
11285 base.head) {
11286 if (connector->new_encoder == encoder) {
11287 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011288 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011289 }
11290 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011291
11292 if (num_connectors == 0)
11293 encoder->new_crtc = NULL;
11294 else if (num_connectors > 1)
11295 return -EINVAL;
11296
Daniel Vetter9a935852012-07-05 22:34:27 +020011297 /* Only now check for crtc changes so we don't miss encoders
11298 * that will be disabled. */
11299 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011300 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011301 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011302 }
11303 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011304 /* Now we've also updated encoder->new_crtc for all encoders. */
Dave Airlie0e32b392014-05-02 14:02:48 +100011305 list_for_each_entry(connector, &dev->mode_config.connector_list,
11306 base.head) {
11307 if (connector->new_encoder)
11308 if (connector->new_encoder != connector->encoder)
11309 connector->encoder = connector->new_encoder;
11310 }
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011311 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011312 crtc->new_enabled = false;
11313
Damien Lespiaub2784e12014-08-05 11:29:37 +010011314 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011315 if (encoder->new_crtc == crtc) {
11316 crtc->new_enabled = true;
11317 break;
11318 }
11319 }
11320
11321 if (crtc->new_enabled != crtc->base.enabled) {
11322 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11323 crtc->new_enabled ? "en" : "dis");
11324 config->mode_changed = true;
11325 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011326
11327 if (crtc->new_enabled)
11328 crtc->new_config = &crtc->config;
11329 else
11330 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011331 }
11332
Daniel Vetter2e431052012-07-04 22:42:15 +020011333 return 0;
11334}
11335
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011336static void disable_crtc_nofb(struct intel_crtc *crtc)
11337{
11338 struct drm_device *dev = crtc->base.dev;
11339 struct intel_encoder *encoder;
11340 struct intel_connector *connector;
11341
11342 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11343 pipe_name(crtc->pipe));
11344
11345 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11346 if (connector->new_encoder &&
11347 connector->new_encoder->new_crtc == crtc)
11348 connector->new_encoder = NULL;
11349 }
11350
Damien Lespiaub2784e12014-08-05 11:29:37 +010011351 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011352 if (encoder->new_crtc == crtc)
11353 encoder->new_crtc = NULL;
11354 }
11355
11356 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011357 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011358}
11359
Daniel Vetter2e431052012-07-04 22:42:15 +020011360static int intel_crtc_set_config(struct drm_mode_set *set)
11361{
11362 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011363 struct drm_mode_set save_set;
11364 struct intel_set_config *config;
11365 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011366
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011367 BUG_ON(!set);
11368 BUG_ON(!set->crtc);
11369 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011370
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011371 /* Enforce sane interface api - has been abused by the fb helper. */
11372 BUG_ON(!set->mode && set->fb);
11373 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011374
Daniel Vetter2e431052012-07-04 22:42:15 +020011375 if (set->fb) {
11376 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11377 set->crtc->base.id, set->fb->base.id,
11378 (int)set->num_connectors, set->x, set->y);
11379 } else {
11380 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011381 }
11382
11383 dev = set->crtc->dev;
11384
11385 ret = -ENOMEM;
11386 config = kzalloc(sizeof(*config), GFP_KERNEL);
11387 if (!config)
11388 goto out_config;
11389
11390 ret = intel_set_config_save_state(dev, config);
11391 if (ret)
11392 goto out_config;
11393
11394 save_set.crtc = set->crtc;
11395 save_set.mode = &set->crtc->mode;
11396 save_set.x = set->crtc->x;
11397 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011398 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011399
11400 /* Compute whether we need a full modeset, only an fb base update or no
11401 * change at all. In the future we might also check whether only the
11402 * mode changed, e.g. for LVDS where we only change the panel fitter in
11403 * such cases. */
11404 intel_set_config_compute_mode_changes(set, config);
11405
Daniel Vetter9a935852012-07-05 22:34:27 +020011406 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011407 if (ret)
11408 goto fail;
11409
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011410 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011411 ret = intel_set_mode(set->crtc, set->mode,
11412 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011413 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011414 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11415
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011416 intel_crtc_wait_for_pending_flips(set->crtc);
11417
Daniel Vetter4f660f42012-07-02 09:47:37 +020011418 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011419 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011420
11421 /*
11422 * We need to make sure the primary plane is re-enabled if it
11423 * has previously been turned off.
11424 */
11425 if (!intel_crtc->primary_enabled && ret == 0) {
11426 WARN_ON(!intel_crtc->active);
Ville Syrjäläfdd508a62014-08-08 21:51:11 +030011427 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070011428 }
11429
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011430 /*
11431 * In the fastboot case this may be our only check of the
11432 * state after boot. It would be better to only do it on
11433 * the first update, but we don't have a nice way of doing that
11434 * (and really, set_config isn't used much for high freq page
11435 * flipping, so increasing its cost here shouldn't be a big
11436 * deal).
11437 */
Jani Nikulad330a952014-01-21 11:24:25 +020011438 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011439 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011440 }
11441
Chris Wilson2d05eae2013-05-03 17:36:25 +010011442 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011443 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11444 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011445fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011446 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011447
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011448 /*
11449 * HACK: if the pipe was on, but we didn't have a framebuffer,
11450 * force the pipe off to avoid oopsing in the modeset code
11451 * due to fb==NULL. This should only happen during boot since
11452 * we don't yet reconstruct the FB from the hardware state.
11453 */
11454 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11455 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11456
Chris Wilson2d05eae2013-05-03 17:36:25 +010011457 /* Try to restore the config */
11458 if (config->mode_changed &&
11459 intel_set_mode(save_set.crtc, save_set.mode,
11460 save_set.x, save_set.y, save_set.fb))
11461 DRM_ERROR("failed to restore config after modeset failure\n");
11462 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011463
Daniel Vetterd9e55602012-07-04 22:16:09 +020011464out_config:
11465 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011466 return ret;
11467}
11468
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011469static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011470 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011471 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011472 .destroy = intel_crtc_destroy,
11473 .page_flip = intel_crtc_page_flip,
11474};
11475
Daniel Vetter53589012013-06-05 13:34:16 +020011476static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11477 struct intel_shared_dpll *pll,
11478 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011479{
Daniel Vetter53589012013-06-05 13:34:16 +020011480 uint32_t val;
11481
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011482 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11483 return false;
11484
Daniel Vetter53589012013-06-05 13:34:16 +020011485 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011486 hw_state->dpll = val;
11487 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11488 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011489
11490 return val & DPLL_VCO_ENABLE;
11491}
11492
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011493static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11494 struct intel_shared_dpll *pll)
11495{
11496 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11497 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11498}
11499
Daniel Vettere7b903d2013-06-05 13:34:14 +020011500static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11501 struct intel_shared_dpll *pll)
11502{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011503 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011504 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011505
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011506 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11507
11508 /* Wait for the clocks to stabilize. */
11509 POSTING_READ(PCH_DPLL(pll->id));
11510 udelay(150);
11511
11512 /* The pixel multiplier can only be updated once the
11513 * DPLL is enabled and the clocks are stable.
11514 *
11515 * So write it again.
11516 */
11517 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11518 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011519 udelay(200);
11520}
11521
11522static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11523 struct intel_shared_dpll *pll)
11524{
11525 struct drm_device *dev = dev_priv->dev;
11526 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011527
11528 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011529 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011530 if (intel_crtc_to_shared_dpll(crtc) == pll)
11531 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11532 }
11533
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011534 I915_WRITE(PCH_DPLL(pll->id), 0);
11535 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011536 udelay(200);
11537}
11538
Daniel Vetter46edb022013-06-05 13:34:12 +020011539static char *ibx_pch_dpll_names[] = {
11540 "PCH DPLL A",
11541 "PCH DPLL B",
11542};
11543
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011544static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011545{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011546 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011547 int i;
11548
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011549 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011550
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011551 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011552 dev_priv->shared_dplls[i].id = i;
11553 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011554 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011555 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11556 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011557 dev_priv->shared_dplls[i].get_hw_state =
11558 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011559 }
11560}
11561
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011562static void intel_shared_dpll_init(struct drm_device *dev)
11563{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011564 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011565
Daniel Vetter9cd86932014-06-25 22:01:57 +030011566 if (HAS_DDI(dev))
11567 intel_ddi_pll_init(dev);
11568 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011569 ibx_pch_dpll_init(dev);
11570 else
11571 dev_priv->num_shared_dpll = 0;
11572
11573 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011574}
11575
Matt Roper465c1202014-05-29 08:06:54 -070011576static int
11577intel_primary_plane_disable(struct drm_plane *plane)
11578{
11579 struct drm_device *dev = plane->dev;
Matt Roper465c1202014-05-29 08:06:54 -070011580 struct intel_crtc *intel_crtc;
11581
11582 if (!plane->fb)
11583 return 0;
11584
11585 BUG_ON(!plane->crtc);
11586
11587 intel_crtc = to_intel_crtc(plane->crtc);
11588
11589 /*
11590 * Even though we checked plane->fb above, it's still possible that
11591 * the primary plane has been implicitly disabled because the crtc
11592 * coordinates given weren't visible, or because we detected
11593 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11594 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11595 * In either case, we need to unpin the FB and let the fb pointer get
11596 * updated, but otherwise we don't need to touch the hardware.
11597 */
11598 if (!intel_crtc->primary_enabled)
11599 goto disable_unpin;
11600
11601 intel_crtc_wait_for_pending_flips(plane->crtc);
Ville Syrjäläfdd508a62014-08-08 21:51:11 +030011602 intel_disable_primary_hw_plane(plane, plane->crtc);
11603
Matt Roper465c1202014-05-29 08:06:54 -070011604disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011605 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011606 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011607 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011608 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011609 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011610 plane->fb = NULL;
11611
11612 return 0;
11613}
11614
11615static int
11616intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11617 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11618 unsigned int crtc_w, unsigned int crtc_h,
11619 uint32_t src_x, uint32_t src_y,
11620 uint32_t src_w, uint32_t src_h)
11621{
11622 struct drm_device *dev = crtc->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053011623 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper465c1202014-05-29 08:06:54 -070011624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011625 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11626 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Matt Roper465c1202014-05-29 08:06:54 -070011627 struct drm_rect dest = {
11628 /* integer pixels */
11629 .x1 = crtc_x,
11630 .y1 = crtc_y,
11631 .x2 = crtc_x + crtc_w,
11632 .y2 = crtc_y + crtc_h,
11633 };
11634 struct drm_rect src = {
11635 /* 16.16 fixed point */
11636 .x1 = src_x,
11637 .y1 = src_y,
11638 .x2 = src_x + src_w,
11639 .y2 = src_y + src_h,
11640 };
11641 const struct drm_rect clip = {
11642 /* integer pixels */
11643 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11644 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11645 };
Sonika Jindalce54d852014-08-21 11:44:39 +053011646 const struct {
11647 int crtc_x, crtc_y;
11648 unsigned int crtc_w, crtc_h;
11649 uint32_t src_x, src_y, src_w, src_h;
11650 } orig = {
11651 .crtc_x = crtc_x,
11652 .crtc_y = crtc_y,
11653 .crtc_w = crtc_w,
11654 .crtc_h = crtc_h,
11655 .src_x = src_x,
11656 .src_y = src_y,
11657 .src_w = src_w,
11658 .src_h = src_h,
11659 };
11660 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper465c1202014-05-29 08:06:54 -070011661 bool visible;
11662 int ret;
11663
11664 ret = drm_plane_helper_check_update(plane, crtc, fb,
11665 &src, &dest, &clip,
11666 DRM_PLANE_HELPER_NO_SCALING,
11667 DRM_PLANE_HELPER_NO_SCALING,
11668 false, true, &visible);
11669
11670 if (ret)
11671 return ret;
11672
11673 /*
11674 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11675 * updating the fb pointer, and returning without touching the
11676 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11677 * turn on the display with all planes setup as desired.
11678 */
11679 if (!crtc->enabled) {
Matt Roper4c345742014-07-09 16:22:10 -070011680 mutex_lock(&dev->struct_mutex);
11681
Matt Roper465c1202014-05-29 08:06:54 -070011682 /*
11683 * If we already called setplane while the crtc was disabled,
11684 * we may have an fb pinned; unpin it.
11685 */
11686 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011687 intel_unpin_fb_obj(old_obj);
11688
11689 i915_gem_track_fb(old_obj, obj,
11690 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper465c1202014-05-29 08:06:54 -070011691
11692 /* Pin and return without programming hardware */
Matt Roper4c345742014-07-09 16:22:10 -070011693 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11694 mutex_unlock(&dev->struct_mutex);
11695
11696 return ret;
Matt Roper465c1202014-05-29 08:06:54 -070011697 }
11698
11699 intel_crtc_wait_for_pending_flips(crtc);
11700
11701 /*
11702 * If clipping results in a non-visible primary plane, we'll disable
11703 * the primary plane. Note that this is a bit different than what
11704 * happens if userspace explicitly disables the plane by passing fb=0
11705 * because plane->fb still gets set and pinned.
11706 */
11707 if (!visible) {
Matt Roper4c345742014-07-09 16:22:10 -070011708 mutex_lock(&dev->struct_mutex);
11709
Matt Roper465c1202014-05-29 08:06:54 -070011710 /*
11711 * Try to pin the new fb first so that we can bail out if we
11712 * fail.
11713 */
11714 if (plane->fb != fb) {
Daniel Vettera071fa02014-06-18 23:28:09 +020011715 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
Matt Roper4c345742014-07-09 16:22:10 -070011716 if (ret) {
11717 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011718 return ret;
Matt Roper4c345742014-07-09 16:22:10 -070011719 }
Matt Roper465c1202014-05-29 08:06:54 -070011720 }
11721
Daniel Vettera071fa02014-06-18 23:28:09 +020011722 i915_gem_track_fb(old_obj, obj,
11723 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11724
Matt Roper465c1202014-05-29 08:06:54 -070011725 if (intel_crtc->primary_enabled)
Ville Syrjäläfdd508a62014-08-08 21:51:11 +030011726 intel_disable_primary_hw_plane(plane, crtc);
Matt Roper465c1202014-05-29 08:06:54 -070011727
11728
11729 if (plane->fb != fb)
11730 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011731 intel_unpin_fb_obj(old_obj);
Matt Roper465c1202014-05-29 08:06:54 -070011732
Matt Roper4c345742014-07-09 16:22:10 -070011733 mutex_unlock(&dev->struct_mutex);
11734
Sonika Jindalce54d852014-08-21 11:44:39 +053011735 } else {
Sonika Jindal48404c12014-08-22 14:06:04 +053011736 if (intel_crtc && intel_crtc->active &&
11737 intel_crtc->primary_enabled) {
11738 /*
11739 * FBC does not work on some platforms for rotated
11740 * planes, so disable it when rotation is not 0 and
11741 * update it when rotation is set back to 0.
11742 *
11743 * FIXME: This is redundant with the fbc update done in
11744 * the primary plane enable function except that that
11745 * one is done too late. We eventually need to unify
11746 * this.
11747 */
11748 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11749 dev_priv->fbc.plane == intel_crtc->plane &&
11750 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11751 intel_disable_fbc(dev);
11752 }
11753 }
Sonika Jindalce54d852014-08-21 11:44:39 +053011754 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11755 if (ret)
11756 return ret;
11757
11758 if (!intel_crtc->primary_enabled)
11759 intel_enable_primary_hw_plane(plane, crtc);
Matt Roper465c1202014-05-29 08:06:54 -070011760 }
11761
Sonika Jindalce54d852014-08-21 11:44:39 +053011762 intel_plane->crtc_x = orig.crtc_x;
11763 intel_plane->crtc_y = orig.crtc_y;
11764 intel_plane->crtc_w = orig.crtc_w;
11765 intel_plane->crtc_h = orig.crtc_h;
11766 intel_plane->src_x = orig.src_x;
11767 intel_plane->src_y = orig.src_y;
11768 intel_plane->src_w = orig.src_w;
11769 intel_plane->src_h = orig.src_h;
11770 intel_plane->obj = obj;
Matt Roper465c1202014-05-29 08:06:54 -070011771
11772 return 0;
11773}
11774
Matt Roper3d7d6512014-06-10 08:28:13 -070011775/* Common destruction function for both primary and cursor planes */
11776static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011777{
11778 struct intel_plane *intel_plane = to_intel_plane(plane);
11779 drm_plane_cleanup(plane);
11780 kfree(intel_plane);
11781}
11782
11783static const struct drm_plane_funcs intel_primary_plane_funcs = {
11784 .update_plane = intel_primary_plane_setplane,
11785 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011786 .destroy = intel_plane_destroy,
Sonika Jindal48404c12014-08-22 14:06:04 +053011787 .set_property = intel_plane_set_property
Matt Roper465c1202014-05-29 08:06:54 -070011788};
11789
11790static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11791 int pipe)
11792{
11793 struct intel_plane *primary;
11794 const uint32_t *intel_primary_formats;
11795 int num_formats;
11796
11797 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11798 if (primary == NULL)
11799 return NULL;
11800
11801 primary->can_scale = false;
11802 primary->max_downscale = 1;
11803 primary->pipe = pipe;
11804 primary->plane = pipe;
Sonika Jindal48404c12014-08-22 14:06:04 +053011805 primary->rotation = BIT(DRM_ROTATE_0);
Matt Roper465c1202014-05-29 08:06:54 -070011806 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11807 primary->plane = !pipe;
11808
11809 if (INTEL_INFO(dev)->gen <= 3) {
11810 intel_primary_formats = intel_primary_formats_gen2;
11811 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11812 } else {
11813 intel_primary_formats = intel_primary_formats_gen4;
11814 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11815 }
11816
11817 drm_universal_plane_init(dev, &primary->base, 0,
11818 &intel_primary_plane_funcs,
11819 intel_primary_formats, num_formats,
11820 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053011821
11822 if (INTEL_INFO(dev)->gen >= 4) {
11823 if (!dev->mode_config.rotation_property)
11824 dev->mode_config.rotation_property =
11825 drm_mode_create_rotation_property(dev,
11826 BIT(DRM_ROTATE_0) |
11827 BIT(DRM_ROTATE_180));
11828 if (dev->mode_config.rotation_property)
11829 drm_object_attach_property(&primary->base.base,
11830 dev->mode_config.rotation_property,
11831 primary->rotation);
11832 }
11833
Matt Roper465c1202014-05-29 08:06:54 -070011834 return &primary->base;
11835}
11836
Matt Roper3d7d6512014-06-10 08:28:13 -070011837static int
11838intel_cursor_plane_disable(struct drm_plane *plane)
11839{
11840 if (!plane->fb)
11841 return 0;
11842
11843 BUG_ON(!plane->crtc);
11844
11845 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11846}
11847
11848static int
11849intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11850 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11851 unsigned int crtc_w, unsigned int crtc_h,
11852 uint32_t src_x, uint32_t src_y,
11853 uint32_t src_w, uint32_t src_h)
11854{
11855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11856 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11857 struct drm_i915_gem_object *obj = intel_fb->obj;
11858 struct drm_rect dest = {
11859 /* integer pixels */
11860 .x1 = crtc_x,
11861 .y1 = crtc_y,
11862 .x2 = crtc_x + crtc_w,
11863 .y2 = crtc_y + crtc_h,
11864 };
11865 struct drm_rect src = {
11866 /* 16.16 fixed point */
11867 .x1 = src_x,
11868 .y1 = src_y,
11869 .x2 = src_x + src_w,
11870 .y2 = src_y + src_h,
11871 };
11872 const struct drm_rect clip = {
11873 /* integer pixels */
Ville Syrjälä1add1432014-08-12 19:39:52 +030011874 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11875 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
Matt Roper3d7d6512014-06-10 08:28:13 -070011876 };
11877 bool visible;
11878 int ret;
11879
11880 ret = drm_plane_helper_check_update(plane, crtc, fb,
11881 &src, &dest, &clip,
11882 DRM_PLANE_HELPER_NO_SCALING,
11883 DRM_PLANE_HELPER_NO_SCALING,
11884 true, true, &visible);
11885 if (ret)
11886 return ret;
11887
11888 crtc->cursor_x = crtc_x;
11889 crtc->cursor_y = crtc_y;
11890 if (fb != crtc->cursor->fb) {
11891 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11892 } else {
11893 intel_crtc_update_cursor(crtc, visible);
Daniel Vetter4ed91092014-08-08 20:27:01 +020011894
11895 intel_frontbuffer_flip(crtc->dev,
11896 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11897
Matt Roper3d7d6512014-06-10 08:28:13 -070011898 return 0;
11899 }
11900}
11901static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11902 .update_plane = intel_cursor_plane_update,
11903 .disable_plane = intel_cursor_plane_disable,
11904 .destroy = intel_plane_destroy,
11905};
11906
11907static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11908 int pipe)
11909{
11910 struct intel_plane *cursor;
11911
11912 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11913 if (cursor == NULL)
11914 return NULL;
11915
11916 cursor->can_scale = false;
11917 cursor->max_downscale = 1;
11918 cursor->pipe = pipe;
11919 cursor->plane = pipe;
11920
11921 drm_universal_plane_init(dev, &cursor->base, 0,
11922 &intel_cursor_plane_funcs,
11923 intel_cursor_formats,
11924 ARRAY_SIZE(intel_cursor_formats),
11925 DRM_PLANE_TYPE_CURSOR);
11926 return &cursor->base;
11927}
11928
Hannes Ederb358d0a2008-12-18 21:18:47 +010011929static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080011930{
Jani Nikulafbee40d2014-03-31 14:27:18 +030011931 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080011932 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070011933 struct drm_plane *primary = NULL;
11934 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070011935 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080011936
Daniel Vetter955382f2013-09-19 14:05:45 +020011937 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080011938 if (intel_crtc == NULL)
11939 return;
11940
Matt Roper465c1202014-05-29 08:06:54 -070011941 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011942 if (!primary)
11943 goto fail;
11944
11945 cursor = intel_cursor_plane_create(dev, pipe);
11946 if (!cursor)
11947 goto fail;
11948
Matt Roper465c1202014-05-29 08:06:54 -070011949 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070011950 cursor, &intel_crtc_funcs);
11951 if (ret)
11952 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011953
11954 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080011955 for (i = 0; i < 256; i++) {
11956 intel_crtc->lut_r[i] = i;
11957 intel_crtc->lut_g[i] = i;
11958 intel_crtc->lut_b[i] = i;
11959 }
11960
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011961 /*
11962 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020011963 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011964 */
Jesse Barnes80824002009-09-10 15:28:06 -070011965 intel_crtc->pipe = pipe;
11966 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010011967 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080011968 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010011969 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070011970 }
11971
Chris Wilson4b0e3332014-05-30 16:35:26 +030011972 intel_crtc->cursor_base = ~0;
11973 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030011974 intel_crtc->cursor_size = ~0;
Chris Wilson4b0e3332014-05-30 16:35:26 +030011975
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080011976 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11977 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11978 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11979 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11980
Jesse Barnes79e53942008-11-07 14:24:08 -080011981 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020011982
11983 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011984 return;
11985
11986fail:
11987 if (primary)
11988 drm_plane_cleanup(primary);
11989 if (cursor)
11990 drm_plane_cleanup(cursor);
11991 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080011992}
11993
Jesse Barnes752aa882013-10-31 18:55:49 +020011994enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11995{
11996 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011997 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020011998
Rob Clark51fd3712013-11-19 12:10:12 -050011999 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020012000
12001 if (!encoder)
12002 return INVALID_PIPE;
12003
12004 return to_intel_crtc(encoder->crtc)->pipe;
12005}
12006
Carl Worth08d7b3d2009-04-29 14:43:54 -070012007int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000012008 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070012009{
Carl Worth08d7b3d2009-04-29 14:43:54 -070012010 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040012011 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020012012 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012013
Daniel Vetter1cff8f62012-04-24 09:55:08 +020012014 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12015 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012016
Rob Clark7707e652014-07-17 23:30:04 -040012017 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070012018
Rob Clark7707e652014-07-17 23:30:04 -040012019 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070012020 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030012021 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012022 }
12023
Rob Clark7707e652014-07-17 23:30:04 -040012024 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020012025 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012026
Daniel Vetterc05422d2009-08-11 16:05:30 +020012027 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012028}
12029
Daniel Vetter66a92782012-07-12 20:08:18 +020012030static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080012031{
Daniel Vetter66a92782012-07-12 20:08:18 +020012032 struct drm_device *dev = encoder->base.dev;
12033 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080012034 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080012035 int entry = 0;
12036
Damien Lespiaub2784e12014-08-05 11:29:37 +010012037 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020012038 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020012039 index_mask |= (1 << entry);
12040
Jesse Barnes79e53942008-11-07 14:24:08 -080012041 entry++;
12042 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010012043
Jesse Barnes79e53942008-11-07 14:24:08 -080012044 return index_mask;
12045}
12046
Chris Wilson4d302442010-12-14 19:21:29 +000012047static bool has_edp_a(struct drm_device *dev)
12048{
12049 struct drm_i915_private *dev_priv = dev->dev_private;
12050
12051 if (!IS_MOBILE(dev))
12052 return false;
12053
12054 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12055 return false;
12056
Damien Lespiaue3589902014-02-07 19:12:50 +000012057 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000012058 return false;
12059
12060 return true;
12061}
12062
Damien Lespiauba0fbca2014-01-08 14:18:23 +000012063const char *intel_output_name(int output)
12064{
12065 static const char *names[] = {
12066 [INTEL_OUTPUT_UNUSED] = "Unused",
12067 [INTEL_OUTPUT_ANALOG] = "Analog",
12068 [INTEL_OUTPUT_DVO] = "DVO",
12069 [INTEL_OUTPUT_SDVO] = "SDVO",
12070 [INTEL_OUTPUT_LVDS] = "LVDS",
12071 [INTEL_OUTPUT_TVOUT] = "TV",
12072 [INTEL_OUTPUT_HDMI] = "HDMI",
12073 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12074 [INTEL_OUTPUT_EDP] = "eDP",
12075 [INTEL_OUTPUT_DSI] = "DSI",
12076 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12077 };
12078
12079 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12080 return "Invalid";
12081
12082 return names[output];
12083}
12084
Jesse Barnes84b4e042014-06-25 08:24:29 -070012085static bool intel_crt_present(struct drm_device *dev)
12086{
12087 struct drm_i915_private *dev_priv = dev->dev_private;
12088
12089 if (IS_ULT(dev))
12090 return false;
12091
12092 if (IS_CHERRYVIEW(dev))
12093 return false;
12094
12095 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12096 return false;
12097
12098 return true;
12099}
12100
Jesse Barnes79e53942008-11-07 14:24:08 -080012101static void intel_setup_outputs(struct drm_device *dev)
12102{
Eric Anholt725e30a2009-01-22 13:01:02 -080012103 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010012104 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012105 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080012106
Daniel Vetterc9093352013-06-06 22:22:47 +020012107 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012108
Jesse Barnes84b4e042014-06-25 08:24:29 -070012109 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020012110 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012111
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012112 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030012113 int found;
12114
12115 /* Haswell uses DDI functions to detect digital outputs */
12116 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12117 /* DDI A only supports eDP */
12118 if (found)
12119 intel_ddi_init(dev, PORT_A);
12120
12121 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12122 * register */
12123 found = I915_READ(SFUSE_STRAP);
12124
12125 if (found & SFUSE_STRAP_DDIB_DETECTED)
12126 intel_ddi_init(dev, PORT_B);
12127 if (found & SFUSE_STRAP_DDIC_DETECTED)
12128 intel_ddi_init(dev, PORT_C);
12129 if (found & SFUSE_STRAP_DDID_DETECTED)
12130 intel_ddi_init(dev, PORT_D);
12131 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012132 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012133 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020012134
12135 if (has_edp_a(dev))
12136 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012137
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012138 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080012139 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010012140 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012141 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012142 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012143 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012144 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012145 }
12146
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012147 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012148 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012149
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012150 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012151 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012152
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012153 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012154 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012155
Daniel Vetter270b3042012-10-27 15:52:05 +020012156 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012157 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070012158 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012159 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12160 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12161 PORT_B);
12162 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12163 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12164 }
12165
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012166 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12167 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12168 PORT_C);
12169 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012170 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012171 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053012172
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012173 if (IS_CHERRYVIEW(dev)) {
12174 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12175 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12176 PORT_D);
12177 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12178 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12179 }
12180 }
12181
Jani Nikula3cfca972013-08-27 15:12:26 +030012182 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080012183 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012184 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080012185
Paulo Zanonie2debe92013-02-18 19:00:27 -030012186 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012187 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012188 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012189 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12190 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012191 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012192 }
Ma Ling27185ae2009-08-24 13:50:23 +080012193
Imre Deake7281ea2013-05-08 13:14:08 +030012194 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012195 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080012196 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012197
12198 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012199
Paulo Zanonie2debe92013-02-18 19:00:27 -030012200 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012201 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012202 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012203 }
Ma Ling27185ae2009-08-24 13:50:23 +080012204
Paulo Zanonie2debe92013-02-18 19:00:27 -030012205 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012206
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012207 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12208 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012209 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012210 }
Imre Deake7281ea2013-05-08 13:14:08 +030012211 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012212 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080012213 }
Ma Ling27185ae2009-08-24 13:50:23 +080012214
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012215 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030012216 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012217 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070012218 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012219 intel_dvo_init(dev);
12220
Zhenyu Wang103a1962009-11-27 11:44:36 +080012221 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012222 intel_tv_init(dev);
12223
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012224 intel_edp_psr_init(dev);
12225
Damien Lespiaub2784e12014-08-05 11:29:37 +010012226 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010012227 encoder->base.possible_crtcs = encoder->crtc_mask;
12228 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012229 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012230 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012231
Paulo Zanonidde86e22012-12-01 12:04:25 -020012232 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012233
12234 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012235}
12236
12237static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12238{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012239 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012240 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012241
Daniel Vetteref2d6332014-02-10 18:00:38 +010012242 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012243 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012244 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012245 drm_gem_object_unreference(&intel_fb->obj->base);
12246 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012247 kfree(intel_fb);
12248}
12249
12250static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012251 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012252 unsigned int *handle)
12253{
12254 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012255 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012256
Chris Wilson05394f32010-11-08 19:18:58 +000012257 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012258}
12259
12260static const struct drm_framebuffer_funcs intel_fb_funcs = {
12261 .destroy = intel_user_framebuffer_destroy,
12262 .create_handle = intel_user_framebuffer_create_handle,
12263};
12264
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012265static int intel_framebuffer_init(struct drm_device *dev,
12266 struct intel_framebuffer *intel_fb,
12267 struct drm_mode_fb_cmd2 *mode_cmd,
12268 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012269{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012270 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012271 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012272 int ret;
12273
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012274 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12275
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012276 if (obj->tiling_mode == I915_TILING_Y) {
12277 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012278 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012279 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012280
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012281 if (mode_cmd->pitches[0] & 63) {
12282 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12283 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012284 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012285 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012286
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012287 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12288 pitch_limit = 32*1024;
12289 } else if (INTEL_INFO(dev)->gen >= 4) {
12290 if (obj->tiling_mode)
12291 pitch_limit = 16*1024;
12292 else
12293 pitch_limit = 32*1024;
12294 } else if (INTEL_INFO(dev)->gen >= 3) {
12295 if (obj->tiling_mode)
12296 pitch_limit = 8*1024;
12297 else
12298 pitch_limit = 16*1024;
12299 } else
12300 /* XXX DSPC is limited to 4k tiled */
12301 pitch_limit = 8*1024;
12302
12303 if (mode_cmd->pitches[0] > pitch_limit) {
12304 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12305 obj->tiling_mode ? "tiled" : "linear",
12306 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012307 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012308 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012309
12310 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012311 mode_cmd->pitches[0] != obj->stride) {
12312 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12313 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012314 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012315 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012316
Ville Syrjälä57779d02012-10-31 17:50:14 +020012317 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012318 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012319 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012320 case DRM_FORMAT_RGB565:
12321 case DRM_FORMAT_XRGB8888:
12322 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012323 break;
12324 case DRM_FORMAT_XRGB1555:
12325 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012326 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012327 DRM_DEBUG("unsupported pixel format: %s\n",
12328 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012329 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012330 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012331 break;
12332 case DRM_FORMAT_XBGR8888:
12333 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012334 case DRM_FORMAT_XRGB2101010:
12335 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012336 case DRM_FORMAT_XBGR2101010:
12337 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012338 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012339 DRM_DEBUG("unsupported pixel format: %s\n",
12340 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012341 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012342 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012343 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012344 case DRM_FORMAT_YUYV:
12345 case DRM_FORMAT_UYVY:
12346 case DRM_FORMAT_YVYU:
12347 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012348 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012349 DRM_DEBUG("unsupported pixel format: %s\n",
12350 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012351 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012352 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012353 break;
12354 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012355 DRM_DEBUG("unsupported pixel format: %s\n",
12356 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012357 return -EINVAL;
12358 }
12359
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012360 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12361 if (mode_cmd->offsets[0] != 0)
12362 return -EINVAL;
12363
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012364 aligned_height = intel_align_height(dev, mode_cmd->height,
12365 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012366 /* FIXME drm helper for size checks (especially planar formats)? */
12367 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12368 return -EINVAL;
12369
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012370 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12371 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012372 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012373
Jesse Barnes79e53942008-11-07 14:24:08 -080012374 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12375 if (ret) {
12376 DRM_ERROR("framebuffer init failed %d\n", ret);
12377 return ret;
12378 }
12379
Jesse Barnes79e53942008-11-07 14:24:08 -080012380 return 0;
12381}
12382
Jesse Barnes79e53942008-11-07 14:24:08 -080012383static struct drm_framebuffer *
12384intel_user_framebuffer_create(struct drm_device *dev,
12385 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012386 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012387{
Chris Wilson05394f32010-11-08 19:18:58 +000012388 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012389
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012390 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12391 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012392 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012393 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012394
Chris Wilsond2dff872011-04-19 08:36:26 +010012395 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012396}
12397
Daniel Vetter4520f532013-10-09 09:18:51 +020012398#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012399static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012400{
12401}
12402#endif
12403
Jesse Barnes79e53942008-11-07 14:24:08 -080012404static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012405 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012406 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012407};
12408
Jesse Barnese70236a2009-09-21 10:42:27 -070012409/* Set up chip specific display functions */
12410static void intel_init_display(struct drm_device *dev)
12411{
12412 struct drm_i915_private *dev_priv = dev->dev_private;
12413
Daniel Vetteree9300b2013-06-03 22:40:22 +020012414 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12415 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012416 else if (IS_CHERRYVIEW(dev))
12417 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012418 else if (IS_VALLEYVIEW(dev))
12419 dev_priv->display.find_dpll = vlv_find_best_dpll;
12420 else if (IS_PINEVIEW(dev))
12421 dev_priv->display.find_dpll = pnv_find_best_dpll;
12422 else
12423 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12424
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012425 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012426 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012427 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012428 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012429 dev_priv->display.crtc_enable = haswell_crtc_enable;
12430 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012431 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012432 dev_priv->display.update_primary_plane =
12433 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012434 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012435 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012436 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012437 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012438 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12439 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012440 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012441 dev_priv->display.update_primary_plane =
12442 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012443 } else if (IS_VALLEYVIEW(dev)) {
12444 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012445 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012446 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12447 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12448 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12449 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012450 dev_priv->display.update_primary_plane =
12451 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012452 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012453 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012454 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012455 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012456 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12457 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012458 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012459 dev_priv->display.update_primary_plane =
12460 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012461 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012462
Jesse Barnese70236a2009-09-21 10:42:27 -070012463 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012464 if (IS_VALLEYVIEW(dev))
12465 dev_priv->display.get_display_clock_speed =
12466 valleyview_get_display_clock_speed;
12467 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012468 dev_priv->display.get_display_clock_speed =
12469 i945_get_display_clock_speed;
12470 else if (IS_I915G(dev))
12471 dev_priv->display.get_display_clock_speed =
12472 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012473 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012474 dev_priv->display.get_display_clock_speed =
12475 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012476 else if (IS_PINEVIEW(dev))
12477 dev_priv->display.get_display_clock_speed =
12478 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012479 else if (IS_I915GM(dev))
12480 dev_priv->display.get_display_clock_speed =
12481 i915gm_get_display_clock_speed;
12482 else if (IS_I865G(dev))
12483 dev_priv->display.get_display_clock_speed =
12484 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012485 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012486 dev_priv->display.get_display_clock_speed =
12487 i855_get_display_clock_speed;
12488 else /* 852, 830 */
12489 dev_priv->display.get_display_clock_speed =
12490 i830_get_display_clock_speed;
12491
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012492 if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080012493 dev_priv->display.write_eld = g4x_write_eld;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012494 } else if (IS_GEN5(dev)) {
12495 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12496 dev_priv->display.write_eld = ironlake_write_eld;
12497 } else if (IS_GEN6(dev)) {
12498 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12499 dev_priv->display.write_eld = ironlake_write_eld;
12500 dev_priv->display.modeset_global_resources =
12501 snb_modeset_global_resources;
12502 } else if (IS_IVYBRIDGE(dev)) {
12503 /* FIXME: detect B0+ stepping and use auto training */
12504 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12505 dev_priv->display.write_eld = ironlake_write_eld;
12506 dev_priv->display.modeset_global_resources =
12507 ivb_modeset_global_resources;
12508 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12509 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12510 dev_priv->display.write_eld = haswell_write_eld;
12511 dev_priv->display.modeset_global_resources =
12512 haswell_modeset_global_resources;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012513 } else if (IS_VALLEYVIEW(dev)) {
12514 dev_priv->display.modeset_global_resources =
12515 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040012516 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070012517 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012518
12519 /* Default just returns -ENODEV to indicate unsupported */
12520 dev_priv->display.queue_flip = intel_default_queue_flip;
12521
12522 switch (INTEL_INFO(dev)->gen) {
12523 case 2:
12524 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12525 break;
12526
12527 case 3:
12528 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12529 break;
12530
12531 case 4:
12532 case 5:
12533 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12534 break;
12535
12536 case 6:
12537 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12538 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012539 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012540 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012541 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12542 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012543 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012544
12545 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012546}
12547
Jesse Barnesb690e962010-07-19 13:53:12 -070012548/*
12549 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12550 * resume, or other times. This quirk makes sure that's the case for
12551 * affected systems.
12552 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012553static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012554{
12555 struct drm_i915_private *dev_priv = dev->dev_private;
12556
12557 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012558 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012559}
12560
Keith Packard435793d2011-07-12 14:56:22 -070012561/*
12562 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12563 */
12564static void quirk_ssc_force_disable(struct drm_device *dev)
12565{
12566 struct drm_i915_private *dev_priv = dev->dev_private;
12567 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012568 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012569}
12570
Carsten Emde4dca20e2012-03-15 15:56:26 +010012571/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012572 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12573 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012574 */
12575static void quirk_invert_brightness(struct drm_device *dev)
12576{
12577 struct drm_i915_private *dev_priv = dev->dev_private;
12578 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012579 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012580}
12581
Scot Doyle9c72cc62014-07-03 23:27:50 +000012582/* Some VBT's incorrectly indicate no backlight is present */
12583static void quirk_backlight_present(struct drm_device *dev)
12584{
12585 struct drm_i915_private *dev_priv = dev->dev_private;
12586 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12587 DRM_INFO("applying backlight present quirk\n");
12588}
12589
Jesse Barnesb690e962010-07-19 13:53:12 -070012590struct intel_quirk {
12591 int device;
12592 int subsystem_vendor;
12593 int subsystem_device;
12594 void (*hook)(struct drm_device *dev);
12595};
12596
Egbert Eich5f85f172012-10-14 15:46:38 +020012597/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12598struct intel_dmi_quirk {
12599 void (*hook)(struct drm_device *dev);
12600 const struct dmi_system_id (*dmi_id_list)[];
12601};
12602
12603static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12604{
12605 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12606 return 1;
12607}
12608
12609static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12610 {
12611 .dmi_id_list = &(const struct dmi_system_id[]) {
12612 {
12613 .callback = intel_dmi_reverse_brightness,
12614 .ident = "NCR Corporation",
12615 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12616 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12617 },
12618 },
12619 { } /* terminating entry */
12620 },
12621 .hook = quirk_invert_brightness,
12622 },
12623};
12624
Ben Widawskyc43b5632012-04-16 14:07:40 -070012625static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012626 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012627 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012628
Jesse Barnesb690e962010-07-19 13:53:12 -070012629 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12630 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12631
Jesse Barnesb690e962010-07-19 13:53:12 -070012632 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12633 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12634
Keith Packard435793d2011-07-12 14:56:22 -070012635 /* Lenovo U160 cannot use SSC on LVDS */
12636 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012637
12638 /* Sony Vaio Y cannot use SSC on LVDS */
12639 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012640
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012641 /* Acer Aspire 5734Z must invert backlight brightness */
12642 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12643
12644 /* Acer/eMachines G725 */
12645 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12646
12647 /* Acer/eMachines e725 */
12648 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12649
12650 /* Acer/Packard Bell NCL20 */
12651 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12652
12653 /* Acer Aspire 4736Z */
12654 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012655
12656 /* Acer Aspire 5336 */
12657 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000012658
12659 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12660 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000012661
12662 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12663 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000012664
12665 /* HP Chromebook 14 (Celeron 2955U) */
12666 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070012667};
12668
12669static void intel_init_quirks(struct drm_device *dev)
12670{
12671 struct pci_dev *d = dev->pdev;
12672 int i;
12673
12674 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12675 struct intel_quirk *q = &intel_quirks[i];
12676
12677 if (d->device == q->device &&
12678 (d->subsystem_vendor == q->subsystem_vendor ||
12679 q->subsystem_vendor == PCI_ANY_ID) &&
12680 (d->subsystem_device == q->subsystem_device ||
12681 q->subsystem_device == PCI_ANY_ID))
12682 q->hook(dev);
12683 }
Egbert Eich5f85f172012-10-14 15:46:38 +020012684 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12685 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12686 intel_dmi_quirks[i].hook(dev);
12687 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012688}
12689
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012690/* Disable the VGA plane that we never use */
12691static void i915_disable_vga(struct drm_device *dev)
12692{
12693 struct drm_i915_private *dev_priv = dev->dev_private;
12694 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012695 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012696
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012697 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012698 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012699 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012700 sr1 = inb(VGA_SR_DATA);
12701 outb(sr1 | 1<<5, VGA_SR_DATA);
12702 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12703 udelay(300);
12704
12705 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12706 POSTING_READ(vga_reg);
12707}
12708
Daniel Vetterf8175862012-04-10 15:50:11 +020012709void intel_modeset_init_hw(struct drm_device *dev)
12710{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012711 intel_prepare_ddi(dev);
12712
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012713 if (IS_VALLEYVIEW(dev))
12714 vlv_update_cdclk(dev);
12715
Daniel Vetterf8175862012-04-10 15:50:11 +020012716 intel_init_clock_gating(dev);
12717
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012718 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012719}
12720
Imre Deak7d708ee2013-04-17 14:04:50 +030012721void intel_modeset_suspend_hw(struct drm_device *dev)
12722{
12723 intel_suspend_hw(dev);
12724}
12725
Jesse Barnes79e53942008-11-07 14:24:08 -080012726void intel_modeset_init(struct drm_device *dev)
12727{
Jesse Barnes652c3932009-08-17 13:31:43 -070012728 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012729 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012730 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012731 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012732
12733 drm_mode_config_init(dev);
12734
12735 dev->mode_config.min_width = 0;
12736 dev->mode_config.min_height = 0;
12737
Dave Airlie019d96c2011-09-29 16:20:42 +010012738 dev->mode_config.preferred_depth = 24;
12739 dev->mode_config.prefer_shadow = 1;
12740
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012741 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012742
Jesse Barnesb690e962010-07-19 13:53:12 -070012743 intel_init_quirks(dev);
12744
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012745 intel_init_pm(dev);
12746
Ben Widawskye3c74752013-04-05 13:12:39 -070012747 if (INTEL_INFO(dev)->num_pipes == 0)
12748 return;
12749
Jesse Barnese70236a2009-09-21 10:42:27 -070012750 intel_init_display(dev);
12751
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012752 if (IS_GEN2(dev)) {
12753 dev->mode_config.max_width = 2048;
12754 dev->mode_config.max_height = 2048;
12755 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070012756 dev->mode_config.max_width = 4096;
12757 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080012758 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012759 dev->mode_config.max_width = 8192;
12760 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080012761 }
Damien Lespiau068be562014-03-28 14:17:49 +000012762
Ville Syrjälädc41c152014-08-13 11:57:05 +030012763 if (IS_845G(dev) || IS_I865G(dev)) {
12764 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12765 dev->mode_config.cursor_height = 1023;
12766 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000012767 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12768 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12769 } else {
12770 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12771 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12772 }
12773
Ben Widawsky5d4545a2013-01-17 12:45:15 -080012774 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080012775
Zhao Yakui28c97732009-10-09 11:39:41 +080012776 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012777 INTEL_INFO(dev)->num_pipes,
12778 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080012779
Damien Lespiau055e3932014-08-18 13:49:10 +010012780 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012781 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000012782 for_each_sprite(pipe, sprite) {
12783 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012784 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030012785 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000012786 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012787 }
Jesse Barnes79e53942008-11-07 14:24:08 -080012788 }
12789
Jesse Barnesf42bb702013-12-16 16:34:23 -080012790 intel_init_dpio(dev);
12791
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012792 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012793
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012794 /* Just disable it once at startup */
12795 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012796 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000012797
12798 /* Just in case the BIOS is doing something questionable. */
12799 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012800
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012801 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012802 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012803 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012804
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012805 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080012806 if (!crtc->active)
12807 continue;
12808
Jesse Barnes46f297f2014-03-07 08:57:48 -080012809 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080012810 * Note that reserving the BIOS fb up front prevents us
12811 * from stuffing other stolen allocations like the ring
12812 * on top. This prevents some ugliness at boot time, and
12813 * can even allow for smooth boot transitions if the BIOS
12814 * fb is large enough for the active pipe configuration.
12815 */
12816 if (dev_priv->display.get_plane_config) {
12817 dev_priv->display.get_plane_config(crtc,
12818 &crtc->plane_config);
12819 /*
12820 * If the fb is shared between multiple heads, we'll
12821 * just get the first one.
12822 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080012823 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012824 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080012825 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010012826}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080012827
Daniel Vetter7fad7982012-07-04 17:51:47 +020012828static void intel_enable_pipe_a(struct drm_device *dev)
12829{
12830 struct intel_connector *connector;
12831 struct drm_connector *crt = NULL;
12832 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012833 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020012834
12835 /* We can't just switch on the pipe A, we need to set things up with a
12836 * proper mode and output configuration. As a gross hack, enable pipe A
12837 * by enabling the load detect pipe once. */
12838 list_for_each_entry(connector,
12839 &dev->mode_config.connector_list,
12840 base.head) {
12841 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12842 crt = &connector->base;
12843 break;
12844 }
12845 }
12846
12847 if (!crt)
12848 return;
12849
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012850 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12851 intel_release_load_detect_pipe(crt, &load_detect_temp);
Daniel Vetter7fad7982012-07-04 17:51:47 +020012852}
12853
Daniel Vetterfa555832012-10-10 23:14:00 +020012854static bool
12855intel_check_plane_mapping(struct intel_crtc *crtc)
12856{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012857 struct drm_device *dev = crtc->base.dev;
12858 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012859 u32 reg, val;
12860
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012861 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020012862 return true;
12863
12864 reg = DSPCNTR(!crtc->plane);
12865 val = I915_READ(reg);
12866
12867 if ((val & DISPLAY_PLANE_ENABLE) &&
12868 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12869 return false;
12870
12871 return true;
12872}
12873
Daniel Vetter24929352012-07-02 20:28:59 +020012874static void intel_sanitize_crtc(struct intel_crtc *crtc)
12875{
12876 struct drm_device *dev = crtc->base.dev;
12877 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012878 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020012879
Daniel Vetter24929352012-07-02 20:28:59 +020012880 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020012881 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012882 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12883
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012884 /* restore vblank interrupts to correct state */
12885 if (crtc->active)
12886 drm_vblank_on(dev, crtc->pipe);
12887 else
12888 drm_vblank_off(dev, crtc->pipe);
12889
Daniel Vetter24929352012-07-02 20:28:59 +020012890 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020012891 * disable the crtc (and hence change the state) if it is wrong. Note
12892 * that gen4+ has a fixed plane -> pipe mapping. */
12893 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020012894 struct intel_connector *connector;
12895 bool plane;
12896
Daniel Vetter24929352012-07-02 20:28:59 +020012897 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12898 crtc->base.base.id);
12899
12900 /* Pipe has the wrong plane attached and the plane is active.
12901 * Temporarily change the plane mapping and disable everything
12902 * ... */
12903 plane = crtc->plane;
12904 crtc->plane = !plane;
Daniel Vetter9c8958b2014-07-14 19:35:31 +020012905 crtc->primary_enabled = true;
Daniel Vetter24929352012-07-02 20:28:59 +020012906 dev_priv->display.crtc_disable(&crtc->base);
12907 crtc->plane = plane;
12908
12909 /* ... and break all links. */
12910 list_for_each_entry(connector, &dev->mode_config.connector_list,
12911 base.head) {
12912 if (connector->encoder->base.crtc != &crtc->base)
12913 continue;
12914
Egbert Eich7f1950f2014-04-25 10:56:22 +020012915 connector->base.dpms = DRM_MODE_DPMS_OFF;
12916 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012917 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012918 /* multiple connectors may have the same encoder:
12919 * handle them and break crtc link separately */
12920 list_for_each_entry(connector, &dev->mode_config.connector_list,
12921 base.head)
12922 if (connector->encoder->base.crtc == &crtc->base) {
12923 connector->encoder->base.crtc = NULL;
12924 connector->encoder->connectors_active = false;
12925 }
Daniel Vetter24929352012-07-02 20:28:59 +020012926
12927 WARN_ON(crtc->active);
12928 crtc->base.enabled = false;
12929 }
Daniel Vetter24929352012-07-02 20:28:59 +020012930
Daniel Vetter7fad7982012-07-04 17:51:47 +020012931 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12932 crtc->pipe == PIPE_A && !crtc->active) {
12933 /* BIOS forgot to enable pipe A, this mostly happens after
12934 * resume. Force-enable the pipe to fix this, the update_dpms
12935 * call below we restore the pipe to the right state, but leave
12936 * the required bits on. */
12937 intel_enable_pipe_a(dev);
12938 }
12939
Daniel Vetter24929352012-07-02 20:28:59 +020012940 /* Adjust the state of the output pipe according to whether we
12941 * have active connectors/encoders. */
12942 intel_crtc_update_dpms(&crtc->base);
12943
12944 if (crtc->active != crtc->base.enabled) {
12945 struct intel_encoder *encoder;
12946
12947 /* This can happen either due to bugs in the get_hw_state
12948 * functions or because the pipe is force-enabled due to the
12949 * pipe A quirk. */
12950 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12951 crtc->base.base.id,
12952 crtc->base.enabled ? "enabled" : "disabled",
12953 crtc->active ? "enabled" : "disabled");
12954
12955 crtc->base.enabled = crtc->active;
12956
12957 /* Because we only establish the connector -> encoder ->
12958 * crtc links if something is active, this means the
12959 * crtc is now deactivated. Break the links. connector
12960 * -> encoder links are only establish when things are
12961 * actually up, hence no need to break them. */
12962 WARN_ON(crtc->active);
12963
12964 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12965 WARN_ON(encoder->connectors_active);
12966 encoder->base.crtc = NULL;
12967 }
12968 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012969
12970 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010012971 /*
12972 * We start out with underrun reporting disabled to avoid races.
12973 * For correct bookkeeping mark this on active crtcs.
12974 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012975 * Also on gmch platforms we dont have any hardware bits to
12976 * disable the underrun reporting. Which means we need to start
12977 * out with underrun reporting disabled also on inactive pipes,
12978 * since otherwise we'll complain about the garbage we read when
12979 * e.g. coming up after runtime pm.
12980 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010012981 * No protection against concurrent access is required - at
12982 * worst a fifo underrun happens which also sets this to false.
12983 */
12984 crtc->cpu_fifo_underrun_disabled = true;
12985 crtc->pch_fifo_underrun_disabled = true;
Ville Syrjälä80715b22014-05-15 20:23:23 +030012986
12987 update_scanline_offset(crtc);
Daniel Vetter4cc31482014-03-24 00:01:41 +010012988 }
Daniel Vetter24929352012-07-02 20:28:59 +020012989}
12990
12991static void intel_sanitize_encoder(struct intel_encoder *encoder)
12992{
12993 struct intel_connector *connector;
12994 struct drm_device *dev = encoder->base.dev;
12995
12996 /* We need to check both for a crtc link (meaning that the
12997 * encoder is active and trying to read from a pipe) and the
12998 * pipe itself being active. */
12999 bool has_active_crtc = encoder->base.crtc &&
13000 to_intel_crtc(encoder->base.crtc)->active;
13001
13002 if (encoder->connectors_active && !has_active_crtc) {
13003 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13004 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030013005 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013006
13007 /* Connector is active, but has no active pipe. This is
13008 * fallout from our resume register restoring. Disable
13009 * the encoder manually again. */
13010 if (encoder->base.crtc) {
13011 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13012 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030013013 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013014 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030013015 if (encoder->post_disable)
13016 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020013017 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020013018 encoder->base.crtc = NULL;
13019 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020013020
13021 /* Inconsistent output/port/pipe state happens presumably due to
13022 * a bug in one of the get_hw_state functions. Or someplace else
13023 * in our code, like the register restore mess on resume. Clamp
13024 * things to off as a safer default. */
13025 list_for_each_entry(connector,
13026 &dev->mode_config.connector_list,
13027 base.head) {
13028 if (connector->encoder != encoder)
13029 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020013030 connector->base.dpms = DRM_MODE_DPMS_OFF;
13031 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013032 }
13033 }
13034 /* Enabled encoders without active connectors will be fixed in
13035 * the crtc fixup. */
13036}
13037
Imre Deak04098752014-02-18 00:02:16 +020013038void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013039{
13040 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020013041 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013042
Imre Deak04098752014-02-18 00:02:16 +020013043 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13044 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13045 i915_disable_vga(dev);
13046 }
13047}
13048
13049void i915_redisable_vga(struct drm_device *dev)
13050{
13051 struct drm_i915_private *dev_priv = dev->dev_private;
13052
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013053 /* This function can be called both from intel_modeset_setup_hw_state or
13054 * at a very early point in our resume sequence, where the power well
13055 * structures are not yet restored. Since this function is at a very
13056 * paranoid "someone might have enabled VGA while we were not looking"
13057 * level, just check if the power well is enabled instead of trying to
13058 * follow the "don't touch the power well if we don't need it" policy
13059 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020013060 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013061 return;
13062
Imre Deak04098752014-02-18 00:02:16 +020013063 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013064}
13065
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013066static bool primary_get_hw_state(struct intel_crtc *crtc)
13067{
13068 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13069
13070 if (!crtc->active)
13071 return false;
13072
13073 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13074}
13075
Daniel Vetter30e984d2013-06-05 13:34:17 +020013076static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020013077{
13078 struct drm_i915_private *dev_priv = dev->dev_private;
13079 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020013080 struct intel_crtc *crtc;
13081 struct intel_encoder *encoder;
13082 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020013083 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020013084
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013085 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010013086 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020013087
Daniel Vetter99535992014-04-13 12:00:33 +020013088 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13089
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013090 crtc->active = dev_priv->display.get_pipe_config(crtc,
13091 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013092
13093 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013094 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020013095
13096 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13097 crtc->base.base.id,
13098 crtc->active ? "enabled" : "disabled");
13099 }
13100
Daniel Vetter53589012013-06-05 13:34:16 +020013101 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13102 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13103
13104 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13105 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013106 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020013107 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13108 pll->active++;
13109 }
13110 pll->refcount = pll->active;
13111
Daniel Vetter35c95372013-07-17 06:55:04 +020013112 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13113 pll->name, pll->refcount, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013114
13115 if (pll->refcount)
13116 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020013117 }
13118
Damien Lespiaub2784e12014-08-05 11:29:37 +010013119 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013120 pipe = 0;
13121
13122 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013123 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13124 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010013125 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013126 } else {
13127 encoder->base.crtc = NULL;
13128 }
13129
13130 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013131 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020013132 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030013133 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013134 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013135 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020013136 }
13137
13138 list_for_each_entry(connector, &dev->mode_config.connector_list,
13139 base.head) {
13140 if (connector->get_hw_state(connector)) {
13141 connector->base.dpms = DRM_MODE_DPMS_ON;
13142 connector->encoder->connectors_active = true;
13143 connector->base.encoder = &connector->encoder->base;
13144 } else {
13145 connector->base.dpms = DRM_MODE_DPMS_OFF;
13146 connector->base.encoder = NULL;
13147 }
13148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13149 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030013150 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013151 connector->base.encoder ? "enabled" : "disabled");
13152 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020013153}
13154
13155/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13156 * and i915 state tracking structures. */
13157void intel_modeset_setup_hw_state(struct drm_device *dev,
13158 bool force_restore)
13159{
13160 struct drm_i915_private *dev_priv = dev->dev_private;
13161 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013162 struct intel_crtc *crtc;
13163 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020013164 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013165
13166 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020013167
Jesse Barnesbabea612013-06-26 18:57:38 +030013168 /*
13169 * Now that we have the config, copy it to each CRTC struct
13170 * Note that this could go away if we move to using crtc_config
13171 * checking everywhere.
13172 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013173 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020013174 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080013175 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030013176 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13177 crtc->base.base.id);
13178 drm_mode_debug_printmodeline(&crtc->base.mode);
13179 }
13180 }
13181
Daniel Vetter24929352012-07-02 20:28:59 +020013182 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010013183 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013184 intel_sanitize_encoder(encoder);
13185 }
13186
Damien Lespiau055e3932014-08-18 13:49:10 +010013187 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020013188 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13189 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020013190 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020013191 }
Daniel Vetter9a935852012-07-05 22:34:27 +020013192
Daniel Vetter35c95372013-07-17 06:55:04 +020013193 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13194 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13195
13196 if (!pll->on || pll->active)
13197 continue;
13198
13199 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13200
13201 pll->disable(dev_priv, pll);
13202 pll->on = false;
13203 }
13204
Ville Syrjälä96f90c52013-12-05 15:51:38 +020013205 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030013206 ilk_wm_get_hw_state(dev);
13207
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013208 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030013209 i915_redisable_vga(dev);
13210
Daniel Vetterf30da182013-04-11 20:22:50 +020013211 /*
13212 * We need to use raw interfaces for restoring state to avoid
13213 * checking (bogus) intermediate states.
13214 */
Damien Lespiau055e3932014-08-18 13:49:10 +010013215 for_each_pipe(dev_priv, pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070013216 struct drm_crtc *crtc =
13217 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020013218
13219 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070013220 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013221 }
13222 } else {
13223 intel_modeset_update_staged_output_state(dev);
13224 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013225
13226 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010013227}
13228
13229void intel_modeset_gem_init(struct drm_device *dev)
13230{
Jesse Barnes484b41d2014-03-07 08:57:55 -080013231 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070013232 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013233
Imre Deakae484342014-03-31 15:10:44 +030013234 mutex_lock(&dev->struct_mutex);
13235 intel_init_gt_powersave(dev);
13236 mutex_unlock(&dev->struct_mutex);
13237
Chris Wilson1833b132012-05-09 11:56:28 +010013238 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013239
13240 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013241
13242 /*
13243 * Make sure any fbs we allocated at startup are properly
13244 * pinned & fenced. When we do the allocation it's too early
13245 * for this.
13246 */
13247 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013248 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013249 obj = intel_fb_obj(c->primary->fb);
13250 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013251 continue;
13252
Matt Roper2ff8fde2014-07-08 07:50:07 -070013253 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013254 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13255 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013256 drm_framebuffer_unreference(c->primary->fb);
13257 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013258 }
13259 }
13260 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013261}
13262
Imre Deak4932e2c2014-02-11 17:12:48 +020013263void intel_connector_unregister(struct intel_connector *intel_connector)
13264{
13265 struct drm_connector *connector = &intel_connector->base;
13266
13267 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010013268 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020013269}
13270
Jesse Barnes79e53942008-11-07 14:24:08 -080013271void intel_modeset_cleanup(struct drm_device *dev)
13272{
Jesse Barnes652c3932009-08-17 13:31:43 -070013273 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013274 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013275
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013276 /*
13277 * Interrupts and polling as the first thing to avoid creating havoc.
13278 * Too much stuff here (turning of rps, connectors, ...) would
13279 * experience fancy races otherwise.
13280 */
13281 drm_irq_uninstall(dev);
Imre Deak1d0d3432014-08-18 14:42:44 +030013282 intel_hpd_cancel_work(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070013283 dev_priv->pm._irqs_disabled = true;
13284
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013285 /*
13286 * Due to the hpd irq storm handling the hotplug work can re-arm the
13287 * poll handlers. Hence disable polling after hpd handling is shut down.
13288 */
Keith Packardf87ea762010-10-03 19:36:26 -070013289 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013290
Jesse Barnes652c3932009-08-17 13:31:43 -070013291 mutex_lock(&dev->struct_mutex);
13292
Jesse Barnes723bfd72010-10-07 16:01:13 -070013293 intel_unregister_dsm_handler();
13294
Chris Wilson973d04f2011-07-08 12:22:37 +010013295 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013296
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013297 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013298
Daniel Vetter930ebb42012-06-29 23:32:16 +020013299 ironlake_teardown_rc6(dev);
13300
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013301 mutex_unlock(&dev->struct_mutex);
13302
Chris Wilson1630fe72011-07-08 12:22:42 +010013303 /* flush any delayed tasks or pending work */
13304 flush_scheduled_work();
13305
Jani Nikuladb31af1d2013-11-08 16:48:53 +020013306 /* destroy the backlight and sysfs files before encoders/connectors */
13307 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013308 struct intel_connector *intel_connector;
13309
13310 intel_connector = to_intel_connector(connector);
13311 intel_connector->unregister(intel_connector);
Jani Nikuladb31af1d2013-11-08 16:48:53 +020013312 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013313
Jesse Barnes79e53942008-11-07 14:24:08 -080013314 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013315
13316 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013317
13318 mutex_lock(&dev->struct_mutex);
13319 intel_cleanup_gt_powersave(dev);
13320 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013321}
13322
Dave Airlie28d52042009-09-21 14:33:58 +100013323/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013324 * Return which encoder is currently attached for connector.
13325 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013326struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013327{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013328 return &intel_attached_encoder(connector)->base;
13329}
Jesse Barnes79e53942008-11-07 14:24:08 -080013330
Chris Wilsondf0e9242010-09-09 16:20:55 +010013331void intel_connector_attach_encoder(struct intel_connector *connector,
13332 struct intel_encoder *encoder)
13333{
13334 connector->encoder = encoder;
13335 drm_mode_connector_attach_encoder(&connector->base,
13336 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013337}
Dave Airlie28d52042009-09-21 14:33:58 +100013338
13339/*
13340 * set vga decode state - true == enable VGA decode
13341 */
13342int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13343{
13344 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013345 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013346 u16 gmch_ctrl;
13347
Chris Wilson75fa0412014-02-07 18:37:02 -020013348 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13349 DRM_ERROR("failed to read control word\n");
13350 return -EIO;
13351 }
13352
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013353 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13354 return 0;
13355
Dave Airlie28d52042009-09-21 14:33:58 +100013356 if (state)
13357 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13358 else
13359 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013360
13361 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13362 DRM_ERROR("failed to write control word\n");
13363 return -EIO;
13364 }
13365
Dave Airlie28d52042009-09-21 14:33:58 +100013366 return 0;
13367}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013368
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013369struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013370
13371 u32 power_well_driver;
13372
Chris Wilson63b66e52013-08-08 15:12:06 +020013373 int num_transcoders;
13374
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013375 struct intel_cursor_error_state {
13376 u32 control;
13377 u32 position;
13378 u32 base;
13379 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013380 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013381
13382 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013383 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013384 u32 source;
Imre Deakf301b1e12014-04-18 15:55:04 +030013385 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013386 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013387
13388 struct intel_plane_error_state {
13389 u32 control;
13390 u32 stride;
13391 u32 size;
13392 u32 pos;
13393 u32 addr;
13394 u32 surface;
13395 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013396 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013397
13398 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013399 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013400 enum transcoder cpu_transcoder;
13401
13402 u32 conf;
13403
13404 u32 htotal;
13405 u32 hblank;
13406 u32 hsync;
13407 u32 vtotal;
13408 u32 vblank;
13409 u32 vsync;
13410 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013411};
13412
13413struct intel_display_error_state *
13414intel_display_capture_error_state(struct drm_device *dev)
13415{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013416 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013417 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013418 int transcoders[] = {
13419 TRANSCODER_A,
13420 TRANSCODER_B,
13421 TRANSCODER_C,
13422 TRANSCODER_EDP,
13423 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013424 int i;
13425
Chris Wilson63b66e52013-08-08 15:12:06 +020013426 if (INTEL_INFO(dev)->num_pipes == 0)
13427 return NULL;
13428
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013429 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013430 if (error == NULL)
13431 return NULL;
13432
Imre Deak190be112013-11-25 17:15:31 +020013433 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013434 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13435
Damien Lespiau055e3932014-08-18 13:49:10 +010013436 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013437 error->pipe[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013438 intel_display_power_enabled_unlocked(dev_priv,
13439 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013440 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013441 continue;
13442
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013443 error->cursor[i].control = I915_READ(CURCNTR(i));
13444 error->cursor[i].position = I915_READ(CURPOS(i));
13445 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013446
13447 error->plane[i].control = I915_READ(DSPCNTR(i));
13448 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013449 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013450 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013451 error->plane[i].pos = I915_READ(DSPPOS(i));
13452 }
Paulo Zanonica291362013-03-06 20:03:14 -030013453 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13454 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013455 if (INTEL_INFO(dev)->gen >= 4) {
13456 error->plane[i].surface = I915_READ(DSPSURF(i));
13457 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13458 }
13459
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013460 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e12014-04-18 15:55:04 +030013461
Sonika Jindal3abfce72014-07-21 15:23:43 +053013462 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e12014-04-18 15:55:04 +030013463 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013464 }
13465
13466 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13467 if (HAS_DDI(dev_priv->dev))
13468 error->num_transcoders++; /* Account for eDP. */
13469
13470 for (i = 0; i < error->num_transcoders; i++) {
13471 enum transcoder cpu_transcoder = transcoders[i];
13472
Imre Deakddf9c532013-11-27 22:02:02 +020013473 error->transcoder[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013474 intel_display_power_enabled_unlocked(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013475 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013476 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013477 continue;
13478
Chris Wilson63b66e52013-08-08 15:12:06 +020013479 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13480
13481 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13482 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13483 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13484 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13485 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13486 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13487 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013488 }
13489
13490 return error;
13491}
13492
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013493#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13494
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013495void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013496intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013497 struct drm_device *dev,
13498 struct intel_display_error_state *error)
13499{
Damien Lespiau055e3932014-08-18 13:49:10 +010013500 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013501 int i;
13502
Chris Wilson63b66e52013-08-08 15:12:06 +020013503 if (!error)
13504 return;
13505
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013506 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013507 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013508 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013509 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010013510 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013511 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013512 err_printf(m, " Power: %s\n",
13513 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013514 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e12014-04-18 15:55:04 +030013515 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013516
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013517 err_printf(m, "Plane [%d]:\n", i);
13518 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13519 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013520 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013521 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13522 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013523 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013524 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013525 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013526 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013527 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13528 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013529 }
13530
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013531 err_printf(m, "Cursor [%d]:\n", i);
13532 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13533 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13534 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013535 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013536
13537 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013538 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013539 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013540 err_printf(m, " Power: %s\n",
13541 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013542 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13543 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13544 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13545 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13546 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13547 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13548 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13549 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013550}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013551
13552void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13553{
13554 struct intel_crtc *crtc;
13555
13556 for_each_intel_crtc(dev, crtc) {
13557 struct intel_unpin_work *work;
13558 unsigned long irqflags;
13559
13560 spin_lock_irqsave(&dev->event_lock, irqflags);
13561
13562 work = crtc->unpin_work;
13563
13564 if (work && work->event &&
13565 work->event->base.file_priv == file) {
13566 kfree(work->event);
13567 work->event = NULL;
13568 }
13569
13570 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13571 }
13572}