Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 31 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 34 | #include <drm/drm_edid.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drmP.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 39 | #include "i915_trace.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/drm_dp_helper.h> |
| 41 | #include <drm/drm_crtc_helper.h> |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 42 | #include <drm/drm_plane_helper.h> |
| 43 | #include <drm/drm_rect.h> |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 44 | #include <linux/dma_remapping.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 45 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 46 | /* Primary plane formats supported by all gen */ |
| 47 | #define COMMON_PRIMARY_FORMATS \ |
| 48 | DRM_FORMAT_C8, \ |
| 49 | DRM_FORMAT_RGB565, \ |
| 50 | DRM_FORMAT_XRGB8888, \ |
| 51 | DRM_FORMAT_ARGB8888 |
| 52 | |
| 53 | /* Primary plane formats for gen <= 3 */ |
| 54 | static const uint32_t intel_primary_formats_gen2[] = { |
| 55 | COMMON_PRIMARY_FORMATS, |
| 56 | DRM_FORMAT_XRGB1555, |
| 57 | DRM_FORMAT_ARGB1555, |
| 58 | }; |
| 59 | |
| 60 | /* Primary plane formats for gen >= 4 */ |
| 61 | static const uint32_t intel_primary_formats_gen4[] = { |
| 62 | COMMON_PRIMARY_FORMATS, \ |
| 63 | DRM_FORMAT_XBGR8888, |
| 64 | DRM_FORMAT_ABGR8888, |
| 65 | DRM_FORMAT_XRGB2101010, |
| 66 | DRM_FORMAT_ARGB2101010, |
| 67 | DRM_FORMAT_XBGR2101010, |
| 68 | DRM_FORMAT_ABGR2101010, |
| 69 | }; |
| 70 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 71 | /* Cursor formats */ |
| 72 | static const uint32_t intel_cursor_formats[] = { |
| 73 | DRM_FORMAT_ARGB8888, |
| 74 | }; |
| 75 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 78 | |
Daniel Vetter | cc36513 | 2014-06-18 13:59:13 +0200 | [diff] [blame] | 79 | static void intel_increase_pllclock(struct drm_device *dev, |
| 80 | enum pipe pipe); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 82 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 84 | struct intel_crtc_config *pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
| 86 | struct intel_crtc_config *pipe_config); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 87 | |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 89 | int x, int y, struct drm_framebuffer *old_fb); |
Jesse Barnes | eb1bfe8 | 2014-02-12 12:26:25 -0800 | [diff] [blame] | 90 | static int intel_framebuffer_init(struct drm_device *dev, |
| 91 | struct intel_framebuffer *ifb, |
| 92 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 93 | struct drm_i915_gem_object *obj); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
| 95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 97 | struct intel_link_m_n *m_n, |
| 98 | struct intel_link_m_n *m2_n2); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
| 101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 103 | static void chv_prepare_pll(struct intel_crtc *crtc); |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 104 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 105 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
| 106 | { |
| 107 | if (!connector->mst_port) |
| 108 | return connector->encoder; |
| 109 | else |
| 110 | return &connector->mst_port->mst_encoders[pipe]->base; |
| 111 | } |
| 112 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 113 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 114 | int min, max; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 115 | } intel_range_t; |
| 116 | |
| 117 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 118 | int dot_limit; |
| 119 | int p2_slow, p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 120 | } intel_p2_t; |
| 121 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 122 | typedef struct intel_limit intel_limit_t; |
| 123 | struct intel_limit { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 124 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 125 | intel_p2_t p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 126 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 127 | |
Daniel Vetter | d2acd21 | 2012-10-20 20:57:43 +0200 | [diff] [blame] | 128 | int |
| 129 | intel_pch_rawclk(struct drm_device *dev) |
| 130 | { |
| 131 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 132 | |
| 133 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
| 134 | |
| 135 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
| 136 | } |
| 137 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 138 | static inline u32 /* units of 100MHz */ |
| 139 | intel_fdi_link_freq(struct drm_device *dev) |
| 140 | { |
Chris Wilson | 8b99e68 | 2010-10-13 09:59:17 +0100 | [diff] [blame] | 141 | if (IS_GEN5(dev)) { |
| 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 143 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 144 | } else |
| 145 | return 27; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 146 | } |
| 147 | |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 148 | static const intel_limit_t intel_limits_i8xx_dac = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 149 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 150 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 151 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 152 | .m = { .min = 96, .max = 140 }, |
| 153 | .m1 = { .min = 18, .max = 26 }, |
| 154 | .m2 = { .min = 6, .max = 16 }, |
| 155 | .p = { .min = 4, .max = 128 }, |
| 156 | .p1 = { .min = 2, .max = 33 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 157 | .p2 = { .dot_limit = 165000, |
| 158 | .p2_slow = 4, .p2_fast = 2 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 159 | }; |
| 160 | |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 161 | static const intel_limit_t intel_limits_i8xx_dvo = { |
| 162 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 163 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 164 | .n = { .min = 2, .max = 16 }, |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 165 | .m = { .min = 96, .max = 140 }, |
| 166 | .m1 = { .min = 18, .max = 26 }, |
| 167 | .m2 = { .min = 6, .max = 16 }, |
| 168 | .p = { .min = 4, .max = 128 }, |
| 169 | .p1 = { .min = 2, .max = 33 }, |
| 170 | .p2 = { .dot_limit = 165000, |
| 171 | .p2_slow = 4, .p2_fast = 4 }, |
| 172 | }; |
| 173 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 174 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 175 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 176 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 177 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 178 | .m = { .min = 96, .max = 140 }, |
| 179 | .m1 = { .min = 18, .max = 26 }, |
| 180 | .m2 = { .min = 6, .max = 16 }, |
| 181 | .p = { .min = 4, .max = 128 }, |
| 182 | .p1 = { .min = 1, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 183 | .p2 = { .dot_limit = 165000, |
| 184 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 185 | }; |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 186 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 187 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 188 | .dot = { .min = 20000, .max = 400000 }, |
| 189 | .vco = { .min = 1400000, .max = 2800000 }, |
| 190 | .n = { .min = 1, .max = 6 }, |
| 191 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 4f7dfb6 | 2013-02-13 22:20:22 +0100 | [diff] [blame] | 192 | .m1 = { .min = 8, .max = 18 }, |
| 193 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 194 | .p = { .min = 5, .max = 80 }, |
| 195 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 196 | .p2 = { .dot_limit = 200000, |
| 197 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 198 | }; |
| 199 | |
| 200 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 201 | .dot = { .min = 20000, .max = 400000 }, |
| 202 | .vco = { .min = 1400000, .max = 2800000 }, |
| 203 | .n = { .min = 1, .max = 6 }, |
| 204 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 53a7d2d | 2013-02-13 22:20:21 +0100 | [diff] [blame] | 205 | .m1 = { .min = 8, .max = 18 }, |
| 206 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 207 | .p = { .min = 7, .max = 98 }, |
| 208 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 209 | .p2 = { .dot_limit = 112000, |
| 210 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 213 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 214 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 215 | .dot = { .min = 25000, .max = 270000 }, |
| 216 | .vco = { .min = 1750000, .max = 3500000}, |
| 217 | .n = { .min = 1, .max = 4 }, |
| 218 | .m = { .min = 104, .max = 138 }, |
| 219 | .m1 = { .min = 17, .max = 23 }, |
| 220 | .m2 = { .min = 5, .max = 11 }, |
| 221 | .p = { .min = 10, .max = 30 }, |
| 222 | .p1 = { .min = 1, .max = 3}, |
| 223 | .p2 = { .dot_limit = 270000, |
| 224 | .p2_slow = 10, |
| 225 | .p2_fast = 10 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 226 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 230 | .dot = { .min = 22000, .max = 400000 }, |
| 231 | .vco = { .min = 1750000, .max = 3500000}, |
| 232 | .n = { .min = 1, .max = 4 }, |
| 233 | .m = { .min = 104, .max = 138 }, |
| 234 | .m1 = { .min = 16, .max = 23 }, |
| 235 | .m2 = { .min = 5, .max = 11 }, |
| 236 | .p = { .min = 5, .max = 80 }, |
| 237 | .p1 = { .min = 1, .max = 8}, |
| 238 | .p2 = { .dot_limit = 165000, |
| 239 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 240 | }; |
| 241 | |
| 242 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 243 | .dot = { .min = 20000, .max = 115000 }, |
| 244 | .vco = { .min = 1750000, .max = 3500000 }, |
| 245 | .n = { .min = 1, .max = 3 }, |
| 246 | .m = { .min = 104, .max = 138 }, |
| 247 | .m1 = { .min = 17, .max = 23 }, |
| 248 | .m2 = { .min = 5, .max = 11 }, |
| 249 | .p = { .min = 28, .max = 112 }, |
| 250 | .p1 = { .min = 2, .max = 8 }, |
| 251 | .p2 = { .dot_limit = 0, |
| 252 | .p2_slow = 14, .p2_fast = 14 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 253 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 254 | }; |
| 255 | |
| 256 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 257 | .dot = { .min = 80000, .max = 224000 }, |
| 258 | .vco = { .min = 1750000, .max = 3500000 }, |
| 259 | .n = { .min = 1, .max = 3 }, |
| 260 | .m = { .min = 104, .max = 138 }, |
| 261 | .m1 = { .min = 17, .max = 23 }, |
| 262 | .m2 = { .min = 5, .max = 11 }, |
| 263 | .p = { .min = 14, .max = 42 }, |
| 264 | .p1 = { .min = 2, .max = 6 }, |
| 265 | .p2 = { .dot_limit = 0, |
| 266 | .p2_slow = 7, .p2_fast = 7 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 267 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 268 | }; |
| 269 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 271 | .dot = { .min = 20000, .max = 400000}, |
| 272 | .vco = { .min = 1700000, .max = 3500000 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 273 | /* Pineview's Ncounter is a ring counter */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 274 | .n = { .min = 3, .max = 6 }, |
| 275 | .m = { .min = 2, .max = 256 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 277 | .m1 = { .min = 0, .max = 0 }, |
| 278 | .m2 = { .min = 0, .max = 254 }, |
| 279 | .p = { .min = 5, .max = 80 }, |
| 280 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 281 | .p2 = { .dot_limit = 200000, |
| 282 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 283 | }; |
| 284 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 285 | static const intel_limit_t intel_limits_pineview_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 286 | .dot = { .min = 20000, .max = 400000 }, |
| 287 | .vco = { .min = 1700000, .max = 3500000 }, |
| 288 | .n = { .min = 3, .max = 6 }, |
| 289 | .m = { .min = 2, .max = 256 }, |
| 290 | .m1 = { .min = 0, .max = 0 }, |
| 291 | .m2 = { .min = 0, .max = 254 }, |
| 292 | .p = { .min = 7, .max = 112 }, |
| 293 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 294 | .p2 = { .dot_limit = 112000, |
| 295 | .p2_slow = 14, .p2_fast = 14 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 296 | }; |
| 297 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 298 | /* Ironlake / Sandybridge |
| 299 | * |
| 300 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 301 | * the range value for them is (actual_value - 2). |
| 302 | */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 303 | static const intel_limit_t intel_limits_ironlake_dac = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 304 | .dot = { .min = 25000, .max = 350000 }, |
| 305 | .vco = { .min = 1760000, .max = 3510000 }, |
| 306 | .n = { .min = 1, .max = 5 }, |
| 307 | .m = { .min = 79, .max = 127 }, |
| 308 | .m1 = { .min = 12, .max = 22 }, |
| 309 | .m2 = { .min = 5, .max = 9 }, |
| 310 | .p = { .min = 5, .max = 80 }, |
| 311 | .p1 = { .min = 1, .max = 8 }, |
| 312 | .p2 = { .dot_limit = 225000, |
| 313 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 314 | }; |
| 315 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 316 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 317 | .dot = { .min = 25000, .max = 350000 }, |
| 318 | .vco = { .min = 1760000, .max = 3510000 }, |
| 319 | .n = { .min = 1, .max = 3 }, |
| 320 | .m = { .min = 79, .max = 118 }, |
| 321 | .m1 = { .min = 12, .max = 22 }, |
| 322 | .m2 = { .min = 5, .max = 9 }, |
| 323 | .p = { .min = 28, .max = 112 }, |
| 324 | .p1 = { .min = 2, .max = 8 }, |
| 325 | .p2 = { .dot_limit = 225000, |
| 326 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 327 | }; |
| 328 | |
| 329 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 330 | .dot = { .min = 25000, .max = 350000 }, |
| 331 | .vco = { .min = 1760000, .max = 3510000 }, |
| 332 | .n = { .min = 1, .max = 3 }, |
| 333 | .m = { .min = 79, .max = 127 }, |
| 334 | .m1 = { .min = 12, .max = 22 }, |
| 335 | .m2 = { .min = 5, .max = 9 }, |
| 336 | .p = { .min = 14, .max = 56 }, |
| 337 | .p1 = { .min = 2, .max = 8 }, |
| 338 | .p2 = { .dot_limit = 225000, |
| 339 | .p2_slow = 7, .p2_fast = 7 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 340 | }; |
| 341 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 342 | /* LVDS 100mhz refclk limits. */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 343 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 344 | .dot = { .min = 25000, .max = 350000 }, |
| 345 | .vco = { .min = 1760000, .max = 3510000 }, |
| 346 | .n = { .min = 1, .max = 2 }, |
| 347 | .m = { .min = 79, .max = 126 }, |
| 348 | .m1 = { .min = 12, .max = 22 }, |
| 349 | .m2 = { .min = 5, .max = 9 }, |
| 350 | .p = { .min = 28, .max = 112 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 351 | .p1 = { .min = 2, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 352 | .p2 = { .dot_limit = 225000, |
| 353 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 354 | }; |
| 355 | |
| 356 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 357 | .dot = { .min = 25000, .max = 350000 }, |
| 358 | .vco = { .min = 1760000, .max = 3510000 }, |
| 359 | .n = { .min = 1, .max = 3 }, |
| 360 | .m = { .min = 79, .max = 126 }, |
| 361 | .m1 = { .min = 12, .max = 22 }, |
| 362 | .m2 = { .min = 5, .max = 9 }, |
| 363 | .p = { .min = 14, .max = 42 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 364 | .p1 = { .min = 2, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 365 | .p2 = { .dot_limit = 225000, |
| 366 | .p2_slow = 7, .p2_fast = 7 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 367 | }; |
| 368 | |
Ville Syrjälä | dc73051 | 2013-09-24 21:26:30 +0300 | [diff] [blame] | 369 | static const intel_limit_t intel_limits_vlv = { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 370 | /* |
| 371 | * These are the data rate limits (measured in fast clocks) |
| 372 | * since those are the strictest limits we have. The fast |
| 373 | * clock and actual rate limits are more relaxed, so checking |
| 374 | * them would make no difference. |
| 375 | */ |
| 376 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
Daniel Vetter | 75e5398 | 2013-04-18 21:10:43 +0200 | [diff] [blame] | 377 | .vco = { .min = 4000000, .max = 6000000 }, |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 378 | .n = { .min = 1, .max = 7 }, |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 379 | .m1 = { .min = 2, .max = 3 }, |
| 380 | .m2 = { .min = 11, .max = 156 }, |
Ville Syrjälä | b99ab66 | 2013-09-24 21:26:26 +0300 | [diff] [blame] | 381 | .p1 = { .min = 2, .max = 3 }, |
Ville Syrjälä | 5fdc9c49 | 2013-09-24 21:26:29 +0300 | [diff] [blame] | 382 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 383 | }; |
| 384 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 385 | static const intel_limit_t intel_limits_chv = { |
| 386 | /* |
| 387 | * These are the data rate limits (measured in fast clocks) |
| 388 | * since those are the strictest limits we have. The fast |
| 389 | * clock and actual rate limits are more relaxed, so checking |
| 390 | * them would make no difference. |
| 391 | */ |
| 392 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
| 393 | .vco = { .min = 4860000, .max = 6700000 }, |
| 394 | .n = { .min = 1, .max = 1 }, |
| 395 | .m1 = { .min = 2, .max = 2 }, |
| 396 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
| 397 | .p1 = { .min = 2, .max = 4 }, |
| 398 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
| 399 | }; |
| 400 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 401 | static void vlv_clock(int refclk, intel_clock_t *clock) |
| 402 | { |
| 403 | clock->m = clock->m1 * clock->m2; |
| 404 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 405 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 406 | return; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 407 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 408 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 409 | } |
| 410 | |
Paulo Zanoni | e0638cd | 2013-09-24 13:52:54 -0300 | [diff] [blame] | 411 | /** |
| 412 | * Returns whether any output on the specified pipe is of the specified type |
| 413 | */ |
| 414 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
| 415 | { |
| 416 | struct drm_device *dev = crtc->dev; |
| 417 | struct intel_encoder *encoder; |
| 418 | |
| 419 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 420 | if (encoder->type == type) |
| 421 | return true; |
| 422 | |
| 423 | return false; |
| 424 | } |
| 425 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 426 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
| 427 | int refclk) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 428 | { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 429 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 430 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 431 | |
| 432 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 433 | if (intel_is_dual_link_lvds(dev)) { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 434 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 435 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 436 | else |
| 437 | limit = &intel_limits_ironlake_dual_lvds; |
| 438 | } else { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 439 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 440 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 441 | else |
| 442 | limit = &intel_limits_ironlake_single_lvds; |
| 443 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 444 | } else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 445 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 446 | |
| 447 | return limit; |
| 448 | } |
| 449 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 450 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 451 | { |
| 452 | struct drm_device *dev = crtc->dev; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 453 | const intel_limit_t *limit; |
| 454 | |
| 455 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 456 | if (intel_is_dual_link_lvds(dev)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 457 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 458 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 459 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 460 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 461 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 462 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 463 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 464 | limit = &intel_limits_g4x_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 465 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 466 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 467 | |
| 468 | return limit; |
| 469 | } |
| 470 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 471 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 472 | { |
| 473 | struct drm_device *dev = crtc->dev; |
| 474 | const intel_limit_t *limit; |
| 475 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 476 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 477 | limit = intel_ironlake_limit(crtc, refclk); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 478 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 479 | limit = intel_g4x_limit(crtc); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 480 | } else if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 482 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 483 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 484 | limit = &intel_limits_pineview_sdvo; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 485 | } else if (IS_CHERRYVIEW(dev)) { |
| 486 | limit = &intel_limits_chv; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 487 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | dc73051 | 2013-09-24 21:26:30 +0300 | [diff] [blame] | 488 | limit = &intel_limits_vlv; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 489 | } else if (!IS_GEN2(dev)) { |
| 490 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 491 | limit = &intel_limits_i9xx_lvds; |
| 492 | else |
| 493 | limit = &intel_limits_i9xx_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 494 | } else { |
| 495 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 496 | limit = &intel_limits_i8xx_lvds; |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 497 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 498 | limit = &intel_limits_i8xx_dvo; |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 499 | else |
| 500 | limit = &intel_limits_i8xx_dac; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 501 | } |
| 502 | return limit; |
| 503 | } |
| 504 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 505 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 506 | static void pineview_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 507 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 508 | clock->m = clock->m2 + 2; |
| 509 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 510 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 511 | return; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 512 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 513 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 514 | } |
| 515 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 516 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
| 517 | { |
| 518 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
| 519 | } |
| 520 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 521 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 522 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 523 | clock->m = i9xx_dpll_compute_m(clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 524 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 525 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
| 526 | return; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 527 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
| 528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 529 | } |
| 530 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 531 | static void chv_clock(int refclk, intel_clock_t *clock) |
| 532 | { |
| 533 | clock->m = clock->m1 * clock->m2; |
| 534 | clock->p = clock->p1 * clock->p2; |
| 535 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 536 | return; |
| 537 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
| 538 | clock->n << 22); |
| 539 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
| 540 | } |
| 541 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 542 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 543 | /** |
| 544 | * Returns whether the given set of divisors are valid for a given refclk with |
| 545 | * the given connectors. |
| 546 | */ |
| 547 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 548 | static bool intel_PLL_is_valid(struct drm_device *dev, |
| 549 | const intel_limit_t *limit, |
| 550 | const intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 551 | { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 552 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 553 | INTELPllInvalid("n out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 554 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 555 | INTELPllInvalid("p1 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 556 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 557 | INTELPllInvalid("m2 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 558 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 559 | INTELPllInvalid("m1 out of range\n"); |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 560 | |
| 561 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
| 562 | if (clock->m1 <= clock->m2) |
| 563 | INTELPllInvalid("m1 <= m2\n"); |
| 564 | |
| 565 | if (!IS_VALLEYVIEW(dev)) { |
| 566 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 567 | INTELPllInvalid("p out of range\n"); |
| 568 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 569 | INTELPllInvalid("m out of range\n"); |
| 570 | } |
| 571 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 572 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 573 | INTELPllInvalid("vco out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 574 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 575 | * connector, etc., rather than just a single range. |
| 576 | */ |
| 577 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 578 | INTELPllInvalid("dot out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 579 | |
| 580 | return true; |
| 581 | } |
| 582 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 583 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 584 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 585 | int target, int refclk, intel_clock_t *match_clock, |
| 586 | intel_clock_t *best_clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 587 | { |
| 588 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 589 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 590 | int err = target; |
| 591 | |
Daniel Vetter | a210b02 | 2012-11-26 17:22:08 +0100 | [diff] [blame] | 592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 593 | /* |
Daniel Vetter | a210b02 | 2012-11-26 17:22:08 +0100 | [diff] [blame] | 594 | * For LVDS just rely on its current settings for dual-channel. |
| 595 | * We haven't figured out how to reliably set up different |
| 596 | * single/dual channel state, if we even can. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 597 | */ |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 598 | if (intel_is_dual_link_lvds(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 599 | clock.p2 = limit->p2.p2_fast; |
| 600 | else |
| 601 | clock.p2 = limit->p2.p2_slow; |
| 602 | } else { |
| 603 | if (target < limit->p2.dot_limit) |
| 604 | clock.p2 = limit->p2.p2_slow; |
| 605 | else |
| 606 | clock.p2 = limit->p2.p2_fast; |
| 607 | } |
| 608 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 609 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 610 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 611 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 612 | clock.m1++) { |
| 613 | for (clock.m2 = limit->m2.min; |
| 614 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | c0efc38 | 2013-06-03 20:56:24 +0200 | [diff] [blame] | 615 | if (clock.m2 >= clock.m1) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 616 | break; |
| 617 | for (clock.n = limit->n.min; |
| 618 | clock.n <= limit->n.max; clock.n++) { |
| 619 | for (clock.p1 = limit->p1.min; |
| 620 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 621 | int this_err; |
| 622 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 623 | i9xx_clock(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 624 | if (!intel_PLL_is_valid(dev, limit, |
| 625 | &clock)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 626 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 627 | if (match_clock && |
| 628 | clock.p != match_clock->p) |
| 629 | continue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 630 | |
| 631 | this_err = abs(clock.dot - target); |
| 632 | if (this_err < err) { |
| 633 | *best_clock = clock; |
| 634 | err = this_err; |
| 635 | } |
| 636 | } |
| 637 | } |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | return (err != target); |
| 642 | } |
| 643 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 644 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 645 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 646 | int target, int refclk, intel_clock_t *match_clock, |
| 647 | intel_clock_t *best_clock) |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 648 | { |
| 649 | struct drm_device *dev = crtc->dev; |
| 650 | intel_clock_t clock; |
| 651 | int err = target; |
| 652 | |
| 653 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 654 | /* |
| 655 | * For LVDS just rely on its current settings for dual-channel. |
| 656 | * We haven't figured out how to reliably set up different |
| 657 | * single/dual channel state, if we even can. |
| 658 | */ |
| 659 | if (intel_is_dual_link_lvds(dev)) |
| 660 | clock.p2 = limit->p2.p2_fast; |
| 661 | else |
| 662 | clock.p2 = limit->p2.p2_slow; |
| 663 | } else { |
| 664 | if (target < limit->p2.dot_limit) |
| 665 | clock.p2 = limit->p2.p2_slow; |
| 666 | else |
| 667 | clock.p2 = limit->p2.p2_fast; |
| 668 | } |
| 669 | |
| 670 | memset(best_clock, 0, sizeof(*best_clock)); |
| 671 | |
| 672 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 673 | clock.m1++) { |
| 674 | for (clock.m2 = limit->m2.min; |
| 675 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 676 | for (clock.n = limit->n.min; |
| 677 | clock.n <= limit->n.max; clock.n++) { |
| 678 | for (clock.p1 = limit->p1.min; |
| 679 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 680 | int this_err; |
| 681 | |
| 682 | pineview_clock(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 683 | if (!intel_PLL_is_valid(dev, limit, |
| 684 | &clock)) |
| 685 | continue; |
| 686 | if (match_clock && |
| 687 | clock.p != match_clock->p) |
| 688 | continue; |
| 689 | |
| 690 | this_err = abs(clock.dot - target); |
| 691 | if (this_err < err) { |
| 692 | *best_clock = clock; |
| 693 | err = this_err; |
| 694 | } |
| 695 | } |
| 696 | } |
| 697 | } |
| 698 | } |
| 699 | |
| 700 | return (err != target); |
| 701 | } |
| 702 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 703 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 704 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 705 | int target, int refclk, intel_clock_t *match_clock, |
| 706 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 707 | { |
| 708 | struct drm_device *dev = crtc->dev; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 709 | intel_clock_t clock; |
| 710 | int max_n; |
| 711 | bool found; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 712 | /* approximately equals target * 0.00585 */ |
| 713 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 714 | found = false; |
| 715 | |
| 716 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 717 | if (intel_is_dual_link_lvds(dev)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 718 | clock.p2 = limit->p2.p2_fast; |
| 719 | else |
| 720 | clock.p2 = limit->p2.p2_slow; |
| 721 | } else { |
| 722 | if (target < limit->p2.dot_limit) |
| 723 | clock.p2 = limit->p2.p2_slow; |
| 724 | else |
| 725 | clock.p2 = limit->p2.p2_fast; |
| 726 | } |
| 727 | |
| 728 | memset(best_clock, 0, sizeof(*best_clock)); |
| 729 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 730 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 731 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 732 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 733 | for (clock.m1 = limit->m1.max; |
| 734 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 735 | for (clock.m2 = limit->m2.max; |
| 736 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 737 | for (clock.p1 = limit->p1.max; |
| 738 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 739 | int this_err; |
| 740 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 741 | i9xx_clock(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 742 | if (!intel_PLL_is_valid(dev, limit, |
| 743 | &clock)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 744 | continue; |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 745 | |
| 746 | this_err = abs(clock.dot - target); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 747 | if (this_err < err_most) { |
| 748 | *best_clock = clock; |
| 749 | err_most = this_err; |
| 750 | max_n = clock.n; |
| 751 | found = true; |
| 752 | } |
| 753 | } |
| 754 | } |
| 755 | } |
| 756 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 757 | return found; |
| 758 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 759 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 760 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 761 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 762 | int target, int refclk, intel_clock_t *match_clock, |
| 763 | intel_clock_t *best_clock) |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 764 | { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 765 | struct drm_device *dev = crtc->dev; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 766 | intel_clock_t clock; |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 767 | unsigned int bestppm = 1000000; |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 768 | /* min update 19.2 MHz */ |
| 769 | int max_n = min(limit->n.max, refclk / 19200); |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 770 | bool found = false; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 771 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 772 | target *= 5; /* fast clock */ |
| 773 | |
| 774 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 775 | |
| 776 | /* based on hardware requirement, prefer smaller n to precision */ |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 777 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Ville Syrjälä | 811bbf0 | 2013-09-24 21:26:25 +0300 | [diff] [blame] | 778 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
Ville Syrjälä | 889059d | 2013-09-24 21:26:27 +0300 | [diff] [blame] | 779 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
Ville Syrjälä | c1a9ae4 | 2013-09-24 21:26:23 +0300 | [diff] [blame] | 780 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 781 | clock.p = clock.p1 * clock.p2; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 782 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 783 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 784 | unsigned int ppm, diff; |
| 785 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 786 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
| 787 | refclk * clock.m1); |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 788 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 789 | vlv_clock(refclk, &clock); |
| 790 | |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 791 | if (!intel_PLL_is_valid(dev, limit, |
| 792 | &clock)) |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 793 | continue; |
| 794 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 795 | diff = abs(clock.dot - target); |
| 796 | ppm = div_u64(1000000ULL * diff, target); |
| 797 | |
| 798 | if (ppm < 100 && clock.p > best_clock->p) { |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 799 | bestppm = 0; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 800 | *best_clock = clock; |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 801 | found = true; |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 802 | } |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 803 | |
Ville Syrjälä | c686122 | 2013-09-24 21:26:21 +0300 | [diff] [blame] | 804 | if (bestppm >= 10 && ppm < bestppm - 10) { |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 805 | bestppm = ppm; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 806 | *best_clock = clock; |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 807 | found = true; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 808 | } |
| 809 | } |
| 810 | } |
| 811 | } |
| 812 | } |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 813 | |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 814 | return found; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 815 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 816 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 817 | static bool |
| 818 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 819 | int target, int refclk, intel_clock_t *match_clock, |
| 820 | intel_clock_t *best_clock) |
| 821 | { |
| 822 | struct drm_device *dev = crtc->dev; |
| 823 | intel_clock_t clock; |
| 824 | uint64_t m2; |
| 825 | int found = false; |
| 826 | |
| 827 | memset(best_clock, 0, sizeof(*best_clock)); |
| 828 | |
| 829 | /* |
| 830 | * Based on hardware doc, the n always set to 1, and m1 always |
| 831 | * set to 2. If requires to support 200Mhz refclk, we need to |
| 832 | * revisit this because n may not 1 anymore. |
| 833 | */ |
| 834 | clock.n = 1, clock.m1 = 2; |
| 835 | target *= 5; /* fast clock */ |
| 836 | |
| 837 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 838 | for (clock.p2 = limit->p2.p2_fast; |
| 839 | clock.p2 >= limit->p2.p2_slow; |
| 840 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
| 841 | |
| 842 | clock.p = clock.p1 * clock.p2; |
| 843 | |
| 844 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * |
| 845 | clock.n) << 22, refclk * clock.m1); |
| 846 | |
| 847 | if (m2 > INT_MAX/clock.m1) |
| 848 | continue; |
| 849 | |
| 850 | clock.m2 = m2; |
| 851 | |
| 852 | chv_clock(refclk, &clock); |
| 853 | |
| 854 | if (!intel_PLL_is_valid(dev, limit, &clock)) |
| 855 | continue; |
| 856 | |
| 857 | /* based on hardware requirement, prefer bigger p |
| 858 | */ |
| 859 | if (clock.p > best_clock->p) { |
| 860 | *best_clock = clock; |
| 861 | found = true; |
| 862 | } |
| 863 | } |
| 864 | } |
| 865 | |
| 866 | return found; |
| 867 | } |
| 868 | |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 869 | bool intel_crtc_active(struct drm_crtc *crtc) |
| 870 | { |
| 871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 872 | |
| 873 | /* Be paranoid as we can arrive here with only partial |
| 874 | * state retrieved from the hardware during setup. |
| 875 | * |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 876 | * We can ditch the adjusted_mode.crtc_clock check as soon |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 877 | * as Haswell has gained clock readout/fastboot support. |
| 878 | * |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 879 | * We can ditch the crtc->primary->fb check as soon as we can |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 880 | * properly reconstruct framebuffers. |
| 881 | */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 882 | return intel_crtc->active && crtc->primary->fb && |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 883 | intel_crtc->config.adjusted_mode.crtc_clock; |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 884 | } |
| 885 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 886 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 887 | enum pipe pipe) |
| 888 | { |
| 889 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 891 | |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 892 | return intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 893 | } |
| 894 | |
Ville Syrjälä | 57e22f4 | 2013-11-06 13:56:28 -0200 | [diff] [blame] | 895 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 896 | { |
| 897 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 57e22f4 | 2013-11-06 13:56:28 -0200 | [diff] [blame] | 898 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 899 | |
| 900 | frame = I915_READ(frame_reg); |
| 901 | |
| 902 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
Damien Lespiau | 31e4b89 | 2014-08-18 13:51:00 +0100 | [diff] [blame] | 903 | WARN(1, "vblank wait on pipe %c timed out\n", |
| 904 | pipe_name(pipe)); |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 905 | } |
| 906 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 907 | /** |
| 908 | * intel_wait_for_vblank - wait for vblank on a given pipe |
| 909 | * @dev: drm device |
| 910 | * @pipe: pipe to wait for |
| 911 | * |
| 912 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
| 913 | * mode setting code. |
| 914 | */ |
| 915 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 916 | { |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 917 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 918 | int pipestat_reg = PIPESTAT(pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 919 | |
Ville Syrjälä | 57e22f4 | 2013-11-06 13:56:28 -0200 | [diff] [blame] | 920 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
| 921 | g4x_wait_for_vblank(dev, pipe); |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 922 | return; |
| 923 | } |
| 924 | |
Chris Wilson | 300387c | 2010-09-05 20:25:43 +0100 | [diff] [blame] | 925 | /* Clear existing vblank status. Note this will clear any other |
| 926 | * sticky status fields as well. |
| 927 | * |
| 928 | * This races with i915_driver_irq_handler() with the result |
| 929 | * that either function could miss a vblank event. Here it is not |
| 930 | * fatal, as we will either wait upon the next vblank interrupt or |
| 931 | * timeout. Generally speaking intel_wait_for_vblank() is only |
| 932 | * called during modeset at which time the GPU should be idle and |
| 933 | * should *not* be performing page flips and thus not waiting on |
| 934 | * vblanks... |
| 935 | * Currently, the result of us stealing a vblank from the irq |
| 936 | * handler is that a single frame will be skipped during swapbuffers. |
| 937 | */ |
| 938 | I915_WRITE(pipestat_reg, |
| 939 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
| 940 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 941 | /* Wait for vblank interrupt bit to set */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 942 | if (wait_for(I915_READ(pipestat_reg) & |
| 943 | PIPE_VBLANK_INTERRUPT_STATUS, |
| 944 | 50)) |
Damien Lespiau | 31e4b89 | 2014-08-18 13:51:00 +0100 | [diff] [blame] | 945 | DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n", |
| 946 | pipe_name(pipe)); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 947 | } |
| 948 | |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 949 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
| 950 | { |
| 951 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 952 | u32 reg = PIPEDSL(pipe); |
| 953 | u32 line1, line2; |
| 954 | u32 line_mask; |
| 955 | |
| 956 | if (IS_GEN2(dev)) |
| 957 | line_mask = DSL_LINEMASK_GEN2; |
| 958 | else |
| 959 | line_mask = DSL_LINEMASK_GEN3; |
| 960 | |
| 961 | line1 = I915_READ(reg) & line_mask; |
| 962 | mdelay(5); |
| 963 | line2 = I915_READ(reg) & line_mask; |
| 964 | |
| 965 | return line1 == line2; |
| 966 | } |
| 967 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 968 | /* |
| 969 | * intel_wait_for_pipe_off - wait for pipe to turn off |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 970 | * @dev: drm device |
| 971 | * @pipe: pipe to wait for |
| 972 | * |
| 973 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 974 | * spinning on the vblank interrupt status bit, since we won't actually |
| 975 | * see an interrupt when the pipe is disabled. |
| 976 | * |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 977 | * On Gen4 and above: |
| 978 | * wait for the pipe register state bit to turn off |
| 979 | * |
| 980 | * Otherwise: |
| 981 | * wait for the display line value to settle (it usually |
| 982 | * ends up stopping at the start of the next frame). |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 983 | * |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 984 | */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 985 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 986 | { |
| 987 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 988 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 989 | pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 990 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 991 | if (INTEL_INFO(dev)->gen >= 4) { |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 992 | int reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 993 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 994 | /* Wait for the Pipe State to go off */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 995 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
| 996 | 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 997 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 998 | } else { |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 999 | /* Wait for the display line to settle */ |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1000 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 1001 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1002 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1003 | } |
| 1004 | |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 1005 | /* |
| 1006 | * ibx_digital_port_connected - is the specified port connected? |
| 1007 | * @dev_priv: i915 private structure |
| 1008 | * @port: the port to test |
| 1009 | * |
| 1010 | * Returns true if @port is connected, false otherwise. |
| 1011 | */ |
| 1012 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 1013 | struct intel_digital_port *port) |
| 1014 | { |
| 1015 | u32 bit; |
| 1016 | |
Damien Lespiau | c36346e | 2012-12-13 16:09:03 +0000 | [diff] [blame] | 1017 | if (HAS_PCH_IBX(dev_priv->dev)) { |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 1018 | switch (port->port) { |
Damien Lespiau | c36346e | 2012-12-13 16:09:03 +0000 | [diff] [blame] | 1019 | case PORT_B: |
| 1020 | bit = SDE_PORTB_HOTPLUG; |
| 1021 | break; |
| 1022 | case PORT_C: |
| 1023 | bit = SDE_PORTC_HOTPLUG; |
| 1024 | break; |
| 1025 | case PORT_D: |
| 1026 | bit = SDE_PORTD_HOTPLUG; |
| 1027 | break; |
| 1028 | default: |
| 1029 | return true; |
| 1030 | } |
| 1031 | } else { |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 1032 | switch (port->port) { |
Damien Lespiau | c36346e | 2012-12-13 16:09:03 +0000 | [diff] [blame] | 1033 | case PORT_B: |
| 1034 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 1035 | break; |
| 1036 | case PORT_C: |
| 1037 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 1038 | break; |
| 1039 | case PORT_D: |
| 1040 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 1041 | break; |
| 1042 | default: |
| 1043 | return true; |
| 1044 | } |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 1045 | } |
| 1046 | |
| 1047 | return I915_READ(SDEISR) & bit; |
| 1048 | } |
| 1049 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1050 | static const char *state_string(bool enabled) |
| 1051 | { |
| 1052 | return enabled ? "on" : "off"; |
| 1053 | } |
| 1054 | |
| 1055 | /* Only for pre-ILK configs */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1056 | void assert_pll(struct drm_i915_private *dev_priv, |
| 1057 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1058 | { |
| 1059 | int reg; |
| 1060 | u32 val; |
| 1061 | bool cur_state; |
| 1062 | |
| 1063 | reg = DPLL(pipe); |
| 1064 | val = I915_READ(reg); |
| 1065 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 1066 | WARN(cur_state != state, |
| 1067 | "PLL state assertion failure (expected %s, current %s)\n", |
| 1068 | state_string(state), state_string(cur_state)); |
| 1069 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1070 | |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1071 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
| 1072 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
| 1073 | { |
| 1074 | u32 val; |
| 1075 | bool cur_state; |
| 1076 | |
| 1077 | mutex_lock(&dev_priv->dpio_lock); |
| 1078 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
| 1079 | mutex_unlock(&dev_priv->dpio_lock); |
| 1080 | |
| 1081 | cur_state = val & DSI_PLL_VCO_EN; |
| 1082 | WARN(cur_state != state, |
| 1083 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
| 1084 | state_string(state), state_string(cur_state)); |
| 1085 | } |
| 1086 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
| 1087 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
| 1088 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1089 | struct intel_shared_dpll * |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1090 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1091 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1092 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 1093 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 1094 | if (crtc->config.shared_dpll < 0) |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1095 | return NULL; |
| 1096 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 1097 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1098 | } |
| 1099 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1100 | /* For ILK+ */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1101 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 1102 | struct intel_shared_dpll *pll, |
| 1103 | bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1104 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1105 | bool cur_state; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 1106 | struct intel_dpll_hw_state hw_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1107 | |
Chris Wilson | 92b27b0 | 2012-05-20 18:10:50 +0100 | [diff] [blame] | 1108 | if (WARN (!pll, |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1109 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1110 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1111 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 1112 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
Chris Wilson | 92b27b0 | 2012-05-20 18:10:50 +0100 | [diff] [blame] | 1113 | WARN(cur_state != state, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 1114 | "%s assertion failure (expected %s, current %s)\n", |
| 1115 | pll->name, state_string(state), state_string(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1116 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1117 | |
| 1118 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 1119 | enum pipe pipe, bool state) |
| 1120 | { |
| 1121 | int reg; |
| 1122 | u32 val; |
| 1123 | bool cur_state; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1124 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1125 | pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1126 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1127 | if (HAS_DDI(dev_priv->dev)) { |
| 1128 | /* DDI does not have a specific FDI_TX register */ |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1129 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1130 | val = I915_READ(reg); |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1131 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1132 | } else { |
| 1133 | reg = FDI_TX_CTL(pipe); |
| 1134 | val = I915_READ(reg); |
| 1135 | cur_state = !!(val & FDI_TX_ENABLE); |
| 1136 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1137 | WARN(cur_state != state, |
| 1138 | "FDI TX state assertion failure (expected %s, current %s)\n", |
| 1139 | state_string(state), state_string(cur_state)); |
| 1140 | } |
| 1141 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 1142 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 1143 | |
| 1144 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 1145 | enum pipe pipe, bool state) |
| 1146 | { |
| 1147 | int reg; |
| 1148 | u32 val; |
| 1149 | bool cur_state; |
| 1150 | |
Paulo Zanoni | d63fa0d | 2012-11-20 13:27:35 -0200 | [diff] [blame] | 1151 | reg = FDI_RX_CTL(pipe); |
| 1152 | val = I915_READ(reg); |
| 1153 | cur_state = !!(val & FDI_RX_ENABLE); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1154 | WARN(cur_state != state, |
| 1155 | "FDI RX state assertion failure (expected %s, current %s)\n", |
| 1156 | state_string(state), state_string(cur_state)); |
| 1157 | } |
| 1158 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 1159 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 1160 | |
| 1161 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 1162 | enum pipe pipe) |
| 1163 | { |
| 1164 | int reg; |
| 1165 | u32 val; |
| 1166 | |
| 1167 | /* ILK FDI PLL is always enabled */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1168 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1169 | return; |
| 1170 | |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1171 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1172 | if (HAS_DDI(dev_priv->dev)) |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1173 | return; |
| 1174 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1175 | reg = FDI_TX_CTL(pipe); |
| 1176 | val = I915_READ(reg); |
| 1177 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
| 1178 | } |
| 1179 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1180 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 1181 | enum pipe pipe, bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1182 | { |
| 1183 | int reg; |
| 1184 | u32 val; |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1185 | bool cur_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1186 | |
| 1187 | reg = FDI_RX_CTL(pipe); |
| 1188 | val = I915_READ(reg); |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1189 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
| 1190 | WARN(cur_state != state, |
| 1191 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
| 1192 | state_string(state), state_string(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1193 | } |
| 1194 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1195 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 1196 | enum pipe pipe) |
| 1197 | { |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1198 | struct drm_device *dev = dev_priv->dev; |
| 1199 | int pp_reg; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1200 | u32 val; |
| 1201 | enum pipe panel_pipe = PIPE_A; |
Thomas Jarosch | 0de3b48 | 2011-08-25 15:37:45 +0200 | [diff] [blame] | 1202 | bool locked = true; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1203 | |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1204 | if (WARN_ON(HAS_DDI(dev))) |
| 1205 | return; |
| 1206 | |
| 1207 | if (HAS_PCH_SPLIT(dev)) { |
| 1208 | u32 port_sel; |
| 1209 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1210 | pp_reg = PCH_PP_CONTROL; |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1211 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
| 1212 | |
| 1213 | if (port_sel == PANEL_PORT_SELECT_LVDS && |
| 1214 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) |
| 1215 | panel_pipe = PIPE_B; |
| 1216 | /* XXX: else fix for eDP */ |
| 1217 | } else if (IS_VALLEYVIEW(dev)) { |
| 1218 | /* presumably write lock depends on pipe, not port select */ |
| 1219 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 1220 | panel_pipe = pipe; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1221 | } else { |
| 1222 | pp_reg = PP_CONTROL; |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1223 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
| 1224 | panel_pipe = PIPE_B; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1225 | } |
| 1226 | |
| 1227 | val = I915_READ(pp_reg); |
| 1228 | if (!(val & PANEL_POWER_ON) || |
Jani Nikula | ec49ba2 | 2014-08-21 15:06:25 +0300 | [diff] [blame] | 1229 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1230 | locked = false; |
| 1231 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1232 | WARN(panel_pipe == pipe && locked, |
| 1233 | "panel assertion failure, pipe %c regs locked\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1234 | pipe_name(pipe)); |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1235 | } |
| 1236 | |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1237 | static void assert_cursor(struct drm_i915_private *dev_priv, |
| 1238 | enum pipe pipe, bool state) |
| 1239 | { |
| 1240 | struct drm_device *dev = dev_priv->dev; |
| 1241 | bool cur_state; |
| 1242 | |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1243 | if (IS_845G(dev) || IS_I865G(dev)) |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1244 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1245 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 1246 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1247 | |
| 1248 | WARN(cur_state != state, |
| 1249 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
| 1250 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
| 1251 | } |
| 1252 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
| 1253 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
| 1254 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1255 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 1256 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1257 | { |
| 1258 | int reg; |
| 1259 | u32 val; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1260 | bool cur_state; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1261 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1262 | pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1263 | |
Daniel Vetter | 8e63678 | 2012-01-22 01:36:48 +0100 | [diff] [blame] | 1264 | /* if we need the pipe A quirk it must be always on */ |
| 1265 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
| 1266 | state = true; |
| 1267 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1268 | if (!intel_display_power_enabled(dev_priv, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 1269 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
Paulo Zanoni | 6931016 | 2013-01-29 16:35:19 -0200 | [diff] [blame] | 1270 | cur_state = false; |
| 1271 | } else { |
| 1272 | reg = PIPECONF(cpu_transcoder); |
| 1273 | val = I915_READ(reg); |
| 1274 | cur_state = !!(val & PIPECONF_ENABLE); |
| 1275 | } |
| 1276 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1277 | WARN(cur_state != state, |
| 1278 | "pipe %c assertion failure (expected %s, current %s)\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1279 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1280 | } |
| 1281 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1282 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 1283 | enum plane plane, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1284 | { |
| 1285 | int reg; |
| 1286 | u32 val; |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1287 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1288 | |
| 1289 | reg = DSPCNTR(plane); |
| 1290 | val = I915_READ(reg); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1291 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
| 1292 | WARN(cur_state != state, |
| 1293 | "plane %c assertion failure (expected %s, current %s)\n", |
| 1294 | plane_name(plane), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1295 | } |
| 1296 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1297 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 1298 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 1299 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1300 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 1301 | enum pipe pipe) |
| 1302 | { |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1303 | struct drm_device *dev = dev_priv->dev; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1304 | int reg, i; |
| 1305 | u32 val; |
| 1306 | int cur_pipe; |
| 1307 | |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1308 | /* Primary planes are fixed to pipes on gen4+ */ |
| 1309 | if (INTEL_INFO(dev)->gen >= 4) { |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1310 | reg = DSPCNTR(pipe); |
| 1311 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1312 | WARN(val & DISPLAY_PLANE_ENABLE, |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1313 | "plane %c assertion failure, should be disabled but not\n", |
| 1314 | plane_name(pipe)); |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1315 | return; |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1316 | } |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1317 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1318 | /* Need to check both planes against the pipe */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1319 | for_each_pipe(dev_priv, i) { |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1320 | reg = DSPCNTR(i); |
| 1321 | val = I915_READ(reg); |
| 1322 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
| 1323 | DISPPLANE_SEL_PIPE_SHIFT; |
| 1324 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1325 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 1326 | plane_name(i), pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1327 | } |
| 1328 | } |
| 1329 | |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1330 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
| 1331 | enum pipe pipe) |
| 1332 | { |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1333 | struct drm_device *dev = dev_priv->dev; |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1334 | int reg, sprite; |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1335 | u32 val; |
| 1336 | |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1337 | if (IS_VALLEYVIEW(dev)) { |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1338 | for_each_sprite(pipe, sprite) { |
| 1339 | reg = SPCNTR(pipe, sprite); |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1340 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1341 | WARN(val & SP_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1342 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1343 | sprite_name(pipe, sprite), pipe_name(pipe)); |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1344 | } |
| 1345 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 1346 | reg = SPRCTL(pipe); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1347 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1348 | WARN(val & SPRITE_ENABLE, |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 1349 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1350 | plane_name(pipe), pipe_name(pipe)); |
| 1351 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 1352 | reg = DVSCNTR(pipe); |
| 1353 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1354 | WARN(val & DVS_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1355 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1356 | plane_name(pipe), pipe_name(pipe)); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1357 | } |
| 1358 | } |
| 1359 | |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 1360 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1361 | { |
| 1362 | u32 val; |
| 1363 | bool enabled; |
| 1364 | |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 1365 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
Eugeni Dodonov | 9d82aa1 | 2012-05-09 15:37:17 -0300 | [diff] [blame] | 1366 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1367 | val = I915_READ(PCH_DREF_CONTROL); |
| 1368 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 1369 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 1370 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 1371 | } |
| 1372 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1373 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1374 | enum pipe pipe) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1375 | { |
| 1376 | int reg; |
| 1377 | u32 val; |
| 1378 | bool enabled; |
| 1379 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1380 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1381 | val = I915_READ(reg); |
| 1382 | enabled = !!(val & TRANS_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1383 | WARN(enabled, |
| 1384 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1385 | pipe_name(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1386 | } |
| 1387 | |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1388 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1389 | enum pipe pipe, u32 port_sel, u32 val) |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1390 | { |
| 1391 | if ((val & DP_PORT_EN) == 0) |
| 1392 | return false; |
| 1393 | |
| 1394 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1395 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
| 1396 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
| 1397 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1398 | return false; |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1399 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1400 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
| 1401 | return false; |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1402 | } else { |
| 1403 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1404 | return false; |
| 1405 | } |
| 1406 | return true; |
| 1407 | } |
| 1408 | |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1409 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1410 | enum pipe pipe, u32 val) |
| 1411 | { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1412 | if ((val & SDVO_ENABLE) == 0) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1413 | return false; |
| 1414 | |
| 1415 | if (HAS_PCH_CPT(dev_priv->dev)) { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1416 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1417 | return false; |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1418 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1419 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
| 1420 | return false; |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1421 | } else { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1422 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1423 | return false; |
| 1424 | } |
| 1425 | return true; |
| 1426 | } |
| 1427 | |
| 1428 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1429 | enum pipe pipe, u32 val) |
| 1430 | { |
| 1431 | if ((val & LVDS_PORT_EN) == 0) |
| 1432 | return false; |
| 1433 | |
| 1434 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1435 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1436 | return false; |
| 1437 | } else { |
| 1438 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1439 | return false; |
| 1440 | } |
| 1441 | return true; |
| 1442 | } |
| 1443 | |
| 1444 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1445 | enum pipe pipe, u32 val) |
| 1446 | { |
| 1447 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1448 | return false; |
| 1449 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1450 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1451 | return false; |
| 1452 | } else { |
| 1453 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1454 | return false; |
| 1455 | } |
| 1456 | return true; |
| 1457 | } |
| 1458 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1459 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1460 | enum pipe pipe, int reg, u32 port_sel) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1461 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1462 | u32 val = I915_READ(reg); |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1463 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1464 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1465 | reg, pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1466 | |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1467 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
| 1468 | && (val & DP_PIPEB_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1469 | "IBX PCH dp port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1470 | } |
| 1471 | |
| 1472 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
| 1473 | enum pipe pipe, int reg) |
| 1474 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1475 | u32 val = I915_READ(reg); |
Xu, Anhua | b70ad58 | 2012-08-13 03:08:33 +0000 | [diff] [blame] | 1476 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
Adam Jackson | 23c99e7 | 2011-10-07 14:38:43 -0400 | [diff] [blame] | 1477 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1478 | reg, pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1479 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1480 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1481 | && (val & SDVO_PIPE_B_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1482 | "IBX PCH hdmi port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1483 | } |
| 1484 | |
| 1485 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1486 | enum pipe pipe) |
| 1487 | { |
| 1488 | int reg; |
| 1489 | u32 val; |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1490 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1491 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1492 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1493 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1494 | |
| 1495 | reg = PCH_ADPA; |
| 1496 | val = I915_READ(reg); |
Xu, Anhua | b70ad58 | 2012-08-13 03:08:33 +0000 | [diff] [blame] | 1497 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1498 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1499 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1500 | |
| 1501 | reg = PCH_LVDS; |
| 1502 | val = I915_READ(reg); |
Xu, Anhua | b70ad58 | 2012-08-13 03:08:33 +0000 | [diff] [blame] | 1503 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1504 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1505 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1506 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 1507 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
| 1508 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
| 1509 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1510 | } |
| 1511 | |
Jesse Barnes | 40e9cf6 | 2013-10-03 11:35:46 -0700 | [diff] [blame] | 1512 | static void intel_init_dpio(struct drm_device *dev) |
| 1513 | { |
| 1514 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1515 | |
| 1516 | if (!IS_VALLEYVIEW(dev)) |
| 1517 | return; |
| 1518 | |
Chon Ming Lee | a09cadd | 2014-04-09 13:28:14 +0300 | [diff] [blame] | 1519 | /* |
| 1520 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), |
| 1521 | * CHV x1 PHY (DP/HDMI D) |
| 1522 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) |
| 1523 | */ |
| 1524 | if (IS_CHERRYVIEW(dev)) { |
| 1525 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; |
| 1526 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; |
| 1527 | } else { |
| 1528 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
| 1529 | } |
Jesse Barnes | 5382f5f35 | 2013-12-16 16:34:24 -0800 | [diff] [blame] | 1530 | } |
| 1531 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1532 | static void vlv_enable_pll(struct intel_crtc *crtc) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1533 | { |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1534 | struct drm_device *dev = crtc->base.dev; |
| 1535 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1536 | int reg = DPLL(crtc->pipe); |
| 1537 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1538 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1539 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1540 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1541 | /* No really, not for ILK+ */ |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1542 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
| 1543 | |
| 1544 | /* PLL is protected by panel, make sure we can write it */ |
Jani Nikula | 6a9e736 | 2014-08-22 15:06:35 +0300 | [diff] [blame] | 1545 | if (IS_MOBILE(dev_priv->dev)) |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1546 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1547 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1548 | I915_WRITE(reg, dpll); |
| 1549 | POSTING_READ(reg); |
| 1550 | udelay(150); |
| 1551 | |
| 1552 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
| 1553 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
| 1554 | |
| 1555 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
| 1556 | POSTING_READ(DPLL_MD(crtc->pipe)); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1557 | |
| 1558 | /* We do this three times for luck */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1559 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1560 | POSTING_READ(reg); |
| 1561 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1562 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1563 | POSTING_READ(reg); |
| 1564 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1565 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1566 | POSTING_READ(reg); |
| 1567 | udelay(150); /* wait for warmup */ |
| 1568 | } |
| 1569 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1570 | static void chv_enable_pll(struct intel_crtc *crtc) |
| 1571 | { |
| 1572 | struct drm_device *dev = crtc->base.dev; |
| 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1574 | int pipe = crtc->pipe; |
| 1575 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1576 | u32 tmp; |
| 1577 | |
| 1578 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 1579 | |
| 1580 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); |
| 1581 | |
| 1582 | mutex_lock(&dev_priv->dpio_lock); |
| 1583 | |
| 1584 | /* Enable back the 10bit clock to display controller */ |
| 1585 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1586 | tmp |= DPIO_DCLKP_EN; |
| 1587 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
| 1588 | |
| 1589 | /* |
| 1590 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
| 1591 | */ |
| 1592 | udelay(1); |
| 1593 | |
| 1594 | /* Enable PLL */ |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1595 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1596 | |
| 1597 | /* Check PLL is locked */ |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1598 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1599 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
| 1600 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1601 | /* not sure when this should be written */ |
| 1602 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); |
| 1603 | POSTING_READ(DPLL_MD(pipe)); |
| 1604 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1605 | mutex_unlock(&dev_priv->dpio_lock); |
| 1606 | } |
| 1607 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1608 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1609 | { |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1610 | struct drm_device *dev = crtc->base.dev; |
| 1611 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1612 | int reg = DPLL(crtc->pipe); |
| 1613 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1614 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1615 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1616 | |
| 1617 | /* No really, not for ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1618 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1619 | |
| 1620 | /* PLL is protected by panel, make sure we can write it */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1621 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
| 1622 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1623 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1624 | I915_WRITE(reg, dpll); |
| 1625 | |
| 1626 | /* Wait for the clocks to stabilize. */ |
| 1627 | POSTING_READ(reg); |
| 1628 | udelay(150); |
| 1629 | |
| 1630 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1631 | I915_WRITE(DPLL_MD(crtc->pipe), |
| 1632 | crtc->config.dpll_hw_state.dpll_md); |
| 1633 | } else { |
| 1634 | /* The pixel multiplier can only be updated once the |
| 1635 | * DPLL is enabled and the clocks are stable. |
| 1636 | * |
| 1637 | * So write it again. |
| 1638 | */ |
| 1639 | I915_WRITE(reg, dpll); |
| 1640 | } |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1641 | |
| 1642 | /* We do this three times for luck */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1643 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1644 | POSTING_READ(reg); |
| 1645 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1646 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1647 | POSTING_READ(reg); |
| 1648 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1649 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1650 | POSTING_READ(reg); |
| 1651 | udelay(150); /* wait for warmup */ |
| 1652 | } |
| 1653 | |
| 1654 | /** |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1655 | * i9xx_disable_pll - disable a PLL |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1656 | * @dev_priv: i915 private structure |
| 1657 | * @pipe: pipe PLL to disable |
| 1658 | * |
| 1659 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1660 | * |
| 1661 | * Note! This is for pre-ILK only. |
| 1662 | */ |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1663 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1664 | { |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1665 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1666 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1667 | return; |
| 1668 | |
| 1669 | /* Make sure the pipe isn't still relying on us */ |
| 1670 | assert_pipe_disabled(dev_priv, pipe); |
| 1671 | |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1672 | I915_WRITE(DPLL(pipe), 0); |
| 1673 | POSTING_READ(DPLL(pipe)); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1674 | } |
| 1675 | |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1676 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1677 | { |
| 1678 | u32 val = 0; |
| 1679 | |
| 1680 | /* Make sure the pipe isn't still relying on us */ |
| 1681 | assert_pipe_disabled(dev_priv, pipe); |
| 1682 | |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1683 | /* |
| 1684 | * Leave integrated clock source and reference clock enabled for pipe B. |
| 1685 | * The latter is needed for VGA hotplug / manual detection. |
| 1686 | */ |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1687 | if (pipe == PIPE_B) |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1688 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1689 | I915_WRITE(DPLL(pipe), val); |
| 1690 | POSTING_READ(DPLL(pipe)); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1691 | |
| 1692 | } |
| 1693 | |
| 1694 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1695 | { |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1696 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1697 | u32 val; |
| 1698 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1699 | /* Make sure the pipe isn't still relying on us */ |
| 1700 | assert_pipe_disabled(dev_priv, pipe); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1701 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1702 | /* Set PLL en = 0 */ |
Ville Syrjälä | d17ec4c | 2014-06-28 02:03:59 +0300 | [diff] [blame] | 1703 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1704 | if (pipe != PIPE_A) |
| 1705 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 1706 | I915_WRITE(DPLL(pipe), val); |
| 1707 | POSTING_READ(DPLL(pipe)); |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1708 | |
| 1709 | mutex_lock(&dev_priv->dpio_lock); |
| 1710 | |
| 1711 | /* Disable 10bit clock to display controller */ |
| 1712 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1713 | val &= ~DPIO_DCLKP_EN; |
| 1714 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
| 1715 | |
Ville Syrjälä | 61407f6 | 2014-05-27 16:32:55 +0300 | [diff] [blame] | 1716 | /* disable left/right clock distribution */ |
| 1717 | if (pipe != PIPE_B) { |
| 1718 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 1719 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 1720 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 1721 | } else { |
| 1722 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 1723 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 1724 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 1725 | } |
| 1726 | |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1727 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1728 | } |
| 1729 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1730 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 1731 | struct intel_digital_port *dport) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1732 | { |
| 1733 | u32 port_mask; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1734 | int dpll_reg; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1735 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1736 | switch (dport->port) { |
| 1737 | case PORT_B: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1738 | port_mask = DPLL_PORTB_READY_MASK; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1739 | dpll_reg = DPLL(0); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1740 | break; |
| 1741 | case PORT_C: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1742 | port_mask = DPLL_PORTC_READY_MASK; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1743 | dpll_reg = DPLL(0); |
| 1744 | break; |
| 1745 | case PORT_D: |
| 1746 | port_mask = DPLL_PORTD_READY_MASK; |
| 1747 | dpll_reg = DPIO_PHY_STATUS; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1748 | break; |
| 1749 | default: |
| 1750 | BUG(); |
| 1751 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1752 | |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1753 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1754 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1755 | port_name(dport->port), I915_READ(dpll_reg)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1756 | } |
| 1757 | |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 1758 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
| 1759 | { |
| 1760 | struct drm_device *dev = crtc->base.dev; |
| 1761 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1762 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 1763 | |
Chris Wilson | be19f0f | 2014-05-28 16:16:42 +0100 | [diff] [blame] | 1764 | if (WARN_ON(pll == NULL)) |
| 1765 | return; |
| 1766 | |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 1767 | WARN_ON(!pll->refcount); |
| 1768 | if (pll->active == 0) { |
| 1769 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
| 1770 | WARN_ON(pll->on); |
| 1771 | assert_shared_dpll_disabled(dev_priv, pll); |
| 1772 | |
| 1773 | pll->mode_set(dev_priv, pll); |
| 1774 | } |
| 1775 | } |
| 1776 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1777 | /** |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 1778 | * intel_enable_shared_dpll - enable PCH PLL |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1779 | * @dev_priv: i915 private structure |
| 1780 | * @pipe: pipe PLL to enable |
| 1781 | * |
| 1782 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 1783 | * drives the transcoder clock. |
| 1784 | */ |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 1785 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1786 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1787 | struct drm_device *dev = crtc->base.dev; |
| 1788 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1789 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1790 | |
Daniel Vetter | 87a875b | 2013-06-05 13:34:19 +0200 | [diff] [blame] | 1791 | if (WARN_ON(pll == NULL)) |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1792 | return; |
| 1793 | |
| 1794 | if (WARN_ON(pll->refcount == 0)) |
| 1795 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1796 | |
Damien Lespiau | 74dd692 | 2014-07-29 18:06:17 +0100 | [diff] [blame] | 1797 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1798 | pll->name, pll->active, pll->on, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1799 | crtc->base.base.id); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1800 | |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 1801 | if (pll->active++) { |
| 1802 | WARN_ON(!pll->on); |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1803 | assert_shared_dpll_enabled(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1804 | return; |
| 1805 | } |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 1806 | WARN_ON(pll->on); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1807 | |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 1808 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 1809 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1810 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 1811 | pll->enable(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1812 | pll->on = true; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1813 | } |
| 1814 | |
Damien Lespiau | f6daaec | 2014-08-09 23:00:56 +0100 | [diff] [blame] | 1815 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1816 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1817 | struct drm_device *dev = crtc->base.dev; |
| 1818 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1819 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | 4c609cb | 2011-09-02 12:52:11 -0700 | [diff] [blame] | 1820 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1821 | /* PCH only available on ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1822 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
Daniel Vetter | 87a875b | 2013-06-05 13:34:19 +0200 | [diff] [blame] | 1823 | if (WARN_ON(pll == NULL)) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1824 | return; |
| 1825 | |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1826 | if (WARN_ON(pll->refcount == 0)) |
| 1827 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1828 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1829 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
| 1830 | pll->name, pll->active, pll->on, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1831 | crtc->base.base.id); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1832 | |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1833 | if (WARN_ON(pll->active == 0)) { |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1834 | assert_shared_dpll_disabled(dev_priv, pll); |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1835 | return; |
| 1836 | } |
| 1837 | |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1838 | assert_shared_dpll_enabled(dev_priv, pll); |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 1839 | WARN_ON(!pll->on); |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 1840 | if (--pll->active) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1841 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1842 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1843 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 1844 | pll->disable(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1845 | pll->on = false; |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 1846 | |
| 1847 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1848 | } |
| 1849 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1850 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1851 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1852 | { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1853 | struct drm_device *dev = dev_priv->dev; |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1854 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1856 | uint32_t reg, val, pipeconf_val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1857 | |
| 1858 | /* PCH only available on ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1859 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1860 | |
| 1861 | /* Make sure PCH DPLL is enabled */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1862 | assert_shared_dpll_enabled(dev_priv, |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1863 | intel_crtc_to_shared_dpll(intel_crtc)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1864 | |
| 1865 | /* FDI must be feeding us bits for PCH ports */ |
| 1866 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1867 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1868 | |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1869 | if (HAS_PCH_CPT(dev)) { |
| 1870 | /* Workaround: Set the timing override bit before enabling the |
| 1871 | * pch transcoder. */ |
| 1872 | reg = TRANS_CHICKEN2(pipe); |
| 1873 | val = I915_READ(reg); |
| 1874 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1875 | I915_WRITE(reg, val); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 1876 | } |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1877 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1878 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1879 | val = I915_READ(reg); |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1880 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1881 | |
| 1882 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 1883 | /* |
| 1884 | * make the BPC in transcoder be consistent with |
| 1885 | * that in pipeconf reg. |
| 1886 | */ |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 1887 | val &= ~PIPECONF_BPC_MASK; |
| 1888 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1889 | } |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1890 | |
| 1891 | val &= ~TRANS_INTERLACE_MASK; |
| 1892 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1893 | if (HAS_PCH_IBX(dev_priv->dev) && |
| 1894 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
| 1895 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 1896 | else |
| 1897 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1898 | else |
| 1899 | val |= TRANS_PROGRESSIVE; |
| 1900 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1901 | I915_WRITE(reg, val | TRANS_ENABLE); |
| 1902 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 1903 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1904 | } |
| 1905 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1906 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1907 | enum transcoder cpu_transcoder) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1908 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1909 | u32 val, pipeconf_val; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1910 | |
| 1911 | /* PCH only available on ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1912 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1913 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1914 | /* FDI must be feeding us bits for PCH ports */ |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1915 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1916 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1917 | |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1918 | /* Workaround: set timing override bit. */ |
| 1919 | val = I915_READ(_TRANSA_CHICKEN2); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1920 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1921 | I915_WRITE(_TRANSA_CHICKEN2, val); |
| 1922 | |
Paulo Zanoni | 25f3ef1 | 2012-10-31 18:12:49 -0200 | [diff] [blame] | 1923 | val = TRANS_ENABLE; |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1924 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1925 | |
Paulo Zanoni | 9a76b1c | 2012-10-31 18:12:48 -0200 | [diff] [blame] | 1926 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
| 1927 | PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | a35f267 | 2012-10-31 18:12:45 -0200 | [diff] [blame] | 1928 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1929 | else |
| 1930 | val |= TRANS_PROGRESSIVE; |
| 1931 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1932 | I915_WRITE(LPT_TRANSCONF, val); |
| 1933 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1934 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1935 | } |
| 1936 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1937 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1938 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1939 | { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1940 | struct drm_device *dev = dev_priv->dev; |
| 1941 | uint32_t reg, val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1942 | |
| 1943 | /* FDI relies on the transcoder */ |
| 1944 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 1945 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 1946 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1947 | /* Ports must be off as well */ |
| 1948 | assert_pch_ports_disabled(dev_priv, pipe); |
| 1949 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1950 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1951 | val = I915_READ(reg); |
| 1952 | val &= ~TRANS_ENABLE; |
| 1953 | I915_WRITE(reg, val); |
| 1954 | /* wait for PCH transcoder off, transcoder state */ |
| 1955 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 1956 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1957 | |
| 1958 | if (!HAS_PCH_IBX(dev)) { |
| 1959 | /* Workaround: Clear the timing override chicken bit again. */ |
| 1960 | reg = TRANS_CHICKEN2(pipe); |
| 1961 | val = I915_READ(reg); |
| 1962 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1963 | I915_WRITE(reg, val); |
| 1964 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1965 | } |
| 1966 | |
Paulo Zanoni | ab4d966 | 2012-10-31 18:12:55 -0200 | [diff] [blame] | 1967 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1968 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1969 | u32 val; |
| 1970 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1971 | val = I915_READ(LPT_TRANSCONF); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1972 | val &= ~TRANS_ENABLE; |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1973 | I915_WRITE(LPT_TRANSCONF, val); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1974 | /* wait for PCH transcoder off, transcoder state */ |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1975 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
Paulo Zanoni | 8a52fd9 | 2012-10-31 18:12:51 -0200 | [diff] [blame] | 1976 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1977 | |
| 1978 | /* Workaround: clear timing override bit. */ |
| 1979 | val = I915_READ(_TRANSA_CHICKEN2); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1980 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1981 | I915_WRITE(_TRANSA_CHICKEN2, val); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1982 | } |
| 1983 | |
| 1984 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1985 | * intel_enable_pipe - enable a pipe, asserting requirements |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1986 | * @crtc: crtc responsible for the pipe |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1987 | * |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1988 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1989 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1990 | */ |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 1991 | static void intel_enable_pipe(struct intel_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1992 | { |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1993 | struct drm_device *dev = crtc->base.dev; |
| 1994 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1995 | enum pipe pipe = crtc->pipe; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1996 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1997 | pipe); |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1998 | enum pipe pch_transcoder; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1999 | int reg; |
| 2000 | u32 val; |
| 2001 | |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 2002 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 2003 | assert_cursor_disabled(dev_priv, pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 2004 | assert_sprites_disabled(dev_priv, pipe); |
| 2005 | |
Paulo Zanoni | 681e581 | 2012-12-06 11:12:38 -0200 | [diff] [blame] | 2006 | if (HAS_PCH_LPT(dev_priv->dev)) |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 2007 | pch_transcoder = TRANSCODER_A; |
| 2008 | else |
| 2009 | pch_transcoder = pipe; |
| 2010 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2011 | /* |
| 2012 | * A pipe without a PLL won't actually be able to drive bits from |
| 2013 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 2014 | * need the check. |
| 2015 | */ |
| 2016 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
Paulo Zanoni | fbf3218 | 2014-01-17 13:51:11 -0200 | [diff] [blame] | 2017 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 2018 | assert_dsi_pll_enabled(dev_priv); |
| 2019 | else |
| 2020 | assert_pll_enabled(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2021 | else { |
Paulo Zanoni | 30421c4 | 2014-01-17 13:51:10 -0200 | [diff] [blame] | 2022 | if (crtc->config.has_pch_encoder) { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2023 | /* if driving the PCH, we need FDI enabled */ |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 2024 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 2025 | assert_fdi_tx_pll_enabled(dev_priv, |
| 2026 | (enum pipe) cpu_transcoder); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2027 | } |
| 2028 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 2029 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2030 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 2031 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2032 | val = I915_READ(reg); |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 2033 | if (val & PIPECONF_ENABLE) { |
| 2034 | WARN_ON(!(pipe == PIPE_A && |
| 2035 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2036 | return; |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 2037 | } |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2038 | |
| 2039 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Paulo Zanoni | 851855d | 2013-12-19 19:12:29 -0200 | [diff] [blame] | 2040 | POSTING_READ(reg); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2041 | } |
| 2042 | |
| 2043 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 2044 | * intel_disable_pipe - disable a pipe, asserting requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2045 | * @dev_priv: i915 private structure |
| 2046 | * @pipe: pipe to disable |
| 2047 | * |
| 2048 | * Disable @pipe, making sure that various hardware specific requirements |
| 2049 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
| 2050 | * |
| 2051 | * @pipe should be %PIPE_A or %PIPE_B. |
| 2052 | * |
| 2053 | * Will wait until the pipe has shut down before returning. |
| 2054 | */ |
| 2055 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
| 2056 | enum pipe pipe) |
| 2057 | { |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 2058 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 2059 | pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2060 | int reg; |
| 2061 | u32 val; |
| 2062 | |
| 2063 | /* |
| 2064 | * Make sure planes won't keep trying to pump pixels to us, |
| 2065 | * or we might hang the display. |
| 2066 | */ |
| 2067 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 2068 | assert_cursor_disabled(dev_priv, pipe); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 2069 | assert_sprites_disabled(dev_priv, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2070 | |
| 2071 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 2072 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 2073 | return; |
| 2074 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 2075 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2076 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2077 | if ((val & PIPECONF_ENABLE) == 0) |
| 2078 | return; |
| 2079 | |
| 2080 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2081 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
| 2082 | } |
| 2083 | |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 2084 | /* |
| 2085 | * Plane regs are double buffered, going from enabled->disabled needs a |
| 2086 | * trigger in order to latch. The display address reg provides this. |
| 2087 | */ |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 2088 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
| 2089 | enum plane plane) |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 2090 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 2091 | struct drm_device *dev = dev_priv->dev; |
| 2092 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 2093 | |
| 2094 | I915_WRITE(reg, I915_READ(reg)); |
| 2095 | POSTING_READ(reg); |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 2096 | } |
| 2097 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2098 | /** |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2099 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2100 | * @plane: plane to be enabled |
| 2101 | * @crtc: crtc for the plane |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2102 | * |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2103 | * Enable @plane on @crtc, making sure that the pipe is running first. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2104 | */ |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2105 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
| 2106 | struct drm_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2107 | { |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2108 | struct drm_device *dev = plane->dev; |
| 2109 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2111 | |
| 2112 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2113 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2114 | |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 2115 | if (intel_crtc->primary_enabled) |
| 2116 | return; |
Ville Syrjälä | 0037f71 | 2013-10-01 18:02:20 +0300 | [diff] [blame] | 2117 | |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 2118 | intel_crtc->primary_enabled = true; |
Ville Syrjälä | 939c2fe | 2013-10-01 18:02:10 +0300 | [diff] [blame] | 2119 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2120 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
| 2121 | crtc->x, crtc->y); |
Ville Syrjälä | 33c3b0d | 2014-06-24 13:59:28 +0300 | [diff] [blame] | 2122 | |
| 2123 | /* |
| 2124 | * BDW signals flip done immediately if the plane |
| 2125 | * is disabled, even if the plane enable is already |
| 2126 | * armed to occur at the next vblank :( |
| 2127 | */ |
| 2128 | if (IS_BROADWELL(dev)) |
| 2129 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2130 | } |
| 2131 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2132 | /** |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2133 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2134 | * @plane: plane to be disabled |
| 2135 | * @crtc: crtc for the plane |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2136 | * |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2137 | * Disable @plane on @crtc, making sure that the pipe is running first. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2138 | */ |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2139 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
| 2140 | struct drm_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2141 | { |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2142 | struct drm_device *dev = plane->dev; |
| 2143 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2145 | |
| 2146 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2147 | |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 2148 | if (!intel_crtc->primary_enabled) |
| 2149 | return; |
Ville Syrjälä | 0037f71 | 2013-10-01 18:02:20 +0300 | [diff] [blame] | 2150 | |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 2151 | intel_crtc->primary_enabled = false; |
Ville Syrjälä | 939c2fe | 2013-10-01 18:02:10 +0300 | [diff] [blame] | 2152 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2153 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
| 2154 | crtc->x, crtc->y); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2155 | } |
| 2156 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 2157 | static bool need_vtd_wa(struct drm_device *dev) |
| 2158 | { |
| 2159 | #ifdef CONFIG_INTEL_IOMMU |
| 2160 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
| 2161 | return true; |
| 2162 | #endif |
| 2163 | return false; |
| 2164 | } |
| 2165 | |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 2166 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
| 2167 | { |
| 2168 | int tile_height; |
| 2169 | |
| 2170 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; |
| 2171 | return ALIGN(height, tile_height); |
| 2172 | } |
| 2173 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 2174 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2175 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2176 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2177 | struct intel_engine_cs *pipelined) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2178 | { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2180 | u32 alignment; |
| 2181 | int ret; |
| 2182 | |
Matt Roper | ebcdd39 | 2014-07-09 16:22:11 -0700 | [diff] [blame] | 2183 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2184 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2185 | switch (obj->tiling_mode) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2186 | case I915_TILING_NONE: |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 2187 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 2188 | alignment = 128 * 1024; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2189 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 2190 | alignment = 4 * 1024; |
| 2191 | else |
| 2192 | alignment = 64 * 1024; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2193 | break; |
| 2194 | case I915_TILING_X: |
| 2195 | /* pin() will align the object as required by fence */ |
| 2196 | alignment = 0; |
| 2197 | break; |
| 2198 | case I915_TILING_Y: |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 2199 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2200 | return -EINVAL; |
| 2201 | default: |
| 2202 | BUG(); |
| 2203 | } |
| 2204 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 2205 | /* Note that the w/a also requires 64 PTE of padding following the |
| 2206 | * bo. We currently fill all unused PTE with the shadow page and so |
| 2207 | * we should always have valid PTE following the scanout preventing |
| 2208 | * the VT-d warning. |
| 2209 | */ |
| 2210 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
| 2211 | alignment = 256 * 1024; |
| 2212 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2213 | dev_priv->mm.interruptible = false; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2214 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2215 | if (ret) |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2216 | goto err_interruptible; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2217 | |
| 2218 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 2219 | * fence, whereas 965+ only requires a fence if using |
| 2220 | * framebuffer compression. For simplicity, we always install |
| 2221 | * a fence as the cost is not that onerous. |
| 2222 | */ |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2223 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2224 | if (ret) |
| 2225 | goto err_unpin; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2226 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2227 | i915_gem_object_pin_fence(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2228 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2229 | dev_priv->mm.interruptible = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2230 | return 0; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2231 | |
| 2232 | err_unpin: |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2233 | i915_gem_object_unpin_from_display_plane(obj); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2234 | err_interruptible: |
| 2235 | dev_priv->mm.interruptible = true; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2236 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2237 | } |
| 2238 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2239 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
| 2240 | { |
Matt Roper | ebcdd39 | 2014-07-09 16:22:11 -0700 | [diff] [blame] | 2241 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
| 2242 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2243 | i915_gem_object_unpin_fence(obj); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2244 | i915_gem_object_unpin_from_display_plane(obj); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2245 | } |
| 2246 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2247 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
| 2248 | * is assumed to be a power-of-two. */ |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2249 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| 2250 | unsigned int tiling_mode, |
| 2251 | unsigned int cpp, |
| 2252 | unsigned int pitch) |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2253 | { |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2254 | if (tiling_mode != I915_TILING_NONE) { |
| 2255 | unsigned int tile_rows, tiles; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2256 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2257 | tile_rows = *y / 8; |
| 2258 | *y %= 8; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2259 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2260 | tiles = *x / (512/cpp); |
| 2261 | *x %= 512/cpp; |
| 2262 | |
| 2263 | return tile_rows * pitch * 8 + tiles * 4096; |
| 2264 | } else { |
| 2265 | unsigned int offset; |
| 2266 | |
| 2267 | offset = *y * pitch + *x * cpp; |
| 2268 | *y = 0; |
| 2269 | *x = (offset & 4095) / cpp; |
| 2270 | return offset & -4096; |
| 2271 | } |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2272 | } |
| 2273 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2274 | int intel_format_to_fourcc(int format) |
| 2275 | { |
| 2276 | switch (format) { |
| 2277 | case DISPPLANE_8BPP: |
| 2278 | return DRM_FORMAT_C8; |
| 2279 | case DISPPLANE_BGRX555: |
| 2280 | return DRM_FORMAT_XRGB1555; |
| 2281 | case DISPPLANE_BGRX565: |
| 2282 | return DRM_FORMAT_RGB565; |
| 2283 | default: |
| 2284 | case DISPPLANE_BGRX888: |
| 2285 | return DRM_FORMAT_XRGB8888; |
| 2286 | case DISPPLANE_RGBX888: |
| 2287 | return DRM_FORMAT_XBGR8888; |
| 2288 | case DISPPLANE_BGRX101010: |
| 2289 | return DRM_FORMAT_XRGB2101010; |
| 2290 | case DISPPLANE_RGBX101010: |
| 2291 | return DRM_FORMAT_XBGR2101010; |
| 2292 | } |
| 2293 | } |
| 2294 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2295 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2296 | struct intel_plane_config *plane_config) |
| 2297 | { |
| 2298 | struct drm_device *dev = crtc->base.dev; |
| 2299 | struct drm_i915_gem_object *obj = NULL; |
| 2300 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
| 2301 | u32 base = plane_config->base; |
| 2302 | |
Chris Wilson | ff2652e | 2014-03-10 08:07:02 +0000 | [diff] [blame] | 2303 | if (plane_config->size == 0) |
| 2304 | return false; |
| 2305 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2306 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
| 2307 | plane_config->size); |
| 2308 | if (!obj) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2309 | return false; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2310 | |
| 2311 | if (plane_config->tiled) { |
| 2312 | obj->tiling_mode = I915_TILING_X; |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2313 | obj->stride = crtc->base.primary->fb->pitches[0]; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2314 | } |
| 2315 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2316 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
| 2317 | mode_cmd.width = crtc->base.primary->fb->width; |
| 2318 | mode_cmd.height = crtc->base.primary->fb->height; |
| 2319 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2320 | |
| 2321 | mutex_lock(&dev->struct_mutex); |
| 2322 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2323 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2324 | &mode_cmd, obj)) { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2325 | DRM_DEBUG_KMS("intel fb init failed\n"); |
| 2326 | goto out_unref_obj; |
| 2327 | } |
| 2328 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 2329 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2330 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2331 | |
| 2332 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); |
| 2333 | return true; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2334 | |
| 2335 | out_unref_obj: |
| 2336 | drm_gem_object_unreference(&obj->base); |
| 2337 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2338 | return false; |
| 2339 | } |
| 2340 | |
| 2341 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, |
| 2342 | struct intel_plane_config *plane_config) |
| 2343 | { |
| 2344 | struct drm_device *dev = intel_crtc->base.dev; |
| 2345 | struct drm_crtc *c; |
| 2346 | struct intel_crtc *i; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2347 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2348 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2349 | if (!intel_crtc->base.primary->fb) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2350 | return; |
| 2351 | |
| 2352 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) |
| 2353 | return; |
| 2354 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2355 | kfree(intel_crtc->base.primary->fb); |
| 2356 | intel_crtc->base.primary->fb = NULL; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2357 | |
| 2358 | /* |
| 2359 | * Failed to alloc the obj, check to see if we should share |
| 2360 | * an fb with another CRTC instead |
| 2361 | */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 2362 | for_each_crtc(dev, c) { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2363 | i = to_intel_crtc(c); |
| 2364 | |
| 2365 | if (c == &intel_crtc->base) |
| 2366 | continue; |
| 2367 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2368 | if (!i->active) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2369 | continue; |
| 2370 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2371 | obj = intel_fb_obj(c->primary->fb); |
| 2372 | if (obj == NULL) |
| 2373 | continue; |
| 2374 | |
| 2375 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2376 | drm_framebuffer_reference(c->primary->fb); |
| 2377 | intel_crtc->base.primary->fb = c->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2378 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2379 | break; |
| 2380 | } |
| 2381 | } |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2382 | } |
| 2383 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 2384 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
| 2385 | struct drm_framebuffer *fb, |
| 2386 | int x, int y) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2387 | { |
| 2388 | struct drm_device *dev = crtc->dev; |
| 2389 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2390 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame^] | 2391 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2392 | int plane = intel_crtc->plane; |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2393 | unsigned long linear_offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2394 | u32 dspcntr; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2395 | u32 reg = DSPCNTR(plane); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2396 | int pixel_size; |
| 2397 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2398 | if (!intel_crtc->primary_enabled) { |
| 2399 | I915_WRITE(reg, 0); |
| 2400 | if (INTEL_INFO(dev)->gen >= 4) |
| 2401 | I915_WRITE(DSPSURF(plane), 0); |
| 2402 | else |
| 2403 | I915_WRITE(DSPADDR(plane), 0); |
| 2404 | POSTING_READ(reg); |
| 2405 | return; |
| 2406 | } |
| 2407 | |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame^] | 2408 | obj = intel_fb_obj(fb); |
| 2409 | if (WARN_ON(obj == NULL)) |
| 2410 | return; |
| 2411 | |
| 2412 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2413 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2414 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 2415 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2416 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2417 | |
| 2418 | if (INTEL_INFO(dev)->gen < 4) { |
| 2419 | if (intel_crtc->pipe == PIPE_B) |
| 2420 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 2421 | |
| 2422 | /* pipesrc and dspsize control the size that is scaled from, |
| 2423 | * which should always be the user's requested size. |
| 2424 | */ |
| 2425 | I915_WRITE(DSPSIZE(plane), |
| 2426 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
| 2427 | (intel_crtc->config.pipe_src_w - 1)); |
| 2428 | I915_WRITE(DSPPOS(plane), 0); |
| 2429 | } |
| 2430 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2431 | switch (fb->pixel_format) { |
| 2432 | case DRM_FORMAT_C8: |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2433 | dspcntr |= DISPPLANE_8BPP; |
| 2434 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2435 | case DRM_FORMAT_XRGB1555: |
| 2436 | case DRM_FORMAT_ARGB1555: |
| 2437 | dspcntr |= DISPPLANE_BGRX555; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2438 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2439 | case DRM_FORMAT_RGB565: |
| 2440 | dspcntr |= DISPPLANE_BGRX565; |
| 2441 | break; |
| 2442 | case DRM_FORMAT_XRGB8888: |
| 2443 | case DRM_FORMAT_ARGB8888: |
| 2444 | dspcntr |= DISPPLANE_BGRX888; |
| 2445 | break; |
| 2446 | case DRM_FORMAT_XBGR8888: |
| 2447 | case DRM_FORMAT_ABGR8888: |
| 2448 | dspcntr |= DISPPLANE_RGBX888; |
| 2449 | break; |
| 2450 | case DRM_FORMAT_XRGB2101010: |
| 2451 | case DRM_FORMAT_ARGB2101010: |
| 2452 | dspcntr |= DISPPLANE_BGRX101010; |
| 2453 | break; |
| 2454 | case DRM_FORMAT_XBGR2101010: |
| 2455 | case DRM_FORMAT_ABGR2101010: |
| 2456 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2457 | break; |
| 2458 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 2459 | BUG(); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2460 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2461 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2462 | if (INTEL_INFO(dev)->gen >= 4 && |
| 2463 | obj->tiling_mode != I915_TILING_NONE) |
| 2464 | dspcntr |= DISPPLANE_TILED; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2465 | |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 2466 | if (IS_G4X(dev)) |
| 2467 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2468 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2469 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2470 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2471 | if (INTEL_INFO(dev)->gen >= 4) { |
| 2472 | intel_crtc->dspaddr_offset = |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2473 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 2474 | fb->bits_per_pixel / 8, |
| 2475 | fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2476 | linear_offset -= intel_crtc->dspaddr_offset; |
| 2477 | } else { |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2478 | intel_crtc->dspaddr_offset = linear_offset; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2479 | } |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2480 | |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2481 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
| 2482 | dspcntr |= DISPPLANE_ROTATE_180; |
| 2483 | |
| 2484 | x += (intel_crtc->config.pipe_src_w - 1); |
| 2485 | y += (intel_crtc->config.pipe_src_h - 1); |
| 2486 | |
| 2487 | /* Finding the last pixel of the last line of the display |
| 2488 | data and adding to linear_offset*/ |
| 2489 | linear_offset += |
| 2490 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + |
| 2491 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; |
| 2492 | } |
| 2493 | |
| 2494 | I915_WRITE(reg, dspcntr); |
| 2495 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2496 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
| 2497 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
| 2498 | fb->pitches[0]); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2499 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2500 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 2501 | I915_WRITE(DSPSURF(plane), |
| 2502 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2503 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2504 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2505 | } else |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2506 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2507 | POSTING_READ(reg); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2508 | } |
| 2509 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 2510 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
| 2511 | struct drm_framebuffer *fb, |
| 2512 | int x, int y) |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2513 | { |
| 2514 | struct drm_device *dev = crtc->dev; |
| 2515 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2516 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame^] | 2517 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2518 | int plane = intel_crtc->plane; |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2519 | unsigned long linear_offset; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2520 | u32 dspcntr; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2521 | u32 reg = DSPCNTR(plane); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2522 | int pixel_size; |
| 2523 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2524 | if (!intel_crtc->primary_enabled) { |
| 2525 | I915_WRITE(reg, 0); |
| 2526 | I915_WRITE(DSPSURF(plane), 0); |
| 2527 | POSTING_READ(reg); |
| 2528 | return; |
| 2529 | } |
| 2530 | |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame^] | 2531 | obj = intel_fb_obj(fb); |
| 2532 | if (WARN_ON(obj == NULL)) |
| 2533 | return; |
| 2534 | |
| 2535 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2536 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2537 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 2538 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2539 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2540 | |
| 2541 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 2542 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
| 2543 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2544 | switch (fb->pixel_format) { |
| 2545 | case DRM_FORMAT_C8: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2546 | dspcntr |= DISPPLANE_8BPP; |
| 2547 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2548 | case DRM_FORMAT_RGB565: |
| 2549 | dspcntr |= DISPPLANE_BGRX565; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2550 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2551 | case DRM_FORMAT_XRGB8888: |
| 2552 | case DRM_FORMAT_ARGB8888: |
| 2553 | dspcntr |= DISPPLANE_BGRX888; |
| 2554 | break; |
| 2555 | case DRM_FORMAT_XBGR8888: |
| 2556 | case DRM_FORMAT_ABGR8888: |
| 2557 | dspcntr |= DISPPLANE_RGBX888; |
| 2558 | break; |
| 2559 | case DRM_FORMAT_XRGB2101010: |
| 2560 | case DRM_FORMAT_ARGB2101010: |
| 2561 | dspcntr |= DISPPLANE_BGRX101010; |
| 2562 | break; |
| 2563 | case DRM_FORMAT_XBGR2101010: |
| 2564 | case DRM_FORMAT_ABGR2101010: |
| 2565 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2566 | break; |
| 2567 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 2568 | BUG(); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2569 | } |
| 2570 | |
| 2571 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2572 | dspcntr |= DISPPLANE_TILED; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2573 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2574 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
Paulo Zanoni | 1f5d76d | 2013-08-23 19:51:28 -0300 | [diff] [blame] | 2575 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2576 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2577 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2578 | intel_crtc->dspaddr_offset = |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2579 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 2580 | fb->bits_per_pixel / 8, |
| 2581 | fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2582 | linear_offset -= intel_crtc->dspaddr_offset; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2583 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
| 2584 | dspcntr |= DISPPLANE_ROTATE_180; |
| 2585 | |
| 2586 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
| 2587 | x += (intel_crtc->config.pipe_src_w - 1); |
| 2588 | y += (intel_crtc->config.pipe_src_h - 1); |
| 2589 | |
| 2590 | /* Finding the last pixel of the last line of the display |
| 2591 | data and adding to linear_offset*/ |
| 2592 | linear_offset += |
| 2593 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + |
| 2594 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; |
| 2595 | } |
| 2596 | } |
| 2597 | |
| 2598 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2599 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2600 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
| 2601 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
| 2602 | fb->pitches[0]); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2603 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 2604 | I915_WRITE(DSPSURF(plane), |
| 2605 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Paulo Zanoni | b3dc685 | 2013-11-02 21:07:33 -0700 | [diff] [blame] | 2606 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Damien Lespiau | bc1c91e | 2012-10-29 12:14:21 +0000 | [diff] [blame] | 2607 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
| 2608 | } else { |
| 2609 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2610 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
| 2611 | } |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2612 | POSTING_READ(reg); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2613 | } |
| 2614 | |
| 2615 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 2616 | static int |
| 2617 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 2618 | int x, int y, enum mode_set_atomic state) |
| 2619 | { |
| 2620 | struct drm_device *dev = crtc->dev; |
| 2621 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2622 | |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 2623 | if (dev_priv->display.disable_fbc) |
| 2624 | dev_priv->display.disable_fbc(dev); |
Daniel Vetter | cc36513 | 2014-06-18 13:59:13 +0200 | [diff] [blame] | 2625 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2626 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 2627 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
| 2628 | |
| 2629 | return 0; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2630 | } |
| 2631 | |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 2632 | void intel_display_handle_reset(struct drm_device *dev) |
| 2633 | { |
| 2634 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2635 | struct drm_crtc *crtc; |
| 2636 | |
| 2637 | /* |
| 2638 | * Flips in the rings have been nuked by the reset, |
| 2639 | * so complete all pending flips so that user space |
| 2640 | * will get its events and not get stuck. |
| 2641 | * |
| 2642 | * Also update the base address of all primary |
| 2643 | * planes to the the last fb to make sure we're |
| 2644 | * showing the correct fb after a reset. |
| 2645 | * |
| 2646 | * Need to make two loops over the crtcs so that we |
| 2647 | * don't try to grab a crtc mutex before the |
| 2648 | * pending_flip_queue really got woken up. |
| 2649 | */ |
| 2650 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 2651 | for_each_crtc(dev, crtc) { |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 2652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2653 | enum plane plane = intel_crtc->plane; |
| 2654 | |
| 2655 | intel_prepare_page_flip(dev, plane); |
| 2656 | intel_finish_page_flip_plane(dev, plane); |
| 2657 | } |
| 2658 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 2659 | for_each_crtc(dev, crtc) { |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 2660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2661 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 2662 | drm_modeset_lock(&crtc->mutex, NULL); |
Chris Wilson | 947fdaadf | 2013-11-27 12:01:32 +0000 | [diff] [blame] | 2663 | /* |
| 2664 | * FIXME: Once we have proper support for primary planes (and |
| 2665 | * disabling them without disabling the entire crtc) allow again |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2666 | * a NULL crtc->primary->fb. |
Chris Wilson | 947fdaadf | 2013-11-27 12:01:32 +0000 | [diff] [blame] | 2667 | */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 2668 | if (intel_crtc->active && crtc->primary->fb) |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2669 | dev_priv->display.update_primary_plane(crtc, |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 2670 | crtc->primary->fb, |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2671 | crtc->x, |
| 2672 | crtc->y); |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 2673 | drm_modeset_unlock(&crtc->mutex); |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 2674 | } |
| 2675 | } |
| 2676 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2677 | static int |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2678 | intel_finish_fb(struct drm_framebuffer *old_fb) |
| 2679 | { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2680 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2681 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2682 | bool was_interruptible = dev_priv->mm.interruptible; |
| 2683 | int ret; |
| 2684 | |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2685 | /* Big Hammer, we also need to ensure that any pending |
| 2686 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 2687 | * current scanout is retired before unpinning the old |
| 2688 | * framebuffer. |
| 2689 | * |
| 2690 | * This should only fail upon a hung GPU, in which case we |
| 2691 | * can safely continue. |
| 2692 | */ |
| 2693 | dev_priv->mm.interruptible = false; |
| 2694 | ret = i915_gem_object_finish_gpu(obj); |
| 2695 | dev_priv->mm.interruptible = was_interruptible; |
| 2696 | |
| 2697 | return ret; |
| 2698 | } |
| 2699 | |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 2700 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
| 2701 | { |
| 2702 | struct drm_device *dev = crtc->dev; |
| 2703 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2705 | unsigned long flags; |
| 2706 | bool pending; |
| 2707 | |
| 2708 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
| 2709 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 2710 | return false; |
| 2711 | |
| 2712 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2713 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
| 2714 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2715 | |
| 2716 | return pending; |
| 2717 | } |
| 2718 | |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2719 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2720 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2721 | struct drm_framebuffer *fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2722 | { |
| 2723 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 2724 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 2726 | enum pipe pipe = intel_crtc->pipe; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2727 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
| 2728 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 2729 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2730 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2731 | |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 2732 | if (intel_crtc_has_pending_flip(crtc)) { |
| 2733 | DRM_ERROR("pipe is still busy with an old pageflip\n"); |
| 2734 | return -EBUSY; |
| 2735 | } |
| 2736 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2737 | /* no fb bound */ |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2738 | if (!fb) { |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2739 | DRM_ERROR("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2740 | return 0; |
| 2741 | } |
| 2742 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 2743 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2744 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
| 2745 | plane_name(intel_crtc->plane), |
| 2746 | INTEL_INFO(dev)->num_pipes); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2747 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2748 | } |
| 2749 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2750 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 2751 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
| 2752 | if (ret == 0) |
Matt Roper | 91565c85 | 2014-06-24 17:05:02 -0700 | [diff] [blame] | 2753 | i915_gem_track_fb(old_obj, obj, |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 2754 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2755 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2756 | if (ret != 0) { |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2757 | DRM_ERROR("pin & fence failed\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2758 | return ret; |
| 2759 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2760 | |
Damien Lespiau | bb2043d | 2013-09-30 14:21:49 +0100 | [diff] [blame] | 2761 | /* |
| 2762 | * Update pipe size and adjust fitter if needed: the reason for this is |
| 2763 | * that in compute_mode_changes we check the native mode (not the pfit |
| 2764 | * mode) to see if we can flip rather than do a full mode set. In the |
| 2765 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
| 2766 | * pfit state, we'll end up with a big fb scanned out into the wrong |
| 2767 | * sized surface. |
| 2768 | * |
| 2769 | * To fix this properly, we need to hoist the checks up into |
| 2770 | * compute_mode_changes (or above), check the actual pfit state and |
| 2771 | * whether the platform allows pfit disable with pipe active, and only |
| 2772 | * then update the pipesrc and pfit state, even on the flip path. |
| 2773 | */ |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2774 | if (i915.fastboot) { |
Damien Lespiau | d7bf63f | 2013-09-30 14:21:50 +0100 | [diff] [blame] | 2775 | const struct drm_display_mode *adjusted_mode = |
| 2776 | &intel_crtc->config.adjusted_mode; |
| 2777 | |
Jesse Barnes | 4d6a3e6 | 2013-06-26 01:38:18 +0300 | [diff] [blame] | 2778 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
Damien Lespiau | d7bf63f | 2013-09-30 14:21:50 +0100 | [diff] [blame] | 2779 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
| 2780 | (adjusted_mode->crtc_vdisplay - 1)); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 2781 | if (!intel_crtc->config.pch_pfit.enabled && |
Jesse Barnes | 4d6a3e6 | 2013-06-26 01:38:18 +0300 | [diff] [blame] | 2782 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
| 2783 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
| 2784 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
| 2785 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
| 2786 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
| 2787 | } |
Jesse Barnes | 0637d60 | 2013-12-19 10:48:01 -0800 | [diff] [blame] | 2788 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
| 2789 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
Jesse Barnes | 4d6a3e6 | 2013-06-26 01:38:18 +0300 | [diff] [blame] | 2790 | } |
| 2791 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 2792 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2793 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 2794 | if (intel_crtc->active) |
| 2795 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
| 2796 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 2797 | crtc->primary->fb = fb; |
Daniel Vetter | 6c4c86f | 2012-09-10 21:58:30 +0200 | [diff] [blame] | 2798 | crtc->x = x; |
| 2799 | crtc->y = y; |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2800 | |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 2801 | if (old_fb) { |
Daniel Vetter | d7697ee | 2013-06-02 17:23:01 +0200 | [diff] [blame] | 2802 | if (intel_crtc->active && old_fb != fb) |
| 2803 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2804 | mutex_lock(&dev->struct_mutex); |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2805 | intel_unpin_fb_obj(old_obj); |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2806 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 2807 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2808 | |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2809 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 2810 | intel_update_fbc(dev); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2811 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2812 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2813 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2814 | } |
| 2815 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2816 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 2817 | { |
| 2818 | struct drm_device *dev = crtc->dev; |
| 2819 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2821 | int pipe = intel_crtc->pipe; |
| 2822 | u32 reg, temp; |
| 2823 | |
| 2824 | /* enable normal train */ |
| 2825 | reg = FDI_TX_CTL(pipe); |
| 2826 | temp = I915_READ(reg); |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2827 | if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2828 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2829 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2830 | } else { |
| 2831 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2832 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2833 | } |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2834 | I915_WRITE(reg, temp); |
| 2835 | |
| 2836 | reg = FDI_RX_CTL(pipe); |
| 2837 | temp = I915_READ(reg); |
| 2838 | if (HAS_PCH_CPT(dev)) { |
| 2839 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2840 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 2841 | } else { |
| 2842 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2843 | temp |= FDI_LINK_TRAIN_NONE; |
| 2844 | } |
| 2845 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 2846 | |
| 2847 | /* wait one idle pattern time */ |
| 2848 | POSTING_READ(reg); |
| 2849 | udelay(1000); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2850 | |
| 2851 | /* IVB wants error correction enabled */ |
| 2852 | if (IS_IVYBRIDGE(dev)) |
| 2853 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 2854 | FDI_FE_ERRC_ENABLE); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2855 | } |
| 2856 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 2857 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 2858 | { |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 2859 | return crtc->base.enabled && crtc->active && |
| 2860 | crtc->config.has_pch_encoder; |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 2861 | } |
| 2862 | |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 2863 | static void ivb_modeset_global_resources(struct drm_device *dev) |
| 2864 | { |
| 2865 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2866 | struct intel_crtc *pipe_B_crtc = |
| 2867 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
| 2868 | struct intel_crtc *pipe_C_crtc = |
| 2869 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
| 2870 | uint32_t temp; |
| 2871 | |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 2872 | /* |
| 2873 | * When everything is off disable fdi C so that we could enable fdi B |
| 2874 | * with all lanes. Note that we don't care about enabled pipes without |
| 2875 | * an enabled pch encoder. |
| 2876 | */ |
| 2877 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
| 2878 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 2879 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 2880 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 2881 | |
| 2882 | temp = I915_READ(SOUTH_CHICKEN1); |
| 2883 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
| 2884 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
| 2885 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 2886 | } |
| 2887 | } |
| 2888 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2889 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 2890 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 2891 | { |
| 2892 | struct drm_device *dev = crtc->dev; |
| 2893 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2895 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2896 | u32 reg, temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2897 | |
Ville Syrjälä | 1c8562f | 2014-04-25 22:12:07 +0300 | [diff] [blame] | 2898 | /* FDI needs bits from pipe first */ |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2899 | assert_pipe_enabled(dev_priv, pipe); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2900 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2901 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2902 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2903 | reg = FDI_RX_IMR(pipe); |
| 2904 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2905 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2906 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2907 | I915_WRITE(reg, temp); |
| 2908 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2909 | udelay(150); |
| 2910 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2911 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2912 | reg = FDI_TX_CTL(pipe); |
| 2913 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 2914 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 2915 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2916 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2917 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2918 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2919 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2920 | reg = FDI_RX_CTL(pipe); |
| 2921 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2922 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2923 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2924 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2925 | |
| 2926 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2927 | udelay(150); |
| 2928 | |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2929 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
Daniel Vetter | 8f5718a | 2012-10-31 22:52:28 +0100 | [diff] [blame] | 2930 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 2931 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 2932 | FDI_RX_PHASE_SYNC_POINTER_EN); |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2933 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2934 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2935 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2936 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2937 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2938 | |
| 2939 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 2940 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2941 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2942 | break; |
| 2943 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2944 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2945 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2946 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2947 | |
| 2948 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2949 | reg = FDI_TX_CTL(pipe); |
| 2950 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2951 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2952 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2953 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2954 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2955 | reg = FDI_RX_CTL(pipe); |
| 2956 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2957 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2958 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2959 | I915_WRITE(reg, temp); |
| 2960 | |
| 2961 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2962 | udelay(150); |
| 2963 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2964 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2965 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2966 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2967 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2968 | |
| 2969 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2970 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2971 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2972 | break; |
| 2973 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2974 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2975 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2976 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2977 | |
| 2978 | DRM_DEBUG_KMS("FDI train done\n"); |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 2979 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2980 | } |
| 2981 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2982 | static const int snb_b_fdi_train_param[] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2983 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 2984 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 2985 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 2986 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 2987 | }; |
| 2988 | |
| 2989 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 2990 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 2991 | { |
| 2992 | struct drm_device *dev = crtc->dev; |
| 2993 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2995 | int pipe = intel_crtc->pipe; |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2996 | u32 reg, temp, i, retry; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2997 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2998 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2999 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3000 | reg = FDI_RX_IMR(pipe); |
| 3001 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3002 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3003 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3004 | I915_WRITE(reg, temp); |
| 3005 | |
| 3006 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3007 | udelay(150); |
| 3008 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3009 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3010 | reg = FDI_TX_CTL(pipe); |
| 3011 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3012 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 3013 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3014 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3015 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3016 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3017 | /* SNB-B */ |
| 3018 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3019 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3020 | |
Daniel Vetter | d74cf32 | 2012-10-26 10:58:13 +0200 | [diff] [blame] | 3021 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3022 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3023 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3024 | reg = FDI_RX_CTL(pipe); |
| 3025 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3026 | if (HAS_PCH_CPT(dev)) { |
| 3027 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3028 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3029 | } else { |
| 3030 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3031 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3032 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3033 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3034 | |
| 3035 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3036 | udelay(150); |
| 3037 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3038 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3039 | reg = FDI_TX_CTL(pipe); |
| 3040 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3041 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3042 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3043 | I915_WRITE(reg, temp); |
| 3044 | |
| 3045 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3046 | udelay(500); |
| 3047 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3048 | for (retry = 0; retry < 5; retry++) { |
| 3049 | reg = FDI_RX_IIR(pipe); |
| 3050 | temp = I915_READ(reg); |
| 3051 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3052 | if (temp & FDI_RX_BIT_LOCK) { |
| 3053 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3054 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 3055 | break; |
| 3056 | } |
| 3057 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3058 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3059 | if (retry < 5) |
| 3060 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3061 | } |
| 3062 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3063 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3064 | |
| 3065 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3066 | reg = FDI_TX_CTL(pipe); |
| 3067 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3068 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3069 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3070 | if (IS_GEN6(dev)) { |
| 3071 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3072 | /* SNB-B */ |
| 3073 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 3074 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3075 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3076 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3077 | reg = FDI_RX_CTL(pipe); |
| 3078 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3079 | if (HAS_PCH_CPT(dev)) { |
| 3080 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3081 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 3082 | } else { |
| 3083 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3084 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3085 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3086 | I915_WRITE(reg, temp); |
| 3087 | |
| 3088 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3089 | udelay(150); |
| 3090 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3091 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3092 | reg = FDI_TX_CTL(pipe); |
| 3093 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3094 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3095 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3096 | I915_WRITE(reg, temp); |
| 3097 | |
| 3098 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3099 | udelay(500); |
| 3100 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3101 | for (retry = 0; retry < 5; retry++) { |
| 3102 | reg = FDI_RX_IIR(pipe); |
| 3103 | temp = I915_READ(reg); |
| 3104 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3105 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 3106 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3107 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3108 | break; |
| 3109 | } |
| 3110 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3111 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3112 | if (retry < 5) |
| 3113 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3114 | } |
| 3115 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3116 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3117 | |
| 3118 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3119 | } |
| 3120 | |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3121 | /* Manual link training for Ivy Bridge A0 parts */ |
| 3122 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 3123 | { |
| 3124 | struct drm_device *dev = crtc->dev; |
| 3125 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3127 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3128 | u32 reg, temp, i, j; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3129 | |
| 3130 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3131 | for train result */ |
| 3132 | reg = FDI_RX_IMR(pipe); |
| 3133 | temp = I915_READ(reg); |
| 3134 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3135 | temp &= ~FDI_RX_BIT_LOCK; |
| 3136 | I915_WRITE(reg, temp); |
| 3137 | |
| 3138 | POSTING_READ(reg); |
| 3139 | udelay(150); |
| 3140 | |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 3141 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
| 3142 | I915_READ(FDI_RX_IIR(pipe))); |
| 3143 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3144 | /* Try each vswing and preemphasis setting twice before moving on */ |
| 3145 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
| 3146 | /* disable first in case we need to retry */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3147 | reg = FDI_TX_CTL(pipe); |
| 3148 | temp = I915_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3149 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 3150 | temp &= ~FDI_TX_ENABLE; |
| 3151 | I915_WRITE(reg, temp); |
| 3152 | |
| 3153 | reg = FDI_RX_CTL(pipe); |
| 3154 | temp = I915_READ(reg); |
| 3155 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 3156 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3157 | temp &= ~FDI_RX_ENABLE; |
| 3158 | I915_WRITE(reg, temp); |
| 3159 | |
| 3160 | /* enable CPU FDI TX and PCH FDI RX */ |
| 3161 | reg = FDI_TX_CTL(pipe); |
| 3162 | temp = I915_READ(reg); |
| 3163 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 3164 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
| 3165 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3166 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3167 | temp |= snb_b_fdi_train_param[j/2]; |
| 3168 | temp |= FDI_COMPOSITE_SYNC; |
| 3169 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 3170 | |
| 3171 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3172 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3173 | |
| 3174 | reg = FDI_RX_CTL(pipe); |
| 3175 | temp = I915_READ(reg); |
| 3176 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3177 | temp |= FDI_COMPOSITE_SYNC; |
| 3178 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3179 | |
| 3180 | POSTING_READ(reg); |
| 3181 | udelay(1); /* should be 0.5us */ |
| 3182 | |
| 3183 | for (i = 0; i < 4; i++) { |
| 3184 | reg = FDI_RX_IIR(pipe); |
| 3185 | temp = I915_READ(reg); |
| 3186 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3187 | |
| 3188 | if (temp & FDI_RX_BIT_LOCK || |
| 3189 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 3190 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3191 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
| 3192 | i); |
| 3193 | break; |
| 3194 | } |
| 3195 | udelay(1); /* should be 0.5us */ |
| 3196 | } |
| 3197 | if (i == 4) { |
| 3198 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
| 3199 | continue; |
| 3200 | } |
| 3201 | |
| 3202 | /* Train 2 */ |
| 3203 | reg = FDI_TX_CTL(pipe); |
| 3204 | temp = I915_READ(reg); |
| 3205 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 3206 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 3207 | I915_WRITE(reg, temp); |
| 3208 | |
| 3209 | reg = FDI_RX_CTL(pipe); |
| 3210 | temp = I915_READ(reg); |
| 3211 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3212 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3213 | I915_WRITE(reg, temp); |
| 3214 | |
| 3215 | POSTING_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3216 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3217 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3218 | for (i = 0; i < 4; i++) { |
| 3219 | reg = FDI_RX_IIR(pipe); |
| 3220 | temp = I915_READ(reg); |
| 3221 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3222 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3223 | if (temp & FDI_RX_SYMBOL_LOCK || |
| 3224 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
| 3225 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3226 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
| 3227 | i); |
| 3228 | goto train_done; |
| 3229 | } |
| 3230 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3231 | } |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3232 | if (i == 4) |
| 3233 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3234 | } |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3235 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3236 | train_done: |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3237 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3238 | } |
| 3239 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3240 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3241 | { |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3242 | struct drm_device *dev = intel_crtc->base.dev; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3243 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3244 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3245 | u32 reg, temp; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3246 | |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 3247 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3248 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3249 | reg = FDI_RX_CTL(pipe); |
| 3250 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3251 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
| 3252 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3253 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3254 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 3255 | |
| 3256 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3257 | udelay(200); |
| 3258 | |
| 3259 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3260 | temp = I915_READ(reg); |
| 3261 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 3262 | |
| 3263 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3264 | udelay(200); |
| 3265 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 3266 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
| 3267 | reg = FDI_TX_CTL(pipe); |
| 3268 | temp = I915_READ(reg); |
| 3269 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 3270 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3271 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 3272 | POSTING_READ(reg); |
| 3273 | udelay(100); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3274 | } |
| 3275 | } |
| 3276 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3277 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
| 3278 | { |
| 3279 | struct drm_device *dev = intel_crtc->base.dev; |
| 3280 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3281 | int pipe = intel_crtc->pipe; |
| 3282 | u32 reg, temp; |
| 3283 | |
| 3284 | /* Switch from PCDclk to Rawclk */ |
| 3285 | reg = FDI_RX_CTL(pipe); |
| 3286 | temp = I915_READ(reg); |
| 3287 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
| 3288 | |
| 3289 | /* Disable CPU FDI TX PLL */ |
| 3290 | reg = FDI_TX_CTL(pipe); |
| 3291 | temp = I915_READ(reg); |
| 3292 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 3293 | |
| 3294 | POSTING_READ(reg); |
| 3295 | udelay(100); |
| 3296 | |
| 3297 | reg = FDI_RX_CTL(pipe); |
| 3298 | temp = I915_READ(reg); |
| 3299 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
| 3300 | |
| 3301 | /* Wait for the clocks to turn off. */ |
| 3302 | POSTING_READ(reg); |
| 3303 | udelay(100); |
| 3304 | } |
| 3305 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3306 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 3307 | { |
| 3308 | struct drm_device *dev = crtc->dev; |
| 3309 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3311 | int pipe = intel_crtc->pipe; |
| 3312 | u32 reg, temp; |
| 3313 | |
| 3314 | /* disable CPU FDI tx and PCH FDI rx */ |
| 3315 | reg = FDI_TX_CTL(pipe); |
| 3316 | temp = I915_READ(reg); |
| 3317 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 3318 | POSTING_READ(reg); |
| 3319 | |
| 3320 | reg = FDI_RX_CTL(pipe); |
| 3321 | temp = I915_READ(reg); |
| 3322 | temp &= ~(0x7 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3323 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3324 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 3325 | |
| 3326 | POSTING_READ(reg); |
| 3327 | udelay(100); |
| 3328 | |
| 3329 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 3330 | if (HAS_PCH_IBX(dev)) |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 3331 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3332 | |
| 3333 | /* still set train pattern 1 */ |
| 3334 | reg = FDI_TX_CTL(pipe); |
| 3335 | temp = I915_READ(reg); |
| 3336 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3337 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3338 | I915_WRITE(reg, temp); |
| 3339 | |
| 3340 | reg = FDI_RX_CTL(pipe); |
| 3341 | temp = I915_READ(reg); |
| 3342 | if (HAS_PCH_CPT(dev)) { |
| 3343 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3344 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3345 | } else { |
| 3346 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3347 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3348 | } |
| 3349 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 3350 | temp &= ~(0x07 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3351 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3352 | I915_WRITE(reg, temp); |
| 3353 | |
| 3354 | POSTING_READ(reg); |
| 3355 | udelay(100); |
| 3356 | } |
| 3357 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3358 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
| 3359 | { |
| 3360 | struct intel_crtc *crtc; |
| 3361 | |
| 3362 | /* Note that we don't need to be called with mode_config.lock here |
| 3363 | * as our list of CRTC objects is static for the lifetime of the |
| 3364 | * device and so cannot disappear as we iterate. Similarly, we can |
| 3365 | * happily treat the predicates as racy, atomic checks as userspace |
| 3366 | * cannot claim and pin a new fb without at least acquring the |
| 3367 | * struct_mutex and so serialising with us. |
| 3368 | */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 3369 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3370 | if (atomic_read(&crtc->unpin_work_count) == 0) |
| 3371 | continue; |
| 3372 | |
| 3373 | if (crtc->unpin_work) |
| 3374 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3375 | |
| 3376 | return true; |
| 3377 | } |
| 3378 | |
| 3379 | return false; |
| 3380 | } |
| 3381 | |
Ville Syrjälä | 46a55d3 | 2014-05-21 14:04:46 +0300 | [diff] [blame] | 3382 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3383 | { |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 3384 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 3385 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3386 | |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 3387 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
Daniel Vetter | eed6d67 | 2014-05-19 16:09:35 +0200 | [diff] [blame] | 3388 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
| 3389 | !intel_crtc_has_pending_flip(crtc), |
| 3390 | 60*HZ) == 0); |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 3391 | |
Chris Wilson | 975d568 | 2014-08-20 13:13:34 +0100 | [diff] [blame] | 3392 | if (crtc->primary->fb) { |
| 3393 | mutex_lock(&dev->struct_mutex); |
| 3394 | intel_finish_fb(crtc->primary->fb); |
| 3395 | mutex_unlock(&dev->struct_mutex); |
| 3396 | } |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3397 | } |
| 3398 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3399 | /* Program iCLKIP clock to the desired frequency */ |
| 3400 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
| 3401 | { |
| 3402 | struct drm_device *dev = crtc->dev; |
| 3403 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 3404 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3405 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
| 3406 | u32 temp; |
| 3407 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 3408 | mutex_lock(&dev_priv->dpio_lock); |
| 3409 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3410 | /* It is necessary to ungate the pixclk gate prior to programming |
| 3411 | * the divisors, and gate it back when it is done. |
| 3412 | */ |
| 3413 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
| 3414 | |
| 3415 | /* Disable SSCCTL */ |
| 3416 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3417 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
| 3418 | SBI_SSCCTL_DISABLE, |
| 3419 | SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3420 | |
| 3421 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3422 | if (clock == 20000) { |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3423 | auxdiv = 1; |
| 3424 | divsel = 0x41; |
| 3425 | phaseinc = 0x20; |
| 3426 | } else { |
| 3427 | /* The iCLK virtual clock root frequency is in MHz, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 3428 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
| 3429 | * divisors, it is necessary to divide one by another, so we |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3430 | * convert the virtual clock precision to KHz here for higher |
| 3431 | * precision. |
| 3432 | */ |
| 3433 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 3434 | u32 iclk_pi_range = 64; |
| 3435 | u32 desired_divisor, msb_divisor_value, pi_value; |
| 3436 | |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3437 | desired_divisor = (iclk_virtual_root_freq / clock); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3438 | msb_divisor_value = desired_divisor / iclk_pi_range; |
| 3439 | pi_value = desired_divisor % iclk_pi_range; |
| 3440 | |
| 3441 | auxdiv = 0; |
| 3442 | divsel = msb_divisor_value - 2; |
| 3443 | phaseinc = pi_value; |
| 3444 | } |
| 3445 | |
| 3446 | /* This should not happen with any sane values */ |
| 3447 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
| 3448 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
| 3449 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
| 3450 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
| 3451 | |
| 3452 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3453 | clock, |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3454 | auxdiv, |
| 3455 | divsel, |
| 3456 | phasedir, |
| 3457 | phaseinc); |
| 3458 | |
| 3459 | /* Program SSCDIVINTPHASE6 */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3460 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3461 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
| 3462 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
| 3463 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
| 3464 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
| 3465 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
| 3466 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3467 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3468 | |
| 3469 | /* Program SSCAUXDIV */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3470 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3471 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
| 3472 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3473 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3474 | |
| 3475 | /* Enable modulator and associated divider */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3476 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3477 | temp &= ~SBI_SSCCTL_DISABLE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3478 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3479 | |
| 3480 | /* Wait for initialization time */ |
| 3481 | udelay(24); |
| 3482 | |
| 3483 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 3484 | |
| 3485 | mutex_unlock(&dev_priv->dpio_lock); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3486 | } |
| 3487 | |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3488 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
| 3489 | enum pipe pch_transcoder) |
| 3490 | { |
| 3491 | struct drm_device *dev = crtc->base.dev; |
| 3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3493 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
| 3494 | |
| 3495 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
| 3496 | I915_READ(HTOTAL(cpu_transcoder))); |
| 3497 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
| 3498 | I915_READ(HBLANK(cpu_transcoder))); |
| 3499 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
| 3500 | I915_READ(HSYNC(cpu_transcoder))); |
| 3501 | |
| 3502 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
| 3503 | I915_READ(VTOTAL(cpu_transcoder))); |
| 3504 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
| 3505 | I915_READ(VBLANK(cpu_transcoder))); |
| 3506 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
| 3507 | I915_READ(VSYNC(cpu_transcoder))); |
| 3508 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
| 3509 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
| 3510 | } |
| 3511 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 3512 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
| 3513 | { |
| 3514 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3515 | uint32_t temp; |
| 3516 | |
| 3517 | temp = I915_READ(SOUTH_CHICKEN1); |
| 3518 | if (temp & FDI_BC_BIFURCATION_SELECT) |
| 3519 | return; |
| 3520 | |
| 3521 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 3522 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 3523 | |
| 3524 | temp |= FDI_BC_BIFURCATION_SELECT; |
| 3525 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
| 3526 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 3527 | POSTING_READ(SOUTH_CHICKEN1); |
| 3528 | } |
| 3529 | |
| 3530 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
| 3531 | { |
| 3532 | struct drm_device *dev = intel_crtc->base.dev; |
| 3533 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3534 | |
| 3535 | switch (intel_crtc->pipe) { |
| 3536 | case PIPE_A: |
| 3537 | break; |
| 3538 | case PIPE_B: |
| 3539 | if (intel_crtc->config.fdi_lanes > 2) |
| 3540 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
| 3541 | else |
| 3542 | cpt_enable_fdi_bc_bifurcation(dev); |
| 3543 | |
| 3544 | break; |
| 3545 | case PIPE_C: |
| 3546 | cpt_enable_fdi_bc_bifurcation(dev); |
| 3547 | |
| 3548 | break; |
| 3549 | default: |
| 3550 | BUG(); |
| 3551 | } |
| 3552 | } |
| 3553 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3554 | /* |
| 3555 | * Enable PCH resources required for PCH ports: |
| 3556 | * - PCH PLLs |
| 3557 | * - FDI training & RX/TX |
| 3558 | * - update transcoder timings |
| 3559 | * - DP transcoding bits |
| 3560 | * - transcoder |
| 3561 | */ |
| 3562 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3563 | { |
| 3564 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3565 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3567 | int pipe = intel_crtc->pipe; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3568 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3569 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 3570 | assert_pch_transcoder_disabled(dev_priv, pipe); |
Chris Wilson | e7e164d | 2012-05-11 09:21:25 +0100 | [diff] [blame] | 3571 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 3572 | if (IS_IVYBRIDGE(dev)) |
| 3573 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
| 3574 | |
Daniel Vetter | cd986ab | 2012-10-26 10:58:12 +0200 | [diff] [blame] | 3575 | /* Write the TU size bits before fdi link training, so that error |
| 3576 | * detection works. */ |
| 3577 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 3578 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
| 3579 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3580 | /* For PCH output, training FDI link */ |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 3581 | dev_priv->display.fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3582 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 3583 | /* We need to program the right clock selection before writing the pixel |
| 3584 | * mutliplier into the DPLL. */ |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 3585 | if (HAS_PCH_CPT(dev)) { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3586 | u32 sel; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 3587 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3588 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 3589 | temp |= TRANS_DPLL_ENABLE(pipe); |
| 3590 | sel = TRANS_DPLLB_SEL(pipe); |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 3591 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3592 | temp |= sel; |
| 3593 | else |
| 3594 | temp &= ~sel; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3595 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3596 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3597 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 3598 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
| 3599 | * transcoder, and we actually should do this to not upset any PCH |
| 3600 | * transcoder that already use the clock when we share it. |
| 3601 | * |
| 3602 | * Note that enable_shared_dpll tries to do the right thing, but |
| 3603 | * get_shared_dpll unconditionally resets the pll - we need that to have |
| 3604 | * the right LVDS enable sequence. */ |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 3605 | intel_enable_shared_dpll(intel_crtc); |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 3606 | |
Jesse Barnes | d9b6cb5 | 2011-01-04 15:09:35 -0800 | [diff] [blame] | 3607 | /* set transcoder timing, panel must allow it */ |
| 3608 | assert_panel_unlocked(dev_priv, pipe); |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3609 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3610 | |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 3611 | intel_fdi_normal_train(crtc); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3612 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3613 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 3614 | if (HAS_PCH_CPT(dev) && |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 3615 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 3616 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3617 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3618 | reg = TRANS_DP_CTL(pipe); |
| 3619 | temp = I915_READ(reg); |
| 3620 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
Eric Anholt | 220cad3 | 2010-11-18 09:32:58 +0800 | [diff] [blame] | 3621 | TRANS_DP_SYNC_MASK | |
| 3622 | TRANS_DP_BPC_MASK); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3623 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
| 3624 | TRANS_DP_ENH_FRAMING); |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 3625 | temp |= bpc << 9; /* same format but at 11:9 */ |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3626 | |
| 3627 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3628 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3629 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3630 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3631 | |
| 3632 | switch (intel_trans_dp_port_sel(crtc)) { |
| 3633 | case PCH_DP_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3634 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3635 | break; |
| 3636 | case PCH_DP_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3637 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3638 | break; |
| 3639 | case PCH_DP_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3640 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3641 | break; |
| 3642 | default: |
Daniel Vetter | e95d41e | 2012-10-26 10:58:16 +0200 | [diff] [blame] | 3643 | BUG(); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3644 | } |
| 3645 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3646 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3647 | } |
| 3648 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 3649 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3650 | } |
| 3651 | |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3652 | static void lpt_pch_enable(struct drm_crtc *crtc) |
| 3653 | { |
| 3654 | struct drm_device *dev = crtc->dev; |
| 3655 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 3657 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3658 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 3659 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3660 | |
Paulo Zanoni | 8c52b5e | 2012-10-31 18:12:24 -0200 | [diff] [blame] | 3661 | lpt_program_iclkip(crtc); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3662 | |
Paulo Zanoni | 0540e48 | 2012-10-31 18:12:40 -0200 | [diff] [blame] | 3663 | /* Set transcoder timing. */ |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3664 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3665 | |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 3666 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3667 | } |
| 3668 | |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 3669 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3670 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3671 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3672 | |
| 3673 | if (pll == NULL) |
| 3674 | return; |
| 3675 | |
| 3676 | if (pll->refcount == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3677 | WARN(1, "bad %s refcount\n", pll->name); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3678 | return; |
| 3679 | } |
| 3680 | |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 3681 | if (--pll->refcount == 0) { |
| 3682 | WARN_ON(pll->on); |
| 3683 | WARN_ON(pll->active); |
| 3684 | } |
| 3685 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 3686 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3687 | } |
| 3688 | |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 3689 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3690 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3691 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 3692 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 3693 | enum intel_dpll_id i; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3694 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3695 | if (pll) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3696 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
| 3697 | crtc->base.base.id, pll->name); |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3698 | intel_put_shared_dpll(crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3699 | } |
| 3700 | |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3701 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 3702 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
Daniel Vetter | d94ab06 | 2013-07-04 12:01:16 +0200 | [diff] [blame] | 3703 | i = (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3704 | pll = &dev_priv->shared_dplls[i]; |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3705 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3706 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 3707 | crtc->base.base.id, pll->name); |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3708 | |
Daniel Vetter | f2a69f4 | 2014-05-20 15:19:19 +0200 | [diff] [blame] | 3709 | WARN_ON(pll->refcount); |
| 3710 | |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3711 | goto found; |
| 3712 | } |
| 3713 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3714 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 3715 | pll = &dev_priv->shared_dplls[i]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3716 | |
| 3717 | /* Only want to check enabled timings first */ |
| 3718 | if (pll->refcount == 0) |
| 3719 | continue; |
| 3720 | |
Daniel Vetter | b89a1d3 | 2013-06-05 13:34:24 +0200 | [diff] [blame] | 3721 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
| 3722 | sizeof(pll->hw_state)) == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3723 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3724 | crtc->base.base.id, |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3725 | pll->name, pll->refcount, pll->active); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3726 | |
| 3727 | goto found; |
| 3728 | } |
| 3729 | } |
| 3730 | |
| 3731 | /* Ok no matching timings, maybe there's a free one? */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3732 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 3733 | pll = &dev_priv->shared_dplls[i]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3734 | if (pll->refcount == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3735 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
| 3736 | crtc->base.base.id, pll->name); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3737 | goto found; |
| 3738 | } |
| 3739 | } |
| 3740 | |
| 3741 | return NULL; |
| 3742 | |
| 3743 | found: |
Daniel Vetter | f2a69f4 | 2014-05-20 15:19:19 +0200 | [diff] [blame] | 3744 | if (pll->refcount == 0) |
| 3745 | pll->hw_state = crtc->config.dpll_hw_state; |
| 3746 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 3747 | crtc->config.shared_dpll = i; |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3748 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
| 3749 | pipe_name(crtc->pipe)); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 3750 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3751 | pll->refcount++; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3752 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3753 | return pll; |
| 3754 | } |
| 3755 | |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 3756 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3757 | { |
| 3758 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 3759 | int dslreg = PIPEDSL(pipe); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3760 | u32 temp; |
| 3761 | |
| 3762 | temp = I915_READ(dslreg); |
| 3763 | udelay(500); |
| 3764 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3765 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 3766 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3767 | } |
| 3768 | } |
| 3769 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 3770 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
| 3771 | { |
| 3772 | struct drm_device *dev = crtc->base.dev; |
| 3773 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3774 | int pipe = crtc->pipe; |
| 3775 | |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 3776 | if (crtc->config.pch_pfit.enabled) { |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 3777 | /* Force use of hard-coded filter coefficients |
| 3778 | * as some pre-programmed values are broken, |
| 3779 | * e.g. x201. |
| 3780 | */ |
| 3781 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 3782 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
| 3783 | PF_PIPE_SEL_IVB(pipe)); |
| 3784 | else |
| 3785 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
| 3786 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
| 3787 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 3788 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3789 | } |
| 3790 | |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3791 | static void intel_enable_planes(struct drm_crtc *crtc) |
| 3792 | { |
| 3793 | struct drm_device *dev = crtc->dev; |
| 3794 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 3795 | struct drm_plane *plane; |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3796 | struct intel_plane *intel_plane; |
| 3797 | |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 3798 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
| 3799 | intel_plane = to_intel_plane(plane); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3800 | if (intel_plane->pipe == pipe) |
| 3801 | intel_plane_restore(&intel_plane->base); |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 3802 | } |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3803 | } |
| 3804 | |
| 3805 | static void intel_disable_planes(struct drm_crtc *crtc) |
| 3806 | { |
| 3807 | struct drm_device *dev = crtc->dev; |
| 3808 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 3809 | struct drm_plane *plane; |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3810 | struct intel_plane *intel_plane; |
| 3811 | |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 3812 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
| 3813 | intel_plane = to_intel_plane(plane); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3814 | if (intel_plane->pipe == pipe) |
| 3815 | intel_plane_disable(&intel_plane->base); |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 3816 | } |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3817 | } |
| 3818 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 3819 | void hsw_enable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3820 | { |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 3821 | struct drm_device *dev = crtc->base.dev; |
| 3822 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3823 | |
| 3824 | if (!crtc->config.ips_enabled) |
| 3825 | return; |
| 3826 | |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 3827 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
| 3828 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3829 | |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3830 | assert_plane_enabled(dev_priv, crtc->plane); |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 3831 | if (IS_BROADWELL(dev)) { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3832 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3833 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
| 3834 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3835 | /* Quoting Art Runyan: "its not safe to expect any particular |
| 3836 | * value in IPS_CTL bit 31 after enabling IPS through the |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 3837 | * mailbox." Moreover, the mailbox may return a bogus state, |
| 3838 | * so we need to just enable it and continue on. |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3839 | */ |
| 3840 | } else { |
| 3841 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
| 3842 | /* The bit only becomes 1 in the next vblank, so this wait here |
| 3843 | * is essentially intel_wait_for_vblank. If we don't have this |
| 3844 | * and don't wait for vblanks until the end of crtc_enable, then |
| 3845 | * the HW state readout code will complain that the expected |
| 3846 | * IPS_CTL value is not the one we read. */ |
| 3847 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
| 3848 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
| 3849 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3850 | } |
| 3851 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 3852 | void hsw_disable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3853 | { |
| 3854 | struct drm_device *dev = crtc->base.dev; |
| 3855 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3856 | |
| 3857 | if (!crtc->config.ips_enabled) |
| 3858 | return; |
| 3859 | |
| 3860 | assert_plane_enabled(dev_priv, crtc->plane); |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 3861 | if (IS_BROADWELL(dev)) { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3862 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3863 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
| 3864 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 3865 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
| 3866 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) |
| 3867 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 3868 | } else { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3869 | I915_WRITE(IPS_CTL, 0); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 3870 | POSTING_READ(IPS_CTL); |
| 3871 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3872 | |
| 3873 | /* We need to wait for a vblank before we can disable the plane. */ |
| 3874 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3875 | } |
| 3876 | |
| 3877 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 3878 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 3879 | { |
| 3880 | struct drm_device *dev = crtc->dev; |
| 3881 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3882 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3883 | enum pipe pipe = intel_crtc->pipe; |
| 3884 | int palreg = PALETTE(pipe); |
| 3885 | int i; |
| 3886 | bool reenable_ips = false; |
| 3887 | |
| 3888 | /* The clocks have to be on to load the palette. */ |
| 3889 | if (!crtc->enabled || !intel_crtc->active) |
| 3890 | return; |
| 3891 | |
| 3892 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
| 3893 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
| 3894 | assert_dsi_pll_enabled(dev_priv); |
| 3895 | else |
| 3896 | assert_pll_enabled(dev_priv, pipe); |
| 3897 | } |
| 3898 | |
| 3899 | /* use legacy palette for Ironlake */ |
Sonika Jindal | 7a1db49 | 2014-07-22 11:18:27 +0530 | [diff] [blame] | 3900 | if (!HAS_GMCH_DISPLAY(dev)) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3901 | palreg = LGC_PALETTE(pipe); |
| 3902 | |
| 3903 | /* Workaround : Do not read or write the pipe palette/gamma data while |
| 3904 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 3905 | */ |
Paulo Zanoni | 41e6fc4 | 2014-01-08 17:26:31 -0200 | [diff] [blame] | 3906 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3907 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
| 3908 | GAMMA_MODE_MODE_SPLIT)) { |
| 3909 | hsw_disable_ips(intel_crtc); |
| 3910 | reenable_ips = true; |
| 3911 | } |
| 3912 | |
| 3913 | for (i = 0; i < 256; i++) { |
| 3914 | I915_WRITE(palreg + 4 * i, |
| 3915 | (intel_crtc->lut_r[i] << 16) | |
| 3916 | (intel_crtc->lut_g[i] << 8) | |
| 3917 | intel_crtc->lut_b[i]); |
| 3918 | } |
| 3919 | |
| 3920 | if (reenable_ips) |
| 3921 | hsw_enable_ips(intel_crtc); |
| 3922 | } |
| 3923 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 3924 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 3925 | { |
| 3926 | if (!enable && intel_crtc->overlay) { |
| 3927 | struct drm_device *dev = intel_crtc->base.dev; |
| 3928 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3929 | |
| 3930 | mutex_lock(&dev->struct_mutex); |
| 3931 | dev_priv->mm.interruptible = false; |
| 3932 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 3933 | dev_priv->mm.interruptible = true; |
| 3934 | mutex_unlock(&dev->struct_mutex); |
| 3935 | } |
| 3936 | |
| 3937 | /* Let userspace switch the overlay on again. In most cases userspace |
| 3938 | * has to recompute where to put it anyway. |
| 3939 | */ |
| 3940 | } |
| 3941 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 3942 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3943 | { |
| 3944 | struct drm_device *dev = crtc->dev; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3946 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3947 | |
Ville Syrjälä | f98551a | 2014-05-22 17:48:06 +0300 | [diff] [blame] | 3948 | drm_vblank_on(dev, pipe); |
| 3949 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 3950 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3951 | intel_enable_planes(crtc); |
| 3952 | intel_crtc_update_cursor(crtc, true); |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 3953 | intel_crtc_dpms_overlay(intel_crtc, true); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3954 | |
| 3955 | hsw_enable_ips(intel_crtc); |
| 3956 | |
| 3957 | mutex_lock(&dev->struct_mutex); |
| 3958 | intel_update_fbc(dev); |
| 3959 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3960 | |
| 3961 | /* |
| 3962 | * FIXME: Once we grow proper nuclear flip support out of this we need |
| 3963 | * to compute the mask of flip planes precisely. For the time being |
| 3964 | * consider this a flip from a NULL plane. |
| 3965 | */ |
| 3966 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3967 | } |
| 3968 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 3969 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3970 | { |
| 3971 | struct drm_device *dev = crtc->dev; |
| 3972 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3974 | int pipe = intel_crtc->pipe; |
| 3975 | int plane = intel_crtc->plane; |
| 3976 | |
| 3977 | intel_crtc_wait_for_pending_flips(crtc); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3978 | |
| 3979 | if (dev_priv->fbc.plane == plane) |
| 3980 | intel_disable_fbc(dev); |
| 3981 | |
| 3982 | hsw_disable_ips(intel_crtc); |
| 3983 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 3984 | intel_crtc_dpms_overlay(intel_crtc, false); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3985 | intel_crtc_update_cursor(crtc, false); |
| 3986 | intel_disable_planes(crtc); |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 3987 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
Ville Syrjälä | f98551a | 2014-05-22 17:48:06 +0300 | [diff] [blame] | 3988 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3989 | /* |
| 3990 | * FIXME: Once we grow proper nuclear flip support out of this we need |
| 3991 | * to compute the mask of flip planes precisely. For the time being |
| 3992 | * consider this a flip to a NULL plane. |
| 3993 | */ |
| 3994 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
| 3995 | |
Ville Syrjälä | f98551a | 2014-05-22 17:48:06 +0300 | [diff] [blame] | 3996 | drm_vblank_off(dev, pipe); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 3997 | } |
| 3998 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3999 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
| 4000 | { |
| 4001 | struct drm_device *dev = crtc->dev; |
| 4002 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4004 | struct intel_encoder *encoder; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4005 | int pipe = intel_crtc->pipe; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4006 | |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 4007 | WARN_ON(!crtc->enabled); |
| 4008 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4009 | if (intel_crtc->active) |
| 4010 | return; |
| 4011 | |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 4012 | if (intel_crtc->config.has_pch_encoder) |
| 4013 | intel_prepare_shared_dpll(intel_crtc); |
| 4014 | |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 4015 | if (intel_crtc->config.has_dp_encoder) |
| 4016 | intel_dp_set_m_n(intel_crtc); |
| 4017 | |
| 4018 | intel_set_pipe_timings(intel_crtc); |
| 4019 | |
| 4020 | if (intel_crtc->config.has_pch_encoder) { |
| 4021 | intel_cpu_transcoder_set_m_n(intel_crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 4022 | &intel_crtc->config.fdi_m_n, NULL); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 4023 | } |
| 4024 | |
| 4025 | ironlake_set_pipeconf(crtc); |
| 4026 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4027 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4028 | |
| 4029 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
| 4030 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
| 4031 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 4032 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Daniel Vetter | 952735e | 2013-06-05 13:34:27 +0200 | [diff] [blame] | 4033 | if (encoder->pre_enable) |
| 4034 | encoder->pre_enable(encoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4035 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 4036 | if (intel_crtc->config.has_pch_encoder) { |
Daniel Vetter | fff367c | 2012-10-27 15:50:28 +0200 | [diff] [blame] | 4037 | /* Note: FDI PLL enabling _must_ be done before we enable the |
| 4038 | * cpu pipes, hence this is separate from all the other fdi/pch |
| 4039 | * enabling. */ |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4040 | ironlake_fdi_pll_enable(intel_crtc); |
Daniel Vetter | 46b6f81 | 2012-09-06 22:08:33 +0200 | [diff] [blame] | 4041 | } else { |
| 4042 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 4043 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 4044 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4045 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4046 | ironlake_pfit_enable(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4047 | |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 4048 | /* |
| 4049 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 4050 | * clocks enabled |
| 4051 | */ |
| 4052 | intel_crtc_load_lut(crtc); |
| 4053 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4054 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4055 | intel_enable_pipe(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4056 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 4057 | if (intel_crtc->config.has_pch_encoder) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4058 | ironlake_pch_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4059 | |
Daniel Vetter | fa5c73b | 2012-07-01 23:24:36 +0200 | [diff] [blame] | 4060 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4061 | encoder->enable(encoder); |
Daniel Vetter | 61b77dd | 2012-07-02 00:16:19 +0200 | [diff] [blame] | 4062 | |
| 4063 | if (HAS_PCH_CPT(dev)) |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 4064 | cpt_verify_modeset(dev, intel_crtc->pipe); |
Daniel Vetter | 6ce9410 | 2012-10-04 19:20:03 +0200 | [diff] [blame] | 4065 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4066 | intel_crtc_enable_planes(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4067 | } |
| 4068 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4069 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 4070 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
| 4071 | { |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 4072 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4073 | } |
| 4074 | |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 4075 | /* |
| 4076 | * This implements the workaround described in the "notes" section of the mode |
| 4077 | * set sequence documentation. When going from no pipes or single pipe to |
| 4078 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
| 4079 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
| 4080 | */ |
| 4081 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
| 4082 | { |
| 4083 | struct drm_device *dev = crtc->base.dev; |
| 4084 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
| 4085 | |
| 4086 | /* We want to get the other_active_crtc only if there's only 1 other |
| 4087 | * active crtc. */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 4088 | for_each_intel_crtc(dev, crtc_it) { |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 4089 | if (!crtc_it->active || crtc_it == crtc) |
| 4090 | continue; |
| 4091 | |
| 4092 | if (other_active_crtc) |
| 4093 | return; |
| 4094 | |
| 4095 | other_active_crtc = crtc_it; |
| 4096 | } |
| 4097 | if (!other_active_crtc) |
| 4098 | return; |
| 4099 | |
| 4100 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
| 4101 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
| 4102 | } |
| 4103 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4104 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
| 4105 | { |
| 4106 | struct drm_device *dev = crtc->dev; |
| 4107 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4109 | struct intel_encoder *encoder; |
| 4110 | int pipe = intel_crtc->pipe; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4111 | |
| 4112 | WARN_ON(!crtc->enabled); |
| 4113 | |
| 4114 | if (intel_crtc->active) |
| 4115 | return; |
| 4116 | |
Daniel Vetter | df8ad70 | 2014-06-25 22:02:03 +0300 | [diff] [blame] | 4117 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
| 4118 | intel_enable_shared_dpll(intel_crtc); |
| 4119 | |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 4120 | if (intel_crtc->config.has_dp_encoder) |
| 4121 | intel_dp_set_m_n(intel_crtc); |
| 4122 | |
| 4123 | intel_set_pipe_timings(intel_crtc); |
| 4124 | |
| 4125 | if (intel_crtc->config.has_pch_encoder) { |
| 4126 | intel_cpu_transcoder_set_m_n(intel_crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 4127 | &intel_crtc->config.fdi_m_n, NULL); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 4128 | } |
| 4129 | |
| 4130 | haswell_set_pipeconf(crtc); |
| 4131 | |
| 4132 | intel_set_pipe_csc(crtc); |
| 4133 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4134 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4135 | |
| 4136 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4137 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4138 | if (encoder->pre_enable) |
| 4139 | encoder->pre_enable(encoder); |
| 4140 | |
Imre Deak | 4fe9467 | 2014-06-25 22:01:49 +0300 | [diff] [blame] | 4141 | if (intel_crtc->config.has_pch_encoder) { |
| 4142 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
| 4143 | dev_priv->display.fdi_link_train(crtc); |
| 4144 | } |
| 4145 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 4146 | intel_ddi_enable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4147 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4148 | ironlake_pfit_enable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4149 | |
| 4150 | /* |
| 4151 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 4152 | * clocks enabled |
| 4153 | */ |
| 4154 | intel_crtc_load_lut(crtc); |
| 4155 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 4156 | intel_ddi_set_pipe_settings(crtc); |
Damien Lespiau | 8228c25 | 2013-03-07 15:30:27 +0000 | [diff] [blame] | 4157 | intel_ddi_enable_transcoder_func(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4158 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4159 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4160 | intel_enable_pipe(intel_crtc); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4161 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 4162 | if (intel_crtc->config.has_pch_encoder) |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4163 | lpt_pch_enable(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4164 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4165 | if (intel_crtc->config.dp_encoder_is_mst) |
| 4166 | intel_ddi_set_vc_payload_alloc(crtc, true); |
| 4167 | |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 4168 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4169 | encoder->enable(encoder); |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 4170 | intel_opregion_notify_encoder(encoder, true); |
| 4171 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4172 | |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 4173 | /* If we change the relative order between pipe/planes enabling, we need |
| 4174 | * to change the workaround. */ |
| 4175 | haswell_mode_set_planes_workaround(intel_crtc); |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4176 | intel_crtc_enable_planes(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4177 | } |
| 4178 | |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 4179 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
| 4180 | { |
| 4181 | struct drm_device *dev = crtc->base.dev; |
| 4182 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4183 | int pipe = crtc->pipe; |
| 4184 | |
| 4185 | /* To avoid upsetting the power well on haswell only disable the pfit if |
| 4186 | * it's in use. The hw state code will make sure we get this right. */ |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 4187 | if (crtc->config.pch_pfit.enabled) { |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 4188 | I915_WRITE(PF_CTL(pipe), 0); |
| 4189 | I915_WRITE(PF_WIN_POS(pipe), 0); |
| 4190 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
| 4191 | } |
| 4192 | } |
| 4193 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4194 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 4195 | { |
| 4196 | struct drm_device *dev = crtc->dev; |
| 4197 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4199 | struct intel_encoder *encoder; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4200 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4201 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4202 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4203 | if (!intel_crtc->active) |
| 4204 | return; |
| 4205 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4206 | intel_crtc_disable_planes(crtc); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4207 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 4208 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4209 | encoder->disable(encoder); |
| 4210 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4211 | if (intel_crtc->config.has_pch_encoder) |
| 4212 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
| 4213 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 4214 | intel_disable_pipe(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4215 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4216 | if (intel_crtc->config.dp_encoder_is_mst) |
| 4217 | intel_ddi_set_vc_payload_alloc(crtc, false); |
| 4218 | |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 4219 | ironlake_pfit_disable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4220 | |
Daniel Vetter | bf49ec8 | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 4221 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4222 | if (encoder->post_disable) |
| 4223 | encoder->post_disable(encoder); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4224 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4225 | if (intel_crtc->config.has_pch_encoder) { |
| 4226 | ironlake_fdi_disable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4227 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4228 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
| 4229 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4230 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4231 | if (HAS_PCH_CPT(dev)) { |
| 4232 | /* disable TRANS_DP_CTL */ |
| 4233 | reg = TRANS_DP_CTL(pipe); |
| 4234 | temp = I915_READ(reg); |
| 4235 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
| 4236 | TRANS_DP_PORT_SEL_MASK); |
| 4237 | temp |= TRANS_DP_PORT_SEL_NONE; |
| 4238 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4239 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4240 | /* disable DPLL_SEL */ |
| 4241 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 4242 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4243 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4244 | } |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4245 | |
| 4246 | /* disable PCH DPLL */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 4247 | intel_disable_shared_dpll(intel_crtc); |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 4248 | |
| 4249 | ironlake_fdi_pll_disable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4250 | } |
| 4251 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4252 | intel_crtc->active = false; |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4253 | intel_update_watermarks(crtc); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 4254 | |
| 4255 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4256 | intel_update_fbc(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 4257 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4258 | } |
| 4259 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4260 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
| 4261 | { |
| 4262 | struct drm_device *dev = crtc->dev; |
| 4263 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4265 | struct intel_encoder *encoder; |
| 4266 | int pipe = intel_crtc->pipe; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 4267 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4268 | |
| 4269 | if (!intel_crtc->active) |
| 4270 | return; |
| 4271 | |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4272 | intel_crtc_disable_planes(crtc); |
Ville Syrjälä | dda9a66 | 2013-09-19 17:00:37 -0300 | [diff] [blame] | 4273 | |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 4274 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 4275 | intel_opregion_notify_encoder(encoder, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4276 | encoder->disable(encoder); |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 4277 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4278 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4279 | if (intel_crtc->config.has_pch_encoder) |
| 4280 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4281 | intel_disable_pipe(dev_priv, pipe); |
| 4282 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 4283 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4284 | |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 4285 | ironlake_pfit_disable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4286 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 4287 | intel_ddi_disable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4288 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 4289 | if (intel_crtc->config.has_pch_encoder) { |
Paulo Zanoni | ab4d966 | 2012-10-31 18:12:55 -0200 | [diff] [blame] | 4290 | lpt_disable_pch_transcoder(dev_priv); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4291 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
Paulo Zanoni | 1ad960f | 2012-11-01 21:05:05 -0200 | [diff] [blame] | 4292 | intel_ddi_fdi_disable(crtc); |
Paulo Zanoni | 8361663 | 2012-10-23 18:29:54 -0200 | [diff] [blame] | 4293 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4294 | |
Imre Deak | 97b040a | 2014-06-25 22:01:50 +0300 | [diff] [blame] | 4295 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4296 | if (encoder->post_disable) |
| 4297 | encoder->post_disable(encoder); |
| 4298 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4299 | intel_crtc->active = false; |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4300 | intel_update_watermarks(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4301 | |
| 4302 | mutex_lock(&dev->struct_mutex); |
| 4303 | intel_update_fbc(dev); |
| 4304 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | df8ad70 | 2014-06-25 22:02:03 +0300 | [diff] [blame] | 4305 | |
| 4306 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
| 4307 | intel_disable_shared_dpll(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4308 | } |
| 4309 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4310 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
| 4311 | { |
| 4312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 4313 | intel_put_shared_dpll(intel_crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4314 | } |
| 4315 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 4316 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4317 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
| 4318 | { |
| 4319 | struct drm_device *dev = crtc->base.dev; |
| 4320 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4321 | struct intel_crtc_config *pipe_config = &crtc->config; |
| 4322 | |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 4323 | if (!crtc->config.gmch_pfit.control) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4324 | return; |
| 4325 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 4326 | /* |
| 4327 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
| 4328 | * according to register description and PRM. |
| 4329 | */ |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4330 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
| 4331 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 4332 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4333 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
| 4334 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
Daniel Vetter | 5a80c45 | 2013-04-25 22:52:18 +0200 | [diff] [blame] | 4335 | |
| 4336 | /* Border color in case we don't scale up to the full screen. Black by |
| 4337 | * default, change to something else for debugging. */ |
| 4338 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4339 | } |
| 4340 | |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 4341 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
| 4342 | { |
| 4343 | switch (port) { |
| 4344 | case PORT_A: |
| 4345 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; |
| 4346 | case PORT_B: |
| 4347 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; |
| 4348 | case PORT_C: |
| 4349 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
| 4350 | case PORT_D: |
| 4351 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
| 4352 | default: |
| 4353 | WARN_ON_ONCE(1); |
| 4354 | return POWER_DOMAIN_PORT_OTHER; |
| 4355 | } |
| 4356 | } |
| 4357 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4358 | #define for_each_power_domain(domain, mask) \ |
| 4359 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
| 4360 | if ((1 << (domain)) & (mask)) |
| 4361 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4362 | enum intel_display_power_domain |
| 4363 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4364 | { |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4365 | struct drm_device *dev = intel_encoder->base.dev; |
| 4366 | struct intel_digital_port *intel_dig_port; |
| 4367 | |
| 4368 | switch (intel_encoder->type) { |
| 4369 | case INTEL_OUTPUT_UNKNOWN: |
| 4370 | /* Only DDI platforms should ever use this output type */ |
| 4371 | WARN_ON_ONCE(!HAS_DDI(dev)); |
| 4372 | case INTEL_OUTPUT_DISPLAYPORT: |
| 4373 | case INTEL_OUTPUT_HDMI: |
| 4374 | case INTEL_OUTPUT_EDP: |
| 4375 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 4376 | return port_to_power_domain(intel_dig_port->port); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4377 | case INTEL_OUTPUT_DP_MST: |
| 4378 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 4379 | return port_to_power_domain(intel_dig_port->port); |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4380 | case INTEL_OUTPUT_ANALOG: |
| 4381 | return POWER_DOMAIN_PORT_CRT; |
| 4382 | case INTEL_OUTPUT_DSI: |
| 4383 | return POWER_DOMAIN_PORT_DSI; |
| 4384 | default: |
| 4385 | return POWER_DOMAIN_PORT_OTHER; |
| 4386 | } |
| 4387 | } |
| 4388 | |
| 4389 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
| 4390 | { |
| 4391 | struct drm_device *dev = crtc->dev; |
| 4392 | struct intel_encoder *intel_encoder; |
| 4393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4394 | enum pipe pipe = intel_crtc->pipe; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4395 | unsigned long mask; |
| 4396 | enum transcoder transcoder; |
| 4397 | |
| 4398 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
| 4399 | |
| 4400 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
| 4401 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4402 | if (intel_crtc->config.pch_pfit.enabled || |
| 4403 | intel_crtc->config.pch_pfit.force_thru) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4404 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
| 4405 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4406 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 4407 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
| 4408 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4409 | return mask; |
| 4410 | } |
| 4411 | |
| 4412 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
| 4413 | bool enable) |
| 4414 | { |
| 4415 | if (dev_priv->power_domains.init_power_on == enable) |
| 4416 | return; |
| 4417 | |
| 4418 | if (enable) |
| 4419 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
| 4420 | else |
| 4421 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
| 4422 | |
| 4423 | dev_priv->power_domains.init_power_on = enable; |
| 4424 | } |
| 4425 | |
| 4426 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
| 4427 | { |
| 4428 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4429 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
| 4430 | struct intel_crtc *crtc; |
| 4431 | |
| 4432 | /* |
| 4433 | * First get all needed power domains, then put all unneeded, to avoid |
| 4434 | * any unnecessary toggling of the power wells. |
| 4435 | */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 4436 | for_each_intel_crtc(dev, crtc) { |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4437 | enum intel_display_power_domain domain; |
| 4438 | |
| 4439 | if (!crtc->base.enabled) |
| 4440 | continue; |
| 4441 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4442 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4443 | |
| 4444 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
| 4445 | intel_display_power_get(dev_priv, domain); |
| 4446 | } |
| 4447 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 4448 | for_each_intel_crtc(dev, crtc) { |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4449 | enum intel_display_power_domain domain; |
| 4450 | |
| 4451 | for_each_power_domain(domain, crtc->enabled_power_domains) |
| 4452 | intel_display_power_put(dev_priv, domain); |
| 4453 | |
| 4454 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
| 4455 | } |
| 4456 | |
| 4457 | intel_display_set_init_power(dev_priv, false); |
| 4458 | } |
| 4459 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4460 | /* returns HPLL frequency in kHz */ |
Ville Syrjälä | f8bf63f | 2014-06-13 13:37:54 +0300 | [diff] [blame] | 4461 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4462 | { |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 4463 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4464 | |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 4465 | /* Obtain SKU information */ |
| 4466 | mutex_lock(&dev_priv->dpio_lock); |
| 4467 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
| 4468 | CCK_FUSE_HPLL_FREQ_MASK; |
| 4469 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4470 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4471 | return vco_freq[hpll_freq] * 1000; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4472 | } |
| 4473 | |
Ville Syrjälä | f8bf63f | 2014-06-13 13:37:54 +0300 | [diff] [blame] | 4474 | static void vlv_update_cdclk(struct drm_device *dev) |
| 4475 | { |
| 4476 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4477 | |
| 4478 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
| 4479 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", |
| 4480 | dev_priv->vlv_cdclk_freq); |
| 4481 | |
| 4482 | /* |
| 4483 | * Program the gmbus_freq based on the cdclk frequency. |
| 4484 | * BSpec erroneously claims we should aim for 4MHz, but |
| 4485 | * in fact 1MHz is the correct frequency. |
| 4486 | */ |
| 4487 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); |
| 4488 | } |
| 4489 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4490 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
| 4491 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
| 4492 | { |
| 4493 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4494 | u32 val, cmd; |
| 4495 | |
Ville Syrjälä | d197b7d | 2014-06-13 13:37:49 +0300 | [diff] [blame] | 4496 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
Imre Deak | d60c447 | 2014-03-27 17:45:10 +0200 | [diff] [blame] | 4497 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4498 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4499 | cmd = 2; |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4500 | else if (cdclk == 266667) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4501 | cmd = 1; |
| 4502 | else |
| 4503 | cmd = 0; |
| 4504 | |
| 4505 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4506 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 4507 | val &= ~DSPFREQGUAR_MASK; |
| 4508 | val |= (cmd << DSPFREQGUAR_SHIFT); |
| 4509 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 4510 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 4511 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
| 4512 | 50)) { |
| 4513 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 4514 | } |
| 4515 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4516 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4517 | if (cdclk == 400000) { |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4518 | u32 divider, vco; |
| 4519 | |
| 4520 | vco = valleyview_get_vco(dev_priv); |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4521 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4522 | |
| 4523 | mutex_lock(&dev_priv->dpio_lock); |
| 4524 | /* adjust cdclk divider */ |
| 4525 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
Ville Syrjälä | 9cf33db | 2014-06-13 13:37:48 +0300 | [diff] [blame] | 4526 | val &= ~DISPLAY_FREQUENCY_VALUES; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4527 | val |= divider; |
| 4528 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
Ville Syrjälä | a877e80 | 2014-06-13 13:37:52 +0300 | [diff] [blame] | 4529 | |
| 4530 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
| 4531 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
| 4532 | 50)) |
| 4533 | DRM_ERROR("timed out waiting for CDclk change\n"); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4534 | mutex_unlock(&dev_priv->dpio_lock); |
| 4535 | } |
| 4536 | |
| 4537 | mutex_lock(&dev_priv->dpio_lock); |
| 4538 | /* adjust self-refresh exit latency value */ |
| 4539 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
| 4540 | val &= ~0x7f; |
| 4541 | |
| 4542 | /* |
| 4543 | * For high bandwidth configs, we set a higher latency in the bunit |
| 4544 | * so that the core display fetch happens in time to avoid underruns. |
| 4545 | */ |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4546 | if (cdclk == 400000) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4547 | val |= 4500 / 250; /* 4.5 usec */ |
| 4548 | else |
| 4549 | val |= 3000 / 250; /* 3.0 usec */ |
| 4550 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
| 4551 | mutex_unlock(&dev_priv->dpio_lock); |
| 4552 | |
Ville Syrjälä | f8bf63f | 2014-06-13 13:37:54 +0300 | [diff] [blame] | 4553 | vlv_update_cdclk(dev); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4554 | } |
| 4555 | |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 4556 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
| 4557 | { |
| 4558 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4559 | u32 val, cmd; |
| 4560 | |
| 4561 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
| 4562 | |
| 4563 | switch (cdclk) { |
| 4564 | case 400000: |
| 4565 | cmd = 3; |
| 4566 | break; |
| 4567 | case 333333: |
| 4568 | case 320000: |
| 4569 | cmd = 2; |
| 4570 | break; |
| 4571 | case 266667: |
| 4572 | cmd = 1; |
| 4573 | break; |
| 4574 | case 200000: |
| 4575 | cmd = 0; |
| 4576 | break; |
| 4577 | default: |
| 4578 | WARN_ON(1); |
| 4579 | return; |
| 4580 | } |
| 4581 | |
| 4582 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4583 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 4584 | val &= ~DSPFREQGUAR_MASK_CHV; |
| 4585 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); |
| 4586 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 4587 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 4588 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), |
| 4589 | 50)) { |
| 4590 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 4591 | } |
| 4592 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4593 | |
| 4594 | vlv_update_cdclk(dev); |
| 4595 | } |
| 4596 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4597 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
| 4598 | int max_pixclk) |
| 4599 | { |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 4600 | int vco = valleyview_get_vco(dev_priv); |
| 4601 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; |
| 4602 | |
Ville Syrjälä | d49a340 | 2014-06-28 02:03:58 +0300 | [diff] [blame] | 4603 | /* FIXME: Punit isn't quite ready yet */ |
| 4604 | if (IS_CHERRYVIEW(dev_priv->dev)) |
| 4605 | return 400000; |
| 4606 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4607 | /* |
| 4608 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
| 4609 | * 200MHz |
| 4610 | * 267MHz |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 4611 | * 320/333MHz (depends on HPLL freq) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4612 | * 400MHz |
| 4613 | * So we check to see whether we're above 90% of the lower bin and |
| 4614 | * adjust if needed. |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 4615 | * |
| 4616 | * We seem to get an unstable or solid color picture at 200MHz. |
| 4617 | * Not sure what's wrong. For now use 200MHz only when all pipes |
| 4618 | * are off. |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4619 | */ |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 4620 | if (max_pixclk > freq_320*9/10) |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4621 | return 400000; |
| 4622 | else if (max_pixclk > 266667*9/10) |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 4623 | return freq_320; |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 4624 | else if (max_pixclk > 0) |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 4625 | return 266667; |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 4626 | else |
| 4627 | return 200000; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4628 | } |
| 4629 | |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4630 | /* compute the max pixel clock for new configuration */ |
| 4631 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4632 | { |
| 4633 | struct drm_device *dev = dev_priv->dev; |
| 4634 | struct intel_crtc *intel_crtc; |
| 4635 | int max_pixclk = 0; |
| 4636 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 4637 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4638 | if (intel_crtc->new_enabled) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4639 | max_pixclk = max(max_pixclk, |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4640 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4641 | } |
| 4642 | |
| 4643 | return max_pixclk; |
| 4644 | } |
| 4645 | |
| 4646 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4647 | unsigned *prepare_pipes) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4648 | { |
| 4649 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4650 | struct intel_crtc *intel_crtc; |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4651 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4652 | |
Imre Deak | d60c447 | 2014-03-27 17:45:10 +0200 | [diff] [blame] | 4653 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
| 4654 | dev_priv->vlv_cdclk_freq) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4655 | return; |
| 4656 | |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4657 | /* disable/enable all currently active pipes while we change cdclk */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 4658 | for_each_intel_crtc(dev, intel_crtc) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4659 | if (intel_crtc->base.enabled) |
| 4660 | *prepare_pipes |= (1 << intel_crtc->pipe); |
| 4661 | } |
| 4662 | |
| 4663 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
| 4664 | { |
| 4665 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4666 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4667 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
| 4668 | |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 4669 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
| 4670 | if (IS_CHERRYVIEW(dev)) |
| 4671 | cherryview_set_cdclk(dev, req_cdclk); |
| 4672 | else |
| 4673 | valleyview_set_cdclk(dev, req_cdclk); |
| 4674 | } |
| 4675 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 4676 | modeset_update_crtc_power_domains(dev); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4677 | } |
| 4678 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4679 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
| 4680 | { |
| 4681 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4682 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4683 | struct intel_encoder *encoder; |
| 4684 | int pipe = intel_crtc->pipe; |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 4685 | bool is_dsi; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4686 | |
| 4687 | WARN_ON(!crtc->enabled); |
| 4688 | |
| 4689 | if (intel_crtc->active) |
| 4690 | return; |
| 4691 | |
Shobhit Kumar | 8525a23 | 2014-06-25 12:20:39 +0530 | [diff] [blame] | 4692 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
| 4693 | |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 4694 | if (!is_dsi) { |
| 4695 | if (IS_CHERRYVIEW(dev)) |
| 4696 | chv_prepare_pll(intel_crtc); |
| 4697 | else |
| 4698 | vlv_prepare_pll(intel_crtc); |
| 4699 | } |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 4700 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 4701 | if (intel_crtc->config.has_dp_encoder) |
| 4702 | intel_dp_set_m_n(intel_crtc); |
| 4703 | |
| 4704 | intel_set_pipe_timings(intel_crtc); |
| 4705 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 4706 | i9xx_set_pipeconf(intel_crtc); |
| 4707 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4708 | intel_crtc->active = true; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4709 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 4710 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
| 4711 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4712 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4713 | if (encoder->pre_pll_enable) |
| 4714 | encoder->pre_pll_enable(encoder); |
| 4715 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 4716 | if (!is_dsi) { |
| 4717 | if (IS_CHERRYVIEW(dev)) |
| 4718 | chv_enable_pll(intel_crtc); |
| 4719 | else |
| 4720 | vlv_enable_pll(intel_crtc); |
| 4721 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4722 | |
| 4723 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4724 | if (encoder->pre_enable) |
| 4725 | encoder->pre_enable(encoder); |
| 4726 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4727 | i9xx_pfit_enable(intel_crtc); |
| 4728 | |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 4729 | intel_crtc_load_lut(crtc); |
| 4730 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4731 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4732 | intel_enable_pipe(intel_crtc); |
Daniel Vetter | be6a6f8 | 2014-04-15 18:41:22 +0200 | [diff] [blame] | 4733 | |
Jani Nikula | 5004945 | 2013-07-30 12:20:32 +0300 | [diff] [blame] | 4734 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4735 | encoder->enable(encoder); |
Ville Syrjälä | 9ab0460 | 2014-05-08 19:23:14 +0300 | [diff] [blame] | 4736 | |
| 4737 | intel_crtc_enable_planes(crtc); |
Daniel Vetter | d40d918 | 2014-05-21 11:45:40 +0200 | [diff] [blame] | 4738 | |
Ville Syrjälä | 56b80e1 | 2014-05-16 19:40:22 +0300 | [diff] [blame] | 4739 | /* Underruns don't raise interrupts, so check manually. */ |
| 4740 | i9xx_check_fifo_underruns(dev); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4741 | } |
| 4742 | |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 4743 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
| 4744 | { |
| 4745 | struct drm_device *dev = crtc->base.dev; |
| 4746 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4747 | |
| 4748 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); |
| 4749 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); |
| 4750 | } |
| 4751 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4752 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4753 | { |
| 4754 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4756 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4757 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4758 | |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 4759 | WARN_ON(!crtc->enabled); |
| 4760 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4761 | if (intel_crtc->active) |
| 4762 | return; |
| 4763 | |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 4764 | i9xx_set_pll_dividers(intel_crtc); |
| 4765 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 4766 | if (intel_crtc->config.has_dp_encoder) |
| 4767 | intel_dp_set_m_n(intel_crtc); |
| 4768 | |
| 4769 | intel_set_pipe_timings(intel_crtc); |
| 4770 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 4771 | i9xx_set_pipeconf(intel_crtc); |
| 4772 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4773 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4774 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 4775 | if (!IS_GEN2(dev)) |
| 4776 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
| 4777 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 4778 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Mika Kuoppala | 9d6d9f1 | 2013-02-08 16:35:38 +0200 | [diff] [blame] | 4779 | if (encoder->pre_enable) |
| 4780 | encoder->pre_enable(encoder); |
| 4781 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 4782 | i9xx_enable_pll(intel_crtc); |
| 4783 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4784 | i9xx_pfit_enable(intel_crtc); |
| 4785 | |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 4786 | intel_crtc_load_lut(crtc); |
| 4787 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4788 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4789 | intel_enable_pipe(intel_crtc); |
Daniel Vetter | be6a6f8 | 2014-04-15 18:41:22 +0200 | [diff] [blame] | 4790 | |
Daniel Vetter | fa5c73b | 2012-07-01 23:24:36 +0200 | [diff] [blame] | 4791 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4792 | encoder->enable(encoder); |
Ville Syrjälä | 9ab0460 | 2014-05-08 19:23:14 +0300 | [diff] [blame] | 4793 | |
| 4794 | intel_crtc_enable_planes(crtc); |
Daniel Vetter | d40d918 | 2014-05-21 11:45:40 +0200 | [diff] [blame] | 4795 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 4796 | /* |
| 4797 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4798 | * So don't enable underrun reporting before at least some planes |
| 4799 | * are enabled. |
| 4800 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4801 | * but leave the pipe running. |
| 4802 | */ |
| 4803 | if (IS_GEN2(dev)) |
| 4804 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
| 4805 | |
Ville Syrjälä | 56b80e1 | 2014-05-16 19:40:22 +0300 | [diff] [blame] | 4806 | /* Underruns don't raise interrupts, so check manually. */ |
| 4807 | i9xx_check_fifo_underruns(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4808 | } |
| 4809 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4810 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
| 4811 | { |
| 4812 | struct drm_device *dev = crtc->base.dev; |
| 4813 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 4814 | |
| 4815 | if (!crtc->config.gmch_pfit.control) |
| 4816 | return; |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4817 | |
| 4818 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 4819 | |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 4820 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
| 4821 | I915_READ(PFIT_CONTROL)); |
| 4822 | I915_WRITE(PFIT_CONTROL, 0); |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4823 | } |
| 4824 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4825 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 4826 | { |
| 4827 | struct drm_device *dev = crtc->dev; |
| 4828 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4830 | struct intel_encoder *encoder; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4831 | int pipe = intel_crtc->pipe; |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4832 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4833 | if (!intel_crtc->active) |
| 4834 | return; |
| 4835 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 4836 | /* |
| 4837 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4838 | * So diasble underrun reporting before all the planes get disabled. |
| 4839 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4840 | * but leave the pipe running. |
| 4841 | */ |
| 4842 | if (IS_GEN2(dev)) |
| 4843 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
| 4844 | |
Imre Deak | 564ed19 | 2014-06-13 14:54:21 +0300 | [diff] [blame] | 4845 | /* |
| 4846 | * Vblank time updates from the shadow to live plane control register |
| 4847 | * are blocked if the memory self-refresh mode is active at that |
| 4848 | * moment. So to make sure the plane gets truly disabled, disable |
| 4849 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 4850 | * will be checked/applied by the HW only at the next frame start |
| 4851 | * event which is after the vblank start event, so we need to have a |
| 4852 | * wait-for-vblank between disabling the plane and the pipe. |
| 4853 | */ |
| 4854 | intel_set_memory_cxsr(dev_priv, false); |
Ville Syrjälä | 9ab0460 | 2014-05-08 19:23:14 +0300 | [diff] [blame] | 4855 | intel_crtc_disable_planes(crtc); |
| 4856 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 4857 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4858 | encoder->disable(encoder); |
| 4859 | |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 4860 | /* |
| 4861 | * On gen2 planes are double buffered but the pipe isn't, so we must |
| 4862 | * wait for planes to fully turn off before disabling the pipe. |
Imre Deak | 564ed19 | 2014-06-13 14:54:21 +0300 | [diff] [blame] | 4863 | * We also need to wait on all gmch platforms because of the |
| 4864 | * self-refresh mode constraint explained above. |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 4865 | */ |
Imre Deak | 564ed19 | 2014-06-13 14:54:21 +0300 | [diff] [blame] | 4866 | intel_wait_for_vblank(dev, pipe); |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 4867 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 4868 | intel_disable_pipe(dev_priv, pipe); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 4869 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4870 | i9xx_pfit_disable(intel_crtc); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 4871 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4872 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4873 | if (encoder->post_disable) |
| 4874 | encoder->post_disable(encoder); |
| 4875 | |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 4876 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
| 4877 | if (IS_CHERRYVIEW(dev)) |
| 4878 | chv_disable_pll(dev_priv, pipe); |
| 4879 | else if (IS_VALLEYVIEW(dev)) |
| 4880 | vlv_disable_pll(dev_priv, pipe); |
| 4881 | else |
| 4882 | i9xx_disable_pll(dev_priv, pipe); |
| 4883 | } |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4884 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 4885 | if (!IS_GEN2(dev)) |
| 4886 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
| 4887 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4888 | intel_crtc->active = false; |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4889 | intel_update_watermarks(crtc); |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4890 | |
Daniel Vetter | efa9624 | 2014-04-24 23:55:02 +0200 | [diff] [blame] | 4891 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4892 | intel_update_fbc(dev); |
Daniel Vetter | efa9624 | 2014-04-24 23:55:02 +0200 | [diff] [blame] | 4893 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4894 | } |
| 4895 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4896 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
| 4897 | { |
| 4898 | } |
| 4899 | |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4900 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
| 4901 | bool enabled) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4902 | { |
| 4903 | struct drm_device *dev = crtc->dev; |
| 4904 | struct drm_i915_master_private *master_priv; |
| 4905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4906 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4907 | |
| 4908 | if (!dev->primary->master) |
| 4909 | return; |
| 4910 | |
| 4911 | master_priv = dev->primary->master->driver_priv; |
| 4912 | if (!master_priv->sarea_priv) |
| 4913 | return; |
| 4914 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4915 | switch (pipe) { |
| 4916 | case 0: |
| 4917 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 4918 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 4919 | break; |
| 4920 | case 1: |
| 4921 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 4922 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 4923 | break; |
| 4924 | default: |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4925 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4926 | break; |
| 4927 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4928 | } |
| 4929 | |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 4930 | /* Master function to enable/disable CRTC and corresponding power wells */ |
| 4931 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4932 | { |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4933 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4934 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 4935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 4936 | enum intel_display_power_domain domain; |
| 4937 | unsigned long domains; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4938 | |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 4939 | if (enable) { |
| 4940 | if (!intel_crtc->active) { |
Daniel Vetter | e1e9fb8 | 2014-06-25 22:02:04 +0300 | [diff] [blame] | 4941 | domains = get_crtc_power_domains(crtc); |
| 4942 | for_each_power_domain(domain, domains) |
| 4943 | intel_display_power_get(dev_priv, domain); |
| 4944 | intel_crtc->enabled_power_domains = domains; |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 4945 | |
| 4946 | dev_priv->display.crtc_enable(crtc); |
| 4947 | } |
| 4948 | } else { |
| 4949 | if (intel_crtc->active) { |
| 4950 | dev_priv->display.crtc_disable(crtc); |
| 4951 | |
Daniel Vetter | e1e9fb8 | 2014-06-25 22:02:04 +0300 | [diff] [blame] | 4952 | domains = intel_crtc->enabled_power_domains; |
| 4953 | for_each_power_domain(domain, domains) |
| 4954 | intel_display_power_put(dev_priv, domain); |
| 4955 | intel_crtc->enabled_power_domains = 0; |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 4956 | } |
| 4957 | } |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 4958 | } |
| 4959 | |
| 4960 | /** |
| 4961 | * Sets the power management mode of the pipe and plane. |
| 4962 | */ |
| 4963 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
| 4964 | { |
| 4965 | struct drm_device *dev = crtc->dev; |
| 4966 | struct intel_encoder *intel_encoder; |
| 4967 | bool enable = false; |
| 4968 | |
| 4969 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 4970 | enable |= intel_encoder->connectors_active; |
| 4971 | |
| 4972 | intel_crtc_control(crtc, enable); |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4973 | |
| 4974 | intel_crtc_update_sarea(crtc, enable); |
| 4975 | } |
| 4976 | |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4977 | static void intel_crtc_disable(struct drm_crtc *crtc) |
| 4978 | { |
| 4979 | struct drm_device *dev = crtc->dev; |
| 4980 | struct drm_connector *connector; |
| 4981 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 4982 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4983 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4984 | |
| 4985 | /* crtc should still be enabled when we disable it. */ |
| 4986 | WARN_ON(!crtc->enabled); |
| 4987 | |
| 4988 | dev_priv->display.crtc_disable(crtc); |
| 4989 | intel_crtc_update_sarea(crtc, false); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4990 | dev_priv->display.off(crtc); |
| 4991 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 4992 | if (crtc->primary->fb) { |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4993 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4994 | intel_unpin_fb_obj(old_obj); |
| 4995 | i915_gem_track_fb(old_obj, NULL, |
| 4996 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4997 | mutex_unlock(&dev->struct_mutex); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 4998 | crtc->primary->fb = NULL; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4999 | } |
| 5000 | |
| 5001 | /* Update computed state. */ |
| 5002 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 5003 | if (!connector->encoder || !connector->encoder->crtc) |
| 5004 | continue; |
| 5005 | |
| 5006 | if (connector->encoder->crtc != crtc) |
| 5007 | continue; |
| 5008 | |
| 5009 | connector->dpms = DRM_MODE_DPMS_OFF; |
| 5010 | to_intel_encoder(connector->encoder)->connectors_active = false; |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 5011 | } |
| 5012 | } |
| 5013 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 5014 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 5015 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5016 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 5017 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 5018 | drm_encoder_cleanup(encoder); |
| 5019 | kfree(intel_encoder); |
| 5020 | } |
| 5021 | |
Damien Lespiau | 9237329 | 2013-08-08 22:28:57 +0100 | [diff] [blame] | 5022 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5023 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
| 5024 | * state of the entire output pipe. */ |
Damien Lespiau | 9237329 | 2013-08-08 22:28:57 +0100 | [diff] [blame] | 5025 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5026 | { |
| 5027 | if (mode == DRM_MODE_DPMS_ON) { |
| 5028 | encoder->connectors_active = true; |
| 5029 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 5030 | intel_crtc_update_dpms(encoder->base.crtc); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5031 | } else { |
| 5032 | encoder->connectors_active = false; |
| 5033 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 5034 | intel_crtc_update_dpms(encoder->base.crtc); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5035 | } |
| 5036 | } |
| 5037 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5038 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
| 5039 | * internal consistency). */ |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 5040 | static void intel_connector_check_state(struct intel_connector *connector) |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5041 | { |
| 5042 | if (connector->get_hw_state(connector)) { |
| 5043 | struct intel_encoder *encoder = connector->encoder; |
| 5044 | struct drm_crtc *crtc; |
| 5045 | bool encoder_enabled; |
| 5046 | enum pipe pipe; |
| 5047 | |
| 5048 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 5049 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 5050 | connector->base.name); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5051 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5052 | /* there is no real hw state for MST connectors */ |
| 5053 | if (connector->mst_port) |
| 5054 | return; |
| 5055 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5056 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
| 5057 | "wrong connector dpms state\n"); |
| 5058 | WARN(connector->base.encoder != &encoder->base, |
| 5059 | "active connector not linked to encoder\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5060 | |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 5061 | if (encoder) { |
| 5062 | WARN(!encoder->connectors_active, |
| 5063 | "encoder->connectors_active not set\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5064 | |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 5065 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
| 5066 | WARN(!encoder_enabled, "encoder not enabled\n"); |
| 5067 | if (WARN_ON(!encoder->base.crtc)) |
| 5068 | return; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5069 | |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 5070 | crtc = encoder->base.crtc; |
| 5071 | |
| 5072 | WARN(!crtc->enabled, "crtc not enabled\n"); |
| 5073 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
| 5074 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
| 5075 | "encoder active on the wrong pipe\n"); |
| 5076 | } |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5077 | } |
| 5078 | } |
| 5079 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5080 | /* Even simpler default implementation, if there's really no special case to |
| 5081 | * consider. */ |
| 5082 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
| 5083 | { |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5084 | /* All the simple cases only support two dpms states. */ |
| 5085 | if (mode != DRM_MODE_DPMS_ON) |
| 5086 | mode = DRM_MODE_DPMS_OFF; |
| 5087 | |
| 5088 | if (mode == connector->dpms) |
| 5089 | return; |
| 5090 | |
| 5091 | connector->dpms = mode; |
| 5092 | |
| 5093 | /* Only need to change hw state when actually enabled */ |
Chris Wilson | c9976dc | 2013-09-29 19:15:07 +0100 | [diff] [blame] | 5094 | if (connector->encoder) |
| 5095 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 5096 | |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 5097 | intel_modeset_check_state(connector->dev); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 5098 | } |
| 5099 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 5100 | /* Simple connector->get_hw_state implementation for encoders that support only |
| 5101 | * one connector and no cloning and hence the encoder state determines the state |
| 5102 | * of the connector. */ |
| 5103 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
| 5104 | { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 5105 | enum pipe pipe = 0; |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 5106 | struct intel_encoder *encoder = connector->encoder; |
| 5107 | |
| 5108 | return encoder->get_hw_state(encoder, &pipe); |
| 5109 | } |
| 5110 | |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 5111 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
| 5112 | struct intel_crtc_config *pipe_config) |
| 5113 | { |
| 5114 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5115 | struct intel_crtc *pipe_B_crtc = |
| 5116 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
| 5117 | |
| 5118 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
| 5119 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 5120 | if (pipe_config->fdi_lanes > 4) { |
| 5121 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
| 5122 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 5123 | return false; |
| 5124 | } |
| 5125 | |
Paulo Zanoni | bafb655 | 2013-11-02 21:07:44 -0700 | [diff] [blame] | 5126 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 5127 | if (pipe_config->fdi_lanes > 2) { |
| 5128 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
| 5129 | pipe_config->fdi_lanes); |
| 5130 | return false; |
| 5131 | } else { |
| 5132 | return true; |
| 5133 | } |
| 5134 | } |
| 5135 | |
| 5136 | if (INTEL_INFO(dev)->num_pipes == 2) |
| 5137 | return true; |
| 5138 | |
| 5139 | /* Ivybridge 3 pipe is really complicated */ |
| 5140 | switch (pipe) { |
| 5141 | case PIPE_A: |
| 5142 | return true; |
| 5143 | case PIPE_B: |
| 5144 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
| 5145 | pipe_config->fdi_lanes > 2) { |
| 5146 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 5147 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 5148 | return false; |
| 5149 | } |
| 5150 | return true; |
| 5151 | case PIPE_C: |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 5152 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 5153 | pipe_B_crtc->config.fdi_lanes <= 2) { |
| 5154 | if (pipe_config->fdi_lanes > 2) { |
| 5155 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 5156 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 5157 | return false; |
| 5158 | } |
| 5159 | } else { |
| 5160 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
| 5161 | return false; |
| 5162 | } |
| 5163 | return true; |
| 5164 | default: |
| 5165 | BUG(); |
| 5166 | } |
| 5167 | } |
| 5168 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5169 | #define RETRY 1 |
| 5170 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
| 5171 | struct intel_crtc_config *pipe_config) |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5172 | { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 5173 | struct drm_device *dev = intel_crtc->base.dev; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5174 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 5175 | int lane, link_bw, fdi_dotclock; |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5176 | bool setup_ok, needs_recompute = false; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5177 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5178 | retry: |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5179 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 5180 | * each output octet as 10 bits. The actual frequency |
| 5181 | * is stored as a divider into a 100MHz clock, and the |
| 5182 | * mode pixel clock is stored in units of 1KHz. |
| 5183 | * Hence the bw of each lane in terms of the mode signal |
| 5184 | * is: |
| 5185 | */ |
| 5186 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
| 5187 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 5188 | fdi_dotclock = adjusted_mode->crtc_clock; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5189 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 5190 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5191 | pipe_config->pipe_bpp); |
| 5192 | |
| 5193 | pipe_config->fdi_lanes = lane; |
| 5194 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 5195 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5196 | link_bw, &pipe_config->fdi_m_n); |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 5197 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5198 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
| 5199 | intel_crtc->pipe, pipe_config); |
| 5200 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
| 5201 | pipe_config->pipe_bpp -= 2*3; |
| 5202 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
| 5203 | pipe_config->pipe_bpp); |
| 5204 | needs_recompute = true; |
| 5205 | pipe_config->bw_constrained = true; |
| 5206 | |
| 5207 | goto retry; |
| 5208 | } |
| 5209 | |
| 5210 | if (needs_recompute) |
| 5211 | return RETRY; |
| 5212 | |
| 5213 | return setup_ok ? 0 : -EINVAL; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5214 | } |
| 5215 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5216 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
| 5217 | struct intel_crtc_config *pipe_config) |
| 5218 | { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 5219 | pipe_config->ips_enabled = i915.enable_ips && |
Paulo Zanoni | 3c4ca58 | 2013-05-31 16:33:23 -0300 | [diff] [blame] | 5220 | hsw_crtc_supports_ips(crtc) && |
Jesse Barnes | b6dfdc9 | 2013-07-25 10:06:50 -0700 | [diff] [blame] | 5221 | pipe_config->pipe_bpp <= 24; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5222 | } |
| 5223 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 5224 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5225 | struct intel_crtc_config *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5226 | { |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 5227 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 5228 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 5229 | |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 5230 | /* FIXME should check pixel clock limits on all platforms */ |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 5231 | if (INTEL_INFO(dev)->gen < 4) { |
| 5232 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5233 | int clock_limit = |
| 5234 | dev_priv->display.get_display_clock_speed(dev); |
| 5235 | |
| 5236 | /* |
| 5237 | * Enable pixel doubling when the dot clock |
| 5238 | * is > 90% of the (display) core speed. |
| 5239 | * |
Ville Syrjälä | b397c96 | 2013-09-04 18:30:06 +0300 | [diff] [blame] | 5240 | * GDG double wide on either pipe, |
| 5241 | * otherwise pipe A only. |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 5242 | */ |
Ville Syrjälä | b397c96 | 2013-09-04 18:30:06 +0300 | [diff] [blame] | 5243 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 5244 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 5245 | clock_limit *= 2; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 5246 | pipe_config->double_wide = true; |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 5247 | } |
| 5248 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 5249 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5250 | return -EINVAL; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5251 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 5252 | |
Ville Syrjälä | 1d1d0e2 | 2013-09-04 18:30:05 +0300 | [diff] [blame] | 5253 | /* |
| 5254 | * Pipe horizontal size must be even in: |
| 5255 | * - DVO ganged mode |
| 5256 | * - LVDS dual channel mode |
| 5257 | * - Double wide pipe |
| 5258 | */ |
| 5259 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
| 5260 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
| 5261 | pipe_config->pipe_src_w &= ~1; |
| 5262 | |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 5263 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
| 5264 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 5265 | */ |
| 5266 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
| 5267 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5268 | return -EINVAL; |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 5269 | |
Daniel Vetter | bd080ee | 2013-04-17 20:01:39 +0200 | [diff] [blame] | 5270 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
Daniel Vetter | 5d2d38d | 2013-03-27 00:45:01 +0100 | [diff] [blame] | 5271 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
Daniel Vetter | bd080ee | 2013-04-17 20:01:39 +0200 | [diff] [blame] | 5272 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
Daniel Vetter | 5d2d38d | 2013-03-27 00:45:01 +0100 | [diff] [blame] | 5273 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
| 5274 | * for lvds. */ |
| 5275 | pipe_config->pipe_bpp = 8*3; |
| 5276 | } |
| 5277 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 5278 | if (HAS_IPS(dev)) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 5279 | hsw_compute_ips_config(crtc, pipe_config); |
| 5280 | |
Daniel Vetter | 1203043 | 2014-06-25 22:02:00 +0300 | [diff] [blame] | 5281 | /* |
| 5282 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the |
| 5283 | * old clock survives for now. |
| 5284 | */ |
| 5285 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 5286 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5287 | |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5288 | if (pipe_config->has_pch_encoder) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 5289 | return ironlake_fdi_compute_config(crtc, pipe_config); |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 5290 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 5291 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5292 | } |
| 5293 | |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 5294 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
| 5295 | { |
Ville Syrjälä | d197b7d | 2014-06-13 13:37:49 +0300 | [diff] [blame] | 5296 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5297 | int vco = valleyview_get_vco(dev_priv); |
| 5298 | u32 val; |
| 5299 | int divider; |
| 5300 | |
Ville Syrjälä | d49a340 | 2014-06-28 02:03:58 +0300 | [diff] [blame] | 5301 | /* FIXME: Punit isn't quite ready yet */ |
| 5302 | if (IS_CHERRYVIEW(dev)) |
| 5303 | return 400000; |
| 5304 | |
Ville Syrjälä | d197b7d | 2014-06-13 13:37:49 +0300 | [diff] [blame] | 5305 | mutex_lock(&dev_priv->dpio_lock); |
| 5306 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
| 5307 | mutex_unlock(&dev_priv->dpio_lock); |
| 5308 | |
| 5309 | divider = val & DISPLAY_FREQUENCY_VALUES; |
| 5310 | |
Ville Syrjälä | 7d007f4 | 2014-06-13 13:37:53 +0300 | [diff] [blame] | 5311 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
| 5312 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
| 5313 | "cdclk change in progress\n"); |
| 5314 | |
Ville Syrjälä | d197b7d | 2014-06-13 13:37:49 +0300 | [diff] [blame] | 5315 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 5316 | } |
| 5317 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5318 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5319 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5320 | return 400000; |
| 5321 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5322 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5323 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 5324 | { |
| 5325 | return 333000; |
| 5326 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5327 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5328 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 5329 | { |
| 5330 | return 200000; |
| 5331 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5332 | |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 5333 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
| 5334 | { |
| 5335 | u16 gcfgc = 0; |
| 5336 | |
| 5337 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 5338 | |
| 5339 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 5340 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
| 5341 | return 267000; |
| 5342 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
| 5343 | return 333000; |
| 5344 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
| 5345 | return 444000; |
| 5346 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
| 5347 | return 200000; |
| 5348 | default: |
| 5349 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
| 5350 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
| 5351 | return 133000; |
| 5352 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
| 5353 | return 167000; |
| 5354 | } |
| 5355 | } |
| 5356 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5357 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 5358 | { |
| 5359 | u16 gcfgc = 0; |
| 5360 | |
| 5361 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 5362 | |
| 5363 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5364 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5365 | else { |
| 5366 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 5367 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 5368 | return 333000; |
| 5369 | default: |
| 5370 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 5371 | return 190000; |
| 5372 | } |
| 5373 | } |
| 5374 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5375 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5376 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 5377 | { |
| 5378 | return 266000; |
| 5379 | } |
| 5380 | |
| 5381 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 5382 | { |
| 5383 | u16 hpllcc = 0; |
| 5384 | /* Assume that the hardware is in the high speed state. This |
| 5385 | * should be the default. |
| 5386 | */ |
| 5387 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 5388 | case GC_CLOCK_133_200: |
| 5389 | case GC_CLOCK_100_200: |
| 5390 | return 200000; |
| 5391 | case GC_CLOCK_166_250: |
| 5392 | return 250000; |
| 5393 | case GC_CLOCK_100_133: |
| 5394 | return 133000; |
| 5395 | } |
| 5396 | |
| 5397 | /* Shouldn't happen */ |
| 5398 | return 0; |
| 5399 | } |
| 5400 | |
| 5401 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 5402 | { |
| 5403 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5404 | } |
| 5405 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5406 | static void |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 5407 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5408 | { |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 5409 | while (*num > DATA_LINK_M_N_MASK || |
| 5410 | *den > DATA_LINK_M_N_MASK) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5411 | *num >>= 1; |
| 5412 | *den >>= 1; |
| 5413 | } |
| 5414 | } |
| 5415 | |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 5416 | static void compute_m_n(unsigned int m, unsigned int n, |
| 5417 | uint32_t *ret_m, uint32_t *ret_n) |
| 5418 | { |
| 5419 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
| 5420 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
| 5421 | intel_reduce_m_n_ratio(ret_m, ret_n); |
| 5422 | } |
| 5423 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 5424 | void |
| 5425 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
| 5426 | int pixel_clock, int link_clock, |
| 5427 | struct intel_link_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5428 | { |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 5429 | m_n->tu = 64; |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 5430 | |
| 5431 | compute_m_n(bits_per_pixel * pixel_clock, |
| 5432 | link_clock * nlanes * 8, |
| 5433 | &m_n->gmch_m, &m_n->gmch_n); |
| 5434 | |
| 5435 | compute_m_n(pixel_clock, link_clock, |
| 5436 | &m_n->link_m, &m_n->link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 5437 | } |
| 5438 | |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 5439 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 5440 | { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 5441 | if (i915.panel_use_ssc >= 0) |
| 5442 | return i915.panel_use_ssc != 0; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5443 | return dev_priv->vbt.lvds_use_ssc |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 5444 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 5445 | } |
| 5446 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5447 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
| 5448 | { |
| 5449 | struct drm_device *dev = crtc->dev; |
| 5450 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5451 | int refclk; |
| 5452 | |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5453 | if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 9a0ea49 | 2013-09-16 11:29:34 +0200 | [diff] [blame] | 5454 | refclk = 100000; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5455 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5456 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 5457 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 5458 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5459 | } else if (!IS_GEN2(dev)) { |
| 5460 | refclk = 96000; |
| 5461 | } else { |
| 5462 | refclk = 48000; |
| 5463 | } |
| 5464 | |
| 5465 | return refclk; |
| 5466 | } |
| 5467 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5468 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5469 | { |
Daniel Vetter | 7df00d7 | 2013-05-21 21:54:55 +0200 | [diff] [blame] | 5470 | return (1 << dpll->n) << 16 | dpll->m2; |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5471 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5472 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5473 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
| 5474 | { |
| 5475 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5476 | } |
| 5477 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5478 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5479 | intel_clock_t *reduced_clock) |
| 5480 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5481 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5482 | u32 fp, fp2 = 0; |
| 5483 | |
| 5484 | if (IS_PINEVIEW(dev)) { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5485 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5486 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5487 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5488 | } else { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5489 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5490 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5491 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5492 | } |
| 5493 | |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5494 | crtc->config.dpll_hw_state.fp0 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5495 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5496 | crtc->lowfreq_avail = false; |
| 5497 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 5498 | reduced_clock && i915.powersave) { |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5499 | crtc->config.dpll_hw_state.fp1 = fp2; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5500 | crtc->lowfreq_avail = true; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5501 | } else { |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5502 | crtc->config.dpll_hw_state.fp1 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5503 | } |
| 5504 | } |
| 5505 | |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 5506 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
| 5507 | pipe) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5508 | { |
| 5509 | u32 reg_val; |
| 5510 | |
| 5511 | /* |
| 5512 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
| 5513 | * and set it to a reasonable value instead. |
| 5514 | */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5515 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5516 | reg_val &= 0xffffff00; |
| 5517 | reg_val |= 0x00000030; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5518 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5519 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5520 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5521 | reg_val &= 0x8cffffff; |
| 5522 | reg_val = 0x8c000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5523 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5524 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5525 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5526 | reg_val &= 0xffffff00; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5527 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5528 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5529 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5530 | reg_val &= 0x00ffffff; |
| 5531 | reg_val |= 0xb0000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5532 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5533 | } |
| 5534 | |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5535 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
| 5536 | struct intel_link_m_n *m_n) |
| 5537 | { |
| 5538 | struct drm_device *dev = crtc->base.dev; |
| 5539 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5540 | int pipe = crtc->pipe; |
| 5541 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 5542 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 5543 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
| 5544 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
| 5545 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5546 | } |
| 5547 | |
| 5548 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 5549 | struct intel_link_m_n *m_n, |
| 5550 | struct intel_link_m_n *m2_n2) |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5551 | { |
| 5552 | struct drm_device *dev = crtc->base.dev; |
| 5553 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5554 | int pipe = crtc->pipe; |
| 5555 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
| 5556 | |
| 5557 | if (INTEL_INFO(dev)->gen >= 5) { |
| 5558 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 5559 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
| 5560 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
| 5561 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 5562 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
| 5563 | * for gen < 8) and if DRRS is supported (to make sure the |
| 5564 | * registers are not unnecessarily accessed). |
| 5565 | */ |
| 5566 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
| 5567 | crtc->config.has_drrs) { |
| 5568 | I915_WRITE(PIPE_DATA_M2(transcoder), |
| 5569 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); |
| 5570 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); |
| 5571 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); |
| 5572 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); |
| 5573 | } |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5574 | } else { |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 5575 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 5576 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
| 5577 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
| 5578 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5579 | } |
| 5580 | } |
| 5581 | |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 5582 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 5583 | { |
| 5584 | if (crtc->config.has_pch_encoder) |
| 5585 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
| 5586 | else |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 5587 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
| 5588 | &crtc->config.dp_m2_n2); |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 5589 | } |
| 5590 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5591 | static void vlv_update_pll(struct intel_crtc *crtc) |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5592 | { |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 5593 | u32 dpll, dpll_md; |
| 5594 | |
| 5595 | /* |
| 5596 | * Enable DPIO clock input. We should never disable the reference |
| 5597 | * clock for pipe B, since VGA hotplug / manual detection depends |
| 5598 | * on it. |
| 5599 | */ |
| 5600 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
| 5601 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
| 5602 | /* We should never disable this, set it here for state tracking */ |
| 5603 | if (crtc->pipe == PIPE_B) |
| 5604 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 5605 | dpll |= DPLL_VCO_ENABLE; |
| 5606 | crtc->config.dpll_hw_state.dpll = dpll; |
| 5607 | |
| 5608 | dpll_md = (crtc->config.pixel_multiplier - 1) |
| 5609 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 5610 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
| 5611 | } |
| 5612 | |
| 5613 | static void vlv_prepare_pll(struct intel_crtc *crtc) |
| 5614 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5615 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5616 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5617 | int pipe = crtc->pipe; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 5618 | u32 mdiv; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5619 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 5620 | u32 coreclk, reg_val; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5621 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 5622 | mutex_lock(&dev_priv->dpio_lock); |
| 5623 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5624 | bestn = crtc->config.dpll.n; |
| 5625 | bestm1 = crtc->config.dpll.m1; |
| 5626 | bestm2 = crtc->config.dpll.m2; |
| 5627 | bestp1 = crtc->config.dpll.p1; |
| 5628 | bestp2 = crtc->config.dpll.p2; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5629 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5630 | /* See eDP HDMI DPIO driver vbios notes doc */ |
| 5631 | |
| 5632 | /* PLL B needs special handling */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 5633 | if (pipe == PIPE_B) |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 5634 | vlv_pllb_recal_opamp(dev_priv, pipe); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5635 | |
| 5636 | /* Set up Tx target for periodic Rcomp update */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5637 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5638 | |
| 5639 | /* Disable target IRef on PLL */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5640 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5641 | reg_val &= 0x00ffffff; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5642 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5643 | |
| 5644 | /* Disable fast lock */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5645 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5646 | |
| 5647 | /* Set idtafcrecal before PLL is enabled */ |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5648 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
| 5649 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
| 5650 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5651 | mdiv |= (1 << DPIO_K_SHIFT); |
Jesse Barnes | 7df5080 | 2013-05-02 10:48:09 -0700 | [diff] [blame] | 5652 | |
| 5653 | /* |
| 5654 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| 5655 | * but we don't support that). |
| 5656 | * Note: don't use the DAC post divider as it seems unstable. |
| 5657 | */ |
| 5658 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5659 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5660 | |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5661 | mdiv |= DPIO_ENABLE_CALIBRATION; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5662 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5663 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5664 | /* Set HBR and RBR LPF coefficients */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 5665 | if (crtc->config.port_clock == 162000 || |
Ville Syrjälä | 99750bd | 2013-06-14 14:02:52 +0300 | [diff] [blame] | 5666 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5667 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5668 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Ville Syrjälä | 885b0120 | 2013-07-05 19:21:38 +0300 | [diff] [blame] | 5669 | 0x009f0003); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5670 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5671 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5672 | 0x00d0000f); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5673 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5674 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
| 5675 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
| 5676 | /* Use SSC source */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 5677 | if (pipe == PIPE_A) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5678 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5679 | 0x0df40000); |
| 5680 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5681 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5682 | 0x0df70000); |
| 5683 | } else { /* HDMI or VGA */ |
| 5684 | /* Use bend source */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 5685 | if (pipe == PIPE_A) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5686 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5687 | 0x0df70000); |
| 5688 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5689 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5690 | 0x0df40000); |
| 5691 | } |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5692 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5693 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5694 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
| 5695 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
| 5696 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
| 5697 | coreclk |= 0x01000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5698 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5699 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5700 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 5701 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5702 | } |
| 5703 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 5704 | static void chv_update_pll(struct intel_crtc *crtc) |
| 5705 | { |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 5706 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
| 5707 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
| 5708 | DPLL_VCO_ENABLE; |
| 5709 | if (crtc->pipe != PIPE_A) |
| 5710 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 5711 | |
| 5712 | crtc->config.dpll_hw_state.dpll_md = |
| 5713 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 5714 | } |
| 5715 | |
| 5716 | static void chv_prepare_pll(struct intel_crtc *crtc) |
| 5717 | { |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 5718 | struct drm_device *dev = crtc->base.dev; |
| 5719 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5720 | int pipe = crtc->pipe; |
| 5721 | int dpll_reg = DPLL(crtc->pipe); |
| 5722 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 5723 | u32 loopfilter, intcoeff; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 5724 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
| 5725 | int refclk; |
| 5726 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 5727 | bestn = crtc->config.dpll.n; |
| 5728 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; |
| 5729 | bestm1 = crtc->config.dpll.m1; |
| 5730 | bestm2 = crtc->config.dpll.m2 >> 22; |
| 5731 | bestp1 = crtc->config.dpll.p1; |
| 5732 | bestp2 = crtc->config.dpll.p2; |
| 5733 | |
| 5734 | /* |
| 5735 | * Enable Refclk and SSC |
| 5736 | */ |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 5737 | I915_WRITE(dpll_reg, |
| 5738 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
| 5739 | |
| 5740 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 5741 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 5742 | /* p1 and p2 divider */ |
| 5743 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
| 5744 | 5 << DPIO_CHV_S1_DIV_SHIFT | |
| 5745 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | |
| 5746 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | |
| 5747 | 1 << DPIO_CHV_K_DIV_SHIFT); |
| 5748 | |
| 5749 | /* Feedback post-divider - m2 */ |
| 5750 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); |
| 5751 | |
| 5752 | /* Feedback refclk divider - n and m1 */ |
| 5753 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), |
| 5754 | DPIO_CHV_M1_DIV_BY_2 | |
| 5755 | 1 << DPIO_CHV_N_DIV_SHIFT); |
| 5756 | |
| 5757 | /* M2 fraction division */ |
| 5758 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
| 5759 | |
| 5760 | /* M2 fraction division enable */ |
| 5761 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), |
| 5762 | DPIO_CHV_FRAC_DIV_EN | |
| 5763 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); |
| 5764 | |
| 5765 | /* Loop filter */ |
| 5766 | refclk = i9xx_get_refclk(&crtc->base, 0); |
| 5767 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
| 5768 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; |
| 5769 | if (refclk == 100000) |
| 5770 | intcoeff = 11; |
| 5771 | else if (refclk == 38400) |
| 5772 | intcoeff = 10; |
| 5773 | else |
| 5774 | intcoeff = 9; |
| 5775 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; |
| 5776 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
| 5777 | |
| 5778 | /* AFC Recal */ |
| 5779 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
| 5780 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
| 5781 | DPIO_AFC_RECAL); |
| 5782 | |
| 5783 | mutex_unlock(&dev_priv->dpio_lock); |
| 5784 | } |
| 5785 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5786 | static void i9xx_update_pll(struct intel_crtc *crtc, |
| 5787 | intel_clock_t *reduced_clock, |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5788 | int num_connectors) |
| 5789 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5790 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5791 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5792 | u32 dpll; |
| 5793 | bool is_sdvo; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5794 | struct dpll *clock = &crtc->config.dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5795 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5796 | i9xx_update_pll_dividers(crtc, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 5797 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5798 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
| 5799 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5800 | |
| 5801 | dpll = DPLL_VGA_MODE_DIS; |
| 5802 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5803 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5804 | dpll |= DPLLB_MODE_LVDS; |
| 5805 | else |
| 5806 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 5807 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 5808 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5809 | dpll |= (crtc->config.pixel_multiplier - 1) |
| 5810 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5811 | } |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5812 | |
| 5813 | if (is_sdvo) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 5814 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5815 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5816 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 5817 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5818 | |
| 5819 | /* compute bitmask from p1 value */ |
| 5820 | if (IS_PINEVIEW(dev)) |
| 5821 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 5822 | else { |
| 5823 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5824 | if (IS_G4X(dev) && reduced_clock) |
| 5825 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 5826 | } |
| 5827 | switch (clock->p2) { |
| 5828 | case 5: |
| 5829 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 5830 | break; |
| 5831 | case 7: |
| 5832 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 5833 | break; |
| 5834 | case 10: |
| 5835 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 5836 | break; |
| 5837 | case 14: |
| 5838 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 5839 | break; |
| 5840 | } |
| 5841 | if (INTEL_INFO(dev)->gen >= 4) |
| 5842 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 5843 | |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 5844 | if (crtc->config.sdvo_tv_clock) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5845 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5846 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5847 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 5848 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 5849 | else |
| 5850 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 5851 | |
| 5852 | dpll |= DPLL_VCO_ENABLE; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5853 | crtc->config.dpll_hw_state.dpll = dpll; |
| 5854 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5855 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 5856 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
| 5857 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5858 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5859 | } |
| 5860 | } |
| 5861 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5862 | static void i8xx_update_pll(struct intel_crtc *crtc, |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5863 | intel_clock_t *reduced_clock, |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5864 | int num_connectors) |
| 5865 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5866 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5867 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5868 | u32 dpll; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5869 | struct dpll *clock = &crtc->config.dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5870 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5871 | i9xx_update_pll_dividers(crtc, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 5872 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5873 | dpll = DPLL_VGA_MODE_DIS; |
| 5874 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5875 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5876 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5877 | } else { |
| 5878 | if (clock->p1 == 2) |
| 5879 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 5880 | else |
| 5881 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5882 | if (clock->p2 == 4) |
| 5883 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 5884 | } |
| 5885 | |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 5886 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
| 5887 | dpll |= DPLL_DVO_2X_MODE; |
| 5888 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5889 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5890 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 5891 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 5892 | else |
| 5893 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 5894 | |
| 5895 | dpll |= DPLL_VCO_ENABLE; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5896 | crtc->config.dpll_hw_state.dpll = dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5897 | } |
| 5898 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 5899 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5900 | { |
| 5901 | struct drm_device *dev = intel_crtc->base.dev; |
| 5902 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5903 | enum pipe pipe = intel_crtc->pipe; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 5904 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 5905 | struct drm_display_mode *adjusted_mode = |
| 5906 | &intel_crtc->config.adjusted_mode; |
Ville Syrjälä | 1caea6e | 2014-03-28 23:29:32 +0200 | [diff] [blame] | 5907 | uint32_t crtc_vtotal, crtc_vblank_end; |
| 5908 | int vsyncshift = 0; |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5909 | |
| 5910 | /* We need to be careful not to changed the adjusted mode, for otherwise |
| 5911 | * the hw state checker will get angry at the mismatch. */ |
| 5912 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
| 5913 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5914 | |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 5915 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5916 | /* the chip adds 2 halflines automatically */ |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5917 | crtc_vtotal -= 1; |
| 5918 | crtc_vblank_end -= 1; |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 5919 | |
| 5920 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
| 5921 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
| 5922 | else |
| 5923 | vsyncshift = adjusted_mode->crtc_hsync_start - |
| 5924 | adjusted_mode->crtc_htotal / 2; |
Ville Syrjälä | 1caea6e | 2014-03-28 23:29:32 +0200 | [diff] [blame] | 5925 | if (vsyncshift < 0) |
| 5926 | vsyncshift += adjusted_mode->crtc_htotal; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5927 | } |
| 5928 | |
| 5929 | if (INTEL_INFO(dev)->gen > 3) |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5930 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5931 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5932 | I915_WRITE(HTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5933 | (adjusted_mode->crtc_hdisplay - 1) | |
| 5934 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5935 | I915_WRITE(HBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5936 | (adjusted_mode->crtc_hblank_start - 1) | |
| 5937 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5938 | I915_WRITE(HSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5939 | (adjusted_mode->crtc_hsync_start - 1) | |
| 5940 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 5941 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5942 | I915_WRITE(VTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5943 | (adjusted_mode->crtc_vdisplay - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5944 | ((crtc_vtotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5945 | I915_WRITE(VBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5946 | (adjusted_mode->crtc_vblank_start - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5947 | ((crtc_vblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5948 | I915_WRITE(VSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5949 | (adjusted_mode->crtc_vsync_start - 1) | |
| 5950 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 5951 | |
Paulo Zanoni | b5e508d | 2012-10-24 11:34:43 -0200 | [diff] [blame] | 5952 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
| 5953 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
| 5954 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
| 5955 | * bits. */ |
| 5956 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
| 5957 | (pipe == PIPE_B || pipe == PIPE_C)) |
| 5958 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
| 5959 | |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5960 | /* pipesrc controls the size that is scaled from, which should |
| 5961 | * always be the user's requested size. |
| 5962 | */ |
| 5963 | I915_WRITE(PIPESRC(pipe), |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 5964 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
| 5965 | (intel_crtc->config.pipe_src_h - 1)); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5966 | } |
| 5967 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 5968 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
| 5969 | struct intel_crtc_config *pipe_config) |
| 5970 | { |
| 5971 | struct drm_device *dev = crtc->base.dev; |
| 5972 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5973 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 5974 | uint32_t tmp; |
| 5975 | |
| 5976 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
| 5977 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
| 5978 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
| 5979 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
| 5980 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
| 5981 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
| 5982 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
| 5983 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
| 5984 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 5985 | |
| 5986 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
| 5987 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
| 5988 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
| 5989 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
| 5990 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
| 5991 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
| 5992 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
| 5993 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
| 5994 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 5995 | |
| 5996 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
| 5997 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 5998 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
| 5999 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
| 6000 | } |
| 6001 | |
| 6002 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 6003 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
| 6004 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
| 6005 | |
| 6006 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
| 6007 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 6008 | } |
| 6009 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 6010 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 6011 | struct intel_crtc_config *pipe_config) |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 6012 | { |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 6013 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
| 6014 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; |
| 6015 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
| 6016 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 6017 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 6018 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
| 6019 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
| 6020 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
| 6021 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 6022 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 6023 | mode->flags = pipe_config->adjusted_mode.flags; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 6024 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 6025 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
| 6026 | mode->flags |= pipe_config->adjusted_mode.flags; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 6027 | } |
| 6028 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6029 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
| 6030 | { |
| 6031 | struct drm_device *dev = intel_crtc->base.dev; |
| 6032 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6033 | uint32_t pipeconf; |
| 6034 | |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 6035 | pipeconf = 0; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6036 | |
Daniel Vetter | 67c72a1 | 2013-09-24 11:46:14 +0200 | [diff] [blame] | 6037 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 6038 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
| 6039 | pipeconf |= PIPECONF_ENABLE; |
| 6040 | |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 6041 | if (intel_crtc->config.double_wide) |
| 6042 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6043 | |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 6044 | /* only g4x and later have fancy bpc/dither controls */ |
| 6045 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 6046 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
| 6047 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
| 6048 | pipeconf |= PIPECONF_DITHER_EN | |
| 6049 | PIPECONF_DITHER_TYPE_SP; |
| 6050 | |
| 6051 | switch (intel_crtc->config.pipe_bpp) { |
| 6052 | case 18: |
| 6053 | pipeconf |= PIPECONF_6BPC; |
| 6054 | break; |
| 6055 | case 24: |
| 6056 | pipeconf |= PIPECONF_8BPC; |
| 6057 | break; |
| 6058 | case 30: |
| 6059 | pipeconf |= PIPECONF_10BPC; |
| 6060 | break; |
| 6061 | default: |
| 6062 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 6063 | BUG(); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6064 | } |
| 6065 | } |
| 6066 | |
| 6067 | if (HAS_PIPE_CXSR(dev)) { |
| 6068 | if (intel_crtc->lowfreq_avail) { |
| 6069 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 6070 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 6071 | } else { |
| 6072 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6073 | } |
| 6074 | } |
| 6075 | |
Ville Syrjälä | efc2cff | 2014-03-28 23:29:31 +0200 | [diff] [blame] | 6076 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
| 6077 | if (INTEL_INFO(dev)->gen < 4 || |
| 6078 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
| 6079 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 6080 | else |
| 6081 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
| 6082 | } else |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6083 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 6084 | |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 6085 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
| 6086 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 9c8e09b | 2013-04-02 16:10:09 +0300 | [diff] [blame] | 6087 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 6088 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
| 6089 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
| 6090 | } |
| 6091 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6092 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6093 | int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 6094 | struct drm_framebuffer *fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6095 | { |
| 6096 | struct drm_device *dev = crtc->dev; |
| 6097 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 6099 | int refclk, num_connectors = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6100 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | a16af72 | 2013-04-30 14:01:44 +0200 | [diff] [blame] | 6101 | bool ok, has_reduced_clock = false; |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6102 | bool is_lvds = false, is_dsi = false; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6103 | struct intel_encoder *encoder; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 6104 | const intel_limit_t *limit; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6105 | |
Daniel Vetter | 6c2b7c1 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 6106 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6107 | switch (encoder->type) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6108 | case INTEL_OUTPUT_LVDS: |
| 6109 | is_lvds = true; |
| 6110 | break; |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6111 | case INTEL_OUTPUT_DSI: |
| 6112 | is_dsi = true; |
| 6113 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6114 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 6115 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 6116 | num_connectors++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6117 | } |
| 6118 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 6119 | if (is_dsi) |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6120 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6121 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 6122 | if (!intel_crtc->config.clock_set) { |
| 6123 | refclk = i9xx_get_refclk(crtc, num_connectors); |
| 6124 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6125 | /* |
| 6126 | * Returns a set of divisors for the desired target clock with |
| 6127 | * the given refclk, or FALSE. The returned values represent |
| 6128 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
| 6129 | * 2) / p1 / p2. |
| 6130 | */ |
| 6131 | limit = intel_limit(crtc, refclk); |
| 6132 | ok = dev_priv->display.find_dpll(limit, crtc, |
| 6133 | intel_crtc->config.port_clock, |
| 6134 | refclk, NULL, &clock); |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 6135 | if (!ok) { |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6136 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 6137 | return -EINVAL; |
| 6138 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6139 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 6140 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
| 6141 | /* |
| 6142 | * Ensure we match the reduced clock's P to the target |
| 6143 | * clock. If the clocks don't match, we can't switch |
| 6144 | * the display clock by using the FP0/FP1. In such case |
| 6145 | * we will disable the LVDS downclock feature. |
| 6146 | */ |
| 6147 | has_reduced_clock = |
| 6148 | dev_priv->display.find_dpll(limit, crtc, |
| 6149 | dev_priv->lvds_downclock, |
| 6150 | refclk, &clock, |
| 6151 | &reduced_clock); |
| 6152 | } |
| 6153 | /* Compat-code for transition, will disappear. */ |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 6154 | intel_crtc->config.dpll.n = clock.n; |
| 6155 | intel_crtc->config.dpll.m1 = clock.m1; |
| 6156 | intel_crtc->config.dpll.m2 = clock.m2; |
| 6157 | intel_crtc->config.dpll.p1 = clock.p1; |
| 6158 | intel_crtc->config.dpll.p2 = clock.p2; |
| 6159 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6160 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6161 | if (IS_GEN2(dev)) { |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 6162 | i8xx_update_pll(intel_crtc, |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 6163 | has_reduced_clock ? &reduced_clock : NULL, |
| 6164 | num_connectors); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 6165 | } else if (IS_CHERRYVIEW(dev)) { |
| 6166 | chv_update_pll(intel_crtc); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6167 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 6168 | vlv_update_pll(intel_crtc); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6169 | } else { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 6170 | i9xx_update_pll(intel_crtc, |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 6171 | has_reduced_clock ? &reduced_clock : NULL, |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 6172 | num_connectors); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 6173 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6174 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 6175 | return 0; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6176 | } |
| 6177 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6178 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
| 6179 | struct intel_crtc_config *pipe_config) |
| 6180 | { |
| 6181 | struct drm_device *dev = crtc->base.dev; |
| 6182 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6183 | uint32_t tmp; |
| 6184 | |
Ville Syrjälä | dc9e7dec | 2014-01-10 14:06:45 +0200 | [diff] [blame] | 6185 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
| 6186 | return; |
| 6187 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6188 | tmp = I915_READ(PFIT_CONTROL); |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 6189 | if (!(tmp & PFIT_ENABLE)) |
| 6190 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6191 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 6192 | /* Check whether the pfit is attached to our pipe. */ |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6193 | if (INTEL_INFO(dev)->gen < 4) { |
| 6194 | if (crtc->pipe != PIPE_B) |
| 6195 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6196 | } else { |
| 6197 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
| 6198 | return; |
| 6199 | } |
| 6200 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 6201 | pipe_config->gmch_pfit.control = tmp; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6202 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
| 6203 | if (INTEL_INFO(dev)->gen < 5) |
| 6204 | pipe_config->gmch_pfit.lvds_border_bits = |
| 6205 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
| 6206 | } |
| 6207 | |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6208 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
| 6209 | struct intel_crtc_config *pipe_config) |
| 6210 | { |
| 6211 | struct drm_device *dev = crtc->base.dev; |
| 6212 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6213 | int pipe = pipe_config->cpu_transcoder; |
| 6214 | intel_clock_t clock; |
| 6215 | u32 mdiv; |
Chris Wilson | 662c6ec | 2013-09-25 14:24:01 -0700 | [diff] [blame] | 6216 | int refclk = 100000; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6217 | |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 6218 | /* In case of MIPI DPLL will not even be used */ |
| 6219 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) |
| 6220 | return; |
| 6221 | |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6222 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 6223 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6224 | mutex_unlock(&dev_priv->dpio_lock); |
| 6225 | |
| 6226 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
| 6227 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
| 6228 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
| 6229 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
| 6230 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
| 6231 | |
Ville Syrjälä | f646628 | 2013-10-14 14:50:31 +0300 | [diff] [blame] | 6232 | vlv_clock(refclk, &clock); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6233 | |
Ville Syrjälä | f646628 | 2013-10-14 14:50:31 +0300 | [diff] [blame] | 6234 | /* clock.dot is the fast clock */ |
| 6235 | pipe_config->port_clock = clock.dot / 5; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6236 | } |
| 6237 | |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6238 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
| 6239 | struct intel_plane_config *plane_config) |
| 6240 | { |
| 6241 | struct drm_device *dev = crtc->base.dev; |
| 6242 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6243 | u32 val, base, offset; |
| 6244 | int pipe = crtc->pipe, plane = crtc->plane; |
| 6245 | int fourcc, pixel_format; |
| 6246 | int aligned_height; |
| 6247 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 6248 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
| 6249 | if (!crtc->base.primary->fb) { |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6250 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 6251 | return; |
| 6252 | } |
| 6253 | |
| 6254 | val = I915_READ(DSPCNTR(plane)); |
| 6255 | |
| 6256 | if (INTEL_INFO(dev)->gen >= 4) |
| 6257 | if (val & DISPPLANE_TILED) |
| 6258 | plane_config->tiled = true; |
| 6259 | |
| 6260 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
| 6261 | fourcc = intel_format_to_fourcc(pixel_format); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 6262 | crtc->base.primary->fb->pixel_format = fourcc; |
| 6263 | crtc->base.primary->fb->bits_per_pixel = |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6264 | drm_format_plane_cpp(fourcc, 0) * 8; |
| 6265 | |
| 6266 | if (INTEL_INFO(dev)->gen >= 4) { |
| 6267 | if (plane_config->tiled) |
| 6268 | offset = I915_READ(DSPTILEOFF(plane)); |
| 6269 | else |
| 6270 | offset = I915_READ(DSPLINOFF(plane)); |
| 6271 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 6272 | } else { |
| 6273 | base = I915_READ(DSPADDR(plane)); |
| 6274 | } |
| 6275 | plane_config->base = base; |
| 6276 | |
| 6277 | val = I915_READ(PIPESRC(pipe)); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 6278 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
| 6279 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6280 | |
| 6281 | val = I915_READ(DSPSTRIDE(pipe)); |
Rafael Barbalho | 026b96e | 2014-07-28 19:56:27 +0100 | [diff] [blame] | 6282 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6283 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 6284 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6285 | plane_config->tiled); |
| 6286 | |
Fabian Frederick | 1267a26 | 2014-07-01 20:39:41 +0200 | [diff] [blame] | 6287 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
| 6288 | aligned_height); |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6289 | |
| 6290 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 6291 | pipe, plane, crtc->base.primary->fb->width, |
| 6292 | crtc->base.primary->fb->height, |
| 6293 | crtc->base.primary->fb->bits_per_pixel, base, |
| 6294 | crtc->base.primary->fb->pitches[0], |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 6295 | plane_config->size); |
| 6296 | |
| 6297 | } |
| 6298 | |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 6299 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
| 6300 | struct intel_crtc_config *pipe_config) |
| 6301 | { |
| 6302 | struct drm_device *dev = crtc->base.dev; |
| 6303 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6304 | int pipe = pipe_config->cpu_transcoder; |
| 6305 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 6306 | intel_clock_t clock; |
| 6307 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; |
| 6308 | int refclk = 100000; |
| 6309 | |
| 6310 | mutex_lock(&dev_priv->dpio_lock); |
| 6311 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
| 6312 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
| 6313 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
| 6314 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
| 6315 | mutex_unlock(&dev_priv->dpio_lock); |
| 6316 | |
| 6317 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
| 6318 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); |
| 6319 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
| 6320 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
| 6321 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
| 6322 | |
| 6323 | chv_clock(refclk, &clock); |
| 6324 | |
| 6325 | /* clock.dot is the fast clock */ |
| 6326 | pipe_config->port_clock = clock.dot / 5; |
| 6327 | } |
| 6328 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 6329 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
| 6330 | struct intel_crtc_config *pipe_config) |
| 6331 | { |
| 6332 | struct drm_device *dev = crtc->base.dev; |
| 6333 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6334 | uint32_t tmp; |
| 6335 | |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 6336 | if (!intel_display_power_enabled(dev_priv, |
| 6337 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 6338 | return false; |
| 6339 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 6340 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 6341 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 6342 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 6343 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 6344 | if (!(tmp & PIPECONF_ENABLE)) |
| 6345 | return false; |
| 6346 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 6347 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
| 6348 | switch (tmp & PIPECONF_BPC_MASK) { |
| 6349 | case PIPECONF_6BPC: |
| 6350 | pipe_config->pipe_bpp = 18; |
| 6351 | break; |
| 6352 | case PIPECONF_8BPC: |
| 6353 | pipe_config->pipe_bpp = 24; |
| 6354 | break; |
| 6355 | case PIPECONF_10BPC: |
| 6356 | pipe_config->pipe_bpp = 30; |
| 6357 | break; |
| 6358 | default: |
| 6359 | break; |
| 6360 | } |
| 6361 | } |
| 6362 | |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 6363 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
| 6364 | pipe_config->limited_color_range = true; |
| 6365 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 6366 | if (INTEL_INFO(dev)->gen < 4) |
| 6367 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
| 6368 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 6369 | intel_get_pipe_timings(crtc, pipe_config); |
| 6370 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6371 | i9xx_get_pfit_config(crtc, pipe_config); |
| 6372 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 6373 | if (INTEL_INFO(dev)->gen >= 4) { |
| 6374 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
| 6375 | pipe_config->pixel_multiplier = |
| 6376 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
| 6377 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 6378 | pipe_config->dpll_hw_state.dpll_md = tmp; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 6379 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 6380 | tmp = I915_READ(DPLL(crtc->pipe)); |
| 6381 | pipe_config->pixel_multiplier = |
| 6382 | ((tmp & SDVO_MULTIPLIER_MASK) |
| 6383 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
| 6384 | } else { |
| 6385 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
| 6386 | * port and will be fixed up in the encoder->get_config |
| 6387 | * function. */ |
| 6388 | pipe_config->pixel_multiplier = 1; |
| 6389 | } |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 6390 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
| 6391 | if (!IS_VALLEYVIEW(dev)) { |
| 6392 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
| 6393 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
Ville Syrjälä | 165e901 | 2013-06-26 17:44:15 +0300 | [diff] [blame] | 6394 | } else { |
| 6395 | /* Mask out read-only status bits. */ |
| 6396 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
| 6397 | DPLL_PORTC_READY_MASK | |
| 6398 | DPLL_PORTB_READY_MASK); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 6399 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 6400 | |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 6401 | if (IS_CHERRYVIEW(dev)) |
| 6402 | chv_crtc_clock_get(crtc, pipe_config); |
| 6403 | else if (IS_VALLEYVIEW(dev)) |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 6404 | vlv_crtc_clock_get(crtc, pipe_config); |
| 6405 | else |
| 6406 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 6407 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 6408 | return true; |
| 6409 | } |
| 6410 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6411 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6412 | { |
| 6413 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6414 | struct intel_encoder *encoder; |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6415 | u32 val, final; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6416 | bool has_lvds = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6417 | bool has_cpu_edp = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6418 | bool has_panel = false; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6419 | bool has_ck505 = false; |
| 6420 | bool can_ssc = false; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6421 | |
| 6422 | /* We need to take the global config into account */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 6423 | for_each_intel_encoder(dev, encoder) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6424 | switch (encoder->type) { |
| 6425 | case INTEL_OUTPUT_LVDS: |
| 6426 | has_panel = true; |
| 6427 | has_lvds = true; |
| 6428 | break; |
| 6429 | case INTEL_OUTPUT_EDP: |
| 6430 | has_panel = true; |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 6431 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6432 | has_cpu_edp = true; |
| 6433 | break; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6434 | } |
| 6435 | } |
| 6436 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6437 | if (HAS_PCH_IBX(dev)) { |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 6438 | has_ck505 = dev_priv->vbt.display_clock_mode; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6439 | can_ssc = has_ck505; |
| 6440 | } else { |
| 6441 | has_ck505 = false; |
| 6442 | can_ssc = true; |
| 6443 | } |
| 6444 | |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 6445 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
| 6446 | has_panel, has_lvds, has_ck505); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6447 | |
| 6448 | /* Ironlake: try to setup display ref clock before DPLL |
| 6449 | * enabling. This is only under driver's control after |
| 6450 | * PCH B stepping, previous chipset stepping should be |
| 6451 | * ignoring this setting. |
| 6452 | */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6453 | val = I915_READ(PCH_DREF_CONTROL); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6454 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6455 | /* As we must carefully and slowly disable/enable each source in turn, |
| 6456 | * compute the final state we want first and check if we need to |
| 6457 | * make any changes at all. |
| 6458 | */ |
| 6459 | final = val; |
| 6460 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6461 | if (has_ck505) |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6462 | final |= DREF_NONSPREAD_CK505_ENABLE; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6463 | else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6464 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 6465 | |
| 6466 | final &= ~DREF_SSC_SOURCE_MASK; |
| 6467 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 6468 | final &= ~DREF_SSC1_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6469 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6470 | if (has_panel) { |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6471 | final |= DREF_SSC_SOURCE_ENABLE; |
| 6472 | |
| 6473 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 6474 | final |= DREF_SSC1_ENABLE; |
| 6475 | |
| 6476 | if (has_cpu_edp) { |
| 6477 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 6478 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 6479 | else |
| 6480 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 6481 | } else |
| 6482 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 6483 | } else { |
| 6484 | final |= DREF_SSC_SOURCE_DISABLE; |
| 6485 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 6486 | } |
| 6487 | |
| 6488 | if (final == val) |
| 6489 | return; |
| 6490 | |
| 6491 | /* Always enable nonspread source */ |
| 6492 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 6493 | |
| 6494 | if (has_ck505) |
| 6495 | val |= DREF_NONSPREAD_CK505_ENABLE; |
| 6496 | else |
| 6497 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 6498 | |
| 6499 | if (has_panel) { |
| 6500 | val &= ~DREF_SSC_SOURCE_MASK; |
| 6501 | val |= DREF_SSC_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6502 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6503 | /* SSC must be turned on before enabling the CPU output */ |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6504 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6505 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6506 | val |= DREF_SSC1_ENABLE; |
Daniel Vetter | e77166b | 2012-03-30 22:14:05 +0200 | [diff] [blame] | 6507 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6508 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6509 | |
| 6510 | /* Get SSC going before enabling the outputs */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6511 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6512 | POSTING_READ(PCH_DREF_CONTROL); |
| 6513 | udelay(200); |
| 6514 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6515 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6516 | |
| 6517 | /* Enable CPU source on CPU attached eDP */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6518 | if (has_cpu_edp) { |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 6519 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6520 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6521 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 6522 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6523 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6524 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6525 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6526 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6527 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6528 | POSTING_READ(PCH_DREF_CONTROL); |
| 6529 | udelay(200); |
| 6530 | } else { |
| 6531 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
| 6532 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6533 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6534 | |
| 6535 | /* Turn off CPU output */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6536 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6537 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6538 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6539 | POSTING_READ(PCH_DREF_CONTROL); |
| 6540 | udelay(200); |
| 6541 | |
| 6542 | /* Turn off the SSC source */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6543 | val &= ~DREF_SSC_SOURCE_MASK; |
| 6544 | val |= DREF_SSC_SOURCE_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6545 | |
| 6546 | /* Turn off SSC1 */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6547 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 6548 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6549 | I915_WRITE(PCH_DREF_CONTROL, val); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6550 | POSTING_READ(PCH_DREF_CONTROL); |
| 6551 | udelay(200); |
| 6552 | } |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6553 | |
| 6554 | BUG_ON(val != final); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6555 | } |
| 6556 | |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6557 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6558 | { |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6559 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6560 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6561 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 6562 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
| 6563 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6564 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6565 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
| 6566 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
| 6567 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6568 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6569 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 6570 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
| 6571 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6572 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6573 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
| 6574 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
| 6575 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6576 | } |
| 6577 | |
| 6578 | /* WaMPhyProgramming:hsw */ |
| 6579 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
| 6580 | { |
| 6581 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6582 | |
| 6583 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
| 6584 | tmp &= ~(0xFF << 24); |
| 6585 | tmp |= (0x12 << 24); |
| 6586 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
| 6587 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6588 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
| 6589 | tmp |= (1 << 11); |
| 6590 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
| 6591 | |
| 6592 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
| 6593 | tmp |= (1 << 11); |
| 6594 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
| 6595 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6596 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
| 6597 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 6598 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
| 6599 | |
| 6600 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
| 6601 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 6602 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
| 6603 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6604 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
| 6605 | tmp &= ~(7 << 13); |
| 6606 | tmp |= (5 << 13); |
| 6607 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6608 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6609 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
| 6610 | tmp &= ~(7 << 13); |
| 6611 | tmp |= (5 << 13); |
| 6612 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6613 | |
| 6614 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
| 6615 | tmp &= ~0xFF; |
| 6616 | tmp |= 0x1C; |
| 6617 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
| 6618 | |
| 6619 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
| 6620 | tmp &= ~0xFF; |
| 6621 | tmp |= 0x1C; |
| 6622 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
| 6623 | |
| 6624 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
| 6625 | tmp &= ~(0xFF << 16); |
| 6626 | tmp |= (0x1C << 16); |
| 6627 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
| 6628 | |
| 6629 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
| 6630 | tmp &= ~(0xFF << 16); |
| 6631 | tmp |= (0x1C << 16); |
| 6632 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
| 6633 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6634 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
| 6635 | tmp |= (1 << 27); |
| 6636 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6637 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6638 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
| 6639 | tmp |= (1 << 27); |
| 6640 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6641 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6642 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
| 6643 | tmp &= ~(0xF << 28); |
| 6644 | tmp |= (4 << 28); |
| 6645 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6646 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6647 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
| 6648 | tmp &= ~(0xF << 28); |
| 6649 | tmp |= (4 << 28); |
| 6650 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6651 | } |
| 6652 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6653 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
| 6654 | * Programming" based on the parameters passed: |
| 6655 | * - Sequence to enable CLKOUT_DP |
| 6656 | * - Sequence to enable CLKOUT_DP without spread |
| 6657 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
| 6658 | */ |
| 6659 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
| 6660 | bool with_fdi) |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6661 | { |
| 6662 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6663 | uint32_t reg, tmp; |
| 6664 | |
| 6665 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
| 6666 | with_spread = true; |
| 6667 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
| 6668 | with_fdi, "LP PCH doesn't have FDI\n")) |
| 6669 | with_fdi = false; |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6670 | |
| 6671 | mutex_lock(&dev_priv->dpio_lock); |
| 6672 | |
| 6673 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 6674 | tmp &= ~SBI_SSCCTL_DISABLE; |
| 6675 | tmp |= SBI_SSCCTL_PATHALT; |
| 6676 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 6677 | |
| 6678 | udelay(24); |
| 6679 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6680 | if (with_spread) { |
| 6681 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 6682 | tmp &= ~SBI_SSCCTL_PATHALT; |
| 6683 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6684 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6685 | if (with_fdi) { |
| 6686 | lpt_reset_fdi_mphy(dev_priv); |
| 6687 | lpt_program_fdi_mphy(dev_priv); |
| 6688 | } |
| 6689 | } |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6690 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6691 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
| 6692 | SBI_GEN0 : SBI_DBUFF0; |
| 6693 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 6694 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 6695 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
Daniel Vetter | c00db24 | 2013-01-22 15:33:27 +0100 | [diff] [blame] | 6696 | |
| 6697 | mutex_unlock(&dev_priv->dpio_lock); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6698 | } |
| 6699 | |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 6700 | /* Sequence to disable CLKOUT_DP */ |
| 6701 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
| 6702 | { |
| 6703 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6704 | uint32_t reg, tmp; |
| 6705 | |
| 6706 | mutex_lock(&dev_priv->dpio_lock); |
| 6707 | |
| 6708 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
| 6709 | SBI_GEN0 : SBI_DBUFF0; |
| 6710 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 6711 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 6712 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 6713 | |
| 6714 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 6715 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
| 6716 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
| 6717 | tmp |= SBI_SSCCTL_PATHALT; |
| 6718 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 6719 | udelay(32); |
| 6720 | } |
| 6721 | tmp |= SBI_SSCCTL_DISABLE; |
| 6722 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 6723 | } |
| 6724 | |
| 6725 | mutex_unlock(&dev_priv->dpio_lock); |
| 6726 | } |
| 6727 | |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 6728 | static void lpt_init_pch_refclk(struct drm_device *dev) |
| 6729 | { |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 6730 | struct intel_encoder *encoder; |
| 6731 | bool has_vga = false; |
| 6732 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 6733 | for_each_intel_encoder(dev, encoder) { |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 6734 | switch (encoder->type) { |
| 6735 | case INTEL_OUTPUT_ANALOG: |
| 6736 | has_vga = true; |
| 6737 | break; |
| 6738 | } |
| 6739 | } |
| 6740 | |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 6741 | if (has_vga) |
| 6742 | lpt_enable_clkout_dp(dev, true, true); |
| 6743 | else |
| 6744 | lpt_disable_clkout_dp(dev); |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 6745 | } |
| 6746 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6747 | /* |
| 6748 | * Initialize reference clocks when the driver loads |
| 6749 | */ |
| 6750 | void intel_init_pch_refclk(struct drm_device *dev) |
| 6751 | { |
| 6752 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 6753 | ironlake_init_pch_refclk(dev); |
| 6754 | else if (HAS_PCH_LPT(dev)) |
| 6755 | lpt_init_pch_refclk(dev); |
| 6756 | } |
| 6757 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6758 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
| 6759 | { |
| 6760 | struct drm_device *dev = crtc->dev; |
| 6761 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6762 | struct intel_encoder *encoder; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6763 | int num_connectors = 0; |
| 6764 | bool is_lvds = false; |
| 6765 | |
Daniel Vetter | 6c2b7c1 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 6766 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6767 | switch (encoder->type) { |
| 6768 | case INTEL_OUTPUT_LVDS: |
| 6769 | is_lvds = true; |
| 6770 | break; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6771 | } |
| 6772 | num_connectors++; |
| 6773 | } |
| 6774 | |
| 6775 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 6776 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 6777 | dev_priv->vbt.lvds_ssc_freq); |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 6778 | return dev_priv->vbt.lvds_ssc_freq; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6779 | } |
| 6780 | |
| 6781 | return 120000; |
| 6782 | } |
| 6783 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6784 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6785 | { |
| 6786 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 6787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6788 | int pipe = intel_crtc->pipe; |
| 6789 | uint32_t val; |
| 6790 | |
Daniel Vetter | 7811407 | 2013-06-13 00:54:57 +0200 | [diff] [blame] | 6791 | val = 0; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6792 | |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 6793 | switch (intel_crtc->config.pipe_bpp) { |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6794 | case 18: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6795 | val |= PIPECONF_6BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6796 | break; |
| 6797 | case 24: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6798 | val |= PIPECONF_8BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6799 | break; |
| 6800 | case 30: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6801 | val |= PIPECONF_10BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6802 | break; |
| 6803 | case 36: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6804 | val |= PIPECONF_12BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6805 | break; |
| 6806 | default: |
Paulo Zanoni | cc769b6 | 2012-09-20 18:36:03 -0300 | [diff] [blame] | 6807 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 6808 | BUG(); |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6809 | } |
| 6810 | |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 6811 | if (intel_crtc->config.dither) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6812 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 6813 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6814 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6815 | val |= PIPECONF_INTERLACED_ILK; |
| 6816 | else |
| 6817 | val |= PIPECONF_PROGRESSIVE; |
| 6818 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6819 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 6820 | val |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 6821 | |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6822 | I915_WRITE(PIPECONF(pipe), val); |
| 6823 | POSTING_READ(PIPECONF(pipe)); |
| 6824 | } |
| 6825 | |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6826 | /* |
| 6827 | * Set up the pipe CSC unit. |
| 6828 | * |
| 6829 | * Currently only full range RGB to limited range RGB conversion |
| 6830 | * is supported, but eventually this should handle various |
| 6831 | * RGB<->YCbCr scenarios as well. |
| 6832 | */ |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6833 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6834 | { |
| 6835 | struct drm_device *dev = crtc->dev; |
| 6836 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6838 | int pipe = intel_crtc->pipe; |
| 6839 | uint16_t coeff = 0x7800; /* 1.0 */ |
| 6840 | |
| 6841 | /* |
| 6842 | * TODO: Check what kind of values actually come out of the pipe |
| 6843 | * with these coeff/postoff values and adjust to get the best |
| 6844 | * accuracy. Perhaps we even need to take the bpc value into |
| 6845 | * consideration. |
| 6846 | */ |
| 6847 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6848 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6849 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
| 6850 | |
| 6851 | /* |
| 6852 | * GY/GU and RY/RU should be the other way around according |
| 6853 | * to BSpec, but reality doesn't agree. Just set them up in |
| 6854 | * a way that results in the correct picture. |
| 6855 | */ |
| 6856 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
| 6857 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
| 6858 | |
| 6859 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
| 6860 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
| 6861 | |
| 6862 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
| 6863 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
| 6864 | |
| 6865 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
| 6866 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
| 6867 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
| 6868 | |
| 6869 | if (INTEL_INFO(dev)->gen > 6) { |
| 6870 | uint16_t postoff = 0; |
| 6871 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6872 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 32cf0cb | 2013-11-28 22:10:38 +0200 | [diff] [blame] | 6873 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6874 | |
| 6875 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
| 6876 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
| 6877 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
| 6878 | |
| 6879 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
| 6880 | } else { |
| 6881 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
| 6882 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6883 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6884 | mode |= CSC_BLACK_SCREEN_OFFSET; |
| 6885 | |
| 6886 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
| 6887 | } |
| 6888 | } |
| 6889 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6890 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6891 | { |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6892 | struct drm_device *dev = crtc->dev; |
| 6893 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6895 | enum pipe pipe = intel_crtc->pipe; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 6896 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6897 | uint32_t val; |
| 6898 | |
Daniel Vetter | 3eff4fa | 2013-06-13 00:54:59 +0200 | [diff] [blame] | 6899 | val = 0; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6900 | |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6901 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6902 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 6903 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6904 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6905 | val |= PIPECONF_INTERLACED_ILK; |
| 6906 | else |
| 6907 | val |= PIPECONF_PROGRESSIVE; |
| 6908 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 6909 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
| 6910 | POSTING_READ(PIPECONF(cpu_transcoder)); |
Daniel Vetter | 3eff4fa | 2013-06-13 00:54:59 +0200 | [diff] [blame] | 6911 | |
| 6912 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
| 6913 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6914 | |
| 6915 | if (IS_BROADWELL(dev)) { |
| 6916 | val = 0; |
| 6917 | |
| 6918 | switch (intel_crtc->config.pipe_bpp) { |
| 6919 | case 18: |
| 6920 | val |= PIPEMISC_DITHER_6_BPC; |
| 6921 | break; |
| 6922 | case 24: |
| 6923 | val |= PIPEMISC_DITHER_8_BPC; |
| 6924 | break; |
| 6925 | case 30: |
| 6926 | val |= PIPEMISC_DITHER_10_BPC; |
| 6927 | break; |
| 6928 | case 36: |
| 6929 | val |= PIPEMISC_DITHER_12_BPC; |
| 6930 | break; |
| 6931 | default: |
| 6932 | /* Case prevented by pipe_config_set_bpp. */ |
| 6933 | BUG(); |
| 6934 | } |
| 6935 | |
| 6936 | if (intel_crtc->config.dither) |
| 6937 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
| 6938 | |
| 6939 | I915_WRITE(PIPEMISC(pipe), val); |
| 6940 | } |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6941 | } |
| 6942 | |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6943 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6944 | intel_clock_t *clock, |
| 6945 | bool *has_reduced_clock, |
| 6946 | intel_clock_t *reduced_clock) |
| 6947 | { |
| 6948 | struct drm_device *dev = crtc->dev; |
| 6949 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6950 | struct intel_encoder *intel_encoder; |
| 6951 | int refclk; |
| 6952 | const intel_limit_t *limit; |
Daniel Vetter | a16af72 | 2013-04-30 14:01:44 +0200 | [diff] [blame] | 6953 | bool ret, is_lvds = false; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6954 | |
| 6955 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 6956 | switch (intel_encoder->type) { |
| 6957 | case INTEL_OUTPUT_LVDS: |
| 6958 | is_lvds = true; |
| 6959 | break; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6960 | } |
| 6961 | } |
| 6962 | |
| 6963 | refclk = ironlake_get_refclk(crtc); |
| 6964 | |
| 6965 | /* |
| 6966 | * Returns a set of divisors for the desired target clock with the given |
| 6967 | * refclk, or FALSE. The returned values represent the clock equation: |
| 6968 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 6969 | */ |
| 6970 | limit = intel_limit(crtc, refclk); |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 6971 | ret = dev_priv->display.find_dpll(limit, crtc, |
| 6972 | to_intel_crtc(crtc)->config.port_clock, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 6973 | refclk, NULL, clock); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6974 | if (!ret) |
| 6975 | return false; |
| 6976 | |
| 6977 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
| 6978 | /* |
| 6979 | * Ensure we match the reduced clock's P to the target clock. |
| 6980 | * If the clocks don't match, we can't switch the display clock |
| 6981 | * by using the FP0/FP1. In such case we will disable the LVDS |
| 6982 | * downclock feature. |
| 6983 | */ |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 6984 | *has_reduced_clock = |
| 6985 | dev_priv->display.find_dpll(limit, crtc, |
| 6986 | dev_priv->lvds_downclock, |
| 6987 | refclk, clock, |
| 6988 | reduced_clock); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6989 | } |
| 6990 | |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6991 | return true; |
| 6992 | } |
| 6993 | |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 6994 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
| 6995 | { |
| 6996 | /* |
| 6997 | * Account for spread spectrum to avoid |
| 6998 | * oversubscribing the link. Max center spread |
| 6999 | * is 2.5%; use 5% for safety's sake. |
| 7000 | */ |
| 7001 | u32 bps = target_clock * bpp * 21 / 20; |
Ville Syrjälä | 619d4d0 | 2014-02-27 14:23:14 +0200 | [diff] [blame] | 7002 | return DIV_ROUND_UP(bps, link_bw * 8); |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 7003 | } |
| 7004 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7005 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 7006 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7007 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
Paulo Zanoni | f48d8f2 | 2012-09-20 18:36:04 -0300 | [diff] [blame] | 7008 | } |
| 7009 | |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 7010 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7011 | u32 *fp, |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 7012 | intel_clock_t *reduced_clock, u32 *fp2) |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 7013 | { |
| 7014 | struct drm_crtc *crtc = &intel_crtc->base; |
| 7015 | struct drm_device *dev = crtc->dev; |
| 7016 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7017 | struct intel_encoder *intel_encoder; |
| 7018 | uint32_t dpll; |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 7019 | int factor, num_connectors = 0; |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 7020 | bool is_lvds = false, is_sdvo = false; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 7021 | |
| 7022 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 7023 | switch (intel_encoder->type) { |
| 7024 | case INTEL_OUTPUT_LVDS: |
| 7025 | is_lvds = true; |
| 7026 | break; |
| 7027 | case INTEL_OUTPUT_SDVO: |
| 7028 | case INTEL_OUTPUT_HDMI: |
| 7029 | is_sdvo = true; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 7030 | break; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 7031 | } |
| 7032 | |
| 7033 | num_connectors++; |
| 7034 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7035 | |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 7036 | /* Enable autotuning of the PLL clock (if permissible) */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 7037 | factor = 21; |
| 7038 | if (is_lvds) { |
| 7039 | if ((intel_panel_use_ssc(dev_priv) && |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 7040 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
Daniel Vetter | f0b4405 | 2013-04-04 22:20:33 +0200 | [diff] [blame] | 7041 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 7042 | factor = 25; |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 7043 | } else if (intel_crtc->config.sdvo_tv_clock) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 7044 | factor = 20; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 7045 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7046 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
Daniel Vetter | 7d0ac5b | 2013-04-04 22:20:32 +0200 | [diff] [blame] | 7047 | *fp |= FP_CB_TUNE; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 7048 | |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 7049 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
| 7050 | *fp2 |= FP_CB_TUNE; |
| 7051 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 7052 | dpll = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7053 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 7054 | if (is_lvds) |
| 7055 | dpll |= DPLLB_MODE_LVDS; |
| 7056 | else |
| 7057 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 7058 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 7059 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
| 7060 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 7061 | |
| 7062 | if (is_sdvo) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 7063 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | 9566e9a | 2013-04-19 11:14:36 +0200 | [diff] [blame] | 7064 | if (intel_crtc->config.has_dp_encoder) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 7065 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7066 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 7067 | /* compute bitmask from p1 value */ |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7068 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 7069 | /* also FPA1 */ |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7070 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 7071 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7072 | switch (intel_crtc->config.dpll.p2) { |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 7073 | case 5: |
| 7074 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 7075 | break; |
| 7076 | case 7: |
| 7077 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 7078 | break; |
| 7079 | case 10: |
| 7080 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 7081 | break; |
| 7082 | case 14: |
| 7083 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 7084 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7085 | } |
| 7086 | |
Daniel Vetter | b4c09f3 | 2013-04-30 14:01:42 +0200 | [diff] [blame] | 7087 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 7088 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7089 | else |
| 7090 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 7091 | |
Daniel Vetter | 959e16d | 2013-06-05 13:34:21 +0200 | [diff] [blame] | 7092 | return dpll | DPLL_VCO_ENABLE; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 7093 | } |
| 7094 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7095 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7096 | int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 7097 | struct drm_framebuffer *fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7098 | { |
| 7099 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 7101 | int num_connectors = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7102 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 7103 | u32 dpll = 0, fp = 0, fp2 = 0; |
Paulo Zanoni | e2f12b0 | 2012-09-20 18:36:06 -0300 | [diff] [blame] | 7104 | bool ok, has_reduced_clock = false; |
Daniel Vetter | 8b47047 | 2013-03-28 10:41:59 +0100 | [diff] [blame] | 7105 | bool is_lvds = false; |
Paulo Zanoni | f48d8f2 | 2012-09-20 18:36:04 -0300 | [diff] [blame] | 7106 | struct intel_encoder *encoder; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 7107 | struct intel_shared_dpll *pll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7108 | |
| 7109 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 7110 | switch (encoder->type) { |
| 7111 | case INTEL_OUTPUT_LVDS: |
| 7112 | is_lvds = true; |
| 7113 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7114 | } |
| 7115 | |
| 7116 | num_connectors++; |
| 7117 | } |
| 7118 | |
Paulo Zanoni | 5dc5298 | 2012-10-05 12:05:56 -0300 | [diff] [blame] | 7119 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
| 7120 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
| 7121 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 7122 | ok = ironlake_compute_clocks(crtc, &clock, |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 7123 | &has_reduced_clock, &reduced_clock); |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 7124 | if (!ok && !intel_crtc->config.clock_set) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7125 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 7126 | return -EINVAL; |
| 7127 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7128 | /* Compat-code for transition, will disappear. */ |
| 7129 | if (!intel_crtc->config.clock_set) { |
| 7130 | intel_crtc->config.dpll.n = clock.n; |
| 7131 | intel_crtc->config.dpll.m1 = clock.m1; |
| 7132 | intel_crtc->config.dpll.m2 = clock.m2; |
| 7133 | intel_crtc->config.dpll.p1 = clock.p1; |
| 7134 | intel_crtc->config.dpll.p2 = clock.p2; |
| 7135 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7136 | |
Paulo Zanoni | 5dc5298 | 2012-10-05 12:05:56 -0300 | [diff] [blame] | 7137 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
Daniel Vetter | 8b47047 | 2013-03-28 10:41:59 +0100 | [diff] [blame] | 7138 | if (intel_crtc->config.has_pch_encoder) { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7139 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 7140 | if (has_reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7141 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 7142 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7143 | dpll = ironlake_compute_dpll(intel_crtc, |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 7144 | &fp, &reduced_clock, |
| 7145 | has_reduced_clock ? &fp2 : NULL); |
| 7146 | |
Daniel Vetter | 959e16d | 2013-06-05 13:34:21 +0200 | [diff] [blame] | 7147 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 7148 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
| 7149 | if (has_reduced_clock) |
| 7150 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
| 7151 | else |
| 7152 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
| 7153 | |
Daniel Vetter | b89a1d3 | 2013-06-05 13:34:24 +0200 | [diff] [blame] | 7154 | pll = intel_get_shared_dpll(intel_crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 7155 | if (pll == NULL) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 7156 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 7157 | pipe_name(intel_crtc->pipe)); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 7158 | return -EINVAL; |
| 7159 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 7160 | } else |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 7161 | intel_put_shared_dpll(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7162 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 7163 | if (is_lvds && has_reduced_clock && i915.powersave) |
Daniel Vetter | bcd644e | 2013-06-05 13:34:22 +0200 | [diff] [blame] | 7164 | intel_crtc->lowfreq_avail = true; |
| 7165 | else |
| 7166 | intel_crtc->lowfreq_avail = false; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 7167 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 7168 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7169 | } |
| 7170 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7171 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
| 7172 | struct intel_link_m_n *m_n) |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 7173 | { |
| 7174 | struct drm_device *dev = crtc->base.dev; |
| 7175 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7176 | enum pipe pipe = crtc->pipe; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 7177 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7178 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
| 7179 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
| 7180 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 7181 | & ~TU_SIZE_MASK; |
| 7182 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
| 7183 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 7184 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 7185 | } |
| 7186 | |
| 7187 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
| 7188 | enum transcoder transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 7189 | struct intel_link_m_n *m_n, |
| 7190 | struct intel_link_m_n *m2_n2) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7191 | { |
| 7192 | struct drm_device *dev = crtc->base.dev; |
| 7193 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7194 | enum pipe pipe = crtc->pipe; |
| 7195 | |
| 7196 | if (INTEL_INFO(dev)->gen >= 5) { |
| 7197 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
| 7198 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
| 7199 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
| 7200 | & ~TU_SIZE_MASK; |
| 7201 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
| 7202 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
| 7203 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 7204 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
| 7205 | * gen < 8) and if DRRS is supported (to make sure the |
| 7206 | * registers are not unnecessarily read). |
| 7207 | */ |
| 7208 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
| 7209 | crtc->config.has_drrs) { |
| 7210 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
| 7211 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); |
| 7212 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) |
| 7213 | & ~TU_SIZE_MASK; |
| 7214 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); |
| 7215 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) |
| 7216 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 7217 | } |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7218 | } else { |
| 7219 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
| 7220 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
| 7221 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 7222 | & ~TU_SIZE_MASK; |
| 7223 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
| 7224 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 7225 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 7226 | } |
| 7227 | } |
| 7228 | |
| 7229 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 7230 | struct intel_crtc_config *pipe_config) |
| 7231 | { |
| 7232 | if (crtc->config.has_pch_encoder) |
| 7233 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
| 7234 | else |
| 7235 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 7236 | &pipe_config->dp_m_n, |
| 7237 | &pipe_config->dp_m2_n2); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7238 | } |
| 7239 | |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 7240 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
| 7241 | struct intel_crtc_config *pipe_config) |
| 7242 | { |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 7243 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 7244 | &pipe_config->fdi_m_n, NULL); |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 7245 | } |
| 7246 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7247 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
| 7248 | struct intel_crtc_config *pipe_config) |
| 7249 | { |
| 7250 | struct drm_device *dev = crtc->base.dev; |
| 7251 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7252 | uint32_t tmp; |
| 7253 | |
| 7254 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
| 7255 | |
| 7256 | if (tmp & PF_ENABLE) { |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 7257 | pipe_config->pch_pfit.enabled = true; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7258 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
| 7259 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
Daniel Vetter | cb8b2a3 | 2013-06-01 17:16:23 +0200 | [diff] [blame] | 7260 | |
| 7261 | /* We currently do not free assignements of panel fitters on |
| 7262 | * ivb/hsw (since we don't use the higher upscaling modes which |
| 7263 | * differentiates them) so just WARN about this case for now. */ |
| 7264 | if (IS_GEN7(dev)) { |
| 7265 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
| 7266 | PF_PIPE_SEL_IVB(crtc->pipe)); |
| 7267 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7268 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7269 | } |
| 7270 | |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7271 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
| 7272 | struct intel_plane_config *plane_config) |
| 7273 | { |
| 7274 | struct drm_device *dev = crtc->base.dev; |
| 7275 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7276 | u32 val, base, offset; |
| 7277 | int pipe = crtc->pipe, plane = crtc->plane; |
| 7278 | int fourcc, pixel_format; |
| 7279 | int aligned_height; |
| 7280 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 7281 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
| 7282 | if (!crtc->base.primary->fb) { |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7283 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 7284 | return; |
| 7285 | } |
| 7286 | |
| 7287 | val = I915_READ(DSPCNTR(plane)); |
| 7288 | |
| 7289 | if (INTEL_INFO(dev)->gen >= 4) |
| 7290 | if (val & DISPPLANE_TILED) |
| 7291 | plane_config->tiled = true; |
| 7292 | |
| 7293 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
| 7294 | fourcc = intel_format_to_fourcc(pixel_format); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 7295 | crtc->base.primary->fb->pixel_format = fourcc; |
| 7296 | crtc->base.primary->fb->bits_per_pixel = |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7297 | drm_format_plane_cpp(fourcc, 0) * 8; |
| 7298 | |
| 7299 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 7300 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 7301 | offset = I915_READ(DSPOFFSET(plane)); |
| 7302 | } else { |
| 7303 | if (plane_config->tiled) |
| 7304 | offset = I915_READ(DSPTILEOFF(plane)); |
| 7305 | else |
| 7306 | offset = I915_READ(DSPLINOFF(plane)); |
| 7307 | } |
| 7308 | plane_config->base = base; |
| 7309 | |
| 7310 | val = I915_READ(PIPESRC(pipe)); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 7311 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
| 7312 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7313 | |
| 7314 | val = I915_READ(DSPSTRIDE(pipe)); |
Rafael Barbalho | 026b96e | 2014-07-28 19:56:27 +0100 | [diff] [blame] | 7315 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7316 | |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 7317 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7318 | plane_config->tiled); |
| 7319 | |
Fabian Frederick | 1267a26 | 2014-07-01 20:39:41 +0200 | [diff] [blame] | 7320 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
| 7321 | aligned_height); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7322 | |
| 7323 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 7324 | pipe, plane, crtc->base.primary->fb->width, |
| 7325 | crtc->base.primary->fb->height, |
| 7326 | crtc->base.primary->fb->bits_per_pixel, base, |
| 7327 | crtc->base.primary->fb->pitches[0], |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 7328 | plane_config->size); |
| 7329 | } |
| 7330 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7331 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
| 7332 | struct intel_crtc_config *pipe_config) |
| 7333 | { |
| 7334 | struct drm_device *dev = crtc->base.dev; |
| 7335 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7336 | uint32_t tmp; |
| 7337 | |
Paulo Zanoni | 930e8c9 | 2014-07-04 13:38:34 -0300 | [diff] [blame] | 7338 | if (!intel_display_power_enabled(dev_priv, |
| 7339 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 7340 | return false; |
| 7341 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 7342 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 7343 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7344 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7345 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 7346 | if (!(tmp & PIPECONF_ENABLE)) |
| 7347 | return false; |
| 7348 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 7349 | switch (tmp & PIPECONF_BPC_MASK) { |
| 7350 | case PIPECONF_6BPC: |
| 7351 | pipe_config->pipe_bpp = 18; |
| 7352 | break; |
| 7353 | case PIPECONF_8BPC: |
| 7354 | pipe_config->pipe_bpp = 24; |
| 7355 | break; |
| 7356 | case PIPECONF_10BPC: |
| 7357 | pipe_config->pipe_bpp = 30; |
| 7358 | break; |
| 7359 | case PIPECONF_12BPC: |
| 7360 | pipe_config->pipe_bpp = 36; |
| 7361 | break; |
| 7362 | default: |
| 7363 | break; |
| 7364 | } |
| 7365 | |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 7366 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
| 7367 | pipe_config->limited_color_range = true; |
| 7368 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 7369 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 7370 | struct intel_shared_dpll *pll; |
| 7371 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7372 | pipe_config->has_pch_encoder = true; |
| 7373 | |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 7374 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
| 7375 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 7376 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 7377 | |
| 7378 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 7379 | |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 7380 | if (HAS_PCH_IBX(dev_priv->dev)) { |
Daniel Vetter | d94ab06 | 2013-07-04 12:01:16 +0200 | [diff] [blame] | 7381 | pipe_config->shared_dpll = |
| 7382 | (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 7383 | } else { |
| 7384 | tmp = I915_READ(PCH_DPLL_SEL); |
| 7385 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
| 7386 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
| 7387 | else |
| 7388 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
| 7389 | } |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 7390 | |
| 7391 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 7392 | |
| 7393 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 7394 | &pipe_config->dpll_hw_state)); |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 7395 | |
| 7396 | tmp = pipe_config->dpll_hw_state.dpll; |
| 7397 | pipe_config->pixel_multiplier = |
| 7398 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
| 7399 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 7400 | |
| 7401 | ironlake_pch_clock_get(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 7402 | } else { |
| 7403 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 7404 | } |
| 7405 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7406 | intel_get_pipe_timings(crtc, pipe_config); |
| 7407 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7408 | ironlake_get_pfit_config(crtc, pipe_config); |
| 7409 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7410 | return true; |
| 7411 | } |
| 7412 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7413 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
| 7414 | { |
| 7415 | struct drm_device *dev = dev_priv->dev; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7416 | struct intel_crtc *crtc; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7417 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 7418 | for_each_intel_crtc(dev, crtc) |
Paulo Zanoni | 798183c | 2013-12-06 20:29:01 -0200 | [diff] [blame] | 7419 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7420 | pipe_name(crtc->pipe)); |
| 7421 | |
| 7422 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
Daniel Vetter | 8cc3e16 | 2014-06-25 22:01:46 +0300 | [diff] [blame] | 7423 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
| 7424 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
| 7425 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7426 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
| 7427 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
| 7428 | "CPU PWM1 enabled\n"); |
Paulo Zanoni | c5107b8 | 2014-07-04 11:50:30 -0300 | [diff] [blame] | 7429 | if (IS_HASWELL(dev)) |
| 7430 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
| 7431 | "CPU PWM2 enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7432 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
| 7433 | "PCH PWM1 enabled\n"); |
| 7434 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
| 7435 | "Utility pin enabled\n"); |
| 7436 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
| 7437 | |
Paulo Zanoni | 9926ada | 2014-04-01 19:39:47 -0300 | [diff] [blame] | 7438 | /* |
| 7439 | * In theory we can still leave IRQs enabled, as long as only the HPD |
| 7440 | * interrupts remain enabled. We used to check for that, but since it's |
| 7441 | * gen-specific and since we only disable LCPLL after we fully disable |
| 7442 | * the interrupts, the check below should be enough. |
| 7443 | */ |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 7444 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7445 | } |
| 7446 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 7447 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
| 7448 | { |
| 7449 | struct drm_device *dev = dev_priv->dev; |
| 7450 | |
| 7451 | if (IS_HASWELL(dev)) |
| 7452 | return I915_READ(D_COMP_HSW); |
| 7453 | else |
| 7454 | return I915_READ(D_COMP_BDW); |
| 7455 | } |
| 7456 | |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 7457 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
| 7458 | { |
| 7459 | struct drm_device *dev = dev_priv->dev; |
| 7460 | |
| 7461 | if (IS_HASWELL(dev)) { |
| 7462 | mutex_lock(&dev_priv->rps.hw_lock); |
| 7463 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
| 7464 | val)) |
Paulo Zanoni | f475dad | 2014-07-04 11:59:57 -0300 | [diff] [blame] | 7465 | DRM_ERROR("Failed to write to D_COMP\n"); |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 7466 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 7467 | } else { |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 7468 | I915_WRITE(D_COMP_BDW, val); |
| 7469 | POSTING_READ(D_COMP_BDW); |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 7470 | } |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7471 | } |
| 7472 | |
| 7473 | /* |
| 7474 | * This function implements pieces of two sequences from BSpec: |
| 7475 | * - Sequence for display software to disable LCPLL |
| 7476 | * - Sequence for display software to allow package C8+ |
| 7477 | * The steps implemented here are just the steps that actually touch the LCPLL |
| 7478 | * register. Callers should take care of disabling all the display engine |
| 7479 | * functions, doing the mode unset, fixing interrupts, etc. |
| 7480 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 7481 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
| 7482 | bool switch_to_fclk, bool allow_power_down) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7483 | { |
| 7484 | uint32_t val; |
| 7485 | |
| 7486 | assert_can_disable_lcpll(dev_priv); |
| 7487 | |
| 7488 | val = I915_READ(LCPLL_CTL); |
| 7489 | |
| 7490 | if (switch_to_fclk) { |
| 7491 | val |= LCPLL_CD_SOURCE_FCLK; |
| 7492 | I915_WRITE(LCPLL_CTL, val); |
| 7493 | |
| 7494 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
| 7495 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 7496 | DRM_ERROR("Switching to FCLK failed\n"); |
| 7497 | |
| 7498 | val = I915_READ(LCPLL_CTL); |
| 7499 | } |
| 7500 | |
| 7501 | val |= LCPLL_PLL_DISABLE; |
| 7502 | I915_WRITE(LCPLL_CTL, val); |
| 7503 | POSTING_READ(LCPLL_CTL); |
| 7504 | |
| 7505 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
| 7506 | DRM_ERROR("LCPLL still locked\n"); |
| 7507 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 7508 | val = hsw_read_dcomp(dev_priv); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7509 | val |= D_COMP_COMP_DISABLE; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 7510 | hsw_write_dcomp(dev_priv, val); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7511 | ndelay(100); |
| 7512 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 7513 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
| 7514 | 1)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7515 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
| 7516 | |
| 7517 | if (allow_power_down) { |
| 7518 | val = I915_READ(LCPLL_CTL); |
| 7519 | val |= LCPLL_POWER_DOWN_ALLOW; |
| 7520 | I915_WRITE(LCPLL_CTL, val); |
| 7521 | POSTING_READ(LCPLL_CTL); |
| 7522 | } |
| 7523 | } |
| 7524 | |
| 7525 | /* |
| 7526 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
| 7527 | * source. |
| 7528 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 7529 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7530 | { |
| 7531 | uint32_t val; |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7532 | unsigned long irqflags; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7533 | |
| 7534 | val = I915_READ(LCPLL_CTL); |
| 7535 | |
| 7536 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
| 7537 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
| 7538 | return; |
| 7539 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7540 | /* |
| 7541 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
| 7542 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
| 7543 | * |
| 7544 | * The other problem is that hsw_restore_lcpll() is called as part of |
| 7545 | * the runtime PM resume sequence, so we can't just call |
| 7546 | * gen6_gt_force_wake_get() because that function calls |
| 7547 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount |
| 7548 | * while we are on the resume sequence. So to solve this problem we have |
| 7549 | * to call special forcewake code that doesn't touch runtime PM and |
| 7550 | * doesn't enable the forcewake delayed work. |
| 7551 | */ |
| 7552 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 7553 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 7554 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
| 7555 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 7556 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7557 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
| 7558 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
| 7559 | I915_WRITE(LCPLL_CTL, val); |
Daniel Vetter | 35d8f2e | 2013-08-21 23:38:08 +0200 | [diff] [blame] | 7560 | POSTING_READ(LCPLL_CTL); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7561 | } |
| 7562 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 7563 | val = hsw_read_dcomp(dev_priv); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7564 | val |= D_COMP_COMP_FORCE; |
| 7565 | val &= ~D_COMP_COMP_DISABLE; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 7566 | hsw_write_dcomp(dev_priv, val); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7567 | |
| 7568 | val = I915_READ(LCPLL_CTL); |
| 7569 | val &= ~LCPLL_PLL_DISABLE; |
| 7570 | I915_WRITE(LCPLL_CTL, val); |
| 7571 | |
| 7572 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
| 7573 | DRM_ERROR("LCPLL not locked yet\n"); |
| 7574 | |
| 7575 | if (val & LCPLL_CD_SOURCE_FCLK) { |
| 7576 | val = I915_READ(LCPLL_CTL); |
| 7577 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 7578 | I915_WRITE(LCPLL_CTL, val); |
| 7579 | |
| 7580 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
| 7581 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 7582 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 7583 | } |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 7584 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7585 | /* See the big comment above. */ |
| 7586 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 7587 | if (--dev_priv->uncore.forcewake_count == 0) |
| 7588 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
| 7589 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7590 | } |
| 7591 | |
Paulo Zanoni | 765dab67 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 7592 | /* |
| 7593 | * Package states C8 and deeper are really deep PC states that can only be |
| 7594 | * reached when all the devices on the system allow it, so even if the graphics |
| 7595 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 7596 | * states. Our driver only allows PC8+ when going into runtime PM. |
| 7597 | * |
| 7598 | * The requirements for PC8+ are that all the outputs are disabled, the power |
| 7599 | * well is disabled and most interrupts are disabled, and these are also |
| 7600 | * requirements for runtime PM. When these conditions are met, we manually do |
| 7601 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
| 7602 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
| 7603 | * hang the machine. |
| 7604 | * |
| 7605 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 7606 | * the state of some registers, so when we come back from PC8+ we need to |
| 7607 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 7608 | * need to take care of the registers kept by RC6. Notice that this happens even |
| 7609 | * if we don't put the device in PCI D3 state (which is what currently happens |
| 7610 | * because of the runtime PM support). |
| 7611 | * |
| 7612 | * For more, read "Display Sequences for Package C8" on the hardware |
| 7613 | * documentation. |
| 7614 | */ |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 7615 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7616 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7617 | struct drm_device *dev = dev_priv->dev; |
| 7618 | uint32_t val; |
| 7619 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7620 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
| 7621 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7622 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 7623 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 7624 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 7625 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 7626 | } |
| 7627 | |
| 7628 | lpt_disable_clkout_dp(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7629 | hsw_disable_lcpll(dev_priv, true, true); |
| 7630 | } |
| 7631 | |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 7632 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7633 | { |
| 7634 | struct drm_device *dev = dev_priv->dev; |
| 7635 | uint32_t val; |
| 7636 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7637 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
| 7638 | |
| 7639 | hsw_restore_lcpll(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7640 | lpt_init_pch_refclk(dev); |
| 7641 | |
| 7642 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 7643 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 7644 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
| 7645 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 7646 | } |
| 7647 | |
| 7648 | intel_prepare_ddi(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7649 | } |
| 7650 | |
Paulo Zanoni | 9a952a0 | 2014-03-07 20:12:34 -0300 | [diff] [blame] | 7651 | static void snb_modeset_global_resources(struct drm_device *dev) |
| 7652 | { |
| 7653 | modeset_update_crtc_power_domains(dev); |
| 7654 | } |
| 7655 | |
Imre Deak | 4f07412 | 2013-10-16 17:25:51 +0300 | [diff] [blame] | 7656 | static void haswell_modeset_global_resources(struct drm_device *dev) |
| 7657 | { |
Paulo Zanoni | da72356 | 2013-12-19 11:54:51 -0200 | [diff] [blame] | 7658 | modeset_update_crtc_power_domains(dev); |
Daniel Vetter | d6dd9eb | 2013-01-29 16:35:20 -0200 | [diff] [blame] | 7659 | } |
| 7660 | |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7661 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7662 | int x, int y, |
| 7663 | struct drm_framebuffer *fb) |
| 7664 | { |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7665 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7666 | |
Paulo Zanoni | 566b734 | 2013-11-25 15:27:08 -0200 | [diff] [blame] | 7667 | if (!intel_ddi_pll_select(intel_crtc)) |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 7668 | return -EINVAL; |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 7669 | |
Daniel Vetter | 644cef3 | 2014-04-24 23:55:07 +0200 | [diff] [blame] | 7670 | intel_crtc->lowfreq_avail = false; |
| 7671 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 7672 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7673 | } |
| 7674 | |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 7675 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 7676 | enum port port, |
| 7677 | struct intel_crtc_config *pipe_config) |
| 7678 | { |
| 7679 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
| 7680 | |
| 7681 | switch (pipe_config->ddi_pll_sel) { |
| 7682 | case PORT_CLK_SEL_WRPLL1: |
| 7683 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; |
| 7684 | break; |
| 7685 | case PORT_CLK_SEL_WRPLL2: |
| 7686 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
| 7687 | break; |
| 7688 | } |
| 7689 | } |
| 7690 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 7691 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
| 7692 | struct intel_crtc_config *pipe_config) |
| 7693 | { |
| 7694 | struct drm_device *dev = crtc->base.dev; |
| 7695 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 7696 | struct intel_shared_dpll *pll; |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 7697 | enum port port; |
| 7698 | uint32_t tmp; |
| 7699 | |
| 7700 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
| 7701 | |
| 7702 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
| 7703 | |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 7704 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 7705 | |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 7706 | if (pipe_config->shared_dpll >= 0) { |
| 7707 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 7708 | |
| 7709 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 7710 | &pipe_config->dpll_hw_state)); |
| 7711 | } |
| 7712 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 7713 | /* |
| 7714 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
| 7715 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
| 7716 | * the PCH transcoder is on. |
| 7717 | */ |
| 7718 | if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
| 7719 | pipe_config->has_pch_encoder = true; |
| 7720 | |
| 7721 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 7722 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 7723 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
| 7724 | |
| 7725 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
| 7726 | } |
| 7727 | } |
| 7728 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7729 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
| 7730 | struct intel_crtc_config *pipe_config) |
| 7731 | { |
| 7732 | struct drm_device *dev = crtc->base.dev; |
| 7733 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7734 | enum intel_display_power_domain pfit_domain; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7735 | uint32_t tmp; |
| 7736 | |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 7737 | if (!intel_display_power_enabled(dev_priv, |
| 7738 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 7739 | return false; |
| 7740 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 7741 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 7742 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
| 7743 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7744 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
| 7745 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
| 7746 | enum pipe trans_edp_pipe; |
| 7747 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 7748 | default: |
| 7749 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
| 7750 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 7751 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 7752 | trans_edp_pipe = PIPE_A; |
| 7753 | break; |
| 7754 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 7755 | trans_edp_pipe = PIPE_B; |
| 7756 | break; |
| 7757 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 7758 | trans_edp_pipe = PIPE_C; |
| 7759 | break; |
| 7760 | } |
| 7761 | |
| 7762 | if (trans_edp_pipe == crtc->pipe) |
| 7763 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 7764 | } |
| 7765 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7766 | if (!intel_display_power_enabled(dev_priv, |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7767 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
Paulo Zanoni | 2bfce95 | 2013-04-18 16:35:40 -0300 | [diff] [blame] | 7768 | return false; |
| 7769 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7770 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7771 | if (!(tmp & PIPECONF_ENABLE)) |
| 7772 | return false; |
| 7773 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 7774 | haswell_get_ddi_port_state(crtc, pipe_config); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 7775 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7776 | intel_get_pipe_timings(crtc, pipe_config); |
| 7777 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7778 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7779 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7780 | ironlake_get_pfit_config(crtc, pipe_config); |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7781 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 7782 | if (IS_HASWELL(dev)) |
| 7783 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
| 7784 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 7785 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 7786 | pipe_config->pixel_multiplier = 1; |
| 7787 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7788 | return true; |
| 7789 | } |
| 7790 | |
Jani Nikula | 1a91510 | 2013-10-16 12:34:48 +0300 | [diff] [blame] | 7791 | static struct { |
| 7792 | int clock; |
| 7793 | u32 config; |
| 7794 | } hdmi_audio_clock[] = { |
| 7795 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
| 7796 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
| 7797 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
| 7798 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
| 7799 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
| 7800 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
| 7801 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
| 7802 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
| 7803 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
| 7804 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
| 7805 | }; |
| 7806 | |
| 7807 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
| 7808 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
| 7809 | { |
| 7810 | int i; |
| 7811 | |
| 7812 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
| 7813 | if (mode->clock == hdmi_audio_clock[i].clock) |
| 7814 | break; |
| 7815 | } |
| 7816 | |
| 7817 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
| 7818 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
| 7819 | i = 1; |
| 7820 | } |
| 7821 | |
| 7822 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
| 7823 | hdmi_audio_clock[i].clock, |
| 7824 | hdmi_audio_clock[i].config); |
| 7825 | |
| 7826 | return hdmi_audio_clock[i].config; |
| 7827 | } |
| 7828 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 7829 | static bool intel_eld_uptodate(struct drm_connector *connector, |
| 7830 | int reg_eldv, uint32_t bits_eldv, |
| 7831 | int reg_elda, uint32_t bits_elda, |
| 7832 | int reg_edid) |
| 7833 | { |
| 7834 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7835 | uint8_t *eld = connector->eld; |
| 7836 | uint32_t i; |
| 7837 | |
| 7838 | i = I915_READ(reg_eldv); |
| 7839 | i &= bits_eldv; |
| 7840 | |
| 7841 | if (!eld[0]) |
| 7842 | return !i; |
| 7843 | |
| 7844 | if (!i) |
| 7845 | return false; |
| 7846 | |
| 7847 | i = I915_READ(reg_elda); |
| 7848 | i &= ~bits_elda; |
| 7849 | I915_WRITE(reg_elda, i); |
| 7850 | |
| 7851 | for (i = 0; i < eld[2]; i++) |
| 7852 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
| 7853 | return false; |
| 7854 | |
| 7855 | return true; |
| 7856 | } |
| 7857 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7858 | static void g4x_write_eld(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7859 | struct drm_crtc *crtc, |
| 7860 | struct drm_display_mode *mode) |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7861 | { |
| 7862 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7863 | uint8_t *eld = connector->eld; |
| 7864 | uint32_t eldv; |
| 7865 | uint32_t len; |
| 7866 | uint32_t i; |
| 7867 | |
| 7868 | i = I915_READ(G4X_AUD_VID_DID); |
| 7869 | |
| 7870 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
| 7871 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 7872 | else |
| 7873 | eldv = G4X_ELDV_DEVCTG; |
| 7874 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 7875 | if (intel_eld_uptodate(connector, |
| 7876 | G4X_AUD_CNTL_ST, eldv, |
| 7877 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
| 7878 | G4X_HDMIW_HDMIEDID)) |
| 7879 | return; |
| 7880 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7881 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 7882 | i &= ~(eldv | G4X_ELD_ADDR); |
| 7883 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
| 7884 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 7885 | |
| 7886 | if (!eld[0]) |
| 7887 | return; |
| 7888 | |
| 7889 | len = min_t(uint8_t, eld[2], len); |
| 7890 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 7891 | for (i = 0; i < len; i++) |
| 7892 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
| 7893 | |
| 7894 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 7895 | i |= eldv; |
| 7896 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 7897 | } |
| 7898 | |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7899 | static void haswell_write_eld(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7900 | struct drm_crtc *crtc, |
| 7901 | struct drm_display_mode *mode) |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7902 | { |
| 7903 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7904 | uint8_t *eld = connector->eld; |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7905 | uint32_t eldv; |
| 7906 | uint32_t i; |
| 7907 | int len; |
| 7908 | int pipe = to_intel_crtc(crtc)->pipe; |
| 7909 | int tmp; |
| 7910 | |
| 7911 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
| 7912 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
| 7913 | int aud_config = HSW_AUD_CFG(pipe); |
| 7914 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
| 7915 | |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7916 | /* Audio output enable */ |
| 7917 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
| 7918 | tmp = I915_READ(aud_cntrl_st2); |
| 7919 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
| 7920 | I915_WRITE(aud_cntrl_st2, tmp); |
Daniel Vetter | c790579 | 2014-04-16 16:56:09 +0200 | [diff] [blame] | 7921 | POSTING_READ(aud_cntrl_st2); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7922 | |
Daniel Vetter | c790579 | 2014-04-16 16:56:09 +0200 | [diff] [blame] | 7923 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7924 | |
| 7925 | /* Set ELD valid state */ |
| 7926 | tmp = I915_READ(aud_cntrl_st2); |
Takashi Iwai | 7e7cb34 | 2013-09-10 07:30:36 +0200 | [diff] [blame] | 7927 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7928 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
| 7929 | I915_WRITE(aud_cntrl_st2, tmp); |
| 7930 | tmp = I915_READ(aud_cntrl_st2); |
Takashi Iwai | 7e7cb34 | 2013-09-10 07:30:36 +0200 | [diff] [blame] | 7931 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7932 | |
| 7933 | /* Enable HDMI mode */ |
| 7934 | tmp = I915_READ(aud_config); |
Takashi Iwai | 7e7cb34 | 2013-09-10 07:30:36 +0200 | [diff] [blame] | 7935 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7936 | /* clear N_programing_enable and N_value_index */ |
| 7937 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
| 7938 | I915_WRITE(aud_config, tmp); |
| 7939 | |
| 7940 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
| 7941 | |
| 7942 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
| 7943 | |
| 7944 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 7945 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
| 7946 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
| 7947 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
Jani Nikula | 1a91510 | 2013-10-16 12:34:48 +0300 | [diff] [blame] | 7948 | } else { |
| 7949 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
| 7950 | } |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7951 | |
| 7952 | if (intel_eld_uptodate(connector, |
| 7953 | aud_cntrl_st2, eldv, |
| 7954 | aud_cntl_st, IBX_ELD_ADDRESS, |
| 7955 | hdmiw_hdmiedid)) |
| 7956 | return; |
| 7957 | |
| 7958 | i = I915_READ(aud_cntrl_st2); |
| 7959 | i &= ~eldv; |
| 7960 | I915_WRITE(aud_cntrl_st2, i); |
| 7961 | |
| 7962 | if (!eld[0]) |
| 7963 | return; |
| 7964 | |
| 7965 | i = I915_READ(aud_cntl_st); |
| 7966 | i &= ~IBX_ELD_ADDRESS; |
| 7967 | I915_WRITE(aud_cntl_st, i); |
| 7968 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
| 7969 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
| 7970 | |
| 7971 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
| 7972 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 7973 | for (i = 0; i < len; i++) |
| 7974 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 7975 | |
| 7976 | i = I915_READ(aud_cntrl_st2); |
| 7977 | i |= eldv; |
| 7978 | I915_WRITE(aud_cntrl_st2, i); |
| 7979 | |
| 7980 | } |
| 7981 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7982 | static void ironlake_write_eld(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7983 | struct drm_crtc *crtc, |
| 7984 | struct drm_display_mode *mode) |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7985 | { |
| 7986 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7987 | uint8_t *eld = connector->eld; |
| 7988 | uint32_t eldv; |
| 7989 | uint32_t i; |
| 7990 | int len; |
| 7991 | int hdmiw_hdmiedid; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 7992 | int aud_config; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7993 | int aud_cntl_st; |
| 7994 | int aud_cntrl_st2; |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 7995 | int pipe = to_intel_crtc(crtc)->pipe; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7996 | |
Wu Fengguang | b3f33cb | 2011-12-09 20:42:17 +0800 | [diff] [blame] | 7997 | if (HAS_PCH_IBX(connector->dev)) { |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 7998 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
| 7999 | aud_config = IBX_AUD_CFG(pipe); |
| 8000 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 8001 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
Mengdong Lin | 9ca2fe7 | 2013-11-01 00:17:03 -0400 | [diff] [blame] | 8002 | } else if (IS_VALLEYVIEW(connector->dev)) { |
| 8003 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
| 8004 | aud_config = VLV_AUD_CFG(pipe); |
| 8005 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
| 8006 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8007 | } else { |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 8008 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
| 8009 | aud_config = CPT_AUD_CFG(pipe); |
| 8010 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 8011 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8012 | } |
| 8013 | |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 8014 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8015 | |
Mengdong Lin | 9ca2fe7 | 2013-11-01 00:17:03 -0400 | [diff] [blame] | 8016 | if (IS_VALLEYVIEW(connector->dev)) { |
| 8017 | struct intel_encoder *intel_encoder; |
| 8018 | struct intel_digital_port *intel_dig_port; |
| 8019 | |
| 8020 | intel_encoder = intel_attached_encoder(connector); |
| 8021 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 8022 | i = intel_dig_port->port; |
| 8023 | } else { |
| 8024 | i = I915_READ(aud_cntl_st); |
| 8025 | i = (i >> 29) & DIP_PORT_SEL_MASK; |
| 8026 | /* DIP_Port_Select, 0x1 = PortB */ |
| 8027 | } |
| 8028 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8029 | if (!i) { |
| 8030 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
| 8031 | /* operate blindly on all ports */ |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 8032 | eldv = IBX_ELD_VALIDB; |
| 8033 | eldv |= IBX_ELD_VALIDB << 4; |
| 8034 | eldv |= IBX_ELD_VALIDB << 8; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8035 | } else { |
Ville Syrjälä | 2582a85 | 2013-04-17 17:48:47 +0300 | [diff] [blame] | 8036 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 8037 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8038 | } |
| 8039 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 8040 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 8041 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
| 8042 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 8043 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
Jani Nikula | 1a91510 | 2013-10-16 12:34:48 +0300 | [diff] [blame] | 8044 | } else { |
| 8045 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
| 8046 | } |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 8047 | |
| 8048 | if (intel_eld_uptodate(connector, |
| 8049 | aud_cntrl_st2, eldv, |
| 8050 | aud_cntl_st, IBX_ELD_ADDRESS, |
| 8051 | hdmiw_hdmiedid)) |
| 8052 | return; |
| 8053 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8054 | i = I915_READ(aud_cntrl_st2); |
| 8055 | i &= ~eldv; |
| 8056 | I915_WRITE(aud_cntrl_st2, i); |
| 8057 | |
| 8058 | if (!eld[0]) |
| 8059 | return; |
| 8060 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8061 | i = I915_READ(aud_cntl_st); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 8062 | i &= ~IBX_ELD_ADDRESS; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8063 | I915_WRITE(aud_cntl_st, i); |
| 8064 | |
| 8065 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
| 8066 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 8067 | for (i = 0; i < len; i++) |
| 8068 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 8069 | |
| 8070 | i = I915_READ(aud_cntrl_st2); |
| 8071 | i |= eldv; |
| 8072 | I915_WRITE(aud_cntrl_st2, i); |
| 8073 | } |
| 8074 | |
| 8075 | void intel_write_eld(struct drm_encoder *encoder, |
| 8076 | struct drm_display_mode *mode) |
| 8077 | { |
| 8078 | struct drm_crtc *crtc = encoder->crtc; |
| 8079 | struct drm_connector *connector; |
| 8080 | struct drm_device *dev = encoder->dev; |
| 8081 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8082 | |
| 8083 | connector = drm_select_eld(encoder, mode); |
| 8084 | if (!connector) |
| 8085 | return; |
| 8086 | |
| 8087 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 8088 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 8089 | connector->name, |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8090 | connector->encoder->base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 8091 | connector->encoder->name); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8092 | |
| 8093 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
| 8094 | |
| 8095 | if (dev_priv->display.write_eld) |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 8096 | dev_priv->display.write_eld(connector, crtc, mode); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 8097 | } |
| 8098 | |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8099 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
| 8100 | { |
| 8101 | struct drm_device *dev = crtc->dev; |
| 8102 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8104 | uint32_t cntl = 0, size = 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8105 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8106 | if (base) { |
| 8107 | unsigned int width = intel_crtc->cursor_width; |
| 8108 | unsigned int height = intel_crtc->cursor_height; |
| 8109 | unsigned int stride = roundup_pow_of_two(width) * 4; |
| 8110 | |
| 8111 | switch (stride) { |
| 8112 | default: |
| 8113 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", |
| 8114 | width, stride); |
| 8115 | stride = 256; |
| 8116 | /* fallthrough */ |
| 8117 | case 256: |
| 8118 | case 512: |
| 8119 | case 1024: |
| 8120 | case 2048: |
| 8121 | break; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8122 | } |
| 8123 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8124 | cntl |= CURSOR_ENABLE | |
| 8125 | CURSOR_GAMMA_ENABLE | |
| 8126 | CURSOR_FORMAT_ARGB | |
| 8127 | CURSOR_STRIDE(stride); |
| 8128 | |
| 8129 | size = (height << 12) | width; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8130 | } |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8131 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8132 | if (intel_crtc->cursor_cntl != 0 && |
| 8133 | (intel_crtc->cursor_base != base || |
| 8134 | intel_crtc->cursor_size != size || |
| 8135 | intel_crtc->cursor_cntl != cntl)) { |
| 8136 | /* On these chipsets we can only modify the base/size/stride |
| 8137 | * whilst the cursor is disabled. |
| 8138 | */ |
| 8139 | I915_WRITE(_CURACNTR, 0); |
| 8140 | POSTING_READ(_CURACNTR); |
| 8141 | intel_crtc->cursor_cntl = 0; |
| 8142 | } |
| 8143 | |
| 8144 | if (intel_crtc->cursor_base != base) |
| 8145 | I915_WRITE(_CURABASE, base); |
| 8146 | |
| 8147 | if (intel_crtc->cursor_size != size) { |
| 8148 | I915_WRITE(CURSIZE, size); |
| 8149 | intel_crtc->cursor_size = size; |
| 8150 | } |
| 8151 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8152 | if (intel_crtc->cursor_cntl != cntl) { |
| 8153 | I915_WRITE(_CURACNTR, cntl); |
| 8154 | POSTING_READ(_CURACNTR); |
| 8155 | intel_crtc->cursor_cntl = cntl; |
| 8156 | } |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8157 | } |
| 8158 | |
| 8159 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
| 8160 | { |
| 8161 | struct drm_device *dev = crtc->dev; |
| 8162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8164 | int pipe = intel_crtc->pipe; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8165 | uint32_t cntl; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8166 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8167 | cntl = 0; |
| 8168 | if (base) { |
| 8169 | cntl = MCURSOR_GAMMA_ENABLE; |
| 8170 | switch (intel_crtc->cursor_width) { |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 8171 | case 64: |
| 8172 | cntl |= CURSOR_MODE_64_ARGB_AX; |
| 8173 | break; |
| 8174 | case 128: |
| 8175 | cntl |= CURSOR_MODE_128_ARGB_AX; |
| 8176 | break; |
| 8177 | case 256: |
| 8178 | cntl |= CURSOR_MODE_256_ARGB_AX; |
| 8179 | break; |
| 8180 | default: |
| 8181 | WARN_ON(1); |
| 8182 | return; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8183 | } |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8184 | cntl |= pipe << 28; /* Connect to correct pipe */ |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 8185 | } |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8186 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 8187 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
| 8188 | |
| 8189 | if (intel_crtc->cursor_cntl != cntl) { |
| 8190 | I915_WRITE(CURCNTR(pipe), cntl); |
| 8191 | POSTING_READ(CURCNTR(pipe)); |
| 8192 | intel_crtc->cursor_cntl = cntl; |
| 8193 | } |
| 8194 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 8195 | /* and commit changes on next vblank */ |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 8196 | I915_WRITE(CURBASE(pipe), base); |
| 8197 | POSTING_READ(CURBASE(pipe)); |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 8198 | } |
| 8199 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8200 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 8201 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 8202 | bool on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8203 | { |
| 8204 | struct drm_device *dev = crtc->dev; |
| 8205 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8207 | int pipe = intel_crtc->pipe; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 8208 | int x = crtc->cursor_x; |
| 8209 | int y = crtc->cursor_y; |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 8210 | u32 base = 0, pos = 0; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8211 | |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 8212 | if (on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8213 | base = intel_crtc->cursor_addr; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8214 | |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 8215 | if (x >= intel_crtc->config.pipe_src_w) |
| 8216 | base = 0; |
| 8217 | |
| 8218 | if (y >= intel_crtc->config.pipe_src_h) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8219 | base = 0; |
| 8220 | |
| 8221 | if (x < 0) { |
Ville Syrjälä | efc9064 | 2013-09-04 18:25:30 +0300 | [diff] [blame] | 8222 | if (x + intel_crtc->cursor_width <= 0) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8223 | base = 0; |
| 8224 | |
| 8225 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 8226 | x = -x; |
| 8227 | } |
| 8228 | pos |= x << CURSOR_X_SHIFT; |
| 8229 | |
| 8230 | if (y < 0) { |
Ville Syrjälä | efc9064 | 2013-09-04 18:25:30 +0300 | [diff] [blame] | 8231 | if (y + intel_crtc->cursor_height <= 0) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8232 | base = 0; |
| 8233 | |
| 8234 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 8235 | y = -y; |
| 8236 | } |
| 8237 | pos |= y << CURSOR_Y_SHIFT; |
| 8238 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8239 | if (base == 0 && intel_crtc->cursor_base == 0) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8240 | return; |
| 8241 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 8242 | I915_WRITE(CURPOS(pipe), pos); |
| 8243 | |
Ville Syrjälä | 8ac5466 | 2014-08-12 19:39:54 +0300 | [diff] [blame] | 8244 | if (IS_845G(dev) || IS_I865G(dev)) |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 8245 | i845_update_cursor(crtc, base); |
| 8246 | else |
| 8247 | i9xx_update_cursor(crtc, base); |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 8248 | intel_crtc->cursor_base = base; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8249 | } |
| 8250 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8251 | static bool cursor_size_ok(struct drm_device *dev, |
| 8252 | uint32_t width, uint32_t height) |
| 8253 | { |
| 8254 | if (width == 0 || height == 0) |
| 8255 | return false; |
| 8256 | |
| 8257 | /* |
| 8258 | * 845g/865g are special in that they are only limited by |
| 8259 | * the width of their cursors, the height is arbitrary up to |
| 8260 | * the precision of the register. Everything else requires |
| 8261 | * square cursors, limited to a few power-of-two sizes. |
| 8262 | */ |
| 8263 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 8264 | if ((width & 63) != 0) |
| 8265 | return false; |
| 8266 | |
| 8267 | if (width > (IS_845G(dev) ? 64 : 512)) |
| 8268 | return false; |
| 8269 | |
| 8270 | if (height > 1023) |
| 8271 | return false; |
| 8272 | } else { |
| 8273 | switch (width | height) { |
| 8274 | case 256: |
| 8275 | case 128: |
| 8276 | if (IS_GEN2(dev)) |
| 8277 | return false; |
| 8278 | case 64: |
| 8279 | break; |
| 8280 | default: |
| 8281 | return false; |
| 8282 | } |
| 8283 | } |
| 8284 | |
| 8285 | return true; |
| 8286 | } |
| 8287 | |
Matt Roper | e328795 | 2014-06-10 08:28:12 -0700 | [diff] [blame] | 8288 | /* |
| 8289 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object |
| 8290 | * |
| 8291 | * Note that the object's reference will be consumed if the update fails. If |
| 8292 | * the update succeeds, the reference of the old object (if any) will be |
| 8293 | * consumed. |
| 8294 | */ |
| 8295 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, |
| 8296 | struct drm_i915_gem_object *obj, |
| 8297 | uint32_t width, uint32_t height) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8298 | { |
| 8299 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8300 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 8301 | enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8302 | unsigned old_width, stride; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8303 | uint32_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8304 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8305 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8306 | /* if we want to turn off the cursor ignore width and height */ |
Matt Roper | e328795 | 2014-06-10 08:28:12 -0700 | [diff] [blame] | 8307 | if (!obj) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 8308 | DRM_DEBUG_KMS("cursor off\n"); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8309 | addr = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 8310 | obj = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 8311 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8312 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8313 | } |
| 8314 | |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 8315 | /* Check for which cursor types we support */ |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8316 | if (!cursor_size_ok(dev, width, height)) { |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 8317 | DRM_DEBUG("Cursor dimension not supported\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8318 | return -EINVAL; |
| 8319 | } |
| 8320 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 8321 | stride = roundup_pow_of_two(width) * 4; |
| 8322 | if (obj->base.size < stride * height) { |
Matt Roper | e328795 | 2014-06-10 08:28:12 -0700 | [diff] [blame] | 8323 | DRM_DEBUG_KMS("buffer is too small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 8324 | ret = -ENOMEM; |
| 8325 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8326 | } |
| 8327 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 8328 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 8329 | mutex_lock(&dev->struct_mutex); |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 8330 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 8331 | unsigned alignment; |
| 8332 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 8333 | if (obj->tiling_mode) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 8334 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 8335 | ret = -EINVAL; |
| 8336 | goto fail_locked; |
| 8337 | } |
| 8338 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 8339 | /* Note that the w/a also requires 2 PTE of padding following |
| 8340 | * the bo. We currently fill all unused PTE with the shadow |
| 8341 | * page and so we should always have valid PTE following the |
| 8342 | * cursor preventing the VT-d warning. |
| 8343 | */ |
| 8344 | alignment = 0; |
| 8345 | if (need_vtd_wa(dev)) |
| 8346 | alignment = 64*1024; |
| 8347 | |
| 8348 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 8349 | if (ret) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 8350 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 8351 | goto fail_locked; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 8352 | } |
| 8353 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 8354 | ret = i915_gem_object_put_fence(obj); |
| 8355 | if (ret) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 8356 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 8357 | goto fail_unpin; |
| 8358 | } |
| 8359 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 8360 | addr = i915_gem_obj_ggtt_offset(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 8361 | } else { |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 8362 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 8363 | ret = i915_gem_object_attach_phys(obj, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 8364 | if (ret) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 8365 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 8366 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 8367 | } |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 8368 | addr = obj->phys_handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8369 | } |
| 8370 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8371 | finish: |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8372 | if (intel_crtc->cursor_bo) { |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 8373 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 8374 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8375 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 8376 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 8377 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
| 8378 | INTEL_FRONTBUFFER_CURSOR(pipe)); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 8379 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8380 | |
Chris Wilson | 64f962e | 2014-03-26 12:38:15 +0000 | [diff] [blame] | 8381 | old_width = intel_crtc->cursor_width; |
| 8382 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8383 | intel_crtc->cursor_addr = addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 8384 | intel_crtc->cursor_bo = obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 8385 | intel_crtc->cursor_width = width; |
| 8386 | intel_crtc->cursor_height = height; |
| 8387 | |
Chris Wilson | 64f962e | 2014-03-26 12:38:15 +0000 | [diff] [blame] | 8388 | if (intel_crtc->active) { |
| 8389 | if (old_width != width) |
| 8390 | intel_update_watermarks(crtc); |
Ville Syrjälä | f2f5f771 | 2013-09-17 18:33:44 +0300 | [diff] [blame] | 8391 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
Chris Wilson | 64f962e | 2014-03-26 12:38:15 +0000 | [diff] [blame] | 8392 | } |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 8393 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 8394 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
| 8395 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8396 | return 0; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 8397 | fail_unpin: |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 8398 | i915_gem_object_unpin_from_display_plane(obj); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 8399 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 8400 | mutex_unlock(&dev->struct_mutex); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 8401 | fail: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 8402 | drm_gem_object_unreference_unlocked(&obj->base); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 8403 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8404 | } |
| 8405 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8406 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 8407 | u16 *blue, uint32_t start, uint32_t size) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8408 | { |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 8409 | int end = (start + size > 256) ? 256 : start + size, i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8411 | |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 8412 | for (i = start; i < end; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8413 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 8414 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 8415 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 8416 | } |
| 8417 | |
| 8418 | intel_crtc_load_lut(crtc); |
| 8419 | } |
| 8420 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8421 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 8422 | static struct drm_display_mode load_detect_mode = { |
| 8423 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 8424 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 8425 | }; |
| 8426 | |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 8427 | struct drm_framebuffer * |
| 8428 | __intel_framebuffer_create(struct drm_device *dev, |
| 8429 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 8430 | struct drm_i915_gem_object *obj) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8431 | { |
| 8432 | struct intel_framebuffer *intel_fb; |
| 8433 | int ret; |
| 8434 | |
| 8435 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 8436 | if (!intel_fb) { |
| 8437 | drm_gem_object_unreference_unlocked(&obj->base); |
| 8438 | return ERR_PTR(-ENOMEM); |
| 8439 | } |
| 8440 | |
| 8441 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 8442 | if (ret) |
| 8443 | goto err; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8444 | |
| 8445 | return &intel_fb->base; |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 8446 | err: |
| 8447 | drm_gem_object_unreference_unlocked(&obj->base); |
| 8448 | kfree(intel_fb); |
| 8449 | |
| 8450 | return ERR_PTR(ret); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8451 | } |
| 8452 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 8453 | static struct drm_framebuffer * |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 8454 | intel_framebuffer_create(struct drm_device *dev, |
| 8455 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 8456 | struct drm_i915_gem_object *obj) |
| 8457 | { |
| 8458 | struct drm_framebuffer *fb; |
| 8459 | int ret; |
| 8460 | |
| 8461 | ret = i915_mutex_lock_interruptible(dev); |
| 8462 | if (ret) |
| 8463 | return ERR_PTR(ret); |
| 8464 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
| 8465 | mutex_unlock(&dev->struct_mutex); |
| 8466 | |
| 8467 | return fb; |
| 8468 | } |
| 8469 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8470 | static u32 |
| 8471 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 8472 | { |
| 8473 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 8474 | return ALIGN(pitch, 64); |
| 8475 | } |
| 8476 | |
| 8477 | static u32 |
| 8478 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 8479 | { |
| 8480 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
Fabian Frederick | 1267a26 | 2014-07-01 20:39:41 +0200 | [diff] [blame] | 8481 | return PAGE_ALIGN(pitch * mode->vdisplay); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8482 | } |
| 8483 | |
| 8484 | static struct drm_framebuffer * |
| 8485 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 8486 | struct drm_display_mode *mode, |
| 8487 | int depth, int bpp) |
| 8488 | { |
| 8489 | struct drm_i915_gem_object *obj; |
Chris Wilson | 0fed39b | 2012-11-05 22:25:07 +0000 | [diff] [blame] | 8490 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8491 | |
| 8492 | obj = i915_gem_alloc_object(dev, |
| 8493 | intel_framebuffer_size_for_mode(mode, bpp)); |
| 8494 | if (obj == NULL) |
| 8495 | return ERR_PTR(-ENOMEM); |
| 8496 | |
| 8497 | mode_cmd.width = mode->hdisplay; |
| 8498 | mode_cmd.height = mode->vdisplay; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 8499 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 8500 | bpp); |
Dave Airlie | 5ca0c34 | 2012-02-23 15:33:40 +0000 | [diff] [blame] | 8501 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8502 | |
| 8503 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
| 8504 | } |
| 8505 | |
| 8506 | static struct drm_framebuffer * |
| 8507 | mode_fits_in_fbdev(struct drm_device *dev, |
| 8508 | struct drm_display_mode *mode) |
| 8509 | { |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 8510 | #ifdef CONFIG_DRM_I915_FBDEV |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8511 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8512 | struct drm_i915_gem_object *obj; |
| 8513 | struct drm_framebuffer *fb; |
| 8514 | |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 8515 | if (!dev_priv->fbdev) |
| 8516 | return NULL; |
| 8517 | |
| 8518 | if (!dev_priv->fbdev->fb) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8519 | return NULL; |
| 8520 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 8521 | obj = dev_priv->fbdev->fb->obj; |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 8522 | BUG_ON(!obj); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8523 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 8524 | fb = &dev_priv->fbdev->fb->base; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 8525 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 8526 | fb->bits_per_pixel)) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8527 | return NULL; |
| 8528 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 8529 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8530 | return NULL; |
| 8531 | |
| 8532 | return fb; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 8533 | #else |
| 8534 | return NULL; |
| 8535 | #endif |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8536 | } |
| 8537 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 8538 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8539 | struct drm_display_mode *mode, |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8540 | struct intel_load_detect_pipe *old, |
| 8541 | struct drm_modeset_acquire_ctx *ctx) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8542 | { |
| 8543 | struct intel_crtc *intel_crtc; |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 8544 | struct intel_encoder *intel_encoder = |
| 8545 | intel_attached_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8546 | struct drm_crtc *possible_crtc; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 8547 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8548 | struct drm_crtc *crtc = NULL; |
| 8549 | struct drm_device *dev = encoder->dev; |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8550 | struct drm_framebuffer *fb; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8551 | struct drm_mode_config *config = &dev->mode_config; |
| 8552 | int ret, i = -1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8553 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8554 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 8555 | connector->base.id, connector->name, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 8556 | encoder->base.id, encoder->name); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8557 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8558 | retry: |
| 8559 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
| 8560 | if (ret) |
| 8561 | goto fail_unlock; |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 8562 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8563 | /* |
| 8564 | * Algorithm gets a little messy: |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 8565 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8566 | * - if the connector already has an assigned crtc, use it (but make |
| 8567 | * sure it's on first) |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 8568 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8569 | * - try to find the first unused crtc that can drive this connector, |
| 8570 | * and use that if we find one |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8571 | */ |
| 8572 | |
| 8573 | /* See if we already have a CRTC for this connector */ |
| 8574 | if (encoder->crtc) { |
| 8575 | crtc = encoder->crtc; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8576 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8577 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 8578 | if (ret) |
| 8579 | goto fail_unlock; |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 8580 | |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8581 | old->dpms_mode = connector->dpms; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8582 | old->load_detect_temp = false; |
| 8583 | |
| 8584 | /* Make sure the crtc and connector are running */ |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8585 | if (connector->dpms != DRM_MODE_DPMS_ON) |
| 8586 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8587 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8588 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8589 | } |
| 8590 | |
| 8591 | /* Find an unused one (if possible) */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 8592 | for_each_crtc(dev, possible_crtc) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8593 | i++; |
| 8594 | if (!(encoder->possible_crtcs & (1 << i))) |
| 8595 | continue; |
Ville Syrjälä | a459249 | 2014-08-11 13:15:36 +0300 | [diff] [blame] | 8596 | if (possible_crtc->enabled) |
| 8597 | continue; |
| 8598 | /* This can occur when applying the pipe A quirk on resume. */ |
| 8599 | if (to_intel_crtc(possible_crtc)->new_enabled) |
| 8600 | continue; |
| 8601 | |
| 8602 | crtc = possible_crtc; |
| 8603 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8604 | } |
| 8605 | |
| 8606 | /* |
| 8607 | * If we didn't find an unused CRTC, don't use any. |
| 8608 | */ |
| 8609 | if (!crtc) { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8610 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8611 | goto fail_unlock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8612 | } |
| 8613 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8614 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 8615 | if (ret) |
| 8616 | goto fail_unlock; |
Daniel Vetter | fc30310 | 2012-07-09 10:40:58 +0200 | [diff] [blame] | 8617 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
| 8618 | to_intel_connector(connector)->new_encoder = intel_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8619 | |
| 8620 | intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8621 | intel_crtc->new_enabled = true; |
| 8622 | intel_crtc->new_config = &intel_crtc->config; |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8623 | old->dpms_mode = connector->dpms; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8624 | old->load_detect_temp = true; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8625 | old->release_fb = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8626 | |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 8627 | if (!mode) |
| 8628 | mode = &load_detect_mode; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8629 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8630 | /* We need a framebuffer large enough to accommodate all accesses |
| 8631 | * that the plane may generate whilst we perform load detection. |
| 8632 | * We can not rely on the fbcon either being present (we get called |
| 8633 | * during its initialisation to detect all boot displays, or it may |
| 8634 | * not even exist) or that it is large enough to satisfy the |
| 8635 | * requested mode. |
| 8636 | */ |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8637 | fb = mode_fits_in_fbdev(dev, mode); |
| 8638 | if (fb == NULL) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8639 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8640 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
| 8641 | old->release_fb = fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8642 | } else |
| 8643 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8644 | if (IS_ERR(fb)) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8645 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8646 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8647 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8648 | |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 8649 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 8650 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8651 | if (old->release_fb) |
| 8652 | old->release_fb->funcs->destroy(old->release_fb); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8653 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8654 | } |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8655 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8656 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 8657 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8658 | return true; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8659 | |
| 8660 | fail: |
| 8661 | intel_crtc->new_enabled = crtc->enabled; |
| 8662 | if (intel_crtc->new_enabled) |
| 8663 | intel_crtc->new_config = &intel_crtc->config; |
| 8664 | else |
| 8665 | intel_crtc->new_config = NULL; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 8666 | fail_unlock: |
| 8667 | if (ret == -EDEADLK) { |
| 8668 | drm_modeset_backoff(ctx); |
| 8669 | goto retry; |
| 8670 | } |
| 8671 | |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8672 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8673 | } |
| 8674 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 8675 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 8676 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8677 | { |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 8678 | struct intel_encoder *intel_encoder = |
| 8679 | intel_attached_encoder(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 8680 | struct drm_encoder *encoder = &intel_encoder->base; |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 8681 | struct drm_crtc *crtc = encoder->crtc; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8682 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8683 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8684 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 8685 | connector->base.id, connector->name, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 8686 | encoder->base.id, encoder->name); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8687 | |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8688 | if (old->load_detect_temp) { |
Daniel Vetter | fc30310 | 2012-07-09 10:40:58 +0200 | [diff] [blame] | 8689 | to_intel_connector(connector)->new_encoder = NULL; |
| 8690 | intel_encoder->new_crtc = NULL; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8691 | intel_crtc->new_enabled = false; |
| 8692 | intel_crtc->new_config = NULL; |
Daniel Vetter | fc30310 | 2012-07-09 10:40:58 +0200 | [diff] [blame] | 8693 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8694 | |
Daniel Vetter | 3620636 | 2012-12-10 20:42:17 +0100 | [diff] [blame] | 8695 | if (old->release_fb) { |
| 8696 | drm_framebuffer_unregister_private(old->release_fb); |
| 8697 | drm_framebuffer_unreference(old->release_fb); |
| 8698 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8699 | |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 8700 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8701 | } |
| 8702 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 8703 | /* Switch crtc and encoder back off if necessary */ |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8704 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
| 8705 | connector->funcs->dpms(connector, old->dpms_mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8706 | } |
| 8707 | |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8708 | static int i9xx_pll_refclk(struct drm_device *dev, |
| 8709 | const struct intel_crtc_config *pipe_config) |
| 8710 | { |
| 8711 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8712 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 8713 | |
| 8714 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 8715 | return dev_priv->vbt.lvds_ssc_freq; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8716 | else if (HAS_PCH_SPLIT(dev)) |
| 8717 | return 120000; |
| 8718 | else if (!IS_GEN2(dev)) |
| 8719 | return 96000; |
| 8720 | else |
| 8721 | return 48000; |
| 8722 | } |
| 8723 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8724 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8725 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 8726 | struct intel_crtc_config *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8727 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8728 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8729 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8730 | int pipe = pipe_config->cpu_transcoder; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8731 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8732 | u32 fp; |
| 8733 | intel_clock_t clock; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8734 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8735 | |
| 8736 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8737 | fp = pipe_config->dpll_hw_state.fp0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8738 | else |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8739 | fp = pipe_config->dpll_hw_state.fp1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8740 | |
| 8741 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 8742 | if (IS_PINEVIEW(dev)) { |
| 8743 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 8744 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 8745 | } else { |
| 8746 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 8747 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 8748 | } |
| 8749 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 8750 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 8751 | if (IS_PINEVIEW(dev)) |
| 8752 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 8753 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 8754 | else |
| 8755 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8756 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 8757 | |
| 8758 | switch (dpll & DPLL_MODE_MASK) { |
| 8759 | case DPLLB_MODE_DAC_SERIAL: |
| 8760 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 8761 | 5 : 10; |
| 8762 | break; |
| 8763 | case DPLLB_MODE_LVDS: |
| 8764 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 8765 | 7 : 14; |
| 8766 | break; |
| 8767 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 8768 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8769 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8770 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8771 | } |
| 8772 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 8773 | if (IS_PINEVIEW(dev)) |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8774 | pineview_clock(refclk, &clock); |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 8775 | else |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8776 | i9xx_clock(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8777 | } else { |
Ville Syrjälä | 0fb5822 | 2014-01-10 14:06:46 +0200 | [diff] [blame] | 8778 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 8779 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8780 | |
| 8781 | if (is_lvds) { |
| 8782 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 8783 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 8784 | |
| 8785 | if (lvds & LVDS_CLKB_POWER_UP) |
| 8786 | clock.p2 = 7; |
| 8787 | else |
| 8788 | clock.p2 = 14; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8789 | } else { |
| 8790 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 8791 | clock.p1 = 2; |
| 8792 | else { |
| 8793 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 8794 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 8795 | } |
| 8796 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 8797 | clock.p2 = 4; |
| 8798 | else |
| 8799 | clock.p2 = 2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8800 | } |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8801 | |
| 8802 | i9xx_clock(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8803 | } |
| 8804 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8805 | /* |
| 8806 | * This value includes pixel_multiplier. We will use |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 8807 | * port_clock to compute adjusted_mode.crtc_clock in the |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8808 | * encoder's get_config() function. |
| 8809 | */ |
| 8810 | pipe_config->port_clock = clock.dot; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8811 | } |
| 8812 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8813 | int intel_dotclock_calculate(int link_freq, |
| 8814 | const struct intel_link_m_n *m_n) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8815 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8816 | /* |
| 8817 | * The calculation for the data clock is: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 8818 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8819 | * But we want to avoid losing precison if possible, so: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 8820 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8821 | * |
| 8822 | * and the link clock is simpler: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 8823 | * link_clock = (m * link_clock) / n |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8824 | */ |
| 8825 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8826 | if (!m_n->link_n) |
| 8827 | return 0; |
| 8828 | |
| 8829 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
| 8830 | } |
| 8831 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8832 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
| 8833 | struct intel_crtc_config *pipe_config) |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8834 | { |
| 8835 | struct drm_device *dev = crtc->base.dev; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8836 | |
| 8837 | /* read out port_clock from the DPLL */ |
| 8838 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8839 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8840 | /* |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8841 | * This value does not include pixel_multiplier. |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 8842 | * We will check that port_clock and adjusted_mode.crtc_clock |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8843 | * agree once we know their relationship in the encoder's |
| 8844 | * get_config() function. |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8845 | */ |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 8846 | pipe_config->adjusted_mode.crtc_clock = |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8847 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
| 8848 | &pipe_config->fdi_m_n); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8849 | } |
| 8850 | |
| 8851 | /** Returns the currently programmed mode of the given pipe. */ |
| 8852 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 8853 | struct drm_crtc *crtc) |
| 8854 | { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 8855 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 8857 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8858 | struct drm_display_mode *mode; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8859 | struct intel_crtc_config pipe_config; |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8860 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
| 8861 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 8862 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
| 8863 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8864 | enum pipe pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8865 | |
| 8866 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 8867 | if (!mode) |
| 8868 | return NULL; |
| 8869 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8870 | /* |
| 8871 | * Construct a pipe_config sufficient for getting the clock info |
| 8872 | * back out of crtc_clock_get. |
| 8873 | * |
| 8874 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
| 8875 | * to use a real value here instead. |
| 8876 | */ |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8877 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8878 | pipe_config.pixel_multiplier = 1; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8879 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
| 8880 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
| 8881 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8882 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
| 8883 | |
Ville Syrjälä | 773ae03 | 2013-09-23 17:48:20 +0300 | [diff] [blame] | 8884 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8885 | mode->hdisplay = (htot & 0xffff) + 1; |
| 8886 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 8887 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 8888 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 8889 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 8890 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 8891 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 8892 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 8893 | |
| 8894 | drm_mode_set_name(mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8895 | |
| 8896 | return mode; |
| 8897 | } |
| 8898 | |
Daniel Vetter | cc36513 | 2014-06-18 13:59:13 +0200 | [diff] [blame] | 8899 | static void intel_increase_pllclock(struct drm_device *dev, |
| 8900 | enum pipe pipe) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8901 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 8902 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 8903 | int dpll_reg = DPLL(pipe); |
| 8904 | int dpll; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8905 | |
Sonika Jindal | baff296 | 2014-07-22 11:16:35 +0530 | [diff] [blame] | 8906 | if (!HAS_GMCH_DISPLAY(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8907 | return; |
| 8908 | |
| 8909 | if (!dev_priv->lvds_downclock_avail) |
| 8910 | return; |
| 8911 | |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 8912 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8913 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8914 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8915 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 8916 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8917 | |
| 8918 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 8919 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 8920 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 8921 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8922 | dpll = I915_READ(dpll_reg); |
| 8923 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8924 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8925 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8926 | } |
| 8927 | |
| 8928 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 8929 | { |
| 8930 | struct drm_device *dev = crtc->dev; |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 8931 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8932 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8933 | |
Sonika Jindal | baff296 | 2014-07-22 11:16:35 +0530 | [diff] [blame] | 8934 | if (!HAS_GMCH_DISPLAY(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8935 | return; |
| 8936 | |
| 8937 | if (!dev_priv->lvds_downclock_avail) |
| 8938 | return; |
| 8939 | |
| 8940 | /* |
| 8941 | * Since this is called by a timer, we should never get here in |
| 8942 | * the manual case. |
| 8943 | */ |
| 8944 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Chris Wilson | 074b5e1 | 2012-05-02 12:07:06 +0100 | [diff] [blame] | 8945 | int pipe = intel_crtc->pipe; |
| 8946 | int dpll_reg = DPLL(pipe); |
Daniel Vetter | dc257cf | 2012-05-07 11:30:46 +0200 | [diff] [blame] | 8947 | int dpll; |
Chris Wilson | 074b5e1 | 2012-05-02 12:07:06 +0100 | [diff] [blame] | 8948 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8949 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8950 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 8951 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8952 | |
Chris Wilson | 074b5e1 | 2012-05-02 12:07:06 +0100 | [diff] [blame] | 8953 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8954 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 8955 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 8956 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8957 | dpll = I915_READ(dpll_reg); |
| 8958 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8959 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8960 | } |
| 8961 | |
| 8962 | } |
| 8963 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 8964 | void intel_mark_busy(struct drm_device *dev) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8965 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 8966 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8967 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 8968 | if (dev_priv->mm.busy) |
| 8969 | return; |
| 8970 | |
Paulo Zanoni | 43694d6 | 2014-03-07 20:08:08 -0300 | [diff] [blame] | 8971 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 8972 | i915_update_gfx_val(dev_priv); |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 8973 | dev_priv->mm.busy = true; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 8974 | } |
| 8975 | |
| 8976 | void intel_mark_idle(struct drm_device *dev) |
| 8977 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 8978 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 725a5b5 | 2013-01-08 11:02:57 +0000 | [diff] [blame] | 8979 | struct drm_crtc *crtc; |
| 8980 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 8981 | if (!dev_priv->mm.busy) |
| 8982 | return; |
| 8983 | |
| 8984 | dev_priv->mm.busy = false; |
| 8985 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 8986 | if (!i915.powersave) |
Paulo Zanoni | bb4cdd5 | 2014-02-21 13:52:19 -0300 | [diff] [blame] | 8987 | goto out; |
Chris Wilson | 725a5b5 | 2013-01-08 11:02:57 +0000 | [diff] [blame] | 8988 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 8989 | for_each_crtc(dev, crtc) { |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 8990 | if (!crtc->primary->fb) |
Chris Wilson | 725a5b5 | 2013-01-08 11:02:57 +0000 | [diff] [blame] | 8991 | continue; |
| 8992 | |
| 8993 | intel_decrease_pllclock(crtc); |
| 8994 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 8995 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 8996 | if (INTEL_INFO(dev)->gen >= 6) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 8997 | gen6_rps_idle(dev->dev_private); |
Paulo Zanoni | bb4cdd5 | 2014-02-21 13:52:19 -0300 | [diff] [blame] | 8998 | |
| 8999 | out: |
Paulo Zanoni | 43694d6 | 2014-03-07 20:08:08 -0300 | [diff] [blame] | 9000 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 9001 | } |
| 9002 | |
Rodrigo Vivi | 7c8f8a7 | 2014-06-13 05:10:03 -0700 | [diff] [blame] | 9003 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9004 | /** |
| 9005 | * intel_mark_fb_busy - mark given planes as busy |
| 9006 | * @dev: DRM device |
| 9007 | * @frontbuffer_bits: bits for the affected planes |
| 9008 | * @ring: optional ring for asynchronous commands |
| 9009 | * |
| 9010 | * This function gets called every time the screen contents change. It can be |
| 9011 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. |
| 9012 | */ |
| 9013 | static void intel_mark_fb_busy(struct drm_device *dev, |
| 9014 | unsigned frontbuffer_bits, |
| 9015 | struct intel_engine_cs *ring) |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 9016 | { |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 9017 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | cc36513 | 2014-06-18 13:59:13 +0200 | [diff] [blame] | 9018 | enum pipe pipe; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9019 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 9020 | if (!i915.powersave) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9021 | return; |
| 9022 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 9023 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9024 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9025 | continue; |
| 9026 | |
Daniel Vetter | cc36513 | 2014-06-18 13:59:13 +0200 | [diff] [blame] | 9027 | intel_increase_pllclock(dev, pipe); |
Chris Wilson | c65355b | 2013-06-06 16:53:41 -0300 | [diff] [blame] | 9028 | if (ring && intel_fbc_enabled(dev)) |
| 9029 | ring->fbc_dirty = true; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9030 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 9031 | } |
| 9032 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9033 | /** |
| 9034 | * intel_fb_obj_invalidate - invalidate frontbuffer object |
| 9035 | * @obj: GEM object to invalidate |
| 9036 | * @ring: set for asynchronous rendering |
| 9037 | * |
| 9038 | * This function gets called every time rendering on the given object starts and |
| 9039 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must |
| 9040 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed |
| 9041 | * until the rendering completes or a flip on this frontbuffer plane is |
| 9042 | * scheduled. |
| 9043 | */ |
| 9044 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
| 9045 | struct intel_engine_cs *ring) |
| 9046 | { |
| 9047 | struct drm_device *dev = obj->base.dev; |
| 9048 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9049 | |
| 9050 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 9051 | |
| 9052 | if (!obj->frontbuffer_bits) |
| 9053 | return; |
| 9054 | |
| 9055 | if (ring) { |
| 9056 | mutex_lock(&dev_priv->fb_tracking.lock); |
| 9057 | dev_priv->fb_tracking.busy_bits |
| 9058 | |= obj->frontbuffer_bits; |
| 9059 | dev_priv->fb_tracking.flip_bits |
| 9060 | &= ~obj->frontbuffer_bits; |
| 9061 | mutex_unlock(&dev_priv->fb_tracking.lock); |
| 9062 | } |
| 9063 | |
| 9064 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); |
| 9065 | |
Daniel Vetter | 9ca1530 | 2014-07-11 10:30:16 -0700 | [diff] [blame] | 9066 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9067 | } |
| 9068 | |
| 9069 | /** |
| 9070 | * intel_frontbuffer_flush - flush frontbuffer |
| 9071 | * @dev: DRM device |
| 9072 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 9073 | * |
| 9074 | * This function gets called every time rendering on the given planes has |
| 9075 | * completed and frontbuffer caching can be started again. Flushes will get |
| 9076 | * delayed if they're blocked by some oustanding asynchronous rendering. |
| 9077 | * |
| 9078 | * Can be called without any locks held. |
| 9079 | */ |
| 9080 | void intel_frontbuffer_flush(struct drm_device *dev, |
| 9081 | unsigned frontbuffer_bits) |
| 9082 | { |
| 9083 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9084 | |
| 9085 | /* Delay flushing when rings are still busy.*/ |
| 9086 | mutex_lock(&dev_priv->fb_tracking.lock); |
| 9087 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; |
| 9088 | mutex_unlock(&dev_priv->fb_tracking.lock); |
| 9089 | |
| 9090 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); |
| 9091 | |
Daniel Vetter | 9ca1530 | 2014-07-11 10:30:16 -0700 | [diff] [blame] | 9092 | intel_edp_psr_flush(dev, frontbuffer_bits); |
Rodrigo Vivi | c5ad011 | 2014-08-04 03:51:38 -0700 | [diff] [blame] | 9093 | |
| 9094 | if (IS_GEN8(dev)) |
| 9095 | gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9096 | } |
| 9097 | |
| 9098 | /** |
| 9099 | * intel_fb_obj_flush - flush frontbuffer object |
| 9100 | * @obj: GEM object to flush |
| 9101 | * @retire: set when retiring asynchronous rendering |
| 9102 | * |
| 9103 | * This function gets called every time rendering on the given object has |
| 9104 | * completed and frontbuffer caching can be started again. If @retire is true |
| 9105 | * then any delayed flushes will be unblocked. |
| 9106 | */ |
| 9107 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, |
| 9108 | bool retire) |
| 9109 | { |
| 9110 | struct drm_device *dev = obj->base.dev; |
| 9111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9112 | unsigned frontbuffer_bits; |
| 9113 | |
| 9114 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 9115 | |
| 9116 | if (!obj->frontbuffer_bits) |
| 9117 | return; |
| 9118 | |
| 9119 | frontbuffer_bits = obj->frontbuffer_bits; |
| 9120 | |
| 9121 | if (retire) { |
| 9122 | mutex_lock(&dev_priv->fb_tracking.lock); |
| 9123 | /* Filter out new bits since rendering started. */ |
| 9124 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; |
| 9125 | |
| 9126 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; |
| 9127 | mutex_unlock(&dev_priv->fb_tracking.lock); |
| 9128 | } |
| 9129 | |
| 9130 | intel_frontbuffer_flush(dev, frontbuffer_bits); |
| 9131 | } |
| 9132 | |
| 9133 | /** |
| 9134 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip |
| 9135 | * @dev: DRM device |
| 9136 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 9137 | * |
| 9138 | * This function gets called after scheduling a flip on @obj. The actual |
| 9139 | * frontbuffer flushing will be delayed until completion is signalled with |
| 9140 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this |
| 9141 | * flush will be cancelled. |
| 9142 | * |
| 9143 | * Can be called without any locks held. |
| 9144 | */ |
| 9145 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
| 9146 | unsigned frontbuffer_bits) |
| 9147 | { |
| 9148 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9149 | |
| 9150 | mutex_lock(&dev_priv->fb_tracking.lock); |
| 9151 | dev_priv->fb_tracking.flip_bits |
| 9152 | |= frontbuffer_bits; |
| 9153 | mutex_unlock(&dev_priv->fb_tracking.lock); |
| 9154 | } |
| 9155 | |
| 9156 | /** |
| 9157 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush |
| 9158 | * @dev: DRM device |
| 9159 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 9160 | * |
| 9161 | * This function gets called after the flip has been latched and will complete |
| 9162 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. |
| 9163 | * |
| 9164 | * Can be called without any locks held. |
| 9165 | */ |
| 9166 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
| 9167 | unsigned frontbuffer_bits) |
| 9168 | { |
| 9169 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9170 | |
| 9171 | mutex_lock(&dev_priv->fb_tracking.lock); |
| 9172 | /* Mask any cancelled flips. */ |
| 9173 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; |
| 9174 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; |
| 9175 | mutex_unlock(&dev_priv->fb_tracking.lock); |
| 9176 | |
| 9177 | intel_frontbuffer_flush(dev, frontbuffer_bits); |
| 9178 | } |
| 9179 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9180 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 9181 | { |
| 9182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 9183 | struct drm_device *dev = crtc->dev; |
| 9184 | struct intel_unpin_work *work; |
| 9185 | unsigned long flags; |
| 9186 | |
| 9187 | spin_lock_irqsave(&dev->event_lock, flags); |
| 9188 | work = intel_crtc->unpin_work; |
| 9189 | intel_crtc->unpin_work = NULL; |
| 9190 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9191 | |
| 9192 | if (work) { |
| 9193 | cancel_work_sync(&work->work); |
| 9194 | kfree(work); |
| 9195 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9196 | |
| 9197 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 9198 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9199 | kfree(intel_crtc); |
| 9200 | } |
| 9201 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9202 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 9203 | { |
| 9204 | struct intel_unpin_work *work = |
| 9205 | container_of(__work, struct intel_unpin_work, work); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9206 | struct drm_device *dev = work->crtc->dev; |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9207 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9208 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9209 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 9210 | intel_unpin_fb_obj(work->old_fb_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 9211 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
| 9212 | drm_gem_object_unreference(&work->old_fb_obj->base); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 9213 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9214 | intel_update_fbc(dev); |
| 9215 | mutex_unlock(&dev->struct_mutex); |
| 9216 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9217 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
| 9218 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9219 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
| 9220 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
| 9221 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9222 | kfree(work); |
| 9223 | } |
| 9224 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 9225 | static void do_intel_finish_page_flip(struct drm_device *dev, |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 9226 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9227 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 9228 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 9230 | struct intel_unpin_work *work; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9231 | unsigned long flags; |
| 9232 | |
| 9233 | /* Ignore early vblank irqs */ |
| 9234 | if (intel_crtc == NULL) |
| 9235 | return; |
| 9236 | |
| 9237 | spin_lock_irqsave(&dev->event_lock, flags); |
| 9238 | work = intel_crtc->unpin_work; |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9239 | |
| 9240 | /* Ensure we don't miss a work->pending update ... */ |
| 9241 | smp_rmb(); |
| 9242 | |
| 9243 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9244 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9245 | return; |
| 9246 | } |
| 9247 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9248 | /* and that the unpin work is consistent wrt ->pending. */ |
| 9249 | smp_rmb(); |
| 9250 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9251 | intel_crtc->unpin_work = NULL; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9252 | |
Rob Clark | 45a066e | 2012-10-08 14:50:40 -0500 | [diff] [blame] | 9253 | if (work->event) |
| 9254 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9255 | |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 9256 | drm_crtc_vblank_put(crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 9257 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9258 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9259 | |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 9260 | wake_up_all(&dev_priv->pending_flip_queue); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9261 | |
| 9262 | queue_work(dev_priv->wq, &work->work); |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 9263 | |
| 9264 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9265 | } |
| 9266 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 9267 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 9268 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 9269 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 9270 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 9271 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 9272 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 9273 | } |
| 9274 | |
| 9275 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 9276 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 9277 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 9278 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 9279 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 9280 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 9281 | } |
| 9282 | |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9283 | /* Is 'a' after or equal to 'b'? */ |
| 9284 | static bool g4x_flip_count_after_eq(u32 a, u32 b) |
| 9285 | { |
| 9286 | return !((a - b) & 0x80000000); |
| 9287 | } |
| 9288 | |
| 9289 | static bool page_flip_finished(struct intel_crtc *crtc) |
| 9290 | { |
| 9291 | struct drm_device *dev = crtc->base.dev; |
| 9292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9293 | |
| 9294 | /* |
| 9295 | * The relevant registers doen't exist on pre-ctg. |
| 9296 | * As the flip done interrupt doesn't trigger for mmio |
| 9297 | * flips on gmch platforms, a flip count check isn't |
| 9298 | * really needed there. But since ctg has the registers, |
| 9299 | * include it in the check anyway. |
| 9300 | */ |
| 9301 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
| 9302 | return true; |
| 9303 | |
| 9304 | /* |
| 9305 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
| 9306 | * used the same base address. In that case the mmio flip might |
| 9307 | * have completed, but the CS hasn't even executed the flip yet. |
| 9308 | * |
| 9309 | * A flip count check isn't enough as the CS might have updated |
| 9310 | * the base address just after start of vblank, but before we |
| 9311 | * managed to process the interrupt. This means we'd complete the |
| 9312 | * CS flip too soon. |
| 9313 | * |
| 9314 | * Combining both checks should get us a good enough result. It may |
| 9315 | * still happen that the CS flip has been executed, but has not |
| 9316 | * yet actually completed. But in case the base address is the same |
| 9317 | * anyway, we don't really care. |
| 9318 | */ |
| 9319 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
| 9320 | crtc->unpin_work->gtt_offset && |
| 9321 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), |
| 9322 | crtc->unpin_work->flip_count); |
| 9323 | } |
| 9324 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9325 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 9326 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 9327 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9328 | struct intel_crtc *intel_crtc = |
| 9329 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 9330 | unsigned long flags; |
| 9331 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9332 | /* NB: An MMIO update of the plane base pointer will also |
| 9333 | * generate a page-flip completion irq, i.e. every modeset |
| 9334 | * is also accompanied by a spurious intel_prepare_page_flip(). |
| 9335 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9336 | spin_lock_irqsave(&dev->event_lock, flags); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9337 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9338 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9339 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9340 | } |
| 9341 | |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 9342 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9343 | { |
| 9344 | /* Ensure that the work item is consistent when activating it ... */ |
| 9345 | smp_wmb(); |
| 9346 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
| 9347 | /* and that it is marked active as soon as the irq could fire. */ |
| 9348 | smp_wmb(); |
| 9349 | } |
| 9350 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9351 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 9352 | struct drm_crtc *crtc, |
| 9353 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9354 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9355 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9356 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9357 | { |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9359 | u32 flip_mask; |
| 9360 | int ret; |
| 9361 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9362 | ret = intel_ring_begin(ring, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9363 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9364 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9365 | |
| 9366 | /* Can't queue multiple flips, so wait for the previous |
| 9367 | * one to finish before executing the next. |
| 9368 | */ |
| 9369 | if (intel_crtc->plane) |
| 9370 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 9371 | else |
| 9372 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9373 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 9374 | intel_ring_emit(ring, MI_NOOP); |
| 9375 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 9376 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 9377 | intel_ring_emit(ring, fb->pitches[0]); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9378 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9379 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9380 | |
| 9381 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 9382 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 9383 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9384 | } |
| 9385 | |
| 9386 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 9387 | struct drm_crtc *crtc, |
| 9388 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9389 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9390 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9391 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9392 | { |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9394 | u32 flip_mask; |
| 9395 | int ret; |
| 9396 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9397 | ret = intel_ring_begin(ring, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9398 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9399 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9400 | |
| 9401 | if (intel_crtc->plane) |
| 9402 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 9403 | else |
| 9404 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9405 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 9406 | intel_ring_emit(ring, MI_NOOP); |
| 9407 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
| 9408 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 9409 | intel_ring_emit(ring, fb->pitches[0]); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9410 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9411 | intel_ring_emit(ring, MI_NOOP); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9412 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9413 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 9414 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 9415 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9416 | } |
| 9417 | |
| 9418 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 9419 | struct drm_crtc *crtc, |
| 9420 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9421 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9422 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9423 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9424 | { |
| 9425 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 9427 | uint32_t pf, pipesrc; |
| 9428 | int ret; |
| 9429 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9430 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9431 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9432 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9433 | |
| 9434 | /* i965+ uses the linear or tiled offsets from the |
| 9435 | * Display Registers (which do not change across a page-flip) |
| 9436 | * so we need only reprogram the base address. |
| 9437 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9438 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 9439 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 9440 | intel_ring_emit(ring, fb->pitches[0]); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9441 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 9442 | obj->tiling_mode); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9443 | |
| 9444 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 9445 | * untested on non-native modes, so ignore it for now. |
| 9446 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 9447 | */ |
| 9448 | pf = 0; |
| 9449 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9450 | intel_ring_emit(ring, pf | pipesrc); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9451 | |
| 9452 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 9453 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 9454 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9455 | } |
| 9456 | |
| 9457 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 9458 | struct drm_crtc *crtc, |
| 9459 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9460 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9461 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9462 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9463 | { |
| 9464 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 9466 | uint32_t pf, pipesrc; |
| 9467 | int ret; |
| 9468 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9469 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9470 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9471 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9472 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9473 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 9474 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 9475 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9476 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9477 | |
Chris Wilson | 99d9acd | 2012-04-17 20:37:00 +0100 | [diff] [blame] | 9478 | /* Contrary to the suggestions in the documentation, |
| 9479 | * "Enable Panel Fitter" does not seem to be required when page |
| 9480 | * flipping with a non-native mode, and worse causes a normal |
| 9481 | * modeset to fail. |
| 9482 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 9483 | */ |
| 9484 | pf = 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9485 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 9486 | intel_ring_emit(ring, pf | pipesrc); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9487 | |
| 9488 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 9489 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 9490 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9491 | } |
| 9492 | |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9493 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 9494 | struct drm_crtc *crtc, |
| 9495 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9496 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9497 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9498 | uint32_t flags) |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9499 | { |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9500 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 9501 | uint32_t plane_bit = 0; |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9502 | int len, ret; |
| 9503 | |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 9504 | switch (intel_crtc->plane) { |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 9505 | case PLANE_A: |
| 9506 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
| 9507 | break; |
| 9508 | case PLANE_B: |
| 9509 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
| 9510 | break; |
| 9511 | case PLANE_C: |
| 9512 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
| 9513 | break; |
| 9514 | default: |
| 9515 | WARN_ONCE(1, "unknown plane in flip command\n"); |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9516 | return -ENODEV; |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 9517 | } |
| 9518 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9519 | len = 4; |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 9520 | if (ring->id == RCS) { |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9521 | len += 6; |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 9522 | /* |
| 9523 | * On Gen 8, SRM is now taking an extra dword to accommodate |
| 9524 | * 48bits addresses, and we need a NOOP for the batch size to |
| 9525 | * stay even. |
| 9526 | */ |
| 9527 | if (IS_GEN8(dev)) |
| 9528 | len += 2; |
| 9529 | } |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9530 | |
Ville Syrjälä | f66fab8 | 2014-02-11 19:52:06 +0200 | [diff] [blame] | 9531 | /* |
| 9532 | * BSpec MI_DISPLAY_FLIP for IVB: |
| 9533 | * "The full packet must be contained within the same cache line." |
| 9534 | * |
| 9535 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
| 9536 | * cacheline, if we ever start emitting more commands before |
| 9537 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
| 9538 | * then do the cacheline alignment, and finally emit the |
| 9539 | * MI_DISPLAY_FLIP. |
| 9540 | */ |
| 9541 | ret = intel_ring_cacheline_align(ring); |
| 9542 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9543 | return ret; |
Ville Syrjälä | f66fab8 | 2014-02-11 19:52:06 +0200 | [diff] [blame] | 9544 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9545 | ret = intel_ring_begin(ring, len); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9546 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9547 | return ret; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9548 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9549 | /* Unmask the flip-done completion message. Note that the bspec says that |
| 9550 | * we should do this for both the BCS and RCS, and that we must not unmask |
| 9551 | * more than one flip event at any time (or ensure that one flip message |
| 9552 | * can be sent by waiting for flip-done prior to queueing new flips). |
| 9553 | * Experimentation says that BCS works despite DERRMR masking all |
| 9554 | * flip-done completion events and that unmasking all planes at once |
| 9555 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
| 9556 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
| 9557 | */ |
| 9558 | if (ring->id == RCS) { |
| 9559 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 9560 | intel_ring_emit(ring, DERRMR); |
| 9561 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
| 9562 | DERRMR_PIPEB_PRI_FLIP_DONE | |
| 9563 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 9564 | if (IS_GEN8(dev)) |
| 9565 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | |
| 9566 | MI_SRM_LRM_GLOBAL_GTT); |
| 9567 | else |
| 9568 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
| 9569 | MI_SRM_LRM_GLOBAL_GTT); |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9570 | intel_ring_emit(ring, DERRMR); |
| 9571 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 9572 | if (IS_GEN8(dev)) { |
| 9573 | intel_ring_emit(ring, 0); |
| 9574 | intel_ring_emit(ring, MI_NOOP); |
| 9575 | } |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 9576 | } |
| 9577 | |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 9578 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 9579 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9580 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9581 | intel_ring_emit(ring, (MI_NOOP)); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 9582 | |
| 9583 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 9584 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 9585 | return 0; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 9586 | } |
| 9587 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 9588 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
| 9589 | struct drm_i915_gem_object *obj) |
| 9590 | { |
| 9591 | /* |
| 9592 | * This is not being used for older platforms, because |
| 9593 | * non-availability of flip done interrupt forces us to use |
| 9594 | * CS flips. Older platforms derive flip done using some clever |
| 9595 | * tricks involving the flip_pending status bits and vblank irqs. |
| 9596 | * So using MMIO flips there would disrupt this mechanism. |
| 9597 | */ |
| 9598 | |
Chris Wilson | 8e09bf8 | 2014-07-08 10:40:30 +0100 | [diff] [blame] | 9599 | if (ring == NULL) |
| 9600 | return true; |
| 9601 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 9602 | if (INTEL_INFO(ring->dev)->gen < 5) |
| 9603 | return false; |
| 9604 | |
| 9605 | if (i915.use_mmio_flip < 0) |
| 9606 | return false; |
| 9607 | else if (i915.use_mmio_flip > 0) |
| 9608 | return true; |
Oscar Mateo | 14bf993 | 2014-07-24 17:04:34 +0100 | [diff] [blame] | 9609 | else if (i915.enable_execlists) |
| 9610 | return true; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 9611 | else |
| 9612 | return ring != obj->ring; |
| 9613 | } |
| 9614 | |
| 9615 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) |
| 9616 | { |
| 9617 | struct drm_device *dev = intel_crtc->base.dev; |
| 9618 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9619 | struct intel_framebuffer *intel_fb = |
| 9620 | to_intel_framebuffer(intel_crtc->base.primary->fb); |
| 9621 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 9622 | u32 dspcntr; |
| 9623 | u32 reg; |
| 9624 | |
| 9625 | intel_mark_page_flip_active(intel_crtc); |
| 9626 | |
| 9627 | reg = DSPCNTR(intel_crtc->plane); |
| 9628 | dspcntr = I915_READ(reg); |
| 9629 | |
| 9630 | if (INTEL_INFO(dev)->gen >= 4) { |
| 9631 | if (obj->tiling_mode != I915_TILING_NONE) |
| 9632 | dspcntr |= DISPPLANE_TILED; |
| 9633 | else |
| 9634 | dspcntr &= ~DISPPLANE_TILED; |
| 9635 | } |
| 9636 | I915_WRITE(reg, dspcntr); |
| 9637 | |
| 9638 | I915_WRITE(DSPSURF(intel_crtc->plane), |
| 9639 | intel_crtc->unpin_work->gtt_offset); |
| 9640 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
| 9641 | } |
| 9642 | |
| 9643 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) |
| 9644 | { |
| 9645 | struct intel_engine_cs *ring; |
| 9646 | int ret; |
| 9647 | |
| 9648 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 9649 | |
| 9650 | if (!obj->last_write_seqno) |
| 9651 | return 0; |
| 9652 | |
| 9653 | ring = obj->ring; |
| 9654 | |
| 9655 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
| 9656 | obj->last_write_seqno)) |
| 9657 | return 0; |
| 9658 | |
| 9659 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); |
| 9660 | if (ret) |
| 9661 | return ret; |
| 9662 | |
| 9663 | if (WARN_ON(!ring->irq_get(ring))) |
| 9664 | return 0; |
| 9665 | |
| 9666 | return 1; |
| 9667 | } |
| 9668 | |
| 9669 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) |
| 9670 | { |
| 9671 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 9672 | struct intel_crtc *intel_crtc; |
| 9673 | unsigned long irq_flags; |
| 9674 | u32 seqno; |
| 9675 | |
| 9676 | seqno = ring->get_seqno(ring, false); |
| 9677 | |
| 9678 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); |
| 9679 | for_each_intel_crtc(ring->dev, intel_crtc) { |
| 9680 | struct intel_mmio_flip *mmio_flip; |
| 9681 | |
| 9682 | mmio_flip = &intel_crtc->mmio_flip; |
| 9683 | if (mmio_flip->seqno == 0) |
| 9684 | continue; |
| 9685 | |
| 9686 | if (ring->id != mmio_flip->ring_id) |
| 9687 | continue; |
| 9688 | |
| 9689 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { |
| 9690 | intel_do_mmio_flip(intel_crtc); |
| 9691 | mmio_flip->seqno = 0; |
| 9692 | ring->irq_put(ring); |
| 9693 | } |
| 9694 | } |
| 9695 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); |
| 9696 | } |
| 9697 | |
| 9698 | static int intel_queue_mmio_flip(struct drm_device *dev, |
| 9699 | struct drm_crtc *crtc, |
| 9700 | struct drm_framebuffer *fb, |
| 9701 | struct drm_i915_gem_object *obj, |
| 9702 | struct intel_engine_cs *ring, |
| 9703 | uint32_t flags) |
| 9704 | { |
| 9705 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 9707 | unsigned long irq_flags; |
| 9708 | int ret; |
| 9709 | |
| 9710 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) |
| 9711 | return -EBUSY; |
| 9712 | |
| 9713 | ret = intel_postpone_flip(obj); |
| 9714 | if (ret < 0) |
| 9715 | return ret; |
| 9716 | if (ret == 0) { |
| 9717 | intel_do_mmio_flip(intel_crtc); |
| 9718 | return 0; |
| 9719 | } |
| 9720 | |
| 9721 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); |
| 9722 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; |
| 9723 | intel_crtc->mmio_flip.ring_id = obj->ring->id; |
| 9724 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); |
| 9725 | |
| 9726 | /* |
| 9727 | * Double check to catch cases where irq fired before |
| 9728 | * mmio flip data was ready |
| 9729 | */ |
| 9730 | intel_notify_mmio_flip(obj->ring); |
| 9731 | return 0; |
| 9732 | } |
| 9733 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9734 | static int intel_default_queue_flip(struct drm_device *dev, |
| 9735 | struct drm_crtc *crtc, |
| 9736 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9737 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9738 | struct intel_engine_cs *ring, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9739 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9740 | { |
| 9741 | return -ENODEV; |
| 9742 | } |
| 9743 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9744 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 9745 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 9746 | struct drm_pending_vblank_event *event, |
| 9747 | uint32_t page_flip_flags) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9748 | { |
| 9749 | struct drm_device *dev = crtc->dev; |
| 9750 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 9751 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 9752 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 9754 | enum pipe pipe = intel_crtc->pipe; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9755 | struct intel_unpin_work *work; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 9756 | struct intel_engine_cs *ring; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9757 | unsigned long flags; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 9758 | int ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9759 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 9760 | /* |
| 9761 | * drm_mode_page_flip_ioctl() should already catch this, but double |
| 9762 | * check to be safe. In the future we may enable pageflipping from |
| 9763 | * a disabled primary plane. |
| 9764 | */ |
| 9765 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) |
| 9766 | return -EBUSY; |
| 9767 | |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 9768 | /* Can't change pixel format via MI display flips. */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 9769 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 9770 | return -EINVAL; |
| 9771 | |
| 9772 | /* |
| 9773 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
| 9774 | * Note that pitch changes could also affect these register. |
| 9775 | */ |
| 9776 | if (INTEL_INFO(dev)->gen > 3 && |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 9777 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
| 9778 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 9779 | return -EINVAL; |
| 9780 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 9781 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 9782 | goto out_hang; |
| 9783 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 9784 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9785 | if (work == NULL) |
| 9786 | return -ENOMEM; |
| 9787 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9788 | work->event = event; |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9789 | work->crtc = crtc; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 9790 | work->old_fb_obj = intel_fb_obj(old_fb); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9791 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 9792 | |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 9793 | ret = drm_crtc_vblank_get(crtc); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 9794 | if (ret) |
| 9795 | goto free_work; |
| 9796 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9797 | /* We borrow the event spin lock for protecting unpin_work */ |
| 9798 | spin_lock_irqsave(&dev->event_lock, flags); |
| 9799 | if (intel_crtc->unpin_work) { |
| 9800 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9801 | kfree(work); |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 9802 | drm_crtc_vblank_put(crtc); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 9803 | |
| 9804 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9805 | return -EBUSY; |
| 9806 | } |
| 9807 | intel_crtc->unpin_work = work; |
| 9808 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9809 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9810 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
| 9811 | flush_workqueue(dev_priv->wq); |
| 9812 | |
Chris Wilson | 7915810 | 2012-05-23 11:13:58 +0100 | [diff] [blame] | 9813 | ret = i915_mutex_lock_interruptible(dev); |
| 9814 | if (ret) |
| 9815 | goto cleanup; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9816 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 9817 | /* Reference the objects for the scheduled work. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 9818 | drm_gem_object_reference(&work->old_fb_obj->base); |
| 9819 | drm_gem_object_reference(&obj->base); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9820 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 9821 | crtc->primary->fb = fb; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 9822 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 9823 | work->pending_flip_obj = obj; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 9824 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 9825 | work->enable_stall_check = true; |
| 9826 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9827 | atomic_inc(&intel_crtc->unpin_work_count); |
Ville Syrjälä | 10d8373 | 2013-01-29 18:13:34 +0200 | [diff] [blame] | 9828 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 9829 | |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9830 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 9831 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 9832 | |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9833 | if (IS_VALLEYVIEW(dev)) { |
| 9834 | ring = &dev_priv->ring[BCS]; |
Chris Wilson | 8e09bf8 | 2014-07-08 10:40:30 +0100 | [diff] [blame] | 9835 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
| 9836 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
| 9837 | ring = NULL; |
Chris Wilson | 2a92d5b | 2014-07-08 10:40:29 +0100 | [diff] [blame] | 9838 | } else if (IS_IVYBRIDGE(dev)) { |
| 9839 | ring = &dev_priv->ring[BCS]; |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9840 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 9841 | ring = obj->ring; |
| 9842 | if (ring == NULL || ring->id != RCS) |
| 9843 | ring = &dev_priv->ring[BCS]; |
| 9844 | } else { |
| 9845 | ring = &dev_priv->ring[RCS]; |
| 9846 | } |
| 9847 | |
| 9848 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9849 | if (ret) |
| 9850 | goto cleanup_pending; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9851 | |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9852 | work->gtt_offset = |
| 9853 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; |
| 9854 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 9855 | if (use_mmio_flip(ring, obj)) |
| 9856 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
| 9857 | page_flip_flags); |
| 9858 | else |
| 9859 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
| 9860 | page_flip_flags); |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9861 | if (ret) |
| 9862 | goto cleanup_unpin; |
| 9863 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 9864 | i915_gem_track_fb(work->old_fb_obj, obj, |
| 9865 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
| 9866 | |
Chris Wilson | 7782de3 | 2011-07-08 12:22:41 +0100 | [diff] [blame] | 9867 | intel_disable_fbc(dev); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 9868 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9869 | mutex_unlock(&dev->struct_mutex); |
| 9870 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 9871 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 9872 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9873 | return 0; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 9874 | |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 9875 | cleanup_unpin: |
| 9876 | intel_unpin_fb_obj(obj); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 9877 | cleanup_pending: |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 9878 | atomic_dec(&intel_crtc->unpin_work_count); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 9879 | crtc->primary->fb = old_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 9880 | drm_gem_object_unreference(&work->old_fb_obj->base); |
| 9881 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 9882 | mutex_unlock(&dev->struct_mutex); |
| 9883 | |
Chris Wilson | 7915810 | 2012-05-23 11:13:58 +0100 | [diff] [blame] | 9884 | cleanup: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 9885 | spin_lock_irqsave(&dev->event_lock, flags); |
| 9886 | intel_crtc->unpin_work = NULL; |
| 9887 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 9888 | |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 9889 | drm_crtc_vblank_put(crtc); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 9890 | free_work: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 9891 | kfree(work); |
| 9892 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 9893 | if (ret == -EIO) { |
| 9894 | out_hang: |
| 9895 | intel_crtc_wait_for_pending_flips(crtc); |
| 9896 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); |
| 9897 | if (ret == 0 && event) |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 9898 | drm_send_vblank_event(dev, pipe, event); |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 9899 | } |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 9900 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 9901 | } |
| 9902 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 9903 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 9904 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
| 9905 | .load_lut = intel_crtc_load_lut, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 9906 | }; |
| 9907 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9908 | /** |
| 9909 | * intel_modeset_update_staged_output_state |
| 9910 | * |
| 9911 | * Updates the staged output configuration state, e.g. after we've read out the |
| 9912 | * current hw state. |
| 9913 | */ |
| 9914 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
| 9915 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9916 | struct intel_crtc *crtc; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9917 | struct intel_encoder *encoder; |
| 9918 | struct intel_connector *connector; |
| 9919 | |
| 9920 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 9921 | base.head) { |
| 9922 | connector->new_encoder = |
| 9923 | to_intel_encoder(connector->base.encoder); |
| 9924 | } |
| 9925 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 9926 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9927 | encoder->new_crtc = |
| 9928 | to_intel_crtc(encoder->base.crtc); |
| 9929 | } |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9930 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 9931 | for_each_intel_crtc(dev, crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9932 | crtc->new_enabled = crtc->base.enabled; |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 9933 | |
| 9934 | if (crtc->new_enabled) |
| 9935 | crtc->new_config = &crtc->config; |
| 9936 | else |
| 9937 | crtc->new_config = NULL; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9938 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9939 | } |
| 9940 | |
| 9941 | /** |
| 9942 | * intel_modeset_commit_output_state |
| 9943 | * |
| 9944 | * This function copies the stage display pipe configuration to the real one. |
| 9945 | */ |
| 9946 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
| 9947 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9948 | struct intel_crtc *crtc; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9949 | struct intel_encoder *encoder; |
| 9950 | struct intel_connector *connector; |
| 9951 | |
| 9952 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 9953 | base.head) { |
| 9954 | connector->base.encoder = &connector->new_encoder->base; |
| 9955 | } |
| 9956 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 9957 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9958 | encoder->base.crtc = &encoder->new_crtc->base; |
| 9959 | } |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9960 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 9961 | for_each_intel_crtc(dev, crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9962 | crtc->base.enabled = crtc->new_enabled; |
| 9963 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9964 | } |
| 9965 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9966 | static void |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 9967 | connected_sink_compute_bpp(struct intel_connector *connector, |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9968 | struct intel_crtc_config *pipe_config) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9969 | { |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9970 | int bpp = pipe_config->pipe_bpp; |
| 9971 | |
| 9972 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
| 9973 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 9974 | connector->base.name); |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9975 | |
| 9976 | /* Don't use an invalid EDID bpc value */ |
| 9977 | if (connector->base.display_info.bpc && |
| 9978 | connector->base.display_info.bpc * 3 < bpp) { |
| 9979 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
| 9980 | bpp, connector->base.display_info.bpc*3); |
| 9981 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
| 9982 | } |
| 9983 | |
| 9984 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
| 9985 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
| 9986 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
| 9987 | bpp); |
| 9988 | pipe_config->pipe_bpp = 24; |
| 9989 | } |
| 9990 | } |
| 9991 | |
| 9992 | static int |
| 9993 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
| 9994 | struct drm_framebuffer *fb, |
| 9995 | struct intel_crtc_config *pipe_config) |
| 9996 | { |
| 9997 | struct drm_device *dev = crtc->base.dev; |
| 9998 | struct intel_connector *connector; |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9999 | int bpp; |
| 10000 | |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 10001 | switch (fb->pixel_format) { |
| 10002 | case DRM_FORMAT_C8: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10003 | bpp = 8*3; /* since we go through a colormap */ |
| 10004 | break; |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 10005 | case DRM_FORMAT_XRGB1555: |
| 10006 | case DRM_FORMAT_ARGB1555: |
| 10007 | /* checked in intel_framebuffer_init already */ |
| 10008 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
| 10009 | return -EINVAL; |
| 10010 | case DRM_FORMAT_RGB565: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10011 | bpp = 6*3; /* min is 18bpp */ |
| 10012 | break; |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 10013 | case DRM_FORMAT_XBGR8888: |
| 10014 | case DRM_FORMAT_ABGR8888: |
| 10015 | /* checked in intel_framebuffer_init already */ |
| 10016 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
| 10017 | return -EINVAL; |
| 10018 | case DRM_FORMAT_XRGB8888: |
| 10019 | case DRM_FORMAT_ARGB8888: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10020 | bpp = 8*3; |
| 10021 | break; |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 10022 | case DRM_FORMAT_XRGB2101010: |
| 10023 | case DRM_FORMAT_ARGB2101010: |
| 10024 | case DRM_FORMAT_XBGR2101010: |
| 10025 | case DRM_FORMAT_ABGR2101010: |
| 10026 | /* checked in intel_framebuffer_init already */ |
| 10027 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 10028 | return -EINVAL; |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10029 | bpp = 10*3; |
| 10030 | break; |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 10031 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10032 | default: |
| 10033 | DRM_DEBUG_KMS("unsupported depth\n"); |
| 10034 | return -EINVAL; |
| 10035 | } |
| 10036 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10037 | pipe_config->pipe_bpp = bpp; |
| 10038 | |
| 10039 | /* Clamp display bpp to EDID value */ |
| 10040 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 10041 | base.head) { |
Daniel Vetter | 1b829e0 | 2013-06-02 13:26:24 +0200 | [diff] [blame] | 10042 | if (!connector->new_encoder || |
| 10043 | connector->new_encoder->new_crtc != crtc) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10044 | continue; |
| 10045 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 10046 | connected_sink_compute_bpp(connector, pipe_config); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10047 | } |
| 10048 | |
| 10049 | return bpp; |
| 10050 | } |
| 10051 | |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 10052 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
| 10053 | { |
| 10054 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
| 10055 | "type: 0x%x flags: 0x%x\n", |
Damien Lespiau | 1342830 | 2013-09-25 16:45:36 +0100 | [diff] [blame] | 10056 | mode->crtc_clock, |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 10057 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
| 10058 | mode->crtc_hsync_end, mode->crtc_htotal, |
| 10059 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
| 10060 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
| 10061 | } |
| 10062 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10063 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
| 10064 | struct intel_crtc_config *pipe_config, |
| 10065 | const char *context) |
| 10066 | { |
| 10067 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
| 10068 | context, pipe_name(crtc->pipe)); |
| 10069 | |
| 10070 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
| 10071 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
| 10072 | pipe_config->pipe_bpp, pipe_config->dither); |
| 10073 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 10074 | pipe_config->has_pch_encoder, |
| 10075 | pipe_config->fdi_lanes, |
| 10076 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
| 10077 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
| 10078 | pipe_config->fdi_m_n.tu); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 10079 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 10080 | pipe_config->has_dp_encoder, |
| 10081 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
| 10082 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
| 10083 | pipe_config->dp_m_n.tu); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 10084 | |
| 10085 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
| 10086 | pipe_config->has_dp_encoder, |
| 10087 | pipe_config->dp_m2_n2.gmch_m, |
| 10088 | pipe_config->dp_m2_n2.gmch_n, |
| 10089 | pipe_config->dp_m2_n2.link_m, |
| 10090 | pipe_config->dp_m2_n2.link_n, |
| 10091 | pipe_config->dp_m2_n2.tu); |
| 10092 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10093 | DRM_DEBUG_KMS("requested mode:\n"); |
| 10094 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
| 10095 | DRM_DEBUG_KMS("adjusted mode:\n"); |
| 10096 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 10097 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
Ville Syrjälä | d71b8d4 | 2013-09-06 23:29:08 +0300 | [diff] [blame] | 10098 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 10099 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
| 10100 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10101 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
| 10102 | pipe_config->gmch_pfit.control, |
| 10103 | pipe_config->gmch_pfit.pgm_ratios, |
| 10104 | pipe_config->gmch_pfit.lvds_border_bits); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 10105 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10106 | pipe_config->pch_pfit.pos, |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 10107 | pipe_config->pch_pfit.size, |
| 10108 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 10109 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 10110 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10111 | } |
| 10112 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10113 | static bool encoders_cloneable(const struct intel_encoder *a, |
| 10114 | const struct intel_encoder *b) |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 10115 | { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10116 | /* masks could be asymmetric, so check both ways */ |
| 10117 | return a == b || (a->cloneable & (1 << b->type) && |
| 10118 | b->cloneable & (1 << a->type)); |
| 10119 | } |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 10120 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10121 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, |
| 10122 | struct intel_encoder *encoder) |
| 10123 | { |
| 10124 | struct drm_device *dev = crtc->base.dev; |
| 10125 | struct intel_encoder *source_encoder; |
| 10126 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10127 | for_each_intel_encoder(dev, source_encoder) { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10128 | if (source_encoder->new_crtc != crtc) |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 10129 | continue; |
| 10130 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10131 | if (!encoders_cloneable(encoder, source_encoder)) |
| 10132 | return false; |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 10133 | } |
| 10134 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10135 | return true; |
| 10136 | } |
| 10137 | |
| 10138 | static bool check_encoder_cloning(struct intel_crtc *crtc) |
| 10139 | { |
| 10140 | struct drm_device *dev = crtc->base.dev; |
| 10141 | struct intel_encoder *encoder; |
| 10142 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10143 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10144 | if (encoder->new_crtc != crtc) |
| 10145 | continue; |
| 10146 | |
| 10147 | if (!check_single_encoder_cloning(crtc, encoder)) |
| 10148 | return false; |
| 10149 | } |
| 10150 | |
| 10151 | return true; |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 10152 | } |
| 10153 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10154 | static struct intel_crtc_config * |
| 10155 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10156 | struct drm_framebuffer *fb, |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10157 | struct drm_display_mode *mode) |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10158 | { |
| 10159 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10160 | struct intel_encoder *encoder; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10161 | struct intel_crtc_config *pipe_config; |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 10162 | int plane_bpp, ret = -EINVAL; |
| 10163 | bool retry = true; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10164 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10165 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 10166 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
| 10167 | return ERR_PTR(-EINVAL); |
| 10168 | } |
| 10169 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10170 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
| 10171 | if (!pipe_config) |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10172 | return ERR_PTR(-ENOMEM); |
| 10173 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10174 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
| 10175 | drm_mode_copy(&pipe_config->requested_mode, mode); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 10176 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 10177 | pipe_config->cpu_transcoder = |
| 10178 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 10179 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10180 | |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 10181 | /* |
| 10182 | * Sanitize sync polarity flags based on requested ones. If neither |
| 10183 | * positive or negative polarity is requested, treat this as meaning |
| 10184 | * negative polarity. |
| 10185 | */ |
| 10186 | if (!(pipe_config->adjusted_mode.flags & |
| 10187 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
| 10188 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
| 10189 | |
| 10190 | if (!(pipe_config->adjusted_mode.flags & |
| 10191 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
| 10192 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
| 10193 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 10194 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
| 10195 | * plane pixel format and any sink constraints into account. Returns the |
| 10196 | * source plane bpp so that dithering can be selected on mismatches |
| 10197 | * after encoders and crtc also have had their say. */ |
| 10198 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
| 10199 | fb, pipe_config); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10200 | if (plane_bpp < 0) |
| 10201 | goto fail; |
| 10202 | |
Ville Syrjälä | e41a56b | 2013-10-01 22:52:14 +0300 | [diff] [blame] | 10203 | /* |
| 10204 | * Determine the real pipe dimensions. Note that stereo modes can |
| 10205 | * increase the actual pipe size due to the frame doubling and |
| 10206 | * insertion of additional space for blanks between the frame. This |
| 10207 | * is stored in the crtc timings. We use the requested mode to do this |
| 10208 | * computation to clearly distinguish it from the adjusted mode, which |
| 10209 | * can be changed by the connectors in the below retry loop. |
| 10210 | */ |
| 10211 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
| 10212 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
| 10213 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
| 10214 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 10215 | encoder_retry: |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 10216 | /* Ensure the port clock defaults are reset when retrying. */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 10217 | pipe_config->port_clock = 0; |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 10218 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 10219 | |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 10220 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
Damien Lespiau | 6ce70f5 | 2013-09-25 16:45:38 +0100 | [diff] [blame] | 10221 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 10222 | |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10223 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
| 10224 | * adjust it according to limitations or connector properties, and also |
| 10225 | * a chance to reject the mode entirely. |
| 10226 | */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10227 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10228 | |
| 10229 | if (&encoder->new_crtc->base != crtc) |
| 10230 | continue; |
Daniel Vetter | 7ae8923 | 2013-03-27 00:44:52 +0100 | [diff] [blame] | 10231 | |
Daniel Vetter | efea6e8 | 2013-07-21 21:36:59 +0200 | [diff] [blame] | 10232 | if (!(encoder->compute_config(encoder, pipe_config))) { |
| 10233 | DRM_DEBUG_KMS("Encoder config failure\n"); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10234 | goto fail; |
| 10235 | } |
| 10236 | } |
| 10237 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 10238 | /* Set default port clock if not overwritten by the encoder. Needs to be |
| 10239 | * done afterwards in case the encoder adjusts the mode. */ |
| 10240 | if (!pipe_config->port_clock) |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 10241 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
| 10242 | * pipe_config->pixel_multiplier; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 10243 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 10244 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 10245 | if (ret < 0) { |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10246 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
| 10247 | goto fail; |
| 10248 | } |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 10249 | |
| 10250 | if (ret == RETRY) { |
| 10251 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
| 10252 | ret = -EINVAL; |
| 10253 | goto fail; |
| 10254 | } |
| 10255 | |
| 10256 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
| 10257 | retry = false; |
| 10258 | goto encoder_retry; |
| 10259 | } |
| 10260 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10261 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
| 10262 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
| 10263 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
| 10264 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10265 | return pipe_config; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10266 | fail: |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10267 | kfree(pipe_config); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 10268 | return ERR_PTR(ret); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10269 | } |
| 10270 | |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10271 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
| 10272 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
| 10273 | static void |
| 10274 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
| 10275 | unsigned *prepare_pipes, unsigned *disable_pipes) |
| 10276 | { |
| 10277 | struct intel_crtc *intel_crtc; |
| 10278 | struct drm_device *dev = crtc->dev; |
| 10279 | struct intel_encoder *encoder; |
| 10280 | struct intel_connector *connector; |
| 10281 | struct drm_crtc *tmp_crtc; |
| 10282 | |
| 10283 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
| 10284 | |
| 10285 | /* Check which crtcs have changed outputs connected to them, these need |
| 10286 | * to be part of the prepare_pipes mask. We don't (yet) support global |
| 10287 | * modeset across multiple crtcs, so modeset_pipes will only have one |
| 10288 | * bit set at most. */ |
| 10289 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 10290 | base.head) { |
| 10291 | if (connector->base.encoder == &connector->new_encoder->base) |
| 10292 | continue; |
| 10293 | |
| 10294 | if (connector->base.encoder) { |
| 10295 | tmp_crtc = connector->base.encoder->crtc; |
| 10296 | |
| 10297 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
| 10298 | } |
| 10299 | |
| 10300 | if (connector->new_encoder) |
| 10301 | *prepare_pipes |= |
| 10302 | 1 << connector->new_encoder->new_crtc->pipe; |
| 10303 | } |
| 10304 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10305 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10306 | if (encoder->base.crtc == &encoder->new_crtc->base) |
| 10307 | continue; |
| 10308 | |
| 10309 | if (encoder->base.crtc) { |
| 10310 | tmp_crtc = encoder->base.crtc; |
| 10311 | |
| 10312 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
| 10313 | } |
| 10314 | |
| 10315 | if (encoder->new_crtc) |
| 10316 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
| 10317 | } |
| 10318 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10319 | /* Check for pipes that will be enabled/disabled ... */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 10320 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10321 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10322 | continue; |
| 10323 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10324 | if (!intel_crtc->new_enabled) |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10325 | *disable_pipes |= 1 << intel_crtc->pipe; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10326 | else |
| 10327 | *prepare_pipes |= 1 << intel_crtc->pipe; |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10328 | } |
| 10329 | |
| 10330 | |
| 10331 | /* set_mode is also used to update properties on life display pipes. */ |
| 10332 | intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10333 | if (intel_crtc->new_enabled) |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10334 | *prepare_pipes |= 1 << intel_crtc->pipe; |
| 10335 | |
Daniel Vetter | b6c5164 | 2013-04-12 18:48:43 +0200 | [diff] [blame] | 10336 | /* |
| 10337 | * For simplicity do a full modeset on any pipe where the output routing |
| 10338 | * changed. We could be more clever, but that would require us to be |
| 10339 | * more careful with calling the relevant encoder->mode_set functions. |
| 10340 | */ |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10341 | if (*prepare_pipes) |
| 10342 | *modeset_pipes = *prepare_pipes; |
| 10343 | |
| 10344 | /* ... and mask these out. */ |
| 10345 | *modeset_pipes &= ~(*disable_pipes); |
| 10346 | *prepare_pipes &= ~(*disable_pipes); |
Daniel Vetter | b6c5164 | 2013-04-12 18:48:43 +0200 | [diff] [blame] | 10347 | |
| 10348 | /* |
| 10349 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
| 10350 | * obies this rule, but the modeset restore mode of |
| 10351 | * intel_modeset_setup_hw_state does not. |
| 10352 | */ |
| 10353 | *modeset_pipes &= 1 << intel_crtc->pipe; |
| 10354 | *prepare_pipes &= 1 << intel_crtc->pipe; |
Daniel Vetter | e3641d3 | 2013-04-11 19:49:07 +0200 | [diff] [blame] | 10355 | |
| 10356 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
| 10357 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10358 | } |
| 10359 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10360 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
| 10361 | { |
| 10362 | struct drm_encoder *encoder; |
| 10363 | struct drm_device *dev = crtc->dev; |
| 10364 | |
| 10365 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
| 10366 | if (encoder->crtc == crtc) |
| 10367 | return true; |
| 10368 | |
| 10369 | return false; |
| 10370 | } |
| 10371 | |
| 10372 | static void |
| 10373 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
| 10374 | { |
| 10375 | struct intel_encoder *intel_encoder; |
| 10376 | struct intel_crtc *intel_crtc; |
| 10377 | struct drm_connector *connector; |
| 10378 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10379 | for_each_intel_encoder(dev, intel_encoder) { |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10380 | if (!intel_encoder->base.crtc) |
| 10381 | continue; |
| 10382 | |
| 10383 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
| 10384 | |
| 10385 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
| 10386 | intel_encoder->connectors_active = false; |
| 10387 | } |
| 10388 | |
| 10389 | intel_modeset_commit_output_state(dev); |
| 10390 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10391 | /* Double check state. */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 10392 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10393 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 10394 | WARN_ON(intel_crtc->new_config && |
| 10395 | intel_crtc->new_config != &intel_crtc->config); |
| 10396 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10397 | } |
| 10398 | |
| 10399 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 10400 | if (!connector->encoder || !connector->encoder->crtc) |
| 10401 | continue; |
| 10402 | |
| 10403 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
| 10404 | |
| 10405 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
Daniel Vetter | 68d3472 | 2012-09-06 22:08:35 +0200 | [diff] [blame] | 10406 | struct drm_property *dpms_property = |
| 10407 | dev->mode_config.dpms_property; |
| 10408 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10409 | connector->dpms = DRM_MODE_DPMS_ON; |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 10410 | drm_object_property_set_value(&connector->base, |
Daniel Vetter | 68d3472 | 2012-09-06 22:08:35 +0200 | [diff] [blame] | 10411 | dpms_property, |
| 10412 | DRM_MODE_DPMS_ON); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10413 | |
| 10414 | intel_encoder = to_intel_encoder(connector->encoder); |
| 10415 | intel_encoder->connectors_active = true; |
| 10416 | } |
| 10417 | } |
| 10418 | |
| 10419 | } |
| 10420 | |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 10421 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10422 | { |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 10423 | int diff; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10424 | |
| 10425 | if (clock1 == clock2) |
| 10426 | return true; |
| 10427 | |
| 10428 | if (!clock1 || !clock2) |
| 10429 | return false; |
| 10430 | |
| 10431 | diff = abs(clock1 - clock2); |
| 10432 | |
| 10433 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
| 10434 | return true; |
| 10435 | |
| 10436 | return false; |
| 10437 | } |
| 10438 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10439 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
| 10440 | list_for_each_entry((intel_crtc), \ |
| 10441 | &(dev)->mode_config.crtc_list, \ |
| 10442 | base.head) \ |
Daniel Vetter | 0973f18 | 2013-04-19 11:25:33 +0200 | [diff] [blame] | 10443 | if (mask & (1 <<(intel_crtc)->pipe)) |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10444 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10445 | static bool |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 10446 | intel_pipe_config_compare(struct drm_device *dev, |
| 10447 | struct intel_crtc_config *current_config, |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10448 | struct intel_crtc_config *pipe_config) |
| 10449 | { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 10450 | #define PIPE_CONF_CHECK_X(name) \ |
| 10451 | if (current_config->name != pipe_config->name) { \ |
| 10452 | DRM_ERROR("mismatch in " #name " " \ |
| 10453 | "(expected 0x%08x, found 0x%08x)\n", \ |
| 10454 | current_config->name, \ |
| 10455 | pipe_config->name); \ |
| 10456 | return false; \ |
| 10457 | } |
| 10458 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 10459 | #define PIPE_CONF_CHECK_I(name) \ |
| 10460 | if (current_config->name != pipe_config->name) { \ |
| 10461 | DRM_ERROR("mismatch in " #name " " \ |
| 10462 | "(expected %i, found %i)\n", \ |
| 10463 | current_config->name, \ |
| 10464 | pipe_config->name); \ |
| 10465 | return false; \ |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 10466 | } |
| 10467 | |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 10468 | /* This is required for BDW+ where there is only one set of registers for |
| 10469 | * switching between high and low RR. |
| 10470 | * This macro can be used whenever a comparison has to be made between one |
| 10471 | * hw state and multiple sw state variables. |
| 10472 | */ |
| 10473 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ |
| 10474 | if ((current_config->name != pipe_config->name) && \ |
| 10475 | (current_config->alt_name != pipe_config->name)) { \ |
| 10476 | DRM_ERROR("mismatch in " #name " " \ |
| 10477 | "(expected %i or %i, found %i)\n", \ |
| 10478 | current_config->name, \ |
| 10479 | current_config->alt_name, \ |
| 10480 | pipe_config->name); \ |
| 10481 | return false; \ |
| 10482 | } |
| 10483 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10484 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
| 10485 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
Jesse Barnes | 6f02488 | 2013-07-01 10:19:09 -0700 | [diff] [blame] | 10486 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10487 | "(expected %i, found %i)\n", \ |
| 10488 | current_config->name & (mask), \ |
| 10489 | pipe_config->name & (mask)); \ |
| 10490 | return false; \ |
| 10491 | } |
| 10492 | |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 10493 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
| 10494 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
| 10495 | DRM_ERROR("mismatch in " #name " " \ |
| 10496 | "(expected %i, found %i)\n", \ |
| 10497 | current_config->name, \ |
| 10498 | pipe_config->name); \ |
| 10499 | return false; \ |
| 10500 | } |
| 10501 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 10502 | #define PIPE_CONF_QUIRK(quirk) \ |
| 10503 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
| 10504 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 10505 | PIPE_CONF_CHECK_I(cpu_transcoder); |
| 10506 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 10507 | PIPE_CONF_CHECK_I(has_pch_encoder); |
| 10508 | PIPE_CONF_CHECK_I(fdi_lanes); |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 10509 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
| 10510 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
| 10511 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
| 10512 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
| 10513 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 10514 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 10515 | PIPE_CONF_CHECK_I(has_dp_encoder); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 10516 | |
| 10517 | if (INTEL_INFO(dev)->gen < 8) { |
| 10518 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
| 10519 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
| 10520 | PIPE_CONF_CHECK_I(dp_m_n.link_m); |
| 10521 | PIPE_CONF_CHECK_I(dp_m_n.link_n); |
| 10522 | PIPE_CONF_CHECK_I(dp_m_n.tu); |
| 10523 | |
| 10524 | if (current_config->has_drrs) { |
| 10525 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); |
| 10526 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); |
| 10527 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); |
| 10528 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); |
| 10529 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); |
| 10530 | } |
| 10531 | } else { |
| 10532 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); |
| 10533 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); |
| 10534 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); |
| 10535 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); |
| 10536 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); |
| 10537 | } |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 10538 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10539 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
| 10540 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
| 10541 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
| 10542 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
| 10543 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
| 10544 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
| 10545 | |
| 10546 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
| 10547 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
| 10548 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
| 10549 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
| 10550 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
| 10551 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
| 10552 | |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 10553 | PIPE_CONF_CHECK_I(pixel_multiplier); |
Daniel Vetter | 6897b4b5 | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 10554 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 10555 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
| 10556 | IS_VALLEYVIEW(dev)) |
| 10557 | PIPE_CONF_CHECK_I(limited_color_range); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 10558 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 10559 | PIPE_CONF_CHECK_I(has_audio); |
| 10560 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10561 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 10562 | DRM_MODE_FLAG_INTERLACE); |
| 10563 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 10564 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
| 10565 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 10566 | DRM_MODE_FLAG_PHSYNC); |
| 10567 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 10568 | DRM_MODE_FLAG_NHSYNC); |
| 10569 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 10570 | DRM_MODE_FLAG_PVSYNC); |
| 10571 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 10572 | DRM_MODE_FLAG_NVSYNC); |
| 10573 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 10574 | |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 10575 | PIPE_CONF_CHECK_I(pipe_src_w); |
| 10576 | PIPE_CONF_CHECK_I(pipe_src_h); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10577 | |
Daniel Vetter | 9953599 | 2014-04-13 12:00:33 +0200 | [diff] [blame] | 10578 | /* |
| 10579 | * FIXME: BIOS likes to set up a cloned config with lvds+external |
| 10580 | * screen. Since we don't yet re-compute the pipe config when moving |
| 10581 | * just the lvds port away to another pipe the sw tracking won't match. |
| 10582 | * |
| 10583 | * Proper atomic modesets with recomputed global state will fix this. |
| 10584 | * Until then just don't check gmch state for inherited modes. |
| 10585 | */ |
| 10586 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { |
| 10587 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
| 10588 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
| 10589 | if (INTEL_INFO(dev)->gen < 4) |
| 10590 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
| 10591 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
| 10592 | } |
| 10593 | |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 10594 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
| 10595 | if (current_config->pch_pfit.enabled) { |
| 10596 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
| 10597 | PIPE_CONF_CHECK_I(pch_pfit.size); |
| 10598 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 10599 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 10600 | /* BDW+ don't expose a synchronous way to read the state */ |
| 10601 | if (IS_HASWELL(dev)) |
| 10602 | PIPE_CONF_CHECK_I(ips_enabled); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 10603 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 10604 | PIPE_CONF_CHECK_I(double_wide); |
| 10605 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10606 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
| 10607 | |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 10608 | PIPE_CONF_CHECK_I(shared_dpll); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 10609 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 10610 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 10611 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
| 10612 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 10613 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 10614 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 10615 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
| 10616 | PIPE_CONF_CHECK_I(pipe_bpp); |
| 10617 | |
Jesse Barnes | a9a7e98 | 2014-01-20 14:18:04 -0800 | [diff] [blame] | 10618 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
| 10619 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 10620 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 10621 | #undef PIPE_CONF_CHECK_X |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 10622 | #undef PIPE_CONF_CHECK_I |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 10623 | #undef PIPE_CONF_CHECK_I_ALT |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10624 | #undef PIPE_CONF_CHECK_FLAGS |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 10625 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 10626 | #undef PIPE_CONF_QUIRK |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 10627 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10628 | return true; |
| 10629 | } |
| 10630 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10631 | static void |
| 10632 | check_connector_state(struct drm_device *dev) |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10633 | { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10634 | struct intel_connector *connector; |
| 10635 | |
| 10636 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 10637 | base.head) { |
| 10638 | /* This also checks the encoder/connector hw state with the |
| 10639 | * ->get_hw_state callbacks. */ |
| 10640 | intel_connector_check_state(connector); |
| 10641 | |
| 10642 | WARN(&connector->new_encoder->base != connector->base.encoder, |
| 10643 | "connector's staged encoder doesn't match current encoder\n"); |
| 10644 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10645 | } |
| 10646 | |
| 10647 | static void |
| 10648 | check_encoder_state(struct drm_device *dev) |
| 10649 | { |
| 10650 | struct intel_encoder *encoder; |
| 10651 | struct intel_connector *connector; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10652 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10653 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10654 | bool enabled = false; |
| 10655 | bool active = false; |
| 10656 | enum pipe pipe, tracked_pipe; |
| 10657 | |
| 10658 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
| 10659 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 10660 | encoder->base.name); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10661 | |
| 10662 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
| 10663 | "encoder's stage crtc doesn't match current crtc\n"); |
| 10664 | WARN(encoder->connectors_active && !encoder->base.crtc, |
| 10665 | "encoder's active_connectors set, but no crtc\n"); |
| 10666 | |
| 10667 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 10668 | base.head) { |
| 10669 | if (connector->base.encoder != &encoder->base) |
| 10670 | continue; |
| 10671 | enabled = true; |
| 10672 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
| 10673 | active = true; |
| 10674 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 10675 | /* |
| 10676 | * for MST connectors if we unplug the connector is gone |
| 10677 | * away but the encoder is still connected to a crtc |
| 10678 | * until a modeset happens in response to the hotplug. |
| 10679 | */ |
| 10680 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) |
| 10681 | continue; |
| 10682 | |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10683 | WARN(!!encoder->base.crtc != enabled, |
| 10684 | "encoder's enabled state mismatch " |
| 10685 | "(expected %i, found %i)\n", |
| 10686 | !!encoder->base.crtc, enabled); |
| 10687 | WARN(active && !encoder->base.crtc, |
| 10688 | "active encoder with no crtc\n"); |
| 10689 | |
| 10690 | WARN(encoder->connectors_active != active, |
| 10691 | "encoder's computed active state doesn't match tracked active state " |
| 10692 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
| 10693 | |
| 10694 | active = encoder->get_hw_state(encoder, &pipe); |
| 10695 | WARN(active != encoder->connectors_active, |
| 10696 | "encoder's hw state doesn't match sw tracking " |
| 10697 | "(expected %i, found %i)\n", |
| 10698 | encoder->connectors_active, active); |
| 10699 | |
| 10700 | if (!encoder->base.crtc) |
| 10701 | continue; |
| 10702 | |
| 10703 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
| 10704 | WARN(active && pipe != tracked_pipe, |
| 10705 | "active encoder's pipe doesn't match" |
| 10706 | "(expected %i, found %i)\n", |
| 10707 | tracked_pipe, pipe); |
| 10708 | |
| 10709 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10710 | } |
| 10711 | |
| 10712 | static void |
| 10713 | check_crtc_state(struct drm_device *dev) |
| 10714 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 10715 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10716 | struct intel_crtc *crtc; |
| 10717 | struct intel_encoder *encoder; |
| 10718 | struct intel_crtc_config pipe_config; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10719 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 10720 | for_each_intel_crtc(dev, crtc) { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10721 | bool enabled = false; |
| 10722 | bool active = false; |
| 10723 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 10724 | memset(&pipe_config, 0, sizeof(pipe_config)); |
| 10725 | |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10726 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
| 10727 | crtc->base.base.id); |
| 10728 | |
| 10729 | WARN(crtc->active && !crtc->base.enabled, |
| 10730 | "active crtc, but not enabled in sw tracking\n"); |
| 10731 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10732 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10733 | if (encoder->base.crtc != &crtc->base) |
| 10734 | continue; |
| 10735 | enabled = true; |
| 10736 | if (encoder->connectors_active) |
| 10737 | active = true; |
| 10738 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 10739 | |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10740 | WARN(active != crtc->active, |
| 10741 | "crtc's computed active state doesn't match tracked active state " |
| 10742 | "(expected %i, found %i)\n", active, crtc->active); |
| 10743 | WARN(enabled != crtc->base.enabled, |
| 10744 | "crtc's computed enabled state doesn't match tracked enabled state " |
| 10745 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
| 10746 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10747 | active = dev_priv->display.get_pipe_config(crtc, |
| 10748 | &pipe_config); |
Daniel Vetter | d62cf62 | 2013-05-29 10:41:29 +0200 | [diff] [blame] | 10749 | |
| 10750 | /* hw state is inconsistent with the pipe A quirk */ |
| 10751 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
| 10752 | active = crtc->active; |
| 10753 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 10754 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 3eaba51 | 2013-08-05 17:57:48 +0300 | [diff] [blame] | 10755 | enum pipe pipe; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 10756 | if (encoder->base.crtc != &crtc->base) |
| 10757 | continue; |
Daniel Vetter | 1d37b68 | 2013-11-18 09:00:59 +0100 | [diff] [blame] | 10758 | if (encoder->get_hw_state(encoder, &pipe)) |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 10759 | encoder->get_config(encoder, &pipe_config); |
| 10760 | } |
| 10761 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10762 | WARN(crtc->active != active, |
| 10763 | "crtc active state doesn't match with hw state " |
| 10764 | "(expected %i, found %i)\n", crtc->active, active); |
| 10765 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10766 | if (active && |
| 10767 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
| 10768 | WARN(1, "pipe state doesn't match!\n"); |
| 10769 | intel_dump_pipe_config(crtc, &pipe_config, |
| 10770 | "[hw state]"); |
| 10771 | intel_dump_pipe_config(crtc, &crtc->config, |
| 10772 | "[sw state]"); |
| 10773 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 10774 | } |
| 10775 | } |
| 10776 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10777 | static void |
| 10778 | check_shared_dpll_state(struct drm_device *dev) |
| 10779 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 10780 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10781 | struct intel_crtc *crtc; |
| 10782 | struct intel_dpll_hw_state dpll_hw_state; |
| 10783 | int i; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10784 | |
| 10785 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 10786 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 10787 | int enabled_crtcs = 0, active_crtcs = 0; |
| 10788 | bool active; |
| 10789 | |
| 10790 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
| 10791 | |
| 10792 | DRM_DEBUG_KMS("%s\n", pll->name); |
| 10793 | |
| 10794 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
| 10795 | |
| 10796 | WARN(pll->active > pll->refcount, |
| 10797 | "more active pll users than references: %i vs %i\n", |
| 10798 | pll->active, pll->refcount); |
| 10799 | WARN(pll->active && !pll->on, |
| 10800 | "pll in active use but not on in sw tracking\n"); |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 10801 | WARN(pll->on && !pll->active, |
| 10802 | "pll in on but not on in use in sw tracking\n"); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10803 | WARN(pll->on != active, |
| 10804 | "pll on state mismatch (expected %i, found %i)\n", |
| 10805 | pll->on, active); |
| 10806 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 10807 | for_each_intel_crtc(dev, crtc) { |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10808 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
| 10809 | enabled_crtcs++; |
| 10810 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
| 10811 | active_crtcs++; |
| 10812 | } |
| 10813 | WARN(pll->active != active_crtcs, |
| 10814 | "pll active crtcs mismatch (expected %i, found %i)\n", |
| 10815 | pll->active, active_crtcs); |
| 10816 | WARN(pll->refcount != enabled_crtcs, |
| 10817 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
| 10818 | pll->refcount, enabled_crtcs); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 10819 | |
| 10820 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
| 10821 | sizeof(dpll_hw_state)), |
| 10822 | "pll hw state mismatch\n"); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10823 | } |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10824 | } |
| 10825 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 10826 | void |
| 10827 | intel_modeset_check_state(struct drm_device *dev) |
| 10828 | { |
| 10829 | check_connector_state(dev); |
| 10830 | check_encoder_state(dev); |
| 10831 | check_crtc_state(dev); |
| 10832 | check_shared_dpll_state(dev); |
| 10833 | } |
| 10834 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10835 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
| 10836 | int dotclock) |
| 10837 | { |
| 10838 | /* |
| 10839 | * FDI already provided one idea for the dotclock. |
| 10840 | * Yell if the encoder disagrees. |
| 10841 | */ |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 10842 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10843 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 10844 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10845 | } |
| 10846 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 10847 | static void update_scanline_offset(struct intel_crtc *crtc) |
| 10848 | { |
| 10849 | struct drm_device *dev = crtc->base.dev; |
| 10850 | |
| 10851 | /* |
| 10852 | * The scanline counter increments at the leading edge of hsync. |
| 10853 | * |
| 10854 | * On most platforms it starts counting from vtotal-1 on the |
| 10855 | * first active line. That means the scanline counter value is |
| 10856 | * always one less than what we would expect. Ie. just after |
| 10857 | * start of vblank, which also occurs at start of hsync (on the |
| 10858 | * last active line), the scanline counter will read vblank_start-1. |
| 10859 | * |
| 10860 | * On gen2 the scanline counter starts counting from 1 instead |
| 10861 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
| 10862 | * to keep the value positive), instead of adding one. |
| 10863 | * |
| 10864 | * On HSW+ the behaviour of the scanline counter depends on the output |
| 10865 | * type. For DP ports it behaves like most other platforms, but on HDMI |
| 10866 | * there's an extra 1 line difference. So we need to add two instead of |
| 10867 | * one to the value. |
| 10868 | */ |
| 10869 | if (IS_GEN2(dev)) { |
| 10870 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
| 10871 | int vtotal; |
| 10872 | |
| 10873 | vtotal = mode->crtc_vtotal; |
| 10874 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 10875 | vtotal /= 2; |
| 10876 | |
| 10877 | crtc->scanline_offset = vtotal - 1; |
| 10878 | } else if (HAS_DDI(dev) && |
| 10879 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { |
| 10880 | crtc->scanline_offset = 2; |
| 10881 | } else |
| 10882 | crtc->scanline_offset = 1; |
| 10883 | } |
| 10884 | |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 10885 | static int __intel_set_mode(struct drm_crtc *crtc, |
| 10886 | struct drm_display_mode *mode, |
| 10887 | int x, int y, struct drm_framebuffer *fb) |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10888 | { |
| 10889 | struct drm_device *dev = crtc->dev; |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 10890 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 4b4b923 | 2013-10-26 17:59:30 +0300 | [diff] [blame] | 10891 | struct drm_display_mode *saved_mode; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10892 | struct intel_crtc_config *pipe_config = NULL; |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10893 | struct intel_crtc *intel_crtc; |
| 10894 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 10895 | int ret = 0; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10896 | |
Ville Syrjälä | 4b4b923 | 2013-10-26 17:59:30 +0300 | [diff] [blame] | 10897 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 10898 | if (!saved_mode) |
| 10899 | return -ENOMEM; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10900 | |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 10901 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10902 | &prepare_pipes, &disable_pipes); |
| 10903 | |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 10904 | *saved_mode = crtc->mode; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10905 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10906 | /* Hack: Because we don't (yet) support global modeset on multiple |
| 10907 | * crtcs, we don't keep track of the new mode for more than one crtc. |
| 10908 | * Hence simply check whether any bit is set in modeset_pipes in all the |
| 10909 | * pieces of code that are not yet converted to deal with mutliple crtcs |
| 10910 | * changing their mode at the same time. */ |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10911 | if (modeset_pipes) { |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 10912 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10913 | if (IS_ERR(pipe_config)) { |
| 10914 | ret = PTR_ERR(pipe_config); |
| 10915 | pipe_config = NULL; |
| 10916 | |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 10917 | goto out; |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10918 | } |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 10919 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
| 10920 | "[modeset]"); |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 10921 | to_intel_crtc(crtc)->new_config = pipe_config; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10922 | } |
| 10923 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 10924 | /* |
| 10925 | * See if the config requires any additional preparation, e.g. |
| 10926 | * to adjust global state with pipes off. We need to do this |
| 10927 | * here so we can get the modeset_pipe updated config for the new |
| 10928 | * mode set on this crtc. For other crtcs we need to use the |
| 10929 | * adjusted_mode bits in the crtc directly. |
| 10930 | */ |
Ville Syrjälä | c164f83 | 2013-11-05 22:34:12 +0200 | [diff] [blame] | 10931 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 10932 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 10933 | |
Ville Syrjälä | c164f83 | 2013-11-05 22:34:12 +0200 | [diff] [blame] | 10934 | /* may have added more to prepare_pipes than we should */ |
| 10935 | prepare_pipes &= ~disable_pipes; |
| 10936 | } |
| 10937 | |
Daniel Vetter | 460da916 | 2013-03-27 00:44:51 +0100 | [diff] [blame] | 10938 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
| 10939 | intel_crtc_disable(&intel_crtc->base); |
| 10940 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10941 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
| 10942 | if (intel_crtc->base.enabled) |
| 10943 | dev_priv->display.crtc_disable(&intel_crtc->base); |
| 10944 | } |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10945 | |
Daniel Vetter | 6c4c86f | 2012-09-10 21:58:30 +0200 | [diff] [blame] | 10946 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
| 10947 | * to set it here already despite that we pass it down the callchain. |
| 10948 | */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10949 | if (modeset_pipes) { |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10950 | crtc->mode = *mode; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10951 | /* mode_set/enable/disable functions rely on a correct pipe |
| 10952 | * config. */ |
| 10953 | to_intel_crtc(crtc)->config = *pipe_config; |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 10954 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
Ville Syrjälä | c326c0a | 2013-10-28 12:53:41 +0200 | [diff] [blame] | 10955 | |
| 10956 | /* |
| 10957 | * Calculate and store various constants which |
| 10958 | * are later needed by vblank and swap-completion |
| 10959 | * timestamping. They are derived from true hwmode. |
| 10960 | */ |
| 10961 | drm_calc_timestamping_constants(crtc, |
| 10962 | &pipe_config->adjusted_mode); |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 10963 | } |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 10964 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 10965 | /* Only after disabling all output pipelines that will be changed can we |
| 10966 | * update the the output configuration. */ |
| 10967 | intel_modeset_update_state(dev, prepare_pipes); |
| 10968 | |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 10969 | if (dev_priv->display.modeset_global_resources) |
| 10970 | dev_priv->display.modeset_global_resources(dev); |
| 10971 | |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 10972 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
| 10973 | * on the DPLL. |
| 10974 | */ |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 10975 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 10976 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
| 10977 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
| 10978 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Daniel Vetter | 4c10794 | 2014-04-24 23:55:05 +0200 | [diff] [blame] | 10979 | |
| 10980 | mutex_lock(&dev->struct_mutex); |
| 10981 | ret = intel_pin_and_fence_fb_obj(dev, |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 10982 | obj, |
Daniel Vetter | 4c10794 | 2014-04-24 23:55:05 +0200 | [diff] [blame] | 10983 | NULL); |
| 10984 | if (ret != 0) { |
| 10985 | DRM_ERROR("pin & fence failed\n"); |
| 10986 | mutex_unlock(&dev->struct_mutex); |
| 10987 | goto done; |
| 10988 | } |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 10989 | if (old_fb) |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 10990 | intel_unpin_fb_obj(old_obj); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 10991 | i915_gem_track_fb(old_obj, obj, |
| 10992 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
Daniel Vetter | 4c10794 | 2014-04-24 23:55:05 +0200 | [diff] [blame] | 10993 | mutex_unlock(&dev->struct_mutex); |
| 10994 | |
| 10995 | crtc->primary->fb = fb; |
| 10996 | crtc->x = x; |
| 10997 | crtc->y = y; |
| 10998 | |
Daniel Vetter | 4271b75 | 2014-04-24 23:55:00 +0200 | [diff] [blame] | 10999 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
| 11000 | x, y, fb); |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 11001 | if (ret) |
| 11002 | goto done; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 11003 | } |
| 11004 | |
| 11005 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 11006 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
| 11007 | update_scanline_offset(intel_crtc); |
| 11008 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 11009 | dev_priv->display.crtc_enable(&intel_crtc->base); |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 11010 | } |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 11011 | |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 11012 | /* FIXME: add subpixel order */ |
| 11013 | done: |
Ville Syrjälä | 4b4b923 | 2013-10-26 17:59:30 +0300 | [diff] [blame] | 11014 | if (ret && crtc->enabled) |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 11015 | crtc->mode = *saved_mode; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 11016 | |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 11017 | out: |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 11018 | kfree(pipe_config); |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 11019 | kfree(saved_mode); |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 11020 | return ret; |
| 11021 | } |
| 11022 | |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 11023 | static int intel_set_mode(struct drm_crtc *crtc, |
| 11024 | struct drm_display_mode *mode, |
| 11025 | int x, int y, struct drm_framebuffer *fb) |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 11026 | { |
| 11027 | int ret; |
| 11028 | |
| 11029 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
| 11030 | |
| 11031 | if (ret == 0) |
| 11032 | intel_modeset_check_state(crtc->dev); |
| 11033 | |
| 11034 | return ret; |
| 11035 | } |
| 11036 | |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 11037 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
| 11038 | { |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11039 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 11040 | } |
| 11041 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 11042 | #undef for_each_intel_crtc_masked |
| 11043 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 11044 | static void intel_set_config_free(struct intel_set_config *config) |
| 11045 | { |
| 11046 | if (!config) |
| 11047 | return; |
| 11048 | |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 11049 | kfree(config->save_connector_encoders); |
| 11050 | kfree(config->save_encoder_crtcs); |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11051 | kfree(config->save_crtc_enabled); |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 11052 | kfree(config); |
| 11053 | } |
| 11054 | |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11055 | static int intel_set_config_save_state(struct drm_device *dev, |
| 11056 | struct intel_set_config *config) |
| 11057 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11058 | struct drm_crtc *crtc; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11059 | struct drm_encoder *encoder; |
| 11060 | struct drm_connector *connector; |
| 11061 | int count; |
| 11062 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11063 | config->save_crtc_enabled = |
| 11064 | kcalloc(dev->mode_config.num_crtc, |
| 11065 | sizeof(bool), GFP_KERNEL); |
| 11066 | if (!config->save_crtc_enabled) |
| 11067 | return -ENOMEM; |
| 11068 | |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 11069 | config->save_encoder_crtcs = |
| 11070 | kcalloc(dev->mode_config.num_encoder, |
| 11071 | sizeof(struct drm_crtc *), GFP_KERNEL); |
| 11072 | if (!config->save_encoder_crtcs) |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11073 | return -ENOMEM; |
| 11074 | |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 11075 | config->save_connector_encoders = |
| 11076 | kcalloc(dev->mode_config.num_connector, |
| 11077 | sizeof(struct drm_encoder *), GFP_KERNEL); |
| 11078 | if (!config->save_connector_encoders) |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11079 | return -ENOMEM; |
| 11080 | |
| 11081 | /* Copy data. Note that driver private data is not affected. |
| 11082 | * Should anything bad happen only the expected state is |
| 11083 | * restored, not the drivers personal bookkeeping. |
| 11084 | */ |
| 11085 | count = 0; |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 11086 | for_each_crtc(dev, crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11087 | config->save_crtc_enabled[count++] = crtc->enabled; |
| 11088 | } |
| 11089 | |
| 11090 | count = 0; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11091 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 11092 | config->save_encoder_crtcs[count++] = encoder->crtc; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11093 | } |
| 11094 | |
| 11095 | count = 0; |
| 11096 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 11097 | config->save_connector_encoders[count++] = connector->encoder; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11098 | } |
| 11099 | |
| 11100 | return 0; |
| 11101 | } |
| 11102 | |
| 11103 | static void intel_set_config_restore_state(struct drm_device *dev, |
| 11104 | struct intel_set_config *config) |
| 11105 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11106 | struct intel_crtc *crtc; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11107 | struct intel_encoder *encoder; |
| 11108 | struct intel_connector *connector; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11109 | int count; |
| 11110 | |
| 11111 | count = 0; |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 11112 | for_each_intel_crtc(dev, crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11113 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 11114 | |
| 11115 | if (crtc->new_enabled) |
| 11116 | crtc->new_config = &crtc->config; |
| 11117 | else |
| 11118 | crtc->new_config = NULL; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11119 | } |
| 11120 | |
| 11121 | count = 0; |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 11122 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11123 | encoder->new_crtc = |
| 11124 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11125 | } |
| 11126 | |
| 11127 | count = 0; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11128 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
| 11129 | connector->new_encoder = |
| 11130 | to_intel_encoder(config->save_connector_encoders[count++]); |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 11131 | } |
| 11132 | } |
| 11133 | |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 11134 | static bool |
Chris Wilson | 2e57f47 | 2013-07-17 12:14:40 +0100 | [diff] [blame] | 11135 | is_crtc_connector_off(struct drm_mode_set *set) |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 11136 | { |
| 11137 | int i; |
| 11138 | |
Chris Wilson | 2e57f47 | 2013-07-17 12:14:40 +0100 | [diff] [blame] | 11139 | if (set->num_connectors == 0) |
| 11140 | return false; |
| 11141 | |
| 11142 | if (WARN_ON(set->connectors == NULL)) |
| 11143 | return false; |
| 11144 | |
| 11145 | for (i = 0; i < set->num_connectors; i++) |
| 11146 | if (set->connectors[i]->encoder && |
| 11147 | set->connectors[i]->encoder->crtc == set->crtc && |
| 11148 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 11149 | return true; |
| 11150 | |
| 11151 | return false; |
| 11152 | } |
| 11153 | |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11154 | static void |
| 11155 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
| 11156 | struct intel_set_config *config) |
| 11157 | { |
| 11158 | |
| 11159 | /* We should be able to check here if the fb has the same properties |
| 11160 | * and then just flip_or_move it */ |
Chris Wilson | 2e57f47 | 2013-07-17 12:14:40 +0100 | [diff] [blame] | 11161 | if (is_crtc_connector_off(set)) { |
| 11162 | config->mode_changed = true; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11163 | } else if (set->crtc->primary->fb != set->fb) { |
Matt Roper | 3b150f0 | 2014-05-29 08:06:53 -0700 | [diff] [blame] | 11164 | /* |
| 11165 | * If we have no fb, we can only flip as long as the crtc is |
| 11166 | * active, otherwise we need a full mode set. The crtc may |
| 11167 | * be active if we've only disabled the primary plane, or |
| 11168 | * in fastboot situations. |
| 11169 | */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11170 | if (set->crtc->primary->fb == NULL) { |
Jesse Barnes | 319d982 | 2013-06-26 01:38:19 +0300 | [diff] [blame] | 11171 | struct intel_crtc *intel_crtc = |
| 11172 | to_intel_crtc(set->crtc); |
| 11173 | |
Matt Roper | 3b150f0 | 2014-05-29 08:06:53 -0700 | [diff] [blame] | 11174 | if (intel_crtc->active) { |
Jesse Barnes | 319d982 | 2013-06-26 01:38:19 +0300 | [diff] [blame] | 11175 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
| 11176 | config->fb_changed = true; |
| 11177 | } else { |
| 11178 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
| 11179 | config->mode_changed = true; |
| 11180 | } |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11181 | } else if (set->fb == NULL) { |
| 11182 | config->mode_changed = true; |
Daniel Vetter | 72f4901 | 2013-03-28 16:01:35 +0100 | [diff] [blame] | 11183 | } else if (set->fb->pixel_format != |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11184 | set->crtc->primary->fb->pixel_format) { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11185 | config->mode_changed = true; |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 11186 | } else { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11187 | config->fb_changed = true; |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 11188 | } |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11189 | } |
| 11190 | |
Daniel Vetter | 835c587 | 2012-07-10 18:11:08 +0200 | [diff] [blame] | 11191 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11192 | config->fb_changed = true; |
| 11193 | |
| 11194 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
| 11195 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
| 11196 | drm_mode_debug_printmodeline(&set->crtc->mode); |
| 11197 | drm_mode_debug_printmodeline(set->mode); |
| 11198 | config->mode_changed = true; |
| 11199 | } |
Chris Wilson | a1d9570 | 2013-08-13 18:48:47 +0100 | [diff] [blame] | 11200 | |
| 11201 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
| 11202 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11203 | } |
| 11204 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11205 | static int |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11206 | intel_modeset_stage_output_state(struct drm_device *dev, |
| 11207 | struct drm_mode_set *set, |
| 11208 | struct intel_set_config *config) |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11209 | { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11210 | struct intel_connector *connector; |
| 11211 | struct intel_encoder *encoder; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11212 | struct intel_crtc *crtc; |
Paulo Zanoni | f3f0857 | 2013-08-12 14:56:53 -0300 | [diff] [blame] | 11213 | int ro; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11214 | |
Damien Lespiau | 9abdda7 | 2013-02-13 13:29:23 +0000 | [diff] [blame] | 11215 | /* The upper layers ensure that we either disable a crtc or have a list |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11216 | * of connectors. For paranoia, double-check this. */ |
| 11217 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
| 11218 | WARN_ON(set->fb && (set->num_connectors == 0)); |
| 11219 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11220 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 11221 | base.head) { |
| 11222 | /* Otherwise traverse passed in connector list and get encoders |
| 11223 | * for them. */ |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11224 | for (ro = 0; ro < set->num_connectors; ro++) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11225 | if (set->connectors[ro] == &connector->base) { |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 11226 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11227 | break; |
| 11228 | } |
| 11229 | } |
| 11230 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11231 | /* If we disable the crtc, disable all its connectors. Also, if |
| 11232 | * the connector is on the changing crtc but not on the new |
| 11233 | * connector list, disable it. */ |
| 11234 | if ((!set->fb || ro == set->num_connectors) && |
| 11235 | connector->base.encoder && |
| 11236 | connector->base.encoder->crtc == set->crtc) { |
| 11237 | connector->new_encoder = NULL; |
| 11238 | |
| 11239 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
| 11240 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 11241 | connector->base.name); |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11242 | } |
| 11243 | |
| 11244 | |
| 11245 | if (&connector->new_encoder->base != connector->base.encoder) { |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11246 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11247 | config->mode_changed = true; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11248 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11249 | } |
| 11250 | /* connector->new_encoder is now updated for all connectors. */ |
| 11251 | |
| 11252 | /* Update crtc of enabled connectors. */ |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11253 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 11254 | base.head) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11255 | struct drm_crtc *new_crtc; |
| 11256 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11257 | if (!connector->new_encoder) |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11258 | continue; |
| 11259 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11260 | new_crtc = connector->new_encoder->base.crtc; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11261 | |
| 11262 | for (ro = 0; ro < set->num_connectors; ro++) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11263 | if (set->connectors[ro] == &connector->base) |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11264 | new_crtc = set->crtc; |
| 11265 | } |
| 11266 | |
| 11267 | /* Make sure the new CRTC will work with the encoder */ |
Thierry Reding | 1450991 | 2014-01-13 12:00:22 +0100 | [diff] [blame] | 11268 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
| 11269 | new_crtc)) { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11270 | return -EINVAL; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11271 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 11272 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11273 | |
| 11274 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
| 11275 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 11276 | connector->base.name, |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11277 | new_crtc->base.id); |
| 11278 | } |
| 11279 | |
| 11280 | /* Check for any encoders that needs to be disabled. */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 11281 | for_each_intel_encoder(dev, encoder) { |
Paulo Zanoni | 5a65f35 | 2014-01-07 14:55:53 -0200 | [diff] [blame] | 11282 | int num_connectors = 0; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11283 | list_for_each_entry(connector, |
| 11284 | &dev->mode_config.connector_list, |
| 11285 | base.head) { |
| 11286 | if (connector->new_encoder == encoder) { |
| 11287 | WARN_ON(!connector->new_encoder->new_crtc); |
Paulo Zanoni | 5a65f35 | 2014-01-07 14:55:53 -0200 | [diff] [blame] | 11288 | num_connectors++; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11289 | } |
| 11290 | } |
Paulo Zanoni | 5a65f35 | 2014-01-07 14:55:53 -0200 | [diff] [blame] | 11291 | |
| 11292 | if (num_connectors == 0) |
| 11293 | encoder->new_crtc = NULL; |
| 11294 | else if (num_connectors > 1) |
| 11295 | return -EINVAL; |
| 11296 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11297 | /* Only now check for crtc changes so we don't miss encoders |
| 11298 | * that will be disabled. */ |
| 11299 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11300 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11301 | config->mode_changed = true; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11302 | } |
| 11303 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11304 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 11305 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 11306 | base.head) { |
| 11307 | if (connector->new_encoder) |
| 11308 | if (connector->new_encoder != connector->encoder) |
| 11309 | connector->encoder = connector->new_encoder; |
| 11310 | } |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 11311 | for_each_intel_crtc(dev, crtc) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11312 | crtc->new_enabled = false; |
| 11313 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 11314 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11315 | if (encoder->new_crtc == crtc) { |
| 11316 | crtc->new_enabled = true; |
| 11317 | break; |
| 11318 | } |
| 11319 | } |
| 11320 | |
| 11321 | if (crtc->new_enabled != crtc->base.enabled) { |
| 11322 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", |
| 11323 | crtc->new_enabled ? "en" : "dis"); |
| 11324 | config->mode_changed = true; |
| 11325 | } |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 11326 | |
| 11327 | if (crtc->new_enabled) |
| 11328 | crtc->new_config = &crtc->config; |
| 11329 | else |
| 11330 | crtc->new_config = NULL; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 11331 | } |
| 11332 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11333 | return 0; |
| 11334 | } |
| 11335 | |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 11336 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
| 11337 | { |
| 11338 | struct drm_device *dev = crtc->base.dev; |
| 11339 | struct intel_encoder *encoder; |
| 11340 | struct intel_connector *connector; |
| 11341 | |
| 11342 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", |
| 11343 | pipe_name(crtc->pipe)); |
| 11344 | |
| 11345 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
| 11346 | if (connector->new_encoder && |
| 11347 | connector->new_encoder->new_crtc == crtc) |
| 11348 | connector->new_encoder = NULL; |
| 11349 | } |
| 11350 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 11351 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 11352 | if (encoder->new_crtc == crtc) |
| 11353 | encoder->new_crtc = NULL; |
| 11354 | } |
| 11355 | |
| 11356 | crtc->new_enabled = false; |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 11357 | crtc->new_config = NULL; |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 11358 | } |
| 11359 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11360 | static int intel_crtc_set_config(struct drm_mode_set *set) |
| 11361 | { |
| 11362 | struct drm_device *dev; |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11363 | struct drm_mode_set save_set; |
| 11364 | struct intel_set_config *config; |
| 11365 | int ret; |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11366 | |
Daniel Vetter | 8d3e375 | 2012-07-05 16:09:09 +0200 | [diff] [blame] | 11367 | BUG_ON(!set); |
| 11368 | BUG_ON(!set->crtc); |
| 11369 | BUG_ON(!set->crtc->helper_private); |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11370 | |
Daniel Vetter | 7e53f3a | 2013-01-21 10:52:17 +0100 | [diff] [blame] | 11371 | /* Enforce sane interface api - has been abused by the fb helper. */ |
| 11372 | BUG_ON(!set->mode && set->fb); |
| 11373 | BUG_ON(set->fb && set->num_connectors == 0); |
Daniel Vetter | 431e50f | 2012-07-10 17:53:42 +0200 | [diff] [blame] | 11374 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11375 | if (set->fb) { |
| 11376 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
| 11377 | set->crtc->base.id, set->fb->base.id, |
| 11378 | (int)set->num_connectors, set->x, set->y); |
| 11379 | } else { |
| 11380 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11381 | } |
| 11382 | |
| 11383 | dev = set->crtc->dev; |
| 11384 | |
| 11385 | ret = -ENOMEM; |
| 11386 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
| 11387 | if (!config) |
| 11388 | goto out_config; |
| 11389 | |
| 11390 | ret = intel_set_config_save_state(dev, config); |
| 11391 | if (ret) |
| 11392 | goto out_config; |
| 11393 | |
| 11394 | save_set.crtc = set->crtc; |
| 11395 | save_set.mode = &set->crtc->mode; |
| 11396 | save_set.x = set->crtc->x; |
| 11397 | save_set.y = set->crtc->y; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11398 | save_set.fb = set->crtc->primary->fb; |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11399 | |
| 11400 | /* Compute whether we need a full modeset, only an fb base update or no |
| 11401 | * change at all. In the future we might also check whether only the |
| 11402 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
| 11403 | * such cases. */ |
| 11404 | intel_set_config_compute_mode_changes(set, config); |
| 11405 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11406 | ret = intel_modeset_stage_output_state(dev, set, config); |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 11407 | if (ret) |
| 11408 | goto fail; |
| 11409 | |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11410 | if (config->mode_changed) { |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 11411 | ret = intel_set_mode(set->crtc, set->mode, |
| 11412 | set->x, set->y, set->fb); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 11413 | } else if (config->fb_changed) { |
Matt Roper | 3b150f0 | 2014-05-29 08:06:53 -0700 | [diff] [blame] | 11414 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
| 11415 | |
Ville Syrjälä | 4878cae | 2013-02-18 19:08:48 +0200 | [diff] [blame] | 11416 | intel_crtc_wait_for_pending_flips(set->crtc); |
| 11417 | |
Daniel Vetter | 4f660f4 | 2012-07-02 09:47:37 +0200 | [diff] [blame] | 11418 | ret = intel_pipe_set_base(set->crtc, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 11419 | set->x, set->y, set->fb); |
Matt Roper | 3b150f0 | 2014-05-29 08:06:53 -0700 | [diff] [blame] | 11420 | |
| 11421 | /* |
| 11422 | * We need to make sure the primary plane is re-enabled if it |
| 11423 | * has previously been turned off. |
| 11424 | */ |
| 11425 | if (!intel_crtc->primary_enabled && ret == 0) { |
| 11426 | WARN_ON(!intel_crtc->active); |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 11427 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
Matt Roper | 3b150f0 | 2014-05-29 08:06:53 -0700 | [diff] [blame] | 11428 | } |
| 11429 | |
Jesse Barnes | 7ca51a3 | 2014-01-07 13:50:49 -0800 | [diff] [blame] | 11430 | /* |
| 11431 | * In the fastboot case this may be our only check of the |
| 11432 | * state after boot. It would be better to only do it on |
| 11433 | * the first update, but we don't have a nice way of doing that |
| 11434 | * (and really, set_config isn't used much for high freq page |
| 11435 | * flipping, so increasing its cost here shouldn't be a big |
| 11436 | * deal). |
| 11437 | */ |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 11438 | if (i915.fastboot && ret == 0) |
Jesse Barnes | 7ca51a3 | 2014-01-07 13:50:49 -0800 | [diff] [blame] | 11439 | intel_modeset_check_state(set->crtc->dev); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11440 | } |
| 11441 | |
Chris Wilson | 2d05eae | 2013-05-03 17:36:25 +0100 | [diff] [blame] | 11442 | if (ret) { |
Daniel Vetter | bf67dfe | 2013-06-25 11:06:52 +0200 | [diff] [blame] | 11443 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
| 11444 | set->crtc->base.id, ret); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11445 | fail: |
Chris Wilson | 2d05eae | 2013-05-03 17:36:25 +0100 | [diff] [blame] | 11446 | intel_set_config_restore_state(dev, config); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11447 | |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 11448 | /* |
| 11449 | * HACK: if the pipe was on, but we didn't have a framebuffer, |
| 11450 | * force the pipe off to avoid oopsing in the modeset code |
| 11451 | * due to fb==NULL. This should only happen during boot since |
| 11452 | * we don't yet reconstruct the FB from the hardware state. |
| 11453 | */ |
| 11454 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) |
| 11455 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); |
| 11456 | |
Chris Wilson | 2d05eae | 2013-05-03 17:36:25 +0100 | [diff] [blame] | 11457 | /* Try to restore the config */ |
| 11458 | if (config->mode_changed && |
| 11459 | intel_set_mode(save_set.crtc, save_set.mode, |
| 11460 | save_set.x, save_set.y, save_set.fb)) |
| 11461 | DRM_ERROR("failed to restore config after modeset failure\n"); |
| 11462 | } |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11463 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 11464 | out_config: |
| 11465 | intel_set_config_free(config); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11466 | return ret; |
| 11467 | } |
| 11468 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 11469 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 11470 | .gamma_set = intel_crtc_gamma_set, |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 11471 | .set_config = intel_crtc_set_config, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 11472 | .destroy = intel_crtc_destroy, |
| 11473 | .page_flip = intel_crtc_page_flip, |
| 11474 | }; |
| 11475 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11476 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 11477 | struct intel_shared_dpll *pll, |
| 11478 | struct intel_dpll_hw_state *hw_state) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 11479 | { |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11480 | uint32_t val; |
| 11481 | |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 11482 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 11483 | return false; |
| 11484 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11485 | val = I915_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 11486 | hw_state->dpll = val; |
| 11487 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
| 11488 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11489 | |
| 11490 | return val & DPLL_VCO_ENABLE; |
| 11491 | } |
| 11492 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 11493 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
| 11494 | struct intel_shared_dpll *pll) |
| 11495 | { |
| 11496 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
| 11497 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
| 11498 | } |
| 11499 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11500 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
| 11501 | struct intel_shared_dpll *pll) |
| 11502 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11503 | /* PCH refclock must be enabled first */ |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 11504 | ibx_assert_pch_refclk_enabled(dev_priv); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11505 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 11506 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
| 11507 | |
| 11508 | /* Wait for the clocks to stabilize. */ |
| 11509 | POSTING_READ(PCH_DPLL(pll->id)); |
| 11510 | udelay(150); |
| 11511 | |
| 11512 | /* The pixel multiplier can only be updated once the |
| 11513 | * DPLL is enabled and the clocks are stable. |
| 11514 | * |
| 11515 | * So write it again. |
| 11516 | */ |
| 11517 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
| 11518 | POSTING_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11519 | udelay(200); |
| 11520 | } |
| 11521 | |
| 11522 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
| 11523 | struct intel_shared_dpll *pll) |
| 11524 | { |
| 11525 | struct drm_device *dev = dev_priv->dev; |
| 11526 | struct intel_crtc *crtc; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11527 | |
| 11528 | /* Make sure no transcoder isn't still depending on us. */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 11529 | for_each_intel_crtc(dev, crtc) { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11530 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
| 11531 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
| 11532 | } |
| 11533 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 11534 | I915_WRITE(PCH_DPLL(pll->id), 0); |
| 11535 | POSTING_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11536 | udelay(200); |
| 11537 | } |
| 11538 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 11539 | static char *ibx_pch_dpll_names[] = { |
| 11540 | "PCH DPLL A", |
| 11541 | "PCH DPLL B", |
| 11542 | }; |
| 11543 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 11544 | static void ibx_pch_dpll_init(struct drm_device *dev) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 11545 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11546 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 11547 | int i; |
| 11548 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 11549 | dev_priv->num_shared_dpll = 2; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 11550 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 11551 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 11552 | dev_priv->shared_dplls[i].id = i; |
| 11553 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 11554 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11555 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
| 11556 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11557 | dev_priv->shared_dplls[i].get_hw_state = |
| 11558 | ibx_pch_dpll_get_hw_state; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 11559 | } |
| 11560 | } |
| 11561 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 11562 | static void intel_shared_dpll_init(struct drm_device *dev) |
| 11563 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 11564 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 11565 | |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 11566 | if (HAS_DDI(dev)) |
| 11567 | intel_ddi_pll_init(dev); |
| 11568 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 11569 | ibx_pch_dpll_init(dev); |
| 11570 | else |
| 11571 | dev_priv->num_shared_dpll = 0; |
| 11572 | |
| 11573 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 11574 | } |
| 11575 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11576 | static int |
| 11577 | intel_primary_plane_disable(struct drm_plane *plane) |
| 11578 | { |
| 11579 | struct drm_device *dev = plane->dev; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11580 | struct intel_crtc *intel_crtc; |
| 11581 | |
| 11582 | if (!plane->fb) |
| 11583 | return 0; |
| 11584 | |
| 11585 | BUG_ON(!plane->crtc); |
| 11586 | |
| 11587 | intel_crtc = to_intel_crtc(plane->crtc); |
| 11588 | |
| 11589 | /* |
| 11590 | * Even though we checked plane->fb above, it's still possible that |
| 11591 | * the primary plane has been implicitly disabled because the crtc |
| 11592 | * coordinates given weren't visible, or because we detected |
| 11593 | * that it was 100% covered by a sprite plane. Or, the CRTC may be |
| 11594 | * off and we've set a fb, but haven't actually turned on the CRTC yet. |
| 11595 | * In either case, we need to unpin the FB and let the fb pointer get |
| 11596 | * updated, but otherwise we don't need to touch the hardware. |
| 11597 | */ |
| 11598 | if (!intel_crtc->primary_enabled) |
| 11599 | goto disable_unpin; |
| 11600 | |
| 11601 | intel_crtc_wait_for_pending_flips(plane->crtc); |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 11602 | intel_disable_primary_hw_plane(plane, plane->crtc); |
| 11603 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11604 | disable_unpin: |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11605 | mutex_lock(&dev->struct_mutex); |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 11606 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11607 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 11608 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11609 | mutex_unlock(&dev->struct_mutex); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11610 | plane->fb = NULL; |
| 11611 | |
| 11612 | return 0; |
| 11613 | } |
| 11614 | |
| 11615 | static int |
| 11616 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, |
| 11617 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
| 11618 | unsigned int crtc_w, unsigned int crtc_h, |
| 11619 | uint32_t src_x, uint32_t src_y, |
| 11620 | uint32_t src_w, uint32_t src_h) |
| 11621 | { |
| 11622 | struct drm_device *dev = crtc->dev; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 11623 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 11625 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 11626 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11627 | struct drm_rect dest = { |
| 11628 | /* integer pixels */ |
| 11629 | .x1 = crtc_x, |
| 11630 | .y1 = crtc_y, |
| 11631 | .x2 = crtc_x + crtc_w, |
| 11632 | .y2 = crtc_y + crtc_h, |
| 11633 | }; |
| 11634 | struct drm_rect src = { |
| 11635 | /* 16.16 fixed point */ |
| 11636 | .x1 = src_x, |
| 11637 | .y1 = src_y, |
| 11638 | .x2 = src_x + src_w, |
| 11639 | .y2 = src_y + src_h, |
| 11640 | }; |
| 11641 | const struct drm_rect clip = { |
| 11642 | /* integer pixels */ |
| 11643 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
| 11644 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
| 11645 | }; |
Sonika Jindal | ce54d85 | 2014-08-21 11:44:39 +0530 | [diff] [blame] | 11646 | const struct { |
| 11647 | int crtc_x, crtc_y; |
| 11648 | unsigned int crtc_w, crtc_h; |
| 11649 | uint32_t src_x, src_y, src_w, src_h; |
| 11650 | } orig = { |
| 11651 | .crtc_x = crtc_x, |
| 11652 | .crtc_y = crtc_y, |
| 11653 | .crtc_w = crtc_w, |
| 11654 | .crtc_h = crtc_h, |
| 11655 | .src_x = src_x, |
| 11656 | .src_y = src_y, |
| 11657 | .src_w = src_w, |
| 11658 | .src_h = src_h, |
| 11659 | }; |
| 11660 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11661 | bool visible; |
| 11662 | int ret; |
| 11663 | |
| 11664 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
| 11665 | &src, &dest, &clip, |
| 11666 | DRM_PLANE_HELPER_NO_SCALING, |
| 11667 | DRM_PLANE_HELPER_NO_SCALING, |
| 11668 | false, true, &visible); |
| 11669 | |
| 11670 | if (ret) |
| 11671 | return ret; |
| 11672 | |
| 11673 | /* |
| 11674 | * If the CRTC isn't enabled, we're just pinning the framebuffer, |
| 11675 | * updating the fb pointer, and returning without touching the |
| 11676 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to |
| 11677 | * turn on the display with all planes setup as desired. |
| 11678 | */ |
| 11679 | if (!crtc->enabled) { |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11680 | mutex_lock(&dev->struct_mutex); |
| 11681 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11682 | /* |
| 11683 | * If we already called setplane while the crtc was disabled, |
| 11684 | * we may have an fb pinned; unpin it. |
| 11685 | */ |
| 11686 | if (plane->fb) |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11687 | intel_unpin_fb_obj(old_obj); |
| 11688 | |
| 11689 | i915_gem_track_fb(old_obj, obj, |
| 11690 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11691 | |
| 11692 | /* Pin and return without programming hardware */ |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11693 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
| 11694 | mutex_unlock(&dev->struct_mutex); |
| 11695 | |
| 11696 | return ret; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11697 | } |
| 11698 | |
| 11699 | intel_crtc_wait_for_pending_flips(crtc); |
| 11700 | |
| 11701 | /* |
| 11702 | * If clipping results in a non-visible primary plane, we'll disable |
| 11703 | * the primary plane. Note that this is a bit different than what |
| 11704 | * happens if userspace explicitly disables the plane by passing fb=0 |
| 11705 | * because plane->fb still gets set and pinned. |
| 11706 | */ |
| 11707 | if (!visible) { |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11708 | mutex_lock(&dev->struct_mutex); |
| 11709 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11710 | /* |
| 11711 | * Try to pin the new fb first so that we can bail out if we |
| 11712 | * fail. |
| 11713 | */ |
| 11714 | if (plane->fb != fb) { |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11715 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11716 | if (ret) { |
| 11717 | mutex_unlock(&dev->struct_mutex); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11718 | return ret; |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11719 | } |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11720 | } |
| 11721 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11722 | i915_gem_track_fb(old_obj, obj, |
| 11723 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
| 11724 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11725 | if (intel_crtc->primary_enabled) |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 11726 | intel_disable_primary_hw_plane(plane, crtc); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11727 | |
| 11728 | |
| 11729 | if (plane->fb != fb) |
| 11730 | if (plane->fb) |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11731 | intel_unpin_fb_obj(old_obj); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11732 | |
Matt Roper | 4c34574 | 2014-07-09 16:22:10 -0700 | [diff] [blame] | 11733 | mutex_unlock(&dev->struct_mutex); |
| 11734 | |
Sonika Jindal | ce54d85 | 2014-08-21 11:44:39 +0530 | [diff] [blame] | 11735 | } else { |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 11736 | if (intel_crtc && intel_crtc->active && |
| 11737 | intel_crtc->primary_enabled) { |
| 11738 | /* |
| 11739 | * FBC does not work on some platforms for rotated |
| 11740 | * planes, so disable it when rotation is not 0 and |
| 11741 | * update it when rotation is set back to 0. |
| 11742 | * |
| 11743 | * FIXME: This is redundant with the fbc update done in |
| 11744 | * the primary plane enable function except that that |
| 11745 | * one is done too late. We eventually need to unify |
| 11746 | * this. |
| 11747 | */ |
| 11748 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
| 11749 | dev_priv->fbc.plane == intel_crtc->plane && |
| 11750 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { |
| 11751 | intel_disable_fbc(dev); |
| 11752 | } |
| 11753 | } |
Sonika Jindal | ce54d85 | 2014-08-21 11:44:39 +0530 | [diff] [blame] | 11754 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); |
| 11755 | if (ret) |
| 11756 | return ret; |
| 11757 | |
| 11758 | if (!intel_crtc->primary_enabled) |
| 11759 | intel_enable_primary_hw_plane(plane, crtc); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11760 | } |
| 11761 | |
Sonika Jindal | ce54d85 | 2014-08-21 11:44:39 +0530 | [diff] [blame] | 11762 | intel_plane->crtc_x = orig.crtc_x; |
| 11763 | intel_plane->crtc_y = orig.crtc_y; |
| 11764 | intel_plane->crtc_w = orig.crtc_w; |
| 11765 | intel_plane->crtc_h = orig.crtc_h; |
| 11766 | intel_plane->src_x = orig.src_x; |
| 11767 | intel_plane->src_y = orig.src_y; |
| 11768 | intel_plane->src_w = orig.src_w; |
| 11769 | intel_plane->src_h = orig.src_h; |
| 11770 | intel_plane->obj = obj; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11771 | |
| 11772 | return 0; |
| 11773 | } |
| 11774 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11775 | /* Common destruction function for both primary and cursor planes */ |
| 11776 | static void intel_plane_destroy(struct drm_plane *plane) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11777 | { |
| 11778 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 11779 | drm_plane_cleanup(plane); |
| 11780 | kfree(intel_plane); |
| 11781 | } |
| 11782 | |
| 11783 | static const struct drm_plane_funcs intel_primary_plane_funcs = { |
| 11784 | .update_plane = intel_primary_plane_setplane, |
| 11785 | .disable_plane = intel_primary_plane_disable, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11786 | .destroy = intel_plane_destroy, |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 11787 | .set_property = intel_plane_set_property |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11788 | }; |
| 11789 | |
| 11790 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
| 11791 | int pipe) |
| 11792 | { |
| 11793 | struct intel_plane *primary; |
| 11794 | const uint32_t *intel_primary_formats; |
| 11795 | int num_formats; |
| 11796 | |
| 11797 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
| 11798 | if (primary == NULL) |
| 11799 | return NULL; |
| 11800 | |
| 11801 | primary->can_scale = false; |
| 11802 | primary->max_downscale = 1; |
| 11803 | primary->pipe = pipe; |
| 11804 | primary->plane = pipe; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 11805 | primary->rotation = BIT(DRM_ROTATE_0); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11806 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
| 11807 | primary->plane = !pipe; |
| 11808 | |
| 11809 | if (INTEL_INFO(dev)->gen <= 3) { |
| 11810 | intel_primary_formats = intel_primary_formats_gen2; |
| 11811 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); |
| 11812 | } else { |
| 11813 | intel_primary_formats = intel_primary_formats_gen4; |
| 11814 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); |
| 11815 | } |
| 11816 | |
| 11817 | drm_universal_plane_init(dev, &primary->base, 0, |
| 11818 | &intel_primary_plane_funcs, |
| 11819 | intel_primary_formats, num_formats, |
| 11820 | DRM_PLANE_TYPE_PRIMARY); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 11821 | |
| 11822 | if (INTEL_INFO(dev)->gen >= 4) { |
| 11823 | if (!dev->mode_config.rotation_property) |
| 11824 | dev->mode_config.rotation_property = |
| 11825 | drm_mode_create_rotation_property(dev, |
| 11826 | BIT(DRM_ROTATE_0) | |
| 11827 | BIT(DRM_ROTATE_180)); |
| 11828 | if (dev->mode_config.rotation_property) |
| 11829 | drm_object_attach_property(&primary->base.base, |
| 11830 | dev->mode_config.rotation_property, |
| 11831 | primary->rotation); |
| 11832 | } |
| 11833 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11834 | return &primary->base; |
| 11835 | } |
| 11836 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11837 | static int |
| 11838 | intel_cursor_plane_disable(struct drm_plane *plane) |
| 11839 | { |
| 11840 | if (!plane->fb) |
| 11841 | return 0; |
| 11842 | |
| 11843 | BUG_ON(!plane->crtc); |
| 11844 | |
| 11845 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); |
| 11846 | } |
| 11847 | |
| 11848 | static int |
| 11849 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, |
| 11850 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
| 11851 | unsigned int crtc_w, unsigned int crtc_h, |
| 11852 | uint32_t src_x, uint32_t src_y, |
| 11853 | uint32_t src_w, uint32_t src_h) |
| 11854 | { |
| 11855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11856 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 11857 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 11858 | struct drm_rect dest = { |
| 11859 | /* integer pixels */ |
| 11860 | .x1 = crtc_x, |
| 11861 | .y1 = crtc_y, |
| 11862 | .x2 = crtc_x + crtc_w, |
| 11863 | .y2 = crtc_y + crtc_h, |
| 11864 | }; |
| 11865 | struct drm_rect src = { |
| 11866 | /* 16.16 fixed point */ |
| 11867 | .x1 = src_x, |
| 11868 | .y1 = src_y, |
| 11869 | .x2 = src_x + src_w, |
| 11870 | .y2 = src_y + src_h, |
| 11871 | }; |
| 11872 | const struct drm_rect clip = { |
| 11873 | /* integer pixels */ |
Ville Syrjälä | 1add143 | 2014-08-12 19:39:52 +0300 | [diff] [blame] | 11874 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
| 11875 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11876 | }; |
| 11877 | bool visible; |
| 11878 | int ret; |
| 11879 | |
| 11880 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
| 11881 | &src, &dest, &clip, |
| 11882 | DRM_PLANE_HELPER_NO_SCALING, |
| 11883 | DRM_PLANE_HELPER_NO_SCALING, |
| 11884 | true, true, &visible); |
| 11885 | if (ret) |
| 11886 | return ret; |
| 11887 | |
| 11888 | crtc->cursor_x = crtc_x; |
| 11889 | crtc->cursor_y = crtc_y; |
| 11890 | if (fb != crtc->cursor->fb) { |
| 11891 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); |
| 11892 | } else { |
| 11893 | intel_crtc_update_cursor(crtc, visible); |
Daniel Vetter | 4ed9109 | 2014-08-08 20:27:01 +0200 | [diff] [blame] | 11894 | |
| 11895 | intel_frontbuffer_flip(crtc->dev, |
| 11896 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe)); |
| 11897 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11898 | return 0; |
| 11899 | } |
| 11900 | } |
| 11901 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
| 11902 | .update_plane = intel_cursor_plane_update, |
| 11903 | .disable_plane = intel_cursor_plane_disable, |
| 11904 | .destroy = intel_plane_destroy, |
| 11905 | }; |
| 11906 | |
| 11907 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
| 11908 | int pipe) |
| 11909 | { |
| 11910 | struct intel_plane *cursor; |
| 11911 | |
| 11912 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
| 11913 | if (cursor == NULL) |
| 11914 | return NULL; |
| 11915 | |
| 11916 | cursor->can_scale = false; |
| 11917 | cursor->max_downscale = 1; |
| 11918 | cursor->pipe = pipe; |
| 11919 | cursor->plane = pipe; |
| 11920 | |
| 11921 | drm_universal_plane_init(dev, &cursor->base, 0, |
| 11922 | &intel_cursor_plane_funcs, |
| 11923 | intel_cursor_formats, |
| 11924 | ARRAY_SIZE(intel_cursor_formats), |
| 11925 | DRM_PLANE_TYPE_CURSOR); |
| 11926 | return &cursor->base; |
| 11927 | } |
| 11928 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 11929 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11930 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 11931 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11932 | struct intel_crtc *intel_crtc; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11933 | struct drm_plane *primary = NULL; |
| 11934 | struct drm_plane *cursor = NULL; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11935 | int i, ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11936 | |
Daniel Vetter | 955382f | 2013-09-19 14:05:45 +0200 | [diff] [blame] | 11937 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11938 | if (intel_crtc == NULL) |
| 11939 | return; |
| 11940 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11941 | primary = intel_primary_plane_create(dev, pipe); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11942 | if (!primary) |
| 11943 | goto fail; |
| 11944 | |
| 11945 | cursor = intel_cursor_plane_create(dev, pipe); |
| 11946 | if (!cursor) |
| 11947 | goto fail; |
| 11948 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 11949 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11950 | cursor, &intel_crtc_funcs); |
| 11951 | if (ret) |
| 11952 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11953 | |
| 11954 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11955 | for (i = 0; i < 256; i++) { |
| 11956 | intel_crtc->lut_r[i] = i; |
| 11957 | intel_crtc->lut_g[i] = i; |
| 11958 | intel_crtc->lut_b[i] = i; |
| 11959 | } |
| 11960 | |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 11961 | /* |
| 11962 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
Daniel Vetter | 8c0f92e | 2014-06-16 02:08:26 +0200 | [diff] [blame] | 11963 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 11964 | */ |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 11965 | intel_crtc->pipe = pipe; |
| 11966 | intel_crtc->plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 11967 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 11968 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 11969 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 11970 | } |
| 11971 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 11972 | intel_crtc->cursor_base = ~0; |
| 11973 | intel_crtc->cursor_cntl = ~0; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 11974 | intel_crtc->cursor_size = ~0; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 11975 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 11976 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 11977 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 11978 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 11979 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 11980 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11981 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 11982 | |
| 11983 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 11984 | return; |
| 11985 | |
| 11986 | fail: |
| 11987 | if (primary) |
| 11988 | drm_plane_cleanup(primary); |
| 11989 | if (cursor) |
| 11990 | drm_plane_cleanup(cursor); |
| 11991 | kfree(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11992 | } |
| 11993 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 11994 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
| 11995 | { |
| 11996 | struct drm_encoder *encoder = connector->base.encoder; |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 11997 | struct drm_device *dev = connector->base.dev; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 11998 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 11999 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 12000 | |
| 12001 | if (!encoder) |
| 12002 | return INVALID_PIPE; |
| 12003 | |
| 12004 | return to_intel_crtc(encoder->crtc)->pipe; |
| 12005 | } |
| 12006 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12007 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 12008 | struct drm_file *file) |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12009 | { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12010 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 12011 | struct drm_crtc *drmmode_crtc; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 12012 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12013 | |
Daniel Vetter | 1cff8f6 | 2012-04-24 09:55:08 +0200 | [diff] [blame] | 12014 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 12015 | return -ENODEV; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12016 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 12017 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12018 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 12019 | if (!drmmode_crtc) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12020 | DRM_ERROR("no such CRTC id\n"); |
Ville Syrjälä | 3f2c205 | 2013-10-17 13:35:03 +0300 | [diff] [blame] | 12021 | return -ENOENT; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12022 | } |
| 12023 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 12024 | crtc = to_intel_crtc(drmmode_crtc); |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 12025 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12026 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 12027 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 12028 | } |
| 12029 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 12030 | static int intel_encoder_clones(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12031 | { |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 12032 | struct drm_device *dev = encoder->base.dev; |
| 12033 | struct intel_encoder *source_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12034 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12035 | int entry = 0; |
| 12036 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 12037 | for_each_intel_encoder(dev, source_encoder) { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 12038 | if (encoders_cloneable(encoder, source_encoder)) |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 12039 | index_mask |= (1 << entry); |
| 12040 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12041 | entry++; |
| 12042 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 12043 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12044 | return index_mask; |
| 12045 | } |
| 12046 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 12047 | static bool has_edp_a(struct drm_device *dev) |
| 12048 | { |
| 12049 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12050 | |
| 12051 | if (!IS_MOBILE(dev)) |
| 12052 | return false; |
| 12053 | |
| 12054 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 12055 | return false; |
| 12056 | |
Damien Lespiau | e358990 | 2014-02-07 19:12:50 +0000 | [diff] [blame] | 12057 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 12058 | return false; |
| 12059 | |
| 12060 | return true; |
| 12061 | } |
| 12062 | |
Damien Lespiau | ba0fbca | 2014-01-08 14:18:23 +0000 | [diff] [blame] | 12063 | const char *intel_output_name(int output) |
| 12064 | { |
| 12065 | static const char *names[] = { |
| 12066 | [INTEL_OUTPUT_UNUSED] = "Unused", |
| 12067 | [INTEL_OUTPUT_ANALOG] = "Analog", |
| 12068 | [INTEL_OUTPUT_DVO] = "DVO", |
| 12069 | [INTEL_OUTPUT_SDVO] = "SDVO", |
| 12070 | [INTEL_OUTPUT_LVDS] = "LVDS", |
| 12071 | [INTEL_OUTPUT_TVOUT] = "TV", |
| 12072 | [INTEL_OUTPUT_HDMI] = "HDMI", |
| 12073 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", |
| 12074 | [INTEL_OUTPUT_EDP] = "eDP", |
| 12075 | [INTEL_OUTPUT_DSI] = "DSI", |
| 12076 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", |
| 12077 | }; |
| 12078 | |
| 12079 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
| 12080 | return "Invalid"; |
| 12081 | |
| 12082 | return names[output]; |
| 12083 | } |
| 12084 | |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 12085 | static bool intel_crt_present(struct drm_device *dev) |
| 12086 | { |
| 12087 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12088 | |
| 12089 | if (IS_ULT(dev)) |
| 12090 | return false; |
| 12091 | |
| 12092 | if (IS_CHERRYVIEW(dev)) |
| 12093 | return false; |
| 12094 | |
| 12095 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) |
| 12096 | return false; |
| 12097 | |
| 12098 | return true; |
| 12099 | } |
| 12100 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12101 | static void intel_setup_outputs(struct drm_device *dev) |
| 12102 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 12103 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 12104 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 12105 | bool dpd_is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12106 | |
Daniel Vetter | c909335 | 2013-06-06 22:22:47 +0200 | [diff] [blame] | 12107 | intel_lvds_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12108 | |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 12109 | if (intel_crt_present(dev)) |
Paulo Zanoni | 79935fc | 2012-11-20 13:27:40 -0200 | [diff] [blame] | 12110 | intel_crt_init(dev); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 12111 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 12112 | if (HAS_DDI(dev)) { |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 12113 | int found; |
| 12114 | |
| 12115 | /* Haswell uses DDI functions to detect digital outputs */ |
| 12116 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
| 12117 | /* DDI A only supports eDP */ |
| 12118 | if (found) |
| 12119 | intel_ddi_init(dev, PORT_A); |
| 12120 | |
| 12121 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
| 12122 | * register */ |
| 12123 | found = I915_READ(SFUSE_STRAP); |
| 12124 | |
| 12125 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
| 12126 | intel_ddi_init(dev, PORT_B); |
| 12127 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
| 12128 | intel_ddi_init(dev, PORT_C); |
| 12129 | if (found & SFUSE_STRAP_DDID_DETECTED) |
| 12130 | intel_ddi_init(dev, PORT_D); |
| 12131 | } else if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 12132 | int found; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 12133 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 12134 | |
| 12135 | if (has_edp_a(dev)) |
| 12136 | intel_dp_init(dev, DP_A, PORT_A); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 12137 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 12138 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 12139 | /* PCH SDVOB multiplex with HDMIB */ |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 12140 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 12141 | if (!found) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12142 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 12143 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 12144 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 12145 | } |
| 12146 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 12147 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12148 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 12149 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 12150 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12151 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 12152 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 12153 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 12154 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 12155 | |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 12156 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 12157 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
Jesse Barnes | 4a87d65 | 2012-06-15 11:55:16 -0700 | [diff] [blame] | 12158 | } else if (IS_VALLEYVIEW(dev)) { |
Artem Bityutskiy | 585a94b | 2013-10-16 18:10:41 +0300 | [diff] [blame] | 12159 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
| 12160 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
| 12161 | PORT_B); |
| 12162 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
| 12163 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
| 12164 | } |
| 12165 | |
Jesse Barnes | 6f6005a | 2013-08-09 09:34:35 -0700 | [diff] [blame] | 12166 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
| 12167 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
| 12168 | PORT_C); |
| 12169 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 12170 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
Jesse Barnes | 6f6005a | 2013-08-09 09:34:35 -0700 | [diff] [blame] | 12171 | } |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 12172 | |
Ville Syrjälä | 9418c1f | 2014-04-09 13:28:56 +0300 | [diff] [blame] | 12173 | if (IS_CHERRYVIEW(dev)) { |
| 12174 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { |
| 12175 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
| 12176 | PORT_D); |
| 12177 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) |
| 12178 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); |
| 12179 | } |
| 12180 | } |
| 12181 | |
Jani Nikula | 3cfca97 | 2013-08-27 15:12:26 +0300 | [diff] [blame] | 12182 | intel_dsi_init(dev); |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 12183 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 12184 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 12185 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12186 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12187 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12188 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12189 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 12190 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12191 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12192 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 12193 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 12194 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 12195 | intel_dp_init(dev, DP_B, PORT_B); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 12196 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 12197 | |
| 12198 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 12199 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12200 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12201 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12202 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12203 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 12204 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12205 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 12206 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12207 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 12208 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 12209 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12210 | } |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 12211 | if (SUPPORTS_INTEGRATED_DP(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 12212 | intel_dp_init(dev, DP_C, PORT_C); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 12213 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 12214 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 12215 | if (SUPPORTS_INTEGRATED_DP(dev) && |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 12216 | (I915_READ(DP_D) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 12217 | intel_dp_init(dev, DP_D, PORT_D); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 12218 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12219 | intel_dvo_init(dev); |
| 12220 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 12221 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12222 | intel_tv_init(dev); |
| 12223 | |
Rodrigo Vivi | 7c8f8a7 | 2014-06-13 05:10:03 -0700 | [diff] [blame] | 12224 | intel_edp_psr_init(dev); |
| 12225 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 12226 | for_each_intel_encoder(dev, encoder) { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 12227 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 12228 | encoder->base.possible_clones = |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 12229 | intel_encoder_clones(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12230 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 12231 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 12232 | intel_init_pch_refclk(dev); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 12233 | |
| 12234 | drm_helper_move_panel_connectors_to_head(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12235 | } |
| 12236 | |
| 12237 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 12238 | { |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 12239 | struct drm_device *dev = fb->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12240 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12241 | |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 12242 | drm_framebuffer_cleanup(fb); |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 12243 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 12244 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 12245 | drm_gem_object_unreference(&intel_fb->obj->base); |
| 12246 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12247 | kfree(intel_fb); |
| 12248 | } |
| 12249 | |
| 12250 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 12251 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12252 | unsigned int *handle) |
| 12253 | { |
| 12254 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 12255 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12256 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 12257 | return drm_gem_handle_create(file, &obj->base, handle); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12258 | } |
| 12259 | |
| 12260 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 12261 | .destroy = intel_user_framebuffer_destroy, |
| 12262 | .create_handle = intel_user_framebuffer_create_handle, |
| 12263 | }; |
| 12264 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 12265 | static int intel_framebuffer_init(struct drm_device *dev, |
| 12266 | struct intel_framebuffer *intel_fb, |
| 12267 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 12268 | struct drm_i915_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12269 | { |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 12270 | int aligned_height; |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 12271 | int pitch_limit; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12272 | int ret; |
| 12273 | |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 12274 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 12275 | |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12276 | if (obj->tiling_mode == I915_TILING_Y) { |
| 12277 | DRM_DEBUG("hardware does not support tiling Y\n"); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 12278 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12279 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 12280 | |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12281 | if (mode_cmd->pitches[0] & 63) { |
| 12282 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
| 12283 | mode_cmd->pitches[0]); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 12284 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12285 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 12286 | |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 12287 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
| 12288 | pitch_limit = 32*1024; |
| 12289 | } else if (INTEL_INFO(dev)->gen >= 4) { |
| 12290 | if (obj->tiling_mode) |
| 12291 | pitch_limit = 16*1024; |
| 12292 | else |
| 12293 | pitch_limit = 32*1024; |
| 12294 | } else if (INTEL_INFO(dev)->gen >= 3) { |
| 12295 | if (obj->tiling_mode) |
| 12296 | pitch_limit = 8*1024; |
| 12297 | else |
| 12298 | pitch_limit = 16*1024; |
| 12299 | } else |
| 12300 | /* XXX DSPC is limited to 4k tiled */ |
| 12301 | pitch_limit = 8*1024; |
| 12302 | |
| 12303 | if (mode_cmd->pitches[0] > pitch_limit) { |
| 12304 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
| 12305 | obj->tiling_mode ? "tiled" : "linear", |
| 12306 | mode_cmd->pitches[0], pitch_limit); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 12307 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12308 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 12309 | |
| 12310 | if (obj->tiling_mode != I915_TILING_NONE && |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12311 | mode_cmd->pitches[0] != obj->stride) { |
| 12312 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
| 12313 | mode_cmd->pitches[0], obj->stride); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 12314 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12315 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 12316 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12317 | /* Reject formats not supported by any plane early. */ |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 12318 | switch (mode_cmd->pixel_format) { |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12319 | case DRM_FORMAT_C8: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 12320 | case DRM_FORMAT_RGB565: |
| 12321 | case DRM_FORMAT_XRGB8888: |
| 12322 | case DRM_FORMAT_ARGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12323 | break; |
| 12324 | case DRM_FORMAT_XRGB1555: |
| 12325 | case DRM_FORMAT_ARGB1555: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12326 | if (INTEL_INFO(dev)->gen > 3) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 12327 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 12328 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12329 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12330 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12331 | break; |
| 12332 | case DRM_FORMAT_XBGR8888: |
| 12333 | case DRM_FORMAT_ABGR8888: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 12334 | case DRM_FORMAT_XRGB2101010: |
| 12335 | case DRM_FORMAT_ARGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12336 | case DRM_FORMAT_XBGR2101010: |
| 12337 | case DRM_FORMAT_ABGR2101010: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12338 | if (INTEL_INFO(dev)->gen < 4) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 12339 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 12340 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12341 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12342 | } |
Jesse Barnes | b562674 | 2011-06-24 12:19:27 -0700 | [diff] [blame] | 12343 | break; |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 12344 | case DRM_FORMAT_YUYV: |
| 12345 | case DRM_FORMAT_UYVY: |
| 12346 | case DRM_FORMAT_YVYU: |
| 12347 | case DRM_FORMAT_VYUY: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12348 | if (INTEL_INFO(dev)->gen < 5) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 12349 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 12350 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 12351 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 12352 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 12353 | break; |
| 12354 | default: |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 12355 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 12356 | drm_get_format_name(mode_cmd->pixel_format)); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 12357 | return -EINVAL; |
| 12358 | } |
| 12359 | |
Ville Syrjälä | 90f9a33 | 2012-10-31 17:50:19 +0200 | [diff] [blame] | 12360 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 12361 | if (mode_cmd->offsets[0] != 0) |
| 12362 | return -EINVAL; |
| 12363 | |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 12364 | aligned_height = intel_align_height(dev, mode_cmd->height, |
| 12365 | obj->tiling_mode); |
Daniel Vetter | 53155c0 | 2013-10-09 21:55:33 +0200 | [diff] [blame] | 12366 | /* FIXME drm helper for size checks (especially planar formats)? */ |
| 12367 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
| 12368 | return -EINVAL; |
| 12369 | |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 12370 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
| 12371 | intel_fb->obj = obj; |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 12372 | intel_fb->obj->framebuffer_references++; |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 12373 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12374 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 12375 | if (ret) { |
| 12376 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 12377 | return ret; |
| 12378 | } |
| 12379 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12380 | return 0; |
| 12381 | } |
| 12382 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12383 | static struct drm_framebuffer * |
| 12384 | intel_user_framebuffer_create(struct drm_device *dev, |
| 12385 | struct drm_file *filp, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 12386 | struct drm_mode_fb_cmd2 *mode_cmd) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12387 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 12388 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12389 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 12390 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
| 12391 | mode_cmd->handles[0])); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 12392 | if (&obj->base == NULL) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 12393 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12394 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 12395 | return intel_framebuffer_create(dev, mode_cmd, obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12396 | } |
| 12397 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 12398 | #ifndef CONFIG_DRM_I915_FBDEV |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 12399 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 12400 | { |
| 12401 | } |
| 12402 | #endif |
| 12403 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12404 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12405 | .fb_create = intel_user_framebuffer_create, |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 12406 | .output_poll_changed = intel_fbdev_output_poll_changed, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12407 | }; |
| 12408 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12409 | /* Set up chip specific display functions */ |
| 12410 | static void intel_init_display(struct drm_device *dev) |
| 12411 | { |
| 12412 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12413 | |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 12414 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
| 12415 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 12416 | else if (IS_CHERRYVIEW(dev)) |
| 12417 | dev_priv->display.find_dpll = chv_find_best_dpll; |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 12418 | else if (IS_VALLEYVIEW(dev)) |
| 12419 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
| 12420 | else if (IS_PINEVIEW(dev)) |
| 12421 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
| 12422 | else |
| 12423 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
| 12424 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 12425 | if (HAS_DDI(dev)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 12426 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 12427 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 12428 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 12429 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 12430 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
Daniel Vetter | df8ad70 | 2014-06-25 22:02:03 +0300 | [diff] [blame] | 12431 | dev_priv->display.off = ironlake_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 12432 | dev_priv->display.update_primary_plane = |
| 12433 | ironlake_update_primary_plane; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 12434 | } else if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 12435 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 12436 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 12437 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 12438 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
| 12439 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 12440 | dev_priv->display.off = ironlake_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 12441 | dev_priv->display.update_primary_plane = |
| 12442 | ironlake_update_primary_plane; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 12443 | } else if (IS_VALLEYVIEW(dev)) { |
| 12444 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 12445 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 12446 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
| 12447 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 12448 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 12449 | dev_priv->display.off = i9xx_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 12450 | dev_priv->display.update_primary_plane = |
| 12451 | i9xx_update_primary_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 12452 | } else { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 12453 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 12454 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 12455 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 12456 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 12457 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 12458 | dev_priv->display.off = i9xx_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 12459 | dev_priv->display.update_primary_plane = |
| 12460 | i9xx_update_primary_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 12461 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12462 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12463 | /* Returns the core display clock speed */ |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 12464 | if (IS_VALLEYVIEW(dev)) |
| 12465 | dev_priv->display.get_display_clock_speed = |
| 12466 | valleyview_get_display_clock_speed; |
| 12467 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12468 | dev_priv->display.get_display_clock_speed = |
| 12469 | i945_get_display_clock_speed; |
| 12470 | else if (IS_I915G(dev)) |
| 12471 | dev_priv->display.get_display_clock_speed = |
| 12472 | i915_get_display_clock_speed; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 12473 | else if (IS_I945GM(dev) || IS_845G(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12474 | dev_priv->display.get_display_clock_speed = |
| 12475 | i9xx_misc_get_display_clock_speed; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 12476 | else if (IS_PINEVIEW(dev)) |
| 12477 | dev_priv->display.get_display_clock_speed = |
| 12478 | pnv_get_display_clock_speed; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12479 | else if (IS_I915GM(dev)) |
| 12480 | dev_priv->display.get_display_clock_speed = |
| 12481 | i915gm_get_display_clock_speed; |
| 12482 | else if (IS_I865G(dev)) |
| 12483 | dev_priv->display.get_display_clock_speed = |
| 12484 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 12485 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12486 | dev_priv->display.get_display_clock_speed = |
| 12487 | i855_get_display_clock_speed; |
| 12488 | else /* 852, 830 */ |
| 12489 | dev_priv->display.get_display_clock_speed = |
| 12490 | i830_get_display_clock_speed; |
| 12491 | |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 12492 | if (IS_G4X(dev)) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 12493 | dev_priv->display.write_eld = g4x_write_eld; |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 12494 | } else if (IS_GEN5(dev)) { |
| 12495 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
| 12496 | dev_priv->display.write_eld = ironlake_write_eld; |
| 12497 | } else if (IS_GEN6(dev)) { |
| 12498 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
| 12499 | dev_priv->display.write_eld = ironlake_write_eld; |
| 12500 | dev_priv->display.modeset_global_resources = |
| 12501 | snb_modeset_global_resources; |
| 12502 | } else if (IS_IVYBRIDGE(dev)) { |
| 12503 | /* FIXME: detect B0+ stepping and use auto training */ |
| 12504 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
| 12505 | dev_priv->display.write_eld = ironlake_write_eld; |
| 12506 | dev_priv->display.modeset_global_resources = |
| 12507 | ivb_modeset_global_resources; |
| 12508 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
| 12509 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
| 12510 | dev_priv->display.write_eld = haswell_write_eld; |
| 12511 | dev_priv->display.modeset_global_resources = |
| 12512 | haswell_modeset_global_resources; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 12513 | } else if (IS_VALLEYVIEW(dev)) { |
| 12514 | dev_priv->display.modeset_global_resources = |
| 12515 | valleyview_modeset_global_resources; |
Mengdong Lin | 9ca2fe7 | 2013-11-01 00:17:03 -0400 | [diff] [blame] | 12516 | dev_priv->display.write_eld = ironlake_write_eld; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12517 | } |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 12518 | |
| 12519 | /* Default just returns -ENODEV to indicate unsupported */ |
| 12520 | dev_priv->display.queue_flip = intel_default_queue_flip; |
| 12521 | |
| 12522 | switch (INTEL_INFO(dev)->gen) { |
| 12523 | case 2: |
| 12524 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 12525 | break; |
| 12526 | |
| 12527 | case 3: |
| 12528 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 12529 | break; |
| 12530 | |
| 12531 | case 4: |
| 12532 | case 5: |
| 12533 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 12534 | break; |
| 12535 | |
| 12536 | case 6: |
| 12537 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 12538 | break; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 12539 | case 7: |
Ben Widawsky | 4e0bbc3 | 2013-11-02 21:07:07 -0700 | [diff] [blame] | 12540 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 12541 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 12542 | break; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 12543 | } |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 12544 | |
| 12545 | intel_panel_init_backlight_funcs(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12546 | } |
| 12547 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12548 | /* |
| 12549 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 12550 | * resume, or other times. This quirk makes sure that's the case for |
| 12551 | * affected systems. |
| 12552 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 12553 | static void quirk_pipea_force(struct drm_device *dev) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12554 | { |
| 12555 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12556 | |
| 12557 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 12558 | DRM_INFO("applying pipe a force quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12559 | } |
| 12560 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 12561 | /* |
| 12562 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 12563 | */ |
| 12564 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 12565 | { |
| 12566 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12567 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 12568 | DRM_INFO("applying lvds SSC disable quirk\n"); |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 12569 | } |
| 12570 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 12571 | /* |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 12572 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
| 12573 | * brightness value |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 12574 | */ |
| 12575 | static void quirk_invert_brightness(struct drm_device *dev) |
| 12576 | { |
| 12577 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12578 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 12579 | DRM_INFO("applying inverted panel brightness quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12580 | } |
| 12581 | |
Scot Doyle | 9c72cc6 | 2014-07-03 23:27:50 +0000 | [diff] [blame] | 12582 | /* Some VBT's incorrectly indicate no backlight is present */ |
| 12583 | static void quirk_backlight_present(struct drm_device *dev) |
| 12584 | { |
| 12585 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12586 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
| 12587 | DRM_INFO("applying backlight present quirk\n"); |
| 12588 | } |
| 12589 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12590 | struct intel_quirk { |
| 12591 | int device; |
| 12592 | int subsystem_vendor; |
| 12593 | int subsystem_device; |
| 12594 | void (*hook)(struct drm_device *dev); |
| 12595 | }; |
| 12596 | |
Egbert Eich | 5f85f17 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 12597 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
| 12598 | struct intel_dmi_quirk { |
| 12599 | void (*hook)(struct drm_device *dev); |
| 12600 | const struct dmi_system_id (*dmi_id_list)[]; |
| 12601 | }; |
| 12602 | |
| 12603 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
| 12604 | { |
| 12605 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
| 12606 | return 1; |
| 12607 | } |
| 12608 | |
| 12609 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
| 12610 | { |
| 12611 | .dmi_id_list = &(const struct dmi_system_id[]) { |
| 12612 | { |
| 12613 | .callback = intel_dmi_reverse_brightness, |
| 12614 | .ident = "NCR Corporation", |
| 12615 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
| 12616 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
| 12617 | }, |
| 12618 | }, |
| 12619 | { } /* terminating entry */ |
| 12620 | }, |
| 12621 | .hook = quirk_invert_brightness, |
| 12622 | }, |
| 12623 | }; |
| 12624 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 12625 | static struct intel_quirk intel_quirks[] = { |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12626 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 12627 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12628 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12629 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 12630 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 12631 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12632 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 12633 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 12634 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 12635 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 12636 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Michel Alexandre Salim | 070d329 | 2011-07-28 18:52:06 +0200 | [diff] [blame] | 12637 | |
| 12638 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 12639 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 12640 | |
Alexander van Heukelum | be505f6 | 2013-12-28 21:00:39 +0100 | [diff] [blame] | 12641 | /* Acer Aspire 5734Z must invert backlight brightness */ |
| 12642 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
| 12643 | |
| 12644 | /* Acer/eMachines G725 */ |
| 12645 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
| 12646 | |
| 12647 | /* Acer/eMachines e725 */ |
| 12648 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
| 12649 | |
| 12650 | /* Acer/Packard Bell NCL20 */ |
| 12651 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
| 12652 | |
| 12653 | /* Acer Aspire 4736Z */ |
| 12654 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
Jani Nikula | 0f540c3 | 2014-01-13 17:30:34 +0200 | [diff] [blame] | 12655 | |
| 12656 | /* Acer Aspire 5336 */ |
| 12657 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
Scot Doyle | 2e93a1a | 2014-07-03 23:27:51 +0000 | [diff] [blame] | 12658 | |
| 12659 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
| 12660 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
Scot Doyle | d4967d8 | 2014-07-03 23:27:52 +0000 | [diff] [blame] | 12661 | |
| 12662 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
| 12663 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
Scot Doyle | 724cb06 | 2014-07-11 22:16:30 +0000 | [diff] [blame] | 12664 | |
| 12665 | /* HP Chromebook 14 (Celeron 2955U) */ |
| 12666 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12667 | }; |
| 12668 | |
| 12669 | static void intel_init_quirks(struct drm_device *dev) |
| 12670 | { |
| 12671 | struct pci_dev *d = dev->pdev; |
| 12672 | int i; |
| 12673 | |
| 12674 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 12675 | struct intel_quirk *q = &intel_quirks[i]; |
| 12676 | |
| 12677 | if (d->device == q->device && |
| 12678 | (d->subsystem_vendor == q->subsystem_vendor || |
| 12679 | q->subsystem_vendor == PCI_ANY_ID) && |
| 12680 | (d->subsystem_device == q->subsystem_device || |
| 12681 | q->subsystem_device == PCI_ANY_ID)) |
| 12682 | q->hook(dev); |
| 12683 | } |
Egbert Eich | 5f85f17 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 12684 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
| 12685 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
| 12686 | intel_dmi_quirks[i].hook(dev); |
| 12687 | } |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12688 | } |
| 12689 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 12690 | /* Disable the VGA plane that we never use */ |
| 12691 | static void i915_disable_vga(struct drm_device *dev) |
| 12692 | { |
| 12693 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12694 | u8 sr1; |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 12695 | u32 vga_reg = i915_vgacntrl_reg(dev); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 12696 | |
Ville Syrjälä | 2b37c61 | 2014-01-22 21:32:38 +0200 | [diff] [blame] | 12697 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 12698 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
Jesse Barnes | 3fdcf43 | 2012-04-06 11:46:27 -0700 | [diff] [blame] | 12699 | outb(SR01, VGA_SR_INDEX); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 12700 | sr1 = inb(VGA_SR_DATA); |
| 12701 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 12702 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 12703 | udelay(300); |
| 12704 | |
| 12705 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 12706 | POSTING_READ(vga_reg); |
| 12707 | } |
| 12708 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 12709 | void intel_modeset_init_hw(struct drm_device *dev) |
| 12710 | { |
Eugeni Dodonov | a8f78b5 | 2012-06-28 15:55:35 -0300 | [diff] [blame] | 12711 | intel_prepare_ddi(dev); |
| 12712 | |
Ville Syrjälä | f8bf63f | 2014-06-13 13:37:54 +0300 | [diff] [blame] | 12713 | if (IS_VALLEYVIEW(dev)) |
| 12714 | vlv_update_cdclk(dev); |
| 12715 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 12716 | intel_init_clock_gating(dev); |
| 12717 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 12718 | intel_enable_gt_powersave(dev); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 12719 | } |
| 12720 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 12721 | void intel_modeset_suspend_hw(struct drm_device *dev) |
| 12722 | { |
| 12723 | intel_suspend_hw(dev); |
| 12724 | } |
| 12725 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12726 | void intel_modeset_init(struct drm_device *dev) |
| 12727 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 12728 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 12729 | int sprite, ret; |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 12730 | enum pipe pipe; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12731 | struct intel_crtc *crtc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12732 | |
| 12733 | drm_mode_config_init(dev); |
| 12734 | |
| 12735 | dev->mode_config.min_width = 0; |
| 12736 | dev->mode_config.min_height = 0; |
| 12737 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 12738 | dev->mode_config.preferred_depth = 24; |
| 12739 | dev->mode_config.prefer_shadow = 1; |
| 12740 | |
Laurent Pinchart | e6ecefa | 2012-05-17 13:27:23 +0200 | [diff] [blame] | 12741 | dev->mode_config.funcs = &intel_mode_funcs; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12742 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 12743 | intel_init_quirks(dev); |
| 12744 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 12745 | intel_init_pm(dev); |
| 12746 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 12747 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 12748 | return; |
| 12749 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 12750 | intel_init_display(dev); |
| 12751 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 12752 | if (IS_GEN2(dev)) { |
| 12753 | dev->mode_config.max_width = 2048; |
| 12754 | dev->mode_config.max_height = 2048; |
| 12755 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 12756 | dev->mode_config.max_width = 4096; |
| 12757 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12758 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 12759 | dev->mode_config.max_width = 8192; |
| 12760 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12761 | } |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 12762 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 12763 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 12764 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; |
| 12765 | dev->mode_config.cursor_height = 1023; |
| 12766 | } else if (IS_GEN2(dev)) { |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 12767 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
| 12768 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; |
| 12769 | } else { |
| 12770 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; |
| 12771 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; |
| 12772 | } |
| 12773 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 12774 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12775 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 12776 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 12777 | INTEL_INFO(dev)->num_pipes, |
| 12778 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12779 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 12780 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 12781 | intel_crtc_init(dev, pipe); |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 12782 | for_each_sprite(pipe, sprite) { |
| 12783 | ret = intel_plane_init(dev, pipe, sprite); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 12784 | if (ret) |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 12785 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 12786 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 12787 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12788 | } |
| 12789 | |
Jesse Barnes | f42bb70 | 2013-12-16 16:34:23 -0800 | [diff] [blame] | 12790 | intel_init_dpio(dev); |
| 12791 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 12792 | intel_shared_dpll_init(dev); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 12793 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 12794 | /* Just disable it once at startup */ |
| 12795 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 12796 | intel_setup_outputs(dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 12797 | |
| 12798 | /* Just in case the BIOS is doing something questionable. */ |
| 12799 | intel_disable_fbc(dev); |
Jesse Barnes | fa9fa08 | 2014-02-11 15:28:56 -0800 | [diff] [blame] | 12800 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 12801 | drm_modeset_lock_all(dev); |
Jesse Barnes | fa9fa08 | 2014-02-11 15:28:56 -0800 | [diff] [blame] | 12802 | intel_modeset_setup_hw_state(dev, false); |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 12803 | drm_modeset_unlock_all(dev); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12804 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 12805 | for_each_intel_crtc(dev, crtc) { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12806 | if (!crtc->active) |
| 12807 | continue; |
| 12808 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12809 | /* |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12810 | * Note that reserving the BIOS fb up front prevents us |
| 12811 | * from stuffing other stolen allocations like the ring |
| 12812 | * on top. This prevents some ugliness at boot time, and |
| 12813 | * can even allow for smooth boot transitions if the BIOS |
| 12814 | * fb is large enough for the active pipe configuration. |
| 12815 | */ |
| 12816 | if (dev_priv->display.get_plane_config) { |
| 12817 | dev_priv->display.get_plane_config(crtc, |
| 12818 | &crtc->plane_config); |
| 12819 | /* |
| 12820 | * If the fb is shared between multiple heads, we'll |
| 12821 | * just get the first one. |
| 12822 | */ |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 12823 | intel_find_plane_obj(crtc, &crtc->plane_config); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12824 | } |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 12825 | } |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 12826 | } |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 12827 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 12828 | static void intel_enable_pipe_a(struct drm_device *dev) |
| 12829 | { |
| 12830 | struct intel_connector *connector; |
| 12831 | struct drm_connector *crt = NULL; |
| 12832 | struct intel_load_detect_pipe load_detect_temp; |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 12833 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 12834 | |
| 12835 | /* We can't just switch on the pipe A, we need to set things up with a |
| 12836 | * proper mode and output configuration. As a gross hack, enable pipe A |
| 12837 | * by enabling the load detect pipe once. */ |
| 12838 | list_for_each_entry(connector, |
| 12839 | &dev->mode_config.connector_list, |
| 12840 | base.head) { |
| 12841 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
| 12842 | crt = &connector->base; |
| 12843 | break; |
| 12844 | } |
| 12845 | } |
| 12846 | |
| 12847 | if (!crt) |
| 12848 | return; |
| 12849 | |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 12850 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
| 12851 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 12852 | } |
| 12853 | |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 12854 | static bool |
| 12855 | intel_check_plane_mapping(struct intel_crtc *crtc) |
| 12856 | { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 12857 | struct drm_device *dev = crtc->base.dev; |
| 12858 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 12859 | u32 reg, val; |
| 12860 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 12861 | if (INTEL_INFO(dev)->num_pipes == 1) |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 12862 | return true; |
| 12863 | |
| 12864 | reg = DSPCNTR(!crtc->plane); |
| 12865 | val = I915_READ(reg); |
| 12866 | |
| 12867 | if ((val & DISPLAY_PLANE_ENABLE) && |
| 12868 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
| 12869 | return false; |
| 12870 | |
| 12871 | return true; |
| 12872 | } |
| 12873 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12874 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
| 12875 | { |
| 12876 | struct drm_device *dev = crtc->base.dev; |
| 12877 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 12878 | u32 reg; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12879 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12880 | /* Clear any frame start delays used for debugging left by the BIOS */ |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 12881 | reg = PIPECONF(crtc->config.cpu_transcoder); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12882 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 12883 | |
Ville Syrjälä | d3eaf88 | 2014-05-20 17:20:05 +0300 | [diff] [blame] | 12884 | /* restore vblank interrupts to correct state */ |
| 12885 | if (crtc->active) |
| 12886 | drm_vblank_on(dev, crtc->pipe); |
| 12887 | else |
| 12888 | drm_vblank_off(dev, crtc->pipe); |
| 12889 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12890 | /* We need to sanitize the plane -> pipe mapping first because this will |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 12891 | * disable the crtc (and hence change the state) if it is wrong. Note |
| 12892 | * that gen4+ has a fixed plane -> pipe mapping. */ |
| 12893 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12894 | struct intel_connector *connector; |
| 12895 | bool plane; |
| 12896 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12897 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
| 12898 | crtc->base.base.id); |
| 12899 | |
| 12900 | /* Pipe has the wrong plane attached and the plane is active. |
| 12901 | * Temporarily change the plane mapping and disable everything |
| 12902 | * ... */ |
| 12903 | plane = crtc->plane; |
| 12904 | crtc->plane = !plane; |
Daniel Vetter | 9c8958b | 2014-07-14 19:35:31 +0200 | [diff] [blame] | 12905 | crtc->primary_enabled = true; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12906 | dev_priv->display.crtc_disable(&crtc->base); |
| 12907 | crtc->plane = plane; |
| 12908 | |
| 12909 | /* ... and break all links. */ |
| 12910 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 12911 | base.head) { |
| 12912 | if (connector->encoder->base.crtc != &crtc->base) |
| 12913 | continue; |
| 12914 | |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 12915 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 12916 | connector->base.encoder = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12917 | } |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 12918 | /* multiple connectors may have the same encoder: |
| 12919 | * handle them and break crtc link separately */ |
| 12920 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 12921 | base.head) |
| 12922 | if (connector->encoder->base.crtc == &crtc->base) { |
| 12923 | connector->encoder->base.crtc = NULL; |
| 12924 | connector->encoder->connectors_active = false; |
| 12925 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12926 | |
| 12927 | WARN_ON(crtc->active); |
| 12928 | crtc->base.enabled = false; |
| 12929 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12930 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 12931 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 12932 | crtc->pipe == PIPE_A && !crtc->active) { |
| 12933 | /* BIOS forgot to enable pipe A, this mostly happens after |
| 12934 | * resume. Force-enable the pipe to fix this, the update_dpms |
| 12935 | * call below we restore the pipe to the right state, but leave |
| 12936 | * the required bits on. */ |
| 12937 | intel_enable_pipe_a(dev); |
| 12938 | } |
| 12939 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12940 | /* Adjust the state of the output pipe according to whether we |
| 12941 | * have active connectors/encoders. */ |
| 12942 | intel_crtc_update_dpms(&crtc->base); |
| 12943 | |
| 12944 | if (crtc->active != crtc->base.enabled) { |
| 12945 | struct intel_encoder *encoder; |
| 12946 | |
| 12947 | /* This can happen either due to bugs in the get_hw_state |
| 12948 | * functions or because the pipe is force-enabled due to the |
| 12949 | * pipe A quirk. */ |
| 12950 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
| 12951 | crtc->base.base.id, |
| 12952 | crtc->base.enabled ? "enabled" : "disabled", |
| 12953 | crtc->active ? "enabled" : "disabled"); |
| 12954 | |
| 12955 | crtc->base.enabled = crtc->active; |
| 12956 | |
| 12957 | /* Because we only establish the connector -> encoder -> |
| 12958 | * crtc links if something is active, this means the |
| 12959 | * crtc is now deactivated. Break the links. connector |
| 12960 | * -> encoder links are only establish when things are |
| 12961 | * actually up, hence no need to break them. */ |
| 12962 | WARN_ON(crtc->active); |
| 12963 | |
| 12964 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
| 12965 | WARN_ON(encoder->connectors_active); |
| 12966 | encoder->base.crtc = NULL; |
| 12967 | } |
| 12968 | } |
Daniel Vetter | c5ab3bc | 2014-05-14 15:40:34 +0200 | [diff] [blame] | 12969 | |
| 12970 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 12971 | /* |
| 12972 | * We start out with underrun reporting disabled to avoid races. |
| 12973 | * For correct bookkeeping mark this on active crtcs. |
| 12974 | * |
Daniel Vetter | c5ab3bc | 2014-05-14 15:40:34 +0200 | [diff] [blame] | 12975 | * Also on gmch platforms we dont have any hardware bits to |
| 12976 | * disable the underrun reporting. Which means we need to start |
| 12977 | * out with underrun reporting disabled also on inactive pipes, |
| 12978 | * since otherwise we'll complain about the garbage we read when |
| 12979 | * e.g. coming up after runtime pm. |
| 12980 | * |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 12981 | * No protection against concurrent access is required - at |
| 12982 | * worst a fifo underrun happens which also sets this to false. |
| 12983 | */ |
| 12984 | crtc->cpu_fifo_underrun_disabled = true; |
| 12985 | crtc->pch_fifo_underrun_disabled = true; |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 12986 | |
| 12987 | update_scanline_offset(crtc); |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 12988 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 12989 | } |
| 12990 | |
| 12991 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
| 12992 | { |
| 12993 | struct intel_connector *connector; |
| 12994 | struct drm_device *dev = encoder->base.dev; |
| 12995 | |
| 12996 | /* We need to check both for a crtc link (meaning that the |
| 12997 | * encoder is active and trying to read from a pipe) and the |
| 12998 | * pipe itself being active. */ |
| 12999 | bool has_active_crtc = encoder->base.crtc && |
| 13000 | to_intel_crtc(encoder->base.crtc)->active; |
| 13001 | |
| 13002 | if (encoder->connectors_active && !has_active_crtc) { |
| 13003 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
| 13004 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 13005 | encoder->base.name); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13006 | |
| 13007 | /* Connector is active, but has no active pipe. This is |
| 13008 | * fallout from our resume register restoring. Disable |
| 13009 | * the encoder manually again. */ |
| 13010 | if (encoder->base.crtc) { |
| 13011 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
| 13012 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 13013 | encoder->base.name); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13014 | encoder->disable(encoder); |
Ville Syrjälä | a62d149 | 2014-06-28 02:04:01 +0300 | [diff] [blame] | 13015 | if (encoder->post_disable) |
| 13016 | encoder->post_disable(encoder); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13017 | } |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 13018 | encoder->base.crtc = NULL; |
| 13019 | encoder->connectors_active = false; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13020 | |
| 13021 | /* Inconsistent output/port/pipe state happens presumably due to |
| 13022 | * a bug in one of the get_hw_state functions. Or someplace else |
| 13023 | * in our code, like the register restore mess on resume. Clamp |
| 13024 | * things to off as a safer default. */ |
| 13025 | list_for_each_entry(connector, |
| 13026 | &dev->mode_config.connector_list, |
| 13027 | base.head) { |
| 13028 | if (connector->encoder != encoder) |
| 13029 | continue; |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 13030 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 13031 | connector->base.encoder = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13032 | } |
| 13033 | } |
| 13034 | /* Enabled encoders without active connectors will be fixed in |
| 13035 | * the crtc fixup. */ |
| 13036 | } |
| 13037 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 13038 | void i915_redisable_vga_power_on(struct drm_device *dev) |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 13039 | { |
| 13040 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 13041 | u32 vga_reg = i915_vgacntrl_reg(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 13042 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 13043 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
| 13044 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
| 13045 | i915_disable_vga(dev); |
| 13046 | } |
| 13047 | } |
| 13048 | |
| 13049 | void i915_redisable_vga(struct drm_device *dev) |
| 13050 | { |
| 13051 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13052 | |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 13053 | /* This function can be called both from intel_modeset_setup_hw_state or |
| 13054 | * at a very early point in our resume sequence, where the power well |
| 13055 | * structures are not yet restored. Since this function is at a very |
| 13056 | * paranoid "someone might have enabled VGA while we were not looking" |
| 13057 | * level, just check if the power well is enabled instead of trying to |
| 13058 | * follow the "don't touch the power well if we don't need it" policy |
| 13059 | * the rest of the driver uses. */ |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 13060 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 13061 | return; |
| 13062 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 13063 | i915_redisable_vga_power_on(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 13064 | } |
| 13065 | |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 13066 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
| 13067 | { |
| 13068 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 13069 | |
| 13070 | if (!crtc->active) |
| 13071 | return false; |
| 13072 | |
| 13073 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; |
| 13074 | } |
| 13075 | |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 13076 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13077 | { |
| 13078 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13079 | enum pipe pipe; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13080 | struct intel_crtc *crtc; |
| 13081 | struct intel_encoder *encoder; |
| 13082 | struct intel_connector *connector; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13083 | int i; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13084 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 13085 | for_each_intel_crtc(dev, crtc) { |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 13086 | memset(&crtc->config, 0, sizeof(crtc->config)); |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 13087 | |
Daniel Vetter | 9953599 | 2014-04-13 12:00:33 +0200 | [diff] [blame] | 13088 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
| 13089 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 13090 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
| 13091 | &crtc->config); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13092 | |
| 13093 | crtc->base.enabled = crtc->active; |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 13094 | crtc->primary_enabled = primary_get_hw_state(crtc); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13095 | |
| 13096 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
| 13097 | crtc->base.base.id, |
| 13098 | crtc->active ? "enabled" : "disabled"); |
| 13099 | } |
| 13100 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13101 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 13102 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 13103 | |
| 13104 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
| 13105 | pll->active = 0; |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 13106 | for_each_intel_crtc(dev, crtc) { |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13107 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
| 13108 | pll->active++; |
| 13109 | } |
| 13110 | pll->refcount = pll->active; |
| 13111 | |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 13112 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
| 13113 | pll->name, pll->refcount, pll->on); |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 13114 | |
| 13115 | if (pll->refcount) |
| 13116 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13117 | } |
| 13118 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 13119 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13120 | pipe = 0; |
| 13121 | |
| 13122 | if (encoder->get_hw_state(encoder, &pipe)) { |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 13123 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 13124 | encoder->base.crtc = &crtc->base; |
Daniel Vetter | 1d37b68 | 2013-11-18 09:00:59 +0100 | [diff] [blame] | 13125 | encoder->get_config(encoder, &crtc->config); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13126 | } else { |
| 13127 | encoder->base.crtc = NULL; |
| 13128 | } |
| 13129 | |
| 13130 | encoder->connectors_active = false; |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 13131 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13132 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 13133 | encoder->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13134 | encoder->base.crtc ? "enabled" : "disabled", |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 13135 | pipe_name(pipe)); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13136 | } |
| 13137 | |
| 13138 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 13139 | base.head) { |
| 13140 | if (connector->get_hw_state(connector)) { |
| 13141 | connector->base.dpms = DRM_MODE_DPMS_ON; |
| 13142 | connector->encoder->connectors_active = true; |
| 13143 | connector->base.encoder = &connector->encoder->base; |
| 13144 | } else { |
| 13145 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 13146 | connector->base.encoder = NULL; |
| 13147 | } |
| 13148 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
| 13149 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 13150 | connector->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13151 | connector->base.encoder ? "enabled" : "disabled"); |
| 13152 | } |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 13153 | } |
| 13154 | |
| 13155 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
| 13156 | * and i915 state tracking structures. */ |
| 13157 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 13158 | bool force_restore) |
| 13159 | { |
| 13160 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13161 | enum pipe pipe; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 13162 | struct intel_crtc *crtc; |
| 13163 | struct intel_encoder *encoder; |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 13164 | int i; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 13165 | |
| 13166 | intel_modeset_readout_hw_state(dev); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13167 | |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 13168 | /* |
| 13169 | * Now that we have the config, copy it to each CRTC struct |
| 13170 | * Note that this could go away if we move to using crtc_config |
| 13171 | * checking everywhere. |
| 13172 | */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 13173 | for_each_intel_crtc(dev, crtc) { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 13174 | if (crtc->active && i915.fastboot) { |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 13175 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 13176 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
| 13177 | crtc->base.base.id); |
| 13178 | drm_mode_debug_printmodeline(&crtc->base.mode); |
| 13179 | } |
| 13180 | } |
| 13181 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13182 | /* HW state is read out, now we need to sanitize this mess. */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 13183 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13184 | intel_sanitize_encoder(encoder); |
| 13185 | } |
| 13186 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 13187 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13188 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 13189 | intel_sanitize_crtc(crtc); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 13190 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 13191 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 13192 | |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 13193 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 13194 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 13195 | |
| 13196 | if (!pll->on || pll->active) |
| 13197 | continue; |
| 13198 | |
| 13199 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
| 13200 | |
| 13201 | pll->disable(dev_priv, pll); |
| 13202 | pll->on = false; |
| 13203 | } |
| 13204 | |
Ville Syrjälä | 96f90c5 | 2013-12-05 15:51:38 +0200 | [diff] [blame] | 13205 | if (HAS_PCH_SPLIT(dev)) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 13206 | ilk_wm_get_hw_state(dev); |
| 13207 | |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 13208 | if (force_restore) { |
Ville Syrjälä | 7d0bc1e | 2013-09-16 17:38:33 +0300 | [diff] [blame] | 13209 | i915_redisable_vga(dev); |
| 13210 | |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 13211 | /* |
| 13212 | * We need to use raw interfaces for restoring state to avoid |
| 13213 | * checking (bogus) intermediate states. |
| 13214 | */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 13215 | for_each_pipe(dev_priv, pipe) { |
Jesse Barnes | b5644d0 | 2013-03-26 13:25:27 -0700 | [diff] [blame] | 13216 | struct drm_crtc *crtc = |
| 13217 | dev_priv->pipe_to_crtc_mapping[pipe]; |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 13218 | |
| 13219 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 13220 | crtc->primary->fb); |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 13221 | } |
| 13222 | } else { |
| 13223 | intel_modeset_update_staged_output_state(dev); |
| 13224 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13225 | |
| 13226 | intel_modeset_check_state(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 13227 | } |
| 13228 | |
| 13229 | void intel_modeset_gem_init(struct drm_device *dev) |
| 13230 | { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 13231 | struct drm_crtc *c; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 13232 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 13233 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 13234 | mutex_lock(&dev->struct_mutex); |
| 13235 | intel_init_gt_powersave(dev); |
| 13236 | mutex_unlock(&dev->struct_mutex); |
| 13237 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 13238 | intel_modeset_init_hw(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 13239 | |
| 13240 | intel_setup_overlay(dev); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 13241 | |
| 13242 | /* |
| 13243 | * Make sure any fbs we allocated at startup are properly |
| 13244 | * pinned & fenced. When we do the allocation it's too early |
| 13245 | * for this. |
| 13246 | */ |
| 13247 | mutex_lock(&dev->struct_mutex); |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 13248 | for_each_crtc(dev, c) { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 13249 | obj = intel_fb_obj(c->primary->fb); |
| 13250 | if (obj == NULL) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 13251 | continue; |
| 13252 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 13253 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 13254 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
| 13255 | to_intel_crtc(c)->pipe); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 13256 | drm_framebuffer_unreference(c->primary->fb); |
| 13257 | c->primary->fb = NULL; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 13258 | } |
| 13259 | } |
| 13260 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13261 | } |
| 13262 | |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 13263 | void intel_connector_unregister(struct intel_connector *intel_connector) |
| 13264 | { |
| 13265 | struct drm_connector *connector = &intel_connector->base; |
| 13266 | |
| 13267 | intel_panel_destroy_backlight(connector); |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 13268 | drm_connector_unregister(connector); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 13269 | } |
| 13270 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13271 | void intel_modeset_cleanup(struct drm_device *dev) |
| 13272 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 13273 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 13274 | struct drm_connector *connector; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 13275 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 13276 | /* |
| 13277 | * Interrupts and polling as the first thing to avoid creating havoc. |
| 13278 | * Too much stuff here (turning of rps, connectors, ...) would |
| 13279 | * experience fancy races otherwise. |
| 13280 | */ |
| 13281 | drm_irq_uninstall(dev); |
Imre Deak | 1d0d343 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 13282 | intel_hpd_cancel_work(dev_priv); |
Jesse Barnes | eb21b92 | 2014-06-20 11:57:33 -0700 | [diff] [blame] | 13283 | dev_priv->pm._irqs_disabled = true; |
| 13284 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 13285 | /* |
| 13286 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
| 13287 | * poll handlers. Hence disable polling after hpd handling is shut down. |
| 13288 | */ |
Keith Packard | f87ea76 | 2010-10-03 19:36:26 -0700 | [diff] [blame] | 13289 | drm_kms_helper_poll_fini(dev); |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 13290 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 13291 | mutex_lock(&dev->struct_mutex); |
| 13292 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 13293 | intel_unregister_dsm_handler(); |
| 13294 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 13295 | intel_disable_fbc(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 13296 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 13297 | intel_disable_gt_powersave(dev); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 13298 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 13299 | ironlake_teardown_rc6(dev); |
| 13300 | |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 13301 | mutex_unlock(&dev->struct_mutex); |
| 13302 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 13303 | /* flush any delayed tasks or pending work */ |
| 13304 | flush_scheduled_work(); |
| 13305 | |
Jani Nikula | db31af1d | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 13306 | /* destroy the backlight and sysfs files before encoders/connectors */ |
| 13307 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 13308 | struct intel_connector *intel_connector; |
| 13309 | |
| 13310 | intel_connector = to_intel_connector(connector); |
| 13311 | intel_connector->unregister(intel_connector); |
Jani Nikula | db31af1d | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 13312 | } |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 13313 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13314 | drm_mode_config_cleanup(dev); |
Daniel Vetter | 4d7bb01 | 2012-12-18 15:24:37 +0100 | [diff] [blame] | 13315 | |
| 13316 | intel_cleanup_overlay(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 13317 | |
| 13318 | mutex_lock(&dev->struct_mutex); |
| 13319 | intel_cleanup_gt_powersave(dev); |
| 13320 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13321 | } |
| 13322 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 13323 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 13324 | * Return which encoder is currently attached for connector. |
| 13325 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 13326 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13327 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 13328 | return &intel_attached_encoder(connector)->base; |
| 13329 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13330 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 13331 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 13332 | struct intel_encoder *encoder) |
| 13333 | { |
| 13334 | connector->encoder = encoder; |
| 13335 | drm_mode_connector_attach_encoder(&connector->base, |
| 13336 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 13337 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 13338 | |
| 13339 | /* |
| 13340 | * set vga decode state - true == enable VGA decode |
| 13341 | */ |
| 13342 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 13343 | { |
| 13344 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a885b3c | 2013-12-17 14:34:50 +0000 | [diff] [blame] | 13345 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 13346 | u16 gmch_ctrl; |
| 13347 | |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 13348 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
| 13349 | DRM_ERROR("failed to read control word\n"); |
| 13350 | return -EIO; |
| 13351 | } |
| 13352 | |
Chris Wilson | c0cc8a5 | 2014-02-07 18:37:03 -0200 | [diff] [blame] | 13353 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
| 13354 | return 0; |
| 13355 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 13356 | if (state) |
| 13357 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 13358 | else |
| 13359 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 13360 | |
| 13361 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
| 13362 | DRM_ERROR("failed to write control word\n"); |
| 13363 | return -EIO; |
| 13364 | } |
| 13365 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 13366 | return 0; |
| 13367 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13368 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13369 | struct intel_display_error_state { |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 13370 | |
| 13371 | u32 power_well_driver; |
| 13372 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13373 | int num_transcoders; |
| 13374 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13375 | struct intel_cursor_error_state { |
| 13376 | u32 control; |
| 13377 | u32 position; |
| 13378 | u32 base; |
| 13379 | u32 size; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 13380 | } cursor[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13381 | |
| 13382 | struct intel_pipe_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13383 | bool power_domain_on; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13384 | u32 source; |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 13385 | u32 stat; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 13386 | } pipe[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13387 | |
| 13388 | struct intel_plane_error_state { |
| 13389 | u32 control; |
| 13390 | u32 stride; |
| 13391 | u32 size; |
| 13392 | u32 pos; |
| 13393 | u32 addr; |
| 13394 | u32 surface; |
| 13395 | u32 tile_offset; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 13396 | } plane[I915_MAX_PIPES]; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13397 | |
| 13398 | struct intel_transcoder_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13399 | bool power_domain_on; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13400 | enum transcoder cpu_transcoder; |
| 13401 | |
| 13402 | u32 conf; |
| 13403 | |
| 13404 | u32 htotal; |
| 13405 | u32 hblank; |
| 13406 | u32 hsync; |
| 13407 | u32 vtotal; |
| 13408 | u32 vblank; |
| 13409 | u32 vsync; |
| 13410 | } transcoder[4]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13411 | }; |
| 13412 | |
| 13413 | struct intel_display_error_state * |
| 13414 | intel_display_capture_error_state(struct drm_device *dev) |
| 13415 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 13416 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13417 | struct intel_display_error_state *error; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13418 | int transcoders[] = { |
| 13419 | TRANSCODER_A, |
| 13420 | TRANSCODER_B, |
| 13421 | TRANSCODER_C, |
| 13422 | TRANSCODER_EDP, |
| 13423 | }; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13424 | int i; |
| 13425 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13426 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 13427 | return NULL; |
| 13428 | |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 13429 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13430 | if (error == NULL) |
| 13431 | return NULL; |
| 13432 | |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 13433 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 13434 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
| 13435 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 13436 | for_each_pipe(dev_priv, i) { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13437 | error->pipe[i].power_domain_on = |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 13438 | intel_display_power_enabled_unlocked(dev_priv, |
| 13439 | POWER_DOMAIN_PIPE(i)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13440 | if (!error->pipe[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 13441 | continue; |
| 13442 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 13443 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 13444 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 13445 | error->cursor[i].base = I915_READ(CURBASE(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13446 | |
| 13447 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 13448 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 13449 | if (INTEL_INFO(dev)->gen <= 3) { |
Paulo Zanoni | 51889b3 | 2013-03-06 20:03:13 -0300 | [diff] [blame] | 13450 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 13451 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
| 13452 | } |
Paulo Zanoni | ca29136 | 2013-03-06 20:03:14 -0300 | [diff] [blame] | 13453 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
| 13454 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13455 | if (INTEL_INFO(dev)->gen >= 4) { |
| 13456 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 13457 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 13458 | } |
| 13459 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13460 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 13461 | |
Sonika Jindal | 3abfce7 | 2014-07-21 15:23:43 +0530 | [diff] [blame] | 13462 | if (HAS_GMCH_DISPLAY(dev)) |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 13463 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13464 | } |
| 13465 | |
| 13466 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
| 13467 | if (HAS_DDI(dev_priv->dev)) |
| 13468 | error->num_transcoders++; /* Account for eDP. */ |
| 13469 | |
| 13470 | for (i = 0; i < error->num_transcoders; i++) { |
| 13471 | enum transcoder cpu_transcoder = transcoders[i]; |
| 13472 | |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13473 | error->transcoder[i].power_domain_on = |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 13474 | intel_display_power_enabled_unlocked(dev_priv, |
Paulo Zanoni | 38cc1da | 2013-12-20 15:09:41 -0200 | [diff] [blame] | 13475 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13476 | if (!error->transcoder[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 13477 | continue; |
| 13478 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13479 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 13480 | |
| 13481 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
| 13482 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
| 13483 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
| 13484 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 13485 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
| 13486 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
| 13487 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13488 | } |
| 13489 | |
| 13490 | return error; |
| 13491 | } |
| 13492 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13493 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 13494 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13495 | void |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13496 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13497 | struct drm_device *dev, |
| 13498 | struct intel_display_error_state *error) |
| 13499 | { |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 13500 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13501 | int i; |
| 13502 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13503 | if (!error) |
| 13504 | return; |
| 13505 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13506 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 13507 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13508 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 13509 | error->power_well_driver); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 13510 | for_each_pipe(dev_priv, i) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13511 | err_printf(m, "Pipe [%d]:\n", i); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13512 | err_printf(m, " Power: %s\n", |
| 13513 | error->pipe[i].power_domain_on ? "on" : "off"); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13514 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 13515 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13516 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13517 | err_printf(m, "Plane [%d]:\n", i); |
| 13518 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 13519 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 13520 | if (INTEL_INFO(dev)->gen <= 3) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13521 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 13522 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 13523 | } |
Paulo Zanoni | 4b71a57 | 2013-03-22 14:19:21 -0300 | [diff] [blame] | 13524 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13525 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13526 | if (INTEL_INFO(dev)->gen >= 4) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13527 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 13528 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13529 | } |
| 13530 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 13531 | err_printf(m, "Cursor [%d]:\n", i); |
| 13532 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 13533 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 13534 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13535 | } |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13536 | |
| 13537 | for (i = 0; i < error->num_transcoders; i++) { |
Chris Wilson | 1cf84bb | 2013-10-21 09:10:33 +0100 | [diff] [blame] | 13538 | err_printf(m, "CPU transcoder: %c\n", |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13539 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 13540 | err_printf(m, " Power: %s\n", |
| 13541 | error->transcoder[i].power_domain_on ? "on" : "off"); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 13542 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
| 13543 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
| 13544 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
| 13545 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
| 13546 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
| 13547 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
| 13548 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
| 13549 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 13550 | } |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 13551 | |
| 13552 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) |
| 13553 | { |
| 13554 | struct intel_crtc *crtc; |
| 13555 | |
| 13556 | for_each_intel_crtc(dev, crtc) { |
| 13557 | struct intel_unpin_work *work; |
| 13558 | unsigned long irqflags; |
| 13559 | |
| 13560 | spin_lock_irqsave(&dev->event_lock, irqflags); |
| 13561 | |
| 13562 | work = crtc->unpin_work; |
| 13563 | |
| 13564 | if (work && work->event && |
| 13565 | work->event->base.file_priv == file) { |
| 13566 | kfree(work->event); |
| 13567 | work->event = NULL; |
| 13568 | } |
| 13569 | |
| 13570 | spin_unlock_irqrestore(&dev->event_lock, irqflags); |
| 13571 | } |
| 13572 | } |