blob: 22e6644f755e4380aed8375f0cf4bc6768d08c12 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Xi Ruoyao319c1d42015-03-12 20:16:32 +080040#include <drm/drm_atomic.h>
Matt Roperc196e1d2015-01-21 16:35:48 -080041#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010042#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070044#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080046#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080047
Matt Roper465c1202014-05-29 08:06:54 -070048/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
Matt Roper3d7d6512014-06-10 08:28:13 -070073/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
Chris Wilson6b383a72010-09-13 13:54:26 +010078static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080079
Jesse Barnesf1f644d2013-06-27 00:39:25 +030080static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020081 struct intel_crtc_state *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030082static void ironlake_pch_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020083 struct intel_crtc_state *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030084
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030085static int intel_set_mode(struct drm_crtc *crtc,
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020086 struct drm_atomic_state *state);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080087static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020091static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020093static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070094 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020096static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020097static void haswell_set_pipeconf(struct drm_crtc *crtc);
98static void intel_set_pipe_csc(struct drm_crtc *crtc);
Ville Syrjäläd288f652014-10-28 13:20:22 +020099static void vlv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200100 const struct intel_crtc_state *pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +0200101static void chv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200102 const struct intel_crtc_state *pipe_config);
Matt Roperea2c67b2014-12-23 10:41:52 -0800103static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104static void intel_finish_crtc_commit(struct drm_crtc *crtc);
Chandra Konduru549e2bf2015-04-07 15:28:38 -0700105static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200107static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
Maarten Lankhorstce22dba2015-04-21 17:12:56 +0300109static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110static void intel_crtc_disable_planes(struct drm_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100111
Dave Airlie0e32b392014-05-02 14:02:48 +1000112static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113{
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118}
119
Jesse Barnes79e53942008-11-07 14:24:08 -0800120typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400121 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800122} intel_range_t;
123
124typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400125 int dot_limit;
126 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800127} intel_p2_t;
128
Ma Lingd4906092009-03-18 20:13:27 +0800129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800133};
Jesse Barnes79e53942008-11-07 14:24:08 -0800134
Daniel Vetterd2acd212012-10-20 20:57:43 +0200135int
136intel_pch_rawclk(struct drm_device *dev)
137{
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143}
144
Chris Wilson021357a2010-09-07 20:54:59 +0100145static inline u32 /* units of 100MHz */
146intel_fdi_link_freq(struct drm_device *dev)
147{
Chris Wilson8b99e682010-10-13 09:59:17 +0100148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100153}
154
Daniel Vetter5d536e22013-07-06 12:52:06 +0200155static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400156 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200157 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200158 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700166};
167
Daniel Vetter5d536e22013-07-06 12:52:06 +0200168static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200170 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200171 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179};
180
Keith Packarde4b36692009-06-05 19:22:17 -0700181static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400182 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200183 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200184 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700192};
Eric Anholt273e27c2011-03-30 13:01:10 -0700193
Keith Packarde4b36692009-06-05 19:22:17 -0700194static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700205};
206
207static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700218};
219
Eric Anholt273e27c2011-03-30 13:01:10 -0700220
Keith Packarde4b36692009-06-05 19:22:17 -0700221static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800233 },
Keith Packarde4b36692009-06-05 19:22:17 -0700234};
235
236static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700247};
248
249static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800260 },
Keith Packarde4b36692009-06-05 19:22:17 -0700261};
262
263static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800274 },
Keith Packarde4b36692009-06-05 19:22:17 -0700275};
276
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500277static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700280 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700283 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700290};
291
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500292static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700303};
304
Eric Anholt273e27c2011-03-30 13:01:10 -0700305/* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800310static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700321};
322
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800323static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800334};
335
336static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800347};
348
Eric Anholt273e27c2011-03-30 13:01:10 -0700349/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800350static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400358 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400371 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800374};
375
Ville Syrjälädc730512013-09-24 21:26:30 +0300376static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200384 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700385 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300388 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700390};
391
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300392static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
Ville Syrjälä17fe1022015-02-26 21:01:52 +0200400 .vco = { .min = 4800000, .max = 6480000 },
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406};
407
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200408static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418};
419
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300420static void vlv_clock(int refclk, intel_clock_t *clock)
421{
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300428}
429
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300430/**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
Damien Lespiau40935612014-10-29 11:16:59 +0000433bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300434{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300435 struct drm_device *dev = crtc->base.dev;
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300436 struct intel_encoder *encoder;
437
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300439 if (encoder->type == type)
440 return true;
441
442 return false;
443}
444
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200445/**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200451static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200453{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200454 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +0300455 struct drm_connector *connector;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200456 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200457 struct intel_encoder *encoder;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200458 int i, num_connectors = 0;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200459
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +0300460 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
465
466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200468 return true;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200469 }
470
471 WARN_ON(num_connectors == 0);
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200472
473 return false;
474}
475
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200476static const intel_limit_t *
477intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800478{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200479 struct drm_device *dev = crtc_state->base.crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800480 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800481
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100483 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000484 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000489 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200494 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800495 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800496
497 return limit;
498}
499
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200500static const intel_limit_t *
501intel_g4x_limit(struct intel_crtc_state *crtc_state)
Ma Ling044c7c42009-03-18 20:13:23 +0800502{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200503 struct drm_device *dev = crtc_state->base.crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800504 const intel_limit_t *limit;
505
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100507 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700508 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800509 else
Keith Packarde4b36692009-06-05 19:22:17 -0700510 limit = &intel_limits_g4x_single_channel_lvds;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700513 limit = &intel_limits_g4x_hdmi;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700515 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800516 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700517 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800518
519 return limit;
520}
521
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200522static const intel_limit_t *
523intel_limit(struct intel_crtc_state *crtc_state, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800524{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200525 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800526 const intel_limit_t *limit;
527
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200531 limit = intel_ironlake_limit(crtc_state, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800532 else if (IS_G4X(dev)) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200533 limit = intel_g4x_limit(crtc_state);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500534 } else if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500536 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800537 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500538 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700541 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300542 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100543 } else if (!IS_GEN2(dev)) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800548 } else {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700550 limit = &intel_limits_i8xx_lvds;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700552 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200553 else
554 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800555 }
556 return limit;
557}
558
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500559/* m1 is reserved as 0 in Pineview, n is a ring counter */
560static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800561{
Shaohua Li21778322009-02-23 15:19:16 +0800562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800568}
569
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200570static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571{
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573}
574
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200575static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800576{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200577 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800578 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800583}
584
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300585static void chv_clock(int refclk, intel_clock_t *clock)
586{
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594}
595
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800596#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800597/**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
Chris Wilson1b894b52010-12-14 20:04:54 +0000602static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800605{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400609 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400611 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400613 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300614
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
Jesse Barnes79e53942008-11-07 14:24:08 -0800626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400627 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400632 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800633
634 return true;
635}
636
Ma Lingd4906092009-03-18 20:13:27 +0800637static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200638i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
Sean Paulcec2f352012-01-10 15:09:36 -0800640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800642{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300644 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800646 int err = target;
647
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800649 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800653 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100654 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
Akshay Joshi0206e352011-08-16 15:34:10 -0400665 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800666
Zhao Yakui42158662009-11-20 11:24:18 +0800667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200671 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800677 int this_err;
678
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200679 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800682 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698}
699
Ma Lingd4906092009-03-18 20:13:27 +0800700static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200701pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200705{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300707 struct drm_device *dev = crtc->base.dev;
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200708 intel_clock_t clock;
709 int err = target;
710
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200712 /*
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
716 */
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
Ma Lingd4906092009-03-18 20:13:27 +0800761static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200762g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800766{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300768 struct drm_device *dev = crtc->base.dev;
Ma Lingd4906092009-03-18 20:13:27 +0800769 intel_clock_t clock;
770 int max_n;
771 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800774 found = false;
775
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100777 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200790 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200792 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200801 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800804 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000805
806 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800817 return found;
818}
Ma Lingd4906092009-03-18 20:13:27 +0800819
Imre Deakd5dd62b2015-03-17 11:40:03 +0200820/*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829{
Imre Deak9ca3ba02015-03-17 11:40:05 +0200830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
Imre Deak24be4e42015-03-17 11:40:04 +0200840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
Imre Deakd5dd62b2015-03-17 11:40:03 +0200843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858}
859
Zhenyu Wang2c072452009-06-05 15:38:42 +0800860static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200861vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700865{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300867 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300868 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300869 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300872 bool found = false;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700873
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700877
878 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300883 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700884 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Imre Deakd5dd62b2015-03-17 11:40:03 +0200886 unsigned int ppm;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300887
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300890
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300891 vlv_clock(refclk, &clock);
892
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300895 continue;
896
Imre Deakd5dd62b2015-03-17 11:40:03 +0200897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300902
Imre Deakd5dd62b2015-03-17 11:40:03 +0200903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700906 }
907 }
908 }
909 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700910
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300911 return found;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700912}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700913
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300914static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200915chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300921 struct drm_device *dev = crtc->base.dev;
Imre Deak9ca3ba02015-03-17 11:40:05 +0200922 unsigned int best_error_ppm;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
Imre Deak9ca3ba02015-03-17 11:40:05 +0200928 best_error_ppm = 1000000;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Imre Deak9ca3ba02015-03-17 11:40:05 +0200942 unsigned int error_ppm;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
Imre Deak9ca3ba02015-03-17 11:40:05 +0200959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300966 }
967 }
968
969 return found;
970}
971
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200972bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974{
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979}
980
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300981bool intel_crtc_active(struct drm_crtc *crtc)
982{
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100988 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300989 * as Haswell has gained clock readout/fastboot support.
990 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000991 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300992 * properly reconstruct framebuffers.
Matt Roperc3d1f432015-03-09 10:19:23 -0700993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300997 */
Matt Roperc3d1f432015-03-09 10:19:23 -0700998 return intel_crtc->active && crtc->primary->state->fb &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200999 intel_crtc->config->base.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001000}
1001
Paulo Zanonia5c961d2012-10-24 15:59:34 -02001002enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004{
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001008 return intel_crtc->config->cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -02001009}
1010
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001011static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012{
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028}
1029
Keith Packardab7ad7f2010-10-03 00:33:06 -07001030/*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001032 * @crtc: crtc whose pipe to wait for
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
Keith Packardab7ad7f2010-10-03 00:33:06 -07001038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +01001044 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001045 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001046static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001047{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001048 struct drm_device *dev = crtc->base.dev;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001049 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001051 enum pipe pipe = crtc->pipe;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001052
Keith Packardab7ad7f2010-10-03 00:33:06 -07001053 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001054 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001055
Keith Packardab7ad7f2010-10-03 00:33:06 -07001056 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001059 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001060 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -07001061 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001063 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001064 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001065}
1066
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001067/*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076{
1077 u32 bit;
1078
Damien Lespiauc36346e2012-12-13 16:09:03 +00001079 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +02001080 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
Robin Schroereba905b2014-05-18 02:24:50 +02001094 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110}
1111
Jesse Barnesb24e7172011-01-04 15:09:30 -08001112static const char *state_string(bool enabled)
1113{
1114 return enabled ? "on" : "off";
1115}
1116
1117/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001118void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001120{
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001128 I915_STATE_WARN(cur_state != state,
Jesse Barnesb24e7172011-01-04 15:09:30 -08001129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001132
Jani Nikula23538ef2013-08-27 15:12:22 +03001133/* XXX: the dsi pll is shared between MIPI DSI ports */
1134static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135{
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
Rob Clarke2c719b2014-12-15 13:56:32 -05001144 I915_STATE_WARN(cur_state != state,
Jani Nikula23538ef2013-08-27 15:12:22 +03001145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147}
1148#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
Daniel Vetter55607e82013-06-16 21:42:39 +02001151struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001152intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001153{
Daniel Vettere2b78262013-06-07 23:10:03 +02001154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001156 if (crtc->config->shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001157 return NULL;
1158
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001160}
1161
Jesse Barnesb24e7172011-01-04 15:09:30 -08001162/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001163void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001166{
Jesse Barnes040484a2011-01-03 12:14:26 -08001167 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001168 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001169
Chris Wilson92b27b02012-05-20 18:10:50 +01001170 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001171 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001172 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001173
Daniel Vetter53589012013-06-05 13:34:16 +02001174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Rob Clarke2c719b2014-12-15 13:56:32 -05001175 I915_STATE_WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001178}
Jesse Barnes040484a2011-01-03 12:14:26 -08001179
1180static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182{
1183 int reg;
1184 u32 val;
1185 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001188
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001192 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
Rob Clarke2c719b2014-12-15 13:56:32 -05001199 I915_STATE_WARN(cur_state != state,
Jesse Barnes040484a2011-01-03 12:14:26 -08001200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202}
1203#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208{
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001216 I915_STATE_WARN(cur_state != state,
Jesse Barnes040484a2011-01-03 12:14:26 -08001217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219}
1220#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225{
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001231 return;
1232
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001234 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001235 return;
1236
Jesse Barnes040484a2011-01-03 12:14:26 -08001237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
Jesse Barnes040484a2011-01-03 12:14:26 -08001240}
1241
Daniel Vetter55607e82013-06-16 21:42:39 +02001242void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001244{
1245 int reg;
1246 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001247 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001252 I915_STATE_WARN(cur_state != state,
Daniel Vetter55607e82013-06-16 21:42:39 +02001253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001255}
1256
Daniel Vetterb680c372014-09-19 18:27:27 +02001257void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
Jesse Barnesea0760c2011-01-04 15:09:32 -08001259{
Jani Nikulabedd4db2014-08-22 15:04:13 +03001260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001264 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001265
Jani Nikulabedd4db2014-08-22 15:04:13 +03001266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
Jesse Barnesea0760c2011-01-04 15:09:32 -08001272 pp_reg = PCH_PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001283 } else {
1284 pp_reg = PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001292 locked = false;
1293
Rob Clarke2c719b2014-12-15 13:56:32 -05001294 I915_STATE_WARN(panel_pipe == pipe && locked,
Jesse Barnesea0760c2011-01-04 15:09:32 -08001295 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001296 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001297}
1298
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001299static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301{
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
Paulo Zanonid9d82082014-02-27 16:30:56 -03001305 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001307 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001309
Rob Clarke2c719b2014-12-15 13:56:32 -05001310 I915_STATE_WARN(cur_state != state,
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313}
1314#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001317void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001319{
1320 int reg;
1321 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001322 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001325
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetter8e636782012-01-22 01:36:48 +01001329 state = true;
1330
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001331 if (!intel_display_power_is_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
Rob Clarke2c719b2014-12-15 13:56:32 -05001340 I915_STATE_WARN(cur_state != state,
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001341 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001342 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001343}
1344
Chris Wilson931872f2012-01-16 23:01:13 +00001345static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001347{
1348 int reg;
1349 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001350 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001355 I915_STATE_WARN(cur_state != state,
Chris Wilson931872f2012-01-16 23:01:13 +00001356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001358}
1359
Chris Wilson931872f2012-01-16 23:01:13 +00001360#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
Jesse Barnesb24e7172011-01-04 15:09:30 -08001363static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001366 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
Ville Syrjälä653e1022013-06-04 13:49:05 +03001371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001378 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001379 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001380
Jesse Barnesb24e7172011-01-04 15:09:30 -08001381 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001382 for_each_pipe(dev_priv, i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
Rob Clarke2c719b2014-12-15 13:56:32 -05001387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001390 }
1391}
1392
Jesse Barnes19332d72013-03-28 09:55:38 -07001393static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001396 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001397 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001398 u32 val;
1399
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001400 if (INTEL_INFO(dev)->gen >= 9) {
Damien Lespiau3bdcfc02015-02-28 14:54:09 +00001401 for_each_sprite(dev_priv, pipe, sprite) {
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001402 val = I915_READ(PLANE_CTL(pipe, sprite));
Rob Clarke2c719b2014-12-15 13:56:32 -05001403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
Damien Lespiau3bdcfc02015-02-28 14:54:09 +00001408 for_each_sprite(dev_priv, pipe, sprite) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001409 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001410 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001411 I915_STATE_WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001413 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001417 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001418 I915_STATE_WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001424 I915_STATE_WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001427 }
1428}
1429
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001430static void assert_vblank_disabled(struct drm_crtc *crtc)
1431{
Rob Clarke2c719b2014-12-15 13:56:32 -05001432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001433 drm_crtc_vblank_put(crtc);
1434}
1435
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001436static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001437{
1438 u32 val;
1439 bool enabled;
1440
Rob Clarke2c719b2014-12-15 13:56:32 -05001441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001442
Jesse Barnes92f25842011-01-04 15:09:34 -08001443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
Rob Clarke2c719b2014-12-15 13:56:32 -05001446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
Jesse Barnes92f25842011-01-04 15:09:34 -08001447}
1448
Daniel Vetterab9412b2013-05-03 11:49:46 +02001449static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001451{
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
Daniel Vetterab9412b2013-05-03 11:49:46 +02001456 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001459 I915_STATE_WARN(enabled,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001462}
1463
Keith Packard4e634382011-08-06 10:39:45 -07001464static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001466{
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483}
1484
Keith Packard1519b992011-08-06 10:35:34 -07001485static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001488 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001493 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001497 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001499 return false;
1500 }
1501 return true;
1502}
1503
1504static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506{
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518}
1519
1520static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522{
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533}
1534
Jesse Barnes291906f2011-02-02 12:28:03 -08001535static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001536 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001537{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001538 u32 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001541 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001542
Rob Clarke2c719b2014-12-15 13:56:32 -05001543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001544 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001545 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001546}
1547
1548static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001551 u32 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001554 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001555
Rob Clarke2c719b2014-12-15 13:56:32 -05001556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001557 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001558 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001559}
1560
1561static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563{
1564 int reg;
1565 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001566
Keith Packardf0575e92011-07-25 22:12:43 -07001567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001574 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001575 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001581 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001582
Paulo Zanonie2debe92013-02-18 19:00:27 -03001583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001586}
1587
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001588static void intel_init_dpio(struct drm_device *dev)
1589{
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001606}
1607
Ville Syrjäläd288f652014-10-28 13:20:22 +02001608static void vlv_enable_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001609 const struct intel_crtc_state *pipe_config)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001610{
Daniel Vetter426115c2013-07-11 22:13:42 +02001611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001614 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001615
Daniel Vetter426115c2013-07-11 22:13:42 +02001616 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001617
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001618 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001622 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001623 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001624
Daniel Vetter426115c2013-07-11 22:13:42 +02001625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
Ville Syrjäläd288f652014-10-28 13:20:22 +02001632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
Daniel Vetter426115c2013-07-11 22:13:42 +02001633 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001634
1635 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001636 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001639 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001642 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645}
1646
Ville Syrjäläd288f652014-10-28 13:20:22 +02001647static void chv_enable_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001648 const struct intel_crtc_state *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001649{
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001674
1675 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001679 /* not sure when this should be written */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001681 POSTING_READ(DPLL_MD(pipe));
1682
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001683 mutex_unlock(&dev_priv->dpio_lock);
1684}
1685
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001686static int intel_num_dvo_pipes(struct drm_device *dev)
1687{
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001694
1695 return count;
1696}
1697
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001698static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001699{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001703 u32 dpll = crtc->config->dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001704
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001705 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001706
1707 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001709
1710 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001713
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001733 crtc->config->dpll_hw_state.dpll_md);
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001742
1743 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001744 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001747 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001750 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753}
1754
1755/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001756 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001764static void i9xx_disable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001765{
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
Daniel Vetter50b44a42013-06-05 13:34:33 +02001788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001790}
1791
Jesse Barnesf6071162013-10-01 10:41:38 -07001792static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793{
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
Imre Deake5cbfbf2014-01-09 17:08:16 +02001799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001803 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001807
1808}
1809
1810static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001813 u32 val;
1814
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001817
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001818 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
Ville Syrjälä61407f62014-05-27 16:32:55 +03001832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
Ville Syrjäläd7520482014-04-09 13:28:59 +03001843 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001844}
1845
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001846void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001847 struct intel_digital_port *dport,
1848 unsigned int expected_mask)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001849{
1850 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001851 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001852
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001853 switch (dport->port) {
1854 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001855 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001856 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001857 break;
1858 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001859 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001860 dpll_reg = DPLL(0);
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001861 expected_mask <<= 4;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001866 break;
1867 default:
1868 BUG();
1869 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001870
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001871 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001874}
1875
Daniel Vetterb14b1052014-04-24 23:55:13 +02001876static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877{
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001882 if (WARN_ON(pll == NULL))
1883 return;
1884
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001885 WARN_ON(!pll->config.crtc_mask);
Daniel Vetterb14b1052014-04-24 23:55:13 +02001886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893}
1894
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001895/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001896 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001903static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001904{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001908
Daniel Vetter87a875b2013-06-05 13:34:19 +02001909 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001910 return;
1911
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001912 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001913 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001914
Damien Lespiau74dd6922014-07-29 18:06:17 +01001915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001916 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001917 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001918
Daniel Vettercdbd2312013-06-05 13:34:03 +02001919 if (pll->active++) {
1920 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001921 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001922 return;
1923 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001924 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001925
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
Daniel Vetter46edb022013-06-05 13:34:12 +02001928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001929 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001930 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001931}
1932
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001933static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001934{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001938
Jesse Barnes92f25842011-01-04 15:09:34 -08001939 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001940 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001941 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001942 return;
1943
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001944 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001945 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001946
Daniel Vetter46edb022013-06-05 13:34:12 +02001947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001949 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001950
Chris Wilson48da64a2012-05-13 20:16:12 +01001951 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001952 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001953 return;
1954 }
1955
Daniel Vettere9d69442013-06-05 13:34:15 +02001956 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001957 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001958 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001959 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001960
Daniel Vetter46edb022013-06-05 13:34:12 +02001961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001962 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001963 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001966}
1967
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001968static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001970{
Daniel Vetter23670b322012-11-01 09:15:30 +01001971 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001974 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001975
1976 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001977 BUG_ON(!HAS_PCH_SPLIT(dev));
Jesse Barnes040484a2011-01-03 12:14:26 -08001978
1979 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001980 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001981 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
Daniel Vetter23670b322012-11-01 09:15:30 +01001987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001994 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001995
Daniel Vetterab9412b2013-05-03 11:49:46 +02001996 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001997 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001998 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07002007 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02002008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02002011 if (HAS_PCH_IBX(dev_priv->dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02002013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02002016 else
2017 val |= TRANS_PROGRESSIVE;
2018
Jesse Barnes040484a2011-01-03 12:14:26 -08002019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03002021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08002022}
2023
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002024static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02002025 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08002026{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002027 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002028
2029 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03002030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002031
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002032 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01002033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02002034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002035
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01002038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02002041 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02002042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002043
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02002044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02002046 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002047 else
2048 val |= TRANS_PROGRESSIVE;
2049
Daniel Vetterab9412b2013-05-03 11:49:46 +02002050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02002052 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002053}
2054
Paulo Zanonib8a4f402012-10-31 18:12:42 -02002055static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08002057{
Daniel Vetter23670b322012-11-01 09:15:30 +01002058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08002060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
Jesse Barnes291906f2011-02-02 12:28:03 -08002065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
Daniel Vetterab9412b2013-05-03 11:49:46 +02002068 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03002074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01002075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
Jesse Barnes040484a2011-01-03 12:14:26 -08002083}
2084
Paulo Zanoniab4d9662012-10-31 18:12:55 -02002085static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002086{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002087 u32 val;
2088
Daniel Vetterab9412b2013-05-03 11:49:46 +02002089 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002090 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02002091 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002092 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02002093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02002094 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01002098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002099 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08002100}
2101
2102/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002103 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02002104 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002105 *
Paulo Zanoni03722642014-01-17 13:51:09 -02002106 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002108 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02002109static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002110{
Paulo Zanoni03722642014-01-17 13:51:09 -02002111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002116 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002117 int reg;
2118 u32 val;
2119
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002120 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002121 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002122 assert_sprites_disabled(dev_priv, pipe);
2123
Paulo Zanoni681e5812012-12-06 11:12:38 -02002124 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
Jesse Barnesb24e7172011-01-04 15:09:30 -08002129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
Imre Deak50360402015-01-16 00:55:16 -08002134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002139 else {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002140 if (crtc->config->has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002141 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002148
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002149 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002150 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002151 if (val & PIPECONF_ENABLE) {
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
Chris Wilson00d70b12011-03-17 07:18:29 +00002154 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002155 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002158 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002159}
2160
2161/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002162 * intel_disable_pipe - disable a pipe, asserting requirements
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002163 * @crtc: crtc whose pipes is to be disabled
Jesse Barnesb24e7172011-01-04 15:09:30 -08002164 *
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002171static void intel_disable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002172{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002175 enum pipe pipe = crtc->pipe;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002184 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002185 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002186
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002187 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002188 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
Ville Syrjälä67adc642014-08-15 01:21:57 +03002192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002196 if (crtc->config->double_wide)
Ville Syrjälä67adc642014-08-15 01:21:57 +03002197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Ville Syrjälä67adc642014-08-15 01:21:57 +03002202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002207}
2208
Keith Packardd74362c2011-07-28 14:47:14 -07002209/*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002213void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002215{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002221}
2222
Jesse Barnesb24e7172011-01-04 15:09:30 -08002223/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002227 *
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002228 * Enable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002229 */
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002230static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002232{
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002239 to_intel_plane_state(plane->state)->visible = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002240
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002241 dev_priv->display.update_primary_plane(crtc, plane->fb,
2242 crtc->x, crtc->y);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002243}
2244
Chris Wilson693db182013-03-05 14:52:39 +00002245static bool need_vtd_wa(struct drm_device *dev)
2246{
2247#ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249 return true;
2250#endif
2251 return false;
2252}
2253
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002254unsigned int
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002255intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256 uint64_t fb_format_modifier)
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002257{
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002258 unsigned int tile_height;
2259 uint32_t pixel_bytes;
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002260
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002261 switch (fb_format_modifier) {
2262 case DRM_FORMAT_MOD_NONE:
2263 tile_height = 1;
2264 break;
2265 case I915_FORMAT_MOD_X_TILED:
2266 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 break;
2268 case I915_FORMAT_MOD_Y_TILED:
2269 tile_height = 32;
2270 break;
2271 case I915_FORMAT_MOD_Yf_TILED:
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002272 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273 switch (pixel_bytes) {
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002274 default:
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002275 case 1:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002276 tile_height = 64;
2277 break;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002278 case 2:
2279 case 4:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002280 tile_height = 32;
2281 break;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002282 case 8:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002283 tile_height = 16;
2284 break;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002285 case 16:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002286 WARN_ONCE(1,
2287 "128-bit pixels are not supported for display!");
2288 tile_height = 16;
2289 break;
2290 }
2291 break;
2292 default:
2293 MISSING_CASE(fb_format_modifier);
2294 tile_height = 1;
2295 break;
2296 }
Daniel Vetter091df6c2015-02-10 17:16:10 +00002297
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002298 return tile_height;
2299}
2300
2301unsigned int
2302intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303 uint32_t pixel_format, uint64_t fb_format_modifier)
2304{
2305 return ALIGN(height, intel_tile_height(dev, pixel_format,
2306 fb_format_modifier));
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002307}
2308
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002309static int
2310intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311 const struct drm_plane_state *plane_state)
2312{
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002313 struct intel_rotation_info *info = &view->rotation_info;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002314
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002315 *view = i915_ggtt_view_normal;
2316
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002317 if (!plane_state)
2318 return 0;
2319
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002320 if (!intel_rotation_90_or_270(plane_state->rotation))
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002321 return 0;
2322
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002323 *view = i915_ggtt_view_rotated;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002324
2325 info->height = fb->height;
2326 info->pixel_format = fb->pixel_format;
2327 info->pitch = fb->pitches[0];
2328 info->fb_modifier = fb->modifier[0];
2329
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002330 return 0;
2331}
2332
Chris Wilson127bd2a2010-07-23 23:32:05 +01002333int
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002334intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002336 const struct drm_plane_state *plane_state,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002337 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002338{
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002339 struct drm_device *dev = fb->dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00002340 struct drm_i915_private *dev_priv = dev->dev_private;
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002342 struct i915_ggtt_view view;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002343 u32 alignment;
2344 int ret;
2345
Matt Roperebcdd392014-07-09 16:22:11 -07002346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
Chris Wilson534843d2010-07-05 18:01:46 +01002353 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002354 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002355 alignment = 4 * 1024;
2356 else
2357 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002358 break;
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002359 case I915_FORMAT_MOD_X_TILED:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002360 if (INTEL_INFO(dev)->gen >= 9)
2361 alignment = 256 * 1024;
2362 else {
2363 /* pin() will align the object as required by fence */
2364 alignment = 0;
2365 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002366 break;
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002367 case I915_FORMAT_MOD_Y_TILED:
Damien Lespiau1327b9a2015-02-27 11:15:20 +00002368 case I915_FORMAT_MOD_Yf_TILED:
2369 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2371 return -EINVAL;
2372 alignment = 1 * 1024 * 1024;
2373 break;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002374 default:
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002375 MISSING_CASE(fb->modifier[0]);
2376 return -EINVAL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002377 }
2378
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002379 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380 if (ret)
2381 return ret;
2382
Chris Wilson693db182013-03-05 14:52:39 +00002383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2386 * the VT-d warning.
2387 */
2388 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389 alignment = 256 * 1024;
2390
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002391 /*
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2397 */
2398 intel_runtime_pm_get(dev_priv);
2399
Chris Wilsonce453d82011-02-21 14:43:56 +00002400 dev_priv->mm.interruptible = false;
Tvrtko Ursuline6617332015-03-23 11:10:33 +00002401 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002402 &view);
Chris Wilson48b956c2010-09-14 12:50:34 +01002403 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002404 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002405
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2410 */
Chris Wilson06d98132012-04-17 15:31:24 +01002411 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002412 if (ret)
2413 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002414
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002415 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002416
Chris Wilsonce453d82011-02-21 14:43:56 +00002417 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002418 intel_runtime_pm_put(dev_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002419 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002420
2421err_unpin:
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002422 i915_gem_object_unpin_from_display_plane(obj, &view);
Chris Wilsonce453d82011-02-21 14:43:56 +00002423err_interruptible:
2424 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002425 intel_runtime_pm_put(dev_priv);
Chris Wilson48b956c2010-09-14 12:50:34 +01002426 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002427}
2428
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002429static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430 const struct drm_plane_state *plane_state)
Chris Wilson1690e1e2011-12-14 13:57:08 +01002431{
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002432 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002433 struct i915_ggtt_view view;
2434 int ret;
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002435
Matt Roperebcdd392014-07-09 16:22:11 -07002436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439 WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
Chris Wilson1690e1e2011-12-14 13:57:08 +01002441 i915_gem_object_unpin_fence(obj);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002442 i915_gem_object_unpin_from_display_plane(obj, &view);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002443}
2444
Daniel Vetterc2c75132012-07-05 12:17:30 +02002445/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002447unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002451{
Chris Wilsonbc752862013-02-21 20:04:31 +00002452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002454
Chris Wilsonbc752862013-02-21 20:04:31 +00002455 tile_rows = *y / 8;
2456 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002457
Chris Wilsonbc752862013-02-21 20:04:31 +00002458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int offset;
2464
2465 offset = *y * pitch + *x * cpp;
2466 *y = 0;
2467 *x = (offset & 4095) / cpp;
2468 return offset & -4096;
2469 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002470}
2471
Damien Lespiaub35d63f2015-01-20 12:51:50 +00002472static int i9xx_format_to_fourcc(int format)
Jesse Barnes46f297f2014-03-07 08:57:48 -08002473{
2474 switch (format) {
2475 case DISPPLANE_8BPP:
2476 return DRM_FORMAT_C8;
2477 case DISPPLANE_BGRX555:
2478 return DRM_FORMAT_XRGB1555;
2479 case DISPPLANE_BGRX565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case DISPPLANE_BGRX888:
2483 return DRM_FORMAT_XRGB8888;
2484 case DISPPLANE_RGBX888:
2485 return DRM_FORMAT_XBGR8888;
2486 case DISPPLANE_BGRX101010:
2487 return DRM_FORMAT_XRGB2101010;
2488 case DISPPLANE_RGBX101010:
2489 return DRM_FORMAT_XBGR2101010;
2490 }
2491}
2492
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00002493static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494{
2495 switch (format) {
2496 case PLANE_CTL_FORMAT_RGB_565:
2497 return DRM_FORMAT_RGB565;
2498 default:
2499 case PLANE_CTL_FORMAT_XRGB_8888:
2500 if (rgb_order) {
2501 if (alpha)
2502 return DRM_FORMAT_ABGR8888;
2503 else
2504 return DRM_FORMAT_XBGR8888;
2505 } else {
2506 if (alpha)
2507 return DRM_FORMAT_ARGB8888;
2508 else
2509 return DRM_FORMAT_XRGB8888;
2510 }
2511 case PLANE_CTL_FORMAT_XRGB_2101010:
2512 if (rgb_order)
2513 return DRM_FORMAT_XBGR2101010;
2514 else
2515 return DRM_FORMAT_XRGB2101010;
2516 }
2517}
2518
Damien Lespiau5724dbd2015-01-20 12:51:52 +00002519static bool
Daniel Vetterf6936e22015-03-26 12:17:05 +01002520intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521 struct intel_initial_plane_config *plane_config)
Jesse Barnes46f297f2014-03-07 08:57:48 -08002522{
2523 struct drm_device *dev = crtc->base.dev;
2524 struct drm_i915_gem_object *obj = NULL;
2525 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Damien Lespiau2d140302015-02-05 17:22:18 +00002526 struct drm_framebuffer *fb = &plane_config->fb->base;
Daniel Vetterf37b5c22015-02-10 23:12:27 +01002527 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529 PAGE_SIZE);
2530
2531 size_aligned -= base_aligned;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002532
Chris Wilsonff2652e2014-03-10 08:07:02 +00002533 if (plane_config->size == 0)
2534 return false;
2535
Daniel Vetterf37b5c22015-02-10 23:12:27 +01002536 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 base_aligned,
2538 base_aligned,
2539 size_aligned);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002540 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002541 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002542
Damien Lespiau49af4492015-01-20 12:51:44 +00002543 obj->tiling_mode = plane_config->tiling;
2544 if (obj->tiling_mode == I915_TILING_X)
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002545 obj->stride = fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002546
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002547 mode_cmd.pixel_format = fb->pixel_format;
2548 mode_cmd.width = fb->width;
2549 mode_cmd.height = fb->height;
2550 mode_cmd.pitches[0] = fb->pitches[0];
Daniel Vetter18c52472015-02-10 17:16:09 +00002551 mode_cmd.modifier[0] = fb->modifier[0];
2552 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002553
2554 mutex_lock(&dev->struct_mutex);
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002555 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002556 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002557 DRM_DEBUG_KMS("intel fb init failed\n");
2558 goto out_unref_obj;
2559 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002560 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002561
Daniel Vetterf6936e22015-03-26 12:17:05 +01002562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002563 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002564
2565out_unref_obj:
2566 drm_gem_object_unreference(&obj->base);
2567 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002568 return false;
2569}
2570
Matt Roperafd65eb2015-02-03 13:10:04 -08002571/* Update plane->state->fb to match plane->fb after driver-internal updates */
2572static void
2573update_state_fb(struct drm_plane *plane)
2574{
2575 if (plane->fb == plane->state->fb)
2576 return;
2577
2578 if (plane->state->fb)
2579 drm_framebuffer_unreference(plane->state->fb);
2580 plane->state->fb = plane->fb;
2581 if (plane->state->fb)
2582 drm_framebuffer_reference(plane->state->fb);
2583}
2584
Damien Lespiau5724dbd2015-01-20 12:51:52 +00002585static void
Daniel Vetterf6936e22015-03-26 12:17:05 +01002586intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587 struct intel_initial_plane_config *plane_config)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002588{
2589 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002590 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002591 struct drm_crtc *c;
2592 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002593 struct drm_i915_gem_object *obj;
Daniel Vetter88595ac2015-03-26 12:42:24 +01002594 struct drm_plane *primary = intel_crtc->base.primary;
2595 struct drm_framebuffer *fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002596
Damien Lespiau2d140302015-02-05 17:22:18 +00002597 if (!plane_config->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002598 return;
2599
Daniel Vetterf6936e22015-03-26 12:17:05 +01002600 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
Daniel Vetter88595ac2015-03-26 12:42:24 +01002601 fb = &plane_config->fb->base;
2602 goto valid_fb;
Damien Lespiauf55548b2015-02-05 18:30:20 +00002603 }
Jesse Barnes484b41d2014-03-07 08:57:55 -08002604
Damien Lespiau2d140302015-02-05 17:22:18 +00002605 kfree(plane_config->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002606
2607 /*
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2610 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002611 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002612 i = to_intel_crtc(c);
2613
2614 if (c == &intel_crtc->base)
2615 continue;
2616
Matt Roper2ff8fde2014-07-08 07:50:07 -07002617 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002618 continue;
2619
Daniel Vetter88595ac2015-03-26 12:42:24 +01002620 fb = c->primary->fb;
2621 if (!fb)
Matt Roper2ff8fde2014-07-08 07:50:07 -07002622 continue;
2623
Daniel Vetter88595ac2015-03-26 12:42:24 +01002624 obj = intel_fb_obj(fb);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002625 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Daniel Vetter88595ac2015-03-26 12:42:24 +01002626 drm_framebuffer_reference(fb);
2627 goto valid_fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002628 }
2629 }
Daniel Vetter88595ac2015-03-26 12:42:24 +01002630
2631 return;
2632
2633valid_fb:
2634 obj = intel_fb_obj(fb);
2635 if (obj->tiling_mode != I915_TILING_NONE)
2636 dev_priv->preserve_bios_swizzle = true;
2637
2638 primary->fb = fb;
2639 primary->state->crtc = &intel_crtc->base;
2640 primary->crtc = &intel_crtc->base;
2641 update_state_fb(primary);
2642 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002643}
2644
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002645static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646 struct drm_framebuffer *fb,
2647 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002648{
2649 struct drm_device *dev = crtc->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002652 struct drm_plane *primary = crtc->primary;
2653 bool visible = to_intel_plane_state(primary->state)->visible;
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002654 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002655 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002656 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002657 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002658 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302659 int pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002660
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002661 if (!visible || !fb) {
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002662 I915_WRITE(reg, 0);
2663 if (INTEL_INFO(dev)->gen >= 4)
2664 I915_WRITE(DSPSURF(plane), 0);
2665 else
2666 I915_WRITE(DSPADDR(plane), 0);
2667 POSTING_READ(reg);
2668 return;
2669 }
2670
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002671 obj = intel_fb_obj(fb);
2672 if (WARN_ON(obj == NULL))
2673 return;
2674
2675 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002677 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002679 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002680
2681 if (INTEL_INFO(dev)->gen < 4) {
2682 if (intel_crtc->pipe == PIPE_B)
2683 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2687 */
2688 I915_WRITE(DSPSIZE(plane),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002691 I915_WRITE(DSPPOS(plane), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002692 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693 I915_WRITE(PRIMSIZE(plane),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002696 I915_WRITE(PRIMPOS(plane), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane), 0);
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002698 }
2699
Ville Syrjälä57779d02012-10-31 17:50:14 +02002700 switch (fb->pixel_format) {
2701 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002702 dspcntr |= DISPPLANE_8BPP;
2703 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002704 case DRM_FORMAT_XRGB1555:
2705 case DRM_FORMAT_ARGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002707 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 case DRM_FORMAT_ARGB8888:
2713 dspcntr |= DISPPLANE_BGRX888;
2714 break;
2715 case DRM_FORMAT_XBGR8888:
2716 case DRM_FORMAT_ABGR8888:
2717 dspcntr |= DISPPLANE_RGBX888;
2718 break;
2719 case DRM_FORMAT_XRGB2101010:
2720 case DRM_FORMAT_ARGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 case DRM_FORMAT_ABGR2101010:
2725 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002726 break;
2727 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002728 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002729 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002730
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002734
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
Ville Syrjäläb98971272014-08-27 16:51:22 +03002738 linear_offset = y * fb->pitches[0] + x * pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002739
Daniel Vetterc2c75132012-07-05 12:17:30 +02002740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002742 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002743 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002744 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002747 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002748 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002749
Matt Roper8e7d6882015-01-21 16:35:41 -08002750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
Sonika Jindal48404c12014-08-22 14:06:04 +05302751 dspcntr |= DISPPLANE_ROTATE_180;
2752
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
Sonika Jindal48404c12014-08-22 14:06:04 +05302755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
Sonika Jindal48404c12014-08-22 14:06:04 +05302761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002765 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002766 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002767 I915_WRITE(DSPSURF(plane),
2768 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002770 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002771 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002772 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002773 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002774}
2775
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002776static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777 struct drm_framebuffer *fb,
2778 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002779{
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002783 struct drm_plane *primary = crtc->primary;
2784 bool visible = to_intel_plane_state(primary->state)->visible;
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002785 struct drm_i915_gem_object *obj;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002786 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002787 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002788 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002789 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302790 int pixel_size;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002791
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002792 if (!visible || !fb) {
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002793 I915_WRITE(reg, 0);
2794 I915_WRITE(DSPSURF(plane), 0);
2795 POSTING_READ(reg);
2796 return;
2797 }
2798
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002799 obj = intel_fb_obj(fb);
2800 if (WARN_ON(obj == NULL))
2801 return;
2802
2803 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
Ville Syrjäläfdd508a62014-08-08 21:51:11 +03002807 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002808
2809 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
Ville Syrjälä57779d02012-10-31 17:50:14 +02002812 switch (fb->pixel_format) {
2813 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002814 dspcntr |= DISPPLANE_8BPP;
2815 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002816 case DRM_FORMAT_RGB565:
2817 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002818 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002819 case DRM_FORMAT_XRGB8888:
2820 case DRM_FORMAT_ARGB8888:
2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
2824 case DRM_FORMAT_ABGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 case DRM_FORMAT_ARGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 case DRM_FORMAT_ABGR2101010:
2833 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002834 break;
2835 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002836 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002841
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002844
Ville Syrjäläb98971272014-08-27 16:51:22 +03002845 linear_offset = y * fb->pitches[0] + x * pixel_size;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002846 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002847 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002848 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002849 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002850 linear_offset -= intel_crtc->dspaddr_offset;
Matt Roper8e7d6882015-01-21 16:35:41 -08002851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
Sonika Jindal48404c12014-08-22 14:06:04 +05302852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
Sonika Jindal48404c12014-08-22 14:06:04 +05302857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
Sonika Jindal48404c12014-08-22 14:06:04 +05302863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002867
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002877 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002878}
2879
Damien Lespiaub3218032015-02-27 11:15:18 +00002880u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882{
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912}
2913
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002914unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002920 view = &i915_ggtt_view_rotated;
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923}
2924
Chandra Kondurua1b22782015-04-07 15:28:45 -07002925/*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929{
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952}
2953
Chandra Konduru6156a452015-04-27 13:48:39 -07002954u32 skl_plane_ctl_format(uint32_t pixel_format)
2955{
2956 u32 plane_ctl_format = 0;
2957 switch (pixel_format) {
2958 case DRM_FORMAT_RGB565:
2959 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
2960 break;
2961 case DRM_FORMAT_XBGR8888:
2962 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963 break;
2964 case DRM_FORMAT_XRGB8888:
2965 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
2966 break;
2967 /*
2968 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2969 * to be already pre-multiplied. We need to add a knob (or a different
2970 * DRM_FORMAT) for user-space to configure that.
2971 */
2972 case DRM_FORMAT_ABGR8888:
2973 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2975 break;
2976 case DRM_FORMAT_ARGB8888:
2977 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979 break;
2980 case DRM_FORMAT_XRGB2101010:
2981 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
2982 break;
2983 case DRM_FORMAT_XBGR2101010:
2984 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2985 break;
2986 case DRM_FORMAT_YUYV:
2987 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2988 break;
2989 case DRM_FORMAT_YVYU:
2990 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2991 break;
2992 case DRM_FORMAT_UYVY:
2993 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2994 break;
2995 case DRM_FORMAT_VYUY:
2996 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2997 break;
2998 default:
2999 BUG();
3000 }
3001 return plane_ctl_format;
3002}
3003
3004u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3005{
3006 u32 plane_ctl_tiling = 0;
3007 switch (fb_modifier) {
3008 case DRM_FORMAT_MOD_NONE:
3009 break;
3010 case I915_FORMAT_MOD_X_TILED:
3011 plane_ctl_tiling = PLANE_CTL_TILED_X;
3012 break;
3013 case I915_FORMAT_MOD_Y_TILED:
3014 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3015 break;
3016 case I915_FORMAT_MOD_Yf_TILED:
3017 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3018 break;
3019 default:
3020 MISSING_CASE(fb_modifier);
3021 }
3022 return plane_ctl_tiling;
3023}
3024
3025u32 skl_plane_ctl_rotation(unsigned int rotation)
3026{
3027 u32 plane_ctl_rotation = 0;
3028 switch (rotation) {
3029 case BIT(DRM_ROTATE_0):
3030 break;
3031 case BIT(DRM_ROTATE_90):
3032 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3033 break;
3034 case BIT(DRM_ROTATE_180):
3035 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3036 break;
3037 case BIT(DRM_ROTATE_270):
3038 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3039 break;
3040 default:
3041 MISSING_CASE(rotation);
3042 }
3043
3044 return plane_ctl_rotation;
3045}
3046
Damien Lespiau70d21f02013-07-03 21:06:04 +01003047static void skylake_update_primary_plane(struct drm_crtc *crtc,
3048 struct drm_framebuffer *fb,
3049 int x, int y)
3050{
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03003054 struct drm_plane *plane = crtc->primary;
3055 bool visible = to_intel_plane_state(plane->state)->visible;
Damien Lespiau70d21f02013-07-03 21:06:04 +01003056 struct drm_i915_gem_object *obj;
3057 int pipe = intel_crtc->pipe;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303058 u32 plane_ctl, stride_div, stride;
3059 u32 tile_height, plane_offset, plane_size;
3060 unsigned int rotation;
3061 int x_offset, y_offset;
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003062 unsigned long surf_addr;
Chandra Konduru6156a452015-04-27 13:48:39 -07003063 struct intel_crtc_state *crtc_state = intel_crtc->config;
3064 struct intel_plane_state *plane_state;
3065 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3066 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3067 int scaler_id = -1;
3068
Chandra Konduru6156a452015-04-27 13:48:39 -07003069 plane_state = to_intel_plane_state(plane->state);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003070
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03003071 if (!visible || !fb) {
Damien Lespiau70d21f02013-07-03 21:06:04 +01003072 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3073 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3074 POSTING_READ(PLANE_CTL(pipe, 0));
3075 return;
3076 }
3077
3078 plane_ctl = PLANE_CTL_ENABLE |
3079 PLANE_CTL_PIPE_GAMMA_ENABLE |
3080 PLANE_CTL_PIPE_CSC_ENABLE;
3081
Chandra Konduru6156a452015-04-27 13:48:39 -07003082 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3083 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003084 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303085
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303086 rotation = plane->state->rotation;
Chandra Konduru6156a452015-04-27 13:48:39 -07003087 plane_ctl |= skl_plane_ctl_rotation(rotation);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003088
Damien Lespiaub3218032015-02-27 11:15:18 +00003089 obj = intel_fb_obj(fb);
3090 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3091 fb->pixel_format);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303092 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3093
Chandra Konduru6156a452015-04-27 13:48:39 -07003094 /*
3095 * FIXME: intel_plane_state->src, dst aren't set when transitional
3096 * update_plane helpers are called from legacy paths.
3097 * Once full atomic crtc is available, below check can be avoided.
3098 */
3099 if (drm_rect_width(&plane_state->src)) {
3100 scaler_id = plane_state->scaler_id;
3101 src_x = plane_state->src.x1 >> 16;
3102 src_y = plane_state->src.y1 >> 16;
3103 src_w = drm_rect_width(&plane_state->src) >> 16;
3104 src_h = drm_rect_height(&plane_state->src) >> 16;
3105 dst_x = plane_state->dst.x1;
3106 dst_y = plane_state->dst.y1;
3107 dst_w = drm_rect_width(&plane_state->dst);
3108 dst_h = drm_rect_height(&plane_state->dst);
3109
3110 WARN_ON(x != src_x || y != src_y);
3111 } else {
3112 src_w = intel_crtc->config->pipe_src_w;
3113 src_h = intel_crtc->config->pipe_src_h;
3114 }
3115
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303116 if (intel_rotation_90_or_270(rotation)) {
3117 /* stride = Surface height in tiles */
3118 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3119 fb->modifier[0]);
3120 stride = DIV_ROUND_UP(fb->height, tile_height);
Chandra Konduru6156a452015-04-27 13:48:39 -07003121 x_offset = stride * tile_height - y - src_h;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303122 y_offset = x;
Chandra Konduru6156a452015-04-27 13:48:39 -07003123 plane_size = (src_w - 1) << 16 | (src_h - 1);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303124 } else {
3125 stride = fb->pitches[0] / stride_div;
3126 x_offset = x;
3127 y_offset = y;
Chandra Konduru6156a452015-04-27 13:48:39 -07003128 plane_size = (src_h - 1) << 16 | (src_w - 1);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303129 }
3130 plane_offset = y_offset << 16 | x_offset;
Damien Lespiaub3218032015-02-27 11:15:18 +00003131
Damien Lespiau70d21f02013-07-03 21:06:04 +01003132 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303133 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3134 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3135 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
Chandra Konduru6156a452015-04-27 13:48:39 -07003136
3137 if (scaler_id >= 0) {
3138 uint32_t ps_ctrl = 0;
3139
3140 WARN_ON(!dst_w || !dst_h);
3141 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3142 crtc_state->scaler_state.scalers[scaler_id].mode;
3143 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3144 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3145 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3146 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3147 I915_WRITE(PLANE_POS(pipe, 0), 0);
3148 } else {
3149 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3150 }
3151
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003152 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003153
3154 POSTING_READ(PLANE_SURF(pipe, 0));
3155}
3156
Jesse Barnes17638cd2011-06-24 12:19:23 -07003157/* Assume fb object is pinned & idle & fenced and just update base pointers */
3158static int
3159intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3160 int x, int y, enum mode_set_atomic state)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003164
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01003165 if (dev_priv->display.disable_fbc)
3166 dev_priv->display.disable_fbc(dev);
Jesse Barnes81255562010-08-02 12:07:50 -07003167
Daniel Vetter29b9bde2014-04-24 23:55:01 +02003168 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3169
3170 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07003171}
3172
Ville Syrjälä75147472014-11-24 18:28:11 +02003173static void intel_complete_page_flips(struct drm_device *dev)
Ville Syrjälä96a02912013-02-18 19:08:49 +02003174{
Ville Syrjälä96a02912013-02-18 19:08:49 +02003175 struct drm_crtc *crtc;
3176
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01003177 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02003178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179 enum plane plane = intel_crtc->plane;
3180
3181 intel_prepare_page_flip(dev, plane);
3182 intel_finish_page_flip_plane(dev, plane);
3183 }
Ville Syrjälä75147472014-11-24 18:28:11 +02003184}
3185
3186static void intel_update_primary_planes(struct drm_device *dev)
3187{
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 struct drm_crtc *crtc;
Ville Syrjälä96a02912013-02-18 19:08:49 +02003190
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01003191 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02003192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193
Rob Clark51fd3712013-11-19 12:10:12 -05003194 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00003195 /*
3196 * FIXME: Once we have proper support for primary planes (and
3197 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10003198 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00003199 */
Matt Roperf4510a22014-04-01 15:22:40 -07003200 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07003201 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10003202 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07003203 crtc->x,
3204 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05003205 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02003206 }
3207}
3208
Maarten Lankhorstce22dba2015-04-21 17:12:56 +03003209void intel_crtc_reset(struct intel_crtc *crtc)
3210{
3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3212
3213 if (!crtc->active)
3214 return;
3215
3216 intel_crtc_disable_planes(&crtc->base);
3217 dev_priv->display.crtc_disable(&crtc->base);
3218 dev_priv->display.crtc_enable(&crtc->base);
3219 intel_crtc_enable_planes(&crtc->base);
3220}
3221
Ville Syrjälä75147472014-11-24 18:28:11 +02003222void intel_prepare_reset(struct drm_device *dev)
3223{
Ville Syrjäläf98ce922014-11-21 21:54:30 +02003224 struct drm_i915_private *dev_priv = to_i915(dev);
3225 struct intel_crtc *crtc;
3226
Ville Syrjälä75147472014-11-24 18:28:11 +02003227 /* no reset support for gen2 */
3228 if (IS_GEN2(dev))
3229 return;
3230
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233 return;
3234
3235 drm_modeset_lock_all(dev);
Ville Syrjäläf98ce922014-11-21 21:54:30 +02003236
3237 /*
3238 * Disabling the crtcs gracefully seems nicer. Also the
3239 * g33 docs say we should at least disable all the planes.
3240 */
3241 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorstce22dba2015-04-21 17:12:56 +03003242 if (!crtc->active)
3243 continue;
3244
3245 intel_crtc_disable_planes(&crtc->base);
3246 dev_priv->display.crtc_disable(&crtc->base);
Ville Syrjäläf98ce922014-11-21 21:54:30 +02003247 }
Ville Syrjälä75147472014-11-24 18:28:11 +02003248}
3249
3250void intel_finish_reset(struct drm_device *dev)
3251{
3252 struct drm_i915_private *dev_priv = to_i915(dev);
3253
3254 /*
3255 * Flips in the rings will be nuked by the reset,
3256 * so complete all pending flips so that user space
3257 * will get its events and not get stuck.
3258 */
3259 intel_complete_page_flips(dev);
3260
3261 /* no reset support for gen2 */
3262 if (IS_GEN2(dev))
3263 return;
3264
3265 /* reset doesn't touch the display */
3266 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3267 /*
3268 * Flips in the rings have been nuked by the reset,
3269 * so update the base address of all primary
3270 * planes to the the last fb to make sure we're
3271 * showing the correct fb after a reset.
3272 */
3273 intel_update_primary_planes(dev);
3274 return;
3275 }
3276
3277 /*
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3280 */
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3283
3284 intel_modeset_init_hw(dev);
3285
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3290
3291 intel_modeset_setup_hw_state(dev, true);
3292
3293 intel_hpd_init(dev_priv);
3294
3295 drm_modeset_unlock_all(dev);
3296}
3297
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003298static int
Chris Wilson14667a42012-04-03 17:58:35 +01003299intel_finish_fb(struct drm_framebuffer *old_fb)
3300{
Matt Roper2ff8fde2014-07-08 07:50:07 -07003301 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01003302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3303 bool was_interruptible = dev_priv->mm.interruptible;
3304 int ret;
3305
Chris Wilson14667a42012-04-03 17:58:35 +01003306 /* Big Hammer, we also need to ensure that any pending
3307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3308 * current scanout is retired before unpinning the old
3309 * framebuffer.
3310 *
3311 * This should only fail upon a hung GPU, in which case we
3312 * can safely continue.
3313 */
3314 dev_priv->mm.interruptible = false;
3315 ret = i915_gem_object_finish_gpu(obj);
3316 dev_priv->mm.interruptible = was_interruptible;
3317
3318 return ret;
3319}
3320
Chris Wilson7d5e3792014-03-04 13:15:08 +00003321static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3322{
3323 struct drm_device *dev = crtc->dev;
3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson7d5e3792014-03-04 13:15:08 +00003326 bool pending;
3327
3328 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3329 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3330 return false;
3331
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003332 spin_lock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00003333 pending = to_intel_crtc(crtc)->unpin_work != NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003334 spin_unlock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00003335
3336 return pending;
3337}
3338
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003339static void intel_update_pipe_size(struct intel_crtc *crtc)
3340{
3341 struct drm_device *dev = crtc->base.dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 const struct drm_display_mode *adjusted_mode;
3344
3345 if (!i915.fastboot)
3346 return;
3347
3348 /*
3349 * Update pipe size and adjust fitter if needed: the reason for this is
3350 * that in compute_mode_changes we check the native mode (not the pfit
3351 * mode) to see if we can flip rather than do a full mode set. In the
3352 * fastboot case, we'll flip, but if we don't update the pipesrc and
3353 * pfit state, we'll end up with a big fb scanned out into the wrong
3354 * sized surface.
3355 *
3356 * To fix this properly, we need to hoist the checks up into
3357 * compute_mode_changes (or above), check the actual pfit state and
3358 * whether the platform allows pfit disable with pipe active, and only
3359 * then update the pipesrc and pfit state, even on the flip path.
3360 */
3361
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003362 adjusted_mode = &crtc->config->base.adjusted_mode;
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003363
3364 I915_WRITE(PIPESRC(crtc->pipe),
3365 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3366 (adjusted_mode->crtc_vdisplay - 1));
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003367 if (!crtc->config->pch_pfit.enabled &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03003368 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3369 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003370 I915_WRITE(PF_CTL(crtc->pipe), 0);
3371 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3372 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3373 }
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003374 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3375 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003376}
3377
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003378static void intel_fdi_normal_train(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
3384 u32 reg, temp;
3385
3386 /* enable normal train */
3387 reg = FDI_TX_CTL(pipe);
3388 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07003389 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07003390 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3391 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07003392 } else {
3393 temp &= ~FDI_LINK_TRAIN_NONE;
3394 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07003395 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003396 I915_WRITE(reg, temp);
3397
3398 reg = FDI_RX_CTL(pipe);
3399 temp = I915_READ(reg);
3400 if (HAS_PCH_CPT(dev)) {
3401 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3402 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3403 } else {
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_NONE;
3406 }
3407 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3408
3409 /* wait one idle pattern time */
3410 POSTING_READ(reg);
3411 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07003412
3413 /* IVB wants error correction enabled */
3414 if (IS_IVYBRIDGE(dev))
3415 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3416 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003417}
3418
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003419/* The FDI link training functions for ILK/Ibexpeak. */
3420static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3421{
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003426 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003427
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03003428 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003429 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003430
Adam Jacksone1a44742010-06-25 15:32:14 -04003431 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3432 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003433 reg = FDI_RX_IMR(pipe);
3434 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003435 temp &= ~FDI_RX_SYMBOL_LOCK;
3436 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003437 I915_WRITE(reg, temp);
3438 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003439 udelay(150);
3440
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003441 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003442 reg = FDI_TX_CTL(pipe);
3443 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003444 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003445 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003449
Chris Wilson5eddb702010-09-11 13:48:45 +01003450 reg = FDI_RX_CTL(pipe);
3451 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3455
3456 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003457 udelay(150);
3458
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003459 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01003460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3462 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003463
Chris Wilson5eddb702010-09-11 13:48:45 +01003464 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003465 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003466 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3468
3469 if ((temp & FDI_RX_BIT_LOCK)) {
3470 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003471 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003472 break;
3473 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003474 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003475 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003476 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003477
3478 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003481 temp &= ~FDI_LINK_TRAIN_NONE;
3482 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003483 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003484
Chris Wilson5eddb702010-09-11 13:48:45 +01003485 reg = FDI_RX_CTL(pipe);
3486 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003487 temp &= ~FDI_LINK_TRAIN_NONE;
3488 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003489 I915_WRITE(reg, temp);
3490
3491 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003492 udelay(150);
3493
Chris Wilson5eddb702010-09-11 13:48:45 +01003494 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003495 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003496 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3498
3499 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003500 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003501 DRM_DEBUG_KMS("FDI train 2 done.\n");
3502 break;
3503 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003504 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003505 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003506 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003507
3508 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07003509
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003510}
3511
Akshay Joshi0206e352011-08-16 15:34:10 -04003512static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003513 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3514 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3515 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3516 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3517};
3518
3519/* The FDI link training functions for SNB/Cougarpoint. */
3520static void gen6_fdi_link_train(struct drm_crtc *crtc)
3521{
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05003526 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003527
Adam Jacksone1a44742010-06-25 15:32:14 -04003528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3529 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003530 reg = FDI_RX_IMR(pipe);
3531 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003532 temp &= ~FDI_RX_SYMBOL_LOCK;
3533 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003534 I915_WRITE(reg, temp);
3535
3536 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003537 udelay(150);
3538
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003539 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003542 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003543 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003544 temp &= ~FDI_LINK_TRAIN_NONE;
3545 temp |= FDI_LINK_TRAIN_PATTERN_1;
3546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3547 /* SNB-B */
3548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003549 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003550
Daniel Vetterd74cf322012-10-26 10:58:13 +02003551 I915_WRITE(FDI_RX_MISC(pipe),
3552 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3553
Chris Wilson5eddb702010-09-11 13:48:45 +01003554 reg = FDI_RX_CTL(pipe);
3555 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003556 if (HAS_PCH_CPT(dev)) {
3557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3558 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3559 } else {
3560 temp &= ~FDI_LINK_TRAIN_NONE;
3561 temp |= FDI_LINK_TRAIN_PATTERN_1;
3562 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3564
3565 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003566 udelay(150);
3567
Akshay Joshi0206e352011-08-16 15:34:10 -04003568 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3572 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003573 I915_WRITE(reg, temp);
3574
3575 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003576 udelay(500);
3577
Sean Paulfa37d392012-03-02 12:53:39 -05003578 for (retry = 0; retry < 5; retry++) {
3579 reg = FDI_RX_IIR(pipe);
3580 temp = I915_READ(reg);
3581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3582 if (temp & FDI_RX_BIT_LOCK) {
3583 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3584 DRM_DEBUG_KMS("FDI train 1 done.\n");
3585 break;
3586 }
3587 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003588 }
Sean Paulfa37d392012-03-02 12:53:39 -05003589 if (retry < 5)
3590 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003591 }
3592 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003593 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003594
3595 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003598 temp &= ~FDI_LINK_TRAIN_NONE;
3599 temp |= FDI_LINK_TRAIN_PATTERN_2;
3600 if (IS_GEN6(dev)) {
3601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3602 /* SNB-B */
3603 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3604 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003605 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003606
Chris Wilson5eddb702010-09-11 13:48:45 +01003607 reg = FDI_RX_CTL(pipe);
3608 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003609 if (HAS_PCH_CPT(dev)) {
3610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3611 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3612 } else {
3613 temp &= ~FDI_LINK_TRAIN_NONE;
3614 temp |= FDI_LINK_TRAIN_PATTERN_2;
3615 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003616 I915_WRITE(reg, temp);
3617
3618 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003619 udelay(150);
3620
Akshay Joshi0206e352011-08-16 15:34:10 -04003621 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003622 reg = FDI_TX_CTL(pipe);
3623 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3625 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003626 I915_WRITE(reg, temp);
3627
3628 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003629 udelay(500);
3630
Sean Paulfa37d392012-03-02 12:53:39 -05003631 for (retry = 0; retry < 5; retry++) {
3632 reg = FDI_RX_IIR(pipe);
3633 temp = I915_READ(reg);
3634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3635 if (temp & FDI_RX_SYMBOL_LOCK) {
3636 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3637 DRM_DEBUG_KMS("FDI train 2 done.\n");
3638 break;
3639 }
3640 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003641 }
Sean Paulfa37d392012-03-02 12:53:39 -05003642 if (retry < 5)
3643 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003644 }
3645 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003646 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003647
3648 DRM_DEBUG_KMS("FDI train done.\n");
3649}
3650
Jesse Barnes357555c2011-04-28 15:09:55 -07003651/* Manual link training for Ivy Bridge A0 parts */
3652static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3653{
3654 struct drm_device *dev = crtc->dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003658 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003659
3660 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3661 for train result */
3662 reg = FDI_RX_IMR(pipe);
3663 temp = I915_READ(reg);
3664 temp &= ~FDI_RX_SYMBOL_LOCK;
3665 temp &= ~FDI_RX_BIT_LOCK;
3666 I915_WRITE(reg, temp);
3667
3668 POSTING_READ(reg);
3669 udelay(150);
3670
Daniel Vetter01a415f2012-10-27 15:58:40 +02003671 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3672 I915_READ(FDI_RX_IIR(pipe)));
3673
Jesse Barnes139ccd32013-08-19 11:04:55 -07003674 /* Try each vswing and preemphasis setting twice before moving on */
3675 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3676 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003679 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3680 temp &= ~FDI_TX_ENABLE;
3681 I915_WRITE(reg, temp);
3682
3683 reg = FDI_RX_CTL(pipe);
3684 temp = I915_READ(reg);
3685 temp &= ~FDI_LINK_TRAIN_AUTO;
3686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3687 temp &= ~FDI_RX_ENABLE;
3688 I915_WRITE(reg, temp);
3689
3690 /* enable CPU FDI TX and PCH FDI RX */
3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003697 temp |= snb_b_fdi_train_param[j/2];
3698 temp |= FDI_COMPOSITE_SYNC;
3699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3700
3701 I915_WRITE(FDI_RX_MISC(pipe),
3702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3703
3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3707 temp |= FDI_COMPOSITE_SYNC;
3708 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3709
3710 POSTING_READ(reg);
3711 udelay(1); /* should be 0.5us */
3712
3713 for (i = 0; i < 4; i++) {
3714 reg = FDI_RX_IIR(pipe);
3715 temp = I915_READ(reg);
3716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3717
3718 if (temp & FDI_RX_BIT_LOCK ||
3719 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3720 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3721 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3722 i);
3723 break;
3724 }
3725 udelay(1); /* should be 0.5us */
3726 }
3727 if (i == 4) {
3728 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3729 continue;
3730 }
3731
3732 /* Train 2 */
3733 reg = FDI_TX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3736 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3737 I915_WRITE(reg, temp);
3738
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3742 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003743 I915_WRITE(reg, temp);
3744
3745 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003746 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003747
Jesse Barnes139ccd32013-08-19 11:04:55 -07003748 for (i = 0; i < 4; i++) {
3749 reg = FDI_RX_IIR(pipe);
3750 temp = I915_READ(reg);
3751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003752
Jesse Barnes139ccd32013-08-19 11:04:55 -07003753 if (temp & FDI_RX_SYMBOL_LOCK ||
3754 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3755 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3756 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3757 i);
3758 goto train_done;
3759 }
3760 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003761 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003762 if (i == 4)
3763 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003764 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003765
Jesse Barnes139ccd32013-08-19 11:04:55 -07003766train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003767 DRM_DEBUG_KMS("FDI train done.\n");
3768}
3769
Daniel Vetter88cefb62012-08-12 19:27:14 +02003770static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003771{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003772 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003773 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003774 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003775 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003776
Jesse Barnesc64e3112010-09-10 11:27:03 -07003777
Jesse Barnes0e23b992010-09-10 11:10:00 -07003778 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003781 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003782 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003783 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003784 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3785
3786 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003787 udelay(200);
3788
3789 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp | FDI_PCDCLK);
3792
3793 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003794 udelay(200);
3795
Paulo Zanoni20749732012-11-23 15:30:38 -02003796 /* Enable CPU FDI TX PLL, always on for Ironlake */
3797 reg = FDI_TX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3800 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003801
Paulo Zanoni20749732012-11-23 15:30:38 -02003802 POSTING_READ(reg);
3803 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003804 }
3805}
3806
Daniel Vetter88cefb62012-08-12 19:27:14 +02003807static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3808{
3809 struct drm_device *dev = intel_crtc->base.dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 int pipe = intel_crtc->pipe;
3812 u32 reg, temp;
3813
3814 /* Switch from PCDclk to Rawclk */
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3818
3819 /* Disable CPU FDI TX PLL */
3820 reg = FDI_TX_CTL(pipe);
3821 temp = I915_READ(reg);
3822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826
3827 reg = FDI_RX_CTL(pipe);
3828 temp = I915_READ(reg);
3829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3830
3831 /* Wait for the clocks to turn off. */
3832 POSTING_READ(reg);
3833 udelay(100);
3834}
3835
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003836static void ironlake_fdi_disable(struct drm_crtc *crtc)
3837{
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841 int pipe = intel_crtc->pipe;
3842 u32 reg, temp;
3843
3844 /* disable CPU FDI tx and PCH FDI rx */
3845 reg = FDI_TX_CTL(pipe);
3846 temp = I915_READ(reg);
3847 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3848 POSTING_READ(reg);
3849
3850 reg = FDI_RX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003854 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858
3859 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003860 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003861 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003862
3863 /* still set train pattern 1 */
3864 reg = FDI_TX_CTL(pipe);
3865 temp = I915_READ(reg);
3866 temp &= ~FDI_LINK_TRAIN_NONE;
3867 temp |= FDI_LINK_TRAIN_PATTERN_1;
3868 I915_WRITE(reg, temp);
3869
3870 reg = FDI_RX_CTL(pipe);
3871 temp = I915_READ(reg);
3872 if (HAS_PCH_CPT(dev)) {
3873 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3874 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3875 } else {
3876 temp &= ~FDI_LINK_TRAIN_NONE;
3877 temp |= FDI_LINK_TRAIN_PATTERN_1;
3878 }
3879 /* BPC in FDI rx is consistent with that in PIPECONF */
3880 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003881 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003882 I915_WRITE(reg, temp);
3883
3884 POSTING_READ(reg);
3885 udelay(100);
3886}
3887
Chris Wilson5dce5b932014-01-20 10:17:36 +00003888bool intel_has_pending_fb_unpin(struct drm_device *dev)
3889{
3890 struct intel_crtc *crtc;
3891
3892 /* Note that we don't need to be called with mode_config.lock here
3893 * as our list of CRTC objects is static for the lifetime of the
3894 * device and so cannot disappear as we iterate. Similarly, we can
3895 * happily treat the predicates as racy, atomic checks as userspace
3896 * cannot claim and pin a new fb without at least acquring the
3897 * struct_mutex and so serialising with us.
3898 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003899 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003900 if (atomic_read(&crtc->unpin_work_count) == 0)
3901 continue;
3902
3903 if (crtc->unpin_work)
3904 intel_wait_for_vblank(dev, crtc->pipe);
3905
3906 return true;
3907 }
3908
3909 return false;
3910}
3911
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003912static void page_flip_completed(struct intel_crtc *intel_crtc)
3913{
3914 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3915 struct intel_unpin_work *work = intel_crtc->unpin_work;
3916
3917 /* ensure that the unpin work is consistent wrt ->pending. */
3918 smp_rmb();
3919 intel_crtc->unpin_work = NULL;
3920
3921 if (work->event)
3922 drm_send_vblank_event(intel_crtc->base.dev,
3923 intel_crtc->pipe,
3924 work->event);
3925
3926 drm_crtc_vblank_put(&intel_crtc->base);
3927
3928 wake_up_all(&dev_priv->pending_flip_queue);
3929 queue_work(dev_priv->wq, &work->work);
3930
3931 trace_i915_flip_complete(intel_crtc->plane,
3932 work->pending_flip_obj);
3933}
3934
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003935void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003936{
Chris Wilson0f911282012-04-17 10:05:38 +01003937 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003938 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003939
Daniel Vetter2c10d572012-12-20 21:24:07 +01003940 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Chris Wilson9c787942014-09-05 07:13:25 +01003941 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3942 !intel_crtc_has_pending_flip(crtc),
3943 60*HZ) == 0)) {
3944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter2c10d572012-12-20 21:24:07 +01003945
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003946 spin_lock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003947 if (intel_crtc->unpin_work) {
3948 WARN_ONCE(1, "Removing stuck page flip\n");
3949 page_flip_completed(intel_crtc);
3950 }
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003951 spin_unlock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003952 }
Chris Wilson5bb61642012-09-27 21:25:58 +01003953
Chris Wilson975d5682014-08-20 13:13:34 +01003954 if (crtc->primary->fb) {
3955 mutex_lock(&dev->struct_mutex);
3956 intel_finish_fb(crtc->primary->fb);
3957 mutex_unlock(&dev->struct_mutex);
3958 }
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003959}
3960
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003961/* Program iCLKIP clock to the desired frequency */
3962static void lpt_program_iclkip(struct drm_crtc *crtc)
3963{
3964 struct drm_device *dev = crtc->dev;
3965 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003966 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003967 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3968 u32 temp;
3969
Daniel Vetter09153002012-12-12 14:06:44 +01003970 mutex_lock(&dev_priv->dpio_lock);
3971
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003972 /* It is necessary to ungate the pixclk gate prior to programming
3973 * the divisors, and gate it back when it is done.
3974 */
3975 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3976
3977 /* Disable SSCCTL */
3978 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003979 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3980 SBI_SSCCTL_DISABLE,
3981 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003982
3983 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003984 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003985 auxdiv = 1;
3986 divsel = 0x41;
3987 phaseinc = 0x20;
3988 } else {
3989 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003990 * but the adjusted_mode->crtc_clock in in KHz. To get the
3991 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003992 * convert the virtual clock precision to KHz here for higher
3993 * precision.
3994 */
3995 u32 iclk_virtual_root_freq = 172800 * 1000;
3996 u32 iclk_pi_range = 64;
3997 u32 desired_divisor, msb_divisor_value, pi_value;
3998
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003999 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004000 msb_divisor_value = desired_divisor / iclk_pi_range;
4001 pi_value = desired_divisor % iclk_pi_range;
4002
4003 auxdiv = 0;
4004 divsel = msb_divisor_value - 2;
4005 phaseinc = pi_value;
4006 }
4007
4008 /* This should not happen with any sane values */
4009 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4010 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4011 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4012 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4013
4014 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03004015 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004016 auxdiv,
4017 divsel,
4018 phasedir,
4019 phaseinc);
4020
4021 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004022 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004023 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4024 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4025 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4026 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4027 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4028 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004029 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004030
4031 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004032 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004033 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4034 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004035 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004036
4037 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004038 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004039 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004040 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004041
4042 /* Wait for initialization time */
4043 udelay(24);
4044
4045 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01004046
4047 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004048}
4049
Daniel Vetter275f01b22013-05-03 11:49:47 +02004050static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4051 enum pipe pch_transcoder)
4052{
4053 struct drm_device *dev = crtc->base.dev;
4054 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Daniel Vetter275f01b22013-05-03 11:49:47 +02004056
4057 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4058 I915_READ(HTOTAL(cpu_transcoder)));
4059 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4060 I915_READ(HBLANK(cpu_transcoder)));
4061 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4062 I915_READ(HSYNC(cpu_transcoder)));
4063
4064 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4065 I915_READ(VTOTAL(cpu_transcoder)));
4066 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4067 I915_READ(VBLANK(cpu_transcoder)));
4068 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4069 I915_READ(VSYNC(cpu_transcoder)));
4070 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4071 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4072}
4073
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004074static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004075{
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 uint32_t temp;
4078
4079 temp = I915_READ(SOUTH_CHICKEN1);
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004080 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004081 return;
4082
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4084 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4085
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004086 temp &= ~FDI_BC_BIFURCATION_SELECT;
4087 if (enable)
4088 temp |= FDI_BC_BIFURCATION_SELECT;
4089
4090 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004091 I915_WRITE(SOUTH_CHICKEN1, temp);
4092 POSTING_READ(SOUTH_CHICKEN1);
4093}
4094
4095static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4096{
4097 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004098
4099 switch (intel_crtc->pipe) {
4100 case PIPE_A:
4101 break;
4102 case PIPE_B:
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004103 if (intel_crtc->config->fdi_lanes > 2)
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004104 cpt_set_fdi_bc_bifurcation(dev, false);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004105 else
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004106 cpt_set_fdi_bc_bifurcation(dev, true);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004107
4108 break;
4109 case PIPE_C:
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004110 cpt_set_fdi_bc_bifurcation(dev, true);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004111
4112 break;
4113 default:
4114 BUG();
4115 }
4116}
4117
Jesse Barnesf67a5592011-01-05 10:31:48 -08004118/*
4119 * Enable PCH resources required for PCH ports:
4120 * - PCH PLLs
4121 * - FDI training & RX/TX
4122 * - update transcoder timings
4123 * - DP transcoding bits
4124 * - transcoder
4125 */
4126static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004127{
4128 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004129 struct drm_i915_private *dev_priv = dev->dev_private;
4130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004132 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004133
Daniel Vetterab9412b2013-05-03 11:49:46 +02004134 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01004135
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004136 if (IS_IVYBRIDGE(dev))
4137 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4138
Daniel Vettercd986ab2012-10-26 10:58:12 +02004139 /* Write the TU size bits before fdi link training, so that error
4140 * detection works. */
4141 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4142 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4143
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004144 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07004145 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004146
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004147 /* We need to program the right clock selection before writing the pixel
4148 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02004149 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004150 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004151
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004152 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004153 temp |= TRANS_DPLL_ENABLE(pipe);
4154 sel = TRANS_DPLLB_SEL(pipe);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004155 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004156 temp |= sel;
4157 else
4158 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004159 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004160 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004161
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004162 /* XXX: pch pll's can be enabled any time before we enable the PCH
4163 * transcoder, and we actually should do this to not upset any PCH
4164 * transcoder that already use the clock when we share it.
4165 *
4166 * Note that enable_shared_dpll tries to do the right thing, but
4167 * get_shared_dpll unconditionally resets the pll - we need that to have
4168 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02004169 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004170
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08004171 /* set transcoder timing, panel must allow it */
4172 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02004173 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004174
Paulo Zanoni303b81e2012-10-31 18:12:23 -02004175 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08004176
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004177 /* For PCH DP, enable TRANS_DP_CTL */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004178 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004179 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01004180 reg = TRANS_DP_CTL(pipe);
4181 temp = I915_READ(reg);
4182 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08004183 TRANS_DP_SYNC_MASK |
4184 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01004185 temp |= (TRANS_DP_OUTPUT_ENABLE |
4186 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07004187 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004188
4189 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01004190 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004191 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01004192 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004193
4194 switch (intel_trans_dp_port_sel(crtc)) {
4195 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01004196 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004197 break;
4198 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01004199 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004200 break;
4201 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01004202 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004203 break;
4204 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02004205 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004206 }
4207
Chris Wilson5eddb702010-09-11 13:48:45 +01004208 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004209 }
4210
Paulo Zanonib8a4f402012-10-31 18:12:42 -02004211 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004212}
4213
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004214static void lpt_pch_enable(struct drm_crtc *crtc)
4215{
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004219 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004220
Daniel Vetterab9412b2013-05-03 11:49:46 +02004221 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004222
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02004223 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004224
Paulo Zanoni0540e482012-10-31 18:12:40 -02004225 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02004226 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004227
Paulo Zanoni937bb612012-10-31 18:12:47 -02004228 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004229}
4230
Daniel Vetter716c2e52014-06-25 22:02:02 +03004231void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004232{
Daniel Vettere2b78262013-06-07 23:10:03 +02004233 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004234
4235 if (pll == NULL)
4236 return;
4237
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02004238 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02004239 WARN(1, "bad %s crtc mask\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004240 return;
4241 }
4242
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02004243 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4244 if (pll->config.crtc_mask == 0) {
Daniel Vetterf4a091c2013-06-10 17:28:22 +02004245 WARN_ON(pll->on);
4246 WARN_ON(pll->active);
4247 }
4248
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004249 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004250}
4251
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004252struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4253 struct intel_crtc_state *crtc_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004254{
Daniel Vettere2b78262013-06-07 23:10:03 +02004255 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004256 struct intel_shared_dpll *pll;
Daniel Vettere2b78262013-06-07 23:10:03 +02004257 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004258
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004259 if (HAS_PCH_IBX(dev_priv->dev)) {
4260 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02004261 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004262 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004263
Daniel Vetter46edb022013-06-05 13:34:12 +02004264 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4265 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004266
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004267 WARN_ON(pll->new_config->crtc_mask);
Daniel Vetterf2a69f42014-05-20 15:19:19 +02004268
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004269 goto found;
4270 }
4271
Satheeshakrishna Mbcddf6102014-08-22 09:49:10 +05304272 if (IS_BROXTON(dev_priv->dev)) {
4273 /* PLL is attached to port in bxt */
4274 struct intel_encoder *encoder;
4275 struct intel_digital_port *intel_dig_port;
4276
4277 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4278 if (WARN_ON(!encoder))
4279 return NULL;
4280
4281 intel_dig_port = enc_to_dig_port(&encoder->base);
4282 /* 1:1 mapping between ports and PLLs */
4283 i = (enum intel_dpll_id)intel_dig_port->port;
4284 pll = &dev_priv->shared_dplls[i];
4285 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4286 crtc->base.base.id, pll->name);
4287 WARN_ON(pll->new_config->crtc_mask);
4288
4289 goto found;
4290 }
4291
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004292 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4293 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004294
4295 /* Only want to check enabled timings first */
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004296 if (pll->new_config->crtc_mask == 0)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004297 continue;
4298
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004299 if (memcmp(&crtc_state->dpll_hw_state,
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004300 &pll->new_config->hw_state,
4301 sizeof(pll->new_config->hw_state)) == 0) {
4302 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02004303 crtc->base.base.id, pll->name,
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004304 pll->new_config->crtc_mask,
4305 pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004306 goto found;
4307 }
4308 }
4309
4310 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004311 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4312 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004313 if (pll->new_config->crtc_mask == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02004314 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4315 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004316 goto found;
4317 }
4318 }
4319
4320 return NULL;
4321
4322found:
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004323 if (pll->new_config->crtc_mask == 0)
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004324 pll->new_config->hw_state = crtc_state->dpll_hw_state;
Daniel Vetterf2a69f42014-05-20 15:19:19 +02004325
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004326 crtc_state->shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02004327 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4328 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02004329
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004330 pll->new_config->crtc_mask |= 1 << crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004331
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004332 return pll;
4333}
4334
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004335/**
4336 * intel_shared_dpll_start_config - start a new PLL staged config
4337 * @dev_priv: DRM device
4338 * @clear_pipes: mask of pipes that will have their PLLs freed
4339 *
4340 * Starts a new PLL staged config, copying the current config but
4341 * releasing the references of pipes specified in clear_pipes.
4342 */
4343static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4344 unsigned clear_pipes)
4345{
4346 struct intel_shared_dpll *pll;
4347 enum intel_dpll_id i;
4348
4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
4351
4352 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4353 GFP_KERNEL);
4354 if (!pll->new_config)
4355 goto cleanup;
4356
4357 pll->new_config->crtc_mask &= ~clear_pipes;
4358 }
4359
4360 return 0;
4361
4362cleanup:
4363 while (--i >= 0) {
4364 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveiraf354d732014-11-07 14:07:41 +02004365 kfree(pll->new_config);
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004366 pll->new_config = NULL;
4367 }
4368
4369 return -ENOMEM;
4370}
4371
4372static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4373{
4374 struct intel_shared_dpll *pll;
4375 enum intel_dpll_id i;
4376
4377 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4378 pll = &dev_priv->shared_dplls[i];
4379
4380 WARN_ON(pll->new_config == &pll->config);
4381
4382 pll->config = *pll->new_config;
4383 kfree(pll->new_config);
4384 pll->new_config = NULL;
4385 }
4386}
4387
4388static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4389{
4390 struct intel_shared_dpll *pll;
4391 enum intel_dpll_id i;
4392
4393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4394 pll = &dev_priv->shared_dplls[i];
4395
4396 WARN_ON(pll->new_config == &pll->config);
4397
4398 kfree(pll->new_config);
4399 pll->new_config = NULL;
4400 }
4401}
4402
Daniel Vettera1520312013-05-03 11:49:50 +02004403static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07004404{
4405 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01004406 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07004407 u32 temp;
4408
4409 temp = I915_READ(dslreg);
4410 udelay(500);
4411 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07004412 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03004413 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07004414 }
4415}
4416
Chandra Kondurua1b22782015-04-07 15:28:45 -07004417/**
4418 * skl_update_scaler_users - Stages update to crtc's scaler state
4419 * @intel_crtc: crtc
4420 * @crtc_state: crtc_state
4421 * @plane: plane (NULL indicates crtc is requesting update)
4422 * @plane_state: plane's state
4423 * @force_detach: request unconditional detachment of scaler
4424 *
4425 * This function updates scaler state for requested plane or crtc.
4426 * To request scaler usage update for a plane, caller shall pass plane pointer.
4427 * To request scaler usage update for crtc, caller shall pass plane pointer
4428 * as NULL.
4429 *
4430 * Return
4431 * 0 - scaler_usage updated successfully
4432 * error - requested scaling cannot be supported or other error condition
4433 */
4434int
4435skl_update_scaler_users(
4436 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4437 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4438 int force_detach)
4439{
4440 int need_scaling;
4441 int idx;
4442 int src_w, src_h, dst_w, dst_h;
4443 int *scaler_id;
4444 struct drm_framebuffer *fb;
4445 struct intel_crtc_scaler_state *scaler_state;
Chandra Konduru6156a452015-04-27 13:48:39 -07004446 unsigned int rotation;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004447
4448 if (!intel_crtc || !crtc_state)
4449 return 0;
4450
4451 scaler_state = &crtc_state->scaler_state;
4452
4453 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4454 fb = intel_plane ? plane_state->base.fb : NULL;
4455
4456 if (intel_plane) {
4457 src_w = drm_rect_width(&plane_state->src) >> 16;
4458 src_h = drm_rect_height(&plane_state->src) >> 16;
4459 dst_w = drm_rect_width(&plane_state->dst);
4460 dst_h = drm_rect_height(&plane_state->dst);
4461 scaler_id = &plane_state->scaler_id;
Chandra Konduru6156a452015-04-27 13:48:39 -07004462 rotation = plane_state->base.rotation;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004463 } else {
4464 struct drm_display_mode *adjusted_mode =
4465 &crtc_state->base.adjusted_mode;
4466 src_w = crtc_state->pipe_src_w;
4467 src_h = crtc_state->pipe_src_h;
4468 dst_w = adjusted_mode->hdisplay;
4469 dst_h = adjusted_mode->vdisplay;
4470 scaler_id = &scaler_state->scaler_id;
Chandra Konduru6156a452015-04-27 13:48:39 -07004471 rotation = DRM_ROTATE_0;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004472 }
Chandra Konduru6156a452015-04-27 13:48:39 -07004473
4474 need_scaling = intel_rotation_90_or_270(rotation) ?
4475 (src_h != dst_w || src_w != dst_h):
4476 (src_w != dst_w || src_h != dst_h);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004477
4478 /*
4479 * if plane is being disabled or scaler is no more required or force detach
4480 * - free scaler binded to this plane/crtc
4481 * - in order to do this, update crtc->scaler_usage
4482 *
4483 * Here scaler state in crtc_state is set free so that
4484 * scaler can be assigned to other user. Actual register
4485 * update to free the scaler is done in plane/panel-fit programming.
4486 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4487 */
4488 if (force_detach || !need_scaling || (intel_plane &&
4489 (!fb || !plane_state->visible))) {
4490 if (*scaler_id >= 0) {
4491 scaler_state->scaler_users &= ~(1 << idx);
4492 scaler_state->scalers[*scaler_id].in_use = 0;
4493
4494 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4495 "crtc_state = %p scaler_users = 0x%x\n",
4496 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4497 intel_plane ? intel_plane->base.base.id :
4498 intel_crtc->base.base.id, crtc_state,
4499 scaler_state->scaler_users);
4500 *scaler_id = -1;
4501 }
4502 return 0;
4503 }
4504
4505 /* range checks */
4506 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4507 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4508
4509 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4510 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4511 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4512 "size is out of scaler range\n",
4513 intel_plane ? "PLANE" : "CRTC",
4514 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4515 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4516 return -EINVAL;
4517 }
4518
4519 /* check colorkey */
4520 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4521 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4522 intel_plane->base.base.id);
4523 return -EINVAL;
4524 }
4525
4526 /* Check src format */
4527 if (intel_plane) {
4528 switch (fb->pixel_format) {
4529 case DRM_FORMAT_RGB565:
4530 case DRM_FORMAT_XBGR8888:
4531 case DRM_FORMAT_XRGB8888:
4532 case DRM_FORMAT_ABGR8888:
4533 case DRM_FORMAT_ARGB8888:
4534 case DRM_FORMAT_XRGB2101010:
4535 case DRM_FORMAT_ARGB2101010:
4536 case DRM_FORMAT_XBGR2101010:
4537 case DRM_FORMAT_ABGR2101010:
4538 case DRM_FORMAT_YUYV:
4539 case DRM_FORMAT_YVYU:
4540 case DRM_FORMAT_UYVY:
4541 case DRM_FORMAT_VYUY:
4542 break;
4543 default:
4544 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4545 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4546 return -EINVAL;
4547 }
4548 }
4549
4550 /* mark this plane as a scaler user in crtc_state */
4551 scaler_state->scaler_users |= (1 << idx);
4552 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4553 "crtc_state = %p scaler_users = 0x%x\n",
4554 intel_plane ? "PLANE" : "CRTC",
4555 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4556 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4557 return 0;
4558}
4559
4560static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004561{
4562 struct drm_device *dev = crtc->base.dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 int pipe = crtc->pipe;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004565 struct intel_crtc_scaler_state *scaler_state =
4566 &crtc->config->scaler_state;
4567
4568 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4569
4570 /* To update pfit, first update scaler state */
4571 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4572 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4573 skl_detach_scalers(crtc);
4574 if (!enable)
4575 return;
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004576
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004577 if (crtc->config->pch_pfit.enabled) {
Chandra Kondurua1b22782015-04-07 15:28:45 -07004578 int id;
4579
4580 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4581 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4582 return;
4583 }
4584
4585 id = scaler_state->scaler_id;
4586 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4587 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4588 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4589 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4590
4591 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004592 }
4593}
4594
Jesse Barnesb074cec2013-04-25 12:55:02 -07004595static void ironlake_pfit_enable(struct intel_crtc *crtc)
4596{
4597 struct drm_device *dev = crtc->base.dev;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 int pipe = crtc->pipe;
4600
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004601 if (crtc->config->pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07004602 /* Force use of hard-coded filter coefficients
4603 * as some pre-programmed values are broken,
4604 * e.g. x201.
4605 */
4606 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4607 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4608 PF_PIPE_SEL_IVB(pipe));
4609 else
4610 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004611 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4612 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08004613 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004614}
4615
Matt Roper4a3b8762014-12-23 10:41:51 -08004616static void intel_enable_sprite_planes(struct drm_crtc *crtc)
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004617{
4618 struct drm_device *dev = crtc->dev;
4619 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004620 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004621 struct intel_plane *intel_plane;
4622
Matt Roperaf2b6532014-04-01 15:22:32 -07004623 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4624 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004625 if (intel_plane->pipe == pipe)
4626 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004627 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004628}
4629
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004630void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004631{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004632 struct drm_device *dev = crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03004634
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004635 if (!crtc->config->ips_enabled)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004636 return;
4637
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004638 /* We can only enable IPS after we enable a plane and wait for a vblank */
4639 intel_wait_for_vblank(dev, crtc->pipe);
4640
Paulo Zanonid77e4532013-09-24 13:52:55 -03004641 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004642 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
4646 /* Quoting Art Runyan: "its not safe to expect any particular
4647 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08004648 * mailbox." Moreover, the mailbox may return a bogus state,
4649 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004650 */
4651 } else {
4652 I915_WRITE(IPS_CTL, IPS_ENABLE);
4653 /* The bit only becomes 1 in the next vblank, so this wait here
4654 * is essentially intel_wait_for_vblank. If we don't have this
4655 * and don't wait for vblanks until the end of crtc_enable, then
4656 * the HW state readout code will complain that the expected
4657 * IPS_CTL value is not the one we read. */
4658 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4659 DRM_ERROR("Timed out waiting for IPS enable\n");
4660 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004661}
4662
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004663void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004664{
4665 struct drm_device *dev = crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004668 if (!crtc->config->ips_enabled)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004669 return;
4670
4671 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004672 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004673 mutex_lock(&dev_priv->rps.hw_lock);
4674 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4675 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004676 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4677 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4678 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08004679 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004680 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08004681 POSTING_READ(IPS_CTL);
4682 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004683
4684 /* We need to wait for a vblank before we can disable the plane. */
4685 intel_wait_for_vblank(dev, crtc->pipe);
4686}
4687
4688/** Loads the palette/gamma unit for the CRTC with the prepared values */
4689static void intel_crtc_load_lut(struct drm_crtc *crtc)
4690{
4691 struct drm_device *dev = crtc->dev;
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4694 enum pipe pipe = intel_crtc->pipe;
4695 int palreg = PALETTE(pipe);
4696 int i;
4697 bool reenable_ips = false;
4698
4699 /* The clocks have to be on to load the palette. */
Matt Roper83d65732015-02-25 13:12:16 -08004700 if (!crtc->state->enable || !intel_crtc->active)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004701 return;
4702
Imre Deak50360402015-01-16 00:55:16 -08004703 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004704 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004705 assert_dsi_pll_enabled(dev_priv);
4706 else
4707 assert_pll_enabled(dev_priv, pipe);
4708 }
4709
4710 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05304711 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004712 palreg = LGC_PALETTE(pipe);
4713
4714 /* Workaround : Do not read or write the pipe palette/gamma data while
4715 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4716 */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004717 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03004718 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4719 GAMMA_MODE_MODE_SPLIT)) {
4720 hsw_disable_ips(intel_crtc);
4721 reenable_ips = true;
4722 }
4723
4724 for (i = 0; i < 256; i++) {
4725 I915_WRITE(palreg + 4 * i,
4726 (intel_crtc->lut_r[i] << 16) |
4727 (intel_crtc->lut_g[i] << 8) |
4728 intel_crtc->lut_b[i]);
4729 }
4730
4731 if (reenable_ips)
4732 hsw_enable_ips(intel_crtc);
4733}
4734
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004735static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004736{
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004737 if (intel_crtc->overlay) {
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004738 struct drm_device *dev = intel_crtc->base.dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740
4741 mutex_lock(&dev->struct_mutex);
4742 dev_priv->mm.interruptible = false;
4743 (void) intel_overlay_switch_off(intel_crtc->overlay);
4744 dev_priv->mm.interruptible = true;
4745 mutex_unlock(&dev->struct_mutex);
4746 }
4747
4748 /* Let userspace switch the overlay on again. In most cases userspace
4749 * has to recompute where to put it anyway.
4750 */
4751}
4752
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004753/**
4754 * intel_post_enable_primary - Perform operations after enabling primary plane
4755 * @crtc: the CRTC whose primary plane was just enabled
4756 *
4757 * Performs potentially sleeping operations that must be done after the primary
4758 * plane is enabled, such as updating FBC and IPS. Note that this may be
4759 * called due to an explicit primary plane update, or due to an implicit
4760 * re-enable that is caused when a sprite plane is updated to no longer
4761 * completely hide the primary plane.
4762 */
4763static void
4764intel_post_enable_primary(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004765{
4766 struct drm_device *dev = crtc->dev;
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004767 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004770
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004771 /*
4772 * BDW signals flip done immediately if the plane
4773 * is disabled, even if the plane enable is already
4774 * armed to occur at the next vblank :(
4775 */
4776 if (IS_BROADWELL(dev))
4777 intel_wait_for_vblank(dev, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004778
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004779 /*
4780 * FIXME IPS should be fine as long as one plane is
4781 * enabled, but in practice it seems to have problems
4782 * when going from primary only to sprite only and vice
4783 * versa.
4784 */
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004785 hsw_enable_ips(intel_crtc);
4786
4787 mutex_lock(&dev->struct_mutex);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02004788 intel_fbc_update(dev);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004789 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02004790
4791 /*
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004792 * Gen2 reports pipe underruns whenever all planes are disabled.
4793 * So don't enable underrun reporting before at least some planes
4794 * are enabled.
4795 * FIXME: Need to fix the logic to work when we turn off all planes
4796 * but leave the pipe running.
Daniel Vetterf99d7062014-06-19 16:01:59 +02004797 */
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004798 if (IS_GEN2(dev))
4799 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4800
4801 /* Underruns don't raise interrupts, so check manually. */
4802 if (HAS_GMCH_DISPLAY(dev))
4803 i9xx_check_fifo_underruns(dev_priv);
4804}
4805
4806/**
4807 * intel_pre_disable_primary - Perform operations before disabling primary plane
4808 * @crtc: the CRTC whose primary plane is to be disabled
4809 *
4810 * Performs potentially sleeping operations that must be done before the
4811 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4812 * be called due to an explicit primary plane update, or due to an implicit
4813 * disable that is caused when a sprite plane completely hides the primary
4814 * plane.
4815 */
4816static void
4817intel_pre_disable_primary(struct drm_crtc *crtc)
4818{
4819 struct drm_device *dev = crtc->dev;
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822 int pipe = intel_crtc->pipe;
4823
4824 /*
4825 * Gen2 reports pipe underruns whenever all planes are disabled.
4826 * So diasble underrun reporting before all the planes get disabled.
4827 * FIXME: Need to fix the logic to work when we turn off all planes
4828 * but leave the pipe running.
4829 */
4830 if (IS_GEN2(dev))
4831 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4832
4833 /*
4834 * Vblank time updates from the shadow to live plane control register
4835 * are blocked if the memory self-refresh mode is active at that
4836 * moment. So to make sure the plane gets truly disabled, disable
4837 * first the self-refresh mode. The self-refresh enable bit in turn
4838 * will be checked/applied by the HW only at the next frame start
4839 * event which is after the vblank start event, so we need to have a
4840 * wait-for-vblank between disabling the plane and the pipe.
4841 */
4842 if (HAS_GMCH_DISPLAY(dev))
4843 intel_set_memory_cxsr(dev_priv, false);
4844
4845 mutex_lock(&dev->struct_mutex);
4846 if (dev_priv->fbc.crtc == intel_crtc)
4847 intel_fbc_disable(dev);
4848 mutex_unlock(&dev->struct_mutex);
4849
4850 /*
4851 * FIXME IPS should be fine as long as one plane is
4852 * enabled, but in practice it seems to have problems
4853 * when going from primary only to sprite only and vice
4854 * versa.
4855 */
4856 hsw_disable_ips(intel_crtc);
4857}
4858
4859static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4860{
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004861 intel_enable_primary_hw_plane(crtc->primary, crtc);
4862 intel_enable_sprite_planes(crtc);
4863 intel_crtc_update_cursor(crtc, true);
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004864
4865 intel_post_enable_primary(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004866}
4867
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004868static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004869{
4870 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorst27321ae2015-04-21 17:12:52 +03004872 struct intel_plane *intel_plane;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004873 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004874
4875 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004876
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004877 intel_pre_disable_primary(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004878
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004879 intel_crtc_dpms_overlay_disable(intel_crtc);
Maarten Lankhorst27321ae2015-04-21 17:12:52 +03004880 for_each_intel_plane(dev, intel_plane) {
4881 if (intel_plane->pipe == pipe) {
4882 struct drm_crtc *from = intel_plane->base.crtc;
4883
4884 intel_plane->disable_plane(&intel_plane->base,
4885 from ?: crtc, true);
4886 }
4887 }
Ville Syrjäläf98551a2014-05-22 17:48:06 +03004888
Daniel Vetterf99d7062014-06-19 16:01:59 +02004889 /*
4890 * FIXME: Once we grow proper nuclear flip support out of this we need
4891 * to compute the mask of flip planes precisely. For the time being
4892 * consider this a flip to a NULL plane.
4893 */
4894 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004895}
4896
Jesse Barnesf67a5592011-01-05 10:31:48 -08004897static void ironlake_crtc_enable(struct drm_crtc *crtc)
4898{
4899 struct drm_device *dev = crtc->dev;
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004902 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004903 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004904
Matt Roper83d65732015-02-25 13:12:16 -08004905 WARN_ON(!crtc->state->enable);
Daniel Vetter08a48462012-07-02 11:43:47 +02004906
Jesse Barnesf67a5592011-01-05 10:31:48 -08004907 if (intel_crtc->active)
4908 return;
4909
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004910 if (intel_crtc->config->has_pch_encoder)
Daniel Vetterb14b1052014-04-24 23:55:13 +02004911 intel_prepare_shared_dpll(intel_crtc);
4912
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004913 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd482015-02-13 15:32:59 +05304914 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004915
4916 intel_set_pipe_timings(intel_crtc);
4917
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004918 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetter29407aa2014-04-24 23:55:08 +02004919 intel_cpu_transcoder_set_m_n(intel_crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004920 &intel_crtc->config->fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004921 }
4922
4923 ironlake_set_pipeconf(crtc);
4924
Jesse Barnesf67a5592011-01-05 10:31:48 -08004925 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004926
Daniel Vettera72e4c92014-09-30 10:56:47 +02004927 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4928 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni86642812013-04-12 17:57:57 -03004929
Daniel Vetterf6736a12013-06-05 13:34:30 +02004930 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004931 if (encoder->pre_enable)
4932 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004933
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004934 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004935 /* Note: FDI PLL enabling _must_ be done before we enable the
4936 * cpu pipes, hence this is separate from all the other fdi/pch
4937 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004938 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004939 } else {
4940 assert_fdi_tx_disabled(dev_priv, pipe);
4941 assert_fdi_rx_disabled(dev_priv, pipe);
4942 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004943
Jesse Barnesb074cec2013-04-25 12:55:02 -07004944 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004945
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004946 /*
4947 * On ILK+ LUT must be loaded before the pipe is running but with
4948 * clocks enabled
4949 */
4950 intel_crtc_load_lut(crtc);
4951
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004952 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004953 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004954
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004955 if (intel_crtc->config->has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004956 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004957
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01004958 assert_vblank_disabled(crtc);
4959 drm_crtc_vblank_on(crtc);
4960
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004961 for_each_encoder_on_crtc(dev, crtc, encoder)
4962 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004963
4964 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004965 cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004966}
4967
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004968/* IPS only exists on ULT machines and is tied to pipe A. */
4969static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4970{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004971 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004972}
4973
Paulo Zanonie4916942013-09-20 16:21:19 -03004974/*
4975 * This implements the workaround described in the "notes" section of the mode
4976 * set sequence documentation. When going from no pipes or single pipe to
4977 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4978 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4979 */
4980static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4981{
4982 struct drm_device *dev = crtc->base.dev;
4983 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4984
4985 /* We want to get the other_active_crtc only if there's only 1 other
4986 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004987 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004988 if (!crtc_it->active || crtc_it == crtc)
4989 continue;
4990
4991 if (other_active_crtc)
4992 return;
4993
4994 other_active_crtc = crtc_it;
4995 }
4996 if (!other_active_crtc)
4997 return;
4998
4999 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5000 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5001}
5002
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005003static void haswell_crtc_enable(struct drm_crtc *crtc)
5004{
5005 struct drm_device *dev = crtc->dev;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5008 struct intel_encoder *encoder;
5009 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005010
Matt Roper83d65732015-02-25 13:12:16 -08005011 WARN_ON(!crtc->state->enable);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005012
5013 if (intel_crtc->active)
5014 return;
5015
Daniel Vetterdf8ad702014-06-25 22:02:03 +03005016 if (intel_crtc_to_shared_dpll(intel_crtc))
5017 intel_enable_shared_dpll(intel_crtc);
5018
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005019 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd482015-02-13 15:32:59 +05305020 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter229fca92014-04-24 23:55:09 +02005021
5022 intel_set_pipe_timings(intel_crtc);
5023
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005024 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5025 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5026 intel_crtc->config->pixel_multiplier - 1);
Clint Taylorebb69c92014-09-30 10:30:22 -07005027 }
5028
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005029 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetter229fca92014-04-24 23:55:09 +02005030 intel_cpu_transcoder_set_m_n(intel_crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005031 &intel_crtc->config->fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02005032 }
5033
5034 haswell_set_pipeconf(crtc);
5035
5036 intel_set_pipe_csc(crtc);
5037
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005038 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03005039
Daniel Vettera72e4c92014-09-30 10:56:47 +02005040 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005041 for_each_encoder_on_crtc(dev, crtc, encoder)
5042 if (encoder->pre_enable)
5043 encoder->pre_enable(encoder);
5044
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005045 if (intel_crtc->config->has_pch_encoder) {
Daniel Vettera72e4c92014-09-30 10:56:47 +02005046 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5047 true);
Imre Deak4fe94672014-06-25 22:01:49 +03005048 dev_priv->display.fdi_link_train(crtc);
5049 }
5050
Paulo Zanoni1f544382012-10-24 11:32:00 -02005051 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005052
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005053 if (INTEL_INFO(dev)->gen == 9)
Chandra Kondurua1b22782015-04-07 15:28:45 -07005054 skylake_pfit_update(intel_crtc, 1);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005055 else if (INTEL_INFO(dev)->gen < 9)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00005056 ironlake_pfit_enable(intel_crtc);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005057 else
5058 MISSING_CASE(INTEL_INFO(dev)->gen);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005059
5060 /*
5061 * On ILK+ LUT must be loaded before the pipe is running but with
5062 * clocks enabled
5063 */
5064 intel_crtc_load_lut(crtc);
5065
Paulo Zanoni1f544382012-10-24 11:32:00 -02005066 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00005067 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005068
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005069 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005070 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005071
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005072 if (intel_crtc->config->has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02005073 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005074
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005075 if (intel_crtc->config->dp_encoder_is_mst)
Dave Airlie0e32b392014-05-02 14:02:48 +10005076 intel_ddi_set_vc_payload_alloc(crtc, true);
5077
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005078 assert_vblank_disabled(crtc);
5079 drm_crtc_vblank_on(crtc);
5080
Jani Nikula8807e552013-08-30 19:40:32 +03005081 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005082 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03005083 intel_opregion_notify_encoder(encoder, true);
5084 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005085
Paulo Zanonie4916942013-09-20 16:21:19 -03005086 /* If we change the relative order between pipe/planes enabling, we need
5087 * to change the workaround. */
5088 haswell_mode_set_planes_workaround(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005089}
5090
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005091static void ironlake_pfit_disable(struct intel_crtc *crtc)
5092{
5093 struct drm_device *dev = crtc->base.dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 int pipe = crtc->pipe;
5096
5097 /* To avoid upsetting the power well on haswell only disable the pfit if
5098 * it's in use. The hw state code will make sure we get this right. */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005099 if (crtc->config->pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005100 I915_WRITE(PF_CTL(pipe), 0);
5101 I915_WRITE(PF_WIN_POS(pipe), 0);
5102 I915_WRITE(PF_WIN_SZ(pipe), 0);
5103 }
5104}
5105
Jesse Barnes6be4a602010-09-10 10:26:01 -07005106static void ironlake_crtc_disable(struct drm_crtc *crtc)
5107{
5108 struct drm_device *dev = crtc->dev;
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005111 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07005112 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01005113 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07005114
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005115 if (!intel_crtc->active)
5116 return;
5117
Daniel Vetterea9d7582012-07-10 10:42:52 +02005118 for_each_encoder_on_crtc(dev, crtc, encoder)
5119 encoder->disable(encoder);
5120
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005121 drm_crtc_vblank_off(crtc);
5122 assert_vblank_disabled(crtc);
5123
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005124 if (intel_crtc->config->has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02005125 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
Daniel Vetterd925c592013-06-05 13:34:04 +02005126
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005127 intel_disable_pipe(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005128
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005129 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005130
Daniel Vetterbf49ec82012-09-06 22:15:40 +02005131 for_each_encoder_on_crtc(dev, crtc, encoder)
5132 if (encoder->post_disable)
5133 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005134
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005135 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetterd925c592013-06-05 13:34:04 +02005136 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005137
Daniel Vetterd925c592013-06-05 13:34:04 +02005138 ironlake_disable_pch_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005139
Daniel Vetterd925c592013-06-05 13:34:04 +02005140 if (HAS_PCH_CPT(dev)) {
5141 /* disable TRANS_DP_CTL */
5142 reg = TRANS_DP_CTL(pipe);
5143 temp = I915_READ(reg);
5144 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5145 TRANS_DP_PORT_SEL_MASK);
5146 temp |= TRANS_DP_PORT_SEL_NONE;
5147 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005148
Daniel Vetterd925c592013-06-05 13:34:04 +02005149 /* disable DPLL_SEL */
5150 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02005151 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02005152 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005153 }
Daniel Vetterd925c592013-06-05 13:34:04 +02005154
5155 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02005156 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02005157
5158 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005159 }
5160
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005161 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03005162 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01005163
5164 mutex_lock(&dev->struct_mutex);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02005165 intel_fbc_update(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01005166 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005167}
5168
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005169static void haswell_crtc_disable(struct drm_crtc *crtc)
5170{
5171 struct drm_device *dev = crtc->dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5174 struct intel_encoder *encoder;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005175 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005176
5177 if (!intel_crtc->active)
5178 return;
5179
Jani Nikula8807e552013-08-30 19:40:32 +03005180 for_each_encoder_on_crtc(dev, crtc, encoder) {
5181 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005182 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03005183 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005184
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005185 drm_crtc_vblank_off(crtc);
5186 assert_vblank_disabled(crtc);
5187
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005188 if (intel_crtc->config->has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02005189 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5190 false);
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005191 intel_disable_pipe(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005192
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005193 if (intel_crtc->config->dp_encoder_is_mst)
Ville Syrjäläa4bf2142014-08-18 21:27:34 +03005194 intel_ddi_set_vc_payload_alloc(crtc, false);
5195
Paulo Zanoniad80a812012-10-24 16:06:19 -02005196 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005197
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005198 if (INTEL_INFO(dev)->gen == 9)
Chandra Kondurua1b22782015-04-07 15:28:45 -07005199 skylake_pfit_update(intel_crtc, 0);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005200 else if (INTEL_INFO(dev)->gen < 9)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00005201 ironlake_pfit_disable(intel_crtc);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005202 else
5203 MISSING_CASE(INTEL_INFO(dev)->gen);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005204
Paulo Zanoni1f544382012-10-24 11:32:00 -02005205 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005206
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005207 if (intel_crtc->config->has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02005208 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02005209 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02005210 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005211
Imre Deak97b040a2014-06-25 22:01:50 +03005212 for_each_encoder_on_crtc(dev, crtc, encoder)
5213 if (encoder->post_disable)
5214 encoder->post_disable(encoder);
5215
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005216 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03005217 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005218
5219 mutex_lock(&dev->struct_mutex);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02005220 intel_fbc_update(dev);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005221 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03005222
5223 if (intel_crtc_to_shared_dpll(intel_crtc))
5224 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005225}
5226
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005227static void ironlake_crtc_off(struct drm_crtc *crtc)
5228{
5229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02005230 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005231}
5232
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005233
Jesse Barnes2dd24552013-04-25 12:55:01 -07005234static void i9xx_pfit_enable(struct intel_crtc *crtc)
5235{
5236 struct drm_device *dev = crtc->base.dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005238 struct intel_crtc_state *pipe_config = crtc->config;
Jesse Barnes2dd24552013-04-25 12:55:01 -07005239
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02005240 if (!pipe_config->gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07005241 return;
5242
Daniel Vetterc0b03412013-05-28 12:05:54 +02005243 /*
5244 * The panel fitter should only be adjusted whilst the pipe is disabled,
5245 * according to register description and PRM.
5246 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07005247 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5248 assert_pipe_disabled(dev_priv, crtc->pipe);
5249
Jesse Barnesb074cec2013-04-25 12:55:02 -07005250 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5251 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02005252
5253 /* Border color in case we don't scale up to the full screen. Black by
5254 * default, change to something else for debugging. */
5255 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07005256}
5257
Dave Airlied05410f2014-06-05 13:22:59 +10005258static enum intel_display_power_domain port_to_power_domain(enum port port)
5259{
5260 switch (port) {
5261 case PORT_A:
5262 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5263 case PORT_B:
5264 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5265 case PORT_C:
5266 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5267 case PORT_D:
5268 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5269 default:
5270 WARN_ON_ONCE(1);
5271 return POWER_DOMAIN_PORT_OTHER;
5272 }
5273}
5274
Imre Deak77d22dc2014-03-05 16:20:52 +02005275#define for_each_power_domain(domain, mask) \
5276 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5277 if ((1 << (domain)) & (mask))
5278
Imre Deak319be8a2014-03-04 19:22:57 +02005279enum intel_display_power_domain
5280intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02005281{
Imre Deak319be8a2014-03-04 19:22:57 +02005282 struct drm_device *dev = intel_encoder->base.dev;
5283 struct intel_digital_port *intel_dig_port;
5284
5285 switch (intel_encoder->type) {
5286 case INTEL_OUTPUT_UNKNOWN:
5287 /* Only DDI platforms should ever use this output type */
5288 WARN_ON_ONCE(!HAS_DDI(dev));
5289 case INTEL_OUTPUT_DISPLAYPORT:
5290 case INTEL_OUTPUT_HDMI:
5291 case INTEL_OUTPUT_EDP:
5292 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10005293 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10005294 case INTEL_OUTPUT_DP_MST:
5295 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5296 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02005297 case INTEL_OUTPUT_ANALOG:
5298 return POWER_DOMAIN_PORT_CRT;
5299 case INTEL_OUTPUT_DSI:
5300 return POWER_DOMAIN_PORT_DSI;
5301 default:
5302 return POWER_DOMAIN_PORT_OTHER;
5303 }
5304}
5305
5306static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5307{
5308 struct drm_device *dev = crtc->dev;
5309 struct intel_encoder *intel_encoder;
5310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02005312 unsigned long mask;
5313 enum transcoder transcoder;
5314
5315 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5316
5317 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5318 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005319 if (intel_crtc->config->pch_pfit.enabled ||
5320 intel_crtc->config->pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02005321 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5322
Imre Deak319be8a2014-03-04 19:22:57 +02005323 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5324 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5325
Imre Deak77d22dc2014-03-05 16:20:52 +02005326 return mask;
5327}
5328
Ander Conselvan de Oliveira679dacd2015-03-20 16:18:15 +02005329static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
Imre Deak77d22dc2014-03-05 16:20:52 +02005330{
Ander Conselvan de Oliveira679dacd2015-03-20 16:18:15 +02005331 struct drm_device *dev = state->dev;
Imre Deak77d22dc2014-03-05 16:20:52 +02005332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5334 struct intel_crtc *crtc;
5335
5336 /*
5337 * First get all needed power domains, then put all unneeded, to avoid
5338 * any unnecessary toggling of the power wells.
5339 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01005340 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02005341 enum intel_display_power_domain domain;
5342
Matt Roper83d65732015-02-25 13:12:16 -08005343 if (!crtc->base.state->enable)
Imre Deak77d22dc2014-03-05 16:20:52 +02005344 continue;
5345
Imre Deak319be8a2014-03-04 19:22:57 +02005346 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02005347
5348 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5349 intel_display_power_get(dev_priv, domain);
5350 }
5351
Ville Syrjälä50f6e502014-11-06 14:49:12 +02005352 if (dev_priv->display.modeset_global_resources)
Ander Conselvan de Oliveira679dacd2015-03-20 16:18:15 +02005353 dev_priv->display.modeset_global_resources(state);
Ville Syrjälä50f6e502014-11-06 14:49:12 +02005354
Damien Lespiaud3fcc802014-05-13 23:32:22 +01005355 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02005356 enum intel_display_power_domain domain;
5357
5358 for_each_power_domain(domain, crtc->enabled_power_domains)
5359 intel_display_power_put(dev_priv, domain);
5360
5361 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5362 }
5363
5364 intel_display_set_init_power(dev_priv, false);
5365}
5366
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305367void broxton_set_cdclk(struct drm_device *dev, int frequency)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t divider;
5371 uint32_t ratio;
5372 uint32_t current_freq;
5373 int ret;
5374
5375 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5376 switch (frequency) {
5377 case 144000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5379 ratio = BXT_DE_PLL_RATIO(60);
5380 break;
5381 case 288000:
5382 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5383 ratio = BXT_DE_PLL_RATIO(60);
5384 break;
5385 case 384000:
5386 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5387 ratio = BXT_DE_PLL_RATIO(60);
5388 break;
5389 case 576000:
5390 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5391 ratio = BXT_DE_PLL_RATIO(60);
5392 break;
5393 case 624000:
5394 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5395 ratio = BXT_DE_PLL_RATIO(65);
5396 break;
5397 case 19200:
5398 /*
5399 * Bypass frequency with DE PLL disabled. Init ratio, divider
5400 * to suppress GCC warning.
5401 */
5402 ratio = 0;
5403 divider = 0;
5404 break;
5405 default:
5406 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5407
5408 return;
5409 }
5410
5411 mutex_lock(&dev_priv->rps.hw_lock);
5412 /* Inform power controller of upcoming frequency change */
5413 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5414 0x80000000);
5415 mutex_unlock(&dev_priv->rps.hw_lock);
5416
5417 if (ret) {
5418 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5419 ret, frequency);
5420 return;
5421 }
5422
5423 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5424 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5425 current_freq = current_freq * 500 + 1000;
5426
5427 /*
5428 * DE PLL has to be disabled when
5429 * - setting to 19.2MHz (bypass, PLL isn't used)
5430 * - before setting to 624MHz (PLL needs toggling)
5431 * - before setting to any frequency from 624MHz (PLL needs toggling)
5432 */
5433 if (frequency == 19200 || frequency == 624000 ||
5434 current_freq == 624000) {
5435 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5436 /* Timeout 200us */
5437 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5438 1))
5439 DRM_ERROR("timout waiting for DE PLL unlock\n");
5440 }
5441
5442 if (frequency != 19200) {
5443 uint32_t val;
5444
5445 val = I915_READ(BXT_DE_PLL_CTL);
5446 val &= ~BXT_DE_PLL_RATIO_MASK;
5447 val |= ratio;
5448 I915_WRITE(BXT_DE_PLL_CTL, val);
5449
5450 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5451 /* Timeout 200us */
5452 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5453 DRM_ERROR("timeout waiting for DE PLL lock\n");
5454
5455 val = I915_READ(CDCLK_CTL);
5456 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5457 val |= divider;
5458 /*
5459 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5460 * enable otherwise.
5461 */
5462 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463 if (frequency >= 500000)
5464 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5465
5466 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5467 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5468 val |= (frequency - 1000) / 500;
5469 I915_WRITE(CDCLK_CTL, val);
5470 }
5471
5472 mutex_lock(&dev_priv->rps.hw_lock);
5473 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5474 DIV_ROUND_UP(frequency, 25000));
5475 mutex_unlock(&dev_priv->rps.hw_lock);
5476
5477 if (ret) {
5478 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5479 ret, frequency);
5480 return;
5481 }
5482
5483 dev_priv->cdclk_freq = frequency;
5484}
5485
5486void broxton_init_cdclk(struct drm_device *dev)
5487{
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 uint32_t val;
5490
5491 /*
5492 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5493 * or else the reset will hang because there is no PCH to respond.
5494 * Move the handshake programming to initialization sequence.
5495 * Previously was left up to BIOS.
5496 */
5497 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5498 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5499 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5500
5501 /* Enable PG1 for cdclk */
5502 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5503
5504 /* check if cd clock is enabled */
5505 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5506 DRM_DEBUG_KMS("Display already initialized\n");
5507 return;
5508 }
5509
5510 /*
5511 * FIXME:
5512 * - The initial CDCLK needs to be read from VBT.
5513 * Need to make this change after VBT has changes for BXT.
5514 * - check if setting the max (or any) cdclk freq is really necessary
5515 * here, it belongs to modeset time
5516 */
5517 broxton_set_cdclk(dev, 624000);
5518
5519 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
Ville Syrjälä22e02c02015-05-06 14:28:57 +03005520 POSTING_READ(DBUF_CTL);
5521
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305522 udelay(10);
5523
5524 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5525 DRM_ERROR("DBuf power enable timeout!\n");
5526}
5527
5528void broxton_uninit_cdclk(struct drm_device *dev)
5529{
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
Ville Syrjälä22e02c02015-05-06 14:28:57 +03005533 POSTING_READ(DBUF_CTL);
5534
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305535 udelay(10);
5536
5537 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5538 DRM_ERROR("DBuf power disable timeout!\n");
5539
5540 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5541 broxton_set_cdclk(dev, 19200);
5542
5543 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5544}
5545
Ville Syrjälädfcab172014-06-13 13:37:47 +03005546/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03005547static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005548{
Jesse Barnes586f49d2013-11-04 16:06:59 -08005549 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08005550
Jesse Barnes586f49d2013-11-04 16:06:59 -08005551 /* Obtain SKU information */
5552 mutex_lock(&dev_priv->dpio_lock);
5553 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5554 CCK_FUSE_HPLL_FREQ_MASK;
5555 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08005556
Ville Syrjälädfcab172014-06-13 13:37:47 +03005557 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005558}
5559
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03005560static void vlv_update_cdclk(struct drm_device *dev)
5561{
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563
Vandana Kannan164dfd22014-11-24 13:37:41 +05305564 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Ville Syrjälä43dc52c2014-10-07 17:41:20 +03005565 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
Vandana Kannan164dfd22014-11-24 13:37:41 +05305566 dev_priv->cdclk_freq);
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03005567
5568 /*
5569 * Program the gmbus_freq based on the cdclk frequency.
5570 * BSpec erroneously claims we should aim for 4MHz, but
5571 * in fact 1MHz is the correct frequency.
5572 */
Vandana Kannan164dfd22014-11-24 13:37:41 +05305573 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03005574}
5575
Jesse Barnes30a970c2013-11-04 13:48:12 -08005576/* Adjust CDclk dividers to allow high res or save power if possible */
5577static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5578{
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5580 u32 val, cmd;
5581
Vandana Kannan164dfd22014-11-24 13:37:41 +05305582 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5583 != dev_priv->cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02005584
Ville Syrjälädfcab172014-06-13 13:37:47 +03005585 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08005586 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03005587 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005588 cmd = 1;
5589 else
5590 cmd = 0;
5591
5592 mutex_lock(&dev_priv->rps.hw_lock);
5593 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5594 val &= ~DSPFREQGUAR_MASK;
5595 val |= (cmd << DSPFREQGUAR_SHIFT);
5596 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5597 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5598 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5599 50)) {
5600 DRM_ERROR("timed out waiting for CDclk change\n");
5601 }
5602 mutex_unlock(&dev_priv->rps.hw_lock);
5603
Ville Syrjälädfcab172014-06-13 13:37:47 +03005604 if (cdclk == 400000) {
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005605 u32 divider;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005606
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005607 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005608
5609 mutex_lock(&dev_priv->dpio_lock);
5610 /* adjust cdclk divider */
5611 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03005612 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005613 val |= divider;
5614 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03005615
5616 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5617 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5618 50))
5619 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08005620 mutex_unlock(&dev_priv->dpio_lock);
5621 }
5622
5623 mutex_lock(&dev_priv->dpio_lock);
5624 /* adjust self-refresh exit latency value */
5625 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5626 val &= ~0x7f;
5627
5628 /*
5629 * For high bandwidth configs, we set a higher latency in the bunit
5630 * so that the core display fetch happens in time to avoid underruns.
5631 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03005632 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005633 val |= 4500 / 250; /* 4.5 usec */
5634 else
5635 val |= 3000 / 250; /* 3.0 usec */
5636 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5637 mutex_unlock(&dev_priv->dpio_lock);
5638
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03005639 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08005640}
5641
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005642static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5643{
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645 u32 val, cmd;
5646
Vandana Kannan164dfd22014-11-24 13:37:41 +05305647 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5648 != dev_priv->cdclk_freq);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005649
5650 switch (cdclk) {
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005651 case 333333:
5652 case 320000:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005653 case 266667:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005654 case 200000:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005655 break;
5656 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +01005657 MISSING_CASE(cdclk);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005658 return;
5659 }
5660
Ville Syrjälä9d0d3fd2015-03-02 20:07:17 +02005661 /*
5662 * Specs are full of misinformation, but testing on actual
5663 * hardware has shown that we just need to write the desired
5664 * CCK divider into the Punit register.
5665 */
5666 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5667
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005668 mutex_lock(&dev_priv->rps.hw_lock);
5669 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5670 val &= ~DSPFREQGUAR_MASK_CHV;
5671 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5672 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5673 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5674 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5675 50)) {
5676 DRM_ERROR("timed out waiting for CDclk change\n");
5677 }
5678 mutex_unlock(&dev_priv->rps.hw_lock);
5679
5680 vlv_update_cdclk(dev);
5681}
5682
Jesse Barnes30a970c2013-11-04 13:48:12 -08005683static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5684 int max_pixclk)
5685{
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005686 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
Ville Syrjälä6cca3192015-03-02 20:07:16 +02005687 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03005688
Jesse Barnes30a970c2013-11-04 13:48:12 -08005689 /*
5690 * Really only a few cases to deal with, as only 4 CDclks are supported:
5691 * 200MHz
5692 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03005693 * 320/333MHz (depends on HPLL freq)
Ville Syrjälä6cca3192015-03-02 20:07:16 +02005694 * 400MHz (VLV only)
5695 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5696 * of the lower bin and adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03005697 *
5698 * We seem to get an unstable or solid color picture at 200MHz.
5699 * Not sure what's wrong. For now use 200MHz only when all pipes
5700 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08005701 */
Ville Syrjälä6cca3192015-03-02 20:07:16 +02005702 if (!IS_CHERRYVIEW(dev_priv) &&
5703 max_pixclk > freq_320*limit/100)
Ville Syrjälädfcab172014-06-13 13:37:47 +03005704 return 400000;
Ville Syrjälä6cca3192015-03-02 20:07:16 +02005705 else if (max_pixclk > 266667*limit/100)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03005706 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03005707 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03005708 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03005709 else
5710 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005711}
5712
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305713static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5714 int max_pixclk)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005715{
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305716 /*
5717 * FIXME:
5718 * - remove the guardband, it's not needed on BXT
5719 * - set 19.2MHz bypass frequency if there are no active pipes
5720 */
5721 if (max_pixclk > 576000*9/10)
5722 return 624000;
5723 else if (max_pixclk > 384000*9/10)
5724 return 576000;
5725 else if (max_pixclk > 288000*9/10)
5726 return 384000;
5727 else if (max_pixclk > 144000*9/10)
5728 return 288000;
5729 else
5730 return 144000;
5731}
5732
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005733/* Compute the max pixel clock for new configuration. Uses atomic state if
5734 * that's non-NULL, look at current state otherwise. */
5735static int intel_mode_max_pixclk(struct drm_device *dev,
5736 struct drm_atomic_state *state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005737{
Jesse Barnes30a970c2013-11-04 13:48:12 -08005738 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005739 struct intel_crtc_state *crtc_state;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005740 int max_pixclk = 0;
5741
Damien Lespiaud3fcc802014-05-13 23:32:22 +01005742 for_each_intel_crtc(dev, intel_crtc) {
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005743 if (state)
5744 crtc_state =
5745 intel_atomic_get_crtc_state(state, intel_crtc);
5746 else
5747 crtc_state = intel_crtc->config;
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005748 if (IS_ERR(crtc_state))
5749 return PTR_ERR(crtc_state);
5750
5751 if (!crtc_state->base.enable)
5752 continue;
5753
5754 max_pixclk = max(max_pixclk,
5755 crtc_state->base.adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08005756 }
5757
5758 return max_pixclk;
5759}
5760
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +03005761static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005762{
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005763 struct drm_i915_private *dev_priv = to_i915(state->dev);
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +03005764 struct drm_crtc *crtc;
5765 struct drm_crtc_state *crtc_state;
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005766 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +03005767 int cdclk, i;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005768
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005769 if (max_pixclk < 0)
5770 return max_pixclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005771
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305772 if (IS_VALLEYVIEW(dev_priv))
5773 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5774 else
5775 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5776
5777 if (cdclk == dev_priv->cdclk_freq)
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005778 return 0;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005779
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +03005780 /* add all active pipes to the state */
5781 for_each_crtc(state->dev, crtc) {
5782 if (!crtc->state->enable)
5783 continue;
5784
5785 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5786 if (IS_ERR(crtc_state))
5787 return PTR_ERR(crtc_state);
5788 }
5789
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02005790 /* disable/enable all currently active pipes while we change cdclk */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +03005791 for_each_crtc_in_state(state, crtc, crtc_state, i)
5792 if (crtc_state->enable)
5793 crtc_state->mode_changed = true;
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005794
5795 return 0;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005796}
5797
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02005798static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5799{
5800 unsigned int credits, default_credits;
5801
5802 if (IS_CHERRYVIEW(dev_priv))
5803 default_credits = PFI_CREDIT(12);
5804 else
5805 default_credits = PFI_CREDIT(8);
5806
Vandana Kannan164dfd22014-11-24 13:37:41 +05305807 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02005808 /* CHV suggested value is 31 or 63 */
5809 if (IS_CHERRYVIEW(dev_priv))
5810 credits = PFI_CREDIT_31;
5811 else
5812 credits = PFI_CREDIT(15);
5813 } else {
5814 credits = default_credits;
5815 }
5816
5817 /*
5818 * WA - write default credits before re-programming
5819 * FIXME: should we also set the resend bit here?
5820 */
5821 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5822 default_credits);
5823
5824 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5825 credits | PFI_CREDIT_RESEND);
5826
5827 /*
5828 * FIXME is this guaranteed to clear
5829 * immediately or should we poll for it?
5830 */
5831 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5832}
5833
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005834static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005835{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005836 struct drm_device *dev = old_state->dev;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005837 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005838 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005839 int req_cdclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005840
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03005841 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5842 * never fail. */
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03005843 if (WARN_ON(max_pixclk < 0))
5844 return;
5845
5846 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
Jesse Barnes30a970c2013-11-04 13:48:12 -08005847
Vandana Kannan164dfd22014-11-24 13:37:41 +05305848 if (req_cdclk != dev_priv->cdclk_freq) {
Imre Deak738c05c2014-11-19 16:25:37 +02005849 /*
5850 * FIXME: We can end up here with all power domains off, yet
5851 * with a CDCLK frequency other than the minimum. To account
5852 * for this take the PIPE-A power domain, which covers the HW
5853 * blocks needed for the following programming. This can be
5854 * removed once it's guaranteed that we get here either with
5855 * the minimum CDCLK set, or the required power domains
5856 * enabled.
5857 */
5858 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5859
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005860 if (IS_CHERRYVIEW(dev))
5861 cherryview_set_cdclk(dev, req_cdclk);
5862 else
5863 valleyview_set_cdclk(dev, req_cdclk);
Imre Deak738c05c2014-11-19 16:25:37 +02005864
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02005865 vlv_program_pfi_credits(dev_priv);
5866
Imre Deak738c05c2014-11-19 16:25:37 +02005867 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005868 }
Jesse Barnes30a970c2013-11-04 13:48:12 -08005869}
5870
Jesse Barnes89b667f2013-04-18 14:51:36 -07005871static void valleyview_crtc_enable(struct drm_crtc *crtc)
5872{
5873 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02005874 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5876 struct intel_encoder *encoder;
5877 int pipe = intel_crtc->pipe;
Jani Nikula23538ef2013-08-27 15:12:22 +03005878 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07005879
Matt Roper83d65732015-02-25 13:12:16 -08005880 WARN_ON(!crtc->state->enable);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005881
5882 if (intel_crtc->active)
5883 return;
5884
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005885 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
Shobhit Kumar8525a232014-06-25 12:20:39 +05305886
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005887 if (!is_dsi) {
5888 if (IS_CHERRYVIEW(dev))
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005889 chv_prepare_pll(intel_crtc, intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005890 else
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005891 vlv_prepare_pll(intel_crtc, intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005892 }
Daniel Vetter5b18e572014-04-24 23:55:06 +02005893
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005894 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd482015-02-13 15:32:59 +05305895 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter5b18e572014-04-24 23:55:06 +02005896
5897 intel_set_pipe_timings(intel_crtc);
5898
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005899 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5900 struct drm_i915_private *dev_priv = dev->dev_private;
5901
5902 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5903 I915_WRITE(CHV_CANVAS(pipe), 0);
5904 }
5905
Daniel Vetter5b18e572014-04-24 23:55:06 +02005906 i9xx_set_pipeconf(intel_crtc);
5907
Jesse Barnes89b667f2013-04-18 14:51:36 -07005908 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07005909
Daniel Vettera72e4c92014-09-30 10:56:47 +02005910 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005911
Jesse Barnes89b667f2013-04-18 14:51:36 -07005912 for_each_encoder_on_crtc(dev, crtc, encoder)
5913 if (encoder->pre_pll_enable)
5914 encoder->pre_pll_enable(encoder);
5915
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005916 if (!is_dsi) {
5917 if (IS_CHERRYVIEW(dev))
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005918 chv_enable_pll(intel_crtc, intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005919 else
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005920 vlv_enable_pll(intel_crtc, intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005921 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07005922
5923 for_each_encoder_on_crtc(dev, crtc, encoder)
5924 if (encoder->pre_enable)
5925 encoder->pre_enable(encoder);
5926
Jesse Barnes2dd24552013-04-25 12:55:01 -07005927 i9xx_pfit_enable(intel_crtc);
5928
Ville Syrjälä63cbb072013-06-04 13:48:59 +03005929 intel_crtc_load_lut(crtc);
5930
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005931 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005932 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02005933
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005934 assert_vblank_disabled(crtc);
5935 drm_crtc_vblank_on(crtc);
5936
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005937 for_each_encoder_on_crtc(dev, crtc, encoder)
5938 encoder->enable(encoder);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005939}
5940
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005941static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5942{
5943 struct drm_device *dev = crtc->base.dev;
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005946 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5947 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005948}
5949
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005950static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005951{
5952 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02005953 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08005954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005955 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005956 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005957
Matt Roper83d65732015-02-25 13:12:16 -08005958 WARN_ON(!crtc->state->enable);
Daniel Vetter08a48462012-07-02 11:43:47 +02005959
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005960 if (intel_crtc->active)
5961 return;
5962
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005963 i9xx_set_pll_dividers(intel_crtc);
5964
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005965 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd482015-02-13 15:32:59 +05305966 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter5b18e572014-04-24 23:55:06 +02005967
5968 intel_set_pipe_timings(intel_crtc);
5969
Daniel Vetter5b18e572014-04-24 23:55:06 +02005970 i9xx_set_pipeconf(intel_crtc);
5971
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005972 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01005973
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005974 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005975 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005976
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02005977 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02005978 if (encoder->pre_enable)
5979 encoder->pre_enable(encoder);
5980
Daniel Vetterf6736a12013-06-05 13:34:30 +02005981 i9xx_enable_pll(intel_crtc);
5982
Jesse Barnes2dd24552013-04-25 12:55:01 -07005983 i9xx_pfit_enable(intel_crtc);
5984
Ville Syrjälä63cbb072013-06-04 13:48:59 +03005985 intel_crtc_load_lut(crtc);
5986
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005987 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005988 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02005989
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005990 assert_vblank_disabled(crtc);
5991 drm_crtc_vblank_on(crtc);
5992
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005993 for_each_encoder_on_crtc(dev, crtc, encoder)
5994 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005995}
5996
Daniel Vetter87476d62013-04-11 16:29:06 +02005997static void i9xx_pfit_disable(struct intel_crtc *crtc)
5998{
5999 struct drm_device *dev = crtc->base.dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02006001
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006002 if (!crtc->config->gmch_pfit.control)
Daniel Vetter328d8e82013-05-08 10:36:31 +02006003 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02006004
6005 assert_pipe_disabled(dev_priv, crtc->pipe);
6006
Daniel Vetter328d8e82013-05-08 10:36:31 +02006007 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6008 I915_READ(PFIT_CONTROL));
6009 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02006010}
6011
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006012static void i9xx_crtc_disable(struct drm_crtc *crtc)
6013{
6014 struct drm_device *dev = crtc->dev;
6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02006017 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006018 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02006019
Chris Wilsonf7abfe82010-09-13 14:19:16 +01006020 if (!intel_crtc->active)
6021 return;
6022
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006023 /*
6024 * On gen2 planes are double buffered but the pipe isn't, so we must
6025 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03006026 * We also need to wait on all gmch platforms because of the
6027 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006028 */
Imre Deak564ed192014-06-13 14:54:21 +03006029 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006030
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006031 for_each_encoder_on_crtc(dev, crtc, encoder)
6032 encoder->disable(encoder);
6033
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01006034 drm_crtc_vblank_off(crtc);
6035 assert_vblank_disabled(crtc);
6036
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03006037 intel_disable_pipe(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02006038
Daniel Vetter87476d62013-04-11 16:29:06 +02006039 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02006040
Jesse Barnes89b667f2013-04-18 14:51:36 -07006041 for_each_encoder_on_crtc(dev, crtc, encoder)
6042 if (encoder->post_disable)
6043 encoder->post_disable(encoder);
6044
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006045 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03006046 if (IS_CHERRYVIEW(dev))
6047 chv_disable_pll(dev_priv, pipe);
6048 else if (IS_VALLEYVIEW(dev))
6049 vlv_disable_pll(dev_priv, pipe);
6050 else
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03006051 i9xx_disable_pll(intel_crtc);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03006052 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006053
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006054 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02006055 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006056
Chris Wilsonf7abfe82010-09-13 14:19:16 +01006057 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03006058 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03006059
Daniel Vetterefa96242014-04-24 23:55:02 +02006060 mutex_lock(&dev->struct_mutex);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02006061 intel_fbc_update(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02006062 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006063}
6064
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006065static void i9xx_crtc_off(struct drm_crtc *crtc)
6066{
6067}
6068
Borun Fub04c5bd2014-07-12 10:02:27 +05306069/* Master function to enable/disable CRTC and corresponding power wells */
6070void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01006071{
Chris Wilsoncdd59982010-09-08 16:30:16 +01006072 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006073 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006075 enum intel_display_power_domain domain;
6076 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02006077
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006078 if (enable) {
6079 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03006080 domains = get_crtc_power_domains(crtc);
6081 for_each_power_domain(domain, domains)
6082 intel_display_power_get(dev_priv, domain);
6083 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006084
6085 dev_priv->display.crtc_enable(crtc);
Maarten Lankhorstce22dba2015-04-21 17:12:56 +03006086 intel_crtc_enable_planes(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006087 }
6088 } else {
6089 if (intel_crtc->active) {
Maarten Lankhorstce22dba2015-04-21 17:12:56 +03006090 intel_crtc_disable_planes(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006091 dev_priv->display.crtc_disable(crtc);
6092
Daniel Vettere1e9fb82014-06-25 22:02:04 +03006093 domains = intel_crtc->enabled_power_domains;
6094 for_each_power_domain(domain, domains)
6095 intel_display_power_put(dev_priv, domain);
6096 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006097 }
6098 }
Borun Fub04c5bd2014-07-12 10:02:27 +05306099}
6100
6101/**
6102 * Sets the power management mode of the pipe and plane.
6103 */
6104void intel_crtc_update_dpms(struct drm_crtc *crtc)
6105{
6106 struct drm_device *dev = crtc->dev;
6107 struct intel_encoder *intel_encoder;
6108 bool enable = false;
6109
6110 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6111 enable |= intel_encoder->connectors_active;
6112
6113 intel_crtc_control(crtc, enable);
Ander Conselvan de Oliveira0f63cca2015-04-21 17:13:17 +03006114
6115 crtc->state->active = enable;
Daniel Vetter976f8a22012-07-08 22:34:21 +02006116}
6117
Daniel Vetter976f8a22012-07-08 22:34:21 +02006118static void intel_crtc_disable(struct drm_crtc *crtc)
6119{
6120 struct drm_device *dev = crtc->dev;
6121 struct drm_connector *connector;
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6123
6124 /* crtc should still be enabled when we disable it. */
Matt Roper83d65732015-02-25 13:12:16 -08006125 WARN_ON(!crtc->state->enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02006126
Maarten Lankhorstce22dba2015-04-21 17:12:56 +03006127 intel_crtc_disable_planes(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02006128 dev_priv->display.crtc_disable(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006129 dev_priv->display.off(crtc);
6130
Matt Roper70a101f2015-04-08 18:56:53 -07006131 drm_plane_helper_disable(crtc->primary);
Daniel Vetter976f8a22012-07-08 22:34:21 +02006132
6133 /* Update computed state. */
6134 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6135 if (!connector->encoder || !connector->encoder->crtc)
6136 continue;
6137
6138 if (connector->encoder->crtc != crtc)
6139 continue;
6140
6141 connector->dpms = DRM_MODE_DPMS_OFF;
6142 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01006143 }
6144}
6145
Chris Wilsonea5b2132010-08-04 13:50:23 +01006146void intel_encoder_destroy(struct drm_encoder *encoder)
6147{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006148 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01006149
Chris Wilsonea5b2132010-08-04 13:50:23 +01006150 drm_encoder_cleanup(encoder);
6151 kfree(intel_encoder);
6152}
6153
Damien Lespiau92373292013-08-08 22:28:57 +01006154/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006155 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6156 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01006157static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006158{
6159 if (mode == DRM_MODE_DPMS_ON) {
6160 encoder->connectors_active = true;
6161
Daniel Vetterb2cabb02012-07-01 22:42:24 +02006162 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006163 } else {
6164 encoder->connectors_active = false;
6165
Daniel Vetterb2cabb02012-07-01 22:42:24 +02006166 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006167 }
6168}
6169
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006170/* Cross check the actual hw state with our own modeset state tracking (and it's
6171 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02006172static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006173{
6174 if (connector->get_hw_state(connector)) {
6175 struct intel_encoder *encoder = connector->encoder;
6176 struct drm_crtc *crtc;
6177 bool encoder_enabled;
6178 enum pipe pipe;
6179
6180 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6181 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03006182 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006183
Dave Airlie0e32b392014-05-02 14:02:48 +10006184 /* there is no real hw state for MST connectors */
6185 if (connector->mst_port)
6186 return;
6187
Rob Clarke2c719b2014-12-15 13:56:32 -05006188 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006189 "wrong connector dpms state\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05006190 I915_STATE_WARN(connector->base.encoder != &encoder->base,
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006191 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006192
Dave Airlie36cd7442014-05-02 13:44:18 +10006193 if (encoder) {
Rob Clarke2c719b2014-12-15 13:56:32 -05006194 I915_STATE_WARN(!encoder->connectors_active,
Dave Airlie36cd7442014-05-02 13:44:18 +10006195 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006196
Dave Airlie36cd7442014-05-02 13:44:18 +10006197 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
Rob Clarke2c719b2014-12-15 13:56:32 -05006198 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6199 if (I915_STATE_WARN_ON(!encoder->base.crtc))
Dave Airlie36cd7442014-05-02 13:44:18 +10006200 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006201
Dave Airlie36cd7442014-05-02 13:44:18 +10006202 crtc = encoder->base.crtc;
6203
Matt Roper83d65732015-02-25 13:12:16 -08006204 I915_STATE_WARN(!crtc->state->enable,
6205 "crtc not enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05006206 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6207 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
Dave Airlie36cd7442014-05-02 13:44:18 +10006208 "encoder active on the wrong pipe\n");
6209 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006210 }
6211}
6212
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006213int intel_connector_init(struct intel_connector *connector)
6214{
6215 struct drm_connector_state *connector_state;
6216
6217 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6218 if (!connector_state)
6219 return -ENOMEM;
6220
6221 connector->base.state = connector_state;
6222 return 0;
6223}
6224
6225struct intel_connector *intel_connector_alloc(void)
6226{
6227 struct intel_connector *connector;
6228
6229 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6230 if (!connector)
6231 return NULL;
6232
6233 if (intel_connector_init(connector) < 0) {
6234 kfree(connector);
6235 return NULL;
6236 }
6237
6238 return connector;
6239}
6240
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006241/* Even simpler default implementation, if there's really no special case to
6242 * consider. */
6243void intel_connector_dpms(struct drm_connector *connector, int mode)
6244{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006245 /* All the simple cases only support two dpms states. */
6246 if (mode != DRM_MODE_DPMS_ON)
6247 mode = DRM_MODE_DPMS_OFF;
6248
6249 if (mode == connector->dpms)
6250 return;
6251
6252 connector->dpms = mode;
6253
6254 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01006255 if (connector->encoder)
6256 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006257
Daniel Vetterb9805142012-08-31 17:37:33 +02006258 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02006259}
6260
Daniel Vetterf0947c32012-07-02 13:10:34 +02006261/* Simple connector->get_hw_state implementation for encoders that support only
6262 * one connector and no cloning and hence the encoder state determines the state
6263 * of the connector. */
6264bool intel_connector_get_hw_state(struct intel_connector *connector)
6265{
Daniel Vetter24929352012-07-02 20:28:59 +02006266 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02006267 struct intel_encoder *encoder = connector->encoder;
6268
6269 return encoder->get_hw_state(encoder, &pipe);
6270}
6271
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006272static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
Ville Syrjäläd272ddf2015-03-11 18:52:31 +02006273{
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006274 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6275 return crtc_state->fdi_lanes;
Ville Syrjäläd272ddf2015-03-11 18:52:31 +02006276
6277 return 0;
6278}
6279
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006280static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006281 struct intel_crtc_state *pipe_config)
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006282{
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006283 struct drm_atomic_state *state = pipe_config->base.state;
6284 struct intel_crtc *other_crtc;
6285 struct intel_crtc_state *other_crtc_state;
6286
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006287 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6288 pipe_name(pipe), pipe_config->fdi_lanes);
6289 if (pipe_config->fdi_lanes > 4) {
6290 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6291 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006292 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006293 }
6294
Paulo Zanonibafb6552013-11-02 21:07:44 -07006295 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006296 if (pipe_config->fdi_lanes > 2) {
6297 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6298 pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006299 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006300 } else {
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006301 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006302 }
6303 }
6304
6305 if (INTEL_INFO(dev)->num_pipes == 2)
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006306 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006307
6308 /* Ivybridge 3 pipe is really complicated */
6309 switch (pipe) {
6310 case PIPE_A:
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006311 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006312 case PIPE_B:
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006313 if (pipe_config->fdi_lanes <= 2)
6314 return 0;
6315
6316 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6317 other_crtc_state =
6318 intel_atomic_get_crtc_state(state, other_crtc);
6319 if (IS_ERR(other_crtc_state))
6320 return PTR_ERR(other_crtc_state);
6321
6322 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006323 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6324 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006325 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006326 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006327 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006328 case PIPE_C:
Ville Syrjälä251cc672015-03-11 18:52:30 +02006329 if (pipe_config->fdi_lanes > 2) {
6330 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6331 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006332 return -EINVAL;
Ville Syrjälä251cc672015-03-11 18:52:30 +02006333 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006334
6335 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6336 other_crtc_state =
6337 intel_atomic_get_crtc_state(state, other_crtc);
6338 if (IS_ERR(other_crtc_state))
6339 return PTR_ERR(other_crtc_state);
6340
6341 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006342 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006343 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006344 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006345 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006346 default:
6347 BUG();
6348 }
6349}
6350
Daniel Vettere29c22c2013-02-21 00:00:16 +01006351#define RETRY 1
6352static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006353 struct intel_crtc_state *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02006354{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006355 struct drm_device *dev = intel_crtc->base.dev;
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02006356 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006357 int lane, link_bw, fdi_dotclock, ret;
6358 bool needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02006359
Daniel Vettere29c22c2013-02-21 00:00:16 +01006360retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02006361 /* FDI is a binary signal running at ~2.7GHz, encoding
6362 * each output octet as 10 bits. The actual frequency
6363 * is stored as a divider into a 100MHz clock, and the
6364 * mode pixel clock is stored in units of 1KHz.
6365 * Hence the bw of each lane in terms of the mode signal
6366 * is:
6367 */
6368 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6369
Damien Lespiau241bfc32013-09-25 16:45:37 +01006370 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02006371
Daniel Vetter2bd89a02013-06-01 17:16:19 +02006372 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02006373 pipe_config->pipe_bpp);
6374
6375 pipe_config->fdi_lanes = lane;
6376
Daniel Vetter2bd89a02013-06-01 17:16:19 +02006377 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02006378 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006379
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006380 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6381 intel_crtc->pipe, pipe_config);
6382 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
Daniel Vettere29c22c2013-02-21 00:00:16 +01006383 pipe_config->pipe_bpp -= 2*3;
6384 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6385 pipe_config->pipe_bpp);
6386 needs_recompute = true;
6387 pipe_config->bw_constrained = true;
6388
6389 goto retry;
6390 }
6391
6392 if (needs_recompute)
6393 return RETRY;
6394
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006395 return ret;
Daniel Vetter877d48d2013-04-19 11:24:43 +02006396}
6397
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006398static void hsw_compute_ips_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006399 struct intel_crtc_state *pipe_config)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006400{
Jani Nikulad330a952014-01-21 11:24:25 +02006401 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03006402 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07006403 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006404}
6405
Daniel Vettera43f6e02013-06-07 23:10:32 +02006406static int intel_crtc_compute_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006407 struct intel_crtc_state *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08006408{
Daniel Vettera43f6e02013-06-07 23:10:32 +02006409 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02006410 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02006411 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Chandra Kondurud03c93d2015-04-09 16:42:46 -07006412 int ret;
Chris Wilson89749352010-09-12 18:25:19 +01006413
Ville Syrjäläad3a4472013-09-04 18:30:04 +03006414 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006415 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006416 int clock_limit =
6417 dev_priv->display.get_display_clock_speed(dev);
6418
6419 /*
6420 * Enable pixel doubling when the dot clock
6421 * is > 90% of the (display) core speed.
6422 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03006423 * GDG double wide on either pipe,
6424 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006425 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03006426 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01006427 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03006428 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006429 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03006430 }
6431
Damien Lespiau241bfc32013-09-25 16:45:37 +01006432 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01006433 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006434 }
Chris Wilson89749352010-09-12 18:25:19 +01006435
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03006436 /*
6437 * Pipe horizontal size must be even in:
6438 * - DVO ganged mode
6439 * - LVDS dual channel mode
6440 * - Double wide pipe
6441 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006442 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03006443 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6444 pipe_config->pipe_src_w &= ~1;
6445
Damien Lespiau8693a822013-05-03 18:48:11 +01006446 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6447 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03006448 */
6449 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6450 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01006451 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03006452
Damien Lespiauf5adf942013-06-24 18:29:34 +01006453 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02006454 hsw_compute_ips_config(crtc, pipe_config);
6455
Daniel Vetter877d48d2013-04-19 11:24:43 +02006456 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02006457 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02006458
Chandra Kondurud03c93d2015-04-09 16:42:46 -07006459 /* FIXME: remove below call once atomic mode set is place and all crtc
6460 * related checks called from atomic_crtc_check function */
6461 ret = 0;
6462 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6463 crtc, pipe_config->base.state);
6464 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6465
6466 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006467}
6468
Ville Syrjälä1652d192015-03-31 14:12:01 +03006469static int skylake_get_display_clock_speed(struct drm_device *dev)
6470{
6471 struct drm_i915_private *dev_priv = to_i915(dev);
6472 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6473 uint32_t cdctl = I915_READ(CDCLK_CTL);
6474 uint32_t linkrate;
6475
6476 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6477 WARN(1, "LCPLL1 not enabled\n");
6478 return 24000; /* 24MHz is the cd freq with NSSC ref */
6479 }
6480
6481 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6482 return 540000;
6483
6484 linkrate = (I915_READ(DPLL_CTRL1) &
Damien Lespiau71cd8422015-04-30 16:39:17 +01006485 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
Ville Syrjälä1652d192015-03-31 14:12:01 +03006486
Damien Lespiau71cd8422015-04-30 16:39:17 +01006487 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6488 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
Ville Syrjälä1652d192015-03-31 14:12:01 +03006489 /* vco 8640 */
6490 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6491 case CDCLK_FREQ_450_432:
6492 return 432000;
6493 case CDCLK_FREQ_337_308:
6494 return 308570;
6495 case CDCLK_FREQ_675_617:
6496 return 617140;
6497 default:
6498 WARN(1, "Unknown cd freq selection\n");
6499 }
6500 } else {
6501 /* vco 8100 */
6502 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6503 case CDCLK_FREQ_450_432:
6504 return 450000;
6505 case CDCLK_FREQ_337_308:
6506 return 337500;
6507 case CDCLK_FREQ_675_617:
6508 return 675000;
6509 default:
6510 WARN(1, "Unknown cd freq selection\n");
6511 }
6512 }
6513
6514 /* error case, do as if DPLL0 isn't enabled */
6515 return 24000;
6516}
6517
6518static int broadwell_get_display_clock_speed(struct drm_device *dev)
6519{
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 uint32_t lcpll = I915_READ(LCPLL_CTL);
6522 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6523
6524 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6525 return 800000;
6526 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6527 return 450000;
6528 else if (freq == LCPLL_CLK_FREQ_450)
6529 return 450000;
6530 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6531 return 540000;
6532 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6533 return 337500;
6534 else
6535 return 675000;
6536}
6537
6538static int haswell_get_display_clock_speed(struct drm_device *dev)
6539{
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541 uint32_t lcpll = I915_READ(LCPLL_CTL);
6542 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6543
6544 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6545 return 800000;
6546 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6547 return 450000;
6548 else if (freq == LCPLL_CLK_FREQ_450)
6549 return 450000;
6550 else if (IS_HSW_ULT(dev))
6551 return 337500;
6552 else
6553 return 540000;
Jesse Barnes79e53942008-11-07 14:24:08 -08006554}
6555
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07006556static int valleyview_get_display_clock_speed(struct drm_device *dev)
6557{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03006558 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03006559 u32 val;
6560 int divider;
6561
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03006562 if (dev_priv->hpll_freq == 0)
6563 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6564
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03006565 mutex_lock(&dev_priv->dpio_lock);
6566 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6567 mutex_unlock(&dev_priv->dpio_lock);
6568
6569 divider = val & DISPLAY_FREQUENCY_VALUES;
6570
Ville Syrjälä7d007f42014-06-13 13:37:53 +03006571 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6572 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6573 "cdclk change in progress\n");
6574
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03006575 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07006576}
6577
Ville Syrjäläb37a6432015-03-31 14:11:54 +03006578static int ilk_get_display_clock_speed(struct drm_device *dev)
6579{
6580 return 450000;
6581}
6582
Jesse Barnese70236a2009-09-21 10:42:27 -07006583static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08006584{
Jesse Barnese70236a2009-09-21 10:42:27 -07006585 return 400000;
6586}
Jesse Barnes79e53942008-11-07 14:24:08 -08006587
Jesse Barnese70236a2009-09-21 10:42:27 -07006588static int i915_get_display_clock_speed(struct drm_device *dev)
6589{
Ville Syrjäläe907f172015-03-31 14:09:47 +03006590 return 333333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006591}
Jesse Barnes79e53942008-11-07 14:24:08 -08006592
Jesse Barnese70236a2009-09-21 10:42:27 -07006593static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6594{
6595 return 200000;
6596}
Jesse Barnes79e53942008-11-07 14:24:08 -08006597
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006598static int pnv_get_display_clock_speed(struct drm_device *dev)
6599{
6600 u16 gcfgc = 0;
6601
6602 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6603
6604 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6605 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006606 return 266667;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006607 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006608 return 333333;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006609 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006610 return 444444;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006611 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6612 return 200000;
6613 default:
6614 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6615 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006616 return 133333;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006617 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006618 return 166667;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006619 }
6620}
6621
Jesse Barnese70236a2009-09-21 10:42:27 -07006622static int i915gm_get_display_clock_speed(struct drm_device *dev)
6623{
6624 u16 gcfgc = 0;
6625
6626 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6627
6628 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Ville Syrjäläe907f172015-03-31 14:09:47 +03006629 return 133333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006630 else {
6631 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6632 case GC_DISPLAY_CLOCK_333_MHZ:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006633 return 333333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006634 default:
6635 case GC_DISPLAY_CLOCK_190_200_MHZ:
6636 return 190000;
6637 }
6638 }
6639}
Jesse Barnes79e53942008-11-07 14:24:08 -08006640
Jesse Barnese70236a2009-09-21 10:42:27 -07006641static int i865_get_display_clock_speed(struct drm_device *dev)
6642{
Ville Syrjäläe907f172015-03-31 14:09:47 +03006643 return 266667;
Jesse Barnese70236a2009-09-21 10:42:27 -07006644}
6645
6646static int i855_get_display_clock_speed(struct drm_device *dev)
6647{
6648 u16 hpllcc = 0;
6649 /* Assume that the hardware is in the high speed state. This
6650 * should be the default.
6651 */
6652 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6653 case GC_CLOCK_133_200:
6654 case GC_CLOCK_100_200:
6655 return 200000;
6656 case GC_CLOCK_166_250:
6657 return 250000;
6658 case GC_CLOCK_100_133:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006659 return 133333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006660 }
6661
6662 /* Shouldn't happen */
6663 return 0;
6664}
6665
6666static int i830_get_display_clock_speed(struct drm_device *dev)
6667{
Ville Syrjäläe907f172015-03-31 14:09:47 +03006668 return 133333;
Jesse Barnes79e53942008-11-07 14:24:08 -08006669}
6670
Zhenyu Wang2c072452009-06-05 15:38:42 +08006671static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03006672intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08006673{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03006674 while (*num > DATA_LINK_M_N_MASK ||
6675 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08006676 *num >>= 1;
6677 *den >>= 1;
6678 }
6679}
6680
Ville Syrjäläa65851a2013-04-23 15:03:34 +03006681static void compute_m_n(unsigned int m, unsigned int n,
6682 uint32_t *ret_m, uint32_t *ret_n)
6683{
6684 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6685 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6686 intel_reduce_m_n_ratio(ret_m, ret_n);
6687}
6688
Daniel Vettere69d0bc2012-11-29 15:59:36 +01006689void
6690intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6691 int pixel_clock, int link_clock,
6692 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08006693{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01006694 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03006695
6696 compute_m_n(bits_per_pixel * pixel_clock,
6697 link_clock * nlanes * 8,
6698 &m_n->gmch_m, &m_n->gmch_n);
6699
6700 compute_m_n(pixel_clock, link_clock,
6701 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08006702}
6703
Chris Wilsona7615032011-01-12 17:04:08 +00006704static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6705{
Jani Nikulad330a952014-01-21 11:24:25 +02006706 if (i915.panel_use_ssc >= 0)
6707 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006708 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07006709 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00006710}
6711
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006712static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6713 int num_connectors)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08006714{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006715 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08006716 struct drm_i915_private *dev_priv = dev->dev_private;
6717 int refclk;
6718
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006719 WARN_ON(!crtc_state->base.state);
6720
Imre Deak5ab7b0b2015-03-06 03:29:25 +02006721 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02006722 refclk = 100000;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006723 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08006724 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006725 refclk = dev_priv->vbt.lvds_ssc_freq;
6726 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08006727 } else if (!IS_GEN2(dev)) {
6728 refclk = 96000;
6729 } else {
6730 refclk = 48000;
6731 }
6732
6733 return refclk;
6734}
6735
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006736static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08006737{
Daniel Vetter7df00d72013-05-21 21:54:55 +02006738 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006739}
Daniel Vetterf47709a2013-03-28 10:42:02 +01006740
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006741static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6742{
6743 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08006744}
6745
Daniel Vetterf47709a2013-03-28 10:42:02 +01006746static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02006747 struct intel_crtc_state *crtc_state,
Jesse Barnesa7516a02011-12-15 12:30:37 -08006748 intel_clock_t *reduced_clock)
6749{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006750 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08006751 u32 fp, fp2 = 0;
6752
6753 if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02006754 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08006755 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006756 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08006757 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02006758 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08006759 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006760 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08006761 }
6762
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02006763 crtc_state->dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08006764
Daniel Vetterf47709a2013-03-28 10:42:02 +01006765 crtc->lowfreq_avail = false;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006766 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Rodrigo Viviab585de2015-03-24 12:40:09 -07006767 reduced_clock) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02006768 crtc_state->dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01006769 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08006770 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02006771 crtc_state->dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08006772 }
6773}
6774
Chon Ming Lee5e69f972013-09-05 20:41:49 +08006775static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6776 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07006777{
6778 u32 reg_val;
6779
6780 /*
6781 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6782 * and set it to a reasonable value instead.
6783 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07006785 reg_val &= 0xffffff00;
6786 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006787 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006788
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006789 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006790 reg_val &= 0x8cffffff;
6791 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006792 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006793
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006794 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07006795 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006796 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006797
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006798 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006799 reg_val &= 0x00ffffff;
6800 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006801 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006802}
6803
Daniel Vetterb5518422013-05-03 11:49:48 +02006804static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6805 struct intel_link_m_n *m_n)
6806{
6807 struct drm_device *dev = crtc->base.dev;
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 int pipe = crtc->pipe;
6810
Daniel Vettere3b95f12013-05-03 11:49:49 +02006811 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6812 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6813 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6814 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02006815}
6816
6817static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07006818 struct intel_link_m_n *m_n,
6819 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02006820{
6821 struct drm_device *dev = crtc->base.dev;
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 int pipe = crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006824 enum transcoder transcoder = crtc->config->cpu_transcoder;
Daniel Vetterb5518422013-05-03 11:49:48 +02006825
6826 if (INTEL_INFO(dev)->gen >= 5) {
6827 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6828 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6829 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6830 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07006831 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6832 * for gen < 8) and if DRRS is supported (to make sure the
6833 * registers are not unnecessarily accessed).
6834 */
Durgadoss R44395bf2015-02-13 15:33:02 +05306835 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006836 crtc->config->has_drrs) {
Vandana Kannanf769cd22014-08-05 07:51:22 -07006837 I915_WRITE(PIPE_DATA_M2(transcoder),
6838 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6839 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6840 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6841 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6842 }
Daniel Vetterb5518422013-05-03 11:49:48 +02006843 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02006844 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6845 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6846 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6847 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02006848 }
6849}
6850
Ramalingam Cfe3cd482015-02-13 15:32:59 +05306851void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02006852{
Ramalingam Cfe3cd482015-02-13 15:32:59 +05306853 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6854
6855 if (m_n == M1_N1) {
6856 dp_m_n = &crtc->config->dp_m_n;
6857 dp_m2_n2 = &crtc->config->dp_m2_n2;
6858 } else if (m_n == M2_N2) {
6859
6860 /*
6861 * M2_N2 registers are not supported. Hence m2_n2 divider value
6862 * needs to be programmed into M1_N1.
6863 */
6864 dp_m_n = &crtc->config->dp_m2_n2;
6865 } else {
6866 DRM_ERROR("Unsupported divider value\n");
6867 return;
6868 }
6869
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006870 if (crtc->config->has_pch_encoder)
6871 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02006872 else
Ramalingam Cfe3cd482015-02-13 15:32:59 +05306873 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02006874}
6875
Ville Syrjäläd288f652014-10-28 13:20:22 +02006876static void vlv_update_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006877 struct intel_crtc_state *pipe_config)
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006878{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006879 u32 dpll, dpll_md;
6880
6881 /*
6882 * Enable DPIO clock input. We should never disable the reference
6883 * clock for pipe B, since VGA hotplug / manual detection depends
6884 * on it.
6885 */
6886 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6887 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6888 /* We should never disable this, set it here for state tracking */
6889 if (crtc->pipe == PIPE_B)
6890 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6891 dpll |= DPLL_VCO_ENABLE;
Ville Syrjäläd288f652014-10-28 13:20:22 +02006892 pipe_config->dpll_hw_state.dpll = dpll;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006893
Ville Syrjäläd288f652014-10-28 13:20:22 +02006894 dpll_md = (pipe_config->pixel_multiplier - 1)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006895 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjäläd288f652014-10-28 13:20:22 +02006896 pipe_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006897}
6898
Ville Syrjäläd288f652014-10-28 13:20:22 +02006899static void vlv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006900 const struct intel_crtc_state *pipe_config)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006901{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006902 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006903 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01006904 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006905 u32 mdiv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006906 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006907 u32 coreclk, reg_val;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006908
Daniel Vetter09153002012-12-12 14:06:44 +01006909 mutex_lock(&dev_priv->dpio_lock);
6910
Ville Syrjäläd288f652014-10-28 13:20:22 +02006911 bestn = pipe_config->dpll.n;
6912 bestm1 = pipe_config->dpll.m1;
6913 bestm2 = pipe_config->dpll.m2;
6914 bestp1 = pipe_config->dpll.p1;
6915 bestp2 = pipe_config->dpll.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006916
Jesse Barnes89b667f2013-04-18 14:51:36 -07006917 /* See eDP HDMI DPIO driver vbios notes doc */
6918
6919 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006920 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08006921 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006922
6923 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006925
6926 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006927 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07006928 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006929 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006930
6931 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006932 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006933
6934 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006935 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6936 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6937 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006938 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07006939
6940 /*
6941 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6942 * but we don't support that).
6943 * Note: don't use the DAC post divider as it seems unstable.
6944 */
6945 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006947
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006948 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006950
Jesse Barnes89b667f2013-04-18 14:51:36 -07006951 /* Set HBR and RBR LPF coefficients */
Ville Syrjäläd288f652014-10-28 13:20:22 +02006952 if (pipe_config->port_clock == 162000 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006953 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6954 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b01202013-07-05 19:21:38 +03006956 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006957 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07006959 0x00d0000f);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006960
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02006961 if (pipe_config->has_dp_encoder) {
Jesse Barnes89b667f2013-04-18 14:51:36 -07006962 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006963 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006964 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07006965 0x0df40000);
6966 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07006968 0x0df70000);
6969 } else { /* HDMI or VGA */
6970 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02006971 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07006973 0x0df70000);
6974 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07006976 0x0df40000);
6977 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006978
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006979 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07006980 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006981 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6982 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Jesse Barnes89b667f2013-04-18 14:51:36 -07006983 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006984 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006985
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006986 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01006987 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07006988}
6989
Ville Syrjäläd288f652014-10-28 13:20:22 +02006990static void chv_update_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006991 struct intel_crtc_state *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006992{
Ville Syrjäläd288f652014-10-28 13:20:22 +02006993 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03006994 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6995 DPLL_VCO_ENABLE;
6996 if (crtc->pipe != PIPE_A)
Ville Syrjäläd288f652014-10-28 13:20:22 +02006997 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03006998
Ville Syrjäläd288f652014-10-28 13:20:22 +02006999 pipe_config->dpll_hw_state.dpll_md =
7000 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007001}
7002
Ville Syrjäläd288f652014-10-28 13:20:22 +02007003static void chv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007004 const struct intel_crtc_state *pipe_config)
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007005{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007006 struct drm_device *dev = crtc->base.dev;
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 int pipe = crtc->pipe;
7009 int dpll_reg = DPLL(crtc->pipe);
7010 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307011 u32 loopfilter, tribuf_calcntr;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007012 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307013 u32 dpio_val;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307014 int vco;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007015
Ville Syrjäläd288f652014-10-28 13:20:22 +02007016 bestn = pipe_config->dpll.n;
7017 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7018 bestm1 = pipe_config->dpll.m1;
7019 bestm2 = pipe_config->dpll.m2 >> 22;
7020 bestp1 = pipe_config->dpll.p1;
7021 bestp2 = pipe_config->dpll.p2;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307022 vco = pipe_config->dpll.vco;
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307023 dpio_val = 0;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307024 loopfilter = 0;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007025
7026 /*
7027 * Enable Refclk and SSC
7028 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03007029 I915_WRITE(dpll_reg,
Ville Syrjäläd288f652014-10-28 13:20:22 +02007030 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03007031
7032 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007033
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007034 /* p1 and p2 divider */
7035 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7036 5 << DPIO_CHV_S1_DIV_SHIFT |
7037 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7038 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7039 1 << DPIO_CHV_K_DIV_SHIFT);
7040
7041 /* Feedback post-divider - m2 */
7042 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7043
7044 /* Feedback refclk divider - n and m1 */
7045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7046 DPIO_CHV_M1_DIV_BY_2 |
7047 1 << DPIO_CHV_N_DIV_SHIFT);
7048
7049 /* M2 fraction division */
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307050 if (bestm2_frac)
7051 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007052
7053 /* M2 fraction division enable */
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307054 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7055 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7056 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7057 if (bestm2_frac)
7058 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7059 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007060
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05307061 /* Program digital lock detect threshold */
7062 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7063 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7064 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7065 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7066 if (!bestm2_frac)
7067 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7068 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7069
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007070 /* Loop filter */
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307071 if (vco == 5400000) {
7072 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7073 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7074 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7075 tribuf_calcntr = 0x9;
7076 } else if (vco <= 6200000) {
7077 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7078 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7079 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7080 tribuf_calcntr = 0x9;
7081 } else if (vco <= 6480000) {
7082 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7083 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7084 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7085 tribuf_calcntr = 0x8;
7086 } else {
7087 /* Not supported. Apply the same limits as in the max case */
7088 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7089 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7090 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7091 tribuf_calcntr = 0;
7092 }
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007093 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7094
Ville Syrjälä968040b2015-03-11 22:52:08 +02007095 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307096 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7097 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7098 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7099
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007100 /* AFC Recal */
7101 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7102 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7103 DPIO_AFC_RECAL);
7104
7105 mutex_unlock(&dev_priv->dpio_lock);
7106}
7107
Ville Syrjäläd288f652014-10-28 13:20:22 +02007108/**
7109 * vlv_force_pll_on - forcibly enable just the PLL
7110 * @dev_priv: i915 private structure
7111 * @pipe: pipe PLL to enable
7112 * @dpll: PLL configuration
7113 *
7114 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7115 * in cases where we need the PLL enabled even when @pipe is not going to
7116 * be enabled.
7117 */
7118void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7119 const struct dpll *dpll)
7120{
7121 struct intel_crtc *crtc =
7122 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007123 struct intel_crtc_state pipe_config = {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007124 .base.crtc = &crtc->base,
Ville Syrjäläd288f652014-10-28 13:20:22 +02007125 .pixel_multiplier = 1,
7126 .dpll = *dpll,
7127 };
7128
7129 if (IS_CHERRYVIEW(dev)) {
7130 chv_update_pll(crtc, &pipe_config);
7131 chv_prepare_pll(crtc, &pipe_config);
7132 chv_enable_pll(crtc, &pipe_config);
7133 } else {
7134 vlv_update_pll(crtc, &pipe_config);
7135 vlv_prepare_pll(crtc, &pipe_config);
7136 vlv_enable_pll(crtc, &pipe_config);
7137 }
7138}
7139
7140/**
7141 * vlv_force_pll_off - forcibly disable just the PLL
7142 * @dev_priv: i915 private structure
7143 * @pipe: pipe PLL to disable
7144 *
7145 * Disable the PLL for @pipe. To be used in cases where we need
7146 * the PLL enabled even when @pipe is not going to be enabled.
7147 */
7148void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7149{
7150 if (IS_CHERRYVIEW(dev))
7151 chv_disable_pll(to_i915(dev), pipe);
7152 else
7153 vlv_disable_pll(to_i915(dev), pipe);
7154}
7155
Daniel Vetterf47709a2013-03-28 10:42:02 +01007156static void i9xx_update_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007157 struct intel_crtc_state *crtc_state,
Daniel Vetterf47709a2013-03-28 10:42:02 +01007158 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007159 int num_connectors)
7160{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007161 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007162 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007163 u32 dpll;
7164 bool is_sdvo;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007165 struct dpll *clock = &crtc_state->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007166
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007167 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05307168
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007169 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7170 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007171
7172 dpll = DPLL_VGA_MODE_DIS;
7173
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007174 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007175 dpll |= DPLLB_MODE_LVDS;
7176 else
7177 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007178
Daniel Vetteref1b4602013-06-01 17:17:04 +02007179 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007180 dpll |= (crtc_state->pixel_multiplier - 1)
Daniel Vetter198a037f2013-04-19 11:14:37 +02007181 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007182 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02007183
7184 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007185 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007186
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007187 if (crtc_state->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007188 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007189
7190 /* compute bitmask from p1 value */
7191 if (IS_PINEVIEW(dev))
7192 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7193 else {
7194 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7195 if (IS_G4X(dev) && reduced_clock)
7196 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7197 }
7198 switch (clock->p2) {
7199 case 5:
7200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7201 break;
7202 case 7:
7203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7204 break;
7205 case 10:
7206 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7207 break;
7208 case 14:
7209 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7210 break;
7211 }
7212 if (INTEL_INFO(dev)->gen >= 4)
7213 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7214
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007215 if (crtc_state->sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007216 dpll |= PLL_REF_INPUT_TVCLKINBC;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007217 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007218 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7219 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7220 else
7221 dpll |= PLL_REF_INPUT_DREFCLK;
7222
7223 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007224 crtc_state->dpll_hw_state.dpll = dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02007225
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007226 if (INTEL_INFO(dev)->gen >= 4) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007227 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02007228 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007229 crtc_state->dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007230 }
7231}
7232
Daniel Vetterf47709a2013-03-28 10:42:02 +01007233static void i8xx_update_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007234 struct intel_crtc_state *crtc_state,
Daniel Vetterf47709a2013-03-28 10:42:02 +01007235 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007236 int num_connectors)
7237{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007238 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007239 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007240 u32 dpll;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007241 struct dpll *clock = &crtc_state->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007242
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007243 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05307244
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007245 dpll = DPLL_VGA_MODE_DIS;
7246
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007247 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007248 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7249 } else {
7250 if (clock->p1 == 2)
7251 dpll |= PLL_P1_DIVIDE_BY_TWO;
7252 else
7253 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7254 if (clock->p2 == 4)
7255 dpll |= PLL_P2_DIVIDE_BY_4;
7256 }
7257
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007258 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
Daniel Vetter4a33e482013-07-06 12:52:05 +02007259 dpll |= DPLL_DVO_2X_MODE;
7260
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007261 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007262 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7263 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7264 else
7265 dpll |= PLL_REF_INPUT_DREFCLK;
7266
7267 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007268 crtc_state->dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007269}
7270
Daniel Vetter8a654f32013-06-01 17:16:22 +02007271static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007272{
7273 struct drm_device *dev = intel_crtc->base.dev;
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007276 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02007277 struct drm_display_mode *adjusted_mode =
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007278 &intel_crtc->config->base.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02007279 uint32_t crtc_vtotal, crtc_vblank_end;
7280 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007281
7282 /* We need to be careful not to changed the adjusted mode, for otherwise
7283 * the hw state checker will get angry at the mismatch. */
7284 crtc_vtotal = adjusted_mode->crtc_vtotal;
7285 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007286
Ville Syrjälä609aeac2014-03-28 23:29:30 +02007287 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007288 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007289 crtc_vtotal -= 1;
7290 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02007291
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007292 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjälä609aeac2014-03-28 23:29:30 +02007293 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7294 else
7295 vsyncshift = adjusted_mode->crtc_hsync_start -
7296 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02007297 if (vsyncshift < 0)
7298 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007299 }
7300
7301 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007302 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007303
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007304 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007305 (adjusted_mode->crtc_hdisplay - 1) |
7306 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007307 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007308 (adjusted_mode->crtc_hblank_start - 1) |
7309 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007310 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007311 (adjusted_mode->crtc_hsync_start - 1) |
7312 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7313
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007314 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007315 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007316 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007317 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007318 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007319 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007320 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007321 (adjusted_mode->crtc_vsync_start - 1) |
7322 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7323
Paulo Zanonib5e508d2012-10-24 11:34:43 -02007324 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7325 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7326 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7327 * bits. */
7328 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7329 (pipe == PIPE_B || pipe == PIPE_C))
7330 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7331
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007332 /* pipesrc controls the size that is scaled from, which should
7333 * always be the user's requested size.
7334 */
7335 I915_WRITE(PIPESRC(pipe),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007336 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7337 (intel_crtc->config->pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007338}
7339
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007340static void intel_get_pipe_timings(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007341 struct intel_crtc_state *pipe_config)
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007342{
7343 struct drm_device *dev = crtc->base.dev;
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7346 uint32_t tmp;
7347
7348 tmp = I915_READ(HTOTAL(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007349 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007351 tmp = I915_READ(HBLANK(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007352 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7353 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007354 tmp = I915_READ(HSYNC(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007355 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7356 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007357
7358 tmp = I915_READ(VTOTAL(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007359 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7360 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007361 tmp = I915_READ(VBLANK(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007362 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7363 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007364 tmp = I915_READ(VSYNC(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007365 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7366 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007367
7368 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007369 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7370 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7371 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007372 }
7373
7374 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03007375 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7376 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7377
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007378 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7379 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007380}
7381
Daniel Vetterf6a83282014-02-11 15:28:57 -08007382void intel_mode_from_pipe_config(struct drm_display_mode *mode,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007383 struct intel_crtc_state *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03007384{
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007385 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7386 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7387 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7388 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03007389
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007390 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7391 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7392 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7393 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03007394
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007395 mode->flags = pipe_config->base.adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03007396
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007397 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7398 mode->flags |= pipe_config->base.adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03007399}
7400
Daniel Vetter84b046f2013-02-19 18:48:54 +01007401static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7402{
7403 struct drm_device *dev = intel_crtc->base.dev;
7404 struct drm_i915_private *dev_priv = dev->dev_private;
7405 uint32_t pipeconf;
7406
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02007407 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01007408
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03007409 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7410 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7411 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
Daniel Vetter67c72a12013-09-24 11:46:14 +02007412
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007413 if (intel_crtc->config->double_wide)
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007414 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01007415
Daniel Vetterff9ce462013-04-24 14:57:17 +02007416 /* only g4x and later have fancy bpc/dither controls */
7417 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02007418 /* Bspec claims that we can't use dithering for 30bpp pipes. */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007419 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
Daniel Vetterff9ce462013-04-24 14:57:17 +02007420 pipeconf |= PIPECONF_DITHER_EN |
7421 PIPECONF_DITHER_TYPE_SP;
7422
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007423 switch (intel_crtc->config->pipe_bpp) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02007424 case 18:
7425 pipeconf |= PIPECONF_6BPC;
7426 break;
7427 case 24:
7428 pipeconf |= PIPECONF_8BPC;
7429 break;
7430 case 30:
7431 pipeconf |= PIPECONF_10BPC;
7432 break;
7433 default:
7434 /* Case prevented by intel_choose_pipe_bpp_dither. */
7435 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01007436 }
7437 }
7438
7439 if (HAS_PIPE_CXSR(dev)) {
7440 if (intel_crtc->lowfreq_avail) {
7441 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7442 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7443 } else {
7444 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01007445 }
7446 }
7447
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007448 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02007449 if (INTEL_INFO(dev)->gen < 4 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007450 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02007451 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7452 else
7453 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7454 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01007455 pipeconf |= PIPECONF_PROGRESSIVE;
7456
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007457 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02007458 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03007459
Daniel Vetter84b046f2013-02-19 18:48:54 +01007460 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7461 POSTING_READ(PIPECONF(intel_crtc->pipe));
7462}
7463
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007464static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7465 struct intel_crtc_state *crtc_state)
Jesse Barnes79e53942008-11-07 14:24:08 -08007466{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007467 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007468 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholtc751ce42010-03-25 11:48:48 -07007469 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07007470 intel_clock_t clock, reduced_clock;
Daniel Vettera16af722013-04-30 14:01:44 +02007471 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007472 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01007473 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08007474 const intel_limit_t *limit;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02007475 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03007476 struct drm_connector *connector;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02007477 struct drm_connector_state *connector_state;
7478 int i;
Jesse Barnes79e53942008-11-07 14:24:08 -08007479
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03007480 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02007481 if (connector_state->crtc != &crtc->base)
7482 continue;
7483
7484 encoder = to_intel_encoder(connector_state->best_encoder);
7485
Chris Wilson5eddb702010-09-11 13:48:45 +01007486 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007487 case INTEL_OUTPUT_LVDS:
7488 is_lvds = true;
7489 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007490 case INTEL_OUTPUT_DSI:
7491 is_dsi = true;
7492 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02007493 default:
7494 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007495 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007496
Eric Anholtc751ce42010-03-25 11:48:48 -07007497 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08007498 }
7499
Jani Nikulaf2335332013-09-13 11:03:09 +03007500 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02007501 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007502
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007503 if (!crtc_state->clock_set) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007504 refclk = i9xx_get_refclk(crtc_state, num_connectors);
Jani Nikulaf2335332013-09-13 11:03:09 +03007505
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007506 /*
7507 * Returns a set of divisors for the desired target clock with
7508 * the given refclk, or FALSE. The returned values represent
7509 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7510 * 2) / p1 / p2.
7511 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007512 limit = intel_limit(crtc_state, refclk);
7513 ok = dev_priv->display.find_dpll(limit, crtc_state,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007514 crtc_state->port_clock,
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007515 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03007516 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007517 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7518 return -EINVAL;
7519 }
Eric Anholtf564048e2011-03-30 13:01:02 -07007520
Jani Nikulaf2335332013-09-13 11:03:09 +03007521 if (is_lvds && dev_priv->lvds_downclock_avail) {
7522 /*
7523 * Ensure we match the reduced clock's P to the target
7524 * clock. If the clocks don't match, we can't switch
7525 * the display clock by using the FP0/FP1. In such case
7526 * we will disable the LVDS downclock feature.
7527 */
7528 has_reduced_clock =
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007529 dev_priv->display.find_dpll(limit, crtc_state,
Jani Nikulaf2335332013-09-13 11:03:09 +03007530 dev_priv->lvds_downclock,
7531 refclk, &clock,
7532 &reduced_clock);
7533 }
7534 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007535 crtc_state->dpll.n = clock.n;
7536 crtc_state->dpll.m1 = clock.m1;
7537 crtc_state->dpll.m2 = clock.m2;
7538 crtc_state->dpll.p1 = clock.p1;
7539 crtc_state->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007540 }
Eric Anholtf564048e2011-03-30 13:01:02 -07007541
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007542 if (IS_GEN2(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007543 i8xx_update_pll(crtc, crtc_state,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05307544 has_reduced_clock ? &reduced_clock : NULL,
7545 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007546 } else if (IS_CHERRYVIEW(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007547 chv_update_pll(crtc, crtc_state);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007548 } else if (IS_VALLEYVIEW(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007549 vlv_update_pll(crtc, crtc_state);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007550 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007551 i9xx_update_pll(crtc, crtc_state,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007552 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02007553 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007554 }
Eric Anholtf564048e2011-03-30 13:01:02 -07007555
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007556 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07007557}
7558
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007559static void i9xx_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007560 struct intel_crtc_state *pipe_config)
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007561{
7562 struct drm_device *dev = crtc->base.dev;
7563 struct drm_i915_private *dev_priv = dev->dev_private;
7564 uint32_t tmp;
7565
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02007566 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7567 return;
7568
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007569 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02007570 if (!(tmp & PFIT_ENABLE))
7571 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007572
Daniel Vetter06922822013-07-11 13:35:40 +02007573 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007574 if (INTEL_INFO(dev)->gen < 4) {
7575 if (crtc->pipe != PIPE_B)
7576 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007577 } else {
7578 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7579 return;
7580 }
7581
Daniel Vetter06922822013-07-11 13:35:40 +02007582 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007583 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7584 if (INTEL_INFO(dev)->gen < 5)
7585 pipe_config->gmch_pfit.lvds_border_bits =
7586 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7587}
7588
Jesse Barnesacbec812013-09-20 11:29:32 -07007589static void vlv_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007590 struct intel_crtc_state *pipe_config)
Jesse Barnesacbec812013-09-20 11:29:32 -07007591{
7592 struct drm_device *dev = crtc->base.dev;
7593 struct drm_i915_private *dev_priv = dev->dev_private;
7594 int pipe = pipe_config->cpu_transcoder;
7595 intel_clock_t clock;
7596 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07007597 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07007598
Shobhit Kumarf573de52014-07-30 20:32:37 +05307599 /* In case of MIPI DPLL will not even be used */
7600 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7601 return;
7602
Jesse Barnesacbec812013-09-20 11:29:32 -07007603 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007604 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07007605 mutex_unlock(&dev_priv->dpio_lock);
7606
7607 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7608 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7609 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7610 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7611 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7612
Ville Syrjäläf6466282013-10-14 14:50:31 +03007613 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07007614
Ville Syrjäläf6466282013-10-14 14:50:31 +03007615 /* clock.dot is the fast clock */
7616 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07007617}
7618
Damien Lespiau5724dbd2015-01-20 12:51:52 +00007619static void
7620i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7621 struct intel_initial_plane_config *plane_config)
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007622{
7623 struct drm_device *dev = crtc->base.dev;
7624 struct drm_i915_private *dev_priv = dev->dev_private;
7625 u32 val, base, offset;
7626 int pipe = crtc->pipe, plane = crtc->plane;
7627 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00007628 unsigned int aligned_height;
Damien Lespiaub113d5e2015-01-20 12:51:46 +00007629 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00007630 struct intel_framebuffer *intel_fb;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007631
Damien Lespiau42a7b082015-02-05 19:35:13 +00007632 val = I915_READ(DSPCNTR(plane));
7633 if (!(val & DISPLAY_PLANE_ENABLE))
7634 return;
7635
Damien Lespiaud9806c92015-01-21 14:07:19 +00007636 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00007637 if (!intel_fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007638 DRM_DEBUG_KMS("failed to alloc fb\n");
7639 return;
7640 }
7641
Damien Lespiau1b842c82015-01-21 13:50:54 +00007642 fb = &intel_fb->base;
7643
Daniel Vetter18c52472015-02-10 17:16:09 +00007644 if (INTEL_INFO(dev)->gen >= 4) {
7645 if (val & DISPPLANE_TILED) {
Damien Lespiau49af4492015-01-20 12:51:44 +00007646 plane_config->tiling = I915_TILING_X;
Daniel Vetter18c52472015-02-10 17:16:09 +00007647 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7648 }
7649 }
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007650
7651 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
Damien Lespiaub35d63f2015-01-20 12:51:50 +00007652 fourcc = i9xx_format_to_fourcc(pixel_format);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00007653 fb->pixel_format = fourcc;
7654 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007655
7656 if (INTEL_INFO(dev)->gen >= 4) {
Damien Lespiau49af4492015-01-20 12:51:44 +00007657 if (plane_config->tiling)
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007658 offset = I915_READ(DSPTILEOFF(plane));
7659 else
7660 offset = I915_READ(DSPLINOFF(plane));
7661 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7662 } else {
7663 base = I915_READ(DSPADDR(plane));
7664 }
7665 plane_config->base = base;
7666
7667 val = I915_READ(PIPESRC(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00007668 fb->width = ((val >> 16) & 0xfff) + 1;
7669 fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007670
7671 val = I915_READ(DSPSTRIDE(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00007672 fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007673
Damien Lespiaub113d5e2015-01-20 12:51:46 +00007674 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00007675 fb->pixel_format,
7676 fb->modifier[0]);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007677
Daniel Vetterf37b5c22015-02-10 23:12:27 +01007678 plane_config->size = fb->pitches[0] * aligned_height;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007679
Damien Lespiau2844a922015-01-20 12:51:48 +00007680 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7681 pipe_name(pipe), plane, fb->width, fb->height,
7682 fb->bits_per_pixel, base, fb->pitches[0],
7683 plane_config->size);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007684
Damien Lespiau2d140302015-02-05 17:22:18 +00007685 plane_config->fb = intel_fb;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08007686}
7687
Ville Syrjälä70b23a92014-04-09 13:28:22 +03007688static void chv_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007689 struct intel_crtc_state *pipe_config)
Ville Syrjälä70b23a92014-04-09 13:28:22 +03007690{
7691 struct drm_device *dev = crtc->base.dev;
7692 struct drm_i915_private *dev_priv = dev->dev_private;
7693 int pipe = pipe_config->cpu_transcoder;
7694 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7695 intel_clock_t clock;
7696 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7697 int refclk = 100000;
7698
7699 mutex_lock(&dev_priv->dpio_lock);
7700 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7701 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7702 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7703 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7704 mutex_unlock(&dev_priv->dpio_lock);
7705
7706 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7707 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7708 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7709 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7710 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7711
7712 chv_clock(refclk, &clock);
7713
7714 /* clock.dot is the fast clock */
7715 pipe_config->port_clock = clock.dot / 5;
7716}
7717
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007718static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007719 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007720{
7721 struct drm_device *dev = crtc->base.dev;
7722 struct drm_i915_private *dev_priv = dev->dev_private;
7723 uint32_t tmp;
7724
Daniel Vetterf458ebb2014-09-30 10:56:39 +02007725 if (!intel_display_power_is_enabled(dev_priv,
7726 POWER_DOMAIN_PIPE(crtc->pipe)))
Imre Deakb5482bd2014-03-05 16:20:55 +02007727 return false;
7728
Daniel Vettere143a212013-07-04 12:01:15 +02007729 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007730 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007731
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007732 tmp = I915_READ(PIPECONF(crtc->pipe));
7733 if (!(tmp & PIPECONF_ENABLE))
7734 return false;
7735
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007736 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7737 switch (tmp & PIPECONF_BPC_MASK) {
7738 case PIPECONF_6BPC:
7739 pipe_config->pipe_bpp = 18;
7740 break;
7741 case PIPECONF_8BPC:
7742 pipe_config->pipe_bpp = 24;
7743 break;
7744 case PIPECONF_10BPC:
7745 pipe_config->pipe_bpp = 30;
7746 break;
7747 default:
7748 break;
7749 }
7750 }
7751
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007752 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7753 pipe_config->limited_color_range = true;
7754
Ville Syrjälä282740f2013-09-04 18:30:03 +03007755 if (INTEL_INFO(dev)->gen < 4)
7756 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7757
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007758 intel_get_pipe_timings(crtc, pipe_config);
7759
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007760 i9xx_get_pfit_config(crtc, pipe_config);
7761
Daniel Vetter6c49f242013-06-06 12:45:25 +02007762 if (INTEL_INFO(dev)->gen >= 4) {
7763 tmp = I915_READ(DPLL_MD(crtc->pipe));
7764 pipe_config->pixel_multiplier =
7765 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7766 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02007767 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02007768 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7769 tmp = I915_READ(DPLL(crtc->pipe));
7770 pipe_config->pixel_multiplier =
7771 ((tmp & SDVO_MULTIPLIER_MASK)
7772 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7773 } else {
7774 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7775 * port and will be fixed up in the encoder->get_config
7776 * function. */
7777 pipe_config->pixel_multiplier = 1;
7778 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02007779 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7780 if (!IS_VALLEYVIEW(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03007781 /*
7782 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7783 * on 830. Filter it out here so that we don't
7784 * report errors due to that.
7785 */
7786 if (IS_I830(dev))
7787 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7788
Daniel Vetter8bcc2792013-06-05 13:34:28 +02007789 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7790 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03007791 } else {
7792 /* Mask out read-only status bits. */
7793 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7794 DPLL_PORTC_READY_MASK |
7795 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02007796 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02007797
Ville Syrjälä70b23a92014-04-09 13:28:22 +03007798 if (IS_CHERRYVIEW(dev))
7799 chv_crtc_clock_get(crtc, pipe_config);
7800 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07007801 vlv_crtc_clock_get(crtc, pipe_config);
7802 else
7803 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03007804
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007805 return true;
7806}
7807
Paulo Zanonidde86e22012-12-01 12:04:25 -02007808static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07007809{
7810 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007811 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007812 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007813 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07007814 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07007815 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07007816 bool has_ck505 = false;
7817 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007818
7819 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01007820 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07007821 switch (encoder->type) {
7822 case INTEL_OUTPUT_LVDS:
7823 has_panel = true;
7824 has_lvds = true;
7825 break;
7826 case INTEL_OUTPUT_EDP:
7827 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03007828 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07007829 has_cpu_edp = true;
7830 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02007831 default:
7832 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007833 }
7834 }
7835
Keith Packard99eb6a02011-09-26 14:29:12 -07007836 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03007837 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07007838 can_ssc = has_ck505;
7839 } else {
7840 has_ck505 = false;
7841 can_ssc = true;
7842 }
7843
Imre Deak2de69052013-05-08 13:14:04 +03007844 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7845 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07007846
7847 /* Ironlake: try to setup display ref clock before DPLL
7848 * enabling. This is only under driver's control after
7849 * PCH B stepping, previous chipset stepping should be
7850 * ignoring this setting.
7851 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007852 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07007853
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007854 /* As we must carefully and slowly disable/enable each source in turn,
7855 * compute the final state we want first and check if we need to
7856 * make any changes at all.
7857 */
7858 final = val;
7859 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07007860 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007861 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07007862 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007863 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7864
7865 final &= ~DREF_SSC_SOURCE_MASK;
7866 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7867 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007868
Keith Packard199e5d72011-09-22 12:01:57 -07007869 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007870 final |= DREF_SSC_SOURCE_ENABLE;
7871
7872 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7873 final |= DREF_SSC1_ENABLE;
7874
7875 if (has_cpu_edp) {
7876 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7877 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7878 else
7879 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7880 } else
7881 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7882 } else {
7883 final |= DREF_SSC_SOURCE_DISABLE;
7884 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7885 }
7886
7887 if (final == val)
7888 return;
7889
7890 /* Always enable nonspread source */
7891 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7892
7893 if (has_ck505)
7894 val |= DREF_NONSPREAD_CK505_ENABLE;
7895 else
7896 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7897
7898 if (has_panel) {
7899 val &= ~DREF_SSC_SOURCE_MASK;
7900 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007901
Keith Packard199e5d72011-09-22 12:01:57 -07007902 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07007903 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07007904 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007905 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02007906 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007907 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07007908
7909 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007910 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07007911 POSTING_READ(PCH_DREF_CONTROL);
7912 udelay(200);
7913
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007914 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07007915
7916 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07007917 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07007918 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07007919 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007920 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02007921 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007922 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07007923 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007924 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07007925
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007926 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07007927 POSTING_READ(PCH_DREF_CONTROL);
7928 udelay(200);
7929 } else {
7930 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7931
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007932 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07007933
7934 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007935 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07007936
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007937 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07007938 POSTING_READ(PCH_DREF_CONTROL);
7939 udelay(200);
7940
7941 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007942 val &= ~DREF_SSC_SOURCE_MASK;
7943 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07007944
7945 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007946 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07007947
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007948 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07007949 POSTING_READ(PCH_DREF_CONTROL);
7950 udelay(200);
7951 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07007952
7953 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07007954}
7955
Paulo Zanonif31f2d52013-07-18 18:51:11 -03007956static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02007957{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03007958 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02007959
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03007960 tmp = I915_READ(SOUTH_CHICKEN2);
7961 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7962 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02007963
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03007964 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7965 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7966 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02007967
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03007968 tmp = I915_READ(SOUTH_CHICKEN2);
7969 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7970 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02007971
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03007972 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7973 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7974 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03007975}
7976
7977/* WaMPhyProgramming:hsw */
7978static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7979{
7980 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02007981
7982 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7983 tmp &= ~(0xFF << 24);
7984 tmp |= (0x12 << 24);
7985 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7986
Paulo Zanonidde86e22012-12-01 12:04:25 -02007987 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7988 tmp |= (1 << 11);
7989 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7990
7991 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7992 tmp |= (1 << 11);
7993 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7994
Paulo Zanonidde86e22012-12-01 12:04:25 -02007995 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7996 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7997 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7998
7999 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8000 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8001 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8002
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008003 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8004 tmp &= ~(7 << 13);
8005 tmp |= (5 << 13);
8006 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008007
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008008 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8009 tmp &= ~(7 << 13);
8010 tmp |= (5 << 13);
8011 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008012
8013 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8014 tmp &= ~0xFF;
8015 tmp |= 0x1C;
8016 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8017
8018 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8019 tmp &= ~0xFF;
8020 tmp |= 0x1C;
8021 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8022
8023 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8024 tmp &= ~(0xFF << 16);
8025 tmp |= (0x1C << 16);
8026 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8027
8028 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8029 tmp &= ~(0xFF << 16);
8030 tmp |= (0x1C << 16);
8031 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8032
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008033 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8034 tmp |= (1 << 27);
8035 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008036
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008037 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8038 tmp |= (1 << 27);
8039 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008040
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008041 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8042 tmp &= ~(0xF << 28);
8043 tmp |= (4 << 28);
8044 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008045
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008046 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8047 tmp &= ~(0xF << 28);
8048 tmp |= (4 << 28);
8049 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008050}
8051
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008052/* Implements 3 different sequences from BSpec chapter "Display iCLK
8053 * Programming" based on the parameters passed:
8054 * - Sequence to enable CLKOUT_DP
8055 * - Sequence to enable CLKOUT_DP without spread
8056 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8057 */
8058static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8059 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008060{
8061 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008062 uint32_t reg, tmp;
8063
8064 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8065 with_spread = true;
8066 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8067 with_fdi, "LP PCH doesn't have FDI\n"))
8068 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008069
8070 mutex_lock(&dev_priv->dpio_lock);
8071
8072 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8073 tmp &= ~SBI_SSCCTL_DISABLE;
8074 tmp |= SBI_SSCCTL_PATHALT;
8075 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8076
8077 udelay(24);
8078
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008079 if (with_spread) {
8080 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8081 tmp &= ~SBI_SSCCTL_PATHALT;
8082 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008083
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008084 if (with_fdi) {
8085 lpt_reset_fdi_mphy(dev_priv);
8086 lpt_program_fdi_mphy(dev_priv);
8087 }
8088 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02008089
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008090 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8091 SBI_GEN0 : SBI_DBUFF0;
8092 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8093 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8094 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01008095
8096 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008097}
8098
Paulo Zanoni47701c32013-07-23 11:19:25 -03008099/* Sequence to disable CLKOUT_DP */
8100static void lpt_disable_clkout_dp(struct drm_device *dev)
8101{
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 uint32_t reg, tmp;
8104
8105 mutex_lock(&dev_priv->dpio_lock);
8106
8107 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8108 SBI_GEN0 : SBI_DBUFF0;
8109 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8110 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8111 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8112
8113 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8114 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8115 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8116 tmp |= SBI_SSCCTL_PATHALT;
8117 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8118 udelay(32);
8119 }
8120 tmp |= SBI_SSCCTL_DISABLE;
8121 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8122 }
8123
8124 mutex_unlock(&dev_priv->dpio_lock);
8125}
8126
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008127static void lpt_init_pch_refclk(struct drm_device *dev)
8128{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008129 struct intel_encoder *encoder;
8130 bool has_vga = false;
8131
Damien Lespiaub2784e12014-08-05 11:29:37 +01008132 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008133 switch (encoder->type) {
8134 case INTEL_OUTPUT_ANALOG:
8135 has_vga = true;
8136 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008137 default:
8138 break;
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008139 }
8140 }
8141
Paulo Zanoni47701c32013-07-23 11:19:25 -03008142 if (has_vga)
8143 lpt_enable_clkout_dp(dev, true, true);
8144 else
8145 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008146}
8147
Paulo Zanonidde86e22012-12-01 12:04:25 -02008148/*
8149 * Initialize reference clocks when the driver loads
8150 */
8151void intel_init_pch_refclk(struct drm_device *dev)
8152{
8153 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8154 ironlake_init_pch_refclk(dev);
8155 else if (HAS_PCH_LPT(dev))
8156 lpt_init_pch_refclk(dev);
8157}
8158
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008159static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008160{
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008161 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008162 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008163 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008164 struct drm_connector *connector;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008165 struct drm_connector_state *connector_state;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008166 struct intel_encoder *encoder;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008167 int num_connectors = 0, i;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008168 bool is_lvds = false;
8169
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008170 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008171 if (connector_state->crtc != crtc_state->base.crtc)
8172 continue;
8173
8174 encoder = to_intel_encoder(connector_state->best_encoder);
8175
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008176 switch (encoder->type) {
8177 case INTEL_OUTPUT_LVDS:
8178 is_lvds = true;
8179 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008180 default:
8181 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008182 }
8183 num_connectors++;
8184 }
8185
8186 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008187 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03008188 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008189 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008190 }
8191
8192 return 120000;
8193}
8194
Daniel Vetter6ff93602013-04-19 11:24:36 +02008195static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03008196{
8197 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8199 int pipe = intel_crtc->pipe;
8200 uint32_t val;
8201
Daniel Vetter78114072013-06-13 00:54:57 +02008202 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03008203
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008204 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03008205 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008206 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008207 break;
8208 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008209 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008210 break;
8211 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008212 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008213 break;
8214 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008215 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008216 break;
8217 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03008218 /* Case prevented by intel_choose_pipe_bpp_dither. */
8219 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03008220 }
8221
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008222 if (intel_crtc->config->dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03008223 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8224
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008225 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03008226 val |= PIPECONF_INTERLACED_ILK;
8227 else
8228 val |= PIPECONF_PROGRESSIVE;
8229
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008230 if (intel_crtc->config->limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02008231 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02008232
Paulo Zanonic8203562012-09-12 10:06:29 -03008233 I915_WRITE(PIPECONF(pipe), val);
8234 POSTING_READ(PIPECONF(pipe));
8235}
8236
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008237/*
8238 * Set up the pipe CSC unit.
8239 *
8240 * Currently only full range RGB to limited range RGB conversion
8241 * is supported, but eventually this should handle various
8242 * RGB<->YCbCr scenarios as well.
8243 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01008244static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008245{
8246 struct drm_device *dev = crtc->dev;
8247 struct drm_i915_private *dev_priv = dev->dev_private;
8248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8249 int pipe = intel_crtc->pipe;
8250 uint16_t coeff = 0x7800; /* 1.0 */
8251
8252 /*
8253 * TODO: Check what kind of values actually come out of the pipe
8254 * with these coeff/postoff values and adjust to get the best
8255 * accuracy. Perhaps we even need to take the bpc value into
8256 * consideration.
8257 */
8258
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008259 if (intel_crtc->config->limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008260 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8261
8262 /*
8263 * GY/GU and RY/RU should be the other way around according
8264 * to BSpec, but reality doesn't agree. Just set them up in
8265 * a way that results in the correct picture.
8266 */
8267 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8268 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8269
8270 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8271 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8272
8273 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8274 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8275
8276 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8277 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8278 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8279
8280 if (INTEL_INFO(dev)->gen > 6) {
8281 uint16_t postoff = 0;
8282
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008283 if (intel_crtc->config->limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02008284 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008285
8286 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8287 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8288 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8289
8290 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8291 } else {
8292 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8293
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008294 if (intel_crtc->config->limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008295 mode |= CSC_BLACK_SCREEN_OFFSET;
8296
8297 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8298 }
8299}
8300
Daniel Vetter6ff93602013-04-19 11:24:36 +02008301static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008302{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008303 struct drm_device *dev = crtc->dev;
8304 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008306 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008307 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008308 uint32_t val;
8309
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02008310 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008311
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008312 if (IS_HASWELL(dev) && intel_crtc->config->dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008313 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8314
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008315 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008316 val |= PIPECONF_INTERLACED_ILK;
8317 else
8318 val |= PIPECONF_PROGRESSIVE;
8319
Paulo Zanoni702e7a52012-10-23 18:29:59 -02008320 I915_WRITE(PIPECONF(cpu_transcoder), val);
8321 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02008322
8323 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8324 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008325
Satheeshakrishna M3cdf122c2014-04-08 15:46:53 +05308326 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008327 val = 0;
8328
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008329 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008330 case 18:
8331 val |= PIPEMISC_DITHER_6_BPC;
8332 break;
8333 case 24:
8334 val |= PIPEMISC_DITHER_8_BPC;
8335 break;
8336 case 30:
8337 val |= PIPEMISC_DITHER_10_BPC;
8338 break;
8339 case 36:
8340 val |= PIPEMISC_DITHER_12_BPC;
8341 break;
8342 default:
8343 /* Case prevented by pipe_config_set_bpp. */
8344 BUG();
8345 }
8346
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008347 if (intel_crtc->config->dither)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008348 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8349
8350 I915_WRITE(PIPEMISC(pipe), val);
8351 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008352}
8353
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008354static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008355 struct intel_crtc_state *crtc_state,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008356 intel_clock_t *clock,
8357 bool *has_reduced_clock,
8358 intel_clock_t *reduced_clock)
8359{
8360 struct drm_device *dev = crtc->dev;
8361 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008362 int refclk;
8363 const intel_limit_t *limit;
Daniel Vettera16af722013-04-30 14:01:44 +02008364 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008365
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02008366 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008367
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008368 refclk = ironlake_get_refclk(crtc_state);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008369
8370 /*
8371 * Returns a set of divisors for the desired target clock with the given
8372 * refclk, or FALSE. The returned values represent the clock equation:
8373 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8374 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02008375 limit = intel_limit(crtc_state, refclk);
8376 ret = dev_priv->display.find_dpll(limit, crtc_state,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008377 crtc_state->port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02008378 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008379 if (!ret)
8380 return false;
8381
8382 if (is_lvds && dev_priv->lvds_downclock_avail) {
8383 /*
8384 * Ensure we match the reduced clock's P to the target clock.
8385 * If the clocks don't match, we can't switch the display clock
8386 * by using the FP0/FP1. In such case we will disable the LVDS
8387 * downclock feature.
8388 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02008389 *has_reduced_clock =
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02008390 dev_priv->display.find_dpll(limit, crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +02008391 dev_priv->lvds_downclock,
8392 refclk, clock,
8393 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008394 }
8395
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008396 return true;
8397}
8398
Paulo Zanonid4b19312012-11-29 11:29:32 -02008399int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8400{
8401 /*
8402 * Account for spread spectrum to avoid
8403 * oversubscribing the link. Max center spread
8404 * is 2.5%; use 5% for safety's sake.
8405 */
8406 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02008407 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02008408}
8409
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008410static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02008411{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008412 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03008413}
8414
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008415static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008416 struct intel_crtc_state *crtc_state,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008417 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02008418 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008419{
8420 struct drm_crtc *crtc = &intel_crtc->base;
8421 struct drm_device *dev = crtc->dev;
8422 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008423 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008424 struct drm_connector *connector;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008425 struct drm_connector_state *connector_state;
8426 struct intel_encoder *encoder;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008427 uint32_t dpll;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008428 int factor, num_connectors = 0, i;
Daniel Vetter09ede542013-04-30 14:01:45 +02008429 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008430
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008431 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008432 if (connector_state->crtc != crtc_state->base.crtc)
8433 continue;
8434
8435 encoder = to_intel_encoder(connector_state->best_encoder);
8436
8437 switch (encoder->type) {
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008438 case INTEL_OUTPUT_LVDS:
8439 is_lvds = true;
8440 break;
8441 case INTEL_OUTPUT_SDVO:
8442 case INTEL_OUTPUT_HDMI:
8443 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008444 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008445 default:
8446 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008447 }
8448
8449 num_connectors++;
8450 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008451
Chris Wilsonc1858122010-12-03 21:35:48 +00008452 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07008453 factor = 21;
8454 if (is_lvds) {
8455 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008456 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02008457 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07008458 factor = 25;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008459 } else if (crtc_state->sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07008460 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00008461
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008462 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02008463 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00008464
Daniel Vetter9a7c7892013-04-04 22:20:34 +02008465 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8466 *fp2 |= FP_CB_TUNE;
8467
Chris Wilson5eddb702010-09-11 13:48:45 +01008468 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08008469
Eric Anholta07d6782011-03-30 13:01:08 -07008470 if (is_lvds)
8471 dpll |= DPLLB_MODE_LVDS;
8472 else
8473 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02008474
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008475 dpll |= (crtc_state->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02008476 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02008477
8478 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02008479 dpll |= DPLL_SDVO_HIGH_SPEED;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008480 if (crtc_state->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02008481 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08008482
Eric Anholta07d6782011-03-30 13:01:08 -07008483 /* compute bitmask from p1 value */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008484 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07008485 /* also FPA1 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008486 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07008487
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008488 switch (crtc_state->dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07008489 case 5:
8490 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8491 break;
8492 case 7:
8493 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8494 break;
8495 case 10:
8496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8497 break;
8498 case 14:
8499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8500 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08008501 }
8502
Daniel Vetterb4c09f32013-04-30 14:01:42 +02008503 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05008504 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08008505 else
8506 dpll |= PLL_REF_INPUT_DREFCLK;
8507
Daniel Vetter959e16d2013-06-05 13:34:21 +02008508 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008509}
8510
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008511static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8512 struct intel_crtc_state *crtc_state)
Jesse Barnes79e53942008-11-07 14:24:08 -08008513{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008514 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008515 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02008516 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03008517 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01008518 bool is_lvds = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02008519 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008520
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03008521 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
Jesse Barnes79e53942008-11-07 14:24:08 -08008522
Paulo Zanoni5dc52982012-10-05 12:05:56 -03008523 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8524 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8525
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008526 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008527 &has_reduced_clock, &reduced_clock);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008528 if (!ok && !crtc_state->clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008529 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8530 return -EINVAL;
8531 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01008532 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008533 if (!crtc_state->clock_set) {
8534 crtc_state->dpll.n = clock.n;
8535 crtc_state->dpll.m1 = clock.m1;
8536 crtc_state->dpll.m2 = clock.m2;
8537 crtc_state->dpll.p1 = clock.p1;
8538 crtc_state->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01008539 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008540
Paulo Zanoni5dc52982012-10-05 12:05:56 -03008541 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008542 if (crtc_state->has_pch_encoder) {
8543 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02008544 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008545 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02008546
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008547 dpll = ironlake_compute_dpll(crtc, crtc_state,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02008548 &fp, &reduced_clock,
8549 has_reduced_clock ? &fp2 : NULL);
8550
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008551 crtc_state->dpll_hw_state.dpll = dpll;
8552 crtc_state->dpll_hw_state.fp0 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02008553 if (has_reduced_clock)
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008554 crtc_state->dpll_hw_state.fp1 = fp2;
Daniel Vetter66e985c2013-06-05 13:34:20 +02008555 else
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008556 crtc_state->dpll_hw_state.fp1 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02008557
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008558 pll = intel_get_shared_dpll(crtc, crtc_state);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008559 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03008560 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008561 pipe_name(crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07008562 return -EINVAL;
8563 }
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02008564 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008565
Rodrigo Viviab585de2015-03-24 12:40:09 -07008566 if (is_lvds && has_reduced_clock)
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008567 crtc->lowfreq_avail = true;
Daniel Vetterbcd644e2013-06-05 13:34:22 +02008568 else
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008569 crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02008570
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02008571 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008572}
8573
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008574static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8575 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02008576{
8577 struct drm_device *dev = crtc->base.dev;
8578 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008579 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02008580
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008581 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8582 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8583 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8584 & ~TU_SIZE_MASK;
8585 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8586 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8587 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8588}
8589
8590static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8591 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07008592 struct intel_link_m_n *m_n,
8593 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008594{
8595 struct drm_device *dev = crtc->base.dev;
8596 struct drm_i915_private *dev_priv = dev->dev_private;
8597 enum pipe pipe = crtc->pipe;
8598
8599 if (INTEL_INFO(dev)->gen >= 5) {
8600 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8601 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8602 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8603 & ~TU_SIZE_MASK;
8604 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8605 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8606 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07008607 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8608 * gen < 8) and if DRRS is supported (to make sure the
8609 * registers are not unnecessarily read).
8610 */
8611 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008612 crtc->config->has_drrs) {
Vandana Kannanb95af8b2014-08-05 07:51:23 -07008613 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8614 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8615 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8616 & ~TU_SIZE_MASK;
8617 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8618 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8619 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8620 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008621 } else {
8622 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8623 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8624 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8625 & ~TU_SIZE_MASK;
8626 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8627 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8628 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8629 }
8630}
8631
8632void intel_dp_get_m_n(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008633 struct intel_crtc_state *pipe_config)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008634{
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02008635 if (pipe_config->has_pch_encoder)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008636 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8637 else
8638 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07008639 &pipe_config->dp_m_n,
8640 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008641}
8642
Daniel Vetter72419202013-04-04 13:28:53 +02008643static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008644 struct intel_crtc_state *pipe_config)
Daniel Vetter72419202013-04-04 13:28:53 +02008645{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008646 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07008647 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02008648}
8649
Jesse Barnesbd2e2442014-11-13 17:51:47 +00008650static void skylake_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008651 struct intel_crtc_state *pipe_config)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00008652{
8653 struct drm_device *dev = crtc->base.dev;
8654 struct drm_i915_private *dev_priv = dev->dev_private;
Chandra Kondurua1b22782015-04-07 15:28:45 -07008655 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8656 uint32_t ps_ctrl = 0;
8657 int id = -1;
8658 int i;
Jesse Barnesbd2e2442014-11-13 17:51:47 +00008659
Chandra Kondurua1b22782015-04-07 15:28:45 -07008660 /* find scaler attached to this pipe */
8661 for (i = 0; i < crtc->num_scalers; i++) {
8662 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8663 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8664 id = i;
8665 pipe_config->pch_pfit.enabled = true;
8666 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8667 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8668 break;
8669 }
8670 }
Jesse Barnesbd2e2442014-11-13 17:51:47 +00008671
Chandra Kondurua1b22782015-04-07 15:28:45 -07008672 scaler_state->scaler_id = id;
8673 if (id >= 0) {
8674 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8675 } else {
8676 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00008677 }
8678}
8679
Damien Lespiau5724dbd2015-01-20 12:51:52 +00008680static void
8681skylake_get_initial_plane_config(struct intel_crtc *crtc,
8682 struct intel_initial_plane_config *plane_config)
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008683{
8684 struct drm_device *dev = crtc->base.dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau40f46282015-02-27 11:15:21 +00008686 u32 val, base, offset, stride_mult, tiling;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008687 int pipe = crtc->pipe;
8688 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00008689 unsigned int aligned_height;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008690 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00008691 struct intel_framebuffer *intel_fb;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008692
Damien Lespiaud9806c92015-01-21 14:07:19 +00008693 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00008694 if (!intel_fb) {
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008695 DRM_DEBUG_KMS("failed to alloc fb\n");
8696 return;
8697 }
8698
Damien Lespiau1b842c82015-01-21 13:50:54 +00008699 fb = &intel_fb->base;
8700
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008701 val = I915_READ(PLANE_CTL(pipe, 0));
Damien Lespiau42a7b082015-02-05 19:35:13 +00008702 if (!(val & PLANE_CTL_ENABLE))
8703 goto error;
8704
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008705 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8706 fourcc = skl_format_to_fourcc(pixel_format,
8707 val & PLANE_CTL_ORDER_RGBX,
8708 val & PLANE_CTL_ALPHA_MASK);
8709 fb->pixel_format = fourcc;
8710 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8711
Damien Lespiau40f46282015-02-27 11:15:21 +00008712 tiling = val & PLANE_CTL_TILED_MASK;
8713 switch (tiling) {
8714 case PLANE_CTL_TILED_LINEAR:
8715 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8716 break;
8717 case PLANE_CTL_TILED_X:
8718 plane_config->tiling = I915_TILING_X;
8719 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8720 break;
8721 case PLANE_CTL_TILED_Y:
8722 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8723 break;
8724 case PLANE_CTL_TILED_YF:
8725 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8726 break;
8727 default:
8728 MISSING_CASE(tiling);
8729 goto error;
8730 }
8731
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008732 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8733 plane_config->base = base;
8734
8735 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8736
8737 val = I915_READ(PLANE_SIZE(pipe, 0));
8738 fb->height = ((val >> 16) & 0xfff) + 1;
8739 fb->width = ((val >> 0) & 0x1fff) + 1;
8740
8741 val = I915_READ(PLANE_STRIDE(pipe, 0));
Damien Lespiau40f46282015-02-27 11:15:21 +00008742 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8743 fb->pixel_format);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008744 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8745
8746 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00008747 fb->pixel_format,
8748 fb->modifier[0]);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008749
Daniel Vetterf37b5c22015-02-10 23:12:27 +01008750 plane_config->size = fb->pitches[0] * aligned_height;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008751
8752 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8753 pipe_name(pipe), fb->width, fb->height,
8754 fb->bits_per_pixel, base, fb->pitches[0],
8755 plane_config->size);
8756
Damien Lespiau2d140302015-02-05 17:22:18 +00008757 plane_config->fb = intel_fb;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00008758 return;
8759
8760error:
8761 kfree(fb);
8762}
8763
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008764static void ironlake_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008765 struct intel_crtc_state *pipe_config)
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008766{
8767 struct drm_device *dev = crtc->base.dev;
8768 struct drm_i915_private *dev_priv = dev->dev_private;
8769 uint32_t tmp;
8770
8771 tmp = I915_READ(PF_CTL(crtc->pipe));
8772
8773 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01008774 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008775 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8776 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02008777
8778 /* We currently do not free assignements of panel fitters on
8779 * ivb/hsw (since we don't use the higher upscaling modes which
8780 * differentiates them) so just WARN about this case for now. */
8781 if (IS_GEN7(dev)) {
8782 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8783 PF_PIPE_SEL_IVB(crtc->pipe));
8784 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008785 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008786}
8787
Damien Lespiau5724dbd2015-01-20 12:51:52 +00008788static void
8789ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8790 struct intel_initial_plane_config *plane_config)
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008791{
8792 struct drm_device *dev = crtc->base.dev;
8793 struct drm_i915_private *dev_priv = dev->dev_private;
8794 u32 val, base, offset;
Damien Lespiauaeee5a42015-01-20 12:51:47 +00008795 int pipe = crtc->pipe;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008796 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00008797 unsigned int aligned_height;
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008798 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00008799 struct intel_framebuffer *intel_fb;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008800
Damien Lespiau42a7b082015-02-05 19:35:13 +00008801 val = I915_READ(DSPCNTR(pipe));
8802 if (!(val & DISPLAY_PLANE_ENABLE))
8803 return;
8804
Damien Lespiaud9806c92015-01-21 14:07:19 +00008805 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00008806 if (!intel_fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008807 DRM_DEBUG_KMS("failed to alloc fb\n");
8808 return;
8809 }
8810
Damien Lespiau1b842c82015-01-21 13:50:54 +00008811 fb = &intel_fb->base;
8812
Daniel Vetter18c52472015-02-10 17:16:09 +00008813 if (INTEL_INFO(dev)->gen >= 4) {
8814 if (val & DISPPLANE_TILED) {
Damien Lespiau49af4492015-01-20 12:51:44 +00008815 plane_config->tiling = I915_TILING_X;
Daniel Vetter18c52472015-02-10 17:16:09 +00008816 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8817 }
8818 }
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008819
8820 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
Damien Lespiaub35d63f2015-01-20 12:51:50 +00008821 fourcc = i9xx_format_to_fourcc(pixel_format);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008822 fb->pixel_format = fourcc;
8823 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008824
Damien Lespiauaeee5a42015-01-20 12:51:47 +00008825 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008826 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiauaeee5a42015-01-20 12:51:47 +00008827 offset = I915_READ(DSPOFFSET(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008828 } else {
Damien Lespiau49af4492015-01-20 12:51:44 +00008829 if (plane_config->tiling)
Damien Lespiauaeee5a42015-01-20 12:51:47 +00008830 offset = I915_READ(DSPTILEOFF(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008831 else
Damien Lespiauaeee5a42015-01-20 12:51:47 +00008832 offset = I915_READ(DSPLINOFF(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008833 }
8834 plane_config->base = base;
8835
8836 val = I915_READ(PIPESRC(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008837 fb->width = ((val >> 16) & 0xfff) + 1;
8838 fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008839
8840 val = I915_READ(DSPSTRIDE(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008841 fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008842
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008843 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00008844 fb->pixel_format,
8845 fb->modifier[0]);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008846
Daniel Vetterf37b5c22015-02-10 23:12:27 +01008847 plane_config->size = fb->pitches[0] * aligned_height;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008848
Damien Lespiau2844a922015-01-20 12:51:48 +00008849 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8850 pipe_name(pipe), fb->width, fb->height,
8851 fb->bits_per_pixel, base, fb->pitches[0],
8852 plane_config->size);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008853
Damien Lespiau2d140302015-02-05 17:22:18 +00008854 plane_config->fb = intel_fb;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08008855}
8856
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008857static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008858 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008859{
8860 struct drm_device *dev = crtc->base.dev;
8861 struct drm_i915_private *dev_priv = dev->dev_private;
8862 uint32_t tmp;
8863
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008864 if (!intel_display_power_is_enabled(dev_priv,
8865 POWER_DOMAIN_PIPE(crtc->pipe)))
Paulo Zanoni930e8c92014-07-04 13:38:34 -03008866 return false;
8867
Daniel Vettere143a212013-07-04 12:01:15 +02008868 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008869 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02008870
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008871 tmp = I915_READ(PIPECONF(crtc->pipe));
8872 if (!(tmp & PIPECONF_ENABLE))
8873 return false;
8874
Ville Syrjälä42571ae2013-09-06 23:29:00 +03008875 switch (tmp & PIPECONF_BPC_MASK) {
8876 case PIPECONF_6BPC:
8877 pipe_config->pipe_bpp = 18;
8878 break;
8879 case PIPECONF_8BPC:
8880 pipe_config->pipe_bpp = 24;
8881 break;
8882 case PIPECONF_10BPC:
8883 pipe_config->pipe_bpp = 30;
8884 break;
8885 case PIPECONF_12BPC:
8886 pipe_config->pipe_bpp = 36;
8887 break;
8888 default:
8889 break;
8890 }
8891
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02008892 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8893 pipe_config->limited_color_range = true;
8894
Daniel Vetterab9412b2013-05-03 11:49:46 +02008895 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02008896 struct intel_shared_dpll *pll;
8897
Daniel Vetter88adfff2013-03-28 10:42:01 +01008898 pipe_config->has_pch_encoder = true;
8899
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008900 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8901 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8902 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02008903
8904 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02008905
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008906 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02008907 pipe_config->shared_dpll =
8908 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008909 } else {
8910 tmp = I915_READ(PCH_DPLL_SEL);
8911 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8912 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8913 else
8914 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8915 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02008916
8917 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8918
8919 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8920 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02008921
8922 tmp = pipe_config->dpll_hw_state.dpll;
8923 pipe_config->pixel_multiplier =
8924 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8925 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008926
8927 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02008928 } else {
8929 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008930 }
8931
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008932 intel_get_pipe_timings(crtc, pipe_config);
8933
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008934 ironlake_get_pfit_config(crtc, pipe_config);
8935
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008936 return true;
8937}
8938
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008939static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8940{
8941 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008942 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008943
Damien Lespiaud3fcc802014-05-13 23:32:22 +01008944 for_each_intel_crtc(dev, crtc)
Rob Clarke2c719b2014-12-15 13:56:32 -05008945 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008946 pipe_name(crtc->pipe));
8947
Rob Clarke2c719b2014-12-15 13:56:32 -05008948 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8949 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8950 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8951 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8952 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8953 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008954 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03008955 if (IS_HASWELL(dev))
Rob Clarke2c719b2014-12-15 13:56:32 -05008956 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
Paulo Zanonic5107b82014-07-04 11:50:30 -03008957 "CPU PWM2 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05008958 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008959 "PCH PWM1 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05008960 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008961 "Utility pin enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05008962 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008963
Paulo Zanoni9926ada2014-04-01 19:39:47 -03008964 /*
8965 * In theory we can still leave IRQs enabled, as long as only the HPD
8966 * interrupts remain enabled. We used to check for that, but since it's
8967 * gen-specific and since we only disable LCPLL after we fully disable
8968 * the interrupts, the check below should be enough.
8969 */
Rob Clarke2c719b2014-12-15 13:56:32 -05008970 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008971}
8972
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03008973static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8974{
8975 struct drm_device *dev = dev_priv->dev;
8976
8977 if (IS_HASWELL(dev))
8978 return I915_READ(D_COMP_HSW);
8979 else
8980 return I915_READ(D_COMP_BDW);
8981}
8982
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03008983static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8984{
8985 struct drm_device *dev = dev_priv->dev;
8986
8987 if (IS_HASWELL(dev)) {
8988 mutex_lock(&dev_priv->rps.hw_lock);
8989 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8990 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03008991 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03008992 mutex_unlock(&dev_priv->rps.hw_lock);
8993 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03008994 I915_WRITE(D_COMP_BDW, val);
8995 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03008996 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008997}
8998
8999/*
9000 * This function implements pieces of two sequences from BSpec:
9001 * - Sequence for display software to disable LCPLL
9002 * - Sequence for display software to allow package C8+
9003 * The steps implemented here are just the steps that actually touch the LCPLL
9004 * register. Callers should take care of disabling all the display engine
9005 * functions, doing the mode unset, fixing interrupts, etc.
9006 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03009007static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9008 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009009{
9010 uint32_t val;
9011
9012 assert_can_disable_lcpll(dev_priv);
9013
9014 val = I915_READ(LCPLL_CTL);
9015
9016 if (switch_to_fclk) {
9017 val |= LCPLL_CD_SOURCE_FCLK;
9018 I915_WRITE(LCPLL_CTL, val);
9019
9020 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9021 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9022 DRM_ERROR("Switching to FCLK failed\n");
9023
9024 val = I915_READ(LCPLL_CTL);
9025 }
9026
9027 val |= LCPLL_PLL_DISABLE;
9028 I915_WRITE(LCPLL_CTL, val);
9029 POSTING_READ(LCPLL_CTL);
9030
9031 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9032 DRM_ERROR("LCPLL still locked\n");
9033
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009034 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009035 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009036 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009037 ndelay(100);
9038
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009039 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9040 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009041 DRM_ERROR("D_COMP RCOMP still in progress\n");
9042
9043 if (allow_power_down) {
9044 val = I915_READ(LCPLL_CTL);
9045 val |= LCPLL_POWER_DOWN_ALLOW;
9046 I915_WRITE(LCPLL_CTL, val);
9047 POSTING_READ(LCPLL_CTL);
9048 }
9049}
9050
9051/*
9052 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9053 * source.
9054 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03009055static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009056{
9057 uint32_t val;
9058
9059 val = I915_READ(LCPLL_CTL);
9060
9061 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9062 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9063 return;
9064
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03009065 /*
9066 * Make sure we're not on PC8 state before disabling PC8, otherwise
9067 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03009068 */
Mika Kuoppala59bad942015-01-16 11:34:40 +02009069 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Paulo Zanoni215733f2013-08-19 13:18:07 -03009070
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009071 if (val & LCPLL_POWER_DOWN_ALLOW) {
9072 val &= ~LCPLL_POWER_DOWN_ALLOW;
9073 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02009074 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009075 }
9076
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009077 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009078 val |= D_COMP_COMP_FORCE;
9079 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009080 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009081
9082 val = I915_READ(LCPLL_CTL);
9083 val &= ~LCPLL_PLL_DISABLE;
9084 I915_WRITE(LCPLL_CTL, val);
9085
9086 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9087 DRM_ERROR("LCPLL not locked yet\n");
9088
9089 if (val & LCPLL_CD_SOURCE_FCLK) {
9090 val = I915_READ(LCPLL_CTL);
9091 val &= ~LCPLL_CD_SOURCE_FCLK;
9092 I915_WRITE(LCPLL_CTL, val);
9093
9094 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9095 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9096 DRM_ERROR("Switching back to LCPLL failed\n");
9097 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03009098
Mika Kuoppala59bad942015-01-16 11:34:40 +02009099 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009100}
9101
Paulo Zanoni765dab672014-03-07 20:08:18 -03009102/*
9103 * Package states C8 and deeper are really deep PC states that can only be
9104 * reached when all the devices on the system allow it, so even if the graphics
9105 * device allows PC8+, it doesn't mean the system will actually get to these
9106 * states. Our driver only allows PC8+ when going into runtime PM.
9107 *
9108 * The requirements for PC8+ are that all the outputs are disabled, the power
9109 * well is disabled and most interrupts are disabled, and these are also
9110 * requirements for runtime PM. When these conditions are met, we manually do
9111 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9112 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9113 * hang the machine.
9114 *
9115 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9116 * the state of some registers, so when we come back from PC8+ we need to
9117 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9118 * need to take care of the registers kept by RC6. Notice that this happens even
9119 * if we don't put the device in PCI D3 state (which is what currently happens
9120 * because of the runtime PM support).
9121 *
9122 * For more, read "Display Sequences for Package C8" on the hardware
9123 * documentation.
9124 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03009125void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03009126{
Paulo Zanonic67a4702013-08-19 13:18:09 -03009127 struct drm_device *dev = dev_priv->dev;
9128 uint32_t val;
9129
Paulo Zanonic67a4702013-08-19 13:18:09 -03009130 DRM_DEBUG_KMS("Enabling package C8+\n");
9131
Paulo Zanonic67a4702013-08-19 13:18:09 -03009132 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9133 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9134 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9135 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9136 }
9137
9138 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009139 hsw_disable_lcpll(dev_priv, true, true);
9140}
9141
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03009142void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03009143{
9144 struct drm_device *dev = dev_priv->dev;
9145 uint32_t val;
9146
Paulo Zanonic67a4702013-08-19 13:18:09 -03009147 DRM_DEBUG_KMS("Disabling package C8+\n");
9148
9149 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009150 lpt_init_pch_refclk(dev);
9151
9152 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9153 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9154 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9155 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9156 }
9157
9158 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009159}
9160
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03009161static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309162{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03009163 struct drm_device *dev = old_state->dev;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309164 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03009165 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309166 int req_cdclk;
9167
9168 /* see the comment in valleyview_modeset_global_resources */
9169 if (WARN_ON(max_pixclk < 0))
9170 return;
9171
9172 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9173
9174 if (req_cdclk != dev_priv->cdclk_freq)
9175 broxton_set_cdclk(dev, req_cdclk);
9176}
9177
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009178static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9179 struct intel_crtc_state *crtc_state)
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03009180{
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009181 if (!intel_ddi_pll_select(crtc, crtc_state))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009182 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03009183
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009184 crtc->lowfreq_avail = false;
Daniel Vetter644cef32014-04-24 23:55:07 +02009185
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02009186 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08009187}
9188
Satheeshakrishna M3760b592014-08-22 09:49:11 +05309189static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9190 enum port port,
9191 struct intel_crtc_state *pipe_config)
9192{
9193 switch (port) {
9194 case PORT_A:
9195 pipe_config->ddi_pll_sel = SKL_DPLL0;
9196 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9197 break;
9198 case PORT_B:
9199 pipe_config->ddi_pll_sel = SKL_DPLL1;
9200 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9201 break;
9202 case PORT_C:
9203 pipe_config->ddi_pll_sel = SKL_DPLL2;
9204 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9205 break;
9206 default:
9207 DRM_ERROR("Incorrect port type\n");
9208 }
9209}
9210
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009211static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9212 enum port port,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009213 struct intel_crtc_state *pipe_config)
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009214{
Damien Lespiau3148ade2014-11-21 16:14:56 +00009215 u32 temp, dpll_ctl1;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009216
9217 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9218 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9219
9220 switch (pipe_config->ddi_pll_sel) {
Damien Lespiau3148ade2014-11-21 16:14:56 +00009221 case SKL_DPLL0:
9222 /*
9223 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9224 * of the shared DPLL framework and thus needs to be read out
9225 * separately
9226 */
9227 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9228 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9229 break;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009230 case SKL_DPLL1:
9231 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9232 break;
9233 case SKL_DPLL2:
9234 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9235 break;
9236 case SKL_DPLL3:
9237 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9238 break;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009239 }
9240}
9241
Damien Lespiau7d2c8172014-07-29 18:06:18 +01009242static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9243 enum port port,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009244 struct intel_crtc_state *pipe_config)
Damien Lespiau7d2c8172014-07-29 18:06:18 +01009245{
9246 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9247
9248 switch (pipe_config->ddi_pll_sel) {
9249 case PORT_CLK_SEL_WRPLL1:
9250 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9251 break;
9252 case PORT_CLK_SEL_WRPLL2:
9253 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9254 break;
9255 }
9256}
9257
Daniel Vetter26804af2014-06-25 22:01:55 +03009258static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009259 struct intel_crtc_state *pipe_config)
Daniel Vetter26804af2014-06-25 22:01:55 +03009260{
9261 struct drm_device *dev = crtc->base.dev;
9262 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03009263 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03009264 enum port port;
9265 uint32_t tmp;
9266
9267 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9268
9269 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9270
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009271 if (IS_SKYLAKE(dev))
9272 skylake_get_ddi_pll(dev_priv, port, pipe_config);
Satheeshakrishna M3760b592014-08-22 09:49:11 +05309273 else if (IS_BROXTON(dev))
9274 bxt_get_ddi_pll(dev_priv, port, pipe_config);
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009275 else
9276 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03009277
Daniel Vetterd452c5b2014-07-04 11:27:39 -03009278 if (pipe_config->shared_dpll >= 0) {
9279 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9280
9281 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9282 &pipe_config->dpll_hw_state));
9283 }
9284
Daniel Vetter26804af2014-06-25 22:01:55 +03009285 /*
9286 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9287 * DDI E. So just check whether this pipe is wired to DDI E and whether
9288 * the PCH transcoder is on.
9289 */
Damien Lespiauca370452013-12-03 13:56:24 +00009290 if (INTEL_INFO(dev)->gen < 9 &&
9291 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter26804af2014-06-25 22:01:55 +03009292 pipe_config->has_pch_encoder = true;
9293
9294 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9295 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9296 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9297
9298 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9299 }
9300}
9301
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009302static bool haswell_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009303 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009304{
9305 struct drm_device *dev = crtc->base.dev;
9306 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009307 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009308 uint32_t tmp;
9309
Daniel Vetterf458ebb2014-09-30 10:56:39 +02009310 if (!intel_display_power_is_enabled(dev_priv,
Imre Deakb5482bd2014-03-05 16:20:55 +02009311 POWER_DOMAIN_PIPE(crtc->pipe)))
9312 return false;
9313
Daniel Vettere143a212013-07-04 12:01:15 +02009314 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009315 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9316
Daniel Vettereccb1402013-05-22 00:50:22 +02009317 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9318 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9319 enum pipe trans_edp_pipe;
9320 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9321 default:
9322 WARN(1, "unknown pipe linked to edp transcoder\n");
9323 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9324 case TRANS_DDI_EDP_INPUT_A_ON:
9325 trans_edp_pipe = PIPE_A;
9326 break;
9327 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9328 trans_edp_pipe = PIPE_B;
9329 break;
9330 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9331 trans_edp_pipe = PIPE_C;
9332 break;
9333 }
9334
9335 if (trans_edp_pipe == crtc->pipe)
9336 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9337 }
9338
Daniel Vetterf458ebb2014-09-30 10:56:39 +02009339 if (!intel_display_power_is_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02009340 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03009341 return false;
9342
Daniel Vettereccb1402013-05-22 00:50:22 +02009343 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009344 if (!(tmp & PIPECONF_ENABLE))
9345 return false;
9346
Daniel Vetter26804af2014-06-25 22:01:55 +03009347 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009348
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009349 intel_get_pipe_timings(crtc, pipe_config);
9350
Chandra Kondurua1b22782015-04-07 15:28:45 -07009351 if (INTEL_INFO(dev)->gen >= 9) {
9352 skl_init_scalers(dev, crtc, pipe_config);
9353 }
9354
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009355 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009356 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
Jesse Barnesff6d9f52015-01-21 17:19:54 -08009357 if (INTEL_INFO(dev)->gen == 9)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009358 skylake_get_pfit_config(crtc, pipe_config);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08009359 else if (INTEL_INFO(dev)->gen < 9)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009360 ironlake_get_pfit_config(crtc, pipe_config);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08009361 else
9362 MISSING_CASE(INTEL_INFO(dev)->gen);
9363
Chandra Kondurua1b22782015-04-07 15:28:45 -07009364 } else {
9365 pipe_config->scaler_state.scaler_id = -1;
9366 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009367 }
Daniel Vetter88adfff2013-03-28 10:42:01 +01009368
Jesse Barnese59150d2014-01-07 13:30:45 -08009369 if (IS_HASWELL(dev))
9370 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9371 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009372
Clint Taylorebb69c92014-09-30 10:30:22 -07009373 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9374 pipe_config->pixel_multiplier =
9375 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9376 } else {
9377 pipe_config->pixel_multiplier = 1;
9378 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02009379
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009380 return true;
9381}
9382
Chris Wilson560b85b2010-08-07 11:01:38 +01009383static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9384{
9385 struct drm_device *dev = crtc->dev;
9386 struct drm_i915_private *dev_priv = dev->dev_private;
9387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +03009388 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01009389
Ville Syrjälädc41c152014-08-13 11:57:05 +03009390 if (base) {
Matt Roper3dd512f2015-02-27 10:12:00 -08009391 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9392 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
Ville Syrjälädc41c152014-08-13 11:57:05 +03009393 unsigned int stride = roundup_pow_of_two(width) * 4;
9394
9395 switch (stride) {
9396 default:
9397 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9398 width, stride);
9399 stride = 256;
9400 /* fallthrough */
9401 case 256:
9402 case 512:
9403 case 1024:
9404 case 2048:
9405 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +03009406 }
9407
Ville Syrjälädc41c152014-08-13 11:57:05 +03009408 cntl |= CURSOR_ENABLE |
9409 CURSOR_GAMMA_ENABLE |
9410 CURSOR_FORMAT_ARGB |
9411 CURSOR_STRIDE(stride);
9412
9413 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +03009414 }
Chris Wilson560b85b2010-08-07 11:01:38 +01009415
Ville Syrjälädc41c152014-08-13 11:57:05 +03009416 if (intel_crtc->cursor_cntl != 0 &&
9417 (intel_crtc->cursor_base != base ||
9418 intel_crtc->cursor_size != size ||
9419 intel_crtc->cursor_cntl != cntl)) {
9420 /* On these chipsets we can only modify the base/size/stride
9421 * whilst the cursor is disabled.
9422 */
9423 I915_WRITE(_CURACNTR, 0);
9424 POSTING_READ(_CURACNTR);
9425 intel_crtc->cursor_cntl = 0;
9426 }
9427
Ville Syrjälä99d1f382014-09-12 20:53:32 +03009428 if (intel_crtc->cursor_base != base) {
Ville Syrjälädc41c152014-08-13 11:57:05 +03009429 I915_WRITE(_CURABASE, base);
Ville Syrjälä99d1f382014-09-12 20:53:32 +03009430 intel_crtc->cursor_base = base;
9431 }
Ville Syrjälädc41c152014-08-13 11:57:05 +03009432
9433 if (intel_crtc->cursor_size != size) {
9434 I915_WRITE(CURSIZE, size);
9435 intel_crtc->cursor_size = size;
9436 }
9437
Chris Wilson4b0e3332014-05-30 16:35:26 +03009438 if (intel_crtc->cursor_cntl != cntl) {
9439 I915_WRITE(_CURACNTR, cntl);
9440 POSTING_READ(_CURACNTR);
9441 intel_crtc->cursor_cntl = cntl;
9442 }
Chris Wilson560b85b2010-08-07 11:01:38 +01009443}
9444
9445static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9446{
9447 struct drm_device *dev = crtc->dev;
9448 struct drm_i915_private *dev_priv = dev->dev_private;
9449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9450 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03009451 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01009452
Chris Wilson4b0e3332014-05-30 16:35:26 +03009453 cntl = 0;
9454 if (base) {
9455 cntl = MCURSOR_GAMMA_ENABLE;
Matt Roper3dd512f2015-02-27 10:12:00 -08009456 switch (intel_crtc->base.cursor->state->crtc_w) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05309457 case 64:
9458 cntl |= CURSOR_MODE_64_ARGB_AX;
9459 break;
9460 case 128:
9461 cntl |= CURSOR_MODE_128_ARGB_AX;
9462 break;
9463 case 256:
9464 cntl |= CURSOR_MODE_256_ARGB_AX;
9465 break;
9466 default:
Matt Roper3dd512f2015-02-27 10:12:00 -08009467 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
Sagar Kamble4726e0b2014-03-10 17:06:23 +05309468 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01009469 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03009470 cntl |= pipe << 28; /* Connect to correct pipe */
Ville Syrjälä47bf17a2014-09-12 20:53:33 +03009471
9472 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9473 cntl |= CURSOR_PIPE_CSC_ENABLE;
Chris Wilson560b85b2010-08-07 11:01:38 +01009474 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03009475
Matt Roper8e7d6882015-01-21 16:35:41 -08009476 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
Ville Syrjälä4398ad42014-10-23 07:41:34 -07009477 cntl |= CURSOR_ROTATE_180;
9478
Chris Wilson4b0e3332014-05-30 16:35:26 +03009479 if (intel_crtc->cursor_cntl != cntl) {
9480 I915_WRITE(CURCNTR(pipe), cntl);
9481 POSTING_READ(CURCNTR(pipe));
9482 intel_crtc->cursor_cntl = cntl;
9483 }
9484
Jesse Barnes65a21cd2011-10-12 11:10:21 -07009485 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03009486 I915_WRITE(CURBASE(pipe), base);
9487 POSTING_READ(CURBASE(pipe));
Ville Syrjälä99d1f382014-09-12 20:53:32 +03009488
9489 intel_crtc->cursor_base = base;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07009490}
9491
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009492/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01009493static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9494 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009495{
9496 struct drm_device *dev = crtc->dev;
9497 struct drm_i915_private *dev_priv = dev->dev_private;
9498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9499 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07009500 int x = crtc->cursor_x;
9501 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03009502 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009503
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03009504 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009505 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009506
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009507 if (x >= intel_crtc->config->pipe_src_w)
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03009508 base = 0;
9509
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009510 if (y >= intel_crtc->config->pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009511 base = 0;
9512
9513 if (x < 0) {
Matt Roper3dd512f2015-02-27 10:12:00 -08009514 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009515 base = 0;
9516
9517 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9518 x = -x;
9519 }
9520 pos |= x << CURSOR_X_SHIFT;
9521
9522 if (y < 0) {
Matt Roper3dd512f2015-02-27 10:12:00 -08009523 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009524 base = 0;
9525
9526 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9527 y = -y;
9528 }
9529 pos |= y << CURSOR_Y_SHIFT;
9530
Chris Wilson4b0e3332014-05-30 16:35:26 +03009531 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009532 return;
9533
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03009534 I915_WRITE(CURPOS(pipe), pos);
9535
Ville Syrjälä4398ad42014-10-23 07:41:34 -07009536 /* ILK+ do this automagically */
9537 if (HAS_GMCH_DISPLAY(dev) &&
Matt Roper8e7d6882015-01-21 16:35:41 -08009538 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
Matt Roper3dd512f2015-02-27 10:12:00 -08009539 base += (intel_crtc->base.cursor->state->crtc_h *
9540 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
Ville Syrjälä4398ad42014-10-23 07:41:34 -07009541 }
9542
Ville Syrjälä8ac54662014-08-12 19:39:54 +03009543 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03009544 i845_update_cursor(crtc, base);
9545 else
9546 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01009547}
9548
Ville Syrjälädc41c152014-08-13 11:57:05 +03009549static bool cursor_size_ok(struct drm_device *dev,
9550 uint32_t width, uint32_t height)
9551{
9552 if (width == 0 || height == 0)
9553 return false;
9554
9555 /*
9556 * 845g/865g are special in that they are only limited by
9557 * the width of their cursors, the height is arbitrary up to
9558 * the precision of the register. Everything else requires
9559 * square cursors, limited to a few power-of-two sizes.
9560 */
9561 if (IS_845G(dev) || IS_I865G(dev)) {
9562 if ((width & 63) != 0)
9563 return false;
9564
9565 if (width > (IS_845G(dev) ? 64 : 512))
9566 return false;
9567
9568 if (height > 1023)
9569 return false;
9570 } else {
9571 switch (width | height) {
9572 case 256:
9573 case 128:
9574 if (IS_GEN2(dev))
9575 return false;
9576 case 64:
9577 break;
9578 default:
9579 return false;
9580 }
9581 }
9582
9583 return true;
9584}
9585
Jesse Barnes79e53942008-11-07 14:24:08 -08009586static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01009587 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08009588{
James Simmons72034252010-08-03 01:33:19 +01009589 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08009590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08009591
James Simmons72034252010-08-03 01:33:19 +01009592 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08009593 intel_crtc->lut_r[i] = red[i] >> 8;
9594 intel_crtc->lut_g[i] = green[i] >> 8;
9595 intel_crtc->lut_b[i] = blue[i] >> 8;
9596 }
9597
9598 intel_crtc_load_lut(crtc);
9599}
9600
Jesse Barnes79e53942008-11-07 14:24:08 -08009601/* VESA 640x480x72Hz mode to set on the pipe */
9602static struct drm_display_mode load_detect_mode = {
9603 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9604 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9605};
9606
Daniel Vettera8bb6812014-02-10 18:00:39 +01009607struct drm_framebuffer *
9608__intel_framebuffer_create(struct drm_device *dev,
9609 struct drm_mode_fb_cmd2 *mode_cmd,
9610 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01009611{
9612 struct intel_framebuffer *intel_fb;
9613 int ret;
9614
9615 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9616 if (!intel_fb) {
Alexey Khoroshilov6ccb81f2014-11-08 01:41:23 +03009617 drm_gem_object_unreference(&obj->base);
Chris Wilsond2dff872011-04-19 08:36:26 +01009618 return ERR_PTR(-ENOMEM);
9619 }
9620
9621 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02009622 if (ret)
9623 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01009624
9625 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02009626err:
Alexey Khoroshilov6ccb81f2014-11-08 01:41:23 +03009627 drm_gem_object_unreference(&obj->base);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02009628 kfree(intel_fb);
9629
9630 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01009631}
9632
Daniel Vetterb5ea6422014-03-02 21:18:00 +01009633static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01009634intel_framebuffer_create(struct drm_device *dev,
9635 struct drm_mode_fb_cmd2 *mode_cmd,
9636 struct drm_i915_gem_object *obj)
9637{
9638 struct drm_framebuffer *fb;
9639 int ret;
9640
9641 ret = i915_mutex_lock_interruptible(dev);
9642 if (ret)
9643 return ERR_PTR(ret);
9644 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9645 mutex_unlock(&dev->struct_mutex);
9646
9647 return fb;
9648}
9649
Chris Wilsond2dff872011-04-19 08:36:26 +01009650static u32
9651intel_framebuffer_pitch_for_width(int width, int bpp)
9652{
9653 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9654 return ALIGN(pitch, 64);
9655}
9656
9657static u32
9658intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9659{
9660 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02009661 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01009662}
9663
9664static struct drm_framebuffer *
9665intel_framebuffer_create_for_mode(struct drm_device *dev,
9666 struct drm_display_mode *mode,
9667 int depth, int bpp)
9668{
9669 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00009670 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01009671
9672 obj = i915_gem_alloc_object(dev,
9673 intel_framebuffer_size_for_mode(mode, bpp));
9674 if (obj == NULL)
9675 return ERR_PTR(-ENOMEM);
9676
9677 mode_cmd.width = mode->hdisplay;
9678 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009679 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9680 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00009681 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01009682
9683 return intel_framebuffer_create(dev, &mode_cmd, obj);
9684}
9685
9686static struct drm_framebuffer *
9687mode_fits_in_fbdev(struct drm_device *dev,
9688 struct drm_display_mode *mode)
9689{
Daniel Vetter4520f532013-10-09 09:18:51 +02009690#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01009691 struct drm_i915_private *dev_priv = dev->dev_private;
9692 struct drm_i915_gem_object *obj;
9693 struct drm_framebuffer *fb;
9694
Daniel Vetter4c0e5522014-02-14 16:35:54 +01009695 if (!dev_priv->fbdev)
9696 return NULL;
9697
9698 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01009699 return NULL;
9700
Jesse Barnes8bcd4552014-02-07 12:10:38 -08009701 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01009702 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01009703
Jesse Barnes8bcd4552014-02-07 12:10:38 -08009704 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009705 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9706 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01009707 return NULL;
9708
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009709 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01009710 return NULL;
9711
9712 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02009713#else
9714 return NULL;
9715#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01009716}
9717
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +03009718static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9719 struct drm_crtc *crtc,
9720 struct drm_display_mode *mode,
9721 struct drm_framebuffer *fb,
9722 int x, int y)
9723{
9724 struct drm_plane_state *plane_state;
9725 int hdisplay, vdisplay;
9726 int ret;
9727
9728 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9729 if (IS_ERR(plane_state))
9730 return PTR_ERR(plane_state);
9731
9732 if (mode)
9733 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9734 else
9735 hdisplay = vdisplay = 0;
9736
9737 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9738 if (ret)
9739 return ret;
9740 drm_atomic_set_fb_for_plane(plane_state, fb);
9741 plane_state->crtc_x = 0;
9742 plane_state->crtc_y = 0;
9743 plane_state->crtc_w = hdisplay;
9744 plane_state->crtc_h = vdisplay;
9745 plane_state->src_x = x << 16;
9746 plane_state->src_y = y << 16;
9747 plane_state->src_w = hdisplay << 16;
9748 plane_state->src_h = vdisplay << 16;
9749
9750 return 0;
9751}
9752
Daniel Vetterd2434ab2012-08-12 21:20:10 +02009753bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01009754 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05009755 struct intel_load_detect_pipe *old,
9756 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08009757{
9758 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02009759 struct intel_encoder *intel_encoder =
9760 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08009761 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01009762 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08009763 struct drm_crtc *crtc = NULL;
9764 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02009765 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05009766 struct drm_mode_config *config = &dev->mode_config;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009767 struct drm_atomic_state *state = NULL;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009768 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +03009769 struct intel_crtc_state *crtc_state;
Rob Clark51fd3712013-11-19 12:10:12 -05009770 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08009771
Chris Wilsond2dff872011-04-19 08:36:26 +01009772 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03009773 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +03009774 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01009775
Rob Clark51fd3712013-11-19 12:10:12 -05009776retry:
9777 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9778 if (ret)
9779 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02009780
Jesse Barnes79e53942008-11-07 14:24:08 -08009781 /*
9782 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01009783 *
Jesse Barnes79e53942008-11-07 14:24:08 -08009784 * - if the connector already has an assigned crtc, use it (but make
9785 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01009786 *
Jesse Barnes79e53942008-11-07 14:24:08 -08009787 * - try to find the first unused crtc that can drive this connector,
9788 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08009789 */
9790
9791 /* See if we already have a CRTC for this connector */
9792 if (encoder->crtc) {
9793 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01009794
Rob Clark51fd3712013-11-19 12:10:12 -05009795 ret = drm_modeset_lock(&crtc->mutex, ctx);
9796 if (ret)
9797 goto fail_unlock;
Daniel Vetter4d02e2d2014-11-11 10:12:00 +01009798 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9799 if (ret)
9800 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01009801
Daniel Vetter24218aa2012-08-12 19:27:11 +02009802 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01009803 old->load_detect_temp = false;
9804
9805 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02009806 if (connector->dpms != DRM_MODE_DPMS_ON)
9807 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01009808
Chris Wilson71731882011-04-19 23:10:58 +01009809 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08009810 }
9811
9812 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01009813 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08009814 i++;
9815 if (!(encoder->possible_crtcs & (1 << i)))
9816 continue;
Matt Roper83d65732015-02-25 13:12:16 -08009817 if (possible_crtc->state->enable)
Ville Syrjäläa4592492014-08-11 13:15:36 +03009818 continue;
9819 /* This can occur when applying the pipe A quirk on resume. */
9820 if (to_intel_crtc(possible_crtc)->new_enabled)
9821 continue;
9822
9823 crtc = possible_crtc;
9824 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08009825 }
9826
9827 /*
9828 * If we didn't find an unused CRTC, don't use any.
9829 */
9830 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01009831 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05009832 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08009833 }
9834
Rob Clark51fd3712013-11-19 12:10:12 -05009835 ret = drm_modeset_lock(&crtc->mutex, ctx);
9836 if (ret)
9837 goto fail_unlock;
Daniel Vetter4d02e2d2014-11-11 10:12:00 +01009838 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9839 if (ret)
9840 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02009841 intel_encoder->new_crtc = to_intel_crtc(crtc);
9842 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08009843
9844 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009845 intel_crtc->new_enabled = true;
Daniel Vetter24218aa2012-08-12 19:27:11 +02009846 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01009847 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01009848 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08009849
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009850 state = drm_atomic_state_alloc(dev);
9851 if (!state)
9852 return false;
9853
9854 state->acquire_ctx = ctx;
9855
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009856 connector_state = drm_atomic_get_connector_state(state, connector);
9857 if (IS_ERR(connector_state)) {
9858 ret = PTR_ERR(connector_state);
9859 goto fail;
9860 }
9861
9862 connector_state->crtc = crtc;
9863 connector_state->best_encoder = &intel_encoder->base;
9864
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +03009865 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9866 if (IS_ERR(crtc_state)) {
9867 ret = PTR_ERR(crtc_state);
9868 goto fail;
9869 }
9870
9871 crtc_state->base.enable = true;
9872
Chris Wilson64927112011-04-20 07:25:26 +01009873 if (!mode)
9874 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08009875
Chris Wilsond2dff872011-04-19 08:36:26 +01009876 /* We need a framebuffer large enough to accommodate all accesses
9877 * that the plane may generate whilst we perform load detection.
9878 * We can not rely on the fbcon either being present (we get called
9879 * during its initialisation to detect all boot displays, or it may
9880 * not even exist) or that it is large enough to satisfy the
9881 * requested mode.
9882 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02009883 fb = mode_fits_in_fbdev(dev, mode);
9884 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01009885 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02009886 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9887 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01009888 } else
9889 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02009890 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01009891 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009892 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08009893 }
Chris Wilsond2dff872011-04-19 08:36:26 +01009894
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +03009895 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9896 if (ret)
9897 goto fail;
9898
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +03009899 drm_mode_copy(&crtc_state->base.mode, mode);
9900
9901 if (intel_set_mode(crtc, state)) {
Chris Wilson64927112011-04-20 07:25:26 +01009902 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01009903 if (old->release_fb)
9904 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009905 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08009906 }
Daniel Vetter9128b042015-03-03 17:31:21 +01009907 crtc->primary->crtc = crtc;
Chris Wilson71731882011-04-19 23:10:58 +01009908
Jesse Barnes79e53942008-11-07 14:24:08 -08009909 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07009910 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01009911 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009912
9913 fail:
Matt Roper83d65732015-02-25 13:12:16 -08009914 intel_crtc->new_enabled = crtc->state->enable;
Rob Clark51fd3712013-11-19 12:10:12 -05009915fail_unlock:
Ander Conselvan de Oliveirae5d958e2015-04-21 17:12:57 +03009916 drm_atomic_state_free(state);
9917 state = NULL;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009918
Rob Clark51fd3712013-11-19 12:10:12 -05009919 if (ret == -EDEADLK) {
9920 drm_modeset_backoff(ctx);
9921 goto retry;
9922 }
9923
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009924 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08009925}
9926
Daniel Vetterd2434ab2012-08-12 21:20:10 +02009927void intel_release_load_detect_pipe(struct drm_connector *connector,
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +02009928 struct intel_load_detect_pipe *old,
9929 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08009930{
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009931 struct drm_device *dev = connector->dev;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02009932 struct intel_encoder *intel_encoder =
9933 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01009934 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01009935 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009937 struct drm_atomic_state *state;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009938 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +03009939 struct intel_crtc_state *crtc_state;
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +03009940 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08009941
Chris Wilsond2dff872011-04-19 08:36:26 +01009942 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03009943 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +03009944 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01009945
Chris Wilson8261b192011-04-19 23:18:09 +01009946 if (old->load_detect_temp) {
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009947 state = drm_atomic_state_alloc(dev);
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009948 if (!state)
9949 goto fail;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +02009950
9951 state->acquire_ctx = ctx;
9952
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009953 connector_state = drm_atomic_get_connector_state(state, connector);
9954 if (IS_ERR(connector_state))
9955 goto fail;
9956
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +03009957 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9958 if (IS_ERR(crtc_state))
9959 goto fail;
9960
Daniel Vetterfc303102012-07-09 10:40:58 +02009961 to_intel_connector(connector)->new_encoder = NULL;
9962 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02009963 intel_crtc->new_enabled = false;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009964
9965 connector_state->best_encoder = NULL;
9966 connector_state->crtc = NULL;
9967
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +03009968 crtc_state->base.enable = false;
9969
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +03009970 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9971 0, 0);
9972 if (ret)
9973 goto fail;
9974
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +03009975 ret = intel_set_mode(crtc, state);
9976 if (ret)
9977 goto fail;
Chris Wilsond2dff872011-04-19 08:36:26 +01009978
Daniel Vetter36206362012-12-10 20:42:17 +01009979 if (old->release_fb) {
9980 drm_framebuffer_unregister_private(old->release_fb);
9981 drm_framebuffer_unreference(old->release_fb);
9982 }
Chris Wilsond2dff872011-04-19 08:36:26 +01009983
Chris Wilson0622a532011-04-21 09:32:11 +01009984 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08009985 }
9986
Eric Anholtc751ce42010-03-25 11:48:48 -07009987 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02009988 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9989 connector->funcs->dpms(connector, old->dpms_mode);
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +02009990
9991 return;
9992fail:
9993 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9994 drm_atomic_state_free(state);
Jesse Barnes79e53942008-11-07 14:24:08 -08009995}
9996
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03009997static int i9xx_pll_refclk(struct drm_device *dev,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009998 const struct intel_crtc_state *pipe_config)
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03009999{
10000 struct drm_i915_private *dev_priv = dev->dev_private;
10001 u32 dpll = pipe_config->dpll_hw_state.dpll;
10002
10003 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +020010004 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010005 else if (HAS_PCH_SPLIT(dev))
10006 return 120000;
10007 else if (!IS_GEN2(dev))
10008 return 96000;
10009 else
10010 return 48000;
10011}
10012
Jesse Barnes79e53942008-11-07 14:24:08 -080010013/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010014static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010015 struct intel_crtc_state *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -080010016{
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010017 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080010018 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010019 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +030010020 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -080010021 u32 fp;
10022 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010023 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -080010024
10025 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +030010026 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -080010027 else
Ville Syrjälä293623f2013-09-13 16:18:46 +030010028 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -080010029
10030 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -050010031 if (IS_PINEVIEW(dev)) {
10032 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10033 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +080010034 } else {
10035 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10036 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10037 }
10038
Chris Wilsona6c45cf2010-09-17 00:32:17 +010010039 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -050010040 if (IS_PINEVIEW(dev))
10041 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10042 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +080010043 else
10044 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -080010045 DPLL_FPA01_P1_POST_DIV_SHIFT);
10046
10047 switch (dpll & DPLL_MODE_MASK) {
10048 case DPLLB_MODE_DAC_SERIAL:
10049 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10050 5 : 10;
10051 break;
10052 case DPLLB_MODE_LVDS:
10053 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10054 7 : 14;
10055 break;
10056 default:
Zhao Yakui28c97732009-10-09 11:39:41 +080010057 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -080010058 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010059 return;
Jesse Barnes79e53942008-11-07 14:24:08 -080010060 }
10061
Daniel Vetterac58c3f2013-06-01 17:16:17 +020010062 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010063 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +020010064 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010065 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080010066 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +020010067 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +020010068 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -080010069
10070 if (is_lvds) {
10071 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10072 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +020010073
10074 if (lvds & LVDS_CLKB_POWER_UP)
10075 clock.p2 = 7;
10076 else
10077 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -080010078 } else {
10079 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10080 clock.p1 = 2;
10081 else {
10082 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10083 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10084 }
10085 if (dpll & PLL_P2_DIVIDE_BY_4)
10086 clock.p2 = 4;
10087 else
10088 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -080010089 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010090
10091 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080010092 }
10093
Ville Syrjälä18442d02013-09-13 16:00:08 +030010094 /*
10095 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +010010096 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +030010097 * encoder's get_config() function.
10098 */
10099 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010100}
10101
Ville Syrjälä6878da02013-09-13 15:59:11 +030010102int intel_dotclock_calculate(int link_freq,
10103 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010104{
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010105 /*
10106 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +030010107 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010108 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +030010109 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010110 *
10111 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +030010112 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -080010113 */
10114
Ville Syrjälä6878da02013-09-13 15:59:11 +030010115 if (!m_n->link_n)
10116 return 0;
10117
10118 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10119}
10120
Ville Syrjälä18442d02013-09-13 16:00:08 +030010121static void ironlake_pch_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010122 struct intel_crtc_state *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +030010123{
10124 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +030010125
10126 /* read out port_clock from the DPLL */
10127 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +030010128
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010129 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +030010130 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +010010131 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +030010132 * agree once we know their relationship in the encoder's
10133 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010134 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020010135 pipe_config->base.adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +030010136 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10137 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -080010138}
10139
10140/** Returns the currently programmed mode of the given pipe. */
10141struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10142 struct drm_crtc *crtc)
10143{
Jesse Barnes548f2452011-02-17 10:40:53 -080010144 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020010146 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080010147 struct drm_display_mode *mode;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010148 struct intel_crtc_state pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -020010149 int htot = I915_READ(HTOTAL(cpu_transcoder));
10150 int hsync = I915_READ(HSYNC(cpu_transcoder));
10151 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10152 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +030010153 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -080010154
10155 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10156 if (!mode)
10157 return NULL;
10158
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010159 /*
10160 * Construct a pipe_config sufficient for getting the clock info
10161 * back out of crtc_clock_get.
10162 *
10163 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10164 * to use a real value here instead.
10165 */
Ville Syrjälä293623f2013-09-13 16:18:46 +030010166 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010167 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +030010168 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10169 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10170 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010171 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10172
Ville Syrjälä773ae032013-09-23 17:48:20 +030010173 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -080010174 mode->hdisplay = (htot & 0xffff) + 1;
10175 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10176 mode->hsync_start = (hsync & 0xffff) + 1;
10177 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10178 mode->vdisplay = (vtot & 0xffff) + 1;
10179 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10180 mode->vsync_start = (vsync & 0xffff) + 1;
10181 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10182
10183 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -080010184
10185 return mode;
10186}
10187
Jesse Barnes652c3932009-08-17 13:31:43 -070010188static void intel_decrease_pllclock(struct drm_crtc *crtc)
10189{
10190 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010191 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -070010192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070010193
Sonika Jindalbaff2962014-07-22 11:16:35 +053010194 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -070010195 return;
10196
10197 if (!dev_priv->lvds_downclock_avail)
10198 return;
10199
10200 /*
10201 * Since this is called by a timer, we should never get here in
10202 * the manual case.
10203 */
10204 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +010010205 int pipe = intel_crtc->pipe;
10206 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +020010207 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +010010208
Zhao Yakui44d98a62009-10-09 11:39:40 +080010209 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -070010210
Sean Paul8ac5a6d2012-02-13 13:14:51 -050010211 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -070010212
Chris Wilson074b5e12012-05-02 12:07:06 +010010213 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -070010214 dpll |= DISPLAY_RATE_SELECT_FPA1;
10215 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -070010216 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -070010217 dpll = I915_READ(dpll_reg);
10218 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +080010219 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -070010220 }
10221
10222}
10223
Chris Wilsonf047e392012-07-21 12:31:41 +010010224void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -070010225{
Paulo Zanonic67a4702013-08-19 13:18:09 -030010226 struct drm_i915_private *dev_priv = dev->dev_private;
10227
Chris Wilsonf62a0072014-02-21 17:55:39 +000010228 if (dev_priv->mm.busy)
10229 return;
10230
Paulo Zanoni43694d62014-03-07 20:08:08 -030010231 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -030010232 i915_update_gfx_val(dev_priv);
Chris Wilson43cf3bf2015-03-18 09:48:22 +000010233 if (INTEL_INFO(dev)->gen >= 6)
10234 gen6_rps_busy(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +000010235 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +010010236}
10237
10238void intel_mark_idle(struct drm_device *dev)
10239{
Paulo Zanonic67a4702013-08-19 13:18:09 -030010240 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +000010241 struct drm_crtc *crtc;
10242
Chris Wilsonf62a0072014-02-21 17:55:39 +000010243 if (!dev_priv->mm.busy)
10244 return;
10245
10246 dev_priv->mm.busy = false;
10247
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010248 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -070010249 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +000010250 continue;
10251
10252 intel_decrease_pllclock(crtc);
10253 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +010010254
Damien Lespiau3d13ef22014-02-07 19:12:47 +000010255 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +010010256 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -030010257
Paulo Zanoni43694d62014-03-07 20:08:08 -030010258 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +010010259}
10260
Jesse Barnes79e53942008-11-07 14:24:08 -080010261static void intel_crtc_destroy(struct drm_crtc *crtc)
10262{
10263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010264 struct drm_device *dev = crtc->dev;
10265 struct intel_unpin_work *work;
Daniel Vetter67e77c52010-08-20 22:26:30 +020010266
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010267 spin_lock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010268 work = intel_crtc->unpin_work;
10269 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010270 spin_unlock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010271
10272 if (work) {
10273 cancel_work_sync(&work->work);
10274 kfree(work);
10275 }
Jesse Barnes79e53942008-11-07 14:24:08 -080010276
10277 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010278
Jesse Barnes79e53942008-11-07 14:24:08 -080010279 kfree(intel_crtc);
10280}
10281
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010282static void intel_unpin_work_fn(struct work_struct *__work)
10283{
10284 struct intel_unpin_work *work =
10285 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010286 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +020010287 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010288
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010289 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000010290 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
Chris Wilson05394f32010-11-08 19:18:58 +000010291 drm_gem_object_unreference(&work->pending_flip_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +000010292
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020010293 intel_fbc_update(dev);
John Harrisonf06cc1b2014-11-24 18:49:37 +000010294
10295 if (work->flip_queued_req)
John Harrison146d84f2014-12-05 13:49:33 +000010296 i915_gem_request_assign(&work->flip_queued_req, NULL);
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010297 mutex_unlock(&dev->struct_mutex);
10298
Daniel Vetterf99d7062014-06-19 16:01:59 +020010299 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilson89ed88b2015-02-16 14:31:49 +000010300 drm_framebuffer_unreference(work->old_fb);
Daniel Vetterf99d7062014-06-19 16:01:59 +020010301
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010302 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10303 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10304
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010305 kfree(work);
10306}
10307
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010308static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +010010309 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010310{
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10312 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010313 unsigned long flags;
10314
10315 /* Ignore early vblank irqs */
10316 if (intel_crtc == NULL)
10317 return;
10318
Daniel Vetterf3260382014-09-15 14:55:23 +020010319 /*
10320 * This is called both by irq handlers and the reset code (to complete
10321 * lost pageflips) so needs the full irqsave spinlocks.
10322 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010323 spin_lock_irqsave(&dev->event_lock, flags);
10324 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +000010325
10326 /* Ensure we don't miss a work->pending update ... */
10327 smp_rmb();
10328
10329 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010330 spin_unlock_irqrestore(&dev->event_lock, flags);
10331 return;
10332 }
10333
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010334 page_flip_completed(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +010010335
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010336 spin_unlock_irqrestore(&dev->event_lock, flags);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010337}
10338
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010339void intel_finish_page_flip(struct drm_device *dev, int pipe)
10340{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010341 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010342 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10343
Mario Kleiner49b14a52010-12-09 07:00:07 +010010344 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010345}
10346
10347void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10348{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010349 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010350 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10351
Mario Kleiner49b14a52010-12-09 07:00:07 +010010352 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010353}
10354
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010355/* Is 'a' after or equal to 'b'? */
10356static bool g4x_flip_count_after_eq(u32 a, u32 b)
10357{
10358 return !((a - b) & 0x80000000);
10359}
10360
10361static bool page_flip_finished(struct intel_crtc *crtc)
10362{
10363 struct drm_device *dev = crtc->base.dev;
10364 struct drm_i915_private *dev_priv = dev->dev_private;
10365
Ville Syrjäläbdfa7542014-05-27 21:33:09 +030010366 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10367 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10368 return true;
10369
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010370 /*
10371 * The relevant registers doen't exist on pre-ctg.
10372 * As the flip done interrupt doesn't trigger for mmio
10373 * flips on gmch platforms, a flip count check isn't
10374 * really needed there. But since ctg has the registers,
10375 * include it in the check anyway.
10376 */
10377 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10378 return true;
10379
10380 /*
10381 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10382 * used the same base address. In that case the mmio flip might
10383 * have completed, but the CS hasn't even executed the flip yet.
10384 *
10385 * A flip count check isn't enough as the CS might have updated
10386 * the base address just after start of vblank, but before we
10387 * managed to process the interrupt. This means we'd complete the
10388 * CS flip too soon.
10389 *
10390 * Combining both checks should get us a good enough result. It may
10391 * still happen that the CS flip has been executed, but has not
10392 * yet actually completed. But in case the base address is the same
10393 * anyway, we don't really care.
10394 */
10395 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10396 crtc->unpin_work->gtt_offset &&
10397 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10398 crtc->unpin_work->flip_count);
10399}
10400
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010401void intel_prepare_page_flip(struct drm_device *dev, int plane)
10402{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010403 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010404 struct intel_crtc *intel_crtc =
10405 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10406 unsigned long flags;
10407
Daniel Vetterf3260382014-09-15 14:55:23 +020010408
10409 /*
10410 * This is called both by irq handlers and the reset code (to complete
10411 * lost pageflips) so needs the full irqsave spinlocks.
10412 *
10413 * NB: An MMIO update of the plane base pointer will also
Chris Wilsone7d841c2012-12-03 11:36:30 +000010414 * generate a page-flip completion irq, i.e. every modeset
10415 * is also accompanied by a spurious intel_prepare_page_flip().
10416 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010417 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010418 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +000010419 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010420 spin_unlock_irqrestore(&dev->event_lock, flags);
10421}
10422
Robin Schroereba905b2014-05-18 02:24:50 +020010423static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +000010424{
10425 /* Ensure that the work item is consistent when activating it ... */
10426 smp_wmb();
10427 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10428 /* and that it is marked active as soon as the irq could fire. */
10429 smp_wmb();
10430}
10431
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010432static int intel_gen2_queue_flip(struct drm_device *dev,
10433 struct drm_crtc *crtc,
10434 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010435 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010436 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -070010437 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010438{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010440 u32 flip_mask;
10441 int ret;
10442
Daniel Vetter6d90c952012-04-26 23:28:05 +020010443 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010444 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010445 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010446
10447 /* Can't queue multiple flips, so wait for the previous
10448 * one to finish before executing the next.
10449 */
10450 if (intel_crtc->plane)
10451 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10452 else
10453 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +020010454 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10455 intel_ring_emit(ring, MI_NOOP);
10456 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10457 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10458 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010459 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +020010460 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +000010461
10462 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +010010463 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +010010464 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010465}
10466
10467static int intel_gen3_queue_flip(struct drm_device *dev,
10468 struct drm_crtc *crtc,
10469 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010470 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010471 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -070010472 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010473{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010475 u32 flip_mask;
10476 int ret;
10477
Daniel Vetter6d90c952012-04-26 23:28:05 +020010478 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010479 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010480 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010481
10482 if (intel_crtc->plane)
10483 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10484 else
10485 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +020010486 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10487 intel_ring_emit(ring, MI_NOOP);
10488 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10489 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10490 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010491 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +020010492 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010493
Chris Wilsone7d841c2012-12-03 11:36:30 +000010494 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +010010495 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +010010496 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010497}
10498
10499static int intel_gen4_queue_flip(struct drm_device *dev,
10500 struct drm_crtc *crtc,
10501 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010502 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010503 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -070010504 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010505{
10506 struct drm_i915_private *dev_priv = dev->dev_private;
10507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10508 uint32_t pf, pipesrc;
10509 int ret;
10510
Daniel Vetter6d90c952012-04-26 23:28:05 +020010511 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010512 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010513 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010514
10515 /* i965+ uses the linear or tiled offsets from the
10516 * Display Registers (which do not change across a page-flip)
10517 * so we need only reprogram the base address.
10518 */
Daniel Vetter6d90c952012-04-26 23:28:05 +020010519 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10520 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10521 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010522 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +020010523 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010524
10525 /* XXX Enabling the panel-fitter across page-flip is so far
10526 * untested on non-native modes, so ignore it for now.
10527 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10528 */
10529 pf = 0;
10530 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +020010531 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +000010532
10533 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +010010534 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +010010535 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010536}
10537
10538static int intel_gen6_queue_flip(struct drm_device *dev,
10539 struct drm_crtc *crtc,
10540 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010541 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010542 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -070010543 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010544{
10545 struct drm_i915_private *dev_priv = dev->dev_private;
10546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10547 uint32_t pf, pipesrc;
10548 int ret;
10549
Daniel Vetter6d90c952012-04-26 23:28:05 +020010550 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010551 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010552 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010553
Daniel Vetter6d90c952012-04-26 23:28:05 +020010554 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10555 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10556 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010557 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010558
Chris Wilson99d9acd2012-04-17 20:37:00 +010010559 /* Contrary to the suggestions in the documentation,
10560 * "Enable Panel Fitter" does not seem to be required when page
10561 * flipping with a non-native mode, and worse causes a normal
10562 * modeset to fail.
10563 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10564 */
10565 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010566 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +020010567 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +000010568
10569 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +010010570 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +010010571 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010572}
10573
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010574static int intel_gen7_queue_flip(struct drm_device *dev,
10575 struct drm_crtc *crtc,
10576 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010577 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010578 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -070010579 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010580{
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +020010582 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +010010583 int len, ret;
10584
Robin Schroereba905b2014-05-18 02:24:50 +020010585 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +020010586 case PLANE_A:
10587 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10588 break;
10589 case PLANE_B:
10590 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10591 break;
10592 case PLANE_C:
10593 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10594 break;
10595 default:
10596 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010597 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +020010598 }
10599
Chris Wilsonffe74d72013-08-26 20:58:12 +010010600 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +010010601 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +010010602 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +010010603 /*
10604 * On Gen 8, SRM is now taking an extra dword to accommodate
10605 * 48bits addresses, and we need a NOOP for the batch size to
10606 * stay even.
10607 */
10608 if (IS_GEN8(dev))
10609 len += 2;
10610 }
Chris Wilsonffe74d72013-08-26 20:58:12 +010010611
Ville Syrjäläf66fab82014-02-11 19:52:06 +020010612 /*
10613 * BSpec MI_DISPLAY_FLIP for IVB:
10614 * "The full packet must be contained within the same cache line."
10615 *
10616 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10617 * cacheline, if we ever start emitting more commands before
10618 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10619 * then do the cacheline alignment, and finally emit the
10620 * MI_DISPLAY_FLIP.
10621 */
10622 ret = intel_ring_cacheline_align(ring);
10623 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010624 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +020010625
Chris Wilsonffe74d72013-08-26 20:58:12 +010010626 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010627 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030010628 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010629
Chris Wilsonffe74d72013-08-26 20:58:12 +010010630 /* Unmask the flip-done completion message. Note that the bspec says that
10631 * we should do this for both the BCS and RCS, and that we must not unmask
10632 * more than one flip event at any time (or ensure that one flip message
10633 * can be sent by waiting for flip-done prior to queueing new flips).
10634 * Experimentation says that BCS works despite DERRMR masking all
10635 * flip-done completion events and that unmasking all planes at once
10636 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10637 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10638 */
10639 if (ring->id == RCS) {
10640 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10641 intel_ring_emit(ring, DERRMR);
10642 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10643 DERRMR_PIPEB_PRI_FLIP_DONE |
10644 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +010010645 if (IS_GEN8(dev))
10646 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10647 MI_SRM_LRM_GLOBAL_GTT);
10648 else
10649 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10650 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +010010651 intel_ring_emit(ring, DERRMR);
10652 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +010010653 if (IS_GEN8(dev)) {
10654 intel_ring_emit(ring, 0);
10655 intel_ring_emit(ring, MI_NOOP);
10656 }
Chris Wilsonffe74d72013-08-26 20:58:12 +010010657 }
10658
Daniel Vettercb05d8d2012-05-23 14:02:00 +020010659 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +020010660 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010661 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010662 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +000010663
10664 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +010010665 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +010010666 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010667}
10668
Sourab Gupta84c33a62014-06-02 16:47:17 +053010669static bool use_mmio_flip(struct intel_engine_cs *ring,
10670 struct drm_i915_gem_object *obj)
10671{
10672 /*
10673 * This is not being used for older platforms, because
10674 * non-availability of flip done interrupt forces us to use
10675 * CS flips. Older platforms derive flip done using some clever
10676 * tricks involving the flip_pending status bits and vblank irqs.
10677 * So using MMIO flips there would disrupt this mechanism.
10678 */
10679
Chris Wilson8e09bf82014-07-08 10:40:30 +010010680 if (ring == NULL)
10681 return true;
10682
Sourab Gupta84c33a62014-06-02 16:47:17 +053010683 if (INTEL_INFO(ring->dev)->gen < 5)
10684 return false;
10685
10686 if (i915.use_mmio_flip < 0)
10687 return false;
10688 else if (i915.use_mmio_flip > 0)
10689 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +010010690 else if (i915.enable_execlists)
10691 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +053010692 else
John Harrison41c52412014-11-24 18:49:43 +000010693 return ring != i915_gem_request_get_ring(obj->last_read_req);
Sourab Gupta84c33a62014-06-02 16:47:17 +053010694}
10695
Damien Lespiauff944562014-11-20 14:58:16 +000010696static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10697{
10698 struct drm_device *dev = intel_crtc->base.dev;
10699 struct drm_i915_private *dev_priv = dev->dev_private;
10700 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
Damien Lespiauff944562014-11-20 14:58:16 +000010701 const enum pipe pipe = intel_crtc->pipe;
10702 u32 ctl, stride;
10703
10704 ctl = I915_READ(PLANE_CTL(pipe, 0));
10705 ctl &= ~PLANE_CTL_TILED_MASK;
Tvrtko Ursulin2ebef632015-04-20 16:22:48 +010010706 switch (fb->modifier[0]) {
10707 case DRM_FORMAT_MOD_NONE:
10708 break;
10709 case I915_FORMAT_MOD_X_TILED:
Damien Lespiauff944562014-11-20 14:58:16 +000010710 ctl |= PLANE_CTL_TILED_X;
Tvrtko Ursulin2ebef632015-04-20 16:22:48 +010010711 break;
10712 case I915_FORMAT_MOD_Y_TILED:
10713 ctl |= PLANE_CTL_TILED_Y;
10714 break;
10715 case I915_FORMAT_MOD_Yf_TILED:
10716 ctl |= PLANE_CTL_TILED_YF;
10717 break;
10718 default:
10719 MISSING_CASE(fb->modifier[0]);
10720 }
Damien Lespiauff944562014-11-20 14:58:16 +000010721
10722 /*
10723 * The stride is either expressed as a multiple of 64 bytes chunks for
10724 * linear buffers or in number of tiles for tiled buffers.
10725 */
Tvrtko Ursulin2ebef632015-04-20 16:22:48 +010010726 stride = fb->pitches[0] /
10727 intel_fb_stride_alignment(dev, fb->modifier[0],
10728 fb->pixel_format);
Damien Lespiauff944562014-11-20 14:58:16 +000010729
10730 /*
10731 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10732 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10733 */
10734 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10735 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10736
10737 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10738 POSTING_READ(PLANE_SURF(pipe, 0));
10739}
10740
10741static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
Sourab Gupta84c33a62014-06-02 16:47:17 +053010742{
10743 struct drm_device *dev = intel_crtc->base.dev;
10744 struct drm_i915_private *dev_priv = dev->dev_private;
10745 struct intel_framebuffer *intel_fb =
10746 to_intel_framebuffer(intel_crtc->base.primary->fb);
10747 struct drm_i915_gem_object *obj = intel_fb->obj;
10748 u32 dspcntr;
10749 u32 reg;
10750
Sourab Gupta84c33a62014-06-02 16:47:17 +053010751 reg = DSPCNTR(intel_crtc->plane);
10752 dspcntr = I915_READ(reg);
10753
Damien Lespiauc5d97472014-10-25 00:11:11 +010010754 if (obj->tiling_mode != I915_TILING_NONE)
10755 dspcntr |= DISPPLANE_TILED;
10756 else
10757 dspcntr &= ~DISPPLANE_TILED;
10758
Sourab Gupta84c33a62014-06-02 16:47:17 +053010759 I915_WRITE(reg, dspcntr);
10760
10761 I915_WRITE(DSPSURF(intel_crtc->plane),
10762 intel_crtc->unpin_work->gtt_offset);
10763 POSTING_READ(DSPSURF(intel_crtc->plane));
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020010764
Damien Lespiauff944562014-11-20 14:58:16 +000010765}
10766
10767/*
10768 * XXX: This is the temporary way to update the plane registers until we get
10769 * around to using the usual plane update functions for MMIO flips
10770 */
10771static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10772{
10773 struct drm_device *dev = intel_crtc->base.dev;
10774 bool atomic_update;
10775 u32 start_vbl_count;
10776
10777 intel_mark_page_flip_active(intel_crtc);
10778
10779 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10780
10781 if (INTEL_INFO(dev)->gen >= 9)
10782 skl_do_mmio_flip(intel_crtc);
10783 else
10784 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10785 ilk_do_mmio_flip(intel_crtc);
10786
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020010787 if (atomic_update)
10788 intel_pipe_update_end(intel_crtc, start_vbl_count);
Sourab Gupta84c33a62014-06-02 16:47:17 +053010789}
10790
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020010791static void intel_mmio_flip_work_func(struct work_struct *work)
Sourab Gupta84c33a62014-06-02 16:47:17 +053010792{
John Harrisoncc8c4cc2014-11-24 18:49:34 +000010793 struct intel_crtc *crtc =
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020010794 container_of(work, struct intel_crtc, mmio_flip.work);
John Harrisoncc8c4cc2014-11-24 18:49:34 +000010795 struct intel_mmio_flip *mmio_flip;
Sourab Gupta84c33a62014-06-02 16:47:17 +053010796
John Harrisoncc8c4cc2014-11-24 18:49:34 +000010797 mmio_flip = &crtc->mmio_flip;
10798 if (mmio_flip->req)
John Harrison9c654812014-11-24 18:49:35 +000010799 WARN_ON(__i915_wait_request(mmio_flip->req,
10800 crtc->reset_counter,
10801 false, NULL, NULL) != 0);
Sourab Gupta84c33a62014-06-02 16:47:17 +053010802
John Harrisoncc8c4cc2014-11-24 18:49:34 +000010803 intel_do_mmio_flip(crtc);
10804 if (mmio_flip->req) {
10805 mutex_lock(&crtc->base.dev->struct_mutex);
John Harrison146d84f2014-12-05 13:49:33 +000010806 i915_gem_request_assign(&mmio_flip->req, NULL);
John Harrisoncc8c4cc2014-11-24 18:49:34 +000010807 mutex_unlock(&crtc->base.dev->struct_mutex);
10808 }
Sourab Gupta84c33a62014-06-02 16:47:17 +053010809}
10810
10811static int intel_queue_mmio_flip(struct drm_device *dev,
10812 struct drm_crtc *crtc,
10813 struct drm_framebuffer *fb,
10814 struct drm_i915_gem_object *obj,
10815 struct intel_engine_cs *ring,
10816 uint32_t flags)
10817{
Sourab Gupta84c33a62014-06-02 16:47:17 +053010818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +053010819
John Harrisoncc8c4cc2014-11-24 18:49:34 +000010820 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10821 obj->last_write_req);
Sourab Gupta84c33a62014-06-02 16:47:17 +053010822
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +020010823 schedule_work(&intel_crtc->mmio_flip.work);
10824
Sourab Gupta84c33a62014-06-02 16:47:17 +053010825 return 0;
10826}
10827
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010828static int intel_default_queue_flip(struct drm_device *dev,
10829 struct drm_crtc *crtc,
10830 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010831 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010832 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -070010833 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010834{
10835 return -ENODEV;
10836}
10837
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010838static bool __intel_pageflip_stall_check(struct drm_device *dev,
10839 struct drm_crtc *crtc)
10840{
10841 struct drm_i915_private *dev_priv = dev->dev_private;
10842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10843 struct intel_unpin_work *work = intel_crtc->unpin_work;
10844 u32 addr;
10845
10846 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10847 return true;
10848
10849 if (!work->enable_stall_check)
10850 return false;
10851
10852 if (work->flip_ready_vblank == 0) {
Daniel Vetter3a8a9462014-11-26 14:39:48 +010010853 if (work->flip_queued_req &&
10854 !i915_gem_request_completed(work->flip_queued_req, true))
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010855 return false;
10856
Daniel Vetter1e3feef2015-02-13 21:03:45 +010010857 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010858 }
10859
Daniel Vetter1e3feef2015-02-13 21:03:45 +010010860 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010861 return false;
10862
10863 /* Potential stall - if we see that the flip has happened,
10864 * assume a missed interrupt. */
10865 if (INTEL_INFO(dev)->gen >= 4)
10866 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10867 else
10868 addr = I915_READ(DSPADDR(intel_crtc->plane));
10869
10870 /* There is a potential issue here with a false positive after a flip
10871 * to the same address. We could address this by checking for a
10872 * non-incrementing frame counter.
10873 */
10874 return addr == work->gtt_offset;
10875}
10876
10877void intel_check_page_flip(struct drm_device *dev, int pipe)
10878{
10879 struct drm_i915_private *dev_priv = dev->dev_private;
10880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson6ad790c2015-04-07 16:20:31 +010010882 struct intel_unpin_work *work;
Daniel Vetterf3260382014-09-15 14:55:23 +020010883
Dave Gordon6c51d462015-03-06 15:34:26 +000010884 WARN_ON(!in_interrupt());
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010885
10886 if (crtc == NULL)
10887 return;
10888
Daniel Vetterf3260382014-09-15 14:55:23 +020010889 spin_lock(&dev->event_lock);
Chris Wilson6ad790c2015-04-07 16:20:31 +010010890 work = intel_crtc->unpin_work;
10891 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010892 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
Chris Wilson6ad790c2015-04-07 16:20:31 +010010893 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010894 page_flip_completed(intel_crtc);
Chris Wilson6ad790c2015-04-07 16:20:31 +010010895 work = NULL;
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010896 }
Chris Wilson6ad790c2015-04-07 16:20:31 +010010897 if (work != NULL &&
10898 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10899 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
Daniel Vetterf3260382014-09-15 14:55:23 +020010900 spin_unlock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010901}
10902
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010903static int intel_crtc_page_flip(struct drm_crtc *crtc,
10904 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070010905 struct drm_pending_vblank_event *event,
10906 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010907{
10908 struct drm_device *dev = crtc->dev;
10909 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -070010910 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -070010911 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Gustavo Padovan455a6802014-12-01 15:40:11 -080010913 struct drm_plane *primary = crtc->primary;
Daniel Vettera071fa02014-06-18 23:28:09 +020010914 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010915 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +010010916 struct intel_engine_cs *ring;
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010010917 bool mmio_flip;
Chris Wilson52e68632010-08-08 10:15:59 +010010918 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010919
Matt Roper2ff8fde2014-07-08 07:50:07 -070010920 /*
10921 * drm_mode_page_flip_ioctl() should already catch this, but double
10922 * check to be safe. In the future we may enable pageflipping from
10923 * a disabled primary plane.
10924 */
10925 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10926 return -EBUSY;
10927
Ville Syrjäläe6a595d2012-05-24 21:08:59 +030010928 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -070010929 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +030010930 return -EINVAL;
10931
10932 /*
10933 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10934 * Note that pitch changes could also affect these register.
10935 */
10936 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -070010937 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10938 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +030010939 return -EINVAL;
10940
Chris Wilsonf900db42014-02-20 09:26:13 +000010941 if (i915_terminally_wedged(&dev_priv->gpu_error))
10942 goto out_hang;
10943
Daniel Vetterb14c5672013-09-19 12:18:32 +020010944 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010945 if (work == NULL)
10946 return -ENOMEM;
10947
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010948 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010949 work->crtc = crtc;
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000010950 work->old_fb = old_fb;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010951 INIT_WORK(&work->work, intel_unpin_work_fn);
10952
Daniel Vetter87b6b102014-05-15 15:33:46 +020010953 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -070010954 if (ret)
10955 goto free_work;
10956
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010957 /* We borrow the event spin lock for protecting unpin_work */
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010958 spin_lock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010959 if (intel_crtc->unpin_work) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010960 /* Before declaring the flip queue wedged, check if
10961 * the hardware completed the operation behind our backs.
10962 */
10963 if (__intel_pageflip_stall_check(dev, crtc)) {
10964 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10965 page_flip_completed(intel_crtc);
10966 } else {
10967 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010968 spin_unlock_irq(&dev->event_lock);
Chris Wilson468f0b42010-05-27 13:18:13 +010010969
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010970 drm_crtc_vblank_put(crtc);
10971 kfree(work);
10972 return -EBUSY;
10973 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010974 }
10975 intel_crtc->unpin_work = work;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010976 spin_unlock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010977
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010978 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10979 flush_workqueue(dev_priv->wq);
10980
Jesse Barnes75dfca82010-02-10 15:09:44 -080010981 /* Reference the objects for the scheduled work. */
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000010982 drm_framebuffer_reference(work->old_fb);
Chris Wilson05394f32010-11-08 19:18:58 +000010983 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010984
Matt Roperf4510a22014-04-01 15:22:40 -070010985 crtc->primary->fb = fb;
Matt Roperafd65eb2015-02-03 13:10:04 -080010986 update_state_fb(crtc->primary);
Matt Roper1ed1f962015-01-30 16:22:36 -080010987
Chris Wilsone1f99ce2010-10-27 12:45:26 +010010988 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +010010989
Chris Wilson89ed88b2015-02-16 14:31:49 +000010990 ret = i915_mutex_lock_interruptible(dev);
10991 if (ret)
10992 goto cleanup;
10993
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010994 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +020010995 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +010010996
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010997 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +020010998 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010999
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011000 if (IS_VALLEYVIEW(dev)) {
11001 ring = &dev_priv->ring[BCS];
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000011002 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
Chris Wilson8e09bf82014-07-08 10:40:30 +010011003 /* vlv: DISPLAY_FLIP fails to change tiling */
11004 ring = NULL;
Chris Wilson48bf5b22014-12-27 09:48:28 +000011005 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Chris Wilson2a92d5b2014-07-08 10:40:29 +010011006 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011007 } else if (INTEL_INFO(dev)->gen >= 7) {
John Harrison41c52412014-11-24 18:49:43 +000011008 ring = i915_gem_request_get_ring(obj->last_read_req);
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011009 if (ring == NULL || ring->id != RCS)
11010 ring = &dev_priv->ring[BCS];
11011 } else {
11012 ring = &dev_priv->ring[RCS];
11013 }
11014
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010011015 mmio_flip = use_mmio_flip(ring, obj);
11016
11017 /* When using CS flips, we want to emit semaphores between rings.
11018 * However, when using mmio flips we will create a task to do the
11019 * synchronisation, so all we want here is to pin the framebuffer
11020 * into the display plane and skip any waits.
11021 */
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000011022 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010011023 crtc->primary->state,
11024 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011025 if (ret)
11026 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011027
Tvrtko Ursulin121920f2015-03-23 11:10:37 +000011028 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11029 + intel_crtc->dspaddr_offset;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011030
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010011031 if (mmio_flip) {
Sourab Gupta84c33a62014-06-02 16:47:17 +053011032 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11033 page_flip_flags);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011034 if (ret)
11035 goto cleanup_unpin;
11036
John Harrisonf06cc1b2014-11-24 18:49:37 +000011037 i915_gem_request_assign(&work->flip_queued_req,
11038 obj->last_write_req);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011039 } else {
Sourab Gupta84c33a62014-06-02 16:47:17 +053011040 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011041 page_flip_flags);
11042 if (ret)
11043 goto cleanup_unpin;
11044
John Harrisonf06cc1b2014-11-24 18:49:37 +000011045 i915_gem_request_assign(&work->flip_queued_req,
11046 intel_ring_get_request(ring));
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011047 }
11048
Daniel Vetter1e3feef2015-02-13 21:03:45 +010011049 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011050 work->enable_stall_check = true;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011051
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000011052 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
Daniel Vettera071fa02014-06-18 23:28:09 +020011053 INTEL_FRONTBUFFER_PRIMARY(pipe));
11054
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020011055 intel_fbc_disable(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +020011056 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011057 mutex_unlock(&dev->struct_mutex);
11058
Jesse Barnese5510fa2010-07-01 16:48:37 -070011059 trace_i915_flip_request(intel_crtc->plane, obj);
11060
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011061 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +010011062
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011063cleanup_unpin:
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000011064 intel_unpin_fb_obj(fb, crtc->primary->state);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011065cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +000011066 atomic_dec(&intel_crtc->unpin_work_count);
Chris Wilson89ed88b2015-02-16 14:31:49 +000011067 mutex_unlock(&dev->struct_mutex);
11068cleanup:
Matt Roperf4510a22014-04-01 15:22:40 -070011069 crtc->primary->fb = old_fb;
Matt Roperafd65eb2015-02-03 13:10:04 -080011070 update_state_fb(crtc->primary);
Chris Wilson96b099f2010-06-07 14:03:04 +010011071
Chris Wilson89ed88b2015-02-16 14:31:49 +000011072 drm_gem_object_unreference_unlocked(&obj->base);
11073 drm_framebuffer_unreference(work->old_fb);
11074
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011075 spin_lock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +010011076 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011077 spin_unlock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +010011078
Daniel Vetter87b6b102014-05-15 15:33:46 +020011079 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -070011080free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +010011081 kfree(work);
11082
Chris Wilsonf900db42014-02-20 09:26:13 +000011083 if (ret == -EIO) {
11084out_hang:
Matt Roper53a366b2014-12-23 10:41:53 -080011085 ret = intel_plane_restore(primary);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +010011086 if (ret == 0 && event) {
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011087 spin_lock_irq(&dev->event_lock);
Daniel Vettera071fa02014-06-18 23:28:09 +020011088 drm_send_vblank_event(dev, pipe, event);
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011089 spin_unlock_irq(&dev->event_lock);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +010011090 }
Chris Wilsonf900db42014-02-20 09:26:13 +000011091 }
Chris Wilson96b099f2010-06-07 14:03:04 +010011092 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011093}
11094
Jani Nikula65b38e02015-04-13 11:26:56 +030011095static const struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011096 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11097 .load_lut = intel_crtc_load_lut,
Matt Roperea2c67b2014-12-23 10:41:52 -080011098 .atomic_begin = intel_begin_crtc_commit,
11099 .atomic_flush = intel_finish_crtc_commit,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011100};
11101
Daniel Vetter9a935852012-07-05 22:34:27 +020011102/**
11103 * intel_modeset_update_staged_output_state
11104 *
11105 * Updates the staged output configuration state, e.g. after we've read out the
11106 * current hw state.
11107 */
11108static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11109{
Ville Syrjälä76688512014-01-10 11:28:06 +020011110 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011111 struct intel_encoder *encoder;
11112 struct intel_connector *connector;
11113
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020011114 for_each_intel_connector(dev, connector) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011115 connector->new_encoder =
11116 to_intel_encoder(connector->base.encoder);
11117 }
11118
Damien Lespiaub2784e12014-08-05 11:29:37 +010011119 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011120 encoder->new_crtc =
11121 to_intel_crtc(encoder->base.crtc);
11122 }
Ville Syrjälä76688512014-01-10 11:28:06 +020011123
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011124 for_each_intel_crtc(dev, crtc) {
Matt Roper83d65732015-02-25 13:12:16 -080011125 crtc->new_enabled = crtc->base.state->enable;
Ville Syrjälä76688512014-01-10 11:28:06 +020011126 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011127}
11128
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020011129/* Transitional helper to copy current connector/encoder state to
11130 * connector->state. This is needed so that code that is partially
11131 * converted to atomic does the right thing.
11132 */
11133static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11134{
11135 struct intel_connector *connector;
11136
11137 for_each_intel_connector(dev, connector) {
11138 if (connector->base.encoder) {
11139 connector->base.state->best_encoder =
11140 connector->base.encoder;
11141 connector->base.state->crtc =
11142 connector->base.encoder->crtc;
11143 } else {
11144 connector->base.state->best_encoder = NULL;
11145 connector->base.state->crtc = NULL;
11146 }
11147 }
11148}
11149
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011150/* Fixup legacy state after an atomic state swap.
Daniel Vetter9a935852012-07-05 22:34:27 +020011151 */
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011152static void intel_modeset_fixup_state(struct drm_atomic_state *state)
Daniel Vetter9a935852012-07-05 22:34:27 +020011153{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011154 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011155 struct intel_encoder *encoder;
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011156 struct intel_connector *connector;
Daniel Vetter9a935852012-07-05 22:34:27 +020011157
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011158 for_each_intel_connector(state->dev, connector) {
11159 connector->base.encoder = connector->base.state->best_encoder;
11160 if (connector->base.encoder)
11161 connector->base.encoder->crtc =
11162 connector->base.state->crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011163 }
11164
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030011165 /* Update crtc of disabled encoders */
11166 for_each_intel_encoder(state->dev, encoder) {
11167 int num_connectors = 0;
11168
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011169 for_each_intel_connector(state->dev, connector)
11170 if (connector->base.encoder == &encoder->base)
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030011171 num_connectors++;
11172
11173 if (num_connectors == 0)
11174 encoder->base.crtc = NULL;
Daniel Vetter9a935852012-07-05 22:34:27 +020011175 }
Ville Syrjälä76688512014-01-10 11:28:06 +020011176
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011177 for_each_intel_crtc(state->dev, crtc) {
11178 crtc->base.enabled = crtc->base.state->enable;
11179 crtc->config = to_intel_crtc_state(crtc->base.state);
Ville Syrjälä76688512014-01-10 11:28:06 +020011180 }
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020011181
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030011182 /* Copy the new configuration to the staged state, to keep the few
11183 * pieces of code that haven't been converted yet happy */
11184 intel_modeset_update_staged_output_state(state->dev);
Daniel Vetter9a935852012-07-05 22:34:27 +020011185}
11186
Daniel Vetter050f7ae2013-06-02 13:26:23 +020011187static void
Robin Schroereba905b2014-05-18 02:24:50 +020011188connected_sink_compute_bpp(struct intel_connector *connector,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011189 struct intel_crtc_state *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011190{
Daniel Vetter050f7ae2013-06-02 13:26:23 +020011191 int bpp = pipe_config->pipe_bpp;
11192
11193 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11194 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011195 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +020011196
11197 /* Don't use an invalid EDID bpc value */
11198 if (connector->base.display_info.bpc &&
11199 connector->base.display_info.bpc * 3 < bpp) {
11200 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11201 bpp, connector->base.display_info.bpc*3);
11202 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11203 }
11204
11205 /* Clamp bpp to 8 on screens without EDID 1.4 */
11206 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11207 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11208 bpp);
11209 pipe_config->pipe_bpp = 24;
11210 }
11211}
11212
11213static int
11214compute_baseline_pipe_bpp(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011215 struct intel_crtc_state *pipe_config)
Daniel Vetter050f7ae2013-06-02 13:26:23 +020011216{
11217 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020011218 struct drm_atomic_state *state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011219 struct drm_connector *connector;
11220 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020011221 int bpp, i;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011222
Daniel Vetterd328c9d2015-04-10 16:22:37 +020011223 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011224 bpp = 10*3;
Daniel Vetterd328c9d2015-04-10 16:22:37 +020011225 else if (INTEL_INFO(dev)->gen >= 5)
11226 bpp = 12*3;
11227 else
11228 bpp = 8*3;
11229
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011230
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011231 pipe_config->pipe_bpp = bpp;
11232
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020011233 state = pipe_config->base.state;
11234
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011235 /* Clamp display bpp to EDID value */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011236 for_each_connector_in_state(state, connector, connector_state, i) {
11237 if (connector_state->crtc != &crtc->base)
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020011238 continue;
11239
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011240 connected_sink_compute_bpp(to_intel_connector(connector),
11241 pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011242 }
11243
11244 return bpp;
11245}
11246
Daniel Vetter644db712013-09-19 14:53:58 +020011247static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11248{
11249 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11250 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010011251 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020011252 mode->crtc_hdisplay, mode->crtc_hsync_start,
11253 mode->crtc_hsync_end, mode->crtc_htotal,
11254 mode->crtc_vdisplay, mode->crtc_vsync_start,
11255 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11256}
11257
Daniel Vetterc0b03412013-05-28 12:05:54 +020011258static void intel_dump_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011259 struct intel_crtc_state *pipe_config,
Daniel Vetterc0b03412013-05-28 12:05:54 +020011260 const char *context)
11261{
Chandra Konduru6a60cd82015-04-07 15:28:40 -070011262 struct drm_device *dev = crtc->base.dev;
11263 struct drm_plane *plane;
11264 struct intel_plane *intel_plane;
11265 struct intel_plane_state *state;
11266 struct drm_framebuffer *fb;
11267
11268 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11269 context, pipe_config, pipe_name(crtc->pipe));
Daniel Vetterc0b03412013-05-28 12:05:54 +020011270
11271 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11272 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11273 pipe_config->pipe_bpp, pipe_config->dither);
11274 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11275 pipe_config->has_pch_encoder,
11276 pipe_config->fdi_lanes,
11277 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11278 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11279 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030011280 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11281 pipe_config->has_dp_encoder,
11282 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11283 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11284 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070011285
11286 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11287 pipe_config->has_dp_encoder,
11288 pipe_config->dp_m2_n2.gmch_m,
11289 pipe_config->dp_m2_n2.gmch_n,
11290 pipe_config->dp_m2_n2.link_m,
11291 pipe_config->dp_m2_n2.link_n,
11292 pipe_config->dp_m2_n2.tu);
11293
Daniel Vetter55072d12014-11-20 16:10:28 +010011294 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11295 pipe_config->has_audio,
11296 pipe_config->has_infoframe);
11297
Daniel Vetterc0b03412013-05-28 12:05:54 +020011298 DRM_DEBUG_KMS("requested mode:\n");
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011299 drm_mode_debug_printmodeline(&pipe_config->base.mode);
Daniel Vetterc0b03412013-05-28 12:05:54 +020011300 DRM_DEBUG_KMS("adjusted mode:\n");
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011301 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11302 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030011303 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030011304 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11305 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Chandra Konduru6a60cd82015-04-07 15:28:40 -070011306 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11307 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11308 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
Daniel Vetterc0b03412013-05-28 12:05:54 +020011309 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11310 pipe_config->gmch_pfit.control,
11311 pipe_config->gmch_pfit.pgm_ratios,
11312 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010011313 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020011314 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010011315 pipe_config->pch_pfit.size,
11316 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030011317 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030011318 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Chandra Konduru6a60cd82015-04-07 15:28:40 -070011319
11320 DRM_DEBUG_KMS("planes on this crtc\n");
11321 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11322 intel_plane = to_intel_plane(plane);
11323 if (intel_plane->pipe != crtc->pipe)
11324 continue;
11325
11326 state = to_intel_plane_state(plane->state);
11327 fb = state->base.fb;
11328 if (!fb) {
11329 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11330 "disabled, scaler_id = %d\n",
11331 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11332 plane->base.id, intel_plane->pipe,
11333 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11334 drm_plane_index(plane), state->scaler_id);
11335 continue;
11336 }
11337
11338 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11339 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11340 plane->base.id, intel_plane->pipe,
11341 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11342 drm_plane_index(plane));
11343 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11344 fb->base.id, fb->width, fb->height, fb->pixel_format);
11345 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11346 state->scaler_id,
11347 state->src.x1 >> 16, state->src.y1 >> 16,
11348 drm_rect_width(&state->src) >> 16,
11349 drm_rect_height(&state->src) >> 16,
11350 state->dst.x1, state->dst.y1,
11351 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11352 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020011353}
11354
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011355static bool encoders_cloneable(const struct intel_encoder *a,
11356 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020011357{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011358 /* masks could be asymmetric, so check both ways */
11359 return a == b || (a->cloneable & (1 << b->type) &&
11360 b->cloneable & (1 << a->type));
11361}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020011362
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011363static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11364 struct intel_crtc *crtc,
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011365 struct intel_encoder *encoder)
11366{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011367 struct intel_encoder *source_encoder;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011368 struct drm_connector *connector;
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011369 struct drm_connector_state *connector_state;
11370 int i;
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011371
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011372 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011373 if (connector_state->crtc != &crtc->base)
11374 continue;
11375
11376 source_encoder =
11377 to_intel_encoder(connector_state->best_encoder);
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011378 if (!encoders_cloneable(encoder, source_encoder))
11379 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020011380 }
11381
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011382 return true;
11383}
11384
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011385static bool check_encoder_cloning(struct drm_atomic_state *state,
11386 struct intel_crtc *crtc)
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011387{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011388 struct intel_encoder *encoder;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011389 struct drm_connector *connector;
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011390 struct drm_connector_state *connector_state;
11391 int i;
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011392
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011393 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011394 if (connector_state->crtc != &crtc->base)
11395 continue;
11396
11397 encoder = to_intel_encoder(connector_state->best_encoder);
11398 if (!check_single_encoder_cloning(state, crtc, encoder))
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011399 return false;
11400 }
11401
11402 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020011403}
11404
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030011405static bool check_digital_port_conflicts(struct drm_atomic_state *state)
Ville Syrjälä00f0b372014-12-02 14:10:46 +020011406{
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030011407 struct drm_device *dev = state->dev;
11408 struct intel_encoder *encoder;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011409 struct drm_connector *connector;
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030011410 struct drm_connector_state *connector_state;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020011411 unsigned int used_ports = 0;
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030011412 int i;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020011413
11414 /*
11415 * Walk the connector list instead of the encoder
11416 * list to detect the problem on ddi platforms
11417 * where there's just one encoder per digital port.
11418 */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011419 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030011420 if (!connector_state->best_encoder)
11421 continue;
11422
11423 encoder = to_intel_encoder(connector_state->best_encoder);
11424
11425 WARN_ON(!connector_state->crtc);
Ville Syrjälä00f0b372014-12-02 14:10:46 +020011426
11427 switch (encoder->type) {
11428 unsigned int port_mask;
11429 case INTEL_OUTPUT_UNKNOWN:
11430 if (WARN_ON(!HAS_DDI(dev)))
11431 break;
11432 case INTEL_OUTPUT_DISPLAYPORT:
11433 case INTEL_OUTPUT_HDMI:
11434 case INTEL_OUTPUT_EDP:
11435 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11436
11437 /* the same port mustn't appear more than once */
11438 if (used_ports & port_mask)
11439 return false;
11440
11441 used_ports |= port_mask;
11442 default:
11443 break;
11444 }
11445 }
11446
11447 return true;
11448}
11449
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011450static void
11451clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11452{
11453 struct drm_crtc_state tmp_state;
Chandra Konduru663a3642015-04-07 15:28:41 -070011454 struct intel_crtc_scaler_state scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030011455 struct intel_dpll_hw_state dpll_hw_state;
11456 enum intel_dpll_id shared_dpll;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011457
Chandra Konduru663a3642015-04-07 15:28:41 -070011458 /* Clear only the intel specific part of the crtc state excluding scalers */
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011459 tmp_state = crtc_state->base;
Chandra Konduru663a3642015-04-07 15:28:41 -070011460 scaler_state = crtc_state->scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030011461 shared_dpll = crtc_state->shared_dpll;
11462 dpll_hw_state = crtc_state->dpll_hw_state;
11463
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011464 memset(crtc_state, 0, sizeof *crtc_state);
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030011465
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011466 crtc_state->base = tmp_state;
Chandra Konduru663a3642015-04-07 15:28:41 -070011467 crtc_state->scaler_state = scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030011468 crtc_state->shared_dpll = shared_dpll;
11469 crtc_state->dpll_hw_state = dpll_hw_state;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011470}
11471
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030011472static int
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010011473intel_modeset_pipe_config(struct drm_crtc *crtc,
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030011474 struct drm_atomic_state *state,
11475 struct intel_crtc_state *pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020011476{
Daniel Vetter7758a112012-07-08 19:40:39 +020011477 struct intel_encoder *encoder;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011478 struct drm_connector *connector;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020011479 struct drm_connector_state *connector_state;
Daniel Vetterd328c9d2015-04-10 16:22:37 +020011480 int base_bpp, ret = -EINVAL;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020011481 int i;
Daniel Vettere29c22c2013-02-21 00:00:16 +010011482 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020011483
Ander Conselvan de Oliveira98a221d2015-04-02 14:48:00 +030011484 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020011485 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030011486 return -EINVAL;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020011487 }
11488
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030011489 if (!check_digital_port_conflicts(state)) {
Ville Syrjälä00f0b372014-12-02 14:10:46 +020011490 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030011491 return -EINVAL;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020011492 }
11493
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020011494 clear_intel_crtc_state(pipe_config);
Daniel Vetter7758a112012-07-08 19:40:39 +020011495
Daniel Vettere143a212013-07-04 12:01:15 +020011496 pipe_config->cpu_transcoder =
11497 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010011498
Imre Deak2960bc92013-07-30 13:36:32 +030011499 /*
11500 * Sanitize sync polarity flags based on requested ones. If neither
11501 * positive or negative polarity is requested, treat this as meaning
11502 * negative polarity.
11503 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011504 if (!(pipe_config->base.adjusted_mode.flags &
Imre Deak2960bc92013-07-30 13:36:32 +030011505 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011506 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
Imre Deak2960bc92013-07-30 13:36:32 +030011507
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011508 if (!(pipe_config->base.adjusted_mode.flags &
Imre Deak2960bc92013-07-30 13:36:32 +030011509 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011510 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
Imre Deak2960bc92013-07-30 13:36:32 +030011511
Daniel Vetter050f7ae2013-06-02 13:26:23 +020011512 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11513 * plane pixel format and any sink constraints into account. Returns the
11514 * source plane bpp so that dithering can be selected on mismatches
11515 * after encoders and crtc also have had their say. */
Daniel Vetterd328c9d2015-04-10 16:22:37 +020011516 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11517 pipe_config);
11518 if (base_bpp < 0)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011519 goto fail;
11520
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030011521 /*
11522 * Determine the real pipe dimensions. Note that stereo modes can
11523 * increase the actual pipe size due to the frame doubling and
11524 * insertion of additional space for blanks between the frame. This
11525 * is stored in the crtc timings. We use the requested mode to do this
11526 * computation to clearly distinguish it from the adjusted mode, which
11527 * can be changed by the connectors in the below retry loop.
11528 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011529 drm_crtc_get_hv_timing(&pipe_config->base.mode,
Gustavo Padovanecb7e162014-12-01 15:40:09 -080011530 &pipe_config->pipe_src_w,
11531 &pipe_config->pipe_src_h);
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030011532
Daniel Vettere29c22c2013-02-21 00:00:16 +010011533encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020011534 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020011535 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020011536 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020011537
Daniel Vetter135c81b2013-07-21 21:37:09 +020011538 /* Fill in default crtc timings, allow encoders to overwrite them. */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011539 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11540 CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020011541
Daniel Vetter7758a112012-07-08 19:40:39 +020011542 /* Pass our mode to the connectors and the CRTC to give them a chance to
11543 * adjust it according to limitations or connector properties, and also
11544 * a chance to reject the mode entirely.
11545 */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030011546 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020011547 if (connector_state->crtc != crtc)
11548 continue;
11549
11550 encoder = to_intel_encoder(connector_state->best_encoder);
11551
Daniel Vetterefea6e82013-07-21 21:36:59 +020011552 if (!(encoder->compute_config(encoder, pipe_config))) {
11553 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020011554 goto fail;
11555 }
11556 }
11557
Daniel Vetterff9a6752013-06-01 17:16:21 +020011558 /* Set default port clock if not overwritten by the encoder. Needs to be
11559 * done afterwards in case the encoder adjusts the mode. */
11560 if (!pipe_config->port_clock)
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011561 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
Damien Lespiau241bfc32013-09-25 16:45:37 +010011562 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020011563
Daniel Vettera43f6e02013-06-07 23:10:32 +020011564 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010011565 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020011566 DRM_DEBUG_KMS("CRTC fixup failed\n");
11567 goto fail;
11568 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010011569
11570 if (ret == RETRY) {
11571 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11572 ret = -EINVAL;
11573 goto fail;
11574 }
11575
11576 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11577 retry = false;
11578 goto encoder_retry;
11579 }
11580
Daniel Vetterd328c9d2015-04-10 16:22:37 +020011581 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011582 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
Daniel Vetterd328c9d2015-04-10 16:22:37 +020011583 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010011584
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030011585 return 0;
Daniel Vetter7758a112012-07-08 19:40:39 +020011586fail:
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030011587 return ret;
Daniel Vetter7758a112012-07-08 19:40:39 +020011588}
11589
Daniel Vetterea9d7582012-07-10 10:42:52 +020011590static bool intel_crtc_in_use(struct drm_crtc *crtc)
11591{
11592 struct drm_encoder *encoder;
11593 struct drm_device *dev = crtc->dev;
11594
11595 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11596 if (encoder->crtc == crtc)
11597 return true;
11598
11599 return false;
11600}
11601
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011602static bool
11603needs_modeset(struct drm_crtc_state *state)
Daniel Vetterea9d7582012-07-10 10:42:52 +020011604{
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011605 return state->mode_changed || state->active_changed;
11606}
11607
11608static void
11609intel_modeset_update_state(struct drm_atomic_state *state)
11610{
11611 struct drm_device *dev = state->dev;
Daniel Vetterba41c0de2014-11-03 15:04:55 +010011612 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterea9d7582012-07-10 10:42:52 +020011613 struct intel_encoder *intel_encoder;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011614 struct drm_crtc *crtc;
11615 struct drm_crtc_state *crtc_state;
Daniel Vetterea9d7582012-07-10 10:42:52 +020011616 struct drm_connector *connector;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011617 int i;
Daniel Vetterea9d7582012-07-10 10:42:52 +020011618
Daniel Vetterba41c0de2014-11-03 15:04:55 +010011619 intel_shared_dpll_commit(dev_priv);
11620
Damien Lespiaub2784e12014-08-05 11:29:37 +010011621 for_each_intel_encoder(dev, intel_encoder) {
Daniel Vetterea9d7582012-07-10 10:42:52 +020011622 if (!intel_encoder->base.crtc)
11623 continue;
11624
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011625 for_each_crtc_in_state(state, crtc, crtc_state, i)
11626 if (crtc == intel_encoder->base.crtc)
11627 break;
Daniel Vetterea9d7582012-07-10 10:42:52 +020011628
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011629 if (crtc != intel_encoder->base.crtc)
11630 continue;
11631
11632 if (crtc_state->enable && needs_modeset(crtc_state))
Daniel Vetterea9d7582012-07-10 10:42:52 +020011633 intel_encoder->connectors_active = false;
11634 }
11635
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011636 drm_atomic_helper_swap_state(state->dev, state);
11637 intel_modeset_fixup_state(state);
Daniel Vetterea9d7582012-07-10 10:42:52 +020011638
Ville Syrjälä76688512014-01-10 11:28:06 +020011639 /* Double check state. */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011640 for_each_crtc(dev, crtc) {
11641 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
Daniel Vetterea9d7582012-07-10 10:42:52 +020011642 }
11643
11644 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11645 if (!connector->encoder || !connector->encoder->crtc)
11646 continue;
11647
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011648 for_each_crtc_in_state(state, crtc, crtc_state, i)
11649 if (crtc == connector->encoder->crtc)
11650 break;
Daniel Vetterea9d7582012-07-10 10:42:52 +020011651
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030011652 if (crtc != connector->encoder->crtc)
11653 continue;
11654
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030011655 if (crtc->state->enable && needs_modeset(crtc->state)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020011656 struct drm_property *dpms_property =
11657 dev->mode_config.dpms_property;
11658
Daniel Vetterea9d7582012-07-10 10:42:52 +020011659 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050011660 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020011661 dpms_property,
11662 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020011663
11664 intel_encoder = to_intel_encoder(connector->encoder);
11665 intel_encoder->connectors_active = true;
11666 }
11667 }
11668
11669}
11670
Ville Syrjälä3bd26262013-09-06 23:29:02 +030011671static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011672{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030011673 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030011674
11675 if (clock1 == clock2)
11676 return true;
11677
11678 if (!clock1 || !clock2)
11679 return false;
11680
11681 diff = abs(clock1 - clock2);
11682
11683 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11684 return true;
11685
11686 return false;
11687}
11688
Daniel Vetter25c5b262012-07-08 22:08:04 +020011689#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11690 list_for_each_entry((intel_crtc), \
11691 &(dev)->mode_config.crtc_list, \
11692 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020011693 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020011694
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011695static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020011696intel_pipe_config_compare(struct drm_device *dev,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020011697 struct intel_crtc_state *current_config,
11698 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011699{
Daniel Vetter66e985c2013-06-05 13:34:20 +020011700#define PIPE_CONF_CHECK_X(name) \
11701 if (current_config->name != pipe_config->name) { \
11702 DRM_ERROR("mismatch in " #name " " \
11703 "(expected 0x%08x, found 0x%08x)\n", \
11704 current_config->name, \
11705 pipe_config->name); \
11706 return false; \
11707 }
11708
Daniel Vetter08a24032013-04-19 11:25:34 +020011709#define PIPE_CONF_CHECK_I(name) \
11710 if (current_config->name != pipe_config->name) { \
11711 DRM_ERROR("mismatch in " #name " " \
11712 "(expected %i, found %i)\n", \
11713 current_config->name, \
11714 pipe_config->name); \
11715 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010011716 }
11717
Vandana Kannanb95af8b2014-08-05 07:51:23 -070011718/* This is required for BDW+ where there is only one set of registers for
11719 * switching between high and low RR.
11720 * This macro can be used whenever a comparison has to be made between one
11721 * hw state and multiple sw state variables.
11722 */
11723#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11724 if ((current_config->name != pipe_config->name) && \
11725 (current_config->alt_name != pipe_config->name)) { \
11726 DRM_ERROR("mismatch in " #name " " \
11727 "(expected %i or %i, found %i)\n", \
11728 current_config->name, \
11729 current_config->alt_name, \
11730 pipe_config->name); \
11731 return false; \
11732 }
11733
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011734#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11735 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070011736 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011737 "(expected %i, found %i)\n", \
11738 current_config->name & (mask), \
11739 pipe_config->name & (mask)); \
11740 return false; \
11741 }
11742
Ville Syrjälä5e550652013-09-06 23:29:07 +030011743#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11744 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11745 DRM_ERROR("mismatch in " #name " " \
11746 "(expected %i, found %i)\n", \
11747 current_config->name, \
11748 pipe_config->name); \
11749 return false; \
11750 }
11751
Daniel Vetterbb760062013-06-06 14:55:52 +020011752#define PIPE_CONF_QUIRK(quirk) \
11753 ((current_config->quirks | pipe_config->quirks) & (quirk))
11754
Daniel Vettereccb1402013-05-22 00:50:22 +020011755 PIPE_CONF_CHECK_I(cpu_transcoder);
11756
Daniel Vetter08a24032013-04-19 11:25:34 +020011757 PIPE_CONF_CHECK_I(has_pch_encoder);
11758 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020011759 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11760 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11761 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11762 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11763 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020011764
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030011765 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070011766
11767 if (INTEL_INFO(dev)->gen < 8) {
11768 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11769 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11770 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11771 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11772 PIPE_CONF_CHECK_I(dp_m_n.tu);
11773
11774 if (current_config->has_drrs) {
11775 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11776 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11777 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11778 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11779 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11780 }
11781 } else {
11782 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11783 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11784 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11785 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11786 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11787 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030011788
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011789 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11790 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11791 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11792 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11793 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11794 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011795
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011796 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11797 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11801 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011802
Daniel Vetterc93f54c2013-06-27 19:47:19 +020011803 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b52014-04-24 23:54:47 +020011804 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020011805 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11806 IS_VALLEYVIEW(dev))
11807 PIPE_CONF_CHECK_I(limited_color_range);
Jesse Barnese43823e2014-11-05 14:26:08 -080011808 PIPE_CONF_CHECK_I(has_infoframe);
Daniel Vetter6c49f242013-06-06 12:45:25 +020011809
Daniel Vetter9ed109a2014-04-24 23:54:52 +020011810 PIPE_CONF_CHECK_I(has_audio);
11811
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011812 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011813 DRM_MODE_FLAG_INTERLACE);
11814
Daniel Vetterbb760062013-06-06 14:55:52 +020011815 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011816 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020011817 DRM_MODE_FLAG_PHSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011818 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020011819 DRM_MODE_FLAG_NHSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011820 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020011821 DRM_MODE_FLAG_PVSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011822 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020011823 DRM_MODE_FLAG_NVSYNC);
11824 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070011825
Ville Syrjälä37327ab2013-09-04 18:25:28 +030011826 PIPE_CONF_CHECK_I(pipe_src_w);
11827 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011828
Daniel Vetter99535992014-04-13 12:00:33 +020011829 /*
11830 * FIXME: BIOS likes to set up a cloned config with lvds+external
11831 * screen. Since we don't yet re-compute the pipe config when moving
11832 * just the lvds port away to another pipe the sw tracking won't match.
11833 *
11834 * Proper atomic modesets with recomputed global state will fix this.
11835 * Until then just don't check gmch state for inherited modes.
11836 */
11837 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11838 PIPE_CONF_CHECK_I(gmch_pfit.control);
11839 /* pfit ratios are autocomputed by the hw on gen4+ */
11840 if (INTEL_INFO(dev)->gen < 4)
11841 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11842 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11843 }
11844
Chris Wilsonfd4daa92013-08-27 17:04:17 +010011845 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11846 if (current_config->pch_pfit.enabled) {
11847 PIPE_CONF_CHECK_I(pch_pfit.pos);
11848 PIPE_CONF_CHECK_I(pch_pfit.size);
11849 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020011850
Chandra Kondurua1b22782015-04-07 15:28:45 -070011851 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11852
Jesse Barnese59150d2014-01-07 13:30:45 -080011853 /* BDW+ don't expose a synchronous way to read the state */
11854 if (IS_HASWELL(dev))
11855 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030011856
Ville Syrjälä282740f2013-09-04 18:30:03 +030011857 PIPE_CONF_CHECK_I(double_wide);
11858
Daniel Vetter26804af2014-06-25 22:01:55 +030011859 PIPE_CONF_CHECK_X(ddi_pll_sel);
11860
Daniel Vetterc0d43d62013-06-07 23:11:08 +020011861 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020011862 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020011863 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020011864 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11865 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030011866 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Damien Lespiau3f4cd192014-11-13 14:55:21 +000011867 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11868 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11869 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020011870
Ville Syrjälä42571ae2013-09-06 23:29:00 +030011871 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11872 PIPE_CONF_CHECK_I(pipe_bpp);
11873
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020011874 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
Jesse Barnesa9a7e982014-01-20 14:18:04 -080011875 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030011876
Daniel Vetter66e985c2013-06-05 13:34:20 +020011877#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020011878#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070011879#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020011880#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030011881#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020011882#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020011883
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011884 return true;
11885}
11886
Damien Lespiau08db6652014-11-04 17:06:52 +000011887static void check_wm_state(struct drm_device *dev)
11888{
11889 struct drm_i915_private *dev_priv = dev->dev_private;
11890 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11891 struct intel_crtc *intel_crtc;
11892 int plane;
11893
11894 if (INTEL_INFO(dev)->gen < 9)
11895 return;
11896
11897 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11898 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11899
11900 for_each_intel_crtc(dev, intel_crtc) {
11901 struct skl_ddb_entry *hw_entry, *sw_entry;
11902 const enum pipe pipe = intel_crtc->pipe;
11903
11904 if (!intel_crtc->active)
11905 continue;
11906
11907 /* planes */
Damien Lespiaudd740782015-02-28 14:54:08 +000011908 for_each_plane(dev_priv, pipe, plane) {
Damien Lespiau08db6652014-11-04 17:06:52 +000011909 hw_entry = &hw_ddb.plane[pipe][plane];
11910 sw_entry = &sw_ddb->plane[pipe][plane];
11911
11912 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11913 continue;
11914
11915 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11916 "(expected (%u,%u), found (%u,%u))\n",
11917 pipe_name(pipe), plane + 1,
11918 sw_entry->start, sw_entry->end,
11919 hw_entry->start, hw_entry->end);
11920 }
11921
11922 /* cursor */
11923 hw_entry = &hw_ddb.cursor[pipe];
11924 sw_entry = &sw_ddb->cursor[pipe];
11925
11926 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11927 continue;
11928
11929 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11930 "(expected (%u,%u), found (%u,%u))\n",
11931 pipe_name(pipe),
11932 sw_entry->start, sw_entry->end,
11933 hw_entry->start, hw_entry->end);
11934 }
11935}
11936
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020011937static void
11938check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011939{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011940 struct intel_connector *connector;
11941
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020011942 for_each_intel_connector(dev, connector) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011943 /* This also checks the encoder/connector hw state with the
11944 * ->get_hw_state callbacks. */
11945 intel_connector_check_state(connector);
11946
Rob Clarke2c719b2014-12-15 13:56:32 -050011947 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011948 "connector's staged encoder doesn't match current encoder\n");
11949 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020011950}
11951
11952static void
11953check_encoder_state(struct drm_device *dev)
11954{
11955 struct intel_encoder *encoder;
11956 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011957
Damien Lespiaub2784e12014-08-05 11:29:37 +010011958 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011959 bool enabled = false;
11960 bool active = false;
11961 enum pipe pipe, tracked_pipe;
11962
11963 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11964 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030011965 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011966
Rob Clarke2c719b2014-12-15 13:56:32 -050011967 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011968 "encoder's stage crtc doesn't match current crtc\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050011969 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011970 "encoder's active_connectors set, but no crtc\n");
11971
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020011972 for_each_intel_connector(dev, connector) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011973 if (connector->base.encoder != &encoder->base)
11974 continue;
11975 enabled = true;
11976 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11977 active = true;
11978 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011979 /*
11980 * for MST connectors if we unplug the connector is gone
11981 * away but the encoder is still connected to a crtc
11982 * until a modeset happens in response to the hotplug.
11983 */
11984 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11985 continue;
11986
Rob Clarke2c719b2014-12-15 13:56:32 -050011987 I915_STATE_WARN(!!encoder->base.crtc != enabled,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011988 "encoder's enabled state mismatch "
11989 "(expected %i, found %i)\n",
11990 !!encoder->base.crtc, enabled);
Rob Clarke2c719b2014-12-15 13:56:32 -050011991 I915_STATE_WARN(active && !encoder->base.crtc,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011992 "active encoder with no crtc\n");
11993
Rob Clarke2c719b2014-12-15 13:56:32 -050011994 I915_STATE_WARN(encoder->connectors_active != active,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011995 "encoder's computed active state doesn't match tracked active state "
11996 "(expected %i, found %i)\n", active, encoder->connectors_active);
11997
11998 active = encoder->get_hw_state(encoder, &pipe);
Rob Clarke2c719b2014-12-15 13:56:32 -050011999 I915_STATE_WARN(active != encoder->connectors_active,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012000 "encoder's hw state doesn't match sw tracking "
12001 "(expected %i, found %i)\n",
12002 encoder->connectors_active, active);
12003
12004 if (!encoder->base.crtc)
12005 continue;
12006
12007 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
Rob Clarke2c719b2014-12-15 13:56:32 -050012008 I915_STATE_WARN(active && pipe != tracked_pipe,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012009 "active encoder's pipe doesn't match"
12010 "(expected %i, found %i)\n",
12011 tracked_pipe, pipe);
12012
12013 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012014}
12015
12016static void
12017check_crtc_state(struct drm_device *dev)
12018{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012019 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012020 struct intel_crtc *crtc;
12021 struct intel_encoder *encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012022 struct intel_crtc_state pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012023
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012024 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012025 bool enabled = false;
12026 bool active = false;
12027
Jesse Barnes045ac3b2013-05-14 17:08:26 -070012028 memset(&pipe_config, 0, sizeof(pipe_config));
12029
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012030 DRM_DEBUG_KMS("[CRTC:%d]\n",
12031 crtc->base.base.id);
12032
Matt Roper83d65732015-02-25 13:12:16 -080012033 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012034 "active crtc, but not enabled in sw tracking\n");
12035
Damien Lespiaub2784e12014-08-05 11:29:37 +010012036 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012037 if (encoder->base.crtc != &crtc->base)
12038 continue;
12039 enabled = true;
12040 if (encoder->connectors_active)
12041 active = true;
12042 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020012043
Rob Clarke2c719b2014-12-15 13:56:32 -050012044 I915_STATE_WARN(active != crtc->active,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012045 "crtc's computed active state doesn't match tracked active state "
12046 "(expected %i, found %i)\n", active, crtc->active);
Matt Roper83d65732015-02-25 13:12:16 -080012047 I915_STATE_WARN(enabled != crtc->base.state->enable,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012048 "crtc's computed enabled state doesn't match tracked enabled state "
Matt Roper83d65732015-02-25 13:12:16 -080012049 "(expected %i, found %i)\n", enabled,
12050 crtc->base.state->enable);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012051
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012052 active = dev_priv->display.get_pipe_config(crtc,
12053 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020012054
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012055 /* hw state is inconsistent with the pipe quirk */
12056 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12057 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetterd62cf622013-05-29 10:41:29 +020012058 active = crtc->active;
12059
Damien Lespiaub2784e12014-08-05 11:29:37 +010012060 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030012061 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020012062 if (encoder->base.crtc != &crtc->base)
12063 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010012064 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020012065 encoder->get_config(encoder, &pipe_config);
12066 }
12067
Rob Clarke2c719b2014-12-15 13:56:32 -050012068 I915_STATE_WARN(crtc->active != active,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012069 "crtc active state doesn't match with hw state "
12070 "(expected %i, found %i)\n", crtc->active, active);
12071
Daniel Vetterc0b03412013-05-28 12:05:54 +020012072 if (active &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020012073 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
Rob Clarke2c719b2014-12-15 13:56:32 -050012074 I915_STATE_WARN(1, "pipe state doesn't match!\n");
Daniel Vetterc0b03412013-05-28 12:05:54 +020012075 intel_dump_pipe_config(crtc, &pipe_config,
12076 "[hw state]");
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020012077 intel_dump_pipe_config(crtc, crtc->config,
Daniel Vetterc0b03412013-05-28 12:05:54 +020012078 "[sw state]");
12079 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012080 }
12081}
12082
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012083static void
12084check_shared_dpll_state(struct drm_device *dev)
12085{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012086 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012087 struct intel_crtc *crtc;
12088 struct intel_dpll_hw_state dpll_hw_state;
12089 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020012090
12091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12092 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12093 int enabled_crtcs = 0, active_crtcs = 0;
12094 bool active;
12095
12096 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12097
12098 DRM_DEBUG_KMS("%s\n", pll->name);
12099
12100 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12101
Rob Clarke2c719b2014-12-15 13:56:32 -050012102 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
Daniel Vetter53589012013-06-05 13:34:16 +020012103 "more active pll users than references: %i vs %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020012104 pll->active, hweight32(pll->config.crtc_mask));
Rob Clarke2c719b2014-12-15 13:56:32 -050012105 I915_STATE_WARN(pll->active && !pll->on,
Daniel Vetter53589012013-06-05 13:34:16 +020012106 "pll in active use but not on in sw tracking\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050012107 I915_STATE_WARN(pll->on && !pll->active,
Daniel Vetter35c95372013-07-17 06:55:04 +020012108 "pll in on but not on in use in sw tracking\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050012109 I915_STATE_WARN(pll->on != active,
Daniel Vetter53589012013-06-05 13:34:16 +020012110 "pll on state mismatch (expected %i, found %i)\n",
12111 pll->on, active);
12112
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012113 for_each_intel_crtc(dev, crtc) {
Matt Roper83d65732015-02-25 13:12:16 -080012114 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
Daniel Vetter53589012013-06-05 13:34:16 +020012115 enabled_crtcs++;
12116 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12117 active_crtcs++;
12118 }
Rob Clarke2c719b2014-12-15 13:56:32 -050012119 I915_STATE_WARN(pll->active != active_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020012120 "pll active crtcs mismatch (expected %i, found %i)\n",
12121 pll->active, active_crtcs);
Rob Clarke2c719b2014-12-15 13:56:32 -050012122 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020012123 "pll enabled crtcs mismatch (expected %i, found %i)\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020012124 hweight32(pll->config.crtc_mask), enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020012125
Rob Clarke2c719b2014-12-15 13:56:32 -050012126 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
Daniel Vetter66e985c2013-06-05 13:34:20 +020012127 sizeof(dpll_hw_state)),
12128 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020012129 }
Daniel Vettere2e1ed42012-07-08 21:14:38 +020012130}
12131
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012132void
12133intel_modeset_check_state(struct drm_device *dev)
12134{
Damien Lespiau08db6652014-11-04 17:06:52 +000012135 check_wm_state(dev);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012136 check_connector_state(dev);
12137 check_encoder_state(dev);
12138 check_crtc_state(dev);
12139 check_shared_dpll_state(dev);
12140}
12141
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012142void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
Ville Syrjälä18442d02013-09-13 16:00:08 +030012143 int dotclock)
12144{
12145 /*
12146 * FDI already provided one idea for the dotclock.
12147 * Yell if the encoder disagrees.
12148 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012149 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030012150 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012151 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030012152}
12153
Ville Syrjälä80715b22014-05-15 20:23:23 +030012154static void update_scanline_offset(struct intel_crtc *crtc)
12155{
12156 struct drm_device *dev = crtc->base.dev;
12157
12158 /*
12159 * The scanline counter increments at the leading edge of hsync.
12160 *
12161 * On most platforms it starts counting from vtotal-1 on the
12162 * first active line. That means the scanline counter value is
12163 * always one less than what we would expect. Ie. just after
12164 * start of vblank, which also occurs at start of hsync (on the
12165 * last active line), the scanline counter will read vblank_start-1.
12166 *
12167 * On gen2 the scanline counter starts counting from 1 instead
12168 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12169 * to keep the value positive), instead of adding one.
12170 *
12171 * On HSW+ the behaviour of the scanline counter depends on the output
12172 * type. For DP ports it behaves like most other platforms, but on HDMI
12173 * there's an extra 1 line difference. So we need to add two instead of
12174 * one to the value.
12175 */
12176 if (IS_GEN2(dev)) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020012177 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
Ville Syrjälä80715b22014-05-15 20:23:23 +030012178 int vtotal;
12179
12180 vtotal = mode->crtc_vtotal;
12181 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12182 vtotal /= 2;
12183
12184 crtc->scanline_offset = vtotal - 1;
12185 } else if (HAS_DDI(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +030012186 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
Ville Syrjälä80715b22014-05-15 20:23:23 +030012187 crtc->scanline_offset = 2;
12188 } else
12189 crtc->scanline_offset = 1;
12190}
12191
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012192static struct intel_crtc_state *
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012193intel_modeset_compute_config(struct drm_crtc *crtc,
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012194 struct drm_atomic_state *state)
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012195{
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012196 struct intel_crtc_state *pipe_config;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020012197 int ret = 0;
12198
12199 ret = drm_atomic_add_affected_connectors(state, crtc);
12200 if (ret)
12201 return ERR_PTR(ret);
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012202
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012203 ret = drm_atomic_helper_check_modeset(state->dev, state);
12204 if (ret)
12205 return ERR_PTR(ret);
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012206
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012207 /*
12208 * Note this needs changes when we start tracking multiple modes
12209 * and crtcs. At that point we'll need to compute the whole config
12210 * (i.e. one pipe_config for each crtc) rather than just the one
12211 * for this crtc.
12212 */
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012213 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12214 if (IS_ERR(pipe_config))
12215 return pipe_config;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012216
Ander Conselvan de Oliveira4fed33f2015-04-21 17:13:03 +030012217 if (!pipe_config->base.enable)
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012218 return pipe_config;
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012219
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012220 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012221 if (ret)
12222 return ERR_PTR(ret);
Ander Conselvan de Oliveiradb7542d2015-03-20 16:18:04 +020012223
Ander Conselvan de Oliveira8d8c9b52015-04-21 17:13:11 +030012224 /* Check things that can only be changed through modeset */
12225 if (pipe_config->has_audio !=
12226 to_intel_crtc(crtc)->config->has_audio)
12227 pipe_config->base.mode_changed = true;
12228
12229 /*
12230 * Note we have an issue here with infoframes: current code
12231 * only updates them on the full mode set path per hw
12232 * requirements. So here we should be checking for any
12233 * required changes and forcing a mode set.
12234 */
12235
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012236 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12237
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012238 ret = drm_atomic_helper_check_planes(state->dev, state);
12239 if (ret)
12240 return ERR_PTR(ret);
12241
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012242 return pipe_config;
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012243}
12244
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012245static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012246{
Ander Conselvan de Oliveira225da592015-04-02 14:47:57 +030012247 struct drm_device *dev = state->dev;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012248 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012249 unsigned clear_pipes = 0;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012250 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012251 struct intel_crtc_state *intel_crtc_state;
12252 struct drm_crtc *crtc;
12253 struct drm_crtc_state *crtc_state;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012254 int ret = 0;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012255 int i;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012256
12257 if (!dev_priv->display.crtc_compute_clock)
12258 return 0;
12259
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012260 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12261 intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012262 intel_crtc_state = to_intel_crtc_state(crtc_state);
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012263
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012264 if (needs_modeset(crtc_state)) {
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012265 clear_pipes |= 1 << intel_crtc->pipe;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012266 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12267 memset(&intel_crtc_state->dpll_hw_state, 0,
12268 sizeof(intel_crtc_state->dpll_hw_state));
12269 }
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012270 }
12271
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012272 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12273 if (ret)
12274 goto done;
12275
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012276 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12277 if (!needs_modeset(crtc_state) || !crtc_state->enable)
Ander Conselvan de Oliveira225da592015-04-02 14:47:57 +030012278 continue;
12279
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012280 intel_crtc = to_intel_crtc(crtc);
12281 intel_crtc_state = to_intel_crtc_state(crtc_state);
12282
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012283 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012284 intel_crtc_state);
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020012285 if (ret) {
12286 intel_shared_dpll_abort_config(dev_priv);
12287 goto done;
12288 }
12289 }
12290
12291done:
12292 return ret;
12293}
12294
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030012295/* Code that should eventually be part of atomic_check() */
12296static int __intel_set_mode_checks(struct drm_atomic_state *state)
12297{
12298 struct drm_device *dev = state->dev;
12299 int ret;
12300
12301 /*
12302 * See if the config requires any additional preparation, e.g.
12303 * to adjust global state with pipes off. We need to do this
12304 * here so we can get the modeset_pipe updated config for the new
12305 * mode set on this crtc. For other crtcs we need to use the
12306 * adjusted_mode bits in the crtc directly.
12307 */
12308 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12309 ret = valleyview_modeset_global_pipes(state);
12310 if (ret)
12311 return ret;
12312 }
12313
12314 ret = __intel_set_mode_setup_plls(state);
12315 if (ret)
12316 return ret;
12317
12318 return 0;
12319}
12320
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012321static int __intel_set_mode(struct drm_crtc *modeset_crtc,
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012322 struct intel_crtc_state *pipe_config)
Daniel Vettera6778b32012-07-02 09:56:42 +020012323{
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012324 struct drm_device *dev = modeset_crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030012325 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +030012326 struct drm_atomic_state *state = pipe_config->base.state;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012327 struct drm_crtc *crtc;
12328 struct drm_crtc_state *crtc_state;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000012329 int ret = 0;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012330 int i;
Daniel Vettera6778b32012-07-02 09:56:42 +020012331
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030012332 ret = __intel_set_mode_checks(state);
12333 if (ret < 0)
12334 return ret;
12335
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030012336 ret = drm_atomic_helper_prepare_planes(dev, state);
12337 if (ret)
12338 return ret;
12339
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012340 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12341 if (!needs_modeset(crtc_state))
12342 continue;
Daniel Vetter460da9162013-03-27 00:44:51 +010012343
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012344 if (!crtc_state->enable) {
Matt Roper90d46902015-05-07 14:31:28 -070012345 crtc_state->active = false;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012346 intel_crtc_disable(crtc);
12347 } else if (crtc->state->enable) {
12348 intel_crtc_disable_planes(crtc);
12349 dev_priv->display.crtc_disable(crtc);
Maarten Lankhorstce22dba2015-04-21 17:12:56 +030012350 }
Daniel Vetterea9d7582012-07-10 10:42:52 +020012351 }
Daniel Vettera6778b32012-07-02 09:56:42 +020012352
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020012353 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12354 * to set it here already despite that we pass it down the callchain.
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012355 *
12356 * Note we'll need to fix this up when we start tracking multiple
12357 * pipes; here we assume a single modeset_pipe and only track the
12358 * single crtc and mode.
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020012359 */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012360 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012361 modeset_crtc->mode = pipe_config->base.mode;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020012362
12363 /*
12364 * Calculate and store various constants which
12365 * are later needed by vblank and swap-completion
12366 * timestamping. They are derived from true hwmode.
12367 */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012368 drm_calc_timestamping_constants(modeset_crtc,
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012369 &pipe_config->base.adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010012370 }
Daniel Vetter7758a112012-07-08 19:40:39 +020012371
Daniel Vetterea9d7582012-07-10 10:42:52 +020012372 /* Only after disabling all output pipelines that will be changed can we
12373 * update the the output configuration. */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012374 intel_modeset_update_state(state);
Daniel Vetterea9d7582012-07-10 10:42:52 +020012375
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030012376 /* The state has been swaped above, so state actually contains the
12377 * old state now. */
12378
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +030012379 modeset_update_crtc_power_domains(state);
Daniel Vetter47fab732012-10-26 10:58:18 +020012380
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030012381 drm_atomic_helper_commit_planes(dev, state);
Daniel Vettera6778b32012-07-02 09:56:42 +020012382
12383 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012384 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +030012385 if (!needs_modeset(crtc->state) || !crtc->state->enable)
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012386 continue;
Ville Syrjälä80715b22014-05-15 20:23:23 +030012387
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012388 update_scanline_offset(to_intel_crtc(crtc));
12389
12390 dev_priv->display.crtc_enable(crtc);
12391 intel_crtc_enable_planes(crtc);
Ville Syrjälä80715b22014-05-15 20:23:23 +030012392 }
Daniel Vettera6778b32012-07-02 09:56:42 +020012393
Daniel Vettera6778b32012-07-02 09:56:42 +020012394 /* FIXME: add subpixel order */
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012395
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030012396 drm_atomic_helper_cleanup_planes(dev, state);
12397
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030012398 drm_atomic_state_free(state);
12399
Ander Conselvan de Oliveira9eb45f22015-04-21 17:13:07 +030012400 return 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020012401}
12402
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012403static int intel_set_mode_with_config(struct drm_crtc *crtc,
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012404 struct intel_crtc_state *pipe_config)
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012405{
12406 int ret;
12407
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012408 ret = __intel_set_mode(crtc, pipe_config);
Jesse Barnes7f27126e2014-11-05 14:26:06 -080012409
12410 if (ret == 0)
12411 intel_modeset_check_state(crtc->dev);
12412
12413 return ret;
12414}
12415
Damien Lespiaue7457a92013-08-08 22:28:59 +010012416static int intel_set_mode(struct drm_crtc *crtc,
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012417 struct drm_atomic_state *state)
Daniel Vetterf30da182013-04-11 20:22:50 +020012418{
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012419 struct intel_crtc_state *pipe_config;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012420 int ret = 0;
Daniel Vetterf30da182013-04-11 20:22:50 +020012421
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012422 pipe_config = intel_modeset_compute_config(crtc, state);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012423 if (IS_ERR(pipe_config)) {
12424 ret = PTR_ERR(pipe_config);
12425 goto out;
12426 }
Daniel Vetterf30da182013-04-11 20:22:50 +020012427
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012428 ret = intel_set_mode_with_config(crtc, pipe_config);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012429 if (ret)
12430 goto out;
12431
12432out:
12433 return ret;
Daniel Vetterf30da182013-04-11 20:22:50 +020012434}
12435
Chris Wilsonc0c36b942012-12-19 16:08:43 +000012436void intel_crtc_restore_mode(struct drm_crtc *crtc)
12437{
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012438 struct drm_device *dev = crtc->dev;
12439 struct drm_atomic_state *state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030012440 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012441 struct intel_encoder *encoder;
12442 struct intel_connector *connector;
12443 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030012444 struct intel_crtc_state *crtc_state;
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030012445 int ret;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012446
12447 state = drm_atomic_state_alloc(dev);
12448 if (!state) {
12449 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12450 crtc->base.id);
12451 return;
12452 }
12453
12454 state->acquire_ctx = dev->mode_config.acquire_ctx;
12455
12456 /* The force restore path in the HW readout code relies on the staged
12457 * config still keeping the user requested config while the actual
12458 * state has been overwritten by the configuration read from HW. We
12459 * need to copy the staged config to the atomic state, otherwise the
12460 * mode set will just reapply the state the HW is already in. */
12461 for_each_intel_encoder(dev, encoder) {
12462 if (&encoder->new_crtc->base != crtc)
12463 continue;
12464
12465 for_each_intel_connector(dev, connector) {
12466 if (connector->new_encoder != encoder)
12467 continue;
12468
12469 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12470 if (IS_ERR(connector_state)) {
12471 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12472 connector->base.base.id,
12473 connector->base.name,
12474 PTR_ERR(connector_state));
12475 continue;
12476 }
12477
12478 connector_state->crtc = crtc;
12479 connector_state->best_encoder = &encoder->base;
12480 }
12481 }
12482
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030012483 for_each_intel_crtc(dev, intel_crtc) {
12484 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12485 continue;
12486
12487 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12488 if (IS_ERR(crtc_state)) {
12489 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12490 intel_crtc->base.base.id,
12491 PTR_ERR(crtc_state));
12492 continue;
12493 }
12494
12495 crtc_state->base.enable = intel_crtc->new_enabled;
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012496
12497 if (&intel_crtc->base == crtc)
12498 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030012499 }
12500
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030012501 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12502 crtc->primary->fb, crtc->x, crtc->y);
12503
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030012504 ret = intel_set_mode(crtc, state);
12505 if (ret)
12506 drm_atomic_state_free(state);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000012507}
12508
Daniel Vetter25c5b262012-07-08 22:08:04 +020012509#undef for_each_intel_crtc_masked
12510
Ander Conselvan de Oliveirab7885262015-04-21 17:13:14 +030012511static bool intel_connector_in_mode_set(struct intel_connector *connector,
12512 struct drm_mode_set *set)
12513{
12514 int ro;
12515
12516 for (ro = 0; ro < set->num_connectors; ro++)
12517 if (set->connectors[ro] == &connector->base)
12518 return true;
12519
12520 return false;
12521}
12522
Daniel Vetter2e431052012-07-04 22:42:15 +020012523static int
Daniel Vetter9a935852012-07-05 22:34:27 +020012524intel_modeset_stage_output_state(struct drm_device *dev,
12525 struct drm_mode_set *set,
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020012526 struct drm_atomic_state *state)
Daniel Vetter50f56112012-07-02 09:35:43 +020012527{
Daniel Vetter9a935852012-07-05 22:34:27 +020012528 struct intel_connector *connector;
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012529 struct drm_connector *drm_connector;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020012530 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012531 struct drm_crtc *crtc;
12532 struct drm_crtc_state *crtc_state;
12533 int i, ret;
Daniel Vetter50f56112012-07-02 09:35:43 +020012534
Damien Lespiau9abdda72013-02-13 13:29:23 +000012535 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020012536 * of connectors. For paranoia, double-check this. */
12537 WARN_ON(!set->fb && (set->num_connectors != 0));
12538 WARN_ON(set->fb && (set->num_connectors == 0));
12539
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020012540 for_each_intel_connector(dev, connector) {
Ander Conselvan de Oliveirab7885262015-04-21 17:13:14 +030012541 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12542
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012543 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12544 continue;
12545
12546 connector_state =
12547 drm_atomic_get_connector_state(state, &connector->base);
12548 if (IS_ERR(connector_state))
12549 return PTR_ERR(connector_state);
12550
Ander Conselvan de Oliveirab7885262015-04-21 17:13:14 +030012551 if (in_mode_set) {
12552 int pipe = to_intel_crtc(set->crtc)->pipe;
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012553 connector_state->best_encoder =
12554 &intel_find_encoder(connector, pipe)->base;
Daniel Vetter50f56112012-07-02 09:35:43 +020012555 }
12556
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012557 if (connector->base.state->crtc != set->crtc)
Ander Conselvan de Oliveirab7885262015-04-21 17:13:14 +030012558 continue;
12559
Daniel Vetter9a935852012-07-05 22:34:27 +020012560 /* If we disable the crtc, disable all its connectors. Also, if
12561 * the connector is on the changing crtc but not on the new
12562 * connector list, disable it. */
Ander Conselvan de Oliveirab7885262015-04-21 17:13:14 +030012563 if (!set->fb || !in_mode_set) {
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012564 connector_state->best_encoder = NULL;
Daniel Vetter9a935852012-07-05 22:34:27 +020012565
12566 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12567 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030012568 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020012569 }
Daniel Vetter9a935852012-07-05 22:34:27 +020012570 }
12571 /* connector->new_encoder is now updated for all connectors. */
12572
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012573 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12574 connector = to_intel_connector(drm_connector);
Ville Syrjälä76688512014-01-10 11:28:06 +020012575
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012576 if (!connector_state->best_encoder) {
12577 ret = drm_atomic_set_crtc_for_connector(connector_state,
12578 NULL);
12579 if (ret)
12580 return ret;
12581
Daniel Vetter50f56112012-07-02 09:35:43 +020012582 continue;
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012583 }
Daniel Vetter50f56112012-07-02 09:35:43 +020012584
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012585 if (intel_connector_in_mode_set(connector, set)) {
12586 struct drm_crtc *crtc = connector->base.state->crtc;
12587
12588 /* If this connector was in a previous crtc, add it
12589 * to the state. We might need to disable it. */
12590 if (crtc) {
12591 crtc_state =
12592 drm_atomic_get_crtc_state(state, crtc);
12593 if (IS_ERR(crtc_state))
12594 return PTR_ERR(crtc_state);
12595 }
12596
12597 ret = drm_atomic_set_crtc_for_connector(connector_state,
12598 set->crtc);
12599 if (ret)
12600 return ret;
12601 }
Daniel Vetter50f56112012-07-02 09:35:43 +020012602
12603 /* Make sure the new CRTC will work with the encoder */
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012604 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12605 connector_state->crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020012606 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020012607 }
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020012608
Daniel Vetter9a935852012-07-05 22:34:27 +020012609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12610 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030012611 connector->base.name,
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012612 connector_state->crtc->base.id);
12613
12614 if (connector_state->best_encoder != &connector->encoder->base)
12615 connector->encoder =
12616 to_intel_encoder(connector_state->best_encoder);
Daniel Vetter9a935852012-07-05 22:34:27 +020012617 }
12618
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012619 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12620 ret = drm_atomic_add_affected_connectors(state, crtc);
12621 if (ret)
12622 return ret;
Paulo Zanoni5a65f352014-01-07 14:55:53 -020012623
Ander Conselvan de Oliveirad5432a9d2015-04-21 17:13:15 +030012624 crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020012625 }
12626
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012627 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12628 set->fb, set->x, set->y);
12629 if (ret)
12630 return ret;
12631
12632 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12633 if (IS_ERR(crtc_state))
12634 return PTR_ERR(crtc_state);
12635
12636 if (set->mode)
12637 drm_mode_copy(&crtc_state->mode, set->mode);
12638
12639 if (set->num_connectors)
12640 crtc_state->active = true;
12641
Daniel Vetter2e431052012-07-04 22:42:15 +020012642 return 0;
12643}
12644
Ander Conselvan de Oliveirabb546622015-04-21 17:13:13 +030012645static bool primary_plane_visible(struct drm_crtc *crtc)
12646{
12647 struct intel_plane_state *plane_state =
12648 to_intel_plane_state(crtc->primary->state);
12649
12650 return plane_state->visible;
12651}
12652
Daniel Vetter2e431052012-07-04 22:42:15 +020012653static int intel_crtc_set_config(struct drm_mode_set *set)
12654{
12655 struct drm_device *dev;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012656 struct drm_atomic_state *state = NULL;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012657 struct intel_crtc_state *pipe_config;
Ander Conselvan de Oliveirabb546622015-04-21 17:13:13 +030012658 bool primary_plane_was_visible;
Daniel Vetter2e431052012-07-04 22:42:15 +020012659 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020012660
Daniel Vetter8d3e3752012-07-05 16:09:09 +020012661 BUG_ON(!set);
12662 BUG_ON(!set->crtc);
12663 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020012664
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010012665 /* Enforce sane interface api - has been abused by the fb helper. */
12666 BUG_ON(!set->mode && set->fb);
12667 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020012668
Daniel Vetter2e431052012-07-04 22:42:15 +020012669 if (set->fb) {
12670 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12671 set->crtc->base.id, set->fb->base.id,
12672 (int)set->num_connectors, set->x, set->y);
12673 } else {
12674 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020012675 }
12676
12677 dev = set->crtc->dev;
12678
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012679 state = drm_atomic_state_alloc(dev);
Ander Conselvan de Oliveira7cbf41d2015-04-21 17:13:16 +030012680 if (!state)
12681 return -ENOMEM;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012682
12683 state->acquire_ctx = dev->mode_config.acquire_ctx;
12684
Ander Conselvan de Oliveira462a4252015-04-21 17:13:00 +030012685 ret = intel_modeset_stage_output_state(dev, set, state);
Daniel Vetter2e431052012-07-04 22:42:15 +020012686 if (ret)
Ander Conselvan de Oliveira7cbf41d2015-04-21 17:13:16 +030012687 goto out;
Daniel Vetter2e431052012-07-04 22:42:15 +020012688
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012689 pipe_config = intel_modeset_compute_config(set->crtc, state);
Jesse Barnes20664592014-11-05 14:26:09 -080012690 if (IS_ERR(pipe_config)) {
Matt Roper6ac04832014-11-17 09:59:28 -080012691 ret = PTR_ERR(pipe_config);
Ander Conselvan de Oliveira7cbf41d2015-04-21 17:13:16 +030012692 goto out;
Jesse Barnes20664592014-11-05 14:26:09 -080012693 }
Jesse Barnes50f52752014-11-07 13:11:00 -080012694
Jesse Barnes1f9954d2014-11-05 14:26:10 -080012695 intel_update_pipe_size(to_intel_crtc(set->crtc));
12696
Ander Conselvan de Oliveirabb546622015-04-21 17:13:13 +030012697 primary_plane_was_visible = primary_plane_visible(set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070012698
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030012699 ret = intel_set_mode_with_config(set->crtc, pipe_config);
Ander Conselvan de Oliveirabb546622015-04-21 17:13:13 +030012700
12701 if (ret == 0 &&
12702 pipe_config->base.enable &&
12703 pipe_config->base.planes_changed &&
12704 !needs_modeset(&pipe_config->base)) {
12705 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070012706
12707 /*
12708 * We need to make sure the primary plane is re-enabled if it
12709 * has previously been turned off.
12710 */
Ander Conselvan de Oliveirabb546622015-04-21 17:13:13 +030012711 if (ret == 0 && !primary_plane_was_visible &&
12712 primary_plane_visible(set->crtc)) {
Matt Roper3b150f02014-05-29 08:06:53 -070012713 WARN_ON(!intel_crtc->active);
Maarten Lankhorst87d43002015-04-21 17:12:54 +030012714 intel_post_enable_primary(set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070012715 }
12716
Jesse Barnes7ca51a32014-01-07 13:50:49 -080012717 /*
12718 * In the fastboot case this may be our only check of the
12719 * state after boot. It would be better to only do it on
12720 * the first update, but we don't have a nice way of doing that
12721 * (and really, set_config isn't used much for high freq page
12722 * flipping, so increasing its cost here shouldn't be a big
12723 * deal).
12724 */
Jani Nikulad330a952014-01-21 11:24:25 +020012725 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080012726 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020012727 }
12728
Chris Wilson2d05eae2013-05-03 17:36:25 +010012729 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020012730 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12731 set->crtc->base.id, ret);
Chris Wilson2d05eae2013-05-03 17:36:25 +010012732 }
Daniel Vetter50f56112012-07-02 09:35:43 +020012733
Ander Conselvan de Oliveira7cbf41d2015-04-21 17:13:16 +030012734out:
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030012735 if (ret)
12736 drm_atomic_state_free(state);
Daniel Vetter50f56112012-07-02 09:35:43 +020012737 return ret;
12738}
12739
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012740static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012741 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020012742 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012743 .destroy = intel_crtc_destroy,
12744 .page_flip = intel_crtc_page_flip,
Matt Roper13568372015-01-21 16:35:47 -080012745 .atomic_duplicate_state = intel_crtc_duplicate_state,
12746 .atomic_destroy_state = intel_crtc_destroy_state,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012747};
12748
Daniel Vetter53589012013-06-05 13:34:16 +020012749static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12750 struct intel_shared_dpll *pll,
12751 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012752{
Daniel Vetter53589012013-06-05 13:34:16 +020012753 uint32_t val;
12754
Daniel Vetterf458ebb2014-09-30 10:56:39 +020012755 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030012756 return false;
12757
Daniel Vetter53589012013-06-05 13:34:16 +020012758 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020012759 hw_state->dpll = val;
12760 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12761 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020012762
12763 return val & DPLL_VCO_ENABLE;
12764}
12765
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020012766static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12767 struct intel_shared_dpll *pll)
12768{
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020012769 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12770 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020012771}
12772
Daniel Vettere7b903d2013-06-05 13:34:14 +020012773static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12774 struct intel_shared_dpll *pll)
12775{
Daniel Vettere7b903d2013-06-05 13:34:14 +020012776 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020012777 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020012778
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020012779 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020012780
12781 /* Wait for the clocks to stabilize. */
12782 POSTING_READ(PCH_DPLL(pll->id));
12783 udelay(150);
12784
12785 /* The pixel multiplier can only be updated once the
12786 * DPLL is enabled and the clocks are stable.
12787 *
12788 * So write it again.
12789 */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020012790 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020012791 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020012792 udelay(200);
12793}
12794
12795static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12796 struct intel_shared_dpll *pll)
12797{
12798 struct drm_device *dev = dev_priv->dev;
12799 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020012800
12801 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012802 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020012803 if (intel_crtc_to_shared_dpll(crtc) == pll)
12804 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12805 }
12806
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020012807 I915_WRITE(PCH_DPLL(pll->id), 0);
12808 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020012809 udelay(200);
12810}
12811
Daniel Vetter46edb022013-06-05 13:34:12 +020012812static char *ibx_pch_dpll_names[] = {
12813 "PCH DPLL A",
12814 "PCH DPLL B",
12815};
12816
Daniel Vetter7c74ade2013-06-05 13:34:11 +020012817static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012818{
Daniel Vettere7b903d2013-06-05 13:34:14 +020012819 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012820 int i;
12821
Daniel Vetter7c74ade2013-06-05 13:34:11 +020012822 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012823
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012824 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020012825 dev_priv->shared_dplls[i].id = i;
12826 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020012827 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020012828 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12829 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020012830 dev_priv->shared_dplls[i].get_hw_state =
12831 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012832 }
12833}
12834
Daniel Vetter7c74ade2013-06-05 13:34:11 +020012835static void intel_shared_dpll_init(struct drm_device *dev)
12836{
Daniel Vettere7b903d2013-06-05 13:34:14 +020012837 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020012838
Daniel Vetter9cd86932014-06-25 22:01:57 +030012839 if (HAS_DDI(dev))
12840 intel_ddi_pll_init(dev);
12841 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020012842 ibx_pch_dpll_init(dev);
12843 else
12844 dev_priv->num_shared_dpll = 0;
12845
12846 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020012847}
12848
Matt Roper6beb8c232014-12-01 15:40:14 -080012849/**
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +000012850 * intel_wm_need_update - Check whether watermarks need updating
12851 * @plane: drm plane
12852 * @state: new plane state
12853 *
12854 * Check current plane state versus the new one to determine whether
12855 * watermarks need to be recalculated.
12856 *
12857 * Returns true or false.
12858 */
12859bool intel_wm_need_update(struct drm_plane *plane,
12860 struct drm_plane_state *state)
12861{
12862 /* Update watermarks on tiling changes. */
12863 if (!plane->state->fb || !state->fb ||
12864 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12865 plane->state->rotation != state->rotation)
12866 return true;
12867
12868 return false;
12869}
12870
12871/**
Matt Roper6beb8c232014-12-01 15:40:14 -080012872 * intel_prepare_plane_fb - Prepare fb for usage on plane
12873 * @plane: drm plane to prepare for
12874 * @fb: framebuffer to prepare for presentation
12875 *
12876 * Prepares a framebuffer for usage on a display plane. Generally this
12877 * involves pinning the underlying object and updating the frontbuffer tracking
12878 * bits. Some older platforms need special physical address handling for
12879 * cursor planes.
12880 *
12881 * Returns 0 on success, negative error code on failure.
12882 */
12883int
12884intel_prepare_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +000012885 struct drm_framebuffer *fb,
12886 const struct drm_plane_state *new_state)
Matt Roper465c1202014-05-29 08:06:54 -070012887{
12888 struct drm_device *dev = plane->dev;
Matt Roper6beb8c232014-12-01 15:40:14 -080012889 struct intel_plane *intel_plane = to_intel_plane(plane);
12890 enum pipe pipe = intel_plane->pipe;
12891 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12892 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12893 unsigned frontbuffer_bits = 0;
12894 int ret = 0;
Matt Roper465c1202014-05-29 08:06:54 -070012895
Matt Roperea2c67b2014-12-23 10:41:52 -080012896 if (!obj)
Matt Roper465c1202014-05-29 08:06:54 -070012897 return 0;
12898
Matt Roper6beb8c232014-12-01 15:40:14 -080012899 switch (plane->type) {
12900 case DRM_PLANE_TYPE_PRIMARY:
12901 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12902 break;
12903 case DRM_PLANE_TYPE_CURSOR:
12904 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12905 break;
12906 case DRM_PLANE_TYPE_OVERLAY:
12907 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12908 break;
12909 }
Matt Roper465c1202014-05-29 08:06:54 -070012910
Matt Roper4c345742014-07-09 16:22:10 -070012911 mutex_lock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070012912
Matt Roper6beb8c232014-12-01 15:40:14 -080012913 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12914 INTEL_INFO(dev)->cursor_needs_physical) {
12915 int align = IS_I830(dev) ? 16 * 1024 : 256;
12916 ret = i915_gem_object_attach_phys(obj, align);
12917 if (ret)
12918 DRM_DEBUG_KMS("failed to attach phys object\n");
12919 } else {
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000012920 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
Matt Roper6beb8c232014-12-01 15:40:14 -080012921 }
12922
12923 if (ret == 0)
12924 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12925
12926 mutex_unlock(&dev->struct_mutex);
12927
12928 return ret;
12929}
12930
Matt Roper38f3ce32014-12-02 07:45:25 -080012931/**
12932 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12933 * @plane: drm plane to clean up for
12934 * @fb: old framebuffer that was on plane
12935 *
12936 * Cleans up a framebuffer that has just been removed from a plane.
12937 */
12938void
12939intel_cleanup_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +000012940 struct drm_framebuffer *fb,
12941 const struct drm_plane_state *old_state)
Matt Roper38f3ce32014-12-02 07:45:25 -080012942{
12943 struct drm_device *dev = plane->dev;
12944 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12945
12946 if (WARN_ON(!obj))
12947 return;
12948
12949 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12950 !INTEL_INFO(dev)->cursor_needs_physical) {
12951 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000012952 intel_unpin_fb_obj(fb, old_state);
Matt Roper38f3ce32014-12-02 07:45:25 -080012953 mutex_unlock(&dev->struct_mutex);
12954 }
Matt Roper465c1202014-05-29 08:06:54 -070012955}
12956
Chandra Konduru6156a452015-04-27 13:48:39 -070012957int
12958skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12959{
12960 int max_scale;
12961 struct drm_device *dev;
12962 struct drm_i915_private *dev_priv;
12963 int crtc_clock, cdclk;
12964
12965 if (!intel_crtc || !crtc_state)
12966 return DRM_PLANE_HELPER_NO_SCALING;
12967
12968 dev = intel_crtc->base.dev;
12969 dev_priv = dev->dev_private;
12970 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12971 cdclk = dev_priv->display.get_display_clock_speed(dev);
12972
12973 if (!crtc_clock || !cdclk)
12974 return DRM_PLANE_HELPER_NO_SCALING;
12975
12976 /*
12977 * skl max scale is lower of:
12978 * close to 3 but not 3, -1 is for that purpose
12979 * or
12980 * cdclk/crtc_clock
12981 */
12982 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
12983
12984 return max_scale;
12985}
12986
Matt Roper465c1202014-05-29 08:06:54 -070012987static int
Gustavo Padovan3c692a42014-09-05 17:04:49 -030012988intel_check_primary_plane(struct drm_plane *plane,
12989 struct intel_plane_state *state)
Matt Roper465c1202014-05-29 08:06:54 -070012990{
Matt Roper32b7eee2014-12-24 07:59:06 -080012991 struct drm_device *dev = plane->dev;
12992 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2b875c22014-12-01 15:40:13 -080012993 struct drm_crtc *crtc = state->base.crtc;
Matt Roperea2c67b2014-12-23 10:41:52 -080012994 struct intel_crtc *intel_crtc;
Chandra Konduru6156a452015-04-27 13:48:39 -070012995 struct intel_crtc_state *crtc_state;
Matt Roper2b875c22014-12-01 15:40:13 -080012996 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan3c692a42014-09-05 17:04:49 -030012997 struct drm_rect *dest = &state->dst;
12998 struct drm_rect *src = &state->src;
12999 const struct drm_rect *clip = &state->clip;
Sonika Jindald8106362015-04-10 14:37:28 +053013000 bool can_position = false;
Chandra Konduru6156a452015-04-27 13:48:39 -070013001 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13002 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013003 int ret;
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013004
Matt Roperea2c67b2014-12-23 10:41:52 -080013005 crtc = crtc ? crtc : plane->crtc;
13006 intel_crtc = to_intel_crtc(crtc);
Chandra Konduru6156a452015-04-27 13:48:39 -070013007 crtc_state = state->base.state ?
13008 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
Matt Roperea2c67b2014-12-23 10:41:52 -080013009
Chandra Konduru6156a452015-04-27 13:48:39 -070013010 if (INTEL_INFO(dev)->gen >= 9) {
13011 min_scale = 1;
13012 max_scale = skl_max_scale(intel_crtc, crtc_state);
Sonika Jindald8106362015-04-10 14:37:28 +053013013 can_position = true;
Chandra Konduru6156a452015-04-27 13:48:39 -070013014 }
Sonika Jindald8106362015-04-10 14:37:28 +053013015
Matt Roperc59cb172014-12-01 15:40:16 -080013016 ret = drm_plane_helper_check_update(plane, crtc, fb,
13017 src, dest, clip,
Chandra Konduru6156a452015-04-27 13:48:39 -070013018 min_scale,
13019 max_scale,
Sonika Jindald8106362015-04-10 14:37:28 +053013020 can_position, true,
13021 &state->visible);
Matt Roperc59cb172014-12-01 15:40:16 -080013022 if (ret)
13023 return ret;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013024
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013025 if (intel_crtc->active) {
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030013026 struct intel_plane_state *old_state =
13027 to_intel_plane_state(plane->state);
13028
Matt Roper32b7eee2014-12-24 07:59:06 -080013029 intel_crtc->atomic.wait_for_flips = true;
13030
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013031 /*
13032 * FBC does not work on some platforms for rotated
13033 * planes, so disable it when rotation is not 0 and
13034 * update it when rotation is set back to 0.
13035 *
13036 * FIXME: This is redundant with the fbc update done in
13037 * the primary plane enable function except that that
13038 * one is done too late. We eventually need to unify
13039 * this.
13040 */
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030013041 if (state->visible &&
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013042 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
Paulo Zanonie35fef22015-02-09 14:46:29 -020013043 dev_priv->fbc.crtc == intel_crtc &&
Matt Roper8e7d6882015-01-21 16:35:41 -080013044 state->base.rotation != BIT(DRM_ROTATE_0)) {
Matt Roper32b7eee2014-12-24 07:59:06 -080013045 intel_crtc->atomic.disable_fbc = true;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013046 }
13047
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030013048 if (state->visible && !old_state->visible) {
Matt Roper32b7eee2014-12-24 07:59:06 -080013049 /*
13050 * BDW signals flip done immediately if the plane
13051 * is disabled, even if the plane enable is already
13052 * armed to occur at the next vblank :(
13053 */
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030013054 if (IS_BROADWELL(dev))
Matt Roper32b7eee2014-12-24 07:59:06 -080013055 intel_crtc->atomic.wait_vblank = true;
13056 }
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013057
Matt Roper32b7eee2014-12-24 07:59:06 -080013058 intel_crtc->atomic.fb_bits |=
13059 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13060
13061 intel_crtc->atomic.update_fbc = true;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +000013062
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +000013063 if (intel_wm_need_update(plane, &state->base))
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +000013064 intel_crtc->atomic.update_wm = true;
Matt Roperc59cb172014-12-01 15:40:16 -080013065 }
13066
Chandra Konduru6156a452015-04-27 13:48:39 -070013067 if (INTEL_INFO(dev)->gen >= 9) {
13068 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13069 to_intel_plane(plane), state, 0);
13070 if (ret)
13071 return ret;
13072 }
13073
Matt Roperc59cb172014-12-01 15:40:16 -080013074 return 0;
Matt Roper465c1202014-05-29 08:06:54 -070013075}
13076
Sonika Jindal48404c12014-08-22 14:06:04 +053013077static void
13078intel_commit_primary_plane(struct drm_plane *plane,
13079 struct intel_plane_state *state)
13080{
Matt Roper2b875c22014-12-01 15:40:13 -080013081 struct drm_crtc *crtc = state->base.crtc;
13082 struct drm_framebuffer *fb = state->base.fb;
13083 struct drm_device *dev = plane->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053013084 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperea2c67b2014-12-23 10:41:52 -080013085 struct intel_crtc *intel_crtc;
Sonika Jindalce54d852014-08-21 11:44:39 +053013086 struct drm_rect *src = &state->src;
Matt Ropercf4c7c12014-12-04 10:27:42 -080013087
Matt Roperea2c67b2014-12-23 10:41:52 -080013088 crtc = crtc ? crtc : plane->crtc;
13089 intel_crtc = to_intel_crtc(crtc);
13090
Matt Ropercf4c7c12014-12-04 10:27:42 -080013091 plane->fb = fb;
Sonika Jindalce54d852014-08-21 11:44:39 +053013092 crtc->x = src->x1 >> 16;
Matt Roper465c1202014-05-29 08:06:54 -070013093 crtc->y = src->y1 >> 16;
13094
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013095 if (intel_crtc->active) {
Maarten Lankhorst27321ae2015-04-21 17:12:52 +030013096 if (state->visible)
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013097 /* FIXME: kill this fastboot hack */
13098 intel_update_pipe_size(intel_crtc);
13099
Maarten Lankhorst27321ae2015-04-21 17:12:52 +030013100 dev_priv->display.update_primary_plane(crtc, plane->fb,
13101 crtc->x, crtc->y);
Matt Roper32b7eee2014-12-24 07:59:06 -080013102 }
13103}
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013104
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013105static void
13106intel_disable_primary_plane(struct drm_plane *plane,
13107 struct drm_crtc *crtc,
13108 bool force)
13109{
13110 struct drm_device *dev = plane->dev;
13111 struct drm_i915_private *dev_priv = dev->dev_private;
13112
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013113 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13114}
13115
Matt Roper32b7eee2014-12-24 07:59:06 -080013116static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13117{
13118 struct drm_device *dev = crtc->dev;
13119 struct drm_i915_private *dev_priv = dev->dev_private;
13120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roperea2c67b2014-12-23 10:41:52 -080013121 struct intel_plane *intel_plane;
13122 struct drm_plane *p;
13123 unsigned fb_bits = 0;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013124
Matt Roperea2c67b2014-12-23 10:41:52 -080013125 /* Track fb's for any planes being disabled */
13126 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13127 intel_plane = to_intel_plane(p);
13128
13129 if (intel_crtc->atomic.disabled_planes &
13130 (1 << drm_plane_index(p))) {
13131 switch (p->type) {
13132 case DRM_PLANE_TYPE_PRIMARY:
13133 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13134 break;
13135 case DRM_PLANE_TYPE_CURSOR:
13136 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13137 break;
13138 case DRM_PLANE_TYPE_OVERLAY:
13139 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13140 break;
13141 }
13142
13143 mutex_lock(&dev->struct_mutex);
13144 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13145 mutex_unlock(&dev->struct_mutex);
13146 }
13147 }
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013148
Matt Roper32b7eee2014-12-24 07:59:06 -080013149 if (intel_crtc->atomic.wait_for_flips)
13150 intel_crtc_wait_for_pending_flips(crtc);
13151
13152 if (intel_crtc->atomic.disable_fbc)
13153 intel_fbc_disable(dev);
13154
13155 if (intel_crtc->atomic.pre_disable_primary)
13156 intel_pre_disable_primary(crtc);
13157
13158 if (intel_crtc->atomic.update_wm)
13159 intel_update_watermarks(crtc);
13160
13161 intel_runtime_pm_get(dev_priv);
Matt Roperc34c9ee2014-12-23 10:41:50 -080013162
13163 /* Perform vblank evasion around commit operation */
13164 if (intel_crtc->active)
13165 intel_crtc->atomic.evade =
13166 intel_pipe_update_start(intel_crtc,
13167 &intel_crtc->atomic.start_vbl_count);
Matt Roper32b7eee2014-12-24 07:59:06 -080013168}
13169
13170static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13171{
13172 struct drm_device *dev = crtc->dev;
13173 struct drm_i915_private *dev_priv = dev->dev_private;
13174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13175 struct drm_plane *p;
13176
Matt Roperc34c9ee2014-12-23 10:41:50 -080013177 if (intel_crtc->atomic.evade)
13178 intel_pipe_update_end(intel_crtc,
13179 intel_crtc->atomic.start_vbl_count);
13180
Matt Roper32b7eee2014-12-24 07:59:06 -080013181 intel_runtime_pm_put(dev_priv);
13182
13183 if (intel_crtc->atomic.wait_vblank)
13184 intel_wait_for_vblank(dev, intel_crtc->pipe);
13185
13186 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13187
13188 if (intel_crtc->atomic.update_fbc) {
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013189 mutex_lock(&dev->struct_mutex);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020013190 intel_fbc_update(dev);
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013191 mutex_unlock(&dev->struct_mutex);
13192 }
Matt Roper465c1202014-05-29 08:06:54 -070013193
Matt Roper32b7eee2014-12-24 07:59:06 -080013194 if (intel_crtc->atomic.post_enable_primary)
13195 intel_post_enable_primary(crtc);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013196
Matt Roper32b7eee2014-12-24 07:59:06 -080013197 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13198 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13199 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13200 false, false);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013201
Matt Roper32b7eee2014-12-24 07:59:06 -080013202 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013203}
13204
Matt Ropercf4c7c12014-12-04 10:27:42 -080013205/**
Matt Roper4a3b8762014-12-23 10:41:51 -080013206 * intel_plane_destroy - destroy a plane
13207 * @plane: plane to destroy
Matt Ropercf4c7c12014-12-04 10:27:42 -080013208 *
Matt Roper4a3b8762014-12-23 10:41:51 -080013209 * Common destruction function for all types of planes (primary, cursor,
13210 * sprite).
Matt Ropercf4c7c12014-12-04 10:27:42 -080013211 */
Matt Roper4a3b8762014-12-23 10:41:51 -080013212void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070013213{
13214 struct intel_plane *intel_plane = to_intel_plane(plane);
13215 drm_plane_cleanup(plane);
13216 kfree(intel_plane);
13217}
13218
Matt Roper65a3fea2015-01-21 16:35:42 -080013219const struct drm_plane_funcs intel_plane_funcs = {
Matt Roper70a101f2015-04-08 18:56:53 -070013220 .update_plane = drm_atomic_helper_update_plane,
13221 .disable_plane = drm_atomic_helper_disable_plane,
Matt Roper3d7d6512014-06-10 08:28:13 -070013222 .destroy = intel_plane_destroy,
Matt Roperc196e1d2015-01-21 16:35:48 -080013223 .set_property = drm_atomic_helper_plane_set_property,
Matt Ropera98b3432015-01-21 16:35:43 -080013224 .atomic_get_property = intel_plane_atomic_get_property,
13225 .atomic_set_property = intel_plane_atomic_set_property,
Matt Roperea2c67b2014-12-23 10:41:52 -080013226 .atomic_duplicate_state = intel_plane_duplicate_state,
13227 .atomic_destroy_state = intel_plane_destroy_state,
13228
Matt Roper465c1202014-05-29 08:06:54 -070013229};
13230
13231static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13232 int pipe)
13233{
13234 struct intel_plane *primary;
Matt Roper8e7d6882015-01-21 16:35:41 -080013235 struct intel_plane_state *state;
Matt Roper465c1202014-05-29 08:06:54 -070013236 const uint32_t *intel_primary_formats;
13237 int num_formats;
13238
13239 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13240 if (primary == NULL)
13241 return NULL;
13242
Matt Roper8e7d6882015-01-21 16:35:41 -080013243 state = intel_create_plane_state(&primary->base);
13244 if (!state) {
Matt Roperea2c67b2014-12-23 10:41:52 -080013245 kfree(primary);
13246 return NULL;
13247 }
Matt Roper8e7d6882015-01-21 16:35:41 -080013248 primary->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -080013249
Matt Roper465c1202014-05-29 08:06:54 -070013250 primary->can_scale = false;
13251 primary->max_downscale = 1;
Chandra Konduru6156a452015-04-27 13:48:39 -070013252 if (INTEL_INFO(dev)->gen >= 9) {
13253 primary->can_scale = true;
13254 }
Chandra Konduru549e2bf2015-04-07 15:28:38 -070013255 state->scaler_id = -1;
Matt Roper465c1202014-05-29 08:06:54 -070013256 primary->pipe = pipe;
13257 primary->plane = pipe;
Matt Roperc59cb172014-12-01 15:40:16 -080013258 primary->check_plane = intel_check_primary_plane;
13259 primary->commit_plane = intel_commit_primary_plane;
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013260 primary->disable_plane = intel_disable_primary_plane;
Chandra Konduru08e221f2015-04-07 15:28:37 -070013261 primary->ckey.flags = I915_SET_COLORKEY_NONE;
Matt Roper465c1202014-05-29 08:06:54 -070013262 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13263 primary->plane = !pipe;
13264
13265 if (INTEL_INFO(dev)->gen <= 3) {
13266 intel_primary_formats = intel_primary_formats_gen2;
13267 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13268 } else {
13269 intel_primary_formats = intel_primary_formats_gen4;
13270 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13271 }
13272
13273 drm_universal_plane_init(dev, &primary->base, 0,
Matt Roper65a3fea2015-01-21 16:35:42 -080013274 &intel_plane_funcs,
Matt Roper465c1202014-05-29 08:06:54 -070013275 intel_primary_formats, num_formats,
13276 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053013277
Sonika Jindal3b7a5112015-04-10 14:37:29 +053013278 if (INTEL_INFO(dev)->gen >= 4)
13279 intel_create_rotation_property(dev, primary);
Sonika Jindal48404c12014-08-22 14:06:04 +053013280
Matt Roperea2c67b2014-12-23 10:41:52 -080013281 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13282
Matt Roper465c1202014-05-29 08:06:54 -070013283 return &primary->base;
13284}
13285
Sonika Jindal3b7a5112015-04-10 14:37:29 +053013286void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13287{
13288 if (!dev->mode_config.rotation_property) {
13289 unsigned long flags = BIT(DRM_ROTATE_0) |
13290 BIT(DRM_ROTATE_180);
13291
13292 if (INTEL_INFO(dev)->gen >= 9)
13293 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13294
13295 dev->mode_config.rotation_property =
13296 drm_mode_create_rotation_property(dev, flags);
13297 }
13298 if (dev->mode_config.rotation_property)
13299 drm_object_attach_property(&plane->base.base,
13300 dev->mode_config.rotation_property,
13301 plane->base.state->rotation);
13302}
13303
Matt Roper3d7d6512014-06-10 08:28:13 -070013304static int
Gustavo Padovan852e7872014-09-05 17:22:31 -030013305intel_check_cursor_plane(struct drm_plane *plane,
13306 struct intel_plane_state *state)
Matt Roper3d7d6512014-06-10 08:28:13 -070013307{
Matt Roper2b875c22014-12-01 15:40:13 -080013308 struct drm_crtc *crtc = state->base.crtc;
Matt Roperea2c67b2014-12-23 10:41:52 -080013309 struct drm_device *dev = plane->dev;
Matt Roper2b875c22014-12-01 15:40:13 -080013310 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan852e7872014-09-05 17:22:31 -030013311 struct drm_rect *dest = &state->dst;
13312 struct drm_rect *src = &state->src;
13313 const struct drm_rect *clip = &state->clip;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013314 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Matt Roperea2c67b2014-12-23 10:41:52 -080013315 struct intel_crtc *intel_crtc;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013316 unsigned stride;
13317 int ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030013318
Matt Roperea2c67b2014-12-23 10:41:52 -080013319 crtc = crtc ? crtc : plane->crtc;
13320 intel_crtc = to_intel_crtc(crtc);
13321
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013322 ret = drm_plane_helper_check_update(plane, crtc, fb,
Gustavo Padovan852e7872014-09-05 17:22:31 -030013323 src, dest, clip,
13324 DRM_PLANE_HELPER_NO_SCALING,
13325 DRM_PLANE_HELPER_NO_SCALING,
13326 true, true, &state->visible);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013327 if (ret)
13328 return ret;
13329
13330
13331 /* if we want to turn off the cursor ignore width and height */
13332 if (!obj)
Matt Roper32b7eee2014-12-24 07:59:06 -080013333 goto finish;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013334
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013335 /* Check for which cursor types we support */
Matt Roperea2c67b2014-12-23 10:41:52 -080013336 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13337 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13338 state->base.crtc_w, state->base.crtc_h);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013339 return -EINVAL;
13340 }
13341
Matt Roperea2c67b2014-12-23 10:41:52 -080013342 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13343 if (obj->base.size < stride * state->base.crtc_h) {
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013344 DRM_DEBUG_KMS("buffer is too small\n");
13345 return -ENOMEM;
13346 }
13347
Ville Syrjälä3a656b52015-03-09 21:08:37 +020013348 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013349 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13350 ret = -EINVAL;
13351 }
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013352
Matt Roper32b7eee2014-12-24 07:59:06 -080013353finish:
13354 if (intel_crtc->active) {
Ville Syrjälä3749f462015-03-10 13:15:22 +020013355 if (plane->state->crtc_w != state->base.crtc_w)
Matt Roper32b7eee2014-12-24 07:59:06 -080013356 intel_crtc->atomic.update_wm = true;
13357
13358 intel_crtc->atomic.fb_bits |=
13359 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13360 }
13361
Gustavo Padovan757f9a32014-09-24 14:20:24 -030013362 return ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030013363}
13364
Matt Roperf4a2cf22014-12-01 15:40:12 -080013365static void
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013366intel_disable_cursor_plane(struct drm_plane *plane,
13367 struct drm_crtc *crtc,
13368 bool force)
13369{
13370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13371
13372 if (!force) {
13373 plane->fb = NULL;
13374 intel_crtc->cursor_bo = NULL;
13375 intel_crtc->cursor_addr = 0;
13376 }
13377
13378 intel_crtc_update_cursor(crtc, false);
13379}
13380
13381static void
Gustavo Padovan852e7872014-09-05 17:22:31 -030013382intel_commit_cursor_plane(struct drm_plane *plane,
13383 struct intel_plane_state *state)
13384{
Matt Roper2b875c22014-12-01 15:40:13 -080013385 struct drm_crtc *crtc = state->base.crtc;
Matt Roperea2c67b2014-12-23 10:41:52 -080013386 struct drm_device *dev = plane->dev;
13387 struct intel_crtc *intel_crtc;
Matt Roper2b875c22014-12-01 15:40:13 -080013388 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
Gustavo Padovana912f122014-12-01 15:40:10 -080013389 uint32_t addr;
Matt Roper3d7d6512014-06-10 08:28:13 -070013390
Matt Roperea2c67b2014-12-23 10:41:52 -080013391 crtc = crtc ? crtc : plane->crtc;
13392 intel_crtc = to_intel_crtc(crtc);
Sonika Jindala919db92014-10-23 07:41:33 -070013393
Matt Roperea2c67b2014-12-23 10:41:52 -080013394 plane->fb = state->base.fb;
13395 crtc->cursor_x = state->base.crtc_x;
13396 crtc->cursor_y = state->base.crtc_y;
13397
Gustavo Padovana912f122014-12-01 15:40:10 -080013398 if (intel_crtc->cursor_bo == obj)
13399 goto update;
13400
Matt Roperf4a2cf22014-12-01 15:40:12 -080013401 if (!obj)
Gustavo Padovana912f122014-12-01 15:40:10 -080013402 addr = 0;
Matt Roperf4a2cf22014-12-01 15:40:12 -080013403 else if (!INTEL_INFO(dev)->cursor_needs_physical)
Gustavo Padovana912f122014-12-01 15:40:10 -080013404 addr = i915_gem_obj_ggtt_offset(obj);
Matt Roperf4a2cf22014-12-01 15:40:12 -080013405 else
Gustavo Padovana912f122014-12-01 15:40:10 -080013406 addr = obj->phys_handle->busaddr;
Gustavo Padovana912f122014-12-01 15:40:10 -080013407
Gustavo Padovana912f122014-12-01 15:40:10 -080013408 intel_crtc->cursor_addr = addr;
13409 intel_crtc->cursor_bo = obj;
13410update:
Gustavo Padovana912f122014-12-01 15:40:10 -080013411
Matt Roper32b7eee2014-12-24 07:59:06 -080013412 if (intel_crtc->active)
Gustavo Padovan852e7872014-09-05 17:22:31 -030013413 intel_crtc_update_cursor(crtc, state->visible);
Matt Roper3d7d6512014-06-10 08:28:13 -070013414}
Gustavo Padovan852e7872014-09-05 17:22:31 -030013415
Matt Roper3d7d6512014-06-10 08:28:13 -070013416static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13417 int pipe)
13418{
13419 struct intel_plane *cursor;
Matt Roper8e7d6882015-01-21 16:35:41 -080013420 struct intel_plane_state *state;
Matt Roper3d7d6512014-06-10 08:28:13 -070013421
13422 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13423 if (cursor == NULL)
13424 return NULL;
13425
Matt Roper8e7d6882015-01-21 16:35:41 -080013426 state = intel_create_plane_state(&cursor->base);
13427 if (!state) {
Matt Roperea2c67b2014-12-23 10:41:52 -080013428 kfree(cursor);
13429 return NULL;
13430 }
Matt Roper8e7d6882015-01-21 16:35:41 -080013431 cursor->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -080013432
Matt Roper3d7d6512014-06-10 08:28:13 -070013433 cursor->can_scale = false;
13434 cursor->max_downscale = 1;
13435 cursor->pipe = pipe;
13436 cursor->plane = pipe;
Chandra Konduru549e2bf2015-04-07 15:28:38 -070013437 state->scaler_id = -1;
Matt Roperc59cb172014-12-01 15:40:16 -080013438 cursor->check_plane = intel_check_cursor_plane;
13439 cursor->commit_plane = intel_commit_cursor_plane;
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013440 cursor->disable_plane = intel_disable_cursor_plane;
Matt Roper3d7d6512014-06-10 08:28:13 -070013441
13442 drm_universal_plane_init(dev, &cursor->base, 0,
Matt Roper65a3fea2015-01-21 16:35:42 -080013443 &intel_plane_funcs,
Matt Roper3d7d6512014-06-10 08:28:13 -070013444 intel_cursor_formats,
13445 ARRAY_SIZE(intel_cursor_formats),
13446 DRM_PLANE_TYPE_CURSOR);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070013447
13448 if (INTEL_INFO(dev)->gen >= 4) {
13449 if (!dev->mode_config.rotation_property)
13450 dev->mode_config.rotation_property =
13451 drm_mode_create_rotation_property(dev,
13452 BIT(DRM_ROTATE_0) |
13453 BIT(DRM_ROTATE_180));
13454 if (dev->mode_config.rotation_property)
13455 drm_object_attach_property(&cursor->base.base,
13456 dev->mode_config.rotation_property,
Matt Roper8e7d6882015-01-21 16:35:41 -080013457 state->base.rotation);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070013458 }
13459
Matt Roperea2c67b2014-12-23 10:41:52 -080013460 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13461
Matt Roper3d7d6512014-06-10 08:28:13 -070013462 return &cursor->base;
13463}
13464
Chandra Konduru549e2bf2015-04-07 15:28:38 -070013465static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13466 struct intel_crtc_state *crtc_state)
13467{
13468 int i;
13469 struct intel_scaler *intel_scaler;
13470 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13471
13472 for (i = 0; i < intel_crtc->num_scalers; i++) {
13473 intel_scaler = &scaler_state->scalers[i];
13474 intel_scaler->in_use = 0;
13475 intel_scaler->id = i;
13476
13477 intel_scaler->mode = PS_SCALER_MODE_DYN;
13478 }
13479
13480 scaler_state->scaler_id = -1;
13481}
13482
Hannes Ederb358d0a2008-12-18 21:18:47 +010013483static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080013484{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013485 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080013486 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020013487 struct intel_crtc_state *crtc_state = NULL;
Matt Roper3d7d6512014-06-10 08:28:13 -070013488 struct drm_plane *primary = NULL;
13489 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070013490 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080013491
Daniel Vetter955382f2013-09-19 14:05:45 +020013492 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080013493 if (intel_crtc == NULL)
13494 return;
13495
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020013496 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13497 if (!crtc_state)
13498 goto fail;
Ander Conselvan de Oliveira550acef2015-04-21 17:13:24 +030013499 intel_crtc->config = crtc_state;
13500 intel_crtc->base.state = &crtc_state->base;
Matt Roper07878242015-02-25 11:43:26 -080013501 crtc_state->base.crtc = &intel_crtc->base;
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020013502
Chandra Konduru549e2bf2015-04-07 15:28:38 -070013503 /* initialize shared scalers */
13504 if (INTEL_INFO(dev)->gen >= 9) {
13505 if (pipe == PIPE_C)
13506 intel_crtc->num_scalers = 1;
13507 else
13508 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13509
13510 skl_init_scalers(dev, intel_crtc, crtc_state);
13511 }
13512
Matt Roper465c1202014-05-29 08:06:54 -070013513 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070013514 if (!primary)
13515 goto fail;
13516
13517 cursor = intel_cursor_plane_create(dev, pipe);
13518 if (!cursor)
13519 goto fail;
13520
Matt Roper465c1202014-05-29 08:06:54 -070013521 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070013522 cursor, &intel_crtc_funcs);
13523 if (ret)
13524 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080013525
13526 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080013527 for (i = 0; i < 256; i++) {
13528 intel_crtc->lut_r[i] = i;
13529 intel_crtc->lut_g[i] = i;
13530 intel_crtc->lut_b[i] = i;
13531 }
13532
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020013533 /*
13534 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020013535 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020013536 */
Jesse Barnes80824002009-09-10 15:28:06 -070013537 intel_crtc->pipe = pipe;
13538 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010013539 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080013540 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010013541 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070013542 }
13543
Chris Wilson4b0e3332014-05-30 16:35:26 +030013544 intel_crtc->cursor_base = ~0;
13545 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030013546 intel_crtc->cursor_size = ~0;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030013547
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080013548 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13549 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13550 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13551 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13552
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020013553 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13554
Jesse Barnes79e53942008-11-07 14:24:08 -080013555 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020013556
13557 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070013558 return;
13559
13560fail:
13561 if (primary)
13562 drm_plane_cleanup(primary);
13563 if (cursor)
13564 drm_plane_cleanup(cursor);
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020013565 kfree(crtc_state);
Matt Roper3d7d6512014-06-10 08:28:13 -070013566 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080013567}
13568
Jesse Barnes752aa882013-10-31 18:55:49 +020013569enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13570{
13571 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020013572 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020013573
Rob Clark51fd3712013-11-19 12:10:12 -050013574 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020013575
Ville Syrjäläd3babd32014-11-07 11:16:01 +020013576 if (!encoder || WARN_ON(!encoder->crtc))
Jesse Barnes752aa882013-10-31 18:55:49 +020013577 return INVALID_PIPE;
13578
13579 return to_intel_crtc(encoder->crtc)->pipe;
13580}
13581
Carl Worth08d7b3d2009-04-29 14:43:54 -070013582int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000013583 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070013584{
Carl Worth08d7b3d2009-04-29 14:43:54 -070013585 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040013586 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020013587 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070013588
Rob Clark7707e652014-07-17 23:30:04 -040013589 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070013590
Rob Clark7707e652014-07-17 23:30:04 -040013591 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070013592 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030013593 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070013594 }
13595
Rob Clark7707e652014-07-17 23:30:04 -040013596 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020013597 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070013598
Daniel Vetterc05422d2009-08-11 16:05:30 +020013599 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070013600}
13601
Daniel Vetter66a92782012-07-12 20:08:18 +020013602static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080013603{
Daniel Vetter66a92782012-07-12 20:08:18 +020013604 struct drm_device *dev = encoder->base.dev;
13605 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080013606 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080013607 int entry = 0;
13608
Damien Lespiaub2784e12014-08-05 11:29:37 +010013609 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020013610 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020013611 index_mask |= (1 << entry);
13612
Jesse Barnes79e53942008-11-07 14:24:08 -080013613 entry++;
13614 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010013615
Jesse Barnes79e53942008-11-07 14:24:08 -080013616 return index_mask;
13617}
13618
Chris Wilson4d302442010-12-14 19:21:29 +000013619static bool has_edp_a(struct drm_device *dev)
13620{
13621 struct drm_i915_private *dev_priv = dev->dev_private;
13622
13623 if (!IS_MOBILE(dev))
13624 return false;
13625
13626 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13627 return false;
13628
Damien Lespiaue3589902014-02-07 19:12:50 +000013629 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000013630 return false;
13631
13632 return true;
13633}
13634
Jesse Barnes84b4e042014-06-25 08:24:29 -070013635static bool intel_crt_present(struct drm_device *dev)
13636{
13637 struct drm_i915_private *dev_priv = dev->dev_private;
13638
Damien Lespiau884497e2013-12-03 13:56:23 +000013639 if (INTEL_INFO(dev)->gen >= 9)
13640 return false;
13641
Damien Lespiaucf404ce2014-10-01 20:04:15 +010013642 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Jesse Barnes84b4e042014-06-25 08:24:29 -070013643 return false;
13644
13645 if (IS_CHERRYVIEW(dev))
13646 return false;
13647
13648 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13649 return false;
13650
13651 return true;
13652}
13653
Jesse Barnes79e53942008-11-07 14:24:08 -080013654static void intel_setup_outputs(struct drm_device *dev)
13655{
Eric Anholt725e30a2009-01-22 13:01:02 -080013656 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010013657 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040013658 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080013659
Daniel Vetterc9093352013-06-06 22:22:47 +020013660 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080013661
Jesse Barnes84b4e042014-06-25 08:24:29 -070013662 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020013663 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040013664
Vandana Kannanc776eb22014-08-19 12:05:01 +053013665 if (IS_BROXTON(dev)) {
13666 /*
13667 * FIXME: Broxton doesn't support port detection via the
13668 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13669 * detect the ports.
13670 */
13671 intel_ddi_init(dev, PORT_A);
13672 intel_ddi_init(dev, PORT_B);
13673 intel_ddi_init(dev, PORT_C);
13674 } else if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030013675 int found;
13676
Jesse Barnesde31fac2015-03-06 15:53:32 -080013677 /*
13678 * Haswell uses DDI functions to detect digital outputs.
13679 * On SKL pre-D0 the strap isn't connected, so we assume
13680 * it's there.
13681 */
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030013682 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
Jesse Barnesde31fac2015-03-06 15:53:32 -080013683 /* WaIgnoreDDIAStrap: skl */
13684 if (found ||
13685 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030013686 intel_ddi_init(dev, PORT_A);
13687
13688 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13689 * register */
13690 found = I915_READ(SFUSE_STRAP);
13691
13692 if (found & SFUSE_STRAP_DDIB_DETECTED)
13693 intel_ddi_init(dev, PORT_B);
13694 if (found & SFUSE_STRAP_DDIC_DETECTED)
13695 intel_ddi_init(dev, PORT_C);
13696 if (found & SFUSE_STRAP_DDID_DETECTED)
13697 intel_ddi_init(dev, PORT_D);
13698 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040013699 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020013700 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020013701
13702 if (has_edp_a(dev))
13703 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040013704
Paulo Zanonidc0fa712013-02-19 16:21:46 -030013705 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080013706 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010013707 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080013708 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030013709 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080013710 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030013711 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080013712 }
13713
Paulo Zanonidc0fa712013-02-19 16:21:46 -030013714 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030013715 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080013716
Paulo Zanonidc0fa712013-02-19 16:21:46 -030013717 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030013718 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080013719
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080013720 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030013721 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080013722
Daniel Vetter270b3042012-10-27 15:52:05 +020013723 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030013724 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070013725 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030013726 /*
13727 * The DP_DETECTED bit is the latched state of the DDC
13728 * SDA pin at boot. However since eDP doesn't require DDC
13729 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13730 * eDP ports may have been muxed to an alternate function.
13731 * Thus we can't rely on the DP_DETECTED bit alone to detect
13732 * eDP ports. Consult the VBT as well as DP_DETECTED to
13733 * detect eDP ports.
13734 */
Ville Syrjäläd2182a62015-01-09 14:21:14 +020013735 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13736 !intel_dp_is_edp(dev, PORT_B))
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030013737 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13738 PORT_B);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030013739 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13740 intel_dp_is_edp(dev, PORT_B))
13741 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030013742
Ville Syrjäläd2182a62015-01-09 14:21:14 +020013743 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13744 !intel_dp_is_edp(dev, PORT_C))
Jesse Barnes6f6005a2013-08-09 09:34:35 -070013745 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13746 PORT_C);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030013747 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13748 intel_dp_is_edp(dev, PORT_C))
13749 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +053013750
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030013751 if (IS_CHERRYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030013752 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030013753 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13754 PORT_D);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030013755 /* eDP not supported on port D, so don't check VBT */
13756 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13757 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030013758 }
13759
Jani Nikula3cfca972013-08-27 15:12:26 +030013760 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080013761 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080013762 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080013763
Paulo Zanonie2debe92013-02-18 19:00:27 -030013764 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013765 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030013766 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013767 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13768 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030013769 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013770 }
Ma Ling27185ae2009-08-24 13:50:23 +080013771
Imre Deake7281ea2013-05-08 13:14:08 +030013772 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030013773 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080013774 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040013775
13776 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040013777
Paulo Zanonie2debe92013-02-18 19:00:27 -030013778 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013779 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030013780 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013781 }
Ma Ling27185ae2009-08-24 13:50:23 +080013782
Paulo Zanonie2debe92013-02-18 19:00:27 -030013783 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080013784
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013785 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13786 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030013787 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013788 }
Imre Deake7281ea2013-05-08 13:14:08 +030013789 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030013790 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080013791 }
Ma Ling27185ae2009-08-24 13:50:23 +080013792
Jesse Barnesb01f2c32009-12-11 11:07:17 -080013793 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030013794 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030013795 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070013796 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080013797 intel_dvo_init(dev);
13798
Zhenyu Wang103a1962009-11-27 11:44:36 +080013799 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080013800 intel_tv_init(dev);
13801
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -080013802 intel_psr_init(dev);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070013803
Damien Lespiaub2784e12014-08-05 11:29:37 +010013804 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010013805 encoder->base.possible_crtcs = encoder->crtc_mask;
13806 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020013807 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080013808 }
Chris Wilson47356eb2011-01-11 17:06:04 +000013809
Paulo Zanonidde86e22012-12-01 12:04:25 -020013810 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020013811
13812 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080013813}
13814
13815static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13816{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030013817 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080013818 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080013819
Daniel Vetteref2d6332014-02-10 18:00:38 +010013820 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030013821 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010013822 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030013823 drm_gem_object_unreference(&intel_fb->obj->base);
13824 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013825 kfree(intel_fb);
13826}
13827
13828static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000013829 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080013830 unsigned int *handle)
13831{
13832 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000013833 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080013834
Chris Wilson05394f32010-11-08 19:18:58 +000013835 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080013836}
13837
13838static const struct drm_framebuffer_funcs intel_fb_funcs = {
13839 .destroy = intel_user_framebuffer_destroy,
13840 .create_handle = intel_user_framebuffer_create_handle,
13841};
13842
Damien Lespiaub3218032015-02-27 11:15:18 +000013843static
13844u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13845 uint32_t pixel_format)
13846{
13847 u32 gen = INTEL_INFO(dev)->gen;
13848
13849 if (gen >= 9) {
13850 /* "The stride in bytes must not exceed the of the size of 8K
13851 * pixels and 32K bytes."
13852 */
13853 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13854 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13855 return 32*1024;
13856 } else if (gen >= 4) {
13857 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13858 return 16*1024;
13859 else
13860 return 32*1024;
13861 } else if (gen >= 3) {
13862 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13863 return 8*1024;
13864 else
13865 return 16*1024;
13866 } else {
13867 /* XXX DSPC is limited to 4k tiled */
13868 return 8*1024;
13869 }
13870}
13871
Daniel Vetterb5ea6422014-03-02 21:18:00 +010013872static int intel_framebuffer_init(struct drm_device *dev,
13873 struct intel_framebuffer *intel_fb,
13874 struct drm_mode_fb_cmd2 *mode_cmd,
13875 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080013876{
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +000013877 unsigned int aligned_height;
Jesse Barnes79e53942008-11-07 14:24:08 -080013878 int ret;
Damien Lespiaub3218032015-02-27 11:15:18 +000013879 u32 pitch_limit, stride_alignment;
Jesse Barnes79e53942008-11-07 14:24:08 -080013880
Daniel Vetterdd4916c2013-10-09 21:23:51 +020013881 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13882
Daniel Vetter2a80ead2015-02-10 17:16:06 +000013883 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13884 /* Enforce that fb modifier and tiling mode match, but only for
13885 * X-tiled. This is needed for FBC. */
13886 if (!!(obj->tiling_mode == I915_TILING_X) !=
13887 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13888 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13889 return -EINVAL;
13890 }
13891 } else {
13892 if (obj->tiling_mode == I915_TILING_X)
13893 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13894 else if (obj->tiling_mode == I915_TILING_Y) {
13895 DRM_DEBUG("No Y tiling for legacy addfb\n");
13896 return -EINVAL;
13897 }
13898 }
13899
Tvrtko Ursulin9a8f0a12015-02-27 11:15:24 +000013900 /* Passed in modifier sanity checking. */
13901 switch (mode_cmd->modifier[0]) {
13902 case I915_FORMAT_MOD_Y_TILED:
13903 case I915_FORMAT_MOD_Yf_TILED:
13904 if (INTEL_INFO(dev)->gen < 9) {
13905 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13906 mode_cmd->modifier[0]);
13907 return -EINVAL;
13908 }
13909 case DRM_FORMAT_MOD_NONE:
13910 case I915_FORMAT_MOD_X_TILED:
13911 break;
13912 default:
Jesse Barnesc0f40422015-03-23 12:43:50 -070013913 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13914 mode_cmd->modifier[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010013915 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013916 }
Chris Wilson57cd6502010-08-08 12:34:44 +010013917
Damien Lespiaub3218032015-02-27 11:15:18 +000013918 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13919 mode_cmd->pixel_format);
13920 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13921 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13922 mode_cmd->pitches[0], stride_alignment);
Chris Wilson57cd6502010-08-08 12:34:44 +010013923 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013924 }
Chris Wilson57cd6502010-08-08 12:34:44 +010013925
Damien Lespiaub3218032015-02-27 11:15:18 +000013926 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13927 mode_cmd->pixel_format);
Chris Wilsona35cdaa2013-06-25 17:26:45 +010013928 if (mode_cmd->pitches[0] > pitch_limit) {
Damien Lespiaub3218032015-02-27 11:15:18 +000013929 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13930 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
Daniel Vetter2a80ead2015-02-10 17:16:06 +000013931 "tiled" : "linear",
Chris Wilsona35cdaa2013-06-25 17:26:45 +010013932 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020013933 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013934 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020013935
Daniel Vetter2a80ead2015-02-10 17:16:06 +000013936 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013937 mode_cmd->pitches[0] != obj->stride) {
13938 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13939 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020013940 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013941 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020013942
Ville Syrjälä57779d02012-10-31 17:50:14 +020013943 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080013944 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020013945 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020013946 case DRM_FORMAT_RGB565:
13947 case DRM_FORMAT_XRGB8888:
13948 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020013949 break;
13950 case DRM_FORMAT_XRGB1555:
13951 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013952 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000013953 DRM_DEBUG("unsupported pixel format: %s\n",
13954 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020013955 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013956 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020013957 break;
13958 case DRM_FORMAT_XBGR8888:
13959 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020013960 case DRM_FORMAT_XRGB2101010:
13961 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020013962 case DRM_FORMAT_XBGR2101010:
13963 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013964 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000013965 DRM_DEBUG("unsupported pixel format: %s\n",
13966 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020013967 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013968 }
Jesse Barnesb5626742011-06-24 12:19:27 -070013969 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020013970 case DRM_FORMAT_YUYV:
13971 case DRM_FORMAT_UYVY:
13972 case DRM_FORMAT_YVYU:
13973 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013974 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000013975 DRM_DEBUG("unsupported pixel format: %s\n",
13976 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020013977 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000013978 }
Chris Wilson57cd6502010-08-08 12:34:44 +010013979 break;
13980 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000013981 DRM_DEBUG("unsupported pixel format: %s\n",
13982 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010013983 return -EINVAL;
13984 }
13985
Ville Syrjälä90f9a332012-10-31 17:50:19 +020013986 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13987 if (mode_cmd->offsets[0] != 0)
13988 return -EINVAL;
13989
Damien Lespiauec2c9812015-01-20 12:51:45 +000013990 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +000013991 mode_cmd->pixel_format,
13992 mode_cmd->modifier[0]);
Daniel Vetter53155c02013-10-09 21:55:33 +020013993 /* FIXME drm helper for size checks (especially planar formats)? */
13994 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13995 return -EINVAL;
13996
Daniel Vetterc7d73f62012-12-13 23:38:38 +010013997 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13998 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020013999 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010014000
Jesse Barnes79e53942008-11-07 14:24:08 -080014001 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14002 if (ret) {
14003 DRM_ERROR("framebuffer init failed %d\n", ret);
14004 return ret;
14005 }
14006
Jesse Barnes79e53942008-11-07 14:24:08 -080014007 return 0;
14008}
14009
Jesse Barnes79e53942008-11-07 14:24:08 -080014010static struct drm_framebuffer *
14011intel_user_framebuffer_create(struct drm_device *dev,
14012 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080014013 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080014014{
Chris Wilson05394f32010-11-08 19:18:58 +000014015 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080014016
Jesse Barnes308e5bc2011-11-14 14:51:28 -080014017 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14018 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000014019 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010014020 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080014021
Chris Wilsond2dff872011-04-19 08:36:26 +010014022 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080014023}
14024
Daniel Vetter4520f532013-10-09 09:18:51 +020014025#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020014026static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020014027{
14028}
14029#endif
14030
Jesse Barnes79e53942008-11-07 14:24:08 -080014031static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080014032 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020014033 .output_poll_changed = intel_fbdev_output_poll_changed,
Matt Roper5ee67f12015-01-21 16:35:44 -080014034 .atomic_check = intel_atomic_check,
14035 .atomic_commit = intel_atomic_commit,
Jesse Barnes79e53942008-11-07 14:24:08 -080014036};
14037
Jesse Barnese70236a2009-09-21 10:42:27 -070014038/* Set up chip specific display functions */
14039static void intel_init_display(struct drm_device *dev)
14040{
14041 struct drm_i915_private *dev_priv = dev->dev_private;
14042
Daniel Vetteree9300b2013-06-03 22:40:22 +020014043 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14044 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030014045 else if (IS_CHERRYVIEW(dev))
14046 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020014047 else if (IS_VALLEYVIEW(dev))
14048 dev_priv->display.find_dpll = vlv_find_best_dpll;
14049 else if (IS_PINEVIEW(dev))
14050 dev_priv->display.find_dpll = pnv_find_best_dpll;
14051 else
14052 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14053
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014054 if (INTEL_INFO(dev)->gen >= 9) {
14055 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014056 dev_priv->display.get_initial_plane_config =
14057 skylake_get_initial_plane_config;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014058 dev_priv->display.crtc_compute_clock =
14059 haswell_crtc_compute_clock;
14060 dev_priv->display.crtc_enable = haswell_crtc_enable;
14061 dev_priv->display.crtc_disable = haswell_crtc_disable;
14062 dev_priv->display.off = ironlake_crtc_off;
14063 dev_priv->display.update_primary_plane =
14064 skylake_update_primary_plane;
14065 } else if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014066 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014067 dev_priv->display.get_initial_plane_config =
14068 ironlake_get_initial_plane_config;
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +020014069 dev_priv->display.crtc_compute_clock =
14070 haswell_crtc_compute_clock;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020014071 dev_priv->display.crtc_enable = haswell_crtc_enable;
14072 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030014073 dev_priv->display.off = ironlake_crtc_off;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014074 dev_priv->display.update_primary_plane =
14075 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030014076 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014077 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014078 dev_priv->display.get_initial_plane_config =
14079 ironlake_get_initial_plane_config;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +020014080 dev_priv->display.crtc_compute_clock =
14081 ironlake_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020014082 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14083 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010014084 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070014085 dev_priv->display.update_primary_plane =
14086 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070014087 } else if (IS_VALLEYVIEW(dev)) {
14088 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014089 dev_priv->display.get_initial_plane_config =
14090 i9xx_get_initial_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020014091 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Jesse Barnes89b667f2013-04-18 14:51:36 -070014092 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14093 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14094 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070014095 dev_priv->display.update_primary_plane =
14096 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070014097 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014098 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014099 dev_priv->display.get_initial_plane_config =
14100 i9xx_get_initial_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020014101 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020014102 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14103 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010014104 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070014105 dev_priv->display.update_primary_plane =
14106 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070014107 }
Jesse Barnese70236a2009-09-21 10:42:27 -070014108
Jesse Barnese70236a2009-09-21 10:42:27 -070014109 /* Returns the core display clock speed */
Ville Syrjälä1652d192015-03-31 14:12:01 +030014110 if (IS_SKYLAKE(dev))
14111 dev_priv->display.get_display_clock_speed =
14112 skylake_get_display_clock_speed;
14113 else if (IS_BROADWELL(dev))
14114 dev_priv->display.get_display_clock_speed =
14115 broadwell_get_display_clock_speed;
14116 else if (IS_HASWELL(dev))
14117 dev_priv->display.get_display_clock_speed =
14118 haswell_get_display_clock_speed;
14119 else if (IS_VALLEYVIEW(dev))
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070014120 dev_priv->display.get_display_clock_speed =
14121 valleyview_get_display_clock_speed;
Ville Syrjäläb37a6432015-03-31 14:11:54 +030014122 else if (IS_GEN5(dev))
14123 dev_priv->display.get_display_clock_speed =
14124 ilk_get_display_clock_speed;
Ville Syrjäläa7c66cd2015-03-31 14:11:56 +030014125 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14126 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070014127 dev_priv->display.get_display_clock_speed =
14128 i945_get_display_clock_speed;
14129 else if (IS_I915G(dev))
14130 dev_priv->display.get_display_clock_speed =
14131 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020014132 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070014133 dev_priv->display.get_display_clock_speed =
14134 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020014135 else if (IS_PINEVIEW(dev))
14136 dev_priv->display.get_display_clock_speed =
14137 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070014138 else if (IS_I915GM(dev))
14139 dev_priv->display.get_display_clock_speed =
14140 i915gm_get_display_clock_speed;
14141 else if (IS_I865G(dev))
14142 dev_priv->display.get_display_clock_speed =
14143 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020014144 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070014145 dev_priv->display.get_display_clock_speed =
14146 i855_get_display_clock_speed;
14147 else /* 852, 830 */
14148 dev_priv->display.get_display_clock_speed =
14149 i830_get_display_clock_speed;
14150
Jani Nikula7c10a2b2014-10-27 16:26:43 +020014151 if (IS_GEN5(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014152 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014153 } else if (IS_GEN6(dev)) {
14154 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014155 } else if (IS_IVYBRIDGE(dev)) {
14156 /* FIXME: detect B0+ stepping and use auto training */
14157 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Paulo Zanoni059b2fe2014-09-02 16:53:57 -030014158 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014159 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Jesse Barnes30a970c2013-11-04 13:48:12 -080014160 } else if (IS_VALLEYVIEW(dev)) {
14161 dev_priv->display.modeset_global_resources =
14162 valleyview_modeset_global_resources;
Vandana Kannanf8437dd12014-11-24 13:37:39 +053014163 } else if (IS_BROXTON(dev)) {
14164 dev_priv->display.modeset_global_resources =
14165 broxton_modeset_global_resources;
Jesse Barnese70236a2009-09-21 10:42:27 -070014166 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070014167
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070014168 switch (INTEL_INFO(dev)->gen) {
14169 case 2:
14170 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14171 break;
14172
14173 case 3:
14174 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14175 break;
14176
14177 case 4:
14178 case 5:
14179 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14180 break;
14181
14182 case 6:
14183 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14184 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070014185 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070014186 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070014187 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14188 break;
Damien Lespiau830c81d2014-11-13 17:51:46 +000014189 case 9:
Tvrtko Ursulinba343e02015-02-10 17:16:12 +000014190 /* Drop through - unsupported since execlist only. */
14191 default:
14192 /* Default just returns -ENODEV to indicate unsupported */
14193 dev_priv->display.queue_flip = intel_default_queue_flip;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070014194 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020014195
14196 intel_panel_init_backlight_funcs(dev);
Ville Syrjäläe39b9992014-09-04 14:53:14 +030014197
14198 mutex_init(&dev_priv->pps_mutex);
Jesse Barnese70236a2009-09-21 10:42:27 -070014199}
14200
Jesse Barnesb690e962010-07-19 13:53:12 -070014201/*
14202 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14203 * resume, or other times. This quirk makes sure that's the case for
14204 * affected systems.
14205 */
Akshay Joshi0206e352011-08-16 15:34:10 -040014206static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070014207{
14208 struct drm_i915_private *dev_priv = dev->dev_private;
14209
14210 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020014211 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070014212}
14213
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030014214static void quirk_pipeb_force(struct drm_device *dev)
14215{
14216 struct drm_i915_private *dev_priv = dev->dev_private;
14217
14218 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14219 DRM_INFO("applying pipe b force quirk\n");
14220}
14221
Keith Packard435793d2011-07-12 14:56:22 -070014222/*
14223 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14224 */
14225static void quirk_ssc_force_disable(struct drm_device *dev)
14226{
14227 struct drm_i915_private *dev_priv = dev->dev_private;
14228 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020014229 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070014230}
14231
Carsten Emde4dca20e2012-03-15 15:56:26 +010014232/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010014233 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14234 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010014235 */
14236static void quirk_invert_brightness(struct drm_device *dev)
14237{
14238 struct drm_i915_private *dev_priv = dev->dev_private;
14239 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020014240 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070014241}
14242
Scot Doyle9c72cc62014-07-03 23:27:50 +000014243/* Some VBT's incorrectly indicate no backlight is present */
14244static void quirk_backlight_present(struct drm_device *dev)
14245{
14246 struct drm_i915_private *dev_priv = dev->dev_private;
14247 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14248 DRM_INFO("applying backlight present quirk\n");
14249}
14250
Jesse Barnesb690e962010-07-19 13:53:12 -070014251struct intel_quirk {
14252 int device;
14253 int subsystem_vendor;
14254 int subsystem_device;
14255 void (*hook)(struct drm_device *dev);
14256};
14257
Egbert Eich5f85f172012-10-14 15:46:38 +020014258/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14259struct intel_dmi_quirk {
14260 void (*hook)(struct drm_device *dev);
14261 const struct dmi_system_id (*dmi_id_list)[];
14262};
14263
14264static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14265{
14266 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14267 return 1;
14268}
14269
14270static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14271 {
14272 .dmi_id_list = &(const struct dmi_system_id[]) {
14273 {
14274 .callback = intel_dmi_reverse_brightness,
14275 .ident = "NCR Corporation",
14276 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14277 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14278 },
14279 },
14280 { } /* terminating entry */
14281 },
14282 .hook = quirk_invert_brightness,
14283 },
14284};
14285
Ben Widawskyc43b5632012-04-16 14:07:40 -070014286static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070014287 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040014288 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070014289
Jesse Barnesb690e962010-07-19 13:53:12 -070014290 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14291 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14292
Jesse Barnesb690e962010-07-19 13:53:12 -070014293 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14294 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14295
Ville Syrjälä5f080c02014-08-15 01:22:06 +030014296 /* 830 needs to leave pipe A & dpll A up */
14297 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14298
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030014299 /* 830 needs to leave pipe B & dpll B up */
14300 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14301
Keith Packard435793d2011-07-12 14:56:22 -070014302 /* Lenovo U160 cannot use SSC on LVDS */
14303 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020014304
14305 /* Sony Vaio Y cannot use SSC on LVDS */
14306 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010014307
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010014308 /* Acer Aspire 5734Z must invert backlight brightness */
14309 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14310
14311 /* Acer/eMachines G725 */
14312 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14313
14314 /* Acer/eMachines e725 */
14315 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14316
14317 /* Acer/Packard Bell NCL20 */
14318 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14319
14320 /* Acer Aspire 4736Z */
14321 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020014322
14323 /* Acer Aspire 5336 */
14324 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000014325
14326 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14327 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000014328
Scot Doyledfb3d47b2014-08-21 16:08:02 +000014329 /* Acer C720 Chromebook (Core i3 4005U) */
14330 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14331
jens steinb2a96012014-10-28 20:25:53 +010014332 /* Apple Macbook 2,1 (Core 2 T7400) */
14333 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14334
Scot Doyled4967d82014-07-03 23:27:52 +000014335 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14336 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000014337
14338 /* HP Chromebook 14 (Celeron 2955U) */
14339 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jani Nikulacf6f0af2015-02-19 10:53:39 +020014340
14341 /* Dell Chromebook 11 */
14342 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070014343};
14344
14345static void intel_init_quirks(struct drm_device *dev)
14346{
14347 struct pci_dev *d = dev->pdev;
14348 int i;
14349
14350 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14351 struct intel_quirk *q = &intel_quirks[i];
14352
14353 if (d->device == q->device &&
14354 (d->subsystem_vendor == q->subsystem_vendor ||
14355 q->subsystem_vendor == PCI_ANY_ID) &&
14356 (d->subsystem_device == q->subsystem_device ||
14357 q->subsystem_device == PCI_ANY_ID))
14358 q->hook(dev);
14359 }
Egbert Eich5f85f172012-10-14 15:46:38 +020014360 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14361 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14362 intel_dmi_quirks[i].hook(dev);
14363 }
Jesse Barnesb690e962010-07-19 13:53:12 -070014364}
14365
Jesse Barnes9cce37f2010-08-13 15:11:26 -070014366/* Disable the VGA plane that we never use */
14367static void i915_disable_vga(struct drm_device *dev)
14368{
14369 struct drm_i915_private *dev_priv = dev->dev_private;
14370 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020014371 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070014372
Ville Syrjälä2b37c612014-01-22 21:32:38 +020014373 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070014374 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070014375 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070014376 sr1 = inb(VGA_SR_DATA);
14377 outb(sr1 | 1<<5, VGA_SR_DATA);
14378 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14379 udelay(300);
14380
Ville Syrjälä01f5a622014-12-16 18:38:37 +020014381 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070014382 POSTING_READ(vga_reg);
14383}
14384
Daniel Vetterf8175862012-04-10 15:50:11 +020014385void intel_modeset_init_hw(struct drm_device *dev)
14386{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030014387 intel_prepare_ddi(dev);
14388
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030014389 if (IS_VALLEYVIEW(dev))
14390 vlv_update_cdclk(dev);
14391
Daniel Vetterf8175862012-04-10 15:50:11 +020014392 intel_init_clock_gating(dev);
14393
Daniel Vetter8090c6b2012-06-24 16:42:32 +020014394 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020014395}
14396
Jesse Barnes79e53942008-11-07 14:24:08 -080014397void intel_modeset_init(struct drm_device *dev)
14398{
Jesse Barnes652c3932009-08-17 13:31:43 -070014399 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000014400 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000014401 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080014402 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080014403
14404 drm_mode_config_init(dev);
14405
14406 dev->mode_config.min_width = 0;
14407 dev->mode_config.min_height = 0;
14408
Dave Airlie019d96c2011-09-29 16:20:42 +010014409 dev->mode_config.preferred_depth = 24;
14410 dev->mode_config.prefer_shadow = 1;
14411
Tvrtko Ursulin25bab382015-02-10 17:16:16 +000014412 dev->mode_config.allow_fb_modifiers = true;
14413
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020014414 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080014415
Jesse Barnesb690e962010-07-19 13:53:12 -070014416 intel_init_quirks(dev);
14417
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030014418 intel_init_pm(dev);
14419
Ben Widawskye3c74752013-04-05 13:12:39 -070014420 if (INTEL_INFO(dev)->num_pipes == 0)
14421 return;
14422
Jesse Barnese70236a2009-09-21 10:42:27 -070014423 intel_init_display(dev);
Jani Nikula7c10a2b2014-10-27 16:26:43 +020014424 intel_init_audio(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070014425
Chris Wilsona6c45cf2010-09-17 00:32:17 +010014426 if (IS_GEN2(dev)) {
14427 dev->mode_config.max_width = 2048;
14428 dev->mode_config.max_height = 2048;
14429 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070014430 dev->mode_config.max_width = 4096;
14431 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080014432 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010014433 dev->mode_config.max_width = 8192;
14434 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080014435 }
Damien Lespiau068be562014-03-28 14:17:49 +000014436
Ville Syrjälädc41c152014-08-13 11:57:05 +030014437 if (IS_845G(dev) || IS_I865G(dev)) {
14438 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14439 dev->mode_config.cursor_height = 1023;
14440 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000014441 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14442 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14443 } else {
14444 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14445 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14446 }
14447
Ben Widawsky5d4545a2013-01-17 12:45:15 -080014448 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080014449
Zhao Yakui28c97732009-10-09 11:39:41 +080014450 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070014451 INTEL_INFO(dev)->num_pipes,
14452 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080014453
Damien Lespiau055e3932014-08-18 13:49:10 +010014454 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000014455 intel_crtc_init(dev, pipe);
Damien Lespiau3bdcfc02015-02-28 14:54:09 +000014456 for_each_sprite(dev_priv, pipe, sprite) {
Damien Lespiau1fe47782014-03-03 17:31:47 +000014457 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070014458 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030014459 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000014460 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070014461 }
Jesse Barnes79e53942008-11-07 14:24:08 -080014462 }
14463
Jesse Barnesf42bb702013-12-16 16:34:23 -080014464 intel_init_dpio(dev);
14465
Daniel Vettere72f9fb2013-06-05 13:34:06 +020014466 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010014467
Jesse Barnes9cce37f2010-08-13 15:11:26 -070014468 /* Just disable it once at startup */
14469 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080014470 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000014471
14472 /* Just in case the BIOS is doing something questionable. */
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020014473 intel_fbc_disable(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080014474
Daniel Vetter6e9f7982014-05-29 23:54:47 +020014475 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080014476 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020014477 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080014478
Damien Lespiaud3fcc802014-05-13 23:32:22 +010014479 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080014480 if (!crtc->active)
14481 continue;
14482
Jesse Barnes46f297f2014-03-07 08:57:48 -080014483 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080014484 * Note that reserving the BIOS fb up front prevents us
14485 * from stuffing other stolen allocations like the ring
14486 * on top. This prevents some ugliness at boot time, and
14487 * can even allow for smooth boot transitions if the BIOS
14488 * fb is large enough for the active pipe configuration.
14489 */
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014490 if (dev_priv->display.get_initial_plane_config) {
14491 dev_priv->display.get_initial_plane_config(crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -080014492 &crtc->plane_config);
14493 /*
14494 * If the fb is shared between multiple heads, we'll
14495 * just get the first one.
14496 */
Daniel Vetterf6936e22015-03-26 12:17:05 +010014497 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080014498 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080014499 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010014500}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080014501
Daniel Vetter7fad7982012-07-04 17:51:47 +020014502static void intel_enable_pipe_a(struct drm_device *dev)
14503{
14504 struct intel_connector *connector;
14505 struct drm_connector *crt = NULL;
14506 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030014507 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020014508
14509 /* We can't just switch on the pipe A, we need to set things up with a
14510 * proper mode and output configuration. As a gross hack, enable pipe A
14511 * by enabling the load detect pipe once. */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020014512 for_each_intel_connector(dev, connector) {
Daniel Vetter7fad7982012-07-04 17:51:47 +020014513 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14514 crt = &connector->base;
14515 break;
14516 }
14517 }
14518
14519 if (!crt)
14520 return;
14521
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030014522 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +020014523 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
Daniel Vetter7fad7982012-07-04 17:51:47 +020014524}
14525
Daniel Vetterfa555832012-10-10 23:14:00 +020014526static bool
14527intel_check_plane_mapping(struct intel_crtc *crtc)
14528{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070014529 struct drm_device *dev = crtc->base.dev;
14530 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020014531 u32 reg, val;
14532
Ben Widawsky7eb552a2013-03-13 14:05:41 -070014533 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020014534 return true;
14535
14536 reg = DSPCNTR(!crtc->plane);
14537 val = I915_READ(reg);
14538
14539 if ((val & DISPLAY_PLANE_ENABLE) &&
14540 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14541 return false;
14542
14543 return true;
14544}
14545
Daniel Vetter24929352012-07-02 20:28:59 +020014546static void intel_sanitize_crtc(struct intel_crtc *crtc)
14547{
14548 struct drm_device *dev = crtc->base.dev;
14549 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020014550 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020014551
Daniel Vetter24929352012-07-02 20:28:59 +020014552 /* Clear any frame start delays used for debugging left by the BIOS */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014553 reg = PIPECONF(crtc->config->cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020014554 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14555
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030014556 /* restore vblank interrupts to correct state */
Daniel Vetter96256042015-02-13 21:03:42 +010014557 drm_crtc_vblank_reset(&crtc->base);
Ville Syrjäläd297e102014-08-06 14:50:01 +030014558 if (crtc->active) {
14559 update_scanline_offset(crtc);
Daniel Vetter96256042015-02-13 21:03:42 +010014560 drm_crtc_vblank_on(&crtc->base);
14561 }
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030014562
Daniel Vetter24929352012-07-02 20:28:59 +020014563 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020014564 * disable the crtc (and hence change the state) if it is wrong. Note
14565 * that gen4+ has a fixed plane -> pipe mapping. */
14566 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020014567 struct intel_connector *connector;
14568 bool plane;
14569
Daniel Vetter24929352012-07-02 20:28:59 +020014570 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14571 crtc->base.base.id);
14572
14573 /* Pipe has the wrong plane attached and the plane is active.
14574 * Temporarily change the plane mapping and disable everything
14575 * ... */
14576 plane = crtc->plane;
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030014577 to_intel_plane_state(crtc->base.primary->state)->visible = true;
Daniel Vetter24929352012-07-02 20:28:59 +020014578 crtc->plane = !plane;
Maarten Lankhorstce22dba2015-04-21 17:12:56 +030014579 intel_crtc_disable_planes(&crtc->base);
Daniel Vetter24929352012-07-02 20:28:59 +020014580 dev_priv->display.crtc_disable(&crtc->base);
14581 crtc->plane = plane;
14582
14583 /* ... and break all links. */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020014584 for_each_intel_connector(dev, connector) {
Daniel Vetter24929352012-07-02 20:28:59 +020014585 if (connector->encoder->base.crtc != &crtc->base)
14586 continue;
14587
Egbert Eich7f1950f2014-04-25 10:56:22 +020014588 connector->base.dpms = DRM_MODE_DPMS_OFF;
14589 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020014590 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020014591 /* multiple connectors may have the same encoder:
14592 * handle them and break crtc link separately */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020014593 for_each_intel_connector(dev, connector)
Egbert Eich7f1950f2014-04-25 10:56:22 +020014594 if (connector->encoder->base.crtc == &crtc->base) {
14595 connector->encoder->base.crtc = NULL;
14596 connector->encoder->connectors_active = false;
14597 }
Daniel Vetter24929352012-07-02 20:28:59 +020014598
14599 WARN_ON(crtc->active);
Matt Roper83d65732015-02-25 13:12:16 -080014600 crtc->base.state->enable = false;
Daniel Vetter24929352012-07-02 20:28:59 +020014601 crtc->base.enabled = false;
14602 }
Daniel Vetter24929352012-07-02 20:28:59 +020014603
Daniel Vetter7fad7982012-07-04 17:51:47 +020014604 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14605 crtc->pipe == PIPE_A && !crtc->active) {
14606 /* BIOS forgot to enable pipe A, this mostly happens after
14607 * resume. Force-enable the pipe to fix this, the update_dpms
14608 * call below we restore the pipe to the right state, but leave
14609 * the required bits on. */
14610 intel_enable_pipe_a(dev);
14611 }
14612
Daniel Vetter24929352012-07-02 20:28:59 +020014613 /* Adjust the state of the output pipe according to whether we
14614 * have active connectors/encoders. */
14615 intel_crtc_update_dpms(&crtc->base);
14616
Matt Roper83d65732015-02-25 13:12:16 -080014617 if (crtc->active != crtc->base.state->enable) {
Daniel Vetter24929352012-07-02 20:28:59 +020014618 struct intel_encoder *encoder;
14619
14620 /* This can happen either due to bugs in the get_hw_state
14621 * functions or because the pipe is force-enabled due to the
14622 * pipe A quirk. */
14623 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14624 crtc->base.base.id,
Matt Roper83d65732015-02-25 13:12:16 -080014625 crtc->base.state->enable ? "enabled" : "disabled",
Daniel Vetter24929352012-07-02 20:28:59 +020014626 crtc->active ? "enabled" : "disabled");
14627
Matt Roper83d65732015-02-25 13:12:16 -080014628 crtc->base.state->enable = crtc->active;
Daniel Vetter24929352012-07-02 20:28:59 +020014629 crtc->base.enabled = crtc->active;
14630
14631 /* Because we only establish the connector -> encoder ->
14632 * crtc links if something is active, this means the
14633 * crtc is now deactivated. Break the links. connector
14634 * -> encoder links are only establish when things are
14635 * actually up, hence no need to break them. */
14636 WARN_ON(crtc->active);
14637
14638 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14639 WARN_ON(encoder->connectors_active);
14640 encoder->base.crtc = NULL;
14641 }
14642 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020014643
Ville Syrjäläa3ed6aa2014-09-03 14:09:52 +030014644 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010014645 /*
14646 * We start out with underrun reporting disabled to avoid races.
14647 * For correct bookkeeping mark this on active crtcs.
14648 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020014649 * Also on gmch platforms we dont have any hardware bits to
14650 * disable the underrun reporting. Which means we need to start
14651 * out with underrun reporting disabled also on inactive pipes,
14652 * since otherwise we'll complain about the garbage we read when
14653 * e.g. coming up after runtime pm.
14654 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010014655 * No protection against concurrent access is required - at
14656 * worst a fifo underrun happens which also sets this to false.
14657 */
14658 crtc->cpu_fifo_underrun_disabled = true;
14659 crtc->pch_fifo_underrun_disabled = true;
14660 }
Daniel Vetter24929352012-07-02 20:28:59 +020014661}
14662
14663static void intel_sanitize_encoder(struct intel_encoder *encoder)
14664{
14665 struct intel_connector *connector;
14666 struct drm_device *dev = encoder->base.dev;
14667
14668 /* We need to check both for a crtc link (meaning that the
14669 * encoder is active and trying to read from a pipe) and the
14670 * pipe itself being active. */
14671 bool has_active_crtc = encoder->base.crtc &&
14672 to_intel_crtc(encoder->base.crtc)->active;
14673
14674 if (encoder->connectors_active && !has_active_crtc) {
14675 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14676 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030014677 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020014678
14679 /* Connector is active, but has no active pipe. This is
14680 * fallout from our resume register restoring. Disable
14681 * the encoder manually again. */
14682 if (encoder->base.crtc) {
14683 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14684 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030014685 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020014686 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030014687 if (encoder->post_disable)
14688 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020014689 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020014690 encoder->base.crtc = NULL;
14691 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020014692
14693 /* Inconsistent output/port/pipe state happens presumably due to
14694 * a bug in one of the get_hw_state functions. Or someplace else
14695 * in our code, like the register restore mess on resume. Clamp
14696 * things to off as a safer default. */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020014697 for_each_intel_connector(dev, connector) {
Daniel Vetter24929352012-07-02 20:28:59 +020014698 if (connector->encoder != encoder)
14699 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020014700 connector->base.dpms = DRM_MODE_DPMS_OFF;
14701 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020014702 }
14703 }
14704 /* Enabled encoders without active connectors will be fixed in
14705 * the crtc fixup. */
14706}
14707
Imre Deak04098752014-02-18 00:02:16 +020014708void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010014709{
14710 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020014711 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010014712
Imre Deak04098752014-02-18 00:02:16 +020014713 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14714 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14715 i915_disable_vga(dev);
14716 }
14717}
14718
14719void i915_redisable_vga(struct drm_device *dev)
14720{
14721 struct drm_i915_private *dev_priv = dev->dev_private;
14722
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030014723 /* This function can be called both from intel_modeset_setup_hw_state or
14724 * at a very early point in our resume sequence, where the power well
14725 * structures are not yet restored. Since this function is at a very
14726 * paranoid "someone might have enabled VGA while we were not looking"
14727 * level, just check if the power well is enabled instead of trying to
14728 * follow the "don't touch the power well if we don't need it" policy
14729 * the rest of the driver uses. */
Daniel Vetterf458ebb2014-09-30 10:56:39 +020014730 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030014731 return;
14732
Imre Deak04098752014-02-18 00:02:16 +020014733 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010014734}
14735
Ville Syrjälä98ec7732014-04-30 17:43:01 +030014736static bool primary_get_hw_state(struct intel_crtc *crtc)
14737{
14738 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14739
14740 if (!crtc->active)
14741 return false;
14742
14743 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14744}
14745
Daniel Vetter30e984d2013-06-05 13:34:17 +020014746static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020014747{
14748 struct drm_i915_private *dev_priv = dev->dev_private;
14749 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020014750 struct intel_crtc *crtc;
14751 struct intel_encoder *encoder;
14752 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020014753 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020014754
Damien Lespiaud3fcc802014-05-13 23:32:22 +010014755 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030014756 struct drm_plane *primary = crtc->base.primary;
14757 struct intel_plane_state *plane_state;
14758
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014759 memset(crtc->config, 0, sizeof(*crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020014760
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014761 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
Daniel Vetter99535992014-04-13 12:00:33 +020014762
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014763 crtc->active = dev_priv->display.get_pipe_config(crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014764 crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020014765
Matt Roper83d65732015-02-25 13:12:16 -080014766 crtc->base.state->enable = crtc->active;
Daniel Vetter24929352012-07-02 20:28:59 +020014767 crtc->base.enabled = crtc->active;
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030014768
14769 plane_state = to_intel_plane_state(primary->state);
14770 plane_state->visible = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020014771
14772 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14773 crtc->base.base.id,
14774 crtc->active ? "enabled" : "disabled");
14775 }
14776
Daniel Vetter53589012013-06-05 13:34:16 +020014777 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14778 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14779
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020014780 pll->on = pll->get_hw_state(dev_priv, pll,
14781 &pll->config.hw_state);
Daniel Vetter53589012013-06-05 13:34:16 +020014782 pll->active = 0;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020014783 pll->config.crtc_mask = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010014784 for_each_intel_crtc(dev, crtc) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020014785 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
Daniel Vetter53589012013-06-05 13:34:16 +020014786 pll->active++;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020014787 pll->config.crtc_mask |= 1 << crtc->pipe;
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020014788 }
Daniel Vetter53589012013-06-05 13:34:16 +020014789 }
Daniel Vetter53589012013-06-05 13:34:16 +020014790
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020014791 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020014792 pll->name, pll->config.crtc_mask, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030014793
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020014794 if (pll->config.crtc_mask)
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030014795 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020014796 }
14797
Damien Lespiaub2784e12014-08-05 11:29:37 +010014798 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020014799 pipe = 0;
14800
14801 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070014802 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14803 encoder->base.crtc = &crtc->base;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014804 encoder->get_config(encoder, crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020014805 } else {
14806 encoder->base.crtc = NULL;
14807 }
14808
14809 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010014810 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020014811 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030014812 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020014813 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010014814 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020014815 }
14816
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020014817 for_each_intel_connector(dev, connector) {
Daniel Vetter24929352012-07-02 20:28:59 +020014818 if (connector->get_hw_state(connector)) {
14819 connector->base.dpms = DRM_MODE_DPMS_ON;
14820 connector->encoder->connectors_active = true;
14821 connector->base.encoder = &connector->encoder->base;
14822 } else {
14823 connector->base.dpms = DRM_MODE_DPMS_OFF;
14824 connector->base.encoder = NULL;
14825 }
14826 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14827 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030014828 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020014829 connector->base.encoder ? "enabled" : "disabled");
14830 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020014831}
14832
14833/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14834 * and i915 state tracking structures. */
14835void intel_modeset_setup_hw_state(struct drm_device *dev,
14836 bool force_restore)
14837{
14838 struct drm_i915_private *dev_priv = dev->dev_private;
14839 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020014840 struct intel_crtc *crtc;
14841 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020014842 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020014843
14844 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020014845
Jesse Barnesbabea612013-06-26 18:57:38 +030014846 /*
14847 * Now that we have the config, copy it to each CRTC struct
14848 * Note that this could go away if we move to using crtc_config
14849 * checking everywhere.
14850 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010014851 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020014852 if (crtc->active && i915.fastboot) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014853 intel_mode_from_pipe_config(&crtc->base.mode,
14854 crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030014855 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14856 crtc->base.base.id);
14857 drm_mode_debug_printmodeline(&crtc->base.mode);
14858 }
14859 }
14860
Daniel Vetter24929352012-07-02 20:28:59 +020014861 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010014862 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020014863 intel_sanitize_encoder(encoder);
14864 }
14865
Damien Lespiau055e3932014-08-18 13:49:10 +010014866 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020014867 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14868 intel_sanitize_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020014869 intel_dump_pipe_config(crtc, crtc->config,
14870 "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020014871 }
Daniel Vetter9a935852012-07-05 22:34:27 +020014872
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020014873 intel_modeset_update_connector_atomic_state(dev);
14874
Daniel Vetter35c95372013-07-17 06:55:04 +020014875 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14876 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14877
14878 if (!pll->on || pll->active)
14879 continue;
14880
14881 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14882
14883 pll->disable(dev_priv, pll);
14884 pll->on = false;
14885 }
14886
Pradeep Bhat30789992014-11-04 17:06:45 +000014887 if (IS_GEN9(dev))
14888 skl_wm_get_hw_state(dev);
14889 else if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030014890 ilk_wm_get_hw_state(dev);
14891
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010014892 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030014893 i915_redisable_vga(dev);
14894
Daniel Vetterf30da182013-04-11 20:22:50 +020014895 /*
14896 * We need to use raw interfaces for restoring state to avoid
14897 * checking (bogus) intermediate states.
14898 */
Damien Lespiau055e3932014-08-18 13:49:10 +010014899 for_each_pipe(dev_priv, pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070014900 struct drm_crtc *crtc =
14901 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020014902
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020014903 intel_crtc_restore_mode(crtc);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010014904 }
14905 } else {
14906 intel_modeset_update_staged_output_state(dev);
14907 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020014908
14909 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010014910}
14911
14912void intel_modeset_gem_init(struct drm_device *dev)
14913{
Jesse Barnes92122782014-10-09 12:57:42 -070014914 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -080014915 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070014916 struct drm_i915_gem_object *obj;
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010014917 int ret;
Jesse Barnes484b41d2014-03-07 08:57:55 -080014918
Imre Deakae484342014-03-31 15:10:44 +030014919 mutex_lock(&dev->struct_mutex);
14920 intel_init_gt_powersave(dev);
14921 mutex_unlock(&dev->struct_mutex);
14922
Jesse Barnes92122782014-10-09 12:57:42 -070014923 /*
14924 * There may be no VBT; and if the BIOS enabled SSC we can
14925 * just keep using it to avoid unnecessary flicker. Whereas if the
14926 * BIOS isn't using it, don't assume it will work even if the VBT
14927 * indicates as much.
14928 */
14929 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14930 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14931 DREF_SSC1_ENABLE);
14932
Chris Wilson1833b132012-05-09 11:56:28 +010014933 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020014934
14935 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080014936
14937 /*
14938 * Make sure any fbs we allocated at startup are properly
14939 * pinned & fenced. When we do the allocation it's too early
14940 * for this.
14941 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010014942 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070014943 obj = intel_fb_obj(c->primary->fb);
14944 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080014945 continue;
14946
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010014947 mutex_lock(&dev->struct_mutex);
14948 ret = intel_pin_and_fence_fb_obj(c->primary,
14949 c->primary->fb,
14950 c->primary->state,
14951 NULL);
14952 mutex_unlock(&dev->struct_mutex);
14953 if (ret) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080014954 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14955 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100014956 drm_framebuffer_unreference(c->primary->fb);
14957 c->primary->fb = NULL;
Matt Roperafd65eb2015-02-03 13:10:04 -080014958 update_state_fb(c->primary);
Jesse Barnes484b41d2014-03-07 08:57:55 -080014959 }
14960 }
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020014961
14962 intel_backlight_register(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080014963}
14964
Imre Deak4932e2c2014-02-11 17:12:48 +020014965void intel_connector_unregister(struct intel_connector *intel_connector)
14966{
14967 struct drm_connector *connector = &intel_connector->base;
14968
14969 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010014970 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020014971}
14972
Jesse Barnes79e53942008-11-07 14:24:08 -080014973void intel_modeset_cleanup(struct drm_device *dev)
14974{
Jesse Barnes652c3932009-08-17 13:31:43 -070014975 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030014976 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070014977
Imre Deak2eb52522014-11-19 15:30:05 +020014978 intel_disable_gt_powersave(dev);
14979
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020014980 intel_backlight_unregister(dev);
14981
Daniel Vetterfd0c0642013-04-24 11:13:35 +020014982 /*
14983 * Interrupts and polling as the first thing to avoid creating havoc.
Imre Deak2eb52522014-11-19 15:30:05 +020014984 * Too much stuff here (turning of connectors, ...) would
Daniel Vetterfd0c0642013-04-24 11:13:35 +020014985 * experience fancy races otherwise.
14986 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +020014987 intel_irq_uninstall(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070014988
Daniel Vetterfd0c0642013-04-24 11:13:35 +020014989 /*
14990 * Due to the hpd irq storm handling the hotplug work can re-arm the
14991 * poll handlers. Hence disable polling after hpd handling is shut down.
14992 */
Keith Packardf87ea762010-10-03 19:36:26 -070014993 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020014994
Jesse Barnes652c3932009-08-17 13:31:43 -070014995 mutex_lock(&dev->struct_mutex);
14996
Jesse Barnes723bfd72010-10-07 16:01:13 -070014997 intel_unregister_dsm_handler();
14998
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020014999 intel_fbc_disable(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070015000
Kristian Høgsberg69341a52009-11-11 12:19:17 -050015001 mutex_unlock(&dev->struct_mutex);
15002
Chris Wilson1630fe72011-07-08 12:22:42 +010015003 /* flush any delayed tasks or pending work */
15004 flush_scheduled_work();
15005
Jani Nikuladb31af1d2013-11-08 16:48:53 +020015006 /* destroy the backlight and sysfs files before encoders/connectors */
15007 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020015008 struct intel_connector *intel_connector;
15009
15010 intel_connector = to_intel_connector(connector);
15011 intel_connector->unregister(intel_connector);
Jani Nikuladb31af1d2013-11-08 16:48:53 +020015012 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030015013
Jesse Barnes79e53942008-11-07 14:24:08 -080015014 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010015015
15016 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030015017
15018 mutex_lock(&dev->struct_mutex);
15019 intel_cleanup_gt_powersave(dev);
15020 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080015021}
15022
Dave Airlie28d52042009-09-21 14:33:58 +100015023/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080015024 * Return which encoder is currently attached for connector.
15025 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010015026struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080015027{
Chris Wilsondf0e9242010-09-09 16:20:55 +010015028 return &intel_attached_encoder(connector)->base;
15029}
Jesse Barnes79e53942008-11-07 14:24:08 -080015030
Chris Wilsondf0e9242010-09-09 16:20:55 +010015031void intel_connector_attach_encoder(struct intel_connector *connector,
15032 struct intel_encoder *encoder)
15033{
15034 connector->encoder = encoder;
15035 drm_mode_connector_attach_encoder(&connector->base,
15036 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080015037}
Dave Airlie28d52042009-09-21 14:33:58 +100015038
15039/*
15040 * set vga decode state - true == enable VGA decode
15041 */
15042int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15043{
15044 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000015045 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100015046 u16 gmch_ctrl;
15047
Chris Wilson75fa0412014-02-07 18:37:02 -020015048 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15049 DRM_ERROR("failed to read control word\n");
15050 return -EIO;
15051 }
15052
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020015053 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15054 return 0;
15055
Dave Airlie28d52042009-09-21 14:33:58 +100015056 if (state)
15057 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15058 else
15059 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020015060
15061 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15062 DRM_ERROR("failed to write control word\n");
15063 return -EIO;
15064 }
15065
Dave Airlie28d52042009-09-21 14:33:58 +100015066 return 0;
15067}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015068
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015069struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030015070
15071 u32 power_well_driver;
15072
Chris Wilson63b66e52013-08-08 15:12:06 +020015073 int num_transcoders;
15074
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015075 struct intel_cursor_error_state {
15076 u32 control;
15077 u32 position;
15078 u32 base;
15079 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010015080 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015081
15082 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020015083 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015084 u32 source;
Imre Deakf301b1e12014-04-18 15:55:04 +030015085 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010015086 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015087
15088 struct intel_plane_error_state {
15089 u32 control;
15090 u32 stride;
15091 u32 size;
15092 u32 pos;
15093 u32 addr;
15094 u32 surface;
15095 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010015096 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020015097
15098 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020015099 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020015100 enum transcoder cpu_transcoder;
15101
15102 u32 conf;
15103
15104 u32 htotal;
15105 u32 hblank;
15106 u32 hsync;
15107 u32 vtotal;
15108 u32 vblank;
15109 u32 vsync;
15110 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015111};
15112
15113struct intel_display_error_state *
15114intel_display_capture_error_state(struct drm_device *dev)
15115{
Jani Nikulafbee40d2014-03-31 14:27:18 +030015116 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015117 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020015118 int transcoders[] = {
15119 TRANSCODER_A,
15120 TRANSCODER_B,
15121 TRANSCODER_C,
15122 TRANSCODER_EDP,
15123 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015124 int i;
15125
Chris Wilson63b66e52013-08-08 15:12:06 +020015126 if (INTEL_INFO(dev)->num_pipes == 0)
15127 return NULL;
15128
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020015129 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015130 if (error == NULL)
15131 return NULL;
15132
Imre Deak190be112013-11-25 17:15:31 +020015133 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030015134 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15135
Damien Lespiau055e3932014-08-18 13:49:10 +010015136 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020015137 error->pipe[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020015138 __intel_display_power_is_enabled(dev_priv,
15139 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020015140 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020015141 continue;
15142
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030015143 error->cursor[i].control = I915_READ(CURCNTR(i));
15144 error->cursor[i].position = I915_READ(CURPOS(i));
15145 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015146
15147 error->plane[i].control = I915_READ(DSPCNTR(i));
15148 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030015149 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030015150 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030015151 error->plane[i].pos = I915_READ(DSPPOS(i));
15152 }
Paulo Zanonica291362013-03-06 20:03:14 -030015153 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15154 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015155 if (INTEL_INFO(dev)->gen >= 4) {
15156 error->plane[i].surface = I915_READ(DSPSURF(i));
15157 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15158 }
15159
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015160 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e12014-04-18 15:55:04 +030015161
Sonika Jindal3abfce72014-07-21 15:23:43 +053015162 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e12014-04-18 15:55:04 +030015163 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020015164 }
15165
15166 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15167 if (HAS_DDI(dev_priv->dev))
15168 error->num_transcoders++; /* Account for eDP. */
15169
15170 for (i = 0; i < error->num_transcoders; i++) {
15171 enum transcoder cpu_transcoder = transcoders[i];
15172
Imre Deakddf9c532013-11-27 22:02:02 +020015173 error->transcoder[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020015174 __intel_display_power_is_enabled(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020015175 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020015176 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020015177 continue;
15178
Chris Wilson63b66e52013-08-08 15:12:06 +020015179 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15180
15181 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15182 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15183 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15184 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15185 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15186 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15187 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015188 }
15189
15190 return error;
15191}
15192
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015193#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15194
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015195void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015196intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015197 struct drm_device *dev,
15198 struct intel_display_error_state *error)
15199{
Damien Lespiau055e3932014-08-18 13:49:10 +010015200 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015201 int i;
15202
Chris Wilson63b66e52013-08-08 15:12:06 +020015203 if (!error)
15204 return;
15205
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015206 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020015207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015208 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030015209 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010015210 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015211 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020015212 err_printf(m, " Power: %s\n",
15213 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015214 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e12014-04-18 15:55:04 +030015215 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015216
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015217 err_printf(m, "Plane [%d]:\n", i);
15218 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15219 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030015220 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015221 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15222 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030015223 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030015224 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015225 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015226 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015227 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15228 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015229 }
15230
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030015231 err_printf(m, "Cursor [%d]:\n", i);
15232 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15233 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15234 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015235 }
Chris Wilson63b66e52013-08-08 15:12:06 +020015236
15237 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010015238 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020015239 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020015240 err_printf(m, " Power: %s\n",
15241 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020015242 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15243 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15244 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15245 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15246 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15247 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15248 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15249 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000015250}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030015251
15252void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15253{
15254 struct intel_crtc *crtc;
15255
15256 for_each_intel_crtc(dev, crtc) {
15257 struct intel_unpin_work *work;
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030015258
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020015259 spin_lock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030015260
15261 work = crtc->unpin_work;
15262
15263 if (work && work->event &&
15264 work->event->base.file_priv == file) {
15265 kfree(work->event);
15266 work->event = NULL;
15267 }
15268
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020015269 spin_unlock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030015270 }
15271}