Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 31 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 34 | #include <drm/drm_edid.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drmP.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 39 | #include "i915_trace.h" |
Xi Ruoyao | 319c1d4 | 2015-03-12 20:16:32 +0800 | [diff] [blame] | 40 | #include <drm/drm_atomic.h> |
Matt Roper | c196e1d | 2015-01-21 16:35:48 -0800 | [diff] [blame] | 41 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 42 | #include <drm/drm_dp_helper.h> |
| 43 | #include <drm/drm_crtc_helper.h> |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 44 | #include <drm/drm_plane_helper.h> |
| 45 | #include <drm/drm_rect.h> |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 46 | #include <linux/dma_remapping.h> |
Alex Goins | fd8e058 | 2015-11-25 18:43:38 -0800 | [diff] [blame] | 47 | #include <linux/reservation.h> |
| 48 | #include <linux/dma-buf.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 49 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 50 | /* Primary plane formats for gen <= 3 */ |
Damien Lespiau | 568db4f | 2015-05-12 16:13:18 +0100 | [diff] [blame] | 51 | static const uint32_t i8xx_primary_formats[] = { |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 52 | DRM_FORMAT_C8, |
| 53 | DRM_FORMAT_RGB565, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 54 | DRM_FORMAT_XRGB1555, |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 55 | DRM_FORMAT_XRGB8888, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 56 | }; |
| 57 | |
| 58 | /* Primary plane formats for gen >= 4 */ |
Damien Lespiau | 568db4f | 2015-05-12 16:13:18 +0100 | [diff] [blame] | 59 | static const uint32_t i965_primary_formats[] = { |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 60 | DRM_FORMAT_C8, |
| 61 | DRM_FORMAT_RGB565, |
| 62 | DRM_FORMAT_XRGB8888, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 63 | DRM_FORMAT_XBGR8888, |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 64 | DRM_FORMAT_XRGB2101010, |
| 65 | DRM_FORMAT_XBGR2101010, |
| 66 | }; |
| 67 | |
| 68 | static const uint32_t skl_primary_formats[] = { |
| 69 | DRM_FORMAT_C8, |
| 70 | DRM_FORMAT_RGB565, |
| 71 | DRM_FORMAT_XRGB8888, |
| 72 | DRM_FORMAT_XBGR8888, |
Damien Lespiau | 67fe7dc | 2015-05-15 19:06:00 +0100 | [diff] [blame] | 73 | DRM_FORMAT_ARGB8888, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 74 | DRM_FORMAT_ABGR8888, |
| 75 | DRM_FORMAT_XRGB2101010, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 76 | DRM_FORMAT_XBGR2101010, |
Kumar, Mahesh | ea916ea | 2015-09-03 16:17:09 +0530 | [diff] [blame] | 77 | DRM_FORMAT_YUYV, |
| 78 | DRM_FORMAT_YVYU, |
| 79 | DRM_FORMAT_UYVY, |
| 80 | DRM_FORMAT_VYUY, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 81 | }; |
| 82 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 83 | /* Cursor formats */ |
| 84 | static const uint32_t intel_cursor_formats[] = { |
| 85 | DRM_FORMAT_ARGB8888, |
| 86 | }; |
| 87 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 88 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 89 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 91 | struct intel_crtc_state *pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 93 | struct intel_crtc_state *pipe_config); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 94 | |
Jesse Barnes | eb1bfe8 | 2014-02-12 12:26:25 -0800 | [diff] [blame] | 95 | static int intel_framebuffer_init(struct drm_device *dev, |
| 96 | struct intel_framebuffer *ifb, |
| 97 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 98 | struct drm_i915_gem_object *obj); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 99 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
| 100 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 102 | struct intel_link_m_n *m_n, |
| 103 | struct intel_link_m_n *m2_n2); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
| 106 | static void intel_set_pipe_csc(struct drm_crtc *crtc); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 108 | const struct intel_crtc_state *pipe_config); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 110 | const struct intel_crtc_state *pipe_config); |
Maarten Lankhorst | 613d2b2 | 2015-07-21 13:28:58 +0200 | [diff] [blame] | 111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
| 112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
| 114 | struct intel_crtc_state *crtc_state); |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 115 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
| 116 | int num_connectors); |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 117 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
| 118 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); |
| 119 | static void ironlake_pfit_enable(struct intel_crtc *crtc); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 120 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 121 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 122 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 123 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 124 | int min, max; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 125 | } intel_range_t; |
| 126 | |
| 127 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 128 | int dot_limit; |
| 129 | int p2_slow, p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 130 | } intel_p2_t; |
| 131 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 132 | typedef struct intel_limit intel_limit_t; |
| 133 | struct intel_limit { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 134 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 135 | intel_p2_t p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 136 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 137 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 138 | /* returns HPLL frequency in kHz */ |
| 139 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
| 140 | { |
| 141 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
| 142 | |
| 143 | /* Obtain SKU information */ |
| 144 | mutex_lock(&dev_priv->sb_lock); |
| 145 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
| 146 | CCK_FUSE_HPLL_FREQ_MASK; |
| 147 | mutex_unlock(&dev_priv->sb_lock); |
| 148 | |
| 149 | return vco_freq[hpll_freq] * 1000; |
| 150 | } |
| 151 | |
| 152 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
| 153 | const char *name, u32 reg) |
| 154 | { |
| 155 | u32 val; |
| 156 | int divider; |
| 157 | |
| 158 | if (dev_priv->hpll_freq == 0) |
| 159 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); |
| 160 | |
| 161 | mutex_lock(&dev_priv->sb_lock); |
| 162 | val = vlv_cck_read(dev_priv, reg); |
| 163 | mutex_unlock(&dev_priv->sb_lock); |
| 164 | |
| 165 | divider = val & CCK_FREQUENCY_VALUES; |
| 166 | |
| 167 | WARN((val & CCK_FREQUENCY_STATUS) != |
| 168 | (divider << CCK_FREQUENCY_STATUS_SHIFT), |
| 169 | "%s change in progress\n", name); |
| 170 | |
| 171 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
| 172 | } |
| 173 | |
Daniel Vetter | d2acd21 | 2012-10-20 20:57:43 +0200 | [diff] [blame] | 174 | int |
| 175 | intel_pch_rawclk(struct drm_device *dev) |
| 176 | { |
| 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 178 | |
| 179 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
| 180 | |
| 181 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
| 182 | } |
| 183 | |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 184 | /* hrawclock is 1/4 the FSB frequency */ |
| 185 | int intel_hrawclk(struct drm_device *dev) |
| 186 | { |
| 187 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 188 | uint32_t clkcfg; |
| 189 | |
| 190 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 191 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Jani Nikula | 79e50a4 | 2015-08-26 10:58:20 +0300 | [diff] [blame] | 192 | return 200; |
| 193 | |
| 194 | clkcfg = I915_READ(CLKCFG); |
| 195 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 196 | case CLKCFG_FSB_400: |
| 197 | return 100; |
| 198 | case CLKCFG_FSB_533: |
| 199 | return 133; |
| 200 | case CLKCFG_FSB_667: |
| 201 | return 166; |
| 202 | case CLKCFG_FSB_800: |
| 203 | return 200; |
| 204 | case CLKCFG_FSB_1067: |
| 205 | return 266; |
| 206 | case CLKCFG_FSB_1333: |
| 207 | return 333; |
| 208 | /* these two are just a guess; one of them might be right */ |
| 209 | case CLKCFG_FSB_1600: |
| 210 | case CLKCFG_FSB_1600_ALT: |
| 211 | return 400; |
| 212 | default: |
| 213 | return 133; |
| 214 | } |
| 215 | } |
| 216 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 217 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
| 218 | { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 219 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 220 | return; |
| 221 | |
| 222 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", |
| 223 | CCK_CZ_CLOCK_CONTROL); |
| 224 | |
| 225 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); |
| 226 | } |
| 227 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 228 | static inline u32 /* units of 100MHz */ |
| 229 | intel_fdi_link_freq(struct drm_device *dev) |
| 230 | { |
Chris Wilson | 8b99e68 | 2010-10-13 09:59:17 +0100 | [diff] [blame] | 231 | if (IS_GEN5(dev)) { |
| 232 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 233 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 234 | } else |
| 235 | return 27; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 236 | } |
| 237 | |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 238 | static const intel_limit_t intel_limits_i8xx_dac = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 239 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 240 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 241 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 242 | .m = { .min = 96, .max = 140 }, |
| 243 | .m1 = { .min = 18, .max = 26 }, |
| 244 | .m2 = { .min = 6, .max = 16 }, |
| 245 | .p = { .min = 4, .max = 128 }, |
| 246 | .p1 = { .min = 2, .max = 33 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 247 | .p2 = { .dot_limit = 165000, |
| 248 | .p2_slow = 4, .p2_fast = 2 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 249 | }; |
| 250 | |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 251 | static const intel_limit_t intel_limits_i8xx_dvo = { |
| 252 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 253 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 254 | .n = { .min = 2, .max = 16 }, |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 255 | .m = { .min = 96, .max = 140 }, |
| 256 | .m1 = { .min = 18, .max = 26 }, |
| 257 | .m2 = { .min = 6, .max = 16 }, |
| 258 | .p = { .min = 4, .max = 128 }, |
| 259 | .p1 = { .min = 2, .max = 33 }, |
| 260 | .p2 = { .dot_limit = 165000, |
| 261 | .p2_slow = 4, .p2_fast = 4 }, |
| 262 | }; |
| 263 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 264 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 265 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 266 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 267 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 268 | .m = { .min = 96, .max = 140 }, |
| 269 | .m1 = { .min = 18, .max = 26 }, |
| 270 | .m2 = { .min = 6, .max = 16 }, |
| 271 | .p = { .min = 4, .max = 128 }, |
| 272 | .p1 = { .min = 1, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 273 | .p2 = { .dot_limit = 165000, |
| 274 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 275 | }; |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 276 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 277 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 278 | .dot = { .min = 20000, .max = 400000 }, |
| 279 | .vco = { .min = 1400000, .max = 2800000 }, |
| 280 | .n = { .min = 1, .max = 6 }, |
| 281 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 4f7dfb6 | 2013-02-13 22:20:22 +0100 | [diff] [blame] | 282 | .m1 = { .min = 8, .max = 18 }, |
| 283 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 284 | .p = { .min = 5, .max = 80 }, |
| 285 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 286 | .p2 = { .dot_limit = 200000, |
| 287 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 291 | .dot = { .min = 20000, .max = 400000 }, |
| 292 | .vco = { .min = 1400000, .max = 2800000 }, |
| 293 | .n = { .min = 1, .max = 6 }, |
| 294 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 53a7d2d | 2013-02-13 22:20:21 +0100 | [diff] [blame] | 295 | .m1 = { .min = 8, .max = 18 }, |
| 296 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 297 | .p = { .min = 7, .max = 98 }, |
| 298 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 299 | .p2 = { .dot_limit = 112000, |
| 300 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 301 | }; |
| 302 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 303 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 304 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 305 | .dot = { .min = 25000, .max = 270000 }, |
| 306 | .vco = { .min = 1750000, .max = 3500000}, |
| 307 | .n = { .min = 1, .max = 4 }, |
| 308 | .m = { .min = 104, .max = 138 }, |
| 309 | .m1 = { .min = 17, .max = 23 }, |
| 310 | .m2 = { .min = 5, .max = 11 }, |
| 311 | .p = { .min = 10, .max = 30 }, |
| 312 | .p1 = { .min = 1, .max = 3}, |
| 313 | .p2 = { .dot_limit = 270000, |
| 314 | .p2_slow = 10, |
| 315 | .p2_fast = 10 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 316 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 320 | .dot = { .min = 22000, .max = 400000 }, |
| 321 | .vco = { .min = 1750000, .max = 3500000}, |
| 322 | .n = { .min = 1, .max = 4 }, |
| 323 | .m = { .min = 104, .max = 138 }, |
| 324 | .m1 = { .min = 16, .max = 23 }, |
| 325 | .m2 = { .min = 5, .max = 11 }, |
| 326 | .p = { .min = 5, .max = 80 }, |
| 327 | .p1 = { .min = 1, .max = 8}, |
| 328 | .p2 = { .dot_limit = 165000, |
| 329 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 333 | .dot = { .min = 20000, .max = 115000 }, |
| 334 | .vco = { .min = 1750000, .max = 3500000 }, |
| 335 | .n = { .min = 1, .max = 3 }, |
| 336 | .m = { .min = 104, .max = 138 }, |
| 337 | .m1 = { .min = 17, .max = 23 }, |
| 338 | .m2 = { .min = 5, .max = 11 }, |
| 339 | .p = { .min = 28, .max = 112 }, |
| 340 | .p1 = { .min = 2, .max = 8 }, |
| 341 | .p2 = { .dot_limit = 0, |
| 342 | .p2_slow = 14, .p2_fast = 14 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 343 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 344 | }; |
| 345 | |
| 346 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 347 | .dot = { .min = 80000, .max = 224000 }, |
| 348 | .vco = { .min = 1750000, .max = 3500000 }, |
| 349 | .n = { .min = 1, .max = 3 }, |
| 350 | .m = { .min = 104, .max = 138 }, |
| 351 | .m1 = { .min = 17, .max = 23 }, |
| 352 | .m2 = { .min = 5, .max = 11 }, |
| 353 | .p = { .min = 14, .max = 42 }, |
| 354 | .p1 = { .min = 2, .max = 6 }, |
| 355 | .p2 = { .dot_limit = 0, |
| 356 | .p2_slow = 7, .p2_fast = 7 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 357 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 358 | }; |
| 359 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 360 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 361 | .dot = { .min = 20000, .max = 400000}, |
| 362 | .vco = { .min = 1700000, .max = 3500000 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 363 | /* Pineview's Ncounter is a ring counter */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 364 | .n = { .min = 3, .max = 6 }, |
| 365 | .m = { .min = 2, .max = 256 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 366 | /* Pineview only has one combined m divider, which we treat as m2. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 367 | .m1 = { .min = 0, .max = 0 }, |
| 368 | .m2 = { .min = 0, .max = 254 }, |
| 369 | .p = { .min = 5, .max = 80 }, |
| 370 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 371 | .p2 = { .dot_limit = 200000, |
| 372 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 373 | }; |
| 374 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 375 | static const intel_limit_t intel_limits_pineview_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 376 | .dot = { .min = 20000, .max = 400000 }, |
| 377 | .vco = { .min = 1700000, .max = 3500000 }, |
| 378 | .n = { .min = 3, .max = 6 }, |
| 379 | .m = { .min = 2, .max = 256 }, |
| 380 | .m1 = { .min = 0, .max = 0 }, |
| 381 | .m2 = { .min = 0, .max = 254 }, |
| 382 | .p = { .min = 7, .max = 112 }, |
| 383 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 384 | .p2 = { .dot_limit = 112000, |
| 385 | .p2_slow = 14, .p2_fast = 14 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 386 | }; |
| 387 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 388 | /* Ironlake / Sandybridge |
| 389 | * |
| 390 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 391 | * the range value for them is (actual_value - 2). |
| 392 | */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 393 | static const intel_limit_t intel_limits_ironlake_dac = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 394 | .dot = { .min = 25000, .max = 350000 }, |
| 395 | .vco = { .min = 1760000, .max = 3510000 }, |
| 396 | .n = { .min = 1, .max = 5 }, |
| 397 | .m = { .min = 79, .max = 127 }, |
| 398 | .m1 = { .min = 12, .max = 22 }, |
| 399 | .m2 = { .min = 5, .max = 9 }, |
| 400 | .p = { .min = 5, .max = 80 }, |
| 401 | .p1 = { .min = 1, .max = 8 }, |
| 402 | .p2 = { .dot_limit = 225000, |
| 403 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 404 | }; |
| 405 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 406 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 407 | .dot = { .min = 25000, .max = 350000 }, |
| 408 | .vco = { .min = 1760000, .max = 3510000 }, |
| 409 | .n = { .min = 1, .max = 3 }, |
| 410 | .m = { .min = 79, .max = 118 }, |
| 411 | .m1 = { .min = 12, .max = 22 }, |
| 412 | .m2 = { .min = 5, .max = 9 }, |
| 413 | .p = { .min = 28, .max = 112 }, |
| 414 | .p1 = { .min = 2, .max = 8 }, |
| 415 | .p2 = { .dot_limit = 225000, |
| 416 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 417 | }; |
| 418 | |
| 419 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 420 | .dot = { .min = 25000, .max = 350000 }, |
| 421 | .vco = { .min = 1760000, .max = 3510000 }, |
| 422 | .n = { .min = 1, .max = 3 }, |
| 423 | .m = { .min = 79, .max = 127 }, |
| 424 | .m1 = { .min = 12, .max = 22 }, |
| 425 | .m2 = { .min = 5, .max = 9 }, |
| 426 | .p = { .min = 14, .max = 56 }, |
| 427 | .p1 = { .min = 2, .max = 8 }, |
| 428 | .p2 = { .dot_limit = 225000, |
| 429 | .p2_slow = 7, .p2_fast = 7 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 430 | }; |
| 431 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 432 | /* LVDS 100mhz refclk limits. */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 433 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 434 | .dot = { .min = 25000, .max = 350000 }, |
| 435 | .vco = { .min = 1760000, .max = 3510000 }, |
| 436 | .n = { .min = 1, .max = 2 }, |
| 437 | .m = { .min = 79, .max = 126 }, |
| 438 | .m1 = { .min = 12, .max = 22 }, |
| 439 | .m2 = { .min = 5, .max = 9 }, |
| 440 | .p = { .min = 28, .max = 112 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 441 | .p1 = { .min = 2, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 442 | .p2 = { .dot_limit = 225000, |
| 443 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 444 | }; |
| 445 | |
| 446 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 447 | .dot = { .min = 25000, .max = 350000 }, |
| 448 | .vco = { .min = 1760000, .max = 3510000 }, |
| 449 | .n = { .min = 1, .max = 3 }, |
| 450 | .m = { .min = 79, .max = 126 }, |
| 451 | .m1 = { .min = 12, .max = 22 }, |
| 452 | .m2 = { .min = 5, .max = 9 }, |
| 453 | .p = { .min = 14, .max = 42 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 454 | .p1 = { .min = 2, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 455 | .p2 = { .dot_limit = 225000, |
| 456 | .p2_slow = 7, .p2_fast = 7 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 457 | }; |
| 458 | |
Ville Syrjälä | dc73051 | 2013-09-24 21:26:30 +0300 | [diff] [blame] | 459 | static const intel_limit_t intel_limits_vlv = { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 460 | /* |
| 461 | * These are the data rate limits (measured in fast clocks) |
| 462 | * since those are the strictest limits we have. The fast |
| 463 | * clock and actual rate limits are more relaxed, so checking |
| 464 | * them would make no difference. |
| 465 | */ |
| 466 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
Daniel Vetter | 75e5398 | 2013-04-18 21:10:43 +0200 | [diff] [blame] | 467 | .vco = { .min = 4000000, .max = 6000000 }, |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 468 | .n = { .min = 1, .max = 7 }, |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 469 | .m1 = { .min = 2, .max = 3 }, |
| 470 | .m2 = { .min = 11, .max = 156 }, |
Ville Syrjälä | b99ab66 | 2013-09-24 21:26:26 +0300 | [diff] [blame] | 471 | .p1 = { .min = 2, .max = 3 }, |
Ville Syrjälä | 5fdc9c49 | 2013-09-24 21:26:29 +0300 | [diff] [blame] | 472 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 473 | }; |
| 474 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 475 | static const intel_limit_t intel_limits_chv = { |
| 476 | /* |
| 477 | * These are the data rate limits (measured in fast clocks) |
| 478 | * since those are the strictest limits we have. The fast |
| 479 | * clock and actual rate limits are more relaxed, so checking |
| 480 | * them would make no difference. |
| 481 | */ |
| 482 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
Ville Syrjälä | 17fe102 | 2015-02-26 21:01:52 +0200 | [diff] [blame] | 483 | .vco = { .min = 4800000, .max = 6480000 }, |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 484 | .n = { .min = 1, .max = 1 }, |
| 485 | .m1 = { .min = 2, .max = 2 }, |
| 486 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
| 487 | .p1 = { .min = 2, .max = 4 }, |
| 488 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
| 489 | }; |
| 490 | |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 491 | static const intel_limit_t intel_limits_bxt = { |
| 492 | /* FIXME: find real dot limits */ |
| 493 | .dot = { .min = 0, .max = INT_MAX }, |
Vandana Kannan | e629255 | 2015-07-01 17:02:57 +0530 | [diff] [blame] | 494 | .vco = { .min = 4800000, .max = 6700000 }, |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 495 | .n = { .min = 1, .max = 1 }, |
| 496 | .m1 = { .min = 2, .max = 2 }, |
| 497 | /* FIXME: find real m2 limits */ |
| 498 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, |
| 499 | .p1 = { .min = 2, .max = 4 }, |
| 500 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, |
| 501 | }; |
| 502 | |
Ander Conselvan de Oliveira | cdba954 | 2015-06-01 12:49:51 +0200 | [diff] [blame] | 503 | static bool |
| 504 | needs_modeset(struct drm_crtc_state *state) |
| 505 | { |
Maarten Lankhorst | fc59666 | 2015-07-21 13:28:57 +0200 | [diff] [blame] | 506 | return drm_atomic_crtc_needs_modeset(state); |
Ander Conselvan de Oliveira | cdba954 | 2015-06-01 12:49:51 +0200 | [diff] [blame] | 507 | } |
| 508 | |
Paulo Zanoni | e0638cd | 2013-09-24 13:52:54 -0300 | [diff] [blame] | 509 | /** |
| 510 | * Returns whether any output on the specified pipe is of the specified type |
| 511 | */ |
Damien Lespiau | 4093561 | 2014-10-29 11:16:59 +0000 | [diff] [blame] | 512 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
Paulo Zanoni | e0638cd | 2013-09-24 13:52:54 -0300 | [diff] [blame] | 513 | { |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 514 | struct drm_device *dev = crtc->base.dev; |
Paulo Zanoni | e0638cd | 2013-09-24 13:52:54 -0300 | [diff] [blame] | 515 | struct intel_encoder *encoder; |
| 516 | |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 517 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
Paulo Zanoni | e0638cd | 2013-09-24 13:52:54 -0300 | [diff] [blame] | 518 | if (encoder->type == type) |
| 519 | return true; |
| 520 | |
| 521 | return false; |
| 522 | } |
| 523 | |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 524 | /** |
| 525 | * Returns whether any output on the specified pipe will have the specified |
| 526 | * type after a staged modeset is complete, i.e., the same as |
| 527 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of |
| 528 | * encoder->crtc. |
| 529 | */ |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 530 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
| 531 | int type) |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 532 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 533 | struct drm_atomic_state *state = crtc_state->base.state; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 534 | struct drm_connector *connector; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 535 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 536 | struct intel_encoder *encoder; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 537 | int i, num_connectors = 0; |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 538 | |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 539 | for_each_connector_in_state(state, connector, connector_state, i) { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 540 | if (connector_state->crtc != crtc_state->base.crtc) |
| 541 | continue; |
| 542 | |
| 543 | num_connectors++; |
| 544 | |
| 545 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 546 | if (encoder->type == type) |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 547 | return true; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | WARN_ON(num_connectors == 0); |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 551 | |
| 552 | return false; |
| 553 | } |
| 554 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 555 | static const intel_limit_t * |
| 556 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 557 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 558 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 559 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 560 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 561 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 562 | if (intel_is_dual_link_lvds(dev)) { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 563 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 564 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 565 | else |
| 566 | limit = &intel_limits_ironlake_dual_lvds; |
| 567 | } else { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 568 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 569 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 570 | else |
| 571 | limit = &intel_limits_ironlake_single_lvds; |
| 572 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 573 | } else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 574 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 575 | |
| 576 | return limit; |
| 577 | } |
| 578 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 579 | static const intel_limit_t * |
| 580 | intel_g4x_limit(struct intel_crtc_state *crtc_state) |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 581 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 582 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 583 | const intel_limit_t *limit; |
| 584 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 585 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 586 | if (intel_is_dual_link_lvds(dev)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 587 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 588 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 589 | limit = &intel_limits_g4x_single_channel_lvds; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
| 591 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 592 | limit = &intel_limits_g4x_hdmi; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 593 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 594 | limit = &intel_limits_g4x_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 595 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 596 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 597 | |
| 598 | return limit; |
| 599 | } |
| 600 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 601 | static const intel_limit_t * |
| 602 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 603 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 604 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 605 | const intel_limit_t *limit; |
| 606 | |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 607 | if (IS_BROXTON(dev)) |
| 608 | limit = &intel_limits_bxt; |
| 609 | else if (HAS_PCH_SPLIT(dev)) |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 610 | limit = intel_ironlake_limit(crtc_state, refclk); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 611 | else if (IS_G4X(dev)) { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 612 | limit = intel_g4x_limit(crtc_state); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 613 | } else if (IS_PINEVIEW(dev)) { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 614 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 615 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 616 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 617 | limit = &intel_limits_pineview_sdvo; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 618 | } else if (IS_CHERRYVIEW(dev)) { |
| 619 | limit = &intel_limits_chv; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 620 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | dc73051 | 2013-09-24 21:26:30 +0300 | [diff] [blame] | 621 | limit = &intel_limits_vlv; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 622 | } else if (!IS_GEN2(dev)) { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 623 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 624 | limit = &intel_limits_i9xx_lvds; |
| 625 | else |
| 626 | limit = &intel_limits_i9xx_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 627 | } else { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 628 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 629 | limit = &intel_limits_i8xx_lvds; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 630 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 631 | limit = &intel_limits_i8xx_dvo; |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 632 | else |
| 633 | limit = &intel_limits_i8xx_dac; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 634 | } |
| 635 | return limit; |
| 636 | } |
| 637 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 638 | /* |
| 639 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), |
| 640 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast |
| 641 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. |
| 642 | * The helpers' return value is the rate of the clock that is fed to the |
| 643 | * display engine's pipe which can be the above fast dot clock rate or a |
| 644 | * divided-down version of it. |
| 645 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 646 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 647 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 648 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 649 | clock->m = clock->m2 + 2; |
| 650 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 651 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 652 | return 0; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 653 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 654 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 655 | |
| 656 | return clock->dot; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 657 | } |
| 658 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 659 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
| 660 | { |
| 661 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
| 662 | } |
| 663 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 664 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 665 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 666 | clock->m = i9xx_dpll_compute_m(clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 667 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 668 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 669 | return 0; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 670 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
| 671 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 672 | |
| 673 | return clock->dot; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 674 | } |
| 675 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 676 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
Imre Deak | 589eca6 | 2015-06-22 23:35:50 +0300 | [diff] [blame] | 677 | { |
| 678 | clock->m = clock->m1 * clock->m2; |
| 679 | clock->p = clock->p1 * clock->p2; |
| 680 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 681 | return 0; |
Imre Deak | 589eca6 | 2015-06-22 23:35:50 +0300 | [diff] [blame] | 682 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 683 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 684 | |
| 685 | return clock->dot / 5; |
Imre Deak | 589eca6 | 2015-06-22 23:35:50 +0300 | [diff] [blame] | 686 | } |
| 687 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 688 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 689 | { |
| 690 | clock->m = clock->m1 * clock->m2; |
| 691 | clock->p = clock->p1 * clock->p2; |
| 692 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 693 | return 0; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 694 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
| 695 | clock->n << 22); |
| 696 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 697 | |
| 698 | return clock->dot / 5; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 699 | } |
| 700 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 701 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 702 | /** |
| 703 | * Returns whether the given set of divisors are valid for a given refclk with |
| 704 | * the given connectors. |
| 705 | */ |
| 706 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 707 | static bool intel_PLL_is_valid(struct drm_device *dev, |
| 708 | const intel_limit_t *limit, |
| 709 | const intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 710 | { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 711 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 712 | INTELPllInvalid("n out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 713 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 714 | INTELPllInvalid("p1 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 715 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 716 | INTELPllInvalid("m2 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 717 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 718 | INTELPllInvalid("m1 out of range\n"); |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 719 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 720 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
| 721 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 722 | if (clock->m1 <= clock->m2) |
| 723 | INTELPllInvalid("m1 <= m2\n"); |
| 724 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 726 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 727 | INTELPllInvalid("p out of range\n"); |
| 728 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 729 | INTELPllInvalid("m out of range\n"); |
| 730 | } |
| 731 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 732 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 733 | INTELPllInvalid("vco out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 734 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 735 | * connector, etc., rather than just a single range. |
| 736 | */ |
| 737 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 738 | INTELPllInvalid("dot out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 739 | |
| 740 | return true; |
| 741 | } |
| 742 | |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 743 | static int |
| 744 | i9xx_select_p2_div(const intel_limit_t *limit, |
| 745 | const struct intel_crtc_state *crtc_state, |
| 746 | int target) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 747 | { |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 748 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 749 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 750 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 751 | /* |
Daniel Vetter | a210b02 | 2012-11-26 17:22:08 +0100 | [diff] [blame] | 752 | * For LVDS just rely on its current settings for dual-channel. |
| 753 | * We haven't figured out how to reliably set up different |
| 754 | * single/dual channel state, if we even can. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 755 | */ |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 756 | if (intel_is_dual_link_lvds(dev)) |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 757 | return limit->p2.p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 758 | else |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 759 | return limit->p2.p2_slow; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 760 | } else { |
| 761 | if (target < limit->p2.dot_limit) |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 762 | return limit->p2.p2_slow; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 763 | else |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 764 | return limit->p2.p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 765 | } |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | static bool |
| 769 | i9xx_find_best_dpll(const intel_limit_t *limit, |
| 770 | struct intel_crtc_state *crtc_state, |
| 771 | int target, int refclk, intel_clock_t *match_clock, |
| 772 | intel_clock_t *best_clock) |
| 773 | { |
| 774 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 775 | intel_clock_t clock; |
| 776 | int err = target; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 777 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 778 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 779 | |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 780 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 781 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 782 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 783 | clock.m1++) { |
| 784 | for (clock.m2 = limit->m2.min; |
| 785 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | c0efc38 | 2013-06-03 20:56:24 +0200 | [diff] [blame] | 786 | if (clock.m2 >= clock.m1) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 787 | break; |
| 788 | for (clock.n = limit->n.min; |
| 789 | clock.n <= limit->n.max; clock.n++) { |
| 790 | for (clock.p1 = limit->p1.min; |
| 791 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 792 | int this_err; |
| 793 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 794 | i9xx_calc_dpll_params(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 795 | if (!intel_PLL_is_valid(dev, limit, |
| 796 | &clock)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 797 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 798 | if (match_clock && |
| 799 | clock.p != match_clock->p) |
| 800 | continue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 801 | |
| 802 | this_err = abs(clock.dot - target); |
| 803 | if (this_err < err) { |
| 804 | *best_clock = clock; |
| 805 | err = this_err; |
| 806 | } |
| 807 | } |
| 808 | } |
| 809 | } |
| 810 | } |
| 811 | |
| 812 | return (err != target); |
| 813 | } |
| 814 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 815 | static bool |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 816 | pnv_find_best_dpll(const intel_limit_t *limit, |
| 817 | struct intel_crtc_state *crtc_state, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 818 | int target, int refclk, intel_clock_t *match_clock, |
| 819 | intel_clock_t *best_clock) |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 820 | { |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 821 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 822 | intel_clock_t clock; |
| 823 | int err = target; |
| 824 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 825 | memset(best_clock, 0, sizeof(*best_clock)); |
| 826 | |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 827 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 828 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 829 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 830 | clock.m1++) { |
| 831 | for (clock.m2 = limit->m2.min; |
| 832 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 833 | for (clock.n = limit->n.min; |
| 834 | clock.n <= limit->n.max; clock.n++) { |
| 835 | for (clock.p1 = limit->p1.min; |
| 836 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 837 | int this_err; |
| 838 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 839 | pnv_calc_dpll_params(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 840 | if (!intel_PLL_is_valid(dev, limit, |
| 841 | &clock)) |
| 842 | continue; |
| 843 | if (match_clock && |
| 844 | clock.p != match_clock->p) |
| 845 | continue; |
| 846 | |
| 847 | this_err = abs(clock.dot - target); |
| 848 | if (this_err < err) { |
| 849 | *best_clock = clock; |
| 850 | err = this_err; |
| 851 | } |
| 852 | } |
| 853 | } |
| 854 | } |
| 855 | } |
| 856 | |
| 857 | return (err != target); |
| 858 | } |
| 859 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 860 | static bool |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 861 | g4x_find_best_dpll(const intel_limit_t *limit, |
| 862 | struct intel_crtc_state *crtc_state, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 863 | int target, int refclk, intel_clock_t *match_clock, |
| 864 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 865 | { |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 866 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 867 | intel_clock_t clock; |
| 868 | int max_n; |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 869 | bool found = false; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 870 | /* approximately equals target * 0.00585 */ |
| 871 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 872 | |
| 873 | memset(best_clock, 0, sizeof(*best_clock)); |
Ville Syrjälä | 3b1429d | 2015-06-18 13:47:22 +0300 | [diff] [blame] | 874 | |
| 875 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 876 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 877 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 878 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 879 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 880 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 881 | for (clock.m1 = limit->m1.max; |
| 882 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 883 | for (clock.m2 = limit->m2.max; |
| 884 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 885 | for (clock.p1 = limit->p1.max; |
| 886 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 887 | int this_err; |
| 888 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 889 | i9xx_calc_dpll_params(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 890 | if (!intel_PLL_is_valid(dev, limit, |
| 891 | &clock)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 892 | continue; |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 893 | |
| 894 | this_err = abs(clock.dot - target); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 895 | if (this_err < err_most) { |
| 896 | *best_clock = clock; |
| 897 | err_most = this_err; |
| 898 | max_n = clock.n; |
| 899 | found = true; |
| 900 | } |
| 901 | } |
| 902 | } |
| 903 | } |
| 904 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 905 | return found; |
| 906 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 907 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 908 | /* |
| 909 | * Check if the calculated PLL configuration is more optimal compared to the |
| 910 | * best configuration and error found so far. Return the calculated error. |
| 911 | */ |
| 912 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, |
| 913 | const intel_clock_t *calculated_clock, |
| 914 | const intel_clock_t *best_clock, |
| 915 | unsigned int best_error_ppm, |
| 916 | unsigned int *error_ppm) |
| 917 | { |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 918 | /* |
| 919 | * For CHV ignore the error and consider only the P value. |
| 920 | * Prefer a bigger P value based on HW requirements. |
| 921 | */ |
| 922 | if (IS_CHERRYVIEW(dev)) { |
| 923 | *error_ppm = 0; |
| 924 | |
| 925 | return calculated_clock->p > best_clock->p; |
| 926 | } |
| 927 | |
Imre Deak | 24be4e4 | 2015-03-17 11:40:04 +0200 | [diff] [blame] | 928 | if (WARN_ON_ONCE(!target_freq)) |
| 929 | return false; |
| 930 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 931 | *error_ppm = div_u64(1000000ULL * |
| 932 | abs(target_freq - calculated_clock->dot), |
| 933 | target_freq); |
| 934 | /* |
| 935 | * Prefer a better P value over a better (smaller) error if the error |
| 936 | * is small. Ensure this preference for future configurations too by |
| 937 | * setting the error to 0. |
| 938 | */ |
| 939 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { |
| 940 | *error_ppm = 0; |
| 941 | |
| 942 | return true; |
| 943 | } |
| 944 | |
| 945 | return *error_ppm + 10 < best_error_ppm; |
| 946 | } |
| 947 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 948 | static bool |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 949 | vlv_find_best_dpll(const intel_limit_t *limit, |
| 950 | struct intel_crtc_state *crtc_state, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 951 | int target, int refclk, intel_clock_t *match_clock, |
| 952 | intel_clock_t *best_clock) |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 953 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 954 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | a919ff1 | 2014-10-20 13:46:43 +0300 | [diff] [blame] | 955 | struct drm_device *dev = crtc->base.dev; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 956 | intel_clock_t clock; |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 957 | unsigned int bestppm = 1000000; |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 958 | /* min update 19.2 MHz */ |
| 959 | int max_n = min(limit->n.max, refclk / 19200); |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 960 | bool found = false; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 961 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 962 | target *= 5; /* fast clock */ |
| 963 | |
| 964 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 965 | |
| 966 | /* based on hardware requirement, prefer smaller n to precision */ |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 967 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Ville Syrjälä | 811bbf0 | 2013-09-24 21:26:25 +0300 | [diff] [blame] | 968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
Ville Syrjälä | 889059d | 2013-09-24 21:26:27 +0300 | [diff] [blame] | 969 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
Ville Syrjälä | c1a9ae4 | 2013-09-24 21:26:23 +0300 | [diff] [blame] | 970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 971 | clock.p = clock.p1 * clock.p2; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 972 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 973 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 974 | unsigned int ppm; |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 975 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 976 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
| 977 | refclk * clock.m1); |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 978 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 979 | vlv_calc_dpll_params(refclk, &clock); |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 980 | |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 981 | if (!intel_PLL_is_valid(dev, limit, |
| 982 | &clock)) |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 983 | continue; |
| 984 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 985 | if (!vlv_PLL_is_optimal(dev, target, |
| 986 | &clock, |
| 987 | best_clock, |
| 988 | bestppm, &ppm)) |
| 989 | continue; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 990 | |
Imre Deak | d5dd62b | 2015-03-17 11:40:03 +0200 | [diff] [blame] | 991 | *best_clock = clock; |
| 992 | bestppm = ppm; |
| 993 | found = true; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 994 | } |
| 995 | } |
| 996 | } |
| 997 | } |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 998 | |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 999 | return found; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 1000 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1001 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1002 | static bool |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 1003 | chv_find_best_dpll(const intel_limit_t *limit, |
| 1004 | struct intel_crtc_state *crtc_state, |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1005 | int target, int refclk, intel_clock_t *match_clock, |
| 1006 | intel_clock_t *best_clock) |
| 1007 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 1008 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | a919ff1 | 2014-10-20 13:46:43 +0300 | [diff] [blame] | 1009 | struct drm_device *dev = crtc->base.dev; |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 1010 | unsigned int best_error_ppm; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1011 | intel_clock_t clock; |
| 1012 | uint64_t m2; |
| 1013 | int found = false; |
| 1014 | |
| 1015 | memset(best_clock, 0, sizeof(*best_clock)); |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 1016 | best_error_ppm = 1000000; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1017 | |
| 1018 | /* |
| 1019 | * Based on hardware doc, the n always set to 1, and m1 always |
| 1020 | * set to 2. If requires to support 200Mhz refclk, we need to |
| 1021 | * revisit this because n may not 1 anymore. |
| 1022 | */ |
| 1023 | clock.n = 1, clock.m1 = 2; |
| 1024 | target *= 5; /* fast clock */ |
| 1025 | |
| 1026 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 1027 | for (clock.p2 = limit->p2.p2_fast; |
| 1028 | clock.p2 >= limit->p2.p2_slow; |
| 1029 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 1030 | unsigned int error_ppm; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1031 | |
| 1032 | clock.p = clock.p1 * clock.p2; |
| 1033 | |
| 1034 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * |
| 1035 | clock.n) << 22, refclk * clock.m1); |
| 1036 | |
| 1037 | if (m2 > INT_MAX/clock.m1) |
| 1038 | continue; |
| 1039 | |
| 1040 | clock.m2 = m2; |
| 1041 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 1042 | chv_calc_dpll_params(refclk, &clock); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1043 | |
| 1044 | if (!intel_PLL_is_valid(dev, limit, &clock)) |
| 1045 | continue; |
| 1046 | |
Imre Deak | 9ca3ba0 | 2015-03-17 11:40:05 +0200 | [diff] [blame] | 1047 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
| 1048 | best_error_ppm, &error_ppm)) |
| 1049 | continue; |
| 1050 | |
| 1051 | *best_clock = clock; |
| 1052 | best_error_ppm = error_ppm; |
| 1053 | found = true; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | return found; |
| 1058 | } |
| 1059 | |
Imre Deak | 5ab7b0b | 2015-03-06 03:29:25 +0200 | [diff] [blame] | 1060 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
| 1061 | intel_clock_t *best_clock) |
| 1062 | { |
| 1063 | int refclk = i9xx_get_refclk(crtc_state, 0); |
| 1064 | |
| 1065 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, |
| 1066 | target_clock, refclk, NULL, best_clock); |
| 1067 | } |
| 1068 | |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1069 | bool intel_crtc_active(struct drm_crtc *crtc) |
| 1070 | { |
| 1071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1072 | |
| 1073 | /* Be paranoid as we can arrive here with only partial |
| 1074 | * state retrieved from the hardware during setup. |
| 1075 | * |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1076 | * We can ditch the adjusted_mode.crtc_clock check as soon |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1077 | * as Haswell has gained clock readout/fastboot support. |
| 1078 | * |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 1079 | * We can ditch the crtc->primary->fb check as soon as we can |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1080 | * properly reconstruct framebuffers. |
Matt Roper | c3d1f43 | 2015-03-09 10:19:23 -0700 | [diff] [blame] | 1081 | * |
| 1082 | * FIXME: The intel_crtc->active here should be switched to |
| 1083 | * crtc->state->active once we have proper CRTC states wired up |
| 1084 | * for atomic. |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1085 | */ |
Matt Roper | c3d1f43 | 2015-03-09 10:19:23 -0700 | [diff] [blame] | 1086 | return intel_crtc->active && crtc->primary->state->fb && |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1087 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1088 | } |
| 1089 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 1090 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 1091 | enum pipe pipe) |
| 1092 | { |
| 1093 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1095 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1096 | return intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 1097 | } |
| 1098 | |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1099 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
| 1100 | { |
| 1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1102 | i915_reg_t reg = PIPEDSL(pipe); |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1103 | u32 line1, line2; |
| 1104 | u32 line_mask; |
| 1105 | |
| 1106 | if (IS_GEN2(dev)) |
| 1107 | line_mask = DSL_LINEMASK_GEN2; |
| 1108 | else |
| 1109 | line_mask = DSL_LINEMASK_GEN3; |
| 1110 | |
| 1111 | line1 = I915_READ(reg) & line_mask; |
Daniel Vetter | 6adfb1e | 2015-07-07 09:10:40 +0200 | [diff] [blame] | 1112 | msleep(5); |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1113 | line2 = I915_READ(reg) & line_mask; |
| 1114 | |
| 1115 | return line1 == line2; |
| 1116 | } |
| 1117 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1118 | /* |
| 1119 | * intel_wait_for_pipe_off - wait for pipe to turn off |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1120 | * @crtc: crtc whose pipe to wait for |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1121 | * |
| 1122 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 1123 | * spinning on the vblank interrupt status bit, since we won't actually |
| 1124 | * see an interrupt when the pipe is disabled. |
| 1125 | * |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1126 | * On Gen4 and above: |
| 1127 | * wait for the pipe register state bit to turn off |
| 1128 | * |
| 1129 | * Otherwise: |
| 1130 | * wait for the display line value to settle (it usually |
| 1131 | * ends up stopping at the start of the next frame). |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1132 | * |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1133 | */ |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1134 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1135 | { |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1136 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1138 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 1139 | enum pipe pipe = crtc->pipe; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1140 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1141 | if (INTEL_INFO(dev)->gen >= 4) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1142 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1143 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1144 | /* Wait for the Pipe State to go off */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1145 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
| 1146 | 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 1147 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1148 | } else { |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1149 | /* Wait for the display line to settle */ |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 1150 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 1151 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 1152 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1153 | } |
| 1154 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1155 | static const char *state_string(bool enabled) |
| 1156 | { |
| 1157 | return enabled ? "on" : "off"; |
| 1158 | } |
| 1159 | |
| 1160 | /* Only for pre-ILK configs */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1161 | void assert_pll(struct drm_i915_private *dev_priv, |
| 1162 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1163 | { |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1164 | u32 val; |
| 1165 | bool cur_state; |
| 1166 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1167 | val = I915_READ(DPLL(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1168 | cur_state = !!(val & DPLL_VCO_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1169 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1170 | "PLL state assertion failure (expected %s, current %s)\n", |
| 1171 | state_string(state), state_string(cur_state)); |
| 1172 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1173 | |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1174 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
| 1175 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
| 1176 | { |
| 1177 | u32 val; |
| 1178 | bool cur_state; |
| 1179 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1180 | mutex_lock(&dev_priv->sb_lock); |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1181 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1182 | mutex_unlock(&dev_priv->sb_lock); |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1183 | |
| 1184 | cur_state = val & DSI_PLL_VCO_EN; |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1185 | I915_STATE_WARN(cur_state != state, |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1186 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
| 1187 | state_string(state), state_string(cur_state)); |
| 1188 | } |
| 1189 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
| 1190 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
| 1191 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1192 | struct intel_shared_dpll * |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1193 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1194 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1195 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 1196 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1197 | if (crtc->config->shared_dpll < 0) |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1198 | return NULL; |
| 1199 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1200 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1201 | } |
| 1202 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1203 | /* For ILK+ */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1204 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 1205 | struct intel_shared_dpll *pll, |
| 1206 | bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1207 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1208 | bool cur_state; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 1209 | struct intel_dpll_hw_state hw_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1210 | |
Chris Wilson | 92b27b0 | 2012-05-20 18:10:50 +0100 | [diff] [blame] | 1211 | if (WARN (!pll, |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1212 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1213 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1214 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 1215 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1216 | I915_STATE_WARN(cur_state != state, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 1217 | "%s assertion failure (expected %s, current %s)\n", |
| 1218 | pll->name, state_string(state), state_string(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1219 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1220 | |
| 1221 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 1222 | enum pipe pipe, bool state) |
| 1223 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1224 | bool cur_state; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1225 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1226 | pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1227 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1228 | if (HAS_DDI(dev_priv->dev)) { |
| 1229 | /* DDI does not have a specific FDI_TX register */ |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1230 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1231 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1232 | } else { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1233 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1234 | cur_state = !!(val & FDI_TX_ENABLE); |
| 1235 | } |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1236 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1237 | "FDI TX state assertion failure (expected %s, current %s)\n", |
| 1238 | state_string(state), state_string(cur_state)); |
| 1239 | } |
| 1240 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 1241 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 1242 | |
| 1243 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 1244 | enum pipe pipe, bool state) |
| 1245 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1246 | u32 val; |
| 1247 | bool cur_state; |
| 1248 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1249 | val = I915_READ(FDI_RX_CTL(pipe)); |
Paulo Zanoni | d63fa0d | 2012-11-20 13:27:35 -0200 | [diff] [blame] | 1250 | cur_state = !!(val & FDI_RX_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1251 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1252 | "FDI RX state assertion failure (expected %s, current %s)\n", |
| 1253 | state_string(state), state_string(cur_state)); |
| 1254 | } |
| 1255 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 1256 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 1257 | |
| 1258 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 1259 | enum pipe pipe) |
| 1260 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1261 | u32 val; |
| 1262 | |
| 1263 | /* ILK FDI PLL is always enabled */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1264 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1265 | return; |
| 1266 | |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1267 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1268 | if (HAS_DDI(dev_priv->dev)) |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1269 | return; |
| 1270 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1271 | val = I915_READ(FDI_TX_CTL(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1272 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1273 | } |
| 1274 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1275 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 1276 | enum pipe pipe, bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1277 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1278 | u32 val; |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1279 | bool cur_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1280 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1281 | val = I915_READ(FDI_RX_CTL(pipe)); |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1282 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1283 | I915_STATE_WARN(cur_state != state, |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1284 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
| 1285 | state_string(state), state_string(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1286 | } |
| 1287 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 1288 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 1289 | enum pipe pipe) |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1290 | { |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1291 | struct drm_device *dev = dev_priv->dev; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1292 | i915_reg_t pp_reg; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1293 | u32 val; |
| 1294 | enum pipe panel_pipe = PIPE_A; |
Thomas Jarosch | 0de3b48 | 2011-08-25 15:37:45 +0200 | [diff] [blame] | 1295 | bool locked = true; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1296 | |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1297 | if (WARN_ON(HAS_DDI(dev))) |
| 1298 | return; |
| 1299 | |
| 1300 | if (HAS_PCH_SPLIT(dev)) { |
| 1301 | u32 port_sel; |
| 1302 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1303 | pp_reg = PCH_PP_CONTROL; |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1304 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
| 1305 | |
| 1306 | if (port_sel == PANEL_PORT_SELECT_LVDS && |
| 1307 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) |
| 1308 | panel_pipe = PIPE_B; |
| 1309 | /* XXX: else fix for eDP */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1310 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1311 | /* presumably write lock depends on pipe, not port select */ |
| 1312 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 1313 | panel_pipe = pipe; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1314 | } else { |
| 1315 | pp_reg = PP_CONTROL; |
Jani Nikula | bedd4db | 2014-08-22 15:04:13 +0300 | [diff] [blame] | 1316 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
| 1317 | panel_pipe = PIPE_B; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1318 | } |
| 1319 | |
| 1320 | val = I915_READ(pp_reg); |
| 1321 | if (!(val & PANEL_POWER_ON) || |
Jani Nikula | ec49ba2 | 2014-08-21 15:06:25 +0300 | [diff] [blame] | 1322 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1323 | locked = false; |
| 1324 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1325 | I915_STATE_WARN(panel_pipe == pipe && locked, |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1326 | "panel assertion failure, pipe %c regs locked\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1327 | pipe_name(pipe)); |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1328 | } |
| 1329 | |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1330 | static void assert_cursor(struct drm_i915_private *dev_priv, |
| 1331 | enum pipe pipe, bool state) |
| 1332 | { |
| 1333 | struct drm_device *dev = dev_priv->dev; |
| 1334 | bool cur_state; |
| 1335 | |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1336 | if (IS_845G(dev) || IS_I865G(dev)) |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 1337 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1338 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 1339 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1340 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1341 | I915_STATE_WARN(cur_state != state, |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1342 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
| 1343 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
| 1344 | } |
| 1345 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
| 1346 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
| 1347 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1348 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 1349 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1350 | { |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1351 | bool cur_state; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1352 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1353 | pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1354 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 1355 | /* if we need the pipe quirk it must be always on */ |
| 1356 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1357 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Daniel Vetter | 8e63678 | 2012-01-22 01:36:48 +0100 | [diff] [blame] | 1358 | state = true; |
| 1359 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1360 | if (!intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 1361 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
Paulo Zanoni | 6931016 | 2013-01-29 16:35:19 -0200 | [diff] [blame] | 1362 | cur_state = false; |
| 1363 | } else { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1364 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
Paulo Zanoni | 6931016 | 2013-01-29 16:35:19 -0200 | [diff] [blame] | 1365 | cur_state = !!(val & PIPECONF_ENABLE); |
| 1366 | } |
| 1367 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1368 | I915_STATE_WARN(cur_state != state, |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1369 | "pipe %c assertion failure (expected %s, current %s)\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1370 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1371 | } |
| 1372 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1373 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 1374 | enum plane plane, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1375 | { |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1376 | u32 val; |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1377 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1378 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1379 | val = I915_READ(DSPCNTR(plane)); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1380 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1381 | I915_STATE_WARN(cur_state != state, |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1382 | "plane %c assertion failure (expected %s, current %s)\n", |
| 1383 | plane_name(plane), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1384 | } |
| 1385 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1386 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 1387 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 1388 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1389 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 1390 | enum pipe pipe) |
| 1391 | { |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1392 | struct drm_device *dev = dev_priv->dev; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1393 | int i; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1394 | |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1395 | /* Primary planes are fixed to pipes on gen4+ */ |
| 1396 | if (INTEL_INFO(dev)->gen >= 4) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1397 | u32 val = I915_READ(DSPCNTR(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1398 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1399 | "plane %c assertion failure, should be disabled but not\n", |
| 1400 | plane_name(pipe)); |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1401 | return; |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1402 | } |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1403 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1404 | /* Need to check both planes against the pipe */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1405 | for_each_pipe(dev_priv, i) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1406 | u32 val = I915_READ(DSPCNTR(i)); |
| 1407 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1408 | DISPPLANE_SEL_PIPE_SHIFT; |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1409 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1410 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 1411 | plane_name(i), pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1412 | } |
| 1413 | } |
| 1414 | |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1415 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
| 1416 | enum pipe pipe) |
| 1417 | { |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1418 | struct drm_device *dev = dev_priv->dev; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1419 | int sprite; |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1420 | |
Damien Lespiau | 7feb8b8 | 2014-03-12 21:05:38 +0000 | [diff] [blame] | 1421 | if (INTEL_INFO(dev)->gen >= 9) { |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 1422 | for_each_sprite(dev_priv, pipe, sprite) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1423 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1424 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
Damien Lespiau | 7feb8b8 | 2014-03-12 21:05:38 +0000 | [diff] [blame] | 1425 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
| 1426 | sprite, pipe_name(pipe)); |
| 1427 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1428 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 1429 | for_each_sprite(dev_priv, pipe, sprite) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1430 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1431 | I915_STATE_WARN(val & SP_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1432 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1433 | sprite_name(pipe, sprite), pipe_name(pipe)); |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1434 | } |
| 1435 | } else if (INTEL_INFO(dev)->gen >= 7) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1436 | u32 val = I915_READ(SPRCTL(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1437 | I915_STATE_WARN(val & SPRITE_ENABLE, |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 1438 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1439 | plane_name(pipe), pipe_name(pipe)); |
| 1440 | } else if (INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1441 | u32 val = I915_READ(DVSCNTR(pipe)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1442 | I915_STATE_WARN(val & DVS_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1443 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1444 | plane_name(pipe), pipe_name(pipe)); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1445 | } |
| 1446 | } |
| 1447 | |
Ville Syrjälä | 08c71e5 | 2014-08-06 14:49:45 +0300 | [diff] [blame] | 1448 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
| 1449 | { |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1450 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
Ville Syrjälä | 08c71e5 | 2014-08-06 14:49:45 +0300 | [diff] [blame] | 1451 | drm_crtc_vblank_put(crtc); |
| 1452 | } |
| 1453 | |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 1454 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1455 | { |
| 1456 | u32 val; |
| 1457 | bool enabled; |
| 1458 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1459 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
Eugeni Dodonov | 9d82aa1 | 2012-05-09 15:37:17 -0300 | [diff] [blame] | 1460 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1461 | val = I915_READ(PCH_DREF_CONTROL); |
| 1462 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 1463 | DREF_SUPERSPREAD_SOURCE_MASK)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1464 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1465 | } |
| 1466 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1467 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1468 | enum pipe pipe) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1469 | { |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1470 | u32 val; |
| 1471 | bool enabled; |
| 1472 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1473 | val = I915_READ(PCH_TRANSCONF(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1474 | enabled = !!(val & TRANS_ENABLE); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1475 | I915_STATE_WARN(enabled, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1476 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1477 | pipe_name(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1478 | } |
| 1479 | |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1480 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1481 | enum pipe pipe, u32 port_sel, u32 val) |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1482 | { |
| 1483 | if ((val & DP_PORT_EN) == 0) |
| 1484 | return false; |
| 1485 | |
| 1486 | if (HAS_PCH_CPT(dev_priv->dev)) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1487 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1488 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1489 | return false; |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1490 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1491 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
| 1492 | return false; |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1493 | } else { |
| 1494 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1495 | return false; |
| 1496 | } |
| 1497 | return true; |
| 1498 | } |
| 1499 | |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1500 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1501 | enum pipe pipe, u32 val) |
| 1502 | { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1503 | if ((val & SDVO_ENABLE) == 0) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1504 | return false; |
| 1505 | |
| 1506 | if (HAS_PCH_CPT(dev_priv->dev)) { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1507 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1508 | return false; |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1509 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1510 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
| 1511 | return false; |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1512 | } else { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1513 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1514 | return false; |
| 1515 | } |
| 1516 | return true; |
| 1517 | } |
| 1518 | |
| 1519 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1520 | enum pipe pipe, u32 val) |
| 1521 | { |
| 1522 | if ((val & LVDS_PORT_EN) == 0) |
| 1523 | return false; |
| 1524 | |
| 1525 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1526 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1527 | return false; |
| 1528 | } else { |
| 1529 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1530 | return false; |
| 1531 | } |
| 1532 | return true; |
| 1533 | } |
| 1534 | |
| 1535 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1536 | enum pipe pipe, u32 val) |
| 1537 | { |
| 1538 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1539 | return false; |
| 1540 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1541 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1542 | return false; |
| 1543 | } else { |
| 1544 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1545 | return false; |
| 1546 | } |
| 1547 | return true; |
| 1548 | } |
| 1549 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1550 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1551 | enum pipe pipe, i915_reg_t reg, |
| 1552 | u32 port_sel) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1553 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1554 | u32 val = I915_READ(reg); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1555 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1556 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1557 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1558 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1559 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1560 | && (val & DP_PIPEB_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1561 | "IBX PCH dp port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1562 | } |
| 1563 | |
| 1564 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1565 | enum pipe pipe, i915_reg_t reg) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1566 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1567 | u32 val = I915_READ(reg); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1568 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
Adam Jackson | 23c99e7 | 2011-10-07 14:38:43 -0400 | [diff] [blame] | 1569 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1570 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1571 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1572 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1573 | && (val & SDVO_PIPE_B_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1574 | "IBX PCH hdmi port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1575 | } |
| 1576 | |
| 1577 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1578 | enum pipe pipe) |
| 1579 | { |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1580 | u32 val; |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1581 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1582 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1583 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1584 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1585 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1586 | val = I915_READ(PCH_ADPA); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1587 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1588 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1589 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1590 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 1591 | val = I915_READ(PCH_LVDS); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1592 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1593 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1594 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1595 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 1596 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
| 1597 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
| 1598 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1599 | } |
| 1600 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1601 | static void vlv_enable_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1602 | const struct intel_crtc_state *pipe_config) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1603 | { |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1604 | struct drm_device *dev = crtc->base.dev; |
| 1605 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1606 | i915_reg_t reg = DPLL(crtc->pipe); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1607 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1608 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1609 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1610 | |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1611 | /* PLL is protected by panel, make sure we can write it */ |
Jani Nikula | 6a9e736 | 2014-08-22 15:06:35 +0300 | [diff] [blame] | 1612 | if (IS_MOBILE(dev_priv->dev)) |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1613 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1614 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1615 | I915_WRITE(reg, dpll); |
| 1616 | POSTING_READ(reg); |
| 1617 | udelay(150); |
| 1618 | |
| 1619 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
| 1620 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
| 1621 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1622 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1623 | POSTING_READ(DPLL_MD(crtc->pipe)); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1624 | |
| 1625 | /* We do this three times for luck */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1626 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1627 | POSTING_READ(reg); |
| 1628 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1629 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1630 | POSTING_READ(reg); |
| 1631 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1632 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1633 | POSTING_READ(reg); |
| 1634 | udelay(150); /* wait for warmup */ |
| 1635 | } |
| 1636 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1637 | static void chv_enable_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1638 | const struct intel_crtc_state *pipe_config) |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1639 | { |
| 1640 | struct drm_device *dev = crtc->base.dev; |
| 1641 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1642 | int pipe = crtc->pipe; |
| 1643 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1644 | u32 tmp; |
| 1645 | |
| 1646 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 1647 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1648 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1649 | |
| 1650 | /* Enable back the 10bit clock to display controller */ |
| 1651 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1652 | tmp |= DPIO_DCLKP_EN; |
| 1653 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
| 1654 | |
Ville Syrjälä | 54433e9 | 2015-05-26 20:42:31 +0300 | [diff] [blame] | 1655 | mutex_unlock(&dev_priv->sb_lock); |
| 1656 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1657 | /* |
| 1658 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
| 1659 | */ |
| 1660 | udelay(1); |
| 1661 | |
| 1662 | /* Enable PLL */ |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1663 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1664 | |
| 1665 | /* Check PLL is locked */ |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1666 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1667 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
| 1668 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1669 | /* not sure when this should be written */ |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 1670 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1671 | POSTING_READ(DPLL_MD(pipe)); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 1672 | } |
| 1673 | |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1674 | static int intel_num_dvo_pipes(struct drm_device *dev) |
| 1675 | { |
| 1676 | struct intel_crtc *crtc; |
| 1677 | int count = 0; |
| 1678 | |
| 1679 | for_each_intel_crtc(dev, crtc) |
Maarten Lankhorst | 3538b9d | 2015-06-01 12:50:10 +0200 | [diff] [blame] | 1680 | count += crtc->base.state->active && |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 1681 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1682 | |
| 1683 | return count; |
| 1684 | } |
| 1685 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1686 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1687 | { |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1688 | struct drm_device *dev = crtc->base.dev; |
| 1689 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1690 | i915_reg_t reg = DPLL(crtc->pipe); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1691 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1692 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1693 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1694 | |
| 1695 | /* No really, not for ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1696 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1697 | |
| 1698 | /* PLL is protected by panel, make sure we can write it */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1699 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
| 1700 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1701 | |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1702 | /* Enable DVO 2x clock on both PLLs if necessary */ |
| 1703 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { |
| 1704 | /* |
| 1705 | * It appears to be important that we don't enable this |
| 1706 | * for the current pipe before otherwise configuring the |
| 1707 | * PLL. No idea how this should be handled if multiple |
| 1708 | * DVO outputs are enabled simultaneosly. |
| 1709 | */ |
| 1710 | dpll |= DPLL_DVO_2X_MODE; |
| 1711 | I915_WRITE(DPLL(!crtc->pipe), |
| 1712 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); |
| 1713 | } |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1714 | |
Ville Syrjälä | c2b6337 | 2015-10-07 22:08:25 +0300 | [diff] [blame] | 1715 | /* |
| 1716 | * Apparently we need to have VGA mode enabled prior to changing |
| 1717 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old |
| 1718 | * dividers, even though the register value does change. |
| 1719 | */ |
| 1720 | I915_WRITE(reg, 0); |
| 1721 | |
Ville Syrjälä | 8e7a65a | 2015-10-07 22:08:24 +0300 | [diff] [blame] | 1722 | I915_WRITE(reg, dpll); |
| 1723 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1724 | /* Wait for the clocks to stabilize. */ |
| 1725 | POSTING_READ(reg); |
| 1726 | udelay(150); |
| 1727 | |
| 1728 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1729 | I915_WRITE(DPLL_MD(crtc->pipe), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1730 | crtc->config->dpll_hw_state.dpll_md); |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1731 | } else { |
| 1732 | /* The pixel multiplier can only be updated once the |
| 1733 | * DPLL is enabled and the clocks are stable. |
| 1734 | * |
| 1735 | * So write it again. |
| 1736 | */ |
| 1737 | I915_WRITE(reg, dpll); |
| 1738 | } |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1739 | |
| 1740 | /* We do this three times for luck */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1741 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1742 | POSTING_READ(reg); |
| 1743 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1744 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1745 | POSTING_READ(reg); |
| 1746 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1747 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1748 | POSTING_READ(reg); |
| 1749 | udelay(150); /* wait for warmup */ |
| 1750 | } |
| 1751 | |
| 1752 | /** |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1753 | * i9xx_disable_pll - disable a PLL |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1754 | * @dev_priv: i915 private structure |
| 1755 | * @pipe: pipe PLL to disable |
| 1756 | * |
| 1757 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1758 | * |
| 1759 | * Note! This is for pre-ILK only. |
| 1760 | */ |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1761 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1762 | { |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1763 | struct drm_device *dev = crtc->base.dev; |
| 1764 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1765 | enum pipe pipe = crtc->pipe; |
| 1766 | |
| 1767 | /* Disable DVO 2x clock on both PLLs if necessary */ |
| 1768 | if (IS_I830(dev) && |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 1769 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
Maarten Lankhorst | 3538b9d | 2015-06-01 12:50:10 +0200 | [diff] [blame] | 1770 | !intel_num_dvo_pipes(dev)) { |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 1771 | I915_WRITE(DPLL(PIPE_B), |
| 1772 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); |
| 1773 | I915_WRITE(DPLL(PIPE_A), |
| 1774 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); |
| 1775 | } |
| 1776 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 1777 | /* Don't disable pipe or pipe PLLs if needed */ |
| 1778 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1779 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1780 | return; |
| 1781 | |
| 1782 | /* Make sure the pipe isn't still relying on us */ |
| 1783 | assert_pipe_disabled(dev_priv, pipe); |
| 1784 | |
Ville Syrjälä | b8afb91 | 2015-06-29 15:25:48 +0300 | [diff] [blame] | 1785 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1786 | POSTING_READ(DPLL(pipe)); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1787 | } |
| 1788 | |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1789 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1790 | { |
Ville Syrjälä | b8afb91 | 2015-06-29 15:25:48 +0300 | [diff] [blame] | 1791 | u32 val; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1792 | |
| 1793 | /* Make sure the pipe isn't still relying on us */ |
| 1794 | assert_pipe_disabled(dev_priv, pipe); |
| 1795 | |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1796 | /* |
| 1797 | * Leave integrated clock source and reference clock enabled for pipe B. |
| 1798 | * The latter is needed for VGA hotplug / manual detection. |
| 1799 | */ |
Ville Syrjälä | b8afb91 | 2015-06-29 15:25:48 +0300 | [diff] [blame] | 1800 | val = DPLL_VGA_MODE_DIS; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1801 | if (pipe == PIPE_B) |
Ville Syrjälä | 60bfe44 | 2015-06-29 15:25:49 +0300 | [diff] [blame] | 1802 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1803 | I915_WRITE(DPLL(pipe), val); |
| 1804 | POSTING_READ(DPLL(pipe)); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1805 | |
| 1806 | } |
| 1807 | |
| 1808 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1809 | { |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1810 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1811 | u32 val; |
| 1812 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1813 | /* Make sure the pipe isn't still relying on us */ |
| 1814 | assert_pipe_disabled(dev_priv, pipe); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 1815 | |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1816 | /* Set PLL en = 0 */ |
Ville Syrjälä | 60bfe44 | 2015-06-29 15:25:49 +0300 | [diff] [blame] | 1817 | val = DPLL_SSC_REF_CLK_CHV | |
| 1818 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 1819 | if (pipe != PIPE_A) |
| 1820 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 1821 | I915_WRITE(DPLL(pipe), val); |
| 1822 | POSTING_READ(DPLL(pipe)); |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1823 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1824 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | d752048 | 2014-04-09 13:28:59 +0300 | [diff] [blame] | 1825 | |
| 1826 | /* Disable 10bit clock to display controller */ |
| 1827 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1828 | val &= ~DPIO_DCLKP_EN; |
| 1829 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
| 1830 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 1831 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1832 | } |
| 1833 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1834 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 1835 | struct intel_digital_port *dport, |
| 1836 | unsigned int expected_mask) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1837 | { |
| 1838 | u32 port_mask; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1839 | i915_reg_t dpll_reg; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1840 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1841 | switch (dport->port) { |
| 1842 | case PORT_B: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1843 | port_mask = DPLL_PORTB_READY_MASK; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1844 | dpll_reg = DPLL(0); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1845 | break; |
| 1846 | case PORT_C: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1847 | port_mask = DPLL_PORTC_READY_MASK; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1848 | dpll_reg = DPLL(0); |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 1849 | expected_mask <<= 4; |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 1850 | break; |
| 1851 | case PORT_D: |
| 1852 | port_mask = DPLL_PORTD_READY_MASK; |
| 1853 | dpll_reg = DPIO_PHY_STATUS; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1854 | break; |
| 1855 | default: |
| 1856 | BUG(); |
| 1857 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1858 | |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 1859 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
| 1860 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
| 1861 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1862 | } |
| 1863 | |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 1864 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
| 1865 | { |
| 1866 | struct drm_device *dev = crtc->base.dev; |
| 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1868 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 1869 | |
Chris Wilson | be19f0f | 2014-05-28 16:16:42 +0100 | [diff] [blame] | 1870 | if (WARN_ON(pll == NULL)) |
| 1871 | return; |
| 1872 | |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 1873 | WARN_ON(!pll->config.crtc_mask); |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 1874 | if (pll->active == 0) { |
| 1875 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
| 1876 | WARN_ON(pll->on); |
| 1877 | assert_shared_dpll_disabled(dev_priv, pll); |
| 1878 | |
| 1879 | pll->mode_set(dev_priv, pll); |
| 1880 | } |
| 1881 | } |
| 1882 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1883 | /** |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 1884 | * intel_enable_shared_dpll - enable PCH PLL |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1885 | * @dev_priv: i915 private structure |
| 1886 | * @pipe: pipe PLL to enable |
| 1887 | * |
| 1888 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 1889 | * drives the transcoder clock. |
| 1890 | */ |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 1891 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1892 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1893 | struct drm_device *dev = crtc->base.dev; |
| 1894 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1895 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1896 | |
Daniel Vetter | 87a875b | 2013-06-05 13:34:19 +0200 | [diff] [blame] | 1897 | if (WARN_ON(pll == NULL)) |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1898 | return; |
| 1899 | |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 1900 | if (WARN_ON(pll->config.crtc_mask == 0)) |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1901 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1902 | |
Damien Lespiau | 74dd692 | 2014-07-29 18:06:17 +0100 | [diff] [blame] | 1903 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1904 | pll->name, pll->active, pll->on, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1905 | crtc->base.base.id); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1906 | |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 1907 | if (pll->active++) { |
| 1908 | WARN_ON(!pll->on); |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1909 | assert_shared_dpll_enabled(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1910 | return; |
| 1911 | } |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 1912 | WARN_ON(pll->on); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1913 | |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 1914 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 1915 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1916 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 1917 | pll->enable(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1918 | pll->on = true; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1919 | } |
| 1920 | |
Damien Lespiau | f6daaec | 2014-08-09 23:00:56 +0100 | [diff] [blame] | 1921 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1922 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1923 | struct drm_device *dev = crtc->base.dev; |
| 1924 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1925 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | 4c609cb | 2011-09-02 12:52:11 -0700 | [diff] [blame] | 1926 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1927 | /* PCH only available on ILK+ */ |
Jesse Barnes | 80aa931 | 2015-08-03 13:09:11 -0700 | [diff] [blame] | 1928 | if (INTEL_INFO(dev)->gen < 5) |
| 1929 | return; |
| 1930 | |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 1931 | if (pll == NULL) |
| 1932 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1933 | |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 1934 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1935 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1936 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1937 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
| 1938 | pll->name, pll->active, pll->on, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1939 | crtc->base.base.id); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1940 | |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1941 | if (WARN_ON(pll->active == 0)) { |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1942 | assert_shared_dpll_disabled(dev_priv, pll); |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1943 | return; |
| 1944 | } |
| 1945 | |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1946 | assert_shared_dpll_enabled(dev_priv, pll); |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 1947 | WARN_ON(!pll->on); |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 1948 | if (--pll->active) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1949 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1950 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1951 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 1952 | pll->disable(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1953 | pll->on = false; |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 1954 | |
| 1955 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1956 | } |
| 1957 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1958 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1959 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1960 | { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1961 | struct drm_device *dev = dev_priv->dev; |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1962 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1964 | i915_reg_t reg; |
| 1965 | uint32_t val, pipeconf_val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1966 | |
| 1967 | /* PCH only available on ILK+ */ |
Ville Syrjälä | 55522f3 | 2014-09-03 14:09:53 +0300 | [diff] [blame] | 1968 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1969 | |
| 1970 | /* Make sure PCH DPLL is enabled */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1971 | assert_shared_dpll_enabled(dev_priv, |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1972 | intel_crtc_to_shared_dpll(intel_crtc)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1973 | |
| 1974 | /* FDI must be feeding us bits for PCH ports */ |
| 1975 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1976 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1977 | |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1978 | if (HAS_PCH_CPT(dev)) { |
| 1979 | /* Workaround: Set the timing override bit before enabling the |
| 1980 | * pch transcoder. */ |
| 1981 | reg = TRANS_CHICKEN2(pipe); |
| 1982 | val = I915_READ(reg); |
| 1983 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1984 | I915_WRITE(reg, val); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 1985 | } |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1986 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1987 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1988 | val = I915_READ(reg); |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1989 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1990 | |
| 1991 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 1992 | /* |
Ville Syrjälä | c5de7c6 | 2015-05-05 17:06:22 +0300 | [diff] [blame] | 1993 | * Make the BPC in transcoder be consistent with |
| 1994 | * that in pipeconf reg. For HDMI we must use 8bpc |
| 1995 | * here for both 8bpc and 12bpc. |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1996 | */ |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 1997 | val &= ~PIPECONF_BPC_MASK; |
Ville Syrjälä | c5de7c6 | 2015-05-05 17:06:22 +0300 | [diff] [blame] | 1998 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
| 1999 | val |= PIPECONF_8BPC; |
| 2000 | else |
| 2001 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 2002 | } |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 2003 | |
| 2004 | val &= ~TRANS_INTERLACE_MASK; |
| 2005 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 2006 | if (HAS_PCH_IBX(dev_priv->dev) && |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 2007 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 2008 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 2009 | else |
| 2010 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 2011 | else |
| 2012 | val |= TRANS_PROGRESSIVE; |
| 2013 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2014 | I915_WRITE(reg, val | TRANS_ENABLE); |
| 2015 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 2016 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2017 | } |
| 2018 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2019 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 2020 | enum transcoder cpu_transcoder) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2021 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2022 | u32 val, pipeconf_val; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2023 | |
| 2024 | /* PCH only available on ILK+ */ |
Ville Syrjälä | 55522f3 | 2014-09-03 14:09:53 +0300 | [diff] [blame] | 2025 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2026 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2027 | /* FDI must be feeding us bits for PCH ports */ |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 2028 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 2029 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2030 | |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 2031 | /* Workaround: set timing override bit. */ |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 2032 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 2033 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 2034 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 2035 | |
Paulo Zanoni | 25f3ef1 | 2012-10-31 18:12:49 -0200 | [diff] [blame] | 2036 | val = TRANS_ENABLE; |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 2037 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2038 | |
Paulo Zanoni | 9a76b1c | 2012-10-31 18:12:48 -0200 | [diff] [blame] | 2039 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
| 2040 | PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | a35f267 | 2012-10-31 18:12:45 -0200 | [diff] [blame] | 2041 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2042 | else |
| 2043 | val |= TRANS_PROGRESSIVE; |
| 2044 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 2045 | I915_WRITE(LPT_TRANSCONF, val); |
| 2046 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 2047 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2048 | } |
| 2049 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 2050 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 2051 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2052 | { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 2053 | struct drm_device *dev = dev_priv->dev; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2054 | i915_reg_t reg; |
| 2055 | uint32_t val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2056 | |
| 2057 | /* FDI relies on the transcoder */ |
| 2058 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 2059 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 2060 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 2061 | /* Ports must be off as well */ |
| 2062 | assert_pch_ports_disabled(dev_priv, pipe); |
| 2063 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 2064 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2065 | val = I915_READ(reg); |
| 2066 | val &= ~TRANS_ENABLE; |
| 2067 | I915_WRITE(reg, val); |
| 2068 | /* wait for PCH transcoder off, transcoder state */ |
| 2069 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 2070 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 2071 | |
Ville Syrjälä | c465613 | 2015-10-29 21:25:56 +0200 | [diff] [blame] | 2072 | if (HAS_PCH_CPT(dev)) { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 2073 | /* Workaround: Clear the timing override chicken bit again. */ |
| 2074 | reg = TRANS_CHICKEN2(pipe); |
| 2075 | val = I915_READ(reg); |
| 2076 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 2077 | I915_WRITE(reg, val); |
| 2078 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2079 | } |
| 2080 | |
Paulo Zanoni | ab4d966 | 2012-10-31 18:12:55 -0200 | [diff] [blame] | 2081 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2082 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2083 | u32 val; |
| 2084 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 2085 | val = I915_READ(LPT_TRANSCONF); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2086 | val &= ~TRANS_ENABLE; |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 2087 | I915_WRITE(LPT_TRANSCONF, val); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 2088 | /* wait for PCH transcoder off, transcoder state */ |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 2089 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
Paulo Zanoni | 8a52fd9 | 2012-10-31 18:12:51 -0200 | [diff] [blame] | 2090 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 2091 | |
| 2092 | /* Workaround: clear timing override bit. */ |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 2093 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 2094 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 2095 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 2096 | } |
| 2097 | |
| 2098 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 2099 | * intel_enable_pipe - enable a pipe, asserting requirements |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 2100 | * @crtc: crtc responsible for the pipe |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2101 | * |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 2102 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2103 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2104 | */ |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 2105 | static void intel_enable_pipe(struct intel_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2106 | { |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 2107 | struct drm_device *dev = crtc->base.dev; |
| 2108 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2109 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | 1a70a728 | 2015-10-29 21:25:50 +0200 | [diff] [blame] | 2110 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 2111 | enum pipe pch_transcoder; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2112 | i915_reg_t reg; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2113 | u32 val; |
| 2114 | |
Ville Syrjälä | 9e2ee2d | 2015-06-24 21:59:35 +0300 | [diff] [blame] | 2115 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
| 2116 | |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 2117 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 2118 | assert_cursor_disabled(dev_priv, pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 2119 | assert_sprites_disabled(dev_priv, pipe); |
| 2120 | |
Paulo Zanoni | 681e581 | 2012-12-06 11:12:38 -0200 | [diff] [blame] | 2121 | if (HAS_PCH_LPT(dev_priv->dev)) |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 2122 | pch_transcoder = TRANSCODER_A; |
| 2123 | else |
| 2124 | pch_transcoder = pipe; |
| 2125 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2126 | /* |
| 2127 | * A pipe without a PLL won't actually be able to drive bits from |
| 2128 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 2129 | * need the check. |
| 2130 | */ |
Imre Deak | 5036040 | 2015-01-16 00:55:16 -0800 | [diff] [blame] | 2131 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 2132 | if (crtc->config->has_dsi_encoder) |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 2133 | assert_dsi_pll_enabled(dev_priv); |
| 2134 | else |
| 2135 | assert_pll_enabled(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2136 | else { |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2137 | if (crtc->config->has_pch_encoder) { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2138 | /* if driving the PCH, we need FDI enabled */ |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 2139 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 2140 | assert_fdi_tx_pll_enabled(dev_priv, |
| 2141 | (enum pipe) cpu_transcoder); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2142 | } |
| 2143 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 2144 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2145 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 2146 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2147 | val = I915_READ(reg); |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 2148 | if (val & PIPECONF_ENABLE) { |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 2149 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 2150 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2151 | return; |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 2152 | } |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2153 | |
| 2154 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Paulo Zanoni | 851855d | 2013-12-19 19:12:29 -0200 | [diff] [blame] | 2155 | POSTING_READ(reg); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2156 | } |
| 2157 | |
| 2158 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 2159 | * intel_disable_pipe - disable a pipe, asserting requirements |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2160 | * @crtc: crtc whose pipes is to be disabled |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2161 | * |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2162 | * Disable the pipe of @crtc, making sure that various hardware |
| 2163 | * specific requirements are met, if applicable, e.g. plane |
| 2164 | * disabled, panel fitter off, etc. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2165 | * |
| 2166 | * Will wait until the pipe has shut down before returning. |
| 2167 | */ |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2168 | static void intel_disable_pipe(struct intel_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2169 | { |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2171 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 2172 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2173 | i915_reg_t reg; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2174 | u32 val; |
| 2175 | |
Ville Syrjälä | 9e2ee2d | 2015-06-24 21:59:35 +0300 | [diff] [blame] | 2176 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
| 2177 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2178 | /* |
| 2179 | * Make sure planes won't keep trying to pump pixels to us, |
| 2180 | * or we might hang the display. |
| 2181 | */ |
| 2182 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 2183 | assert_cursor_disabled(dev_priv, pipe); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 2184 | assert_sprites_disabled(dev_priv, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2185 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 2186 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2187 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 2188 | if ((val & PIPECONF_ENABLE) == 0) |
| 2189 | return; |
| 2190 | |
Ville Syrjälä | 67adc64 | 2014-08-15 01:21:57 +0300 | [diff] [blame] | 2191 | /* |
| 2192 | * Double wide has implications for planes |
| 2193 | * so best keep it disabled when not needed. |
| 2194 | */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2195 | if (crtc->config->double_wide) |
Ville Syrjälä | 67adc64 | 2014-08-15 01:21:57 +0300 | [diff] [blame] | 2196 | val &= ~PIPECONF_DOUBLE_WIDE; |
| 2197 | |
| 2198 | /* Don't disable pipe or pipe PLLs if needed */ |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 2199 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
| 2200 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Ville Syrjälä | 67adc64 | 2014-08-15 01:21:57 +0300 | [diff] [blame] | 2201 | val &= ~PIPECONF_ENABLE; |
| 2202 | |
| 2203 | I915_WRITE(reg, val); |
| 2204 | if ((val & PIPECONF_ENABLE) == 0) |
| 2205 | intel_wait_for_pipe_off(crtc); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2206 | } |
| 2207 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 2208 | static bool need_vtd_wa(struct drm_device *dev) |
| 2209 | { |
| 2210 | #ifdef CONFIG_INTEL_IOMMU |
| 2211 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
| 2212 | return true; |
| 2213 | #endif |
| 2214 | return false; |
| 2215 | } |
| 2216 | |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2217 | unsigned int |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2218 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
Tvrtko Ursulin | fe47ea0 | 2015-09-21 10:45:32 +0100 | [diff] [blame] | 2219 | uint64_t fb_format_modifier, unsigned int plane) |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 2220 | { |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2221 | unsigned int tile_height; |
| 2222 | uint32_t pixel_bytes; |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 2223 | |
Damien Lespiau | b5d0e9b | 2015-02-27 11:15:19 +0000 | [diff] [blame] | 2224 | switch (fb_format_modifier) { |
| 2225 | case DRM_FORMAT_MOD_NONE: |
| 2226 | tile_height = 1; |
| 2227 | break; |
| 2228 | case I915_FORMAT_MOD_X_TILED: |
| 2229 | tile_height = IS_GEN2(dev) ? 16 : 8; |
| 2230 | break; |
| 2231 | case I915_FORMAT_MOD_Y_TILED: |
| 2232 | tile_height = 32; |
| 2233 | break; |
| 2234 | case I915_FORMAT_MOD_Yf_TILED: |
Tvrtko Ursulin | fe47ea0 | 2015-09-21 10:45:32 +0100 | [diff] [blame] | 2235 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2236 | switch (pixel_bytes) { |
Damien Lespiau | b5d0e9b | 2015-02-27 11:15:19 +0000 | [diff] [blame] | 2237 | default: |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2238 | case 1: |
Damien Lespiau | b5d0e9b | 2015-02-27 11:15:19 +0000 | [diff] [blame] | 2239 | tile_height = 64; |
| 2240 | break; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2241 | case 2: |
| 2242 | case 4: |
Damien Lespiau | b5d0e9b | 2015-02-27 11:15:19 +0000 | [diff] [blame] | 2243 | tile_height = 32; |
| 2244 | break; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2245 | case 8: |
Damien Lespiau | b5d0e9b | 2015-02-27 11:15:19 +0000 | [diff] [blame] | 2246 | tile_height = 16; |
| 2247 | break; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2248 | case 16: |
Damien Lespiau | b5d0e9b | 2015-02-27 11:15:19 +0000 | [diff] [blame] | 2249 | WARN_ONCE(1, |
| 2250 | "128-bit pixels are not supported for display!"); |
| 2251 | tile_height = 16; |
| 2252 | break; |
| 2253 | } |
| 2254 | break; |
| 2255 | default: |
| 2256 | MISSING_CASE(fb_format_modifier); |
| 2257 | tile_height = 1; |
| 2258 | break; |
| 2259 | } |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 2260 | |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 2261 | return tile_height; |
| 2262 | } |
| 2263 | |
| 2264 | unsigned int |
| 2265 | intel_fb_align_height(struct drm_device *dev, unsigned int height, |
| 2266 | uint32_t pixel_format, uint64_t fb_format_modifier) |
| 2267 | { |
| 2268 | return ALIGN(height, intel_tile_height(dev, pixel_format, |
Tvrtko Ursulin | fe47ea0 | 2015-09-21 10:45:32 +0100 | [diff] [blame] | 2269 | fb_format_modifier, 0)); |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 2270 | } |
| 2271 | |
Daniel Vetter | 75c82a5 | 2015-10-14 16:51:04 +0200 | [diff] [blame] | 2272 | static void |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2273 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
| 2274 | const struct drm_plane_state *plane_state) |
| 2275 | { |
Daniel Vetter | a6d0918 | 2015-10-14 16:51:05 +0200 | [diff] [blame] | 2276 | struct intel_rotation_info *info = &view->params.rotation_info; |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2277 | unsigned int tile_height, tile_pitch; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2278 | |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2279 | *view = i915_ggtt_view_normal; |
| 2280 | |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2281 | if (!plane_state) |
Daniel Vetter | 75c82a5 | 2015-10-14 16:51:04 +0200 | [diff] [blame] | 2282 | return; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2283 | |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 2284 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
Daniel Vetter | 75c82a5 | 2015-10-14 16:51:04 +0200 | [diff] [blame] | 2285 | return; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2286 | |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 2287 | *view = i915_ggtt_view_rotated; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2288 | |
| 2289 | info->height = fb->height; |
| 2290 | info->pixel_format = fb->pixel_format; |
| 2291 | info->pitch = fb->pitches[0]; |
Tvrtko Ursulin | 89e3e14 | 2015-09-21 10:45:34 +0100 | [diff] [blame] | 2292 | info->uv_offset = fb->offsets[1]; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2293 | info->fb_modifier = fb->modifier[0]; |
| 2294 | |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2295 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
Tvrtko Ursulin | fe47ea0 | 2015-09-21 10:45:32 +0100 | [diff] [blame] | 2296 | fb->modifier[0], 0); |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2297 | tile_pitch = PAGE_SIZE / tile_height; |
| 2298 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
| 2299 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
| 2300 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; |
| 2301 | |
Tvrtko Ursulin | 89e3e14 | 2015-09-21 10:45:34 +0100 | [diff] [blame] | 2302 | if (info->pixel_format == DRM_FORMAT_NV12) { |
| 2303 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
| 2304 | fb->modifier[0], 1); |
| 2305 | tile_pitch = PAGE_SIZE / tile_height; |
| 2306 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
| 2307 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, |
| 2308 | tile_height); |
| 2309 | info->size_uv = info->width_pages_uv * info->height_pages_uv * |
| 2310 | PAGE_SIZE; |
| 2311 | } |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2312 | } |
| 2313 | |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2314 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
| 2315 | { |
| 2316 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 2317 | return 256 * 1024; |
Ville Syrjälä | 985b8bb | 2015-06-11 16:31:15 +0300 | [diff] [blame] | 2318 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2319 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2320 | return 128 * 1024; |
| 2321 | else if (INTEL_INFO(dev_priv)->gen >= 4) |
| 2322 | return 4 * 1024; |
| 2323 | else |
Ville Syrjälä | 44c5905 | 2015-06-11 16:31:16 +0300 | [diff] [blame] | 2324 | return 0; |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2325 | } |
| 2326 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 2327 | int |
Tvrtko Ursulin | 850c4cd | 2014-10-30 16:39:38 +0000 | [diff] [blame] | 2328 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
| 2329 | struct drm_framebuffer *fb, |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 2330 | const struct drm_plane_state *plane_state) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2331 | { |
Tvrtko Ursulin | 850c4cd | 2014-10-30 16:39:38 +0000 | [diff] [blame] | 2332 | struct drm_device *dev = fb->dev; |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 850c4cd | 2014-10-30 16:39:38 +0000 | [diff] [blame] | 2334 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2335 | struct i915_ggtt_view view; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2336 | u32 alignment; |
| 2337 | int ret; |
| 2338 | |
Matt Roper | ebcdd39 | 2014-07-09 16:22:11 -0700 | [diff] [blame] | 2339 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2340 | |
Tvrtko Ursulin | 7b911ad | 2015-02-10 17:16:15 +0000 | [diff] [blame] | 2341 | switch (fb->modifier[0]) { |
| 2342 | case DRM_FORMAT_MOD_NONE: |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2343 | alignment = intel_linear_alignment(dev_priv); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2344 | break; |
Tvrtko Ursulin | 7b911ad | 2015-02-10 17:16:15 +0000 | [diff] [blame] | 2345 | case I915_FORMAT_MOD_X_TILED: |
Damien Lespiau | 1fada4c | 2013-07-03 21:06:02 +0100 | [diff] [blame] | 2346 | if (INTEL_INFO(dev)->gen >= 9) |
| 2347 | alignment = 256 * 1024; |
| 2348 | else { |
| 2349 | /* pin() will align the object as required by fence */ |
| 2350 | alignment = 0; |
| 2351 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2352 | break; |
Tvrtko Ursulin | 7b911ad | 2015-02-10 17:16:15 +0000 | [diff] [blame] | 2353 | case I915_FORMAT_MOD_Y_TILED: |
Damien Lespiau | 1327b9a | 2015-02-27 11:15:20 +0000 | [diff] [blame] | 2354 | case I915_FORMAT_MOD_Yf_TILED: |
| 2355 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, |
| 2356 | "Y tiling bo slipped through, driver bug!\n")) |
| 2357 | return -EINVAL; |
| 2358 | alignment = 1 * 1024 * 1024; |
| 2359 | break; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2360 | default: |
Tvrtko Ursulin | 7b911ad | 2015-02-10 17:16:15 +0000 | [diff] [blame] | 2361 | MISSING_CASE(fb->modifier[0]); |
| 2362 | return -EINVAL; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2363 | } |
| 2364 | |
Daniel Vetter | 75c82a5 | 2015-10-14 16:51:04 +0200 | [diff] [blame] | 2365 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2366 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 2367 | /* Note that the w/a also requires 64 PTE of padding following the |
| 2368 | * bo. We currently fill all unused PTE with the shadow page and so |
| 2369 | * we should always have valid PTE following the scanout preventing |
| 2370 | * the VT-d warning. |
| 2371 | */ |
| 2372 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
| 2373 | alignment = 256 * 1024; |
| 2374 | |
Paulo Zanoni | d6dd684 | 2014-08-15 15:59:32 -0300 | [diff] [blame] | 2375 | /* |
| 2376 | * Global gtt pte registers are special registers which actually forward |
| 2377 | * writes to a chunk of system memory. Which means that there is no risk |
| 2378 | * that the register values disappear as soon as we call |
| 2379 | * intel_runtime_pm_put(), so it is correct to wrap only the |
| 2380 | * pin/unpin/fence and not more. |
| 2381 | */ |
| 2382 | intel_runtime_pm_get(dev_priv); |
| 2383 | |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 2384 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
| 2385 | &view); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2386 | if (ret) |
Maarten Lankhorst | b26a6b3 | 2015-09-23 13:27:09 +0200 | [diff] [blame] | 2387 | goto err_pm; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2388 | |
| 2389 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 2390 | * fence, whereas 965+ only requires a fence if using |
| 2391 | * framebuffer compression. For simplicity, we always install |
| 2392 | * a fence as the cost is not that onerous. |
| 2393 | */ |
Vivek Kasireddy | 9807216 | 2015-10-29 18:54:38 -0700 | [diff] [blame] | 2394 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
| 2395 | ret = i915_gem_object_get_fence(obj); |
| 2396 | if (ret == -EDEADLK) { |
| 2397 | /* |
| 2398 | * -EDEADLK means there are no free fences |
| 2399 | * no pending flips. |
| 2400 | * |
| 2401 | * This is propagated to atomic, but it uses |
| 2402 | * -EDEADLK to force a locking recovery, so |
| 2403 | * change the returned error to -EBUSY. |
| 2404 | */ |
| 2405 | ret = -EBUSY; |
| 2406 | goto err_unpin; |
| 2407 | } else if (ret) |
| 2408 | goto err_unpin; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2409 | |
Vivek Kasireddy | 9807216 | 2015-10-29 18:54:38 -0700 | [diff] [blame] | 2410 | i915_gem_object_pin_fence(obj); |
| 2411 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2412 | |
Paulo Zanoni | d6dd684 | 2014-08-15 15:59:32 -0300 | [diff] [blame] | 2413 | intel_runtime_pm_put(dev_priv); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2414 | return 0; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2415 | |
| 2416 | err_unpin: |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
Maarten Lankhorst | b26a6b3 | 2015-09-23 13:27:09 +0200 | [diff] [blame] | 2418 | err_pm: |
Paulo Zanoni | d6dd684 | 2014-08-15 15:59:32 -0300 | [diff] [blame] | 2419 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2420 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2421 | } |
| 2422 | |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 2423 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
| 2424 | const struct drm_plane_state *plane_state) |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2425 | { |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 2426 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2427 | struct i915_ggtt_view view; |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 2428 | |
Matt Roper | ebcdd39 | 2014-07-09 16:22:11 -0700 | [diff] [blame] | 2429 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
| 2430 | |
Daniel Vetter | 75c82a5 | 2015-10-14 16:51:04 +0200 | [diff] [blame] | 2431 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2432 | |
Vivek Kasireddy | 9807216 | 2015-10-29 18:54:38 -0700 | [diff] [blame] | 2433 | if (view.type == I915_GGTT_VIEW_NORMAL) |
| 2434 | i915_gem_object_unpin_fence(obj); |
| 2435 | |
Tvrtko Ursulin | f64b98c | 2015-03-23 11:10:35 +0000 | [diff] [blame] | 2436 | i915_gem_object_unpin_from_display_plane(obj, &view); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2437 | } |
| 2438 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2439 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
| 2440 | * is assumed to be a power-of-two. */ |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2441 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
| 2442 | int *x, int *y, |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2443 | unsigned int tiling_mode, |
| 2444 | unsigned int cpp, |
| 2445 | unsigned int pitch) |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2446 | { |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2447 | if (tiling_mode != I915_TILING_NONE) { |
| 2448 | unsigned int tile_rows, tiles; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2449 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2450 | tile_rows = *y / 8; |
| 2451 | *y %= 8; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2452 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2453 | tiles = *x / (512/cpp); |
| 2454 | *x %= 512/cpp; |
| 2455 | |
| 2456 | return tile_rows * pitch * 8 + tiles * 4096; |
| 2457 | } else { |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2458 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2459 | unsigned int offset; |
| 2460 | |
| 2461 | offset = *y * pitch + *x * cpp; |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2462 | *y = (offset & alignment) / pitch; |
| 2463 | *x = ((offset & alignment) - *y * pitch) / cpp; |
| 2464 | return offset & ~alignment; |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2465 | } |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2466 | } |
| 2467 | |
Damien Lespiau | b35d63f | 2015-01-20 12:51:50 +0000 | [diff] [blame] | 2468 | static int i9xx_format_to_fourcc(int format) |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2469 | { |
| 2470 | switch (format) { |
| 2471 | case DISPPLANE_8BPP: |
| 2472 | return DRM_FORMAT_C8; |
| 2473 | case DISPPLANE_BGRX555: |
| 2474 | return DRM_FORMAT_XRGB1555; |
| 2475 | case DISPPLANE_BGRX565: |
| 2476 | return DRM_FORMAT_RGB565; |
| 2477 | default: |
| 2478 | case DISPPLANE_BGRX888: |
| 2479 | return DRM_FORMAT_XRGB8888; |
| 2480 | case DISPPLANE_RGBX888: |
| 2481 | return DRM_FORMAT_XBGR8888; |
| 2482 | case DISPPLANE_BGRX101010: |
| 2483 | return DRM_FORMAT_XRGB2101010; |
| 2484 | case DISPPLANE_RGBX101010: |
| 2485 | return DRM_FORMAT_XBGR2101010; |
| 2486 | } |
| 2487 | } |
| 2488 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 2489 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
| 2490 | { |
| 2491 | switch (format) { |
| 2492 | case PLANE_CTL_FORMAT_RGB_565: |
| 2493 | return DRM_FORMAT_RGB565; |
| 2494 | default: |
| 2495 | case PLANE_CTL_FORMAT_XRGB_8888: |
| 2496 | if (rgb_order) { |
| 2497 | if (alpha) |
| 2498 | return DRM_FORMAT_ABGR8888; |
| 2499 | else |
| 2500 | return DRM_FORMAT_XBGR8888; |
| 2501 | } else { |
| 2502 | if (alpha) |
| 2503 | return DRM_FORMAT_ARGB8888; |
| 2504 | else |
| 2505 | return DRM_FORMAT_XRGB8888; |
| 2506 | } |
| 2507 | case PLANE_CTL_FORMAT_XRGB_2101010: |
| 2508 | if (rgb_order) |
| 2509 | return DRM_FORMAT_XBGR2101010; |
| 2510 | else |
| 2511 | return DRM_FORMAT_XRGB2101010; |
| 2512 | } |
| 2513 | } |
| 2514 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 2515 | static bool |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2516 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
| 2517 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2518 | { |
| 2519 | struct drm_device *dev = crtc->base.dev; |
Paulo Zanoni | 3badb49 | 2015-09-23 12:52:23 -0300 | [diff] [blame] | 2520 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2521 | struct drm_i915_gem_object *obj = NULL; |
| 2522 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 2523 | struct drm_framebuffer *fb = &plane_config->fb->base; |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 2524 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
| 2525 | u32 size_aligned = round_up(plane_config->base + plane_config->size, |
| 2526 | PAGE_SIZE); |
| 2527 | |
| 2528 | size_aligned -= base_aligned; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2529 | |
Chris Wilson | ff2652e | 2014-03-10 08:07:02 +0000 | [diff] [blame] | 2530 | if (plane_config->size == 0) |
| 2531 | return false; |
| 2532 | |
Paulo Zanoni | 3badb49 | 2015-09-23 12:52:23 -0300 | [diff] [blame] | 2533 | /* If the FB is too big, just don't use it since fbdev is not very |
| 2534 | * important and we should probably use that space with FBC or other |
| 2535 | * features. */ |
| 2536 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) |
| 2537 | return false; |
| 2538 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 2539 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
| 2540 | base_aligned, |
| 2541 | base_aligned, |
| 2542 | size_aligned); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2543 | if (!obj) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2544 | return false; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2545 | |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 2546 | obj->tiling_mode = plane_config->tiling; |
| 2547 | if (obj->tiling_mode == I915_TILING_X) |
Damien Lespiau | 6bf129d | 2015-02-05 17:22:16 +0000 | [diff] [blame] | 2548 | obj->stride = fb->pitches[0]; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2549 | |
Damien Lespiau | 6bf129d | 2015-02-05 17:22:16 +0000 | [diff] [blame] | 2550 | mode_cmd.pixel_format = fb->pixel_format; |
| 2551 | mode_cmd.width = fb->width; |
| 2552 | mode_cmd.height = fb->height; |
| 2553 | mode_cmd.pitches[0] = fb->pitches[0]; |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 2554 | mode_cmd.modifier[0] = fb->modifier[0]; |
| 2555 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2556 | |
| 2557 | mutex_lock(&dev->struct_mutex); |
Damien Lespiau | 6bf129d | 2015-02-05 17:22:16 +0000 | [diff] [blame] | 2558 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2559 | &mode_cmd, obj)) { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2560 | DRM_DEBUG_KMS("intel fb init failed\n"); |
| 2561 | goto out_unref_obj; |
| 2562 | } |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2563 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2564 | |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2565 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2566 | return true; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2567 | |
| 2568 | out_unref_obj: |
| 2569 | drm_gem_object_unreference(&obj->base); |
| 2570 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2571 | return false; |
| 2572 | } |
| 2573 | |
Matt Roper | afd65eb | 2015-02-03 13:10:04 -0800 | [diff] [blame] | 2574 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
| 2575 | static void |
| 2576 | update_state_fb(struct drm_plane *plane) |
| 2577 | { |
| 2578 | if (plane->fb == plane->state->fb) |
| 2579 | return; |
| 2580 | |
| 2581 | if (plane->state->fb) |
| 2582 | drm_framebuffer_unreference(plane->state->fb); |
| 2583 | plane->state->fb = plane->fb; |
| 2584 | if (plane->state->fb) |
| 2585 | drm_framebuffer_reference(plane->state->fb); |
| 2586 | } |
| 2587 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 2588 | static void |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2589 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
| 2590 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2591 | { |
| 2592 | struct drm_device *dev = intel_crtc->base.dev; |
Jesse Barnes | d9ceb81 | 2014-10-09 12:57:43 -0700 | [diff] [blame] | 2593 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2594 | struct drm_crtc *c; |
| 2595 | struct intel_crtc *i; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2596 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2597 | struct drm_plane *primary = intel_crtc->base.primary; |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2598 | struct drm_plane_state *plane_state = primary->state; |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 2599 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
| 2600 | struct intel_plane *intel_plane = to_intel_plane(primary); |
Matt Roper | 0a8d8a8 | 2015-12-03 11:37:38 -0800 | [diff] [blame^] | 2601 | struct intel_plane_state *intel_state = |
| 2602 | to_intel_plane_state(plane_state); |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2603 | struct drm_framebuffer *fb; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2604 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 2605 | if (!plane_config->fb) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2606 | return; |
| 2607 | |
Daniel Vetter | f6936e2 | 2015-03-26 12:17:05 +0100 | [diff] [blame] | 2608 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2609 | fb = &plane_config->fb->base; |
| 2610 | goto valid_fb; |
Damien Lespiau | f55548b | 2015-02-05 18:30:20 +0000 | [diff] [blame] | 2611 | } |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2612 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 2613 | kfree(plane_config->fb); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2614 | |
| 2615 | /* |
| 2616 | * Failed to alloc the obj, check to see if we should share |
| 2617 | * an fb with another CRTC instead |
| 2618 | */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 2619 | for_each_crtc(dev, c) { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2620 | i = to_intel_crtc(c); |
| 2621 | |
| 2622 | if (c == &intel_crtc->base) |
| 2623 | continue; |
| 2624 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2625 | if (!i->active) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2626 | continue; |
| 2627 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2628 | fb = c->primary->fb; |
| 2629 | if (!fb) |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2630 | continue; |
| 2631 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2632 | obj = intel_fb_obj(fb); |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 2633 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2634 | drm_framebuffer_reference(fb); |
| 2635 | goto valid_fb; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2636 | } |
| 2637 | } |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2638 | |
Matt Roper | 200757f | 2015-12-03 11:37:36 -0800 | [diff] [blame] | 2639 | /* |
| 2640 | * We've failed to reconstruct the BIOS FB. Current display state |
| 2641 | * indicates that the primary plane is visible, but has a NULL FB, |
| 2642 | * which will lead to problems later if we don't fix it up. The |
| 2643 | * simplest solution is to just disable the primary plane now and |
| 2644 | * pretend the BIOS never had it enabled. |
| 2645 | */ |
| 2646 | to_intel_plane_state(plane_state)->visible = false; |
| 2647 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
| 2648 | intel_pre_disable_primary(&intel_crtc->base); |
| 2649 | intel_plane->disable_plane(primary, &intel_crtc->base); |
| 2650 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2651 | return; |
| 2652 | |
| 2653 | valid_fb: |
Ville Syrjälä | f44e265 | 2015-11-13 19:16:13 +0200 | [diff] [blame] | 2654 | plane_state->src_x = 0; |
| 2655 | plane_state->src_y = 0; |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2656 | plane_state->src_w = fb->width << 16; |
| 2657 | plane_state->src_h = fb->height << 16; |
| 2658 | |
Ville Syrjälä | f44e265 | 2015-11-13 19:16:13 +0200 | [diff] [blame] | 2659 | plane_state->crtc_x = 0; |
| 2660 | plane_state->crtc_y = 0; |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2661 | plane_state->crtc_w = fb->width; |
| 2662 | plane_state->crtc_h = fb->height; |
| 2663 | |
Matt Roper | 0a8d8a8 | 2015-12-03 11:37:38 -0800 | [diff] [blame^] | 2664 | intel_state->src.x1 = plane_state->src_x; |
| 2665 | intel_state->src.y1 = plane_state->src_y; |
| 2666 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; |
| 2667 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; |
| 2668 | intel_state->dst.x1 = plane_state->crtc_x; |
| 2669 | intel_state->dst.y1 = plane_state->crtc_y; |
| 2670 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; |
| 2671 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; |
| 2672 | |
Daniel Vetter | 88595ac | 2015-03-26 12:42:24 +0100 | [diff] [blame] | 2673 | obj = intel_fb_obj(fb); |
| 2674 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2675 | dev_priv->preserve_bios_swizzle = true; |
| 2676 | |
Maarten Lankhorst | be5651f | 2015-07-13 16:30:18 +0200 | [diff] [blame] | 2677 | drm_framebuffer_reference(fb); |
| 2678 | primary->fb = primary->state->fb = fb; |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 2679 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 2680 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 2681 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2682 | } |
| 2683 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 2684 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
| 2685 | struct drm_framebuffer *fb, |
| 2686 | int x, int y) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2687 | { |
| 2688 | struct drm_device *dev = crtc->dev; |
| 2689 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 2691 | struct drm_plane *primary = crtc->primary; |
| 2692 | bool visible = to_intel_plane_state(primary->state)->visible; |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame] | 2693 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2694 | int plane = intel_crtc->plane; |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2695 | unsigned long linear_offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2696 | u32 dspcntr; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2697 | i915_reg_t reg = DSPCNTR(plane); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2698 | int pixel_size; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2699 | |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 2700 | if (!visible || !fb) { |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2701 | I915_WRITE(reg, 0); |
| 2702 | if (INTEL_INFO(dev)->gen >= 4) |
| 2703 | I915_WRITE(DSPSURF(plane), 0); |
| 2704 | else |
| 2705 | I915_WRITE(DSPADDR(plane), 0); |
| 2706 | POSTING_READ(reg); |
| 2707 | return; |
| 2708 | } |
| 2709 | |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame] | 2710 | obj = intel_fb_obj(fb); |
| 2711 | if (WARN_ON(obj == NULL)) |
| 2712 | return; |
| 2713 | |
| 2714 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2715 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2716 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 2717 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2718 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2719 | |
| 2720 | if (INTEL_INFO(dev)->gen < 4) { |
| 2721 | if (intel_crtc->pipe == PIPE_B) |
| 2722 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 2723 | |
| 2724 | /* pipesrc and dspsize control the size that is scaled from, |
| 2725 | * which should always be the user's requested size. |
| 2726 | */ |
| 2727 | I915_WRITE(DSPSIZE(plane), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2728 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
| 2729 | (intel_crtc->config->pipe_src_w - 1)); |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2730 | I915_WRITE(DSPPOS(plane), 0); |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2731 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
| 2732 | I915_WRITE(PRIMSIZE(plane), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2733 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
| 2734 | (intel_crtc->config->pipe_src_w - 1)); |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 2735 | I915_WRITE(PRIMPOS(plane), 0); |
| 2736 | I915_WRITE(PRIMCNSTALPHA(plane), 0); |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2737 | } |
| 2738 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2739 | switch (fb->pixel_format) { |
| 2740 | case DRM_FORMAT_C8: |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2741 | dspcntr |= DISPPLANE_8BPP; |
| 2742 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2743 | case DRM_FORMAT_XRGB1555: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2744 | dspcntr |= DISPPLANE_BGRX555; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2745 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2746 | case DRM_FORMAT_RGB565: |
| 2747 | dspcntr |= DISPPLANE_BGRX565; |
| 2748 | break; |
| 2749 | case DRM_FORMAT_XRGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2750 | dspcntr |= DISPPLANE_BGRX888; |
| 2751 | break; |
| 2752 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2753 | dspcntr |= DISPPLANE_RGBX888; |
| 2754 | break; |
| 2755 | case DRM_FORMAT_XRGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2756 | dspcntr |= DISPPLANE_BGRX101010; |
| 2757 | break; |
| 2758 | case DRM_FORMAT_XBGR2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2759 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2760 | break; |
| 2761 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 2762 | BUG(); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2763 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2764 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2765 | if (INTEL_INFO(dev)->gen >= 4 && |
| 2766 | obj->tiling_mode != I915_TILING_NONE) |
| 2767 | dspcntr |= DISPPLANE_TILED; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2768 | |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 2769 | if (IS_G4X(dev)) |
| 2770 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2771 | |
Ville Syrjälä | b9897127 | 2014-08-27 16:51:22 +0300 | [diff] [blame] | 2772 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2773 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2774 | if (INTEL_INFO(dev)->gen >= 4) { |
| 2775 | intel_crtc->dspaddr_offset = |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2776 | intel_gen4_compute_page_offset(dev_priv, |
| 2777 | &x, &y, obj->tiling_mode, |
Ville Syrjälä | b9897127 | 2014-08-27 16:51:22 +0300 | [diff] [blame] | 2778 | pixel_size, |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2779 | fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2780 | linear_offset -= intel_crtc->dspaddr_offset; |
| 2781 | } else { |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2782 | intel_crtc->dspaddr_offset = linear_offset; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2783 | } |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2784 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 2785 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2786 | dspcntr |= DISPPLANE_ROTATE_180; |
| 2787 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2788 | x += (intel_crtc->config->pipe_src_w - 1); |
| 2789 | y += (intel_crtc->config->pipe_src_h - 1); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2790 | |
| 2791 | /* Finding the last pixel of the last line of the display |
| 2792 | data and adding to linear_offset*/ |
| 2793 | linear_offset += |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2794 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
| 2795 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2796 | } |
| 2797 | |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 2798 | intel_crtc->adjusted_x = x; |
| 2799 | intel_crtc->adjusted_y = y; |
| 2800 | |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2801 | I915_WRITE(reg, dspcntr); |
| 2802 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2803 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2804 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 2805 | I915_WRITE(DSPSURF(plane), |
| 2806 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2807 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2808 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2809 | } else |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2810 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2811 | POSTING_READ(reg); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2812 | } |
| 2813 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 2814 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
| 2815 | struct drm_framebuffer *fb, |
| 2816 | int x, int y) |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2817 | { |
| 2818 | struct drm_device *dev = crtc->dev; |
| 2819 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 2821 | struct drm_plane *primary = crtc->primary; |
| 2822 | bool visible = to_intel_plane_state(primary->state)->visible; |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame] | 2823 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2824 | int plane = intel_crtc->plane; |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2825 | unsigned long linear_offset; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2826 | u32 dspcntr; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2827 | i915_reg_t reg = DSPCNTR(plane); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2828 | int pixel_size; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2829 | |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 2830 | if (!visible || !fb) { |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2831 | I915_WRITE(reg, 0); |
| 2832 | I915_WRITE(DSPSURF(plane), 0); |
| 2833 | POSTING_READ(reg); |
| 2834 | return; |
| 2835 | } |
| 2836 | |
Ville Syrjälä | c9ba6fa | 2014-08-27 17:48:41 +0300 | [diff] [blame] | 2837 | obj = intel_fb_obj(fb); |
| 2838 | if (WARN_ON(obj == NULL)) |
| 2839 | return; |
| 2840 | |
| 2841 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2842 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2843 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 2844 | |
Ville Syrjälä | fdd508a6 | 2014-08-08 21:51:11 +0300 | [diff] [blame] | 2845 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2846 | |
| 2847 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 2848 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
| 2849 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2850 | switch (fb->pixel_format) { |
| 2851 | case DRM_FORMAT_C8: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2852 | dspcntr |= DISPPLANE_8BPP; |
| 2853 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2854 | case DRM_FORMAT_RGB565: |
| 2855 | dspcntr |= DISPPLANE_BGRX565; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2856 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2857 | case DRM_FORMAT_XRGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2858 | dspcntr |= DISPPLANE_BGRX888; |
| 2859 | break; |
| 2860 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2861 | dspcntr |= DISPPLANE_RGBX888; |
| 2862 | break; |
| 2863 | case DRM_FORMAT_XRGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2864 | dspcntr |= DISPPLANE_BGRX101010; |
| 2865 | break; |
| 2866 | case DRM_FORMAT_XBGR2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2867 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2868 | break; |
| 2869 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 2870 | BUG(); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2871 | } |
| 2872 | |
| 2873 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2874 | dspcntr |= DISPPLANE_TILED; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2875 | |
Ville Syrjälä | f45651b | 2014-08-08 21:51:10 +0300 | [diff] [blame] | 2876 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
Paulo Zanoni | 1f5d76d | 2013-08-23 19:51:28 -0300 | [diff] [blame] | 2877 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2878 | |
Ville Syrjälä | b9897127 | 2014-08-27 16:51:22 +0300 | [diff] [blame] | 2879 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2880 | intel_crtc->dspaddr_offset = |
Ville Syrjälä | 4e9a86b | 2015-06-11 16:31:14 +0300 | [diff] [blame] | 2881 | intel_gen4_compute_page_offset(dev_priv, |
| 2882 | &x, &y, obj->tiling_mode, |
Ville Syrjälä | b9897127 | 2014-08-27 16:51:22 +0300 | [diff] [blame] | 2883 | pixel_size, |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2884 | fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2885 | linear_offset -= intel_crtc->dspaddr_offset; |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 2886 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2887 | dspcntr |= DISPPLANE_ROTATE_180; |
| 2888 | |
| 2889 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2890 | x += (intel_crtc->config->pipe_src_w - 1); |
| 2891 | y += (intel_crtc->config->pipe_src_h - 1); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2892 | |
| 2893 | /* Finding the last pixel of the last line of the display |
| 2894 | data and adding to linear_offset*/ |
| 2895 | linear_offset += |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2896 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
| 2897 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2898 | } |
| 2899 | } |
| 2900 | |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 2901 | intel_crtc->adjusted_x = x; |
| 2902 | intel_crtc->adjusted_y = y; |
| 2903 | |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 2904 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2905 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2906 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 2907 | I915_WRITE(DSPSURF(plane), |
| 2908 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Paulo Zanoni | b3dc685 | 2013-11-02 21:07:33 -0700 | [diff] [blame] | 2909 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Damien Lespiau | bc1c91e | 2012-10-29 12:14:21 +0000 | [diff] [blame] | 2910 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
| 2911 | } else { |
| 2912 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2913 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
| 2914 | } |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2915 | POSTING_READ(reg); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2916 | } |
| 2917 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 2918 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
| 2919 | uint32_t pixel_format) |
| 2920 | { |
| 2921 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; |
| 2922 | |
| 2923 | /* |
| 2924 | * The stride is either expressed as a multiple of 64 bytes |
| 2925 | * chunks for linear buffers or in number of tiles for tiled |
| 2926 | * buffers. |
| 2927 | */ |
| 2928 | switch (fb_modifier) { |
| 2929 | case DRM_FORMAT_MOD_NONE: |
| 2930 | return 64; |
| 2931 | case I915_FORMAT_MOD_X_TILED: |
| 2932 | if (INTEL_INFO(dev)->gen == 2) |
| 2933 | return 128; |
| 2934 | return 512; |
| 2935 | case I915_FORMAT_MOD_Y_TILED: |
| 2936 | /* No need to check for old gens and Y tiling since this is |
| 2937 | * about the display engine and those will be blocked before |
| 2938 | * we get here. |
| 2939 | */ |
| 2940 | return 128; |
| 2941 | case I915_FORMAT_MOD_Yf_TILED: |
| 2942 | if (bits_per_pixel == 8) |
| 2943 | return 64; |
| 2944 | else |
| 2945 | return 128; |
| 2946 | default: |
| 2947 | MISSING_CASE(fb_modifier); |
| 2948 | return 64; |
| 2949 | } |
| 2950 | } |
| 2951 | |
Mika Kuoppala | 44eb0cb | 2015-10-30 13:26:15 +0200 | [diff] [blame] | 2952 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
| 2953 | struct drm_i915_gem_object *obj, |
| 2954 | unsigned int plane) |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 2955 | { |
Daniel Vetter | ce7f172 | 2015-10-14 16:51:06 +0200 | [diff] [blame] | 2956 | struct i915_ggtt_view view; |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 2957 | struct i915_vma *vma; |
Mika Kuoppala | 44eb0cb | 2015-10-30 13:26:15 +0200 | [diff] [blame] | 2958 | u64 offset; |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 2959 | |
Daniel Vetter | ce7f172 | 2015-10-14 16:51:06 +0200 | [diff] [blame] | 2960 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
| 2961 | intel_plane->base.state); |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 2962 | |
Daniel Vetter | ce7f172 | 2015-10-14 16:51:06 +0200 | [diff] [blame] | 2963 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 2964 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
Daniel Vetter | ce7f172 | 2015-10-14 16:51:06 +0200 | [diff] [blame] | 2965 | view.type)) |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 2966 | return -1; |
| 2967 | |
Mika Kuoppala | 44eb0cb | 2015-10-30 13:26:15 +0200 | [diff] [blame] | 2968 | offset = vma->node.start; |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 2969 | |
| 2970 | if (plane == 1) { |
Daniel Vetter | a6d0918 | 2015-10-14 16:51:05 +0200 | [diff] [blame] | 2971 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 2972 | PAGE_SIZE; |
| 2973 | } |
| 2974 | |
Mika Kuoppala | 44eb0cb | 2015-10-30 13:26:15 +0200 | [diff] [blame] | 2975 | WARN_ON(upper_32_bits(offset)); |
| 2976 | |
| 2977 | return lower_32_bits(offset); |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 2978 | } |
| 2979 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 2980 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
| 2981 | { |
| 2982 | struct drm_device *dev = intel_crtc->base.dev; |
| 2983 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2984 | |
| 2985 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); |
| 2986 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); |
| 2987 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 2988 | } |
| 2989 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 2990 | /* |
| 2991 | * This function detaches (aka. unbinds) unused scalers in hardware |
| 2992 | */ |
Maarten Lankhorst | 0583236 | 2015-06-15 12:33:48 +0200 | [diff] [blame] | 2993 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 2994 | { |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 2995 | struct intel_crtc_scaler_state *scaler_state; |
| 2996 | int i; |
| 2997 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 2998 | scaler_state = &intel_crtc->config->scaler_state; |
| 2999 | |
| 3000 | /* loop through and disable scalers that aren't in use */ |
| 3001 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 3002 | if (!scaler_state->scalers[i].in_use) |
| 3003 | skl_detach_scaler(intel_crtc, i); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 3004 | } |
| 3005 | } |
| 3006 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3007 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
| 3008 | { |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3009 | switch (pixel_format) { |
Damien Lespiau | d161cf7 | 2015-05-12 16:13:17 +0100 | [diff] [blame] | 3010 | case DRM_FORMAT_C8: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3011 | return PLANE_CTL_FORMAT_INDEXED; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3012 | case DRM_FORMAT_RGB565: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3013 | return PLANE_CTL_FORMAT_RGB_565; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3014 | case DRM_FORMAT_XBGR8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3015 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3016 | case DRM_FORMAT_XRGB8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3017 | return PLANE_CTL_FORMAT_XRGB_8888; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3018 | /* |
| 3019 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers |
| 3020 | * to be already pre-multiplied. We need to add a knob (or a different |
| 3021 | * DRM_FORMAT) for user-space to configure that. |
| 3022 | */ |
| 3023 | case DRM_FORMAT_ABGR8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3024 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3025 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3026 | case DRM_FORMAT_ARGB8888: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3027 | return PLANE_CTL_FORMAT_XRGB_8888 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3028 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3029 | case DRM_FORMAT_XRGB2101010: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3030 | return PLANE_CTL_FORMAT_XRGB_2101010; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3031 | case DRM_FORMAT_XBGR2101010: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3032 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3033 | case DRM_FORMAT_YUYV: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3034 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3035 | case DRM_FORMAT_YVYU: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3036 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3037 | case DRM_FORMAT_UYVY: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3038 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3039 | case DRM_FORMAT_VYUY: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3040 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3041 | default: |
Damien Lespiau | 4249eee | 2015-05-12 16:13:16 +0100 | [diff] [blame] | 3042 | MISSING_CASE(pixel_format); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3043 | } |
Damien Lespiau | 8cfcba4 | 2015-05-12 16:13:14 +0100 | [diff] [blame] | 3044 | |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3045 | return 0; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3046 | } |
| 3047 | |
| 3048 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
| 3049 | { |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3050 | switch (fb_modifier) { |
| 3051 | case DRM_FORMAT_MOD_NONE: |
| 3052 | break; |
| 3053 | case I915_FORMAT_MOD_X_TILED: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3054 | return PLANE_CTL_TILED_X; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3055 | case I915_FORMAT_MOD_Y_TILED: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3056 | return PLANE_CTL_TILED_Y; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3057 | case I915_FORMAT_MOD_Yf_TILED: |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3058 | return PLANE_CTL_TILED_YF; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3059 | default: |
| 3060 | MISSING_CASE(fb_modifier); |
| 3061 | } |
Damien Lespiau | 8cfcba4 | 2015-05-12 16:13:14 +0100 | [diff] [blame] | 3062 | |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3063 | return 0; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3064 | } |
| 3065 | |
| 3066 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
| 3067 | { |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3068 | switch (rotation) { |
| 3069 | case BIT(DRM_ROTATE_0): |
| 3070 | break; |
Sonika Jindal | 1e8df16 | 2015-05-20 13:40:48 +0530 | [diff] [blame] | 3071 | /* |
| 3072 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr |
| 3073 | * while i915 HW rotation is clockwise, thats why this swapping. |
| 3074 | */ |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3075 | case BIT(DRM_ROTATE_90): |
Sonika Jindal | 1e8df16 | 2015-05-20 13:40:48 +0530 | [diff] [blame] | 3076 | return PLANE_CTL_ROTATE_270; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3077 | case BIT(DRM_ROTATE_180): |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3078 | return PLANE_CTL_ROTATE_180; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3079 | case BIT(DRM_ROTATE_270): |
Sonika Jindal | 1e8df16 | 2015-05-20 13:40:48 +0530 | [diff] [blame] | 3080 | return PLANE_CTL_ROTATE_90; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3081 | default: |
| 3082 | MISSING_CASE(rotation); |
| 3083 | } |
| 3084 | |
Damien Lespiau | c34ce3d | 2015-05-15 15:07:02 +0100 | [diff] [blame] | 3085 | return 0; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3086 | } |
| 3087 | |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3088 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
| 3089 | struct drm_framebuffer *fb, |
| 3090 | int x, int y) |
| 3091 | { |
| 3092 | struct drm_device *dev = crtc->dev; |
| 3093 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 3095 | struct drm_plane *plane = crtc->primary; |
| 3096 | bool visible = to_intel_plane_state(plane->state)->visible; |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3097 | struct drm_i915_gem_object *obj; |
| 3098 | int pipe = intel_crtc->pipe; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3099 | u32 plane_ctl, stride_div, stride; |
| 3100 | u32 tile_height, plane_offset, plane_size; |
| 3101 | unsigned int rotation; |
| 3102 | int x_offset, y_offset; |
Mika Kuoppala | 44eb0cb | 2015-10-30 13:26:15 +0200 | [diff] [blame] | 3103 | u32 surf_addr; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3104 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
| 3105 | struct intel_plane_state *plane_state; |
| 3106 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; |
| 3107 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; |
| 3108 | int scaler_id = -1; |
| 3109 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3110 | plane_state = to_intel_plane_state(plane->state); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3111 | |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 3112 | if (!visible || !fb) { |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3113 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
| 3114 | I915_WRITE(PLANE_SURF(pipe, 0), 0); |
| 3115 | POSTING_READ(PLANE_CTL(pipe, 0)); |
| 3116 | return; |
| 3117 | } |
| 3118 | |
| 3119 | plane_ctl = PLANE_CTL_ENABLE | |
| 3120 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
| 3121 | PLANE_CTL_PIPE_CSC_ENABLE; |
| 3122 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3123 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
| 3124 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3125 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3126 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3127 | rotation = plane->state->rotation; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3128 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3129 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 3130 | obj = intel_fb_obj(fb); |
| 3131 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
| 3132 | fb->pixel_format); |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 3133 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3134 | |
Paulo Zanoni | a42e5a2 | 2015-09-30 17:05:43 -0300 | [diff] [blame] | 3135 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3136 | |
Paulo Zanoni | a42e5a2 | 2015-09-30 17:05:43 -0300 | [diff] [blame] | 3137 | scaler_id = plane_state->scaler_id; |
| 3138 | src_x = plane_state->src.x1 >> 16; |
| 3139 | src_y = plane_state->src.y1 >> 16; |
| 3140 | src_w = drm_rect_width(&plane_state->src) >> 16; |
| 3141 | src_h = drm_rect_height(&plane_state->src) >> 16; |
| 3142 | dst_x = plane_state->dst.x1; |
| 3143 | dst_y = plane_state->dst.y1; |
| 3144 | dst_w = drm_rect_width(&plane_state->dst); |
| 3145 | dst_h = drm_rect_height(&plane_state->dst); |
| 3146 | |
| 3147 | WARN_ON(x != src_x || y != src_y); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3148 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3149 | if (intel_rotation_90_or_270(rotation)) { |
| 3150 | /* stride = Surface height in tiles */ |
Chandra Konduru | 2614f17 | 2015-05-08 20:22:46 -0700 | [diff] [blame] | 3151 | tile_height = intel_tile_height(dev, fb->pixel_format, |
Tvrtko Ursulin | fe47ea0 | 2015-09-21 10:45:32 +0100 | [diff] [blame] | 3152 | fb->modifier[0], 0); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3153 | stride = DIV_ROUND_UP(fb->height, tile_height); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3154 | x_offset = stride * tile_height - y - src_h; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3155 | y_offset = x; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3156 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3157 | } else { |
| 3158 | stride = fb->pitches[0] / stride_div; |
| 3159 | x_offset = x; |
| 3160 | y_offset = y; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3161 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3162 | } |
| 3163 | plane_offset = y_offset << 16 | x_offset; |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 3164 | |
Paulo Zanoni | 2db3366 | 2015-09-14 15:20:03 -0300 | [diff] [blame] | 3165 | intel_crtc->adjusted_x = x_offset; |
| 3166 | intel_crtc->adjusted_y = y_offset; |
| 3167 | |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3168 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 3169 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
| 3170 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); |
| 3171 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 3172 | |
| 3173 | if (scaler_id >= 0) { |
| 3174 | uint32_t ps_ctrl = 0; |
| 3175 | |
| 3176 | WARN_ON(!dst_w || !dst_h); |
| 3177 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | |
| 3178 | crtc_state->scaler_state.scalers[scaler_id].mode; |
| 3179 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
| 3180 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
| 3181 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); |
| 3182 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); |
| 3183 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
| 3184 | } else { |
| 3185 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); |
| 3186 | } |
| 3187 | |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 3188 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
Damien Lespiau | 70d21f0 | 2013-07-03 21:06:04 +0100 | [diff] [blame] | 3189 | |
| 3190 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 3191 | } |
| 3192 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3193 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 3194 | static int |
| 3195 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 3196 | int x, int y, enum mode_set_atomic state) |
| 3197 | { |
| 3198 | struct drm_device *dev = crtc->dev; |
| 3199 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 3200 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 3201 | if (dev_priv->fbc.deactivate) |
| 3202 | dev_priv->fbc.deactivate(dev_priv); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3203 | |
Daniel Vetter | 29b9bde | 2014-04-24 23:55:01 +0200 | [diff] [blame] | 3204 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
| 3205 | |
| 3206 | return 0; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 3207 | } |
| 3208 | |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3209 | static void intel_complete_page_flips(struct drm_device *dev) |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3210 | { |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3211 | struct drm_crtc *crtc; |
| 3212 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 3213 | for_each_crtc(dev, crtc) { |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3215 | enum plane plane = intel_crtc->plane; |
| 3216 | |
| 3217 | intel_prepare_page_flip(dev, plane); |
| 3218 | intel_finish_page_flip_plane(dev, plane); |
| 3219 | } |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3220 | } |
| 3221 | |
| 3222 | static void intel_update_primary_planes(struct drm_device *dev) |
| 3223 | { |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3224 | struct drm_crtc *crtc; |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3225 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 3226 | for_each_crtc(dev, crtc) { |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3227 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
| 3228 | struct intel_plane_state *plane_state; |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3229 | |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3230 | drm_modeset_lock_crtc(crtc, &plane->base); |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3231 | plane_state = to_intel_plane_state(plane->base.state); |
| 3232 | |
Maarten Lankhorst | f029ee8 | 2015-09-23 16:29:37 +0200 | [diff] [blame] | 3233 | if (crtc->state->active && plane_state->base.fb) |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3234 | plane->commit_plane(&plane->base, plane_state); |
| 3235 | |
| 3236 | drm_modeset_unlock_crtc(crtc); |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 3237 | } |
| 3238 | } |
| 3239 | |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3240 | void intel_prepare_reset(struct drm_device *dev) |
| 3241 | { |
| 3242 | /* no reset support for gen2 */ |
| 3243 | if (IS_GEN2(dev)) |
| 3244 | return; |
| 3245 | |
| 3246 | /* reset doesn't touch the display */ |
| 3247 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 3248 | return; |
| 3249 | |
| 3250 | drm_modeset_lock_all(dev); |
Ville Syrjälä | f98ce92 | 2014-11-21 21:54:30 +0200 | [diff] [blame] | 3251 | /* |
| 3252 | * Disabling the crtcs gracefully seems nicer. Also the |
| 3253 | * g33 docs say we should at least disable all the planes. |
| 3254 | */ |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 3255 | intel_display_suspend(dev); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3256 | } |
| 3257 | |
| 3258 | void intel_finish_reset(struct drm_device *dev) |
| 3259 | { |
| 3260 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3261 | |
| 3262 | /* |
| 3263 | * Flips in the rings will be nuked by the reset, |
| 3264 | * so complete all pending flips so that user space |
| 3265 | * will get its events and not get stuck. |
| 3266 | */ |
| 3267 | intel_complete_page_flips(dev); |
| 3268 | |
| 3269 | /* no reset support for gen2 */ |
| 3270 | if (IS_GEN2(dev)) |
| 3271 | return; |
| 3272 | |
| 3273 | /* reset doesn't touch the display */ |
| 3274 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { |
| 3275 | /* |
| 3276 | * Flips in the rings have been nuked by the reset, |
| 3277 | * so update the base address of all primary |
| 3278 | * planes to the the last fb to make sure we're |
| 3279 | * showing the correct fb after a reset. |
Maarten Lankhorst | 11c22da | 2015-09-10 16:07:58 +0200 | [diff] [blame] | 3280 | * |
| 3281 | * FIXME: Atomic will make this obsolete since we won't schedule |
| 3282 | * CS-based flips (which might get lost in gpu resets) any more. |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3283 | */ |
| 3284 | intel_update_primary_planes(dev); |
| 3285 | return; |
| 3286 | } |
| 3287 | |
| 3288 | /* |
| 3289 | * The display has been reset as well, |
| 3290 | * so need a full re-initialization. |
| 3291 | */ |
| 3292 | intel_runtime_pm_disable_interrupts(dev_priv); |
| 3293 | intel_runtime_pm_enable_interrupts(dev_priv); |
| 3294 | |
| 3295 | intel_modeset_init_hw(dev); |
| 3296 | |
| 3297 | spin_lock_irq(&dev_priv->irq_lock); |
| 3298 | if (dev_priv->display.hpd_irq_setup) |
| 3299 | dev_priv->display.hpd_irq_setup(dev); |
| 3300 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3301 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 3302 | intel_display_resume(dev); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame] | 3303 | |
| 3304 | intel_hpd_init(dev_priv); |
| 3305 | |
| 3306 | drm_modeset_unlock_all(dev); |
| 3307 | } |
| 3308 | |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 3309 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
| 3310 | { |
| 3311 | struct drm_device *dev = crtc->dev; |
| 3312 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 3314 | bool pending; |
| 3315 | |
| 3316 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
| 3317 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 3318 | return false; |
| 3319 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 3320 | spin_lock_irq(&dev->event_lock); |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 3321 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 3322 | spin_unlock_irq(&dev->event_lock); |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 3323 | |
| 3324 | return pending; |
| 3325 | } |
| 3326 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3327 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
| 3328 | struct intel_crtc_state *old_crtc_state) |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3329 | { |
| 3330 | struct drm_device *dev = crtc->base.dev; |
| 3331 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3332 | struct intel_crtc_state *pipe_config = |
| 3333 | to_intel_crtc_state(crtc->base.state); |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3334 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3335 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
| 3336 | crtc->base.mode = crtc->base.state->mode; |
| 3337 | |
| 3338 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", |
| 3339 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, |
| 3340 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3341 | |
Maarten Lankhorst | 44522d8 | 2015-08-27 15:44:02 +0200 | [diff] [blame] | 3342 | if (HAS_DDI(dev)) |
| 3343 | intel_set_pipe_csc(&crtc->base); |
| 3344 | |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3345 | /* |
| 3346 | * Update pipe size and adjust fitter if needed: the reason for this is |
| 3347 | * that in compute_mode_changes we check the native mode (not the pfit |
| 3348 | * mode) to see if we can flip rather than do a full mode set. In the |
| 3349 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
| 3350 | * pfit state, we'll end up with a big fb scanned out into the wrong |
| 3351 | * sized surface. |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3352 | */ |
| 3353 | |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3354 | I915_WRITE(PIPESRC(crtc->pipe), |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 3355 | ((pipe_config->pipe_src_w - 1) << 16) | |
| 3356 | (pipe_config->pipe_src_h - 1)); |
| 3357 | |
| 3358 | /* on skylake this is done by detaching scalers */ |
| 3359 | if (INTEL_INFO(dev)->gen >= 9) { |
| 3360 | skl_detach_scalers(crtc); |
| 3361 | |
| 3362 | if (pipe_config->pch_pfit.enabled) |
| 3363 | skylake_pfit_enable(crtc); |
| 3364 | } else if (HAS_PCH_SPLIT(dev)) { |
| 3365 | if (pipe_config->pch_pfit.enabled) |
| 3366 | ironlake_pfit_enable(crtc); |
| 3367 | else if (old_crtc_state->pch_pfit.enabled) |
| 3368 | ironlake_pfit_disable(crtc, true); |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3369 | } |
Gustavo Padovan | e30e8f7 | 2014-09-10 12:04:17 -0300 | [diff] [blame] | 3370 | } |
| 3371 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3372 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 3373 | { |
| 3374 | struct drm_device *dev = crtc->dev; |
| 3375 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3377 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3378 | i915_reg_t reg; |
| 3379 | u32 temp; |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3380 | |
| 3381 | /* enable normal train */ |
| 3382 | reg = FDI_TX_CTL(pipe); |
| 3383 | temp = I915_READ(reg); |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 3384 | if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3385 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 3386 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 3387 | } else { |
| 3388 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3389 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3390 | } |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3391 | I915_WRITE(reg, temp); |
| 3392 | |
| 3393 | reg = FDI_RX_CTL(pipe); |
| 3394 | temp = I915_READ(reg); |
| 3395 | if (HAS_PCH_CPT(dev)) { |
| 3396 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3397 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 3398 | } else { |
| 3399 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3400 | temp |= FDI_LINK_TRAIN_NONE; |
| 3401 | } |
| 3402 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 3403 | |
| 3404 | /* wait one idle pattern time */ |
| 3405 | POSTING_READ(reg); |
| 3406 | udelay(1000); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3407 | |
| 3408 | /* IVB wants error correction enabled */ |
| 3409 | if (IS_IVYBRIDGE(dev)) |
| 3410 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 3411 | FDI_FE_ERRC_ENABLE); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3412 | } |
| 3413 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3414 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 3415 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 3416 | { |
| 3417 | struct drm_device *dev = crtc->dev; |
| 3418 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3419 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3420 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3421 | i915_reg_t reg; |
| 3422 | u32 temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3423 | |
Ville Syrjälä | 1c8562f | 2014-04-25 22:12:07 +0300 | [diff] [blame] | 3424 | /* FDI needs bits from pipe first */ |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3425 | assert_pipe_enabled(dev_priv, pipe); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3426 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3427 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3428 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3429 | reg = FDI_RX_IMR(pipe); |
| 3430 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3431 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3432 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3433 | I915_WRITE(reg, temp); |
| 3434 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3435 | udelay(150); |
| 3436 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3437 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3438 | reg = FDI_TX_CTL(pipe); |
| 3439 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3440 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3441 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3442 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3443 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3444 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3445 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3446 | reg = FDI_RX_CTL(pipe); |
| 3447 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3448 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3449 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3450 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3451 | |
| 3452 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3453 | udelay(150); |
| 3454 | |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 3455 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
Daniel Vetter | 8f5718a | 2012-10-31 22:52:28 +0100 | [diff] [blame] | 3456 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 3457 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 3458 | FDI_RX_PHASE_SYNC_POINTER_EN); |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 3459 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3460 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3461 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3462 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3463 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3464 | |
| 3465 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 3466 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3467 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3468 | break; |
| 3469 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3470 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3471 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3472 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3473 | |
| 3474 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3475 | reg = FDI_TX_CTL(pipe); |
| 3476 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3477 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3478 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3479 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3480 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3481 | reg = FDI_RX_CTL(pipe); |
| 3482 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3483 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3484 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3485 | I915_WRITE(reg, temp); |
| 3486 | |
| 3487 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3488 | udelay(150); |
| 3489 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3490 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3491 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3492 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3493 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3494 | |
| 3495 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3496 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3497 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3498 | break; |
| 3499 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3500 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3501 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3502 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3503 | |
| 3504 | DRM_DEBUG_KMS("FDI train done\n"); |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 3505 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3506 | } |
| 3507 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3508 | static const int snb_b_fdi_train_param[] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3509 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 3510 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 3511 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 3512 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 3513 | }; |
| 3514 | |
| 3515 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 3516 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 3517 | { |
| 3518 | struct drm_device *dev = crtc->dev; |
| 3519 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3521 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3522 | i915_reg_t reg; |
| 3523 | u32 temp, i, retry; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3524 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3525 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3526 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3527 | reg = FDI_RX_IMR(pipe); |
| 3528 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3529 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3530 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3531 | I915_WRITE(reg, temp); |
| 3532 | |
| 3533 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 3534 | udelay(150); |
| 3535 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3536 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3537 | reg = FDI_TX_CTL(pipe); |
| 3538 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3539 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3540 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3541 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3542 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3544 | /* SNB-B */ |
| 3545 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3546 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3547 | |
Daniel Vetter | d74cf32 | 2012-10-26 10:58:13 +0200 | [diff] [blame] | 3548 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3549 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3550 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3551 | reg = FDI_RX_CTL(pipe); |
| 3552 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3553 | if (HAS_PCH_CPT(dev)) { |
| 3554 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3555 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3556 | } else { |
| 3557 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3558 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3559 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3560 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3561 | |
| 3562 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3563 | udelay(150); |
| 3564 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3565 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3566 | reg = FDI_TX_CTL(pipe); |
| 3567 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3568 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3569 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3570 | I915_WRITE(reg, temp); |
| 3571 | |
| 3572 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3573 | udelay(500); |
| 3574 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3575 | for (retry = 0; retry < 5; retry++) { |
| 3576 | reg = FDI_RX_IIR(pipe); |
| 3577 | temp = I915_READ(reg); |
| 3578 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3579 | if (temp & FDI_RX_BIT_LOCK) { |
| 3580 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3581 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 3582 | break; |
| 3583 | } |
| 3584 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3585 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3586 | if (retry < 5) |
| 3587 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3588 | } |
| 3589 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3590 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3591 | |
| 3592 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3593 | reg = FDI_TX_CTL(pipe); |
| 3594 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3595 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3596 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3597 | if (IS_GEN6(dev)) { |
| 3598 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3599 | /* SNB-B */ |
| 3600 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 3601 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3602 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3603 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3604 | reg = FDI_RX_CTL(pipe); |
| 3605 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3606 | if (HAS_PCH_CPT(dev)) { |
| 3607 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3608 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 3609 | } else { |
| 3610 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3611 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3612 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3613 | I915_WRITE(reg, temp); |
| 3614 | |
| 3615 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3616 | udelay(150); |
| 3617 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3618 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3619 | reg = FDI_TX_CTL(pipe); |
| 3620 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3621 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3622 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3623 | I915_WRITE(reg, temp); |
| 3624 | |
| 3625 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3626 | udelay(500); |
| 3627 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3628 | for (retry = 0; retry < 5; retry++) { |
| 3629 | reg = FDI_RX_IIR(pipe); |
| 3630 | temp = I915_READ(reg); |
| 3631 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3632 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 3633 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3634 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3635 | break; |
| 3636 | } |
| 3637 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3638 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 3639 | if (retry < 5) |
| 3640 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3641 | } |
| 3642 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3643 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3644 | |
| 3645 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3646 | } |
| 3647 | |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3648 | /* Manual link training for Ivy Bridge A0 parts */ |
| 3649 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 3650 | { |
| 3651 | struct drm_device *dev = crtc->dev; |
| 3652 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3654 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3655 | i915_reg_t reg; |
| 3656 | u32 temp, i, j; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3657 | |
| 3658 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3659 | for train result */ |
| 3660 | reg = FDI_RX_IMR(pipe); |
| 3661 | temp = I915_READ(reg); |
| 3662 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3663 | temp &= ~FDI_RX_BIT_LOCK; |
| 3664 | I915_WRITE(reg, temp); |
| 3665 | |
| 3666 | POSTING_READ(reg); |
| 3667 | udelay(150); |
| 3668 | |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 3669 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
| 3670 | I915_READ(FDI_RX_IIR(pipe))); |
| 3671 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3672 | /* Try each vswing and preemphasis setting twice before moving on */ |
| 3673 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
| 3674 | /* disable first in case we need to retry */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3675 | reg = FDI_TX_CTL(pipe); |
| 3676 | temp = I915_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3677 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 3678 | temp &= ~FDI_TX_ENABLE; |
| 3679 | I915_WRITE(reg, temp); |
| 3680 | |
| 3681 | reg = FDI_RX_CTL(pipe); |
| 3682 | temp = I915_READ(reg); |
| 3683 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 3684 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3685 | temp &= ~FDI_RX_ENABLE; |
| 3686 | I915_WRITE(reg, temp); |
| 3687 | |
| 3688 | /* enable CPU FDI TX and PCH FDI RX */ |
| 3689 | reg = FDI_TX_CTL(pipe); |
| 3690 | temp = I915_READ(reg); |
| 3691 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3692 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3693 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3694 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3695 | temp |= snb_b_fdi_train_param[j/2]; |
| 3696 | temp |= FDI_COMPOSITE_SYNC; |
| 3697 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 3698 | |
| 3699 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3700 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3701 | |
| 3702 | reg = FDI_RX_CTL(pipe); |
| 3703 | temp = I915_READ(reg); |
| 3704 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3705 | temp |= FDI_COMPOSITE_SYNC; |
| 3706 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3707 | |
| 3708 | POSTING_READ(reg); |
| 3709 | udelay(1); /* should be 0.5us */ |
| 3710 | |
| 3711 | for (i = 0; i < 4; i++) { |
| 3712 | reg = FDI_RX_IIR(pipe); |
| 3713 | temp = I915_READ(reg); |
| 3714 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3715 | |
| 3716 | if (temp & FDI_RX_BIT_LOCK || |
| 3717 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 3718 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3719 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
| 3720 | i); |
| 3721 | break; |
| 3722 | } |
| 3723 | udelay(1); /* should be 0.5us */ |
| 3724 | } |
| 3725 | if (i == 4) { |
| 3726 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
| 3727 | continue; |
| 3728 | } |
| 3729 | |
| 3730 | /* Train 2 */ |
| 3731 | reg = FDI_TX_CTL(pipe); |
| 3732 | temp = I915_READ(reg); |
| 3733 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 3734 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 3735 | I915_WRITE(reg, temp); |
| 3736 | |
| 3737 | reg = FDI_RX_CTL(pipe); |
| 3738 | temp = I915_READ(reg); |
| 3739 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3740 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3741 | I915_WRITE(reg, temp); |
| 3742 | |
| 3743 | POSTING_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3744 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3745 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3746 | for (i = 0; i < 4; i++) { |
| 3747 | reg = FDI_RX_IIR(pipe); |
| 3748 | temp = I915_READ(reg); |
| 3749 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3750 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3751 | if (temp & FDI_RX_SYMBOL_LOCK || |
| 3752 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
| 3753 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3754 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
| 3755 | i); |
| 3756 | goto train_done; |
| 3757 | } |
| 3758 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3759 | } |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3760 | if (i == 4) |
| 3761 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3762 | } |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3763 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 3764 | train_done: |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 3765 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3766 | } |
| 3767 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3768 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3769 | { |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3770 | struct drm_device *dev = intel_crtc->base.dev; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3771 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3772 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3773 | i915_reg_t reg; |
| 3774 | u32 temp; |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 3775 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3776 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3777 | reg = FDI_RX_CTL(pipe); |
| 3778 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 3779 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3780 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3781 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3782 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 3783 | |
| 3784 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3785 | udelay(200); |
| 3786 | |
| 3787 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3788 | temp = I915_READ(reg); |
| 3789 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 3790 | |
| 3791 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3792 | udelay(200); |
| 3793 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 3794 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
| 3795 | reg = FDI_TX_CTL(pipe); |
| 3796 | temp = I915_READ(reg); |
| 3797 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 3798 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3799 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 3800 | POSTING_READ(reg); |
| 3801 | udelay(100); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3802 | } |
| 3803 | } |
| 3804 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3805 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
| 3806 | { |
| 3807 | struct drm_device *dev = intel_crtc->base.dev; |
| 3808 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3809 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3810 | i915_reg_t reg; |
| 3811 | u32 temp; |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3812 | |
| 3813 | /* Switch from PCDclk to Rawclk */ |
| 3814 | reg = FDI_RX_CTL(pipe); |
| 3815 | temp = I915_READ(reg); |
| 3816 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
| 3817 | |
| 3818 | /* Disable CPU FDI TX PLL */ |
| 3819 | reg = FDI_TX_CTL(pipe); |
| 3820 | temp = I915_READ(reg); |
| 3821 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 3822 | |
| 3823 | POSTING_READ(reg); |
| 3824 | udelay(100); |
| 3825 | |
| 3826 | reg = FDI_RX_CTL(pipe); |
| 3827 | temp = I915_READ(reg); |
| 3828 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
| 3829 | |
| 3830 | /* Wait for the clocks to turn off. */ |
| 3831 | POSTING_READ(reg); |
| 3832 | udelay(100); |
| 3833 | } |
| 3834 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3835 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 3836 | { |
| 3837 | struct drm_device *dev = crtc->dev; |
| 3838 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3840 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3841 | i915_reg_t reg; |
| 3842 | u32 temp; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3843 | |
| 3844 | /* disable CPU FDI tx and PCH FDI rx */ |
| 3845 | reg = FDI_TX_CTL(pipe); |
| 3846 | temp = I915_READ(reg); |
| 3847 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 3848 | POSTING_READ(reg); |
| 3849 | |
| 3850 | reg = FDI_RX_CTL(pipe); |
| 3851 | temp = I915_READ(reg); |
| 3852 | temp &= ~(0x7 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3853 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3854 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 3855 | |
| 3856 | POSTING_READ(reg); |
| 3857 | udelay(100); |
| 3858 | |
| 3859 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 3860 | if (HAS_PCH_IBX(dev)) |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 3861 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3862 | |
| 3863 | /* still set train pattern 1 */ |
| 3864 | reg = FDI_TX_CTL(pipe); |
| 3865 | temp = I915_READ(reg); |
| 3866 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3867 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3868 | I915_WRITE(reg, temp); |
| 3869 | |
| 3870 | reg = FDI_RX_CTL(pipe); |
| 3871 | temp = I915_READ(reg); |
| 3872 | if (HAS_PCH_CPT(dev)) { |
| 3873 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3874 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3875 | } else { |
| 3876 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3877 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3878 | } |
| 3879 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 3880 | temp &= ~(0x07 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3881 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3882 | I915_WRITE(reg, temp); |
| 3883 | |
| 3884 | POSTING_READ(reg); |
| 3885 | udelay(100); |
| 3886 | } |
| 3887 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3888 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
| 3889 | { |
| 3890 | struct intel_crtc *crtc; |
| 3891 | |
| 3892 | /* Note that we don't need to be called with mode_config.lock here |
| 3893 | * as our list of CRTC objects is static for the lifetime of the |
| 3894 | * device and so cannot disappear as we iterate. Similarly, we can |
| 3895 | * happily treat the predicates as racy, atomic checks as userspace |
| 3896 | * cannot claim and pin a new fb without at least acquring the |
| 3897 | * struct_mutex and so serialising with us. |
| 3898 | */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 3899 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3900 | if (atomic_read(&crtc->unpin_work_count) == 0) |
| 3901 | continue; |
| 3902 | |
| 3903 | if (crtc->unpin_work) |
| 3904 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3905 | |
| 3906 | return true; |
| 3907 | } |
| 3908 | |
| 3909 | return false; |
| 3910 | } |
| 3911 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3912 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
| 3913 | { |
| 3914 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
| 3915 | struct intel_unpin_work *work = intel_crtc->unpin_work; |
| 3916 | |
| 3917 | /* ensure that the unpin work is consistent wrt ->pending. */ |
| 3918 | smp_rmb(); |
| 3919 | intel_crtc->unpin_work = NULL; |
| 3920 | |
| 3921 | if (work->event) |
| 3922 | drm_send_vblank_event(intel_crtc->base.dev, |
| 3923 | intel_crtc->pipe, |
| 3924 | work->event); |
| 3925 | |
| 3926 | drm_crtc_vblank_put(&intel_crtc->base); |
| 3927 | |
| 3928 | wake_up_all(&dev_priv->pending_flip_queue); |
| 3929 | queue_work(dev_priv->wq, &work->work); |
| 3930 | |
| 3931 | trace_i915_flip_complete(intel_crtc->plane, |
| 3932 | work->pending_flip_obj); |
| 3933 | } |
| 3934 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 3935 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3936 | { |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 3937 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 3938 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 3939 | long ret; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3940 | |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 3941 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 3942 | |
| 3943 | ret = wait_event_interruptible_timeout( |
| 3944 | dev_priv->pending_flip_queue, |
| 3945 | !intel_crtc_has_pending_flip(crtc), |
| 3946 | 60*HZ); |
| 3947 | |
| 3948 | if (ret < 0) |
| 3949 | return ret; |
| 3950 | |
| 3951 | if (ret == 0) { |
Chris Wilson | 9c78794 | 2014-09-05 07:13:25 +0100 | [diff] [blame] | 3952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 3953 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 3954 | spin_lock_irq(&dev->event_lock); |
Chris Wilson | 9c78794 | 2014-09-05 07:13:25 +0100 | [diff] [blame] | 3955 | if (intel_crtc->unpin_work) { |
| 3956 | WARN_ONCE(1, "Removing stuck page flip\n"); |
| 3957 | page_flip_completed(intel_crtc); |
| 3958 | } |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 3959 | spin_unlock_irq(&dev->event_lock); |
Chris Wilson | 9c78794 | 2014-09-05 07:13:25 +0100 | [diff] [blame] | 3960 | } |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 3961 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 3962 | return 0; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3963 | } |
| 3964 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 3965 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
| 3966 | { |
| 3967 | u32 temp; |
| 3968 | |
| 3969 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
| 3970 | |
| 3971 | mutex_lock(&dev_priv->sb_lock); |
| 3972 | |
| 3973 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
| 3974 | temp |= SBI_SSCCTL_DISABLE; |
| 3975 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
| 3976 | |
| 3977 | mutex_unlock(&dev_priv->sb_lock); |
| 3978 | } |
| 3979 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3980 | /* Program iCLKIP clock to the desired frequency */ |
| 3981 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
| 3982 | { |
| 3983 | struct drm_device *dev = crtc->dev; |
| 3984 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3985 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3986 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
| 3987 | u32 temp; |
| 3988 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 3989 | lpt_disable_iclkip(dev_priv); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3990 | |
| 3991 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3992 | if (clock == 20000) { |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3993 | auxdiv = 1; |
| 3994 | divsel = 0x41; |
| 3995 | phaseinc = 0x20; |
| 3996 | } else { |
| 3997 | /* The iCLK virtual clock root frequency is in MHz, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 3998 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
| 3999 | * divisors, it is necessary to divide one by another, so we |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4000 | * convert the virtual clock precision to KHz here for higher |
| 4001 | * precision. |
| 4002 | */ |
| 4003 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 4004 | u32 iclk_pi_range = 64; |
| 4005 | u32 desired_divisor, msb_divisor_value, pi_value; |
| 4006 | |
Ville Syrjälä | a2572f5 | 2015-12-04 22:20:21 +0200 | [diff] [blame] | 4007 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4008 | msb_divisor_value = desired_divisor / iclk_pi_range; |
| 4009 | pi_value = desired_divisor % iclk_pi_range; |
| 4010 | |
| 4011 | auxdiv = 0; |
| 4012 | divsel = msb_divisor_value - 2; |
| 4013 | phaseinc = pi_value; |
| 4014 | } |
| 4015 | |
| 4016 | /* This should not happen with any sane values */ |
| 4017 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
| 4018 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
| 4019 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
| 4020 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
| 4021 | |
| 4022 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 4023 | clock, |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4024 | auxdiv, |
| 4025 | divsel, |
| 4026 | phasedir, |
| 4027 | phaseinc); |
| 4028 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 4029 | mutex_lock(&dev_priv->sb_lock); |
| 4030 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4031 | /* Program SSCDIVINTPHASE6 */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4032 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4033 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
| 4034 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
| 4035 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
| 4036 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
| 4037 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
| 4038 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4039 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4040 | |
| 4041 | /* Program SSCAUXDIV */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4042 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4043 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
| 4044 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4045 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4046 | |
| 4047 | /* Enable modulator and associated divider */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4048 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4049 | temp &= ~SBI_SSCCTL_DISABLE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 4050 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4051 | |
Ville Syrjälä | 060f02d | 2015-12-04 22:21:34 +0200 | [diff] [blame] | 4052 | mutex_unlock(&dev_priv->sb_lock); |
| 4053 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 4054 | /* Wait for initialization time */ |
| 4055 | udelay(24); |
| 4056 | |
| 4057 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
| 4058 | } |
| 4059 | |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4060 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
| 4061 | enum pipe pch_transcoder) |
| 4062 | { |
| 4063 | struct drm_device *dev = crtc->base.dev; |
| 4064 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4065 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4066 | |
| 4067 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
| 4068 | I915_READ(HTOTAL(cpu_transcoder))); |
| 4069 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
| 4070 | I915_READ(HBLANK(cpu_transcoder))); |
| 4071 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
| 4072 | I915_READ(HSYNC(cpu_transcoder))); |
| 4073 | |
| 4074 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
| 4075 | I915_READ(VTOTAL(cpu_transcoder))); |
| 4076 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
| 4077 | I915_READ(VBLANK(cpu_transcoder))); |
| 4078 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
| 4079 | I915_READ(VSYNC(cpu_transcoder))); |
| 4080 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
| 4081 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
| 4082 | } |
| 4083 | |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4084 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4085 | { |
| 4086 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4087 | uint32_t temp; |
| 4088 | |
| 4089 | temp = I915_READ(SOUTH_CHICKEN1); |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4090 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4091 | return; |
| 4092 | |
| 4093 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 4094 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 4095 | |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4096 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
| 4097 | if (enable) |
| 4098 | temp |= FDI_BC_BIFURCATION_SELECT; |
| 4099 | |
| 4100 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4101 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 4102 | POSTING_READ(SOUTH_CHICKEN1); |
| 4103 | } |
| 4104 | |
| 4105 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
| 4106 | { |
| 4107 | struct drm_device *dev = intel_crtc->base.dev; |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4108 | |
| 4109 | switch (intel_crtc->pipe) { |
| 4110 | case PIPE_A: |
| 4111 | break; |
| 4112 | case PIPE_B: |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4113 | if (intel_crtc->config->fdi_lanes > 2) |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4114 | cpt_set_fdi_bc_bifurcation(dev, false); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4115 | else |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4116 | cpt_set_fdi_bc_bifurcation(dev, true); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4117 | |
| 4118 | break; |
| 4119 | case PIPE_C: |
Ander Conselvan de Oliveira | 003632d | 2015-03-11 13:35:43 +0200 | [diff] [blame] | 4120 | cpt_set_fdi_bc_bifurcation(dev, true); |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4121 | |
| 4122 | break; |
| 4123 | default: |
| 4124 | BUG(); |
| 4125 | } |
| 4126 | } |
| 4127 | |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4128 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 4129 | static enum port |
| 4130 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
| 4131 | { |
| 4132 | struct drm_device *dev = crtc->dev; |
| 4133 | struct intel_encoder *encoder; |
| 4134 | |
| 4135 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 4136 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 4137 | encoder->type == INTEL_OUTPUT_EDP) |
| 4138 | return enc_to_dig_port(&encoder->base)->port; |
| 4139 | } |
| 4140 | |
| 4141 | return -1; |
| 4142 | } |
| 4143 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4144 | /* |
| 4145 | * Enable PCH resources required for PCH ports: |
| 4146 | * - PCH PLLs |
| 4147 | * - FDI training & RX/TX |
| 4148 | * - update transcoder timings |
| 4149 | * - DP transcoding bits |
| 4150 | * - transcoder |
| 4151 | */ |
| 4152 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4153 | { |
| 4154 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4155 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4157 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4158 | u32 temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4159 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 4160 | assert_pch_transcoder_disabled(dev_priv, pipe); |
Chris Wilson | e7e164d | 2012-05-11 09:21:25 +0100 | [diff] [blame] | 4161 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 4162 | if (IS_IVYBRIDGE(dev)) |
| 4163 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
| 4164 | |
Daniel Vetter | cd986ab | 2012-10-26 10:58:12 +0200 | [diff] [blame] | 4165 | /* Write the TU size bits before fdi link training, so that error |
| 4166 | * detection works. */ |
| 4167 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 4168 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
| 4169 | |
Ville Syrjälä | 3860b2e | 2015-11-20 22:09:18 +0200 | [diff] [blame] | 4170 | /* |
| 4171 | * Sometimes spurious CPU pipe underruns happen during FDI |
| 4172 | * training, at least with VGA+HDMI cloning. Suppress them. |
| 4173 | */ |
| 4174 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 4175 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4176 | /* For PCH output, training FDI link */ |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 4177 | dev_priv->display.fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4178 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 4179 | /* We need to program the right clock selection before writing the pixel |
| 4180 | * mutliplier into the DPLL. */ |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 4181 | if (HAS_PCH_CPT(dev)) { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4182 | u32 sel; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4183 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4184 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 4185 | temp |= TRANS_DPLL_ENABLE(pipe); |
| 4186 | sel = TRANS_DPLLB_SEL(pipe); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4187 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4188 | temp |= sel; |
| 4189 | else |
| 4190 | temp &= ~sel; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4191 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4192 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4193 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 4194 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
| 4195 | * transcoder, and we actually should do this to not upset any PCH |
| 4196 | * transcoder that already use the clock when we share it. |
| 4197 | * |
| 4198 | * Note that enable_shared_dpll tries to do the right thing, but |
| 4199 | * get_shared_dpll unconditionally resets the pll - we need that to have |
| 4200 | * the right LVDS enable sequence. */ |
Daniel Vetter | 85b3894 | 2014-04-24 23:55:14 +0200 | [diff] [blame] | 4201 | intel_enable_shared_dpll(intel_crtc); |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 4202 | |
Jesse Barnes | d9b6cb5 | 2011-01-04 15:09:35 -0800 | [diff] [blame] | 4203 | /* set transcoder timing, panel must allow it */ |
| 4204 | assert_panel_unlocked(dev_priv, pipe); |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4205 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4206 | |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 4207 | intel_fdi_normal_train(crtc); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 4208 | |
Ville Syrjälä | 3860b2e | 2015-11-20 22:09:18 +0200 | [diff] [blame] | 4209 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4210 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4211 | /* For PCH DP, enable TRANS_DP_CTL */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4212 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
Ville Syrjälä | 9c4edae | 2015-10-29 21:25:51 +0200 | [diff] [blame] | 4213 | const struct drm_display_mode *adjusted_mode = |
| 4214 | &intel_crtc->config->base.adjusted_mode; |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 4215 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4216 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4217 | temp = I915_READ(reg); |
| 4218 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
Eric Anholt | 220cad3 | 2010-11-18 09:32:58 +0800 | [diff] [blame] | 4219 | TRANS_DP_SYNC_MASK | |
| 4220 | TRANS_DP_BPC_MASK); |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 4221 | temp |= TRANS_DP_OUTPUT_ENABLE; |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 4222 | temp |= bpc << 9; /* same format but at 11:9 */ |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4223 | |
Ville Syrjälä | 9c4edae | 2015-10-29 21:25:51 +0200 | [diff] [blame] | 4224 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4225 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Ville Syrjälä | 9c4edae | 2015-10-29 21:25:51 +0200 | [diff] [blame] | 4226 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4227 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4228 | |
| 4229 | switch (intel_trans_dp_port_sel(crtc)) { |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4230 | case PORT_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4231 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4232 | break; |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4233 | case PORT_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4234 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4235 | break; |
Ville Syrjälä | c48b530 | 2015-11-04 23:19:56 +0200 | [diff] [blame] | 4236 | case PORT_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4237 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4238 | break; |
| 4239 | default: |
Daniel Vetter | e95d41e | 2012-10-26 10:58:16 +0200 | [diff] [blame] | 4240 | BUG(); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4241 | } |
| 4242 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4243 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 4244 | } |
| 4245 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 4246 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4247 | } |
| 4248 | |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4249 | static void lpt_pch_enable(struct drm_crtc *crtc) |
| 4250 | { |
| 4251 | struct drm_device *dev = crtc->dev; |
| 4252 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4254 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4255 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 4256 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4257 | |
Paulo Zanoni | 8c52b5e | 2012-10-31 18:12:24 -0200 | [diff] [blame] | 4258 | lpt_program_iclkip(crtc); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4259 | |
Paulo Zanoni | 0540e48 | 2012-10-31 18:12:40 -0200 | [diff] [blame] | 4260 | /* Set transcoder timing. */ |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 4261 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 4262 | |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 4263 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4264 | } |
| 4265 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 4266 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
| 4267 | struct intel_crtc_state *crtc_state) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4268 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 4269 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4270 | struct intel_shared_dpll *pll; |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4271 | struct intel_shared_dpll_config *shared_dpll; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 4272 | enum intel_dpll_id i; |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 4273 | int max = dev_priv->num_shared_dpll; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4274 | |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4275 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
| 4276 | |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 4277 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 4278 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
Daniel Vetter | d94ab06 | 2013-07-04 12:01:16 +0200 | [diff] [blame] | 4279 | i = (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 4280 | pll = &dev_priv->shared_dplls[i]; |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 4281 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 4282 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 4283 | crtc->base.base.id, pll->name); |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 4284 | |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4285 | WARN_ON(shared_dpll[i].crtc_mask); |
Daniel Vetter | f2a69f4 | 2014-05-20 15:19:19 +0200 | [diff] [blame] | 4286 | |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 4287 | goto found; |
| 4288 | } |
| 4289 | |
Satheeshakrishna M | bcddf610 | 2014-08-22 09:49:10 +0530 | [diff] [blame] | 4290 | if (IS_BROXTON(dev_priv->dev)) { |
| 4291 | /* PLL is attached to port in bxt */ |
| 4292 | struct intel_encoder *encoder; |
| 4293 | struct intel_digital_port *intel_dig_port; |
| 4294 | |
| 4295 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); |
| 4296 | if (WARN_ON(!encoder)) |
| 4297 | return NULL; |
| 4298 | |
| 4299 | intel_dig_port = enc_to_dig_port(&encoder->base); |
| 4300 | /* 1:1 mapping between ports and PLLs */ |
| 4301 | i = (enum intel_dpll_id)intel_dig_port->port; |
| 4302 | pll = &dev_priv->shared_dplls[i]; |
| 4303 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 4304 | crtc->base.base.id, pll->name); |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4305 | WARN_ON(shared_dpll[i].crtc_mask); |
Satheeshakrishna M | bcddf610 | 2014-08-22 09:49:10 +0530 | [diff] [blame] | 4306 | |
| 4307 | goto found; |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 4308 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
| 4309 | /* Do not consider SPLL */ |
| 4310 | max = 2; |
Satheeshakrishna M | bcddf610 | 2014-08-22 09:49:10 +0530 | [diff] [blame] | 4311 | |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 4312 | for (i = 0; i < max; i++) { |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 4313 | pll = &dev_priv->shared_dplls[i]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4314 | |
| 4315 | /* Only want to check enabled timings first */ |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4316 | if (shared_dpll[i].crtc_mask == 0) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4317 | continue; |
| 4318 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 4319 | if (memcmp(&crtc_state->dpll_hw_state, |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4320 | &shared_dpll[i].hw_state, |
| 4321 | sizeof(crtc_state->dpll_hw_state)) == 0) { |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4322 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 4323 | crtc->base.base.id, pll->name, |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4324 | shared_dpll[i].crtc_mask, |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4325 | pll->active); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4326 | goto found; |
| 4327 | } |
| 4328 | } |
| 4329 | |
| 4330 | /* Ok no matching timings, maybe there's a free one? */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 4331 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 4332 | pll = &dev_priv->shared_dplls[i]; |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4333 | if (shared_dpll[i].crtc_mask == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 4334 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
| 4335 | crtc->base.base.id, pll->name); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4336 | goto found; |
| 4337 | } |
| 4338 | } |
| 4339 | |
| 4340 | return NULL; |
| 4341 | |
| 4342 | found: |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4343 | if (shared_dpll[i].crtc_mask == 0) |
| 4344 | shared_dpll[i].hw_state = |
| 4345 | crtc_state->dpll_hw_state; |
Daniel Vetter | f2a69f4 | 2014-05-20 15:19:19 +0200 | [diff] [blame] | 4346 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 4347 | crtc_state->shared_dpll = i; |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 4348 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
| 4349 | pipe_name(crtc->pipe)); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 4350 | |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4351 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4352 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4353 | return pll; |
| 4354 | } |
| 4355 | |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4356 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4357 | { |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4358 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 4359 | struct intel_shared_dpll_config *shared_dpll; |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4360 | struct intel_shared_dpll *pll; |
| 4361 | enum intel_dpll_id i; |
| 4362 | |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4363 | if (!to_intel_atomic_state(state)->dpll_set) |
| 4364 | return; |
| 4365 | |
| 4366 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4367 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 4368 | pll = &dev_priv->shared_dplls[i]; |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 4369 | pll->config = shared_dpll[i]; |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 4370 | } |
| 4371 | } |
| 4372 | |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 4373 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4374 | { |
| 4375 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4376 | i915_reg_t dslreg = PIPEDSL(pipe); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4377 | u32 temp; |
| 4378 | |
| 4379 | temp = I915_READ(dslreg); |
| 4380 | udelay(500); |
| 4381 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4382 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 4383 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 4384 | } |
| 4385 | } |
| 4386 | |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4387 | static int |
| 4388 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, |
| 4389 | unsigned scaler_user, int *scaler_id, unsigned int rotation, |
| 4390 | int src_w, int src_h, int dst_w, int dst_h) |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4391 | { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4392 | struct intel_crtc_scaler_state *scaler_state = |
| 4393 | &crtc_state->scaler_state; |
| 4394 | struct intel_crtc *intel_crtc = |
| 4395 | to_intel_crtc(crtc_state->base.crtc); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4396 | int need_scaling; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 4397 | |
| 4398 | need_scaling = intel_rotation_90_or_270(rotation) ? |
| 4399 | (src_h != dst_w || src_w != dst_h): |
| 4400 | (src_w != dst_w || src_h != dst_h); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4401 | |
| 4402 | /* |
| 4403 | * if plane is being disabled or scaler is no more required or force detach |
| 4404 | * - free scaler binded to this plane/crtc |
| 4405 | * - in order to do this, update crtc->scaler_usage |
| 4406 | * |
| 4407 | * Here scaler state in crtc_state is set free so that |
| 4408 | * scaler can be assigned to other user. Actual register |
| 4409 | * update to free the scaler is done in plane/panel-fit programming. |
| 4410 | * For this purpose crtc/plane_state->scaler_id isn't reset here. |
| 4411 | */ |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4412 | if (force_detach || !need_scaling) { |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4413 | if (*scaler_id >= 0) { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4414 | scaler_state->scaler_users &= ~(1 << scaler_user); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4415 | scaler_state->scalers[*scaler_id].in_use = 0; |
| 4416 | |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4417 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
| 4418 | "Staged freeing scaler id %d scaler_users = 0x%x\n", |
| 4419 | intel_crtc->pipe, scaler_user, *scaler_id, |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4420 | scaler_state->scaler_users); |
| 4421 | *scaler_id = -1; |
| 4422 | } |
| 4423 | return 0; |
| 4424 | } |
| 4425 | |
| 4426 | /* range checks */ |
| 4427 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || |
| 4428 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || |
| 4429 | |
| 4430 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || |
| 4431 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4432 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4433 | "size is out of scaler range\n", |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4434 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4435 | return -EINVAL; |
| 4436 | } |
| 4437 | |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4438 | /* mark this plane as a scaler user in crtc_state */ |
| 4439 | scaler_state->scaler_users |= (1 << scaler_user); |
| 4440 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
| 4441 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", |
| 4442 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, |
| 4443 | scaler_state->scaler_users); |
| 4444 | |
| 4445 | return 0; |
| 4446 | } |
| 4447 | |
| 4448 | /** |
| 4449 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. |
| 4450 | * |
| 4451 | * @state: crtc's scaler state |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4452 | * |
| 4453 | * Return |
| 4454 | * 0 - scaler_usage updated successfully |
| 4455 | * error - requested scaling cannot be supported or other error condition |
| 4456 | */ |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 4457 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4458 | { |
| 4459 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 4460 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4461 | |
| 4462 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", |
| 4463 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); |
| 4464 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 4465 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4466 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
| 4467 | state->pipe_src_w, state->pipe_src_h, |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 4468 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4469 | } |
| 4470 | |
| 4471 | /** |
| 4472 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. |
| 4473 | * |
| 4474 | * @state: crtc's scaler state |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4475 | * @plane_state: atomic plane state to update |
| 4476 | * |
| 4477 | * Return |
| 4478 | * 0 - scaler_usage updated successfully |
| 4479 | * error - requested scaling cannot be supported or other error condition |
| 4480 | */ |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 4481 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
| 4482 | struct intel_plane_state *plane_state) |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4483 | { |
| 4484 | |
| 4485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 4486 | struct intel_plane *intel_plane = |
| 4487 | to_intel_plane(plane_state->base.plane); |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4488 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 4489 | int ret; |
| 4490 | |
| 4491 | bool force_detach = !fb || !plane_state->visible; |
| 4492 | |
| 4493 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", |
| 4494 | intel_plane->base.base.id, intel_crtc->pipe, |
| 4495 | drm_plane_index(&intel_plane->base)); |
| 4496 | |
| 4497 | ret = skl_update_scaler(crtc_state, force_detach, |
| 4498 | drm_plane_index(&intel_plane->base), |
| 4499 | &plane_state->scaler_id, |
| 4500 | plane_state->base.rotation, |
| 4501 | drm_rect_width(&plane_state->src) >> 16, |
| 4502 | drm_rect_height(&plane_state->src) >> 16, |
| 4503 | drm_rect_width(&plane_state->dst), |
| 4504 | drm_rect_height(&plane_state->dst)); |
| 4505 | |
| 4506 | if (ret || plane_state->scaler_id < 0) |
| 4507 | return ret; |
| 4508 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4509 | /* check colorkey */ |
Maarten Lankhorst | 818ed96 | 2015-06-15 12:33:54 +0200 | [diff] [blame] | 4510 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4511 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
Maarten Lankhorst | 818ed96 | 2015-06-15 12:33:54 +0200 | [diff] [blame] | 4512 | intel_plane->base.base.id); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4513 | return -EINVAL; |
| 4514 | } |
| 4515 | |
| 4516 | /* Check src format */ |
Maarten Lankhorst | 86adf9d | 2015-06-22 09:50:32 +0200 | [diff] [blame] | 4517 | switch (fb->pixel_format) { |
| 4518 | case DRM_FORMAT_RGB565: |
| 4519 | case DRM_FORMAT_XBGR8888: |
| 4520 | case DRM_FORMAT_XRGB8888: |
| 4521 | case DRM_FORMAT_ABGR8888: |
| 4522 | case DRM_FORMAT_ARGB8888: |
| 4523 | case DRM_FORMAT_XRGB2101010: |
| 4524 | case DRM_FORMAT_XBGR2101010: |
| 4525 | case DRM_FORMAT_YUYV: |
| 4526 | case DRM_FORMAT_YVYU: |
| 4527 | case DRM_FORMAT_UYVY: |
| 4528 | case DRM_FORMAT_VYUY: |
| 4529 | break; |
| 4530 | default: |
| 4531 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", |
| 4532 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); |
| 4533 | return -EINVAL; |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4534 | } |
| 4535 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4536 | return 0; |
| 4537 | } |
| 4538 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 4539 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
| 4540 | { |
| 4541 | int i; |
| 4542 | |
| 4543 | for (i = 0; i < crtc->num_scalers; i++) |
| 4544 | skl_detach_scaler(crtc, i); |
| 4545 | } |
| 4546 | |
| 4547 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 4548 | { |
| 4549 | struct drm_device *dev = crtc->base.dev; |
| 4550 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4551 | int pipe = crtc->pipe; |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4552 | struct intel_crtc_scaler_state *scaler_state = |
| 4553 | &crtc->config->scaler_state; |
| 4554 | |
| 4555 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); |
| 4556 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4557 | if (crtc->config->pch_pfit.enabled) { |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 4558 | int id; |
| 4559 | |
| 4560 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { |
| 4561 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); |
| 4562 | return; |
| 4563 | } |
| 4564 | |
| 4565 | id = scaler_state->scaler_id; |
| 4566 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | |
| 4567 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); |
| 4568 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); |
| 4569 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); |
| 4570 | |
| 4571 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 4572 | } |
| 4573 | } |
| 4574 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4575 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
| 4576 | { |
| 4577 | struct drm_device *dev = crtc->base.dev; |
| 4578 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4579 | int pipe = crtc->pipe; |
| 4580 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4581 | if (crtc->config->pch_pfit.enabled) { |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4582 | /* Force use of hard-coded filter coefficients |
| 4583 | * as some pre-programmed values are broken, |
| 4584 | * e.g. x201. |
| 4585 | */ |
| 4586 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 4587 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
| 4588 | PF_PIPE_SEL_IVB(pipe)); |
| 4589 | else |
| 4590 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4591 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
| 4592 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 4593 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4594 | } |
| 4595 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 4596 | void hsw_enable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4597 | { |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 4598 | struct drm_device *dev = crtc->base.dev; |
| 4599 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4600 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4601 | if (!crtc->config->ips_enabled) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4602 | return; |
| 4603 | |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 4604 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
| 4605 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4606 | |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4607 | assert_plane_enabled(dev_priv, crtc->plane); |
Ville Syrjälä | cea165c | 2014-04-15 21:41:35 +0300 | [diff] [blame] | 4608 | if (IS_BROADWELL(dev)) { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4609 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4610 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
| 4611 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4612 | /* Quoting Art Runyan: "its not safe to expect any particular |
| 4613 | * value in IPS_CTL bit 31 after enabling IPS through the |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 4614 | * mailbox." Moreover, the mailbox may return a bogus state, |
| 4615 | * so we need to just enable it and continue on. |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4616 | */ |
| 4617 | } else { |
| 4618 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
| 4619 | /* The bit only becomes 1 in the next vblank, so this wait here |
| 4620 | * is essentially intel_wait_for_vblank. If we don't have this |
| 4621 | * and don't wait for vblanks until the end of crtc_enable, then |
| 4622 | * the HW state readout code will complain that the expected |
| 4623 | * IPS_CTL value is not the one we read. */ |
| 4624 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
| 4625 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
| 4626 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4627 | } |
| 4628 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 4629 | void hsw_disable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4630 | { |
| 4631 | struct drm_device *dev = crtc->base.dev; |
| 4632 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4633 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4634 | if (!crtc->config->ips_enabled) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4635 | return; |
| 4636 | |
| 4637 | assert_plane_enabled(dev_priv, crtc->plane); |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 4638 | if (IS_BROADWELL(dev)) { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4639 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4640 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
| 4641 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 23d0b13 | 2014-04-10 14:32:41 -0700 | [diff] [blame] | 4642 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
| 4643 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) |
| 4644 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 4645 | } else { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 4646 | I915_WRITE(IPS_CTL, 0); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 4647 | POSTING_READ(IPS_CTL); |
| 4648 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4649 | |
| 4650 | /* We need to wait for a vblank before we can disable the plane. */ |
| 4651 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4652 | } |
| 4653 | |
| 4654 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 4655 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 4656 | { |
| 4657 | struct drm_device *dev = crtc->dev; |
| 4658 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4659 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4660 | enum pipe pipe = intel_crtc->pipe; |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4661 | int i; |
| 4662 | bool reenable_ips = false; |
| 4663 | |
| 4664 | /* The clocks have to be on to load the palette. */ |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 4665 | if (!crtc->state->active) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4666 | return; |
| 4667 | |
Imre Deak | 5036040 | 2015-01-16 00:55:16 -0800 | [diff] [blame] | 4668 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 4669 | if (intel_crtc->config->has_dsi_encoder) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4670 | assert_dsi_pll_enabled(dev_priv); |
| 4671 | else |
| 4672 | assert_pll_enabled(dev_priv, pipe); |
| 4673 | } |
| 4674 | |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4675 | /* Workaround : Do not read or write the pipe palette/gamma data while |
| 4676 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 4677 | */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4678 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4679 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
| 4680 | GAMMA_MODE_MODE_SPLIT)) { |
| 4681 | hsw_disable_ips(intel_crtc); |
| 4682 | reenable_ips = true; |
| 4683 | } |
| 4684 | |
| 4685 | for (i = 0; i < 256; i++) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4686 | i915_reg_t palreg; |
Ville Syrjälä | f65a9c5 | 2015-09-18 20:03:28 +0300 | [diff] [blame] | 4687 | |
| 4688 | if (HAS_GMCH_DISPLAY(dev)) |
| 4689 | palreg = PALETTE(pipe, i); |
| 4690 | else |
| 4691 | palreg = LGC_PALETTE(pipe, i); |
| 4692 | |
| 4693 | I915_WRITE(palreg, |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 4694 | (intel_crtc->lut_r[i] << 16) | |
| 4695 | (intel_crtc->lut_g[i] << 8) | |
| 4696 | intel_crtc->lut_b[i]); |
| 4697 | } |
| 4698 | |
| 4699 | if (reenable_ips) |
| 4700 | hsw_enable_ips(intel_crtc); |
| 4701 | } |
| 4702 | |
Maarten Lankhorst | 7cac945 | 2015-04-21 17:12:55 +0300 | [diff] [blame] | 4703 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4704 | { |
Maarten Lankhorst | 7cac945 | 2015-04-21 17:12:55 +0300 | [diff] [blame] | 4705 | if (intel_crtc->overlay) { |
Ville Syrjälä | d3eedb1 | 2014-05-08 19:23:13 +0300 | [diff] [blame] | 4706 | struct drm_device *dev = intel_crtc->base.dev; |
| 4707 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4708 | |
| 4709 | mutex_lock(&dev->struct_mutex); |
| 4710 | dev_priv->mm.interruptible = false; |
| 4711 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 4712 | dev_priv->mm.interruptible = true; |
| 4713 | mutex_unlock(&dev->struct_mutex); |
| 4714 | } |
| 4715 | |
| 4716 | /* Let userspace switch the overlay on again. In most cases userspace |
| 4717 | * has to recompute where to put it anyway. |
| 4718 | */ |
| 4719 | } |
| 4720 | |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4721 | /** |
| 4722 | * intel_post_enable_primary - Perform operations after enabling primary plane |
| 4723 | * @crtc: the CRTC whose primary plane was just enabled |
| 4724 | * |
| 4725 | * Performs potentially sleeping operations that must be done after the primary |
| 4726 | * plane is enabled, such as updating FBC and IPS. Note that this may be |
| 4727 | * called due to an explicit primary plane update, or due to an implicit |
| 4728 | * re-enable that is caused when a sprite plane is updated to no longer |
| 4729 | * completely hide the primary plane. |
| 4730 | */ |
| 4731 | static void |
| 4732 | intel_post_enable_primary(struct drm_crtc *crtc) |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4733 | { |
| 4734 | struct drm_device *dev = crtc->dev; |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4735 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4737 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4738 | |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4739 | /* |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4740 | * FIXME IPS should be fine as long as one plane is |
| 4741 | * enabled, but in practice it seems to have problems |
| 4742 | * when going from primary only to sprite only and vice |
| 4743 | * versa. |
| 4744 | */ |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4745 | hsw_enable_ips(intel_crtc); |
| 4746 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4747 | /* |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4748 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4749 | * So don't enable underrun reporting before at least some planes |
| 4750 | * are enabled. |
| 4751 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4752 | * but leave the pipe running. |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4753 | */ |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4754 | if (IS_GEN2(dev)) |
| 4755 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4756 | |
Ville Syrjälä | aca7b68 | 2015-10-30 19:22:21 +0200 | [diff] [blame] | 4757 | /* Underruns don't always raise interrupts, so check manually. */ |
| 4758 | intel_check_cpu_fifo_underruns(dev_priv); |
| 4759 | intel_check_pch_fifo_underruns(dev_priv); |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4760 | } |
| 4761 | |
| 4762 | /** |
| 4763 | * intel_pre_disable_primary - Perform operations before disabling primary plane |
| 4764 | * @crtc: the CRTC whose primary plane is to be disabled |
| 4765 | * |
| 4766 | * Performs potentially sleeping operations that must be done before the |
| 4767 | * primary plane is disabled, such as updating FBC and IPS. Note that this may |
| 4768 | * be called due to an explicit primary plane update, or due to an implicit |
| 4769 | * disable that is caused when a sprite plane completely hides the primary |
| 4770 | * plane. |
| 4771 | */ |
| 4772 | static void |
| 4773 | intel_pre_disable_primary(struct drm_crtc *crtc) |
| 4774 | { |
| 4775 | struct drm_device *dev = crtc->dev; |
| 4776 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4778 | int pipe = intel_crtc->pipe; |
| 4779 | |
| 4780 | /* |
| 4781 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4782 | * So diasble underrun reporting before all the planes get disabled. |
| 4783 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4784 | * but leave the pipe running. |
| 4785 | */ |
| 4786 | if (IS_GEN2(dev)) |
| 4787 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 4788 | |
| 4789 | /* |
| 4790 | * Vblank time updates from the shadow to live plane control register |
| 4791 | * are blocked if the memory self-refresh mode is active at that |
| 4792 | * moment. So to make sure the plane gets truly disabled, disable |
| 4793 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 4794 | * will be checked/applied by the HW only at the next frame start |
| 4795 | * event which is after the vblank start event, so we need to have a |
| 4796 | * wait-for-vblank between disabling the plane and the pipe. |
| 4797 | */ |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 4798 | if (HAS_GMCH_DISPLAY(dev)) { |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4799 | intel_set_memory_cxsr(dev_priv, false); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 4800 | dev_priv->wm.vlv.cxsr = false; |
| 4801 | intel_wait_for_vblank(dev, pipe); |
| 4802 | } |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4803 | |
Maarten Lankhorst | 87d4300 | 2015-04-21 17:12:54 +0300 | [diff] [blame] | 4804 | /* |
| 4805 | * FIXME IPS should be fine as long as one plane is |
| 4806 | * enabled, but in practice it seems to have problems |
| 4807 | * when going from primary only to sprite only and vice |
| 4808 | * versa. |
| 4809 | */ |
| 4810 | hsw_disable_ips(intel_crtc); |
| 4811 | } |
| 4812 | |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4813 | static void intel_post_plane_update(struct intel_crtc *crtc) |
| 4814 | { |
| 4815 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 4816 | struct intel_crtc_state *pipe_config = |
| 4817 | to_intel_crtc_state(crtc->base.state); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4818 | struct drm_device *dev = crtc->base.dev; |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4819 | |
| 4820 | if (atomic->wait_vblank) |
| 4821 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4822 | |
| 4823 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
| 4824 | |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 4825 | crtc->wm.cxsr_allowed = true; |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 4826 | |
Maarten Lankhorst | b900111 | 2015-11-19 16:07:16 +0100 | [diff] [blame] | 4827 | if (pipe_config->wm_changed && pipe_config->base.active) |
Ville Syrjälä | f015c55 | 2015-06-24 22:00:02 +0300 | [diff] [blame] | 4828 | intel_update_watermarks(&crtc->base); |
| 4829 | |
Paulo Zanoni | c80ac85 | 2015-07-02 19:25:13 -0300 | [diff] [blame] | 4830 | if (atomic->update_fbc) |
Paulo Zanoni | 754d113 | 2015-10-13 19:13:25 -0300 | [diff] [blame] | 4831 | intel_fbc_update(crtc); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4832 | |
| 4833 | if (atomic->post_enable_primary) |
| 4834 | intel_post_enable_primary(&crtc->base); |
| 4835 | |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4836 | memset(atomic, 0, sizeof(*atomic)); |
| 4837 | } |
| 4838 | |
| 4839 | static void intel_pre_plane_update(struct intel_crtc *crtc) |
| 4840 | { |
| 4841 | struct drm_device *dev = crtc->base.dev; |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 4842 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4843 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 4844 | struct intel_crtc_state *pipe_config = |
| 4845 | to_intel_crtc_state(crtc->base.state); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4846 | |
Paulo Zanoni | c80ac85 | 2015-07-02 19:25:13 -0300 | [diff] [blame] | 4847 | if (atomic->disable_fbc) |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 4848 | intel_fbc_deactivate(crtc); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4849 | |
Rodrigo Vivi | 066cf55 | 2015-06-26 13:55:54 -0700 | [diff] [blame] | 4850 | if (crtc->atomic.disable_ips) |
| 4851 | hsw_disable_ips(crtc); |
| 4852 | |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4853 | if (atomic->pre_disable_primary) |
| 4854 | intel_pre_disable_primary(&crtc->base); |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 4855 | |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 4856 | if (pipe_config->disable_cxsr) { |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 4857 | crtc->wm.cxsr_allowed = false; |
| 4858 | intel_set_memory_cxsr(dev_priv, false); |
| 4859 | } |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 4860 | |
| 4861 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) |
| 4862 | intel_update_watermarks(&crtc->base); |
Maarten Lankhorst | ac21b22 | 2015-06-15 12:33:49 +0200 | [diff] [blame] | 4863 | } |
| 4864 | |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 4865 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4866 | { |
| 4867 | struct drm_device *dev = crtc->dev; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 4869 | struct drm_plane *p; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4870 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4871 | |
Maarten Lankhorst | 7cac945 | 2015-04-21 17:12:55 +0300 | [diff] [blame] | 4872 | intel_crtc_dpms_overlay_disable(intel_crtc); |
Maarten Lankhorst | 27321ae | 2015-04-21 17:12:52 +0300 | [diff] [blame] | 4873 | |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 4874 | drm_for_each_plane_mask(p, dev, plane_mask) |
| 4875 | to_intel_plane(p)->disable_plane(p, crtc); |
Ville Syrjälä | f98551a | 2014-05-22 17:48:06 +0300 | [diff] [blame] | 4876 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4877 | /* |
| 4878 | * FIXME: Once we grow proper nuclear flip support out of this we need |
| 4879 | * to compute the mask of flip planes precisely. For the time being |
| 4880 | * consider this a flip to a NULL plane. |
| 4881 | */ |
| 4882 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
Ville Syrjälä | a5c4d7b | 2014-03-07 18:32:13 +0200 | [diff] [blame] | 4883 | } |
| 4884 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4885 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
| 4886 | { |
| 4887 | struct drm_device *dev = crtc->dev; |
| 4888 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4890 | struct intel_encoder *encoder; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4891 | int pipe = intel_crtc->pipe; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4892 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 4893 | if (WARN_ON(intel_crtc->active)) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4894 | return; |
| 4895 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4896 | if (intel_crtc->config->has_pch_encoder) |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 4897 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
| 4898 | |
| 4899 | if (intel_crtc->config->has_pch_encoder) |
Daniel Vetter | b14b105 | 2014-04-24 23:55:13 +0200 | [diff] [blame] | 4900 | intel_prepare_shared_dpll(intel_crtc); |
| 4901 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4902 | if (intel_crtc->config->has_dp_encoder) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 4903 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 4904 | |
| 4905 | intel_set_pipe_timings(intel_crtc); |
| 4906 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4907 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 4908 | intel_cpu_transcoder_set_m_n(intel_crtc, |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4909 | &intel_crtc->config->fdi_m_n, NULL); |
Daniel Vetter | 29407aa | 2014-04-24 23:55:08 +0200 | [diff] [blame] | 4910 | } |
| 4911 | |
| 4912 | ironlake_set_pipeconf(crtc); |
| 4913 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4914 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4915 | |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 4916 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 4917 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 4918 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Daniel Vetter | 952735e | 2013-06-05 13:34:27 +0200 | [diff] [blame] | 4919 | if (encoder->pre_enable) |
| 4920 | encoder->pre_enable(encoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4921 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4922 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | fff367c | 2012-10-27 15:50:28 +0200 | [diff] [blame] | 4923 | /* Note: FDI PLL enabling _must_ be done before we enable the |
| 4924 | * cpu pipes, hence this is separate from all the other fdi/pch |
| 4925 | * enabling. */ |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 4926 | ironlake_fdi_pll_enable(intel_crtc); |
Daniel Vetter | 46b6f81 | 2012-09-06 22:08:33 +0200 | [diff] [blame] | 4927 | } else { |
| 4928 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 4929 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 4930 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4931 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4932 | ironlake_pfit_enable(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4933 | |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 4934 | /* |
| 4935 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 4936 | * clocks enabled |
| 4937 | */ |
| 4938 | intel_crtc_load_lut(crtc); |
| 4939 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4940 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4941 | intel_enable_pipe(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4942 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4943 | if (intel_crtc->config->has_pch_encoder) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 4944 | ironlake_pch_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4945 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 4946 | assert_vblank_disabled(crtc); |
| 4947 | drm_crtc_vblank_on(crtc); |
| 4948 | |
Daniel Vetter | fa5c73b | 2012-07-01 23:24:36 +0200 | [diff] [blame] | 4949 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4950 | encoder->enable(encoder); |
Daniel Vetter | 61b77dd | 2012-07-02 00:16:19 +0200 | [diff] [blame] | 4951 | |
| 4952 | if (HAS_PCH_CPT(dev)) |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 4953 | cpt_verify_modeset(dev, intel_crtc->pipe); |
Ville Syrjälä | 37ca8d4 | 2015-10-30 19:20:27 +0200 | [diff] [blame] | 4954 | |
| 4955 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ |
| 4956 | if (intel_crtc->config->has_pch_encoder) |
| 4957 | intel_wait_for_vblank(dev, pipe); |
| 4958 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 4959 | |
| 4960 | intel_fbc_enable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 4961 | } |
| 4962 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4963 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 4964 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
| 4965 | { |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 4966 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4967 | } |
| 4968 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4969 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
| 4970 | { |
| 4971 | struct drm_device *dev = crtc->dev; |
| 4972 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4974 | struct intel_encoder *encoder; |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 4975 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
| 4976 | struct intel_crtc_state *pipe_config = |
| 4977 | to_intel_crtc_state(crtc->state); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4978 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 4979 | if (WARN_ON(intel_crtc->active)) |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 4980 | return; |
| 4981 | |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 4982 | if (intel_crtc->config->has_pch_encoder) |
| 4983 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 4984 | false); |
| 4985 | |
Daniel Vetter | df8ad70 | 2014-06-25 22:02:03 +0300 | [diff] [blame] | 4986 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
| 4987 | intel_enable_shared_dpll(intel_crtc); |
| 4988 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4989 | if (intel_crtc->config->has_dp_encoder) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 4990 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 4991 | |
| 4992 | intel_set_pipe_timings(intel_crtc); |
| 4993 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4994 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
| 4995 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), |
| 4996 | intel_crtc->config->pixel_multiplier - 1); |
Clint Taylor | ebb69c9 | 2014-09-30 10:30:22 -0700 | [diff] [blame] | 4997 | } |
| 4998 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 4999 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5000 | intel_cpu_transcoder_set_m_n(intel_crtc, |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5001 | &intel_crtc->config->fdi_m_n, NULL); |
Daniel Vetter | 229fca9 | 2014-04-24 23:55:09 +0200 | [diff] [blame] | 5002 | } |
| 5003 | |
| 5004 | haswell_set_pipeconf(crtc); |
| 5005 | |
| 5006 | intel_set_pipe_csc(crtc); |
| 5007 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5008 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 5009 | |
Daniel Vetter | 6b69851 | 2015-11-28 11:05:39 +0100 | [diff] [blame] | 5010 | if (intel_crtc->config->has_pch_encoder) |
| 5011 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5012 | else |
| 5013 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5014 | |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5015 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5016 | if (encoder->pre_enable) |
| 5017 | encoder->pre_enable(encoder); |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5018 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5019 | |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5020 | if (intel_crtc->config->has_pch_encoder) |
Imre Deak | 4fe9467 | 2014-06-25 22:01:49 +0300 | [diff] [blame] | 5021 | dev_priv->display.fdi_link_train(crtc); |
Imre Deak | 4fe9467 | 2014-06-25 22:01:49 +0300 | [diff] [blame] | 5022 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 5023 | if (!intel_crtc->config->has_dsi_encoder) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5024 | intel_ddi_enable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5025 | |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 5026 | if (INTEL_INFO(dev)->gen >= 9) |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 5027 | skylake_pfit_enable(intel_crtc); |
Jesse Barnes | ff6d9f5 | 2015-01-21 17:19:54 -0800 | [diff] [blame] | 5028 | else |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 5029 | ironlake_pfit_enable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5030 | |
| 5031 | /* |
| 5032 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 5033 | * clocks enabled |
| 5034 | */ |
| 5035 | intel_crtc_load_lut(crtc); |
| 5036 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 5037 | intel_ddi_set_pipe_settings(crtc); |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 5038 | if (!intel_crtc->config->has_dsi_encoder) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5039 | intel_ddi_enable_transcoder_func(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5040 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 5041 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 5042 | intel_enable_pipe(intel_crtc); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 5043 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5044 | if (intel_crtc->config->has_pch_encoder) |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 5045 | lpt_pch_enable(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5046 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 5047 | if (intel_crtc->config->dp_encoder_is_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5048 | intel_ddi_set_vc_payload_alloc(crtc, true); |
| 5049 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5050 | assert_vblank_disabled(crtc); |
| 5051 | drm_crtc_vblank_on(crtc); |
| 5052 | |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 5053 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5054 | encoder->enable(encoder); |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 5055 | intel_opregion_notify_encoder(encoder, true); |
| 5056 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5057 | |
Daniel Vetter | 6b69851 | 2015-11-28 11:05:39 +0100 | [diff] [blame] | 5058 | if (intel_crtc->config->has_pch_encoder) { |
| 5059 | intel_wait_for_vblank(dev, pipe); |
| 5060 | intel_wait_for_vblank(dev, pipe); |
| 5061 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5062 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5063 | true); |
Daniel Vetter | 6b69851 | 2015-11-28 11:05:39 +0100 | [diff] [blame] | 5064 | } |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5065 | |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 5066 | /* If we change the relative order between pipe/planes enabling, we need |
| 5067 | * to change the workaround. */ |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 5068 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
| 5069 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
| 5070 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
| 5071 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
| 5072 | } |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 5073 | |
| 5074 | intel_fbc_enable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5075 | } |
| 5076 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5077 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 5078 | { |
| 5079 | struct drm_device *dev = crtc->base.dev; |
| 5080 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5081 | int pipe = crtc->pipe; |
| 5082 | |
| 5083 | /* To avoid upsetting the power well on haswell only disable the pfit if |
| 5084 | * it's in use. The hw state code will make sure we get this right. */ |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5085 | if (force || crtc->config->pch_pfit.enabled) { |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 5086 | I915_WRITE(PF_CTL(pipe), 0); |
| 5087 | I915_WRITE(PF_WIN_POS(pipe), 0); |
| 5088 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
| 5089 | } |
| 5090 | } |
| 5091 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5092 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 5093 | { |
| 5094 | struct drm_device *dev = crtc->dev; |
| 5095 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5096 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 5097 | struct intel_encoder *encoder; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5098 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5099 | |
Ville Syrjälä | 37ca8d4 | 2015-10-30 19:20:27 +0200 | [diff] [blame] | 5100 | if (intel_crtc->config->has_pch_encoder) |
| 5101 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5102 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 5103 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 5104 | encoder->disable(encoder); |
| 5105 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5106 | drm_crtc_vblank_off(crtc); |
| 5107 | assert_vblank_disabled(crtc); |
| 5108 | |
Ville Syrjälä | 3860b2e | 2015-11-20 22:09:18 +0200 | [diff] [blame] | 5109 | /* |
| 5110 | * Sometimes spurious CPU pipe underruns happen when the |
| 5111 | * pipe is already disabled, but FDI RX/TX is still enabled. |
| 5112 | * Happens at least with VGA+HDMI cloning. Suppress them. |
| 5113 | */ |
| 5114 | if (intel_crtc->config->has_pch_encoder) |
| 5115 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5116 | |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 5117 | intel_disable_pipe(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5118 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5119 | ironlake_pfit_disable(intel_crtc, false); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5120 | |
Ville Syrjälä | 3860b2e | 2015-11-20 22:09:18 +0200 | [diff] [blame] | 5121 | if (intel_crtc->config->has_pch_encoder) { |
Ville Syrjälä | 5a74f70 | 2015-05-05 17:17:38 +0300 | [diff] [blame] | 5122 | ironlake_fdi_disable(crtc); |
Ville Syrjälä | 3860b2e | 2015-11-20 22:09:18 +0200 | [diff] [blame] | 5123 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5124 | } |
Ville Syrjälä | 5a74f70 | 2015-05-05 17:17:38 +0300 | [diff] [blame] | 5125 | |
Daniel Vetter | bf49ec8 | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 5126 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 5127 | if (encoder->post_disable) |
| 5128 | encoder->post_disable(encoder); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5129 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5130 | if (intel_crtc->config->has_pch_encoder) { |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5131 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5132 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5133 | if (HAS_PCH_CPT(dev)) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5134 | i915_reg_t reg; |
| 5135 | u32 temp; |
| 5136 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5137 | /* disable TRANS_DP_CTL */ |
| 5138 | reg = TRANS_DP_CTL(pipe); |
| 5139 | temp = I915_READ(reg); |
| 5140 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
| 5141 | TRANS_DP_PORT_SEL_MASK); |
| 5142 | temp |= TRANS_DP_PORT_SEL_NONE; |
| 5143 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5144 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5145 | /* disable DPLL_SEL */ |
| 5146 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 5147 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5148 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 5149 | } |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5150 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 5151 | ironlake_fdi_pll_disable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5152 | } |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5153 | |
| 5154 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 5155 | |
| 5156 | intel_fbc_disable_crtc(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 5157 | } |
| 5158 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5159 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
| 5160 | { |
| 5161 | struct drm_device *dev = crtc->dev; |
| 5162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5164 | struct intel_encoder *encoder; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5165 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5166 | |
Ville Syrjälä | d2d6540 | 2015-10-29 21:25:53 +0200 | [diff] [blame] | 5167 | if (intel_crtc->config->has_pch_encoder) |
| 5168 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5169 | false); |
| 5170 | |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 5171 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 5172 | intel_opregion_notify_encoder(encoder, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5173 | encoder->disable(encoder); |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 5174 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5175 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 5176 | drm_crtc_vblank_off(crtc); |
| 5177 | assert_vblank_disabled(crtc); |
| 5178 | |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 5179 | intel_disable_pipe(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5180 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5181 | if (intel_crtc->config->dp_encoder_is_mst) |
Ville Syrjälä | a4bf214 | 2014-08-18 21:27:34 +0300 | [diff] [blame] | 5182 | intel_ddi_set_vc_payload_alloc(crtc, false); |
| 5183 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 5184 | if (!intel_crtc->config->has_dsi_encoder) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5185 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5186 | |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 5187 | if (INTEL_INFO(dev)->gen >= 9) |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 5188 | skylake_scaler_disable(intel_crtc); |
Jesse Barnes | ff6d9f5 | 2015-01-21 17:19:54 -0800 | [diff] [blame] | 5189 | else |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 5190 | ironlake_pfit_disable(intel_crtc, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5191 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 5192 | if (!intel_crtc->config->has_dsi_encoder) |
Shashank Sharma | 7d4aefd | 2015-10-01 22:23:49 +0530 | [diff] [blame] | 5193 | intel_ddi_disable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5194 | |
Imre Deak | 97b040a | 2014-06-25 22:01:50 +0300 | [diff] [blame] | 5195 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 5196 | if (encoder->post_disable) |
| 5197 | encoder->post_disable(encoder); |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5198 | |
Ville Syrjälä | 92966a3 | 2015-12-08 16:05:48 +0200 | [diff] [blame] | 5199 | if (intel_crtc->config->has_pch_encoder) { |
| 5200 | lpt_disable_pch_transcoder(dev_priv); |
Ville Syrjälä | 503a74e | 2015-12-04 22:22:14 +0200 | [diff] [blame] | 5201 | lpt_disable_iclkip(dev_priv); |
Ville Syrjälä | 92966a3 | 2015-12-08 16:05:48 +0200 | [diff] [blame] | 5202 | intel_ddi_fdi_disable(crtc); |
| 5203 | |
Ville Syrjälä | 81b088c | 2015-10-30 19:21:31 +0200 | [diff] [blame] | 5204 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5205 | true); |
Ville Syrjälä | 92966a3 | 2015-12-08 16:05:48 +0200 | [diff] [blame] | 5206 | } |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 5207 | |
| 5208 | intel_fbc_disable_crtc(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 5209 | } |
| 5210 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5211 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
| 5212 | { |
| 5213 | struct drm_device *dev = crtc->base.dev; |
| 5214 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5215 | struct intel_crtc_state *pipe_config = crtc->config; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5216 | |
Ander Conselvan de Oliveira | 681a850 | 2015-01-15 14:55:24 +0200 | [diff] [blame] | 5217 | if (!pipe_config->gmch_pfit.control) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5218 | return; |
| 5219 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 5220 | /* |
| 5221 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
| 5222 | * according to register description and PRM. |
| 5223 | */ |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5224 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
| 5225 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 5226 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 5227 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
| 5228 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
Daniel Vetter | 5a80c45 | 2013-04-25 22:52:18 +0200 | [diff] [blame] | 5229 | |
| 5230 | /* Border color in case we don't scale up to the full screen. Black by |
| 5231 | * default, change to something else for debugging. */ |
| 5232 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 5233 | } |
| 5234 | |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5235 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
| 5236 | { |
| 5237 | switch (port) { |
| 5238 | case PORT_A: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5239 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5240 | case PORT_B: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5241 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5242 | case PORT_C: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5243 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5244 | case PORT_D: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5245 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
Xiong Zhang | d8e19f9 | 2015-08-13 18:00:12 +0800 | [diff] [blame] | 5246 | case PORT_E: |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 5247 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5248 | default: |
Imre Deak | b9fec16 | 2015-11-18 15:57:25 +0200 | [diff] [blame] | 5249 | MISSING_CASE(port); |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5250 | return POWER_DOMAIN_PORT_OTHER; |
| 5251 | } |
| 5252 | } |
| 5253 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5254 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
| 5255 | { |
| 5256 | switch (port) { |
| 5257 | case PORT_A: |
| 5258 | return POWER_DOMAIN_AUX_A; |
| 5259 | case PORT_B: |
| 5260 | return POWER_DOMAIN_AUX_B; |
| 5261 | case PORT_C: |
| 5262 | return POWER_DOMAIN_AUX_C; |
| 5263 | case PORT_D: |
| 5264 | return POWER_DOMAIN_AUX_D; |
| 5265 | case PORT_E: |
| 5266 | /* FIXME: Check VBT for actual wiring of PORT E */ |
| 5267 | return POWER_DOMAIN_AUX_D; |
| 5268 | default: |
Imre Deak | b9fec16 | 2015-11-18 15:57:25 +0200 | [diff] [blame] | 5269 | MISSING_CASE(port); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5270 | return POWER_DOMAIN_AUX_A; |
| 5271 | } |
| 5272 | } |
| 5273 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5274 | enum intel_display_power_domain |
| 5275 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5276 | { |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5277 | struct drm_device *dev = intel_encoder->base.dev; |
| 5278 | struct intel_digital_port *intel_dig_port; |
| 5279 | |
| 5280 | switch (intel_encoder->type) { |
| 5281 | case INTEL_OUTPUT_UNKNOWN: |
| 5282 | /* Only DDI platforms should ever use this output type */ |
| 5283 | WARN_ON_ONCE(!HAS_DDI(dev)); |
| 5284 | case INTEL_OUTPUT_DISPLAYPORT: |
| 5285 | case INTEL_OUTPUT_HDMI: |
| 5286 | case INTEL_OUTPUT_EDP: |
| 5287 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
Dave Airlie | d05410f | 2014-06-05 13:22:59 +1000 | [diff] [blame] | 5288 | return port_to_power_domain(intel_dig_port->port); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5289 | case INTEL_OUTPUT_DP_MST: |
| 5290 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 5291 | return port_to_power_domain(intel_dig_port->port); |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5292 | case INTEL_OUTPUT_ANALOG: |
| 5293 | return POWER_DOMAIN_PORT_CRT; |
| 5294 | case INTEL_OUTPUT_DSI: |
| 5295 | return POWER_DOMAIN_PORT_DSI; |
| 5296 | default: |
| 5297 | return POWER_DOMAIN_PORT_OTHER; |
| 5298 | } |
| 5299 | } |
| 5300 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5301 | enum intel_display_power_domain |
| 5302 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) |
| 5303 | { |
| 5304 | struct drm_device *dev = intel_encoder->base.dev; |
| 5305 | struct intel_digital_port *intel_dig_port; |
| 5306 | |
| 5307 | switch (intel_encoder->type) { |
| 5308 | case INTEL_OUTPUT_UNKNOWN: |
Imre Deak | 651174a | 2015-11-18 15:57:24 +0200 | [diff] [blame] | 5309 | case INTEL_OUTPUT_HDMI: |
| 5310 | /* |
| 5311 | * Only DDI platforms should ever use these output types. |
| 5312 | * We can get here after the HDMI detect code has already set |
| 5313 | * the type of the shared encoder. Since we can't be sure |
| 5314 | * what's the status of the given connectors, play safe and |
| 5315 | * run the DP detection too. |
| 5316 | */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5317 | WARN_ON_ONCE(!HAS_DDI(dev)); |
| 5318 | case INTEL_OUTPUT_DISPLAYPORT: |
| 5319 | case INTEL_OUTPUT_EDP: |
| 5320 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 5321 | return port_to_aux_power_domain(intel_dig_port->port); |
| 5322 | case INTEL_OUTPUT_DP_MST: |
| 5323 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 5324 | return port_to_aux_power_domain(intel_dig_port->port); |
| 5325 | default: |
Imre Deak | b9fec16 | 2015-11-18 15:57:25 +0200 | [diff] [blame] | 5326 | MISSING_CASE(intel_encoder->type); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5327 | return POWER_DOMAIN_AUX_A; |
| 5328 | } |
| 5329 | } |
| 5330 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5331 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
| 5332 | { |
| 5333 | struct drm_device *dev = crtc->dev; |
| 5334 | struct intel_encoder *intel_encoder; |
| 5335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5336 | enum pipe pipe = intel_crtc->pipe; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5337 | unsigned long mask; |
Ville Syrjälä | 1a70a728 | 2015-10-29 21:25:50 +0200 | [diff] [blame] | 5338 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5339 | |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5340 | if (!crtc->state->active) |
| 5341 | return 0; |
| 5342 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5343 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
| 5344 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5345 | if (intel_crtc->config->pch_pfit.enabled || |
| 5346 | intel_crtc->config->pch_pfit.force_thru) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5347 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
| 5348 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5349 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 5350 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
| 5351 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5352 | return mask; |
| 5353 | } |
| 5354 | |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5355 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
| 5356 | { |
| 5357 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 5358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5359 | enum intel_display_power_domain domain; |
| 5360 | unsigned long domains, new_domains, old_domains; |
| 5361 | |
| 5362 | old_domains = intel_crtc->enabled_power_domains; |
| 5363 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); |
| 5364 | |
| 5365 | domains = new_domains & ~old_domains; |
| 5366 | |
| 5367 | for_each_power_domain(domain, domains) |
| 5368 | intel_display_power_get(dev_priv, domain); |
| 5369 | |
| 5370 | return old_domains & ~new_domains; |
| 5371 | } |
| 5372 | |
| 5373 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, |
| 5374 | unsigned long domains) |
| 5375 | { |
| 5376 | enum intel_display_power_domain domain; |
| 5377 | |
| 5378 | for_each_power_domain(domain, domains) |
| 5379 | intel_display_power_put(dev_priv, domain); |
| 5380 | } |
| 5381 | |
Ander Conselvan de Oliveira | 679dacd | 2015-03-20 16:18:15 +0200 | [diff] [blame] | 5382 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5383 | { |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 5384 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Ander Conselvan de Oliveira | 679dacd | 2015-03-20 16:18:15 +0200 | [diff] [blame] | 5385 | struct drm_device *dev = state->dev; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5386 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5387 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
| 5388 | struct drm_crtc_state *crtc_state; |
| 5389 | struct drm_crtc *crtc; |
| 5390 | int i; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5391 | |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5392 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 5393 | if (needs_modeset(crtc->state)) |
| 5394 | put_domains[to_intel_crtc(crtc)->pipe] = |
| 5395 | modeset_get_crtc_power_domains(crtc); |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5396 | } |
| 5397 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 5398 | if (dev_priv->display.modeset_commit_cdclk && |
| 5399 | intel_state->dev_cdclk != dev_priv->cdclk_freq) |
| 5400 | dev_priv->display.modeset_commit_cdclk(state); |
Ville Syrjälä | 50f6e50 | 2014-11-06 14:49:12 +0200 | [diff] [blame] | 5401 | |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 5402 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 5403 | if (put_domains[i]) |
| 5404 | modeset_put_power_domains(dev_priv, put_domains[i]); |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 5405 | } |
| 5406 | |
Mika Kahola | adafdc6 | 2015-08-18 14:36:59 +0300 | [diff] [blame] | 5407 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
| 5408 | { |
| 5409 | int max_cdclk_freq = dev_priv->max_cdclk_freq; |
| 5410 | |
| 5411 | if (INTEL_INFO(dev_priv)->gen >= 9 || |
| 5412 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 5413 | return max_cdclk_freq; |
| 5414 | else if (IS_CHERRYVIEW(dev_priv)) |
| 5415 | return max_cdclk_freq*95/100; |
| 5416 | else if (INTEL_INFO(dev_priv)->gen < 4) |
| 5417 | return 2*max_cdclk_freq*90/100; |
| 5418 | else |
| 5419 | return max_cdclk_freq*90/100; |
| 5420 | } |
| 5421 | |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5422 | static void intel_update_max_cdclk(struct drm_device *dev) |
| 5423 | { |
| 5424 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5425 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 5426 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5427 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
| 5428 | |
| 5429 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
| 5430 | dev_priv->max_cdclk_freq = 675000; |
| 5431 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
| 5432 | dev_priv->max_cdclk_freq = 540000; |
| 5433 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
| 5434 | dev_priv->max_cdclk_freq = 450000; |
| 5435 | else |
| 5436 | dev_priv->max_cdclk_freq = 337500; |
| 5437 | } else if (IS_BROADWELL(dev)) { |
| 5438 | /* |
| 5439 | * FIXME with extra cooling we can allow |
| 5440 | * 540 MHz for ULX and 675 Mhz for ULT. |
| 5441 | * How can we know if extra cooling is |
| 5442 | * available? PCI ID, VTB, something else? |
| 5443 | */ |
| 5444 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 5445 | dev_priv->max_cdclk_freq = 450000; |
| 5446 | else if (IS_BDW_ULX(dev)) |
| 5447 | dev_priv->max_cdclk_freq = 450000; |
| 5448 | else if (IS_BDW_ULT(dev)) |
| 5449 | dev_priv->max_cdclk_freq = 540000; |
| 5450 | else |
| 5451 | dev_priv->max_cdclk_freq = 675000; |
Mika Kahola | 0904dea | 2015-06-12 10:11:32 +0300 | [diff] [blame] | 5452 | } else if (IS_CHERRYVIEW(dev)) { |
| 5453 | dev_priv->max_cdclk_freq = 320000; |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5454 | } else if (IS_VALLEYVIEW(dev)) { |
| 5455 | dev_priv->max_cdclk_freq = 400000; |
| 5456 | } else { |
| 5457 | /* otherwise assume cdclk is fixed */ |
| 5458 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; |
| 5459 | } |
| 5460 | |
Mika Kahola | adafdc6 | 2015-08-18 14:36:59 +0300 | [diff] [blame] | 5461 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
| 5462 | |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5463 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
| 5464 | dev_priv->max_cdclk_freq); |
Mika Kahola | adafdc6 | 2015-08-18 14:36:59 +0300 | [diff] [blame] | 5465 | |
| 5466 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", |
| 5467 | dev_priv->max_dotclk_freq); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5468 | } |
| 5469 | |
| 5470 | static void intel_update_cdclk(struct drm_device *dev) |
| 5471 | { |
| 5472 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5473 | |
| 5474 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
| 5475 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
| 5476 | dev_priv->cdclk_freq); |
| 5477 | |
| 5478 | /* |
| 5479 | * Program the gmbus_freq based on the cdclk frequency. |
| 5480 | * BSpec erroneously claims we should aim for 4MHz, but |
| 5481 | * in fact 1MHz is the correct frequency. |
| 5482 | */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5483 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5484 | /* |
| 5485 | * Program the gmbus_freq based on the cdclk frequency. |
| 5486 | * BSpec erroneously claims we should aim for 4MHz, but |
| 5487 | * in fact 1MHz is the correct frequency. |
| 5488 | */ |
| 5489 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
| 5490 | } |
| 5491 | |
| 5492 | if (dev_priv->max_cdclk_freq == 0) |
| 5493 | intel_update_max_cdclk(dev); |
| 5494 | } |
| 5495 | |
Damien Lespiau | 70d0c57 | 2015-06-04 18:21:29 +0100 | [diff] [blame] | 5496 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5497 | { |
| 5498 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5499 | uint32_t divider; |
| 5500 | uint32_t ratio; |
| 5501 | uint32_t current_freq; |
| 5502 | int ret; |
| 5503 | |
| 5504 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ |
| 5505 | switch (frequency) { |
| 5506 | case 144000: |
| 5507 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
| 5508 | ratio = BXT_DE_PLL_RATIO(60); |
| 5509 | break; |
| 5510 | case 288000: |
| 5511 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
| 5512 | ratio = BXT_DE_PLL_RATIO(60); |
| 5513 | break; |
| 5514 | case 384000: |
| 5515 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
| 5516 | ratio = BXT_DE_PLL_RATIO(60); |
| 5517 | break; |
| 5518 | case 576000: |
| 5519 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 5520 | ratio = BXT_DE_PLL_RATIO(60); |
| 5521 | break; |
| 5522 | case 624000: |
| 5523 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 5524 | ratio = BXT_DE_PLL_RATIO(65); |
| 5525 | break; |
| 5526 | case 19200: |
| 5527 | /* |
| 5528 | * Bypass frequency with DE PLL disabled. Init ratio, divider |
| 5529 | * to suppress GCC warning. |
| 5530 | */ |
| 5531 | ratio = 0; |
| 5532 | divider = 0; |
| 5533 | break; |
| 5534 | default: |
| 5535 | DRM_ERROR("unsupported CDCLK freq %d", frequency); |
| 5536 | |
| 5537 | return; |
| 5538 | } |
| 5539 | |
| 5540 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5541 | /* Inform power controller of upcoming frequency change */ |
| 5542 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 5543 | 0x80000000); |
| 5544 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5545 | |
| 5546 | if (ret) { |
| 5547 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", |
| 5548 | ret, frequency); |
| 5549 | return; |
| 5550 | } |
| 5551 | |
| 5552 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; |
| 5553 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ |
| 5554 | current_freq = current_freq * 500 + 1000; |
| 5555 | |
| 5556 | /* |
| 5557 | * DE PLL has to be disabled when |
| 5558 | * - setting to 19.2MHz (bypass, PLL isn't used) |
| 5559 | * - before setting to 624MHz (PLL needs toggling) |
| 5560 | * - before setting to any frequency from 624MHz (PLL needs toggling) |
| 5561 | */ |
| 5562 | if (frequency == 19200 || frequency == 624000 || |
| 5563 | current_freq == 624000) { |
| 5564 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); |
| 5565 | /* Timeout 200us */ |
| 5566 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), |
| 5567 | 1)) |
| 5568 | DRM_ERROR("timout waiting for DE PLL unlock\n"); |
| 5569 | } |
| 5570 | |
| 5571 | if (frequency != 19200) { |
| 5572 | uint32_t val; |
| 5573 | |
| 5574 | val = I915_READ(BXT_DE_PLL_CTL); |
| 5575 | val &= ~BXT_DE_PLL_RATIO_MASK; |
| 5576 | val |= ratio; |
| 5577 | I915_WRITE(BXT_DE_PLL_CTL, val); |
| 5578 | |
| 5579 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); |
| 5580 | /* Timeout 200us */ |
| 5581 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) |
| 5582 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
| 5583 | |
| 5584 | val = I915_READ(CDCLK_CTL); |
| 5585 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; |
| 5586 | val |= divider; |
| 5587 | /* |
| 5588 | * Disable SSA Precharge when CD clock frequency < 500 MHz, |
| 5589 | * enable otherwise. |
| 5590 | */ |
| 5591 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 5592 | if (frequency >= 500000) |
| 5593 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 5594 | |
| 5595 | val &= ~CDCLK_FREQ_DECIMAL_MASK; |
| 5596 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
| 5597 | val |= (frequency - 1000) / 500; |
| 5598 | I915_WRITE(CDCLK_CTL, val); |
| 5599 | } |
| 5600 | |
| 5601 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5602 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 5603 | DIV_ROUND_UP(frequency, 25000)); |
| 5604 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5605 | |
| 5606 | if (ret) { |
| 5607 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", |
| 5608 | ret, frequency); |
| 5609 | return; |
| 5610 | } |
| 5611 | |
Damien Lespiau | a47871b | 2015-06-04 18:21:34 +0100 | [diff] [blame] | 5612 | intel_update_cdclk(dev); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5613 | } |
| 5614 | |
| 5615 | void broxton_init_cdclk(struct drm_device *dev) |
| 5616 | { |
| 5617 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5618 | uint32_t val; |
| 5619 | |
| 5620 | /* |
| 5621 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT |
| 5622 | * or else the reset will hang because there is no PCH to respond. |
| 5623 | * Move the handshake programming to initialization sequence. |
| 5624 | * Previously was left up to BIOS. |
| 5625 | */ |
| 5626 | val = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 5627 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 5628 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); |
| 5629 | |
| 5630 | /* Enable PG1 for cdclk */ |
| 5631 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 5632 | |
| 5633 | /* check if cd clock is enabled */ |
| 5634 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { |
| 5635 | DRM_DEBUG_KMS("Display already initialized\n"); |
| 5636 | return; |
| 5637 | } |
| 5638 | |
| 5639 | /* |
| 5640 | * FIXME: |
| 5641 | * - The initial CDCLK needs to be read from VBT. |
| 5642 | * Need to make this change after VBT has changes for BXT. |
| 5643 | * - check if setting the max (or any) cdclk freq is really necessary |
| 5644 | * here, it belongs to modeset time |
| 5645 | */ |
| 5646 | broxton_set_cdclk(dev, 624000); |
| 5647 | |
| 5648 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); |
Ville Syrjälä | 22e02c0 | 2015-05-06 14:28:57 +0300 | [diff] [blame] | 5649 | POSTING_READ(DBUF_CTL); |
| 5650 | |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5651 | udelay(10); |
| 5652 | |
| 5653 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
| 5654 | DRM_ERROR("DBuf power enable timeout!\n"); |
| 5655 | } |
| 5656 | |
| 5657 | void broxton_uninit_cdclk(struct drm_device *dev) |
| 5658 | { |
| 5659 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5660 | |
| 5661 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
Ville Syrjälä | 22e02c0 | 2015-05-06 14:28:57 +0300 | [diff] [blame] | 5662 | POSTING_READ(DBUF_CTL); |
| 5663 | |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 5664 | udelay(10); |
| 5665 | |
| 5666 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
| 5667 | DRM_ERROR("DBuf power disable timeout!\n"); |
| 5668 | |
| 5669 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ |
| 5670 | broxton_set_cdclk(dev, 19200); |
| 5671 | |
| 5672 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 5673 | } |
| 5674 | |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5675 | static const struct skl_cdclk_entry { |
| 5676 | unsigned int freq; |
| 5677 | unsigned int vco; |
| 5678 | } skl_cdclk_frequencies[] = { |
| 5679 | { .freq = 308570, .vco = 8640 }, |
| 5680 | { .freq = 337500, .vco = 8100 }, |
| 5681 | { .freq = 432000, .vco = 8640 }, |
| 5682 | { .freq = 450000, .vco = 8100 }, |
| 5683 | { .freq = 540000, .vco = 8100 }, |
| 5684 | { .freq = 617140, .vco = 8640 }, |
| 5685 | { .freq = 675000, .vco = 8100 }, |
| 5686 | }; |
| 5687 | |
| 5688 | static unsigned int skl_cdclk_decimal(unsigned int freq) |
| 5689 | { |
| 5690 | return (freq - 1000) / 500; |
| 5691 | } |
| 5692 | |
| 5693 | static unsigned int skl_cdclk_get_vco(unsigned int freq) |
| 5694 | { |
| 5695 | unsigned int i; |
| 5696 | |
| 5697 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { |
| 5698 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; |
| 5699 | |
| 5700 | if (e->freq == freq) |
| 5701 | return e->vco; |
| 5702 | } |
| 5703 | |
| 5704 | return 8100; |
| 5705 | } |
| 5706 | |
| 5707 | static void |
| 5708 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) |
| 5709 | { |
| 5710 | unsigned int min_freq; |
| 5711 | u32 val; |
| 5712 | |
| 5713 | /* select the minimum CDCLK before enabling DPLL 0 */ |
| 5714 | val = I915_READ(CDCLK_CTL); |
| 5715 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; |
| 5716 | val |= CDCLK_FREQ_337_308; |
| 5717 | |
| 5718 | if (required_vco == 8640) |
| 5719 | min_freq = 308570; |
| 5720 | else |
| 5721 | min_freq = 337500; |
| 5722 | |
| 5723 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); |
| 5724 | |
| 5725 | I915_WRITE(CDCLK_CTL, val); |
| 5726 | POSTING_READ(CDCLK_CTL); |
| 5727 | |
| 5728 | /* |
| 5729 | * We always enable DPLL0 with the lowest link rate possible, but still |
| 5730 | * taking into account the VCO required to operate the eDP panel at the |
| 5731 | * desired frequency. The usual DP link rates operate with a VCO of |
| 5732 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. |
| 5733 | * The modeset code is responsible for the selection of the exact link |
| 5734 | * rate later on, with the constraint of choosing a frequency that |
| 5735 | * works with required_vco. |
| 5736 | */ |
| 5737 | val = I915_READ(DPLL_CTRL1); |
| 5738 | |
| 5739 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | |
| 5740 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
| 5741 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
| 5742 | if (required_vco == 8640) |
| 5743 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
| 5744 | SKL_DPLL0); |
| 5745 | else |
| 5746 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
| 5747 | SKL_DPLL0); |
| 5748 | |
| 5749 | I915_WRITE(DPLL_CTRL1, val); |
| 5750 | POSTING_READ(DPLL_CTRL1); |
| 5751 | |
| 5752 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); |
| 5753 | |
| 5754 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) |
| 5755 | DRM_ERROR("DPLL0 not locked\n"); |
| 5756 | } |
| 5757 | |
| 5758 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
| 5759 | { |
| 5760 | int ret; |
| 5761 | u32 val; |
| 5762 | |
| 5763 | /* inform PCU we want to change CDCLK */ |
| 5764 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; |
| 5765 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5766 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); |
| 5767 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5768 | |
| 5769 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); |
| 5770 | } |
| 5771 | |
| 5772 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) |
| 5773 | { |
| 5774 | unsigned int i; |
| 5775 | |
| 5776 | for (i = 0; i < 15; i++) { |
| 5777 | if (skl_cdclk_pcu_ready(dev_priv)) |
| 5778 | return true; |
| 5779 | udelay(10); |
| 5780 | } |
| 5781 | |
| 5782 | return false; |
| 5783 | } |
| 5784 | |
| 5785 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) |
| 5786 | { |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5787 | struct drm_device *dev = dev_priv->dev; |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5788 | u32 freq_select, pcu_ack; |
| 5789 | |
| 5790 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); |
| 5791 | |
| 5792 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { |
| 5793 | DRM_ERROR("failed to inform PCU about cdclk change\n"); |
| 5794 | return; |
| 5795 | } |
| 5796 | |
| 5797 | /* set CDCLK_CTL */ |
| 5798 | switch(freq) { |
| 5799 | case 450000: |
| 5800 | case 432000: |
| 5801 | freq_select = CDCLK_FREQ_450_432; |
| 5802 | pcu_ack = 1; |
| 5803 | break; |
| 5804 | case 540000: |
| 5805 | freq_select = CDCLK_FREQ_540; |
| 5806 | pcu_ack = 2; |
| 5807 | break; |
| 5808 | case 308570: |
| 5809 | case 337500: |
| 5810 | default: |
| 5811 | freq_select = CDCLK_FREQ_337_308; |
| 5812 | pcu_ack = 0; |
| 5813 | break; |
| 5814 | case 617140: |
| 5815 | case 675000: |
| 5816 | freq_select = CDCLK_FREQ_675_617; |
| 5817 | pcu_ack = 3; |
| 5818 | break; |
| 5819 | } |
| 5820 | |
| 5821 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); |
| 5822 | POSTING_READ(CDCLK_CTL); |
| 5823 | |
| 5824 | /* inform PCU of the change */ |
| 5825 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5826 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); |
| 5827 | mutex_unlock(&dev_priv->rps.hw_lock); |
Damien Lespiau | 560a7ae | 2015-06-04 18:21:33 +0100 | [diff] [blame] | 5828 | |
| 5829 | intel_update_cdclk(dev); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5830 | } |
| 5831 | |
| 5832 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
| 5833 | { |
| 5834 | /* disable DBUF power */ |
| 5835 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
| 5836 | POSTING_READ(DBUF_CTL); |
| 5837 | |
| 5838 | udelay(10); |
| 5839 | |
| 5840 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
| 5841 | DRM_ERROR("DBuf power disable timeout\n"); |
| 5842 | |
Imre Deak | ab96c1ee | 2015-11-04 19:24:18 +0200 | [diff] [blame] | 5843 | /* disable DPLL0 */ |
| 5844 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); |
| 5845 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) |
| 5846 | DRM_ERROR("Couldn't disable DPLL0\n"); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5847 | } |
| 5848 | |
| 5849 | void skl_init_cdclk(struct drm_i915_private *dev_priv) |
| 5850 | { |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5851 | unsigned int required_vco; |
| 5852 | |
Gary Wang | 39d9b85 | 2015-08-28 16:40:34 +0800 | [diff] [blame] | 5853 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
| 5854 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { |
| 5855 | /* enable DPLL0 */ |
| 5856 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); |
| 5857 | skl_dpll0_enable(dev_priv, required_vco); |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5858 | } |
| 5859 | |
Damien Lespiau | 5d96d8a | 2015-05-21 16:37:48 +0100 | [diff] [blame] | 5860 | /* set CDCLK to the frequency the BIOS chose */ |
| 5861 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); |
| 5862 | |
| 5863 | /* enable DBUF power */ |
| 5864 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); |
| 5865 | POSTING_READ(DBUF_CTL); |
| 5866 | |
| 5867 | udelay(10); |
| 5868 | |
| 5869 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
| 5870 | DRM_ERROR("DBuf power enable timeout\n"); |
| 5871 | } |
| 5872 | |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 5873 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
| 5874 | { |
| 5875 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
| 5876 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 5877 | int freq = dev_priv->skl_boot_cdclk; |
| 5878 | |
Shobhit Kumar | f1b391a | 2015-11-05 18:05:32 +0530 | [diff] [blame] | 5879 | /* |
| 5880 | * check if the pre-os intialized the display |
| 5881 | * There is SWF18 scratchpad register defined which is set by the |
| 5882 | * pre-os which can be used by the OS drivers to check the status |
| 5883 | */ |
| 5884 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) |
| 5885 | goto sanitize; |
| 5886 | |
Shobhit Kumar | c73666f | 2015-10-20 18:13:12 +0530 | [diff] [blame] | 5887 | /* Is PLL enabled and locked ? */ |
| 5888 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) |
| 5889 | goto sanitize; |
| 5890 | |
| 5891 | /* DPLL okay; verify the cdclock |
| 5892 | * |
| 5893 | * Noticed in some instances that the freq selection is correct but |
| 5894 | * decimal part is programmed wrong from BIOS where pre-os does not |
| 5895 | * enable display. Verify the same as well. |
| 5896 | */ |
| 5897 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) |
| 5898 | /* All well; nothing to sanitize */ |
| 5899 | return false; |
| 5900 | sanitize: |
| 5901 | /* |
| 5902 | * As of now initialize with max cdclk till |
| 5903 | * we get dynamic cdclk support |
| 5904 | * */ |
| 5905 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; |
| 5906 | skl_init_cdclk(dev_priv); |
| 5907 | |
| 5908 | /* we did have to sanitize */ |
| 5909 | return true; |
| 5910 | } |
| 5911 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5912 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
| 5913 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
| 5914 | { |
| 5915 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5916 | u32 val, cmd; |
| 5917 | |
Vandana Kannan | 164dfd2 | 2014-11-24 13:37:41 +0530 | [diff] [blame] | 5918 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
| 5919 | != dev_priv->cdclk_freq); |
Imre Deak | d60c447 | 2014-03-27 17:45:10 +0200 | [diff] [blame] | 5920 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 5921 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5922 | cmd = 2; |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 5923 | else if (cdclk == 266667) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5924 | cmd = 1; |
| 5925 | else |
| 5926 | cmd = 0; |
| 5927 | |
| 5928 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5929 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 5930 | val &= ~DSPFREQGUAR_MASK; |
| 5931 | val |= (cmd << DSPFREQGUAR_SHIFT); |
| 5932 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 5933 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 5934 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
| 5935 | 50)) { |
| 5936 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 5937 | } |
| 5938 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5939 | |
Ville Syrjälä | 54433e9 | 2015-05-26 20:42:31 +0300 | [diff] [blame] | 5940 | mutex_lock(&dev_priv->sb_lock); |
| 5941 | |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 5942 | if (cdclk == 400000) { |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 5943 | u32 divider; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5944 | |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 5945 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5946 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5947 | /* adjust cdclk divider */ |
| 5948 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
Vandana Kannan | 87d5d25 | 2015-09-24 23:29:17 +0300 | [diff] [blame] | 5949 | val &= ~CCK_FREQUENCY_VALUES; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5950 | val |= divider; |
| 5951 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
Ville Syrjälä | a877e80 | 2014-06-13 13:37:52 +0300 | [diff] [blame] | 5952 | |
| 5953 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
Vandana Kannan | 87d5d25 | 2015-09-24 23:29:17 +0300 | [diff] [blame] | 5954 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
Ville Syrjälä | a877e80 | 2014-06-13 13:37:52 +0300 | [diff] [blame] | 5955 | 50)) |
| 5956 | DRM_ERROR("timed out waiting for CDclk change\n"); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5957 | } |
| 5958 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5959 | /* adjust self-refresh exit latency value */ |
| 5960 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
| 5961 | val &= ~0x7f; |
| 5962 | |
| 5963 | /* |
| 5964 | * For high bandwidth configs, we set a higher latency in the bunit |
| 5965 | * so that the core display fetch happens in time to avoid underruns. |
| 5966 | */ |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 5967 | if (cdclk == 400000) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5968 | val |= 4500 / 250; /* 4.5 usec */ |
| 5969 | else |
| 5970 | val |= 3000 / 250; /* 3.0 usec */ |
| 5971 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
Ville Syrjälä | 54433e9 | 2015-05-26 20:42:31 +0300 | [diff] [blame] | 5972 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 5973 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5974 | |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 5975 | intel_update_cdclk(dev); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 5976 | } |
| 5977 | |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5978 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
| 5979 | { |
| 5980 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5981 | u32 val, cmd; |
| 5982 | |
Vandana Kannan | 164dfd2 | 2014-11-24 13:37:41 +0530 | [diff] [blame] | 5983 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
| 5984 | != dev_priv->cdclk_freq); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5985 | |
| 5986 | switch (cdclk) { |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5987 | case 333333: |
| 5988 | case 320000: |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5989 | case 266667: |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5990 | case 200000: |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5991 | break; |
| 5992 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 5993 | MISSING_CASE(cdclk); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 5994 | return; |
| 5995 | } |
| 5996 | |
Ville Syrjälä | 9d0d3fd | 2015-03-02 20:07:17 +0200 | [diff] [blame] | 5997 | /* |
| 5998 | * Specs are full of misinformation, but testing on actual |
| 5999 | * hardware has shown that we just need to write the desired |
| 6000 | * CCK divider into the Punit register. |
| 6001 | */ |
| 6002 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
| 6003 | |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6004 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6005 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 6006 | val &= ~DSPFREQGUAR_MASK_CHV; |
| 6007 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); |
| 6008 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 6009 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 6010 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), |
| 6011 | 50)) { |
| 6012 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 6013 | } |
| 6014 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6015 | |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 6016 | intel_update_cdclk(dev); |
Ville Syrjälä | 383c5a6 | 2014-06-28 02:03:57 +0300 | [diff] [blame] | 6017 | } |
| 6018 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6019 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
| 6020 | int max_pixclk) |
| 6021 | { |
Ville Syrjälä | 6bcda4f | 2014-10-07 17:41:22 +0300 | [diff] [blame] | 6022 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6023 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 6024 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6025 | /* |
| 6026 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
| 6027 | * 200MHz |
| 6028 | * 267MHz |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 6029 | * 320/333MHz (depends on HPLL freq) |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6030 | * 400MHz (VLV only) |
| 6031 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) |
| 6032 | * of the lower bin and adjust if needed. |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 6033 | * |
| 6034 | * We seem to get an unstable or solid color picture at 200MHz. |
| 6035 | * Not sure what's wrong. For now use 200MHz only when all pipes |
| 6036 | * are off. |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6037 | */ |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6038 | if (!IS_CHERRYVIEW(dev_priv) && |
| 6039 | max_pixclk > freq_320*limit/100) |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6040 | return 400000; |
Ville Syrjälä | 6cca319 | 2015-03-02 20:07:16 +0200 | [diff] [blame] | 6041 | else if (max_pixclk > 266667*limit/100) |
Ville Syrjälä | 29dc7ef | 2014-06-13 13:37:50 +0300 | [diff] [blame] | 6042 | return freq_320; |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 6043 | else if (max_pixclk > 0) |
Ville Syrjälä | dfcab17 | 2014-06-13 13:37:47 +0300 | [diff] [blame] | 6044 | return 266667; |
Ville Syrjälä | e37c67a | 2014-06-13 13:37:51 +0300 | [diff] [blame] | 6045 | else |
| 6046 | return 200000; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6047 | } |
| 6048 | |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6049 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
| 6050 | int max_pixclk) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6051 | { |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6052 | /* |
| 6053 | * FIXME: |
| 6054 | * - remove the guardband, it's not needed on BXT |
| 6055 | * - set 19.2MHz bypass frequency if there are no active pipes |
| 6056 | */ |
| 6057 | if (max_pixclk > 576000*9/10) |
| 6058 | return 624000; |
| 6059 | else if (max_pixclk > 384000*9/10) |
| 6060 | return 576000; |
| 6061 | else if (max_pixclk > 288000*9/10) |
| 6062 | return 384000; |
| 6063 | else if (max_pixclk > 144000*9/10) |
| 6064 | return 288000; |
| 6065 | else |
| 6066 | return 144000; |
| 6067 | } |
| 6068 | |
Ander Conselvan de Oliveira | a821fc4 | 2015-04-21 17:13:23 +0300 | [diff] [blame] | 6069 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
| 6070 | * that's non-NULL, look at current state otherwise. */ |
| 6071 | static int intel_mode_max_pixclk(struct drm_device *dev, |
| 6072 | struct drm_atomic_state *state) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6073 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6074 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 6075 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6076 | struct drm_crtc *crtc; |
| 6077 | struct drm_crtc_state *crtc_state; |
| 6078 | unsigned max_pixclk = 0, i; |
| 6079 | enum pipe pipe; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6080 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6081 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 6082 | sizeof(intel_state->min_pixclk)); |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6083 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6084 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 6085 | int pixclk = 0; |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6086 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6087 | if (crtc_state->enable) |
| 6088 | pixclk = crtc_state->adjusted_mode.crtc_clock; |
| 6089 | |
| 6090 | intel_state->min_pixclk[i] = pixclk; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6091 | } |
| 6092 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6093 | if (!intel_state->active_crtcs) |
| 6094 | return 0; |
| 6095 | |
| 6096 | for_each_pipe(dev_priv, pipe) |
| 6097 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); |
| 6098 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6099 | return max_pixclk; |
| 6100 | } |
| 6101 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6102 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6103 | { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6104 | struct drm_device *dev = state->dev; |
| 6105 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6106 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6107 | struct intel_atomic_state *intel_state = |
| 6108 | to_intel_atomic_state(state); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6109 | |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6110 | if (max_pixclk < 0) |
| 6111 | return max_pixclk; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6112 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6113 | intel_state->cdclk = intel_state->dev_cdclk = |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6114 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 6115 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6116 | if (!intel_state->active_crtcs) |
| 6117 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); |
| 6118 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6119 | return 0; |
| 6120 | } |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6121 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6122 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 6123 | { |
| 6124 | struct drm_device *dev = state->dev; |
| 6125 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6126 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6127 | struct intel_atomic_state *intel_state = |
| 6128 | to_intel_atomic_state(state); |
Maarten Lankhorst | 85a96e7 | 2015-06-01 12:49:53 +0200 | [diff] [blame] | 6129 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6130 | if (max_pixclk < 0) |
| 6131 | return max_pixclk; |
Maarten Lankhorst | 85a96e7 | 2015-06-01 12:49:53 +0200 | [diff] [blame] | 6132 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6133 | intel_state->cdclk = intel_state->dev_cdclk = |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6134 | broxton_calc_cdclk(dev_priv, max_pixclk); |
Maarten Lankhorst | 85a96e7 | 2015-06-01 12:49:53 +0200 | [diff] [blame] | 6135 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6136 | if (!intel_state->active_crtcs) |
| 6137 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); |
| 6138 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6139 | return 0; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6140 | } |
| 6141 | |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 6142 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
| 6143 | { |
| 6144 | unsigned int credits, default_credits; |
| 6145 | |
| 6146 | if (IS_CHERRYVIEW(dev_priv)) |
| 6147 | default_credits = PFI_CREDIT(12); |
| 6148 | else |
| 6149 | default_credits = PFI_CREDIT(8); |
| 6150 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 6151 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 6152 | /* CHV suggested value is 31 or 63 */ |
| 6153 | if (IS_CHERRYVIEW(dev_priv)) |
Ville Syrjälä | fcc0008 | 2015-05-26 20:22:40 +0300 | [diff] [blame] | 6154 | credits = PFI_CREDIT_63; |
Vidya Srinivas | 1e69cd7 | 2015-03-05 21:19:50 +0200 | [diff] [blame] | 6155 | else |
| 6156 | credits = PFI_CREDIT(15); |
| 6157 | } else { |
| 6158 | credits = default_credits; |
| 6159 | } |
| 6160 | |
| 6161 | /* |
| 6162 | * WA - write default credits before re-programming |
| 6163 | * FIXME: should we also set the resend bit here? |
| 6164 | */ |
| 6165 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 6166 | default_credits); |
| 6167 | |
| 6168 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 6169 | credits | PFI_CREDIT_RESEND); |
| 6170 | |
| 6171 | /* |
| 6172 | * FIXME is this guaranteed to clear |
| 6173 | * immediately or should we poll for it? |
| 6174 | */ |
| 6175 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); |
| 6176 | } |
| 6177 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6178 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6179 | { |
Ander Conselvan de Oliveira | a821fc4 | 2015-04-21 17:13:23 +0300 | [diff] [blame] | 6180 | struct drm_device *dev = old_state->dev; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6181 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 6182 | struct intel_atomic_state *old_intel_state = |
| 6183 | to_intel_atomic_state(old_state); |
| 6184 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6185 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6186 | /* |
| 6187 | * FIXME: We can end up here with all power domains off, yet |
| 6188 | * with a CDCLK frequency other than the minimum. To account |
| 6189 | * for this take the PIPE-A power domain, which covers the HW |
| 6190 | * blocks needed for the following programming. This can be |
| 6191 | * removed once it's guaranteed that we get here either with |
| 6192 | * the minimum CDCLK set, or the required power domains |
| 6193 | * enabled. |
| 6194 | */ |
| 6195 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); |
Ander Conselvan de Oliveira | 304603f | 2015-04-02 14:47:56 +0300 | [diff] [blame] | 6196 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6197 | if (IS_CHERRYVIEW(dev)) |
| 6198 | cherryview_set_cdclk(dev, req_cdclk); |
| 6199 | else |
| 6200 | valleyview_set_cdclk(dev, req_cdclk); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6201 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6202 | vlv_program_pfi_credits(dev_priv); |
Imre Deak | 738c05c | 2014-11-19 16:25:37 +0200 | [diff] [blame] | 6203 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 6204 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 6205 | } |
| 6206 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6207 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
| 6208 | { |
| 6209 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6210 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6211 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6212 | struct intel_encoder *encoder; |
| 6213 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6214 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 6215 | if (WARN_ON(intel_crtc->active)) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6216 | return; |
| 6217 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6218 | if (intel_crtc->config->has_dp_encoder) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 6219 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6220 | |
| 6221 | intel_set_pipe_timings(intel_crtc); |
| 6222 | |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 6223 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
| 6224 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6225 | |
| 6226 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
| 6227 | I915_WRITE(CHV_CANVAS(pipe), 0); |
| 6228 | } |
| 6229 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6230 | i9xx_set_pipeconf(intel_crtc); |
| 6231 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6232 | intel_crtc->active = true; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6233 | |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6234 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6235 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6236 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6237 | if (encoder->pre_pll_enable) |
| 6238 | encoder->pre_pll_enable(encoder); |
| 6239 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 6240 | if (!intel_crtc->config->has_dsi_encoder) { |
Ville Syrjälä | c0b4c66 | 2015-07-08 23:45:52 +0300 | [diff] [blame] | 6241 | if (IS_CHERRYVIEW(dev)) { |
| 6242 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6243 | chv_enable_pll(intel_crtc, intel_crtc->config); |
Ville Syrjälä | c0b4c66 | 2015-07-08 23:45:52 +0300 | [diff] [blame] | 6244 | } else { |
| 6245 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6246 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
Ville Syrjälä | c0b4c66 | 2015-07-08 23:45:52 +0300 | [diff] [blame] | 6247 | } |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 6248 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6249 | |
| 6250 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6251 | if (encoder->pre_enable) |
| 6252 | encoder->pre_enable(encoder); |
| 6253 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 6254 | i9xx_pfit_enable(intel_crtc); |
| 6255 | |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 6256 | intel_crtc_load_lut(crtc); |
| 6257 | |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 6258 | intel_enable_pipe(intel_crtc); |
Daniel Vetter | be6a6f8 | 2014-04-15 18:41:22 +0200 | [diff] [blame] | 6259 | |
Ville Syrjälä | 4b3a952 | 2014-08-14 22:04:37 +0300 | [diff] [blame] | 6260 | assert_vblank_disabled(crtc); |
| 6261 | drm_crtc_vblank_on(crtc); |
| 6262 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 6263 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6264 | encoder->enable(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6265 | } |
| 6266 | |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6267 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
| 6268 | { |
| 6269 | struct drm_device *dev = crtc->base.dev; |
| 6270 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6271 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6272 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
| 6273 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6274 | } |
| 6275 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6276 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6277 | { |
| 6278 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6279 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 6281 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6282 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6283 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 6284 | if (WARN_ON(intel_crtc->active)) |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 6285 | return; |
| 6286 | |
Daniel Vetter | f13c2ef | 2014-04-24 23:55:10 +0200 | [diff] [blame] | 6287 | i9xx_set_pll_dividers(intel_crtc); |
| 6288 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6289 | if (intel_crtc->config->has_dp_encoder) |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 6290 | intel_dp_set_m_n(intel_crtc, M1_N1); |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6291 | |
| 6292 | intel_set_pipe_timings(intel_crtc); |
| 6293 | |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 6294 | i9xx_set_pipeconf(intel_crtc); |
| 6295 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 6296 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 6297 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6298 | if (!IS_GEN2(dev)) |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6299 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6300 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 6301 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Mika Kuoppala | 9d6d9f1 | 2013-02-08 16:35:38 +0200 | [diff] [blame] | 6302 | if (encoder->pre_enable) |
| 6303 | encoder->pre_enable(encoder); |
| 6304 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 6305 | i9xx_enable_pll(intel_crtc); |
| 6306 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 6307 | i9xx_pfit_enable(intel_crtc); |
| 6308 | |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 6309 | intel_crtc_load_lut(crtc); |
| 6310 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 6311 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 6312 | intel_enable_pipe(intel_crtc); |
Daniel Vetter | be6a6f8 | 2014-04-15 18:41:22 +0200 | [diff] [blame] | 6313 | |
Ville Syrjälä | 4b3a952 | 2014-08-14 22:04:37 +0300 | [diff] [blame] | 6314 | assert_vblank_disabled(crtc); |
| 6315 | drm_crtc_vblank_on(crtc); |
| 6316 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 6317 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6318 | encoder->enable(encoder); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 6319 | |
| 6320 | intel_fbc_enable(intel_crtc); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6321 | } |
| 6322 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6323 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
| 6324 | { |
| 6325 | struct drm_device *dev = crtc->base.dev; |
| 6326 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 6327 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 6328 | if (!crtc->config->gmch_pfit.control) |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 6329 | return; |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6330 | |
| 6331 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 6332 | |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 6333 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
| 6334 | I915_READ(PFIT_CONTROL)); |
| 6335 | I915_WRITE(PFIT_CONTROL, 0); |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6336 | } |
| 6337 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6338 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 6339 | { |
| 6340 | struct drm_device *dev = crtc->dev; |
| 6341 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6342 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 6343 | struct intel_encoder *encoder; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6344 | int pipe = intel_crtc->pipe; |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 6345 | |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 6346 | /* |
| 6347 | * On gen2 planes are double buffered but the pipe isn't, so we must |
| 6348 | * wait for planes to fully turn off before disabling the pipe. |
Imre Deak | 564ed19 | 2014-06-13 14:54:21 +0300 | [diff] [blame] | 6349 | * We also need to wait on all gmch platforms because of the |
| 6350 | * self-refresh mode constraint explained above. |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 6351 | */ |
Imre Deak | 564ed19 | 2014-06-13 14:54:21 +0300 | [diff] [blame] | 6352 | intel_wait_for_vblank(dev, pipe); |
Ville Syrjälä | 6304cd9 | 2014-04-25 13:30:12 +0300 | [diff] [blame] | 6353 | |
Ville Syrjälä | 4b3a952 | 2014-08-14 22:04:37 +0300 | [diff] [blame] | 6354 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6355 | encoder->disable(encoder); |
| 6356 | |
Daniel Vetter | f9b61ff | 2015-01-07 13:54:39 +0100 | [diff] [blame] | 6357 | drm_crtc_vblank_off(crtc); |
| 6358 | assert_vblank_disabled(crtc); |
| 6359 | |
Ville Syrjälä | 575f7ab | 2014-08-15 01:21:56 +0300 | [diff] [blame] | 6360 | intel_disable_pipe(intel_crtc); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 6361 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 6362 | i9xx_pfit_disable(intel_crtc); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 6363 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 6364 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6365 | if (encoder->post_disable) |
| 6366 | encoder->post_disable(encoder); |
| 6367 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 6368 | if (!intel_crtc->config->has_dsi_encoder) { |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 6369 | if (IS_CHERRYVIEW(dev)) |
| 6370 | chv_disable_pll(dev_priv, pipe); |
| 6371 | else if (IS_VALLEYVIEW(dev)) |
| 6372 | vlv_disable_pll(dev_priv, pipe); |
| 6373 | else |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 6374 | i9xx_disable_pll(intel_crtc); |
Chon Ming Lee | 076ed3b | 2014-04-09 13:28:17 +0300 | [diff] [blame] | 6375 | } |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6376 | |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 6377 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6378 | if (encoder->post_pll_disable) |
| 6379 | encoder->post_pll_disable(encoder); |
| 6380 | |
Ville Syrjälä | 4a3436e | 2014-05-16 19:40:25 +0300 | [diff] [blame] | 6381 | if (!IS_GEN2(dev)) |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 6382 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 6383 | |
| 6384 | intel_fbc_disable_crtc(intel_crtc); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 6385 | } |
| 6386 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6387 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6388 | { |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6389 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6390 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6391 | enum intel_display_power_domain domain; |
| 6392 | unsigned long domains; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 6393 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6394 | if (!intel_crtc->active) |
| 6395 | return; |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6396 | |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 6397 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
Maarten Lankhorst | fc32b1f | 2015-10-19 17:09:23 +0200 | [diff] [blame] | 6398 | WARN_ON(intel_crtc->unpin_work); |
| 6399 | |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 6400 | intel_pre_disable_primary(crtc); |
Maarten Lankhorst | 54a41961 | 2015-11-23 10:25:28 +0100 | [diff] [blame] | 6401 | |
| 6402 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
| 6403 | to_intel_plane_state(crtc->primary->state)->visible = false; |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 6404 | } |
| 6405 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6406 | dev_priv->display.crtc_disable(crtc); |
Matt Roper | 37d9078 | 2015-09-24 15:53:06 -0700 | [diff] [blame] | 6407 | intel_crtc->active = false; |
| 6408 | intel_update_watermarks(crtc); |
Maarten Lankhorst | 1f7457b | 2015-07-13 11:55:05 +0200 | [diff] [blame] | 6409 | intel_disable_shared_dpll(intel_crtc); |
Daniel Vetter | 0e572fe | 2014-04-24 23:55:42 +0200 | [diff] [blame] | 6410 | |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6411 | domains = intel_crtc->enabled_power_domains; |
| 6412 | for_each_power_domain(domain, domains) |
| 6413 | intel_display_power_put(dev_priv, domain); |
| 6414 | intel_crtc->enabled_power_domains = 0; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 6415 | |
| 6416 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); |
| 6417 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 6418 | } |
| 6419 | |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6420 | /* |
| 6421 | * turn all crtc's off, but do not adjust state |
| 6422 | * This has to be paired with a call to intel_modeset_setup_hw_state. |
| 6423 | */ |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6424 | int intel_display_suspend(struct drm_device *dev) |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6425 | { |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6426 | struct drm_mode_config *config = &dev->mode_config; |
| 6427 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; |
| 6428 | struct drm_atomic_state *state; |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6429 | struct drm_crtc *crtc; |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6430 | unsigned crtc_mask = 0; |
| 6431 | int ret = 0; |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6432 | |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6433 | if (WARN_ON(!ctx)) |
| 6434 | return 0; |
| 6435 | |
| 6436 | lockdep_assert_held(&ctx->ww_ctx); |
| 6437 | state = drm_atomic_state_alloc(dev); |
| 6438 | if (WARN_ON(!state)) |
| 6439 | return -ENOMEM; |
| 6440 | |
| 6441 | state->acquire_ctx = ctx; |
| 6442 | state->allow_modeset = true; |
| 6443 | |
| 6444 | for_each_crtc(dev, crtc) { |
| 6445 | struct drm_crtc_state *crtc_state = |
| 6446 | drm_atomic_get_crtc_state(state, crtc); |
| 6447 | |
| 6448 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 6449 | if (ret) |
| 6450 | goto free; |
| 6451 | |
| 6452 | if (!crtc_state->active) |
| 6453 | continue; |
| 6454 | |
| 6455 | crtc_state->active = false; |
| 6456 | crtc_mask |= 1 << drm_crtc_index(crtc); |
| 6457 | } |
| 6458 | |
| 6459 | if (crtc_mask) { |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 6460 | ret = drm_atomic_commit(state); |
Maarten Lankhorst | 70e0bd7 | 2015-07-13 16:30:29 +0200 | [diff] [blame] | 6461 | |
| 6462 | if (!ret) { |
| 6463 | for_each_crtc(dev, crtc) |
| 6464 | if (crtc_mask & (1 << drm_crtc_index(crtc))) |
| 6465 | crtc->state->active = true; |
| 6466 | |
| 6467 | return ret; |
| 6468 | } |
| 6469 | } |
| 6470 | |
| 6471 | free: |
| 6472 | if (ret) |
| 6473 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
| 6474 | drm_atomic_state_free(state); |
| 6475 | return ret; |
Maarten Lankhorst | 6b72d48 | 2015-06-01 12:49:47 +0200 | [diff] [blame] | 6476 | } |
| 6477 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 6478 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 6479 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6480 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 6481 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 6482 | drm_encoder_cleanup(encoder); |
| 6483 | kfree(intel_encoder); |
| 6484 | } |
| 6485 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6486 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
| 6487 | * internal consistency). */ |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 6488 | static void intel_connector_check_state(struct intel_connector *connector) |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6489 | { |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6490 | struct drm_crtc *crtc = connector->base.state->crtc; |
| 6491 | |
| 6492 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 6493 | connector->base.base.id, |
| 6494 | connector->base.name); |
| 6495 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6496 | if (connector->get_hw_state(connector)) { |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6497 | struct intel_encoder *encoder = connector->encoder; |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6498 | struct drm_connector_state *conn_state = connector->base.state; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6499 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6500 | I915_STATE_WARN(!crtc, |
| 6501 | "connector enabled without attached crtc\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6502 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6503 | if (!crtc) |
| 6504 | return; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6505 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6506 | I915_STATE_WARN(!crtc->state->active, |
| 6507 | "connector is active, but attached crtc isn't\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6508 | |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6509 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6510 | return; |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6511 | |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6512 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6513 | "atomic encoder doesn't match attached encoder\n"); |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 6514 | |
Maarten Lankhorst | e85376c | 2015-08-27 13:13:31 +0200 | [diff] [blame] | 6515 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6516 | "attached encoder crtc differs from connector crtc\n"); |
| 6517 | } else { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 6518 | I915_STATE_WARN(crtc && crtc->state->active, |
| 6519 | "attached crtc is active, but connector isn't\n"); |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 6520 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
| 6521 | "best encoder set without crtc!\n"); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 6522 | } |
| 6523 | } |
| 6524 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 6525 | int intel_connector_init(struct intel_connector *connector) |
| 6526 | { |
| 6527 | struct drm_connector_state *connector_state; |
| 6528 | |
| 6529 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); |
| 6530 | if (!connector_state) |
| 6531 | return -ENOMEM; |
| 6532 | |
| 6533 | connector->base.state = connector_state; |
| 6534 | return 0; |
| 6535 | } |
| 6536 | |
| 6537 | struct intel_connector *intel_connector_alloc(void) |
| 6538 | { |
| 6539 | struct intel_connector *connector; |
| 6540 | |
| 6541 | connector = kzalloc(sizeof *connector, GFP_KERNEL); |
| 6542 | if (!connector) |
| 6543 | return NULL; |
| 6544 | |
| 6545 | if (intel_connector_init(connector) < 0) { |
| 6546 | kfree(connector); |
| 6547 | return NULL; |
| 6548 | } |
| 6549 | |
| 6550 | return connector; |
| 6551 | } |
| 6552 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 6553 | /* Simple connector->get_hw_state implementation for encoders that support only |
| 6554 | * one connector and no cloning and hence the encoder state determines the state |
| 6555 | * of the connector. */ |
| 6556 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
| 6557 | { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 6558 | enum pipe pipe = 0; |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 6559 | struct intel_encoder *encoder = connector->encoder; |
| 6560 | |
| 6561 | return encoder->get_hw_state(encoder, &pipe); |
| 6562 | } |
| 6563 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6564 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
Ville Syrjälä | d272ddf | 2015-03-11 18:52:31 +0200 | [diff] [blame] | 6565 | { |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6566 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
| 6567 | return crtc_state->fdi_lanes; |
Ville Syrjälä | d272ddf | 2015-03-11 18:52:31 +0200 | [diff] [blame] | 6568 | |
| 6569 | return 0; |
| 6570 | } |
| 6571 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6572 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 6573 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6574 | { |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6575 | struct drm_atomic_state *state = pipe_config->base.state; |
| 6576 | struct intel_crtc *other_crtc; |
| 6577 | struct intel_crtc_state *other_crtc_state; |
| 6578 | |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6579 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
| 6580 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 6581 | if (pipe_config->fdi_lanes > 4) { |
| 6582 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
| 6583 | pipe_name(pipe), pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6584 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6585 | } |
| 6586 | |
Paulo Zanoni | bafb655 | 2013-11-02 21:07:44 -0700 | [diff] [blame] | 6587 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6588 | if (pipe_config->fdi_lanes > 2) { |
| 6589 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
| 6590 | pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6591 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6592 | } else { |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6593 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6594 | } |
| 6595 | } |
| 6596 | |
| 6597 | if (INTEL_INFO(dev)->num_pipes == 2) |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6598 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6599 | |
| 6600 | /* Ivybridge 3 pipe is really complicated */ |
| 6601 | switch (pipe) { |
| 6602 | case PIPE_A: |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6603 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6604 | case PIPE_B: |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6605 | if (pipe_config->fdi_lanes <= 2) |
| 6606 | return 0; |
| 6607 | |
| 6608 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); |
| 6609 | other_crtc_state = |
| 6610 | intel_atomic_get_crtc_state(state, other_crtc); |
| 6611 | if (IS_ERR(other_crtc_state)) |
| 6612 | return PTR_ERR(other_crtc_state); |
| 6613 | |
| 6614 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6615 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 6616 | pipe_name(pipe), pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6617 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6618 | } |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6619 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6620 | case PIPE_C: |
Ville Syrjälä | 251cc67 | 2015-03-11 18:52:30 +0200 | [diff] [blame] | 6621 | if (pipe_config->fdi_lanes > 2) { |
| 6622 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", |
| 6623 | pipe_name(pipe), pipe_config->fdi_lanes); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6624 | return -EINVAL; |
Ville Syrjälä | 251cc67 | 2015-03-11 18:52:30 +0200 | [diff] [blame] | 6625 | } |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6626 | |
| 6627 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); |
| 6628 | other_crtc_state = |
| 6629 | intel_atomic_get_crtc_state(state, other_crtc); |
| 6630 | if (IS_ERR(other_crtc_state)) |
| 6631 | return PTR_ERR(other_crtc_state); |
| 6632 | |
| 6633 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6634 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6635 | return -EINVAL; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6636 | } |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6637 | return 0; |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6638 | default: |
| 6639 | BUG(); |
| 6640 | } |
| 6641 | } |
| 6642 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 6643 | #define RETRY 1 |
| 6644 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 6645 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6646 | { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6647 | struct drm_device *dev = intel_crtc->base.dev; |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 6648 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6649 | int lane, link_bw, fdi_dotclock, ret; |
| 6650 | bool needs_recompute = false; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6651 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 6652 | retry: |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6653 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 6654 | * each output octet as 10 bits. The actual frequency |
| 6655 | * is stored as a divider into a 100MHz clock, and the |
| 6656 | * mode pixel clock is stored in units of 1KHz. |
| 6657 | * Hence the bw of each lane in terms of the mode signal |
| 6658 | * is: |
| 6659 | */ |
| 6660 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
| 6661 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 6662 | fdi_dotclock = adjusted_mode->crtc_clock; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6663 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 6664 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6665 | pipe_config->pipe_bpp); |
| 6666 | |
| 6667 | pipe_config->fdi_lanes = lane; |
| 6668 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 6669 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6670 | link_bw, &pipe_config->fdi_m_n); |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6671 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6672 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
| 6673 | intel_crtc->pipe, pipe_config); |
| 6674 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 6675 | pipe_config->pipe_bpp -= 2*3; |
| 6676 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
| 6677 | pipe_config->pipe_bpp); |
| 6678 | needs_recompute = true; |
| 6679 | pipe_config->bw_constrained = true; |
| 6680 | |
| 6681 | goto retry; |
| 6682 | } |
| 6683 | |
| 6684 | if (needs_recompute) |
| 6685 | return RETRY; |
| 6686 | |
Ander Conselvan de Oliveira | 6d29398 | 2015-03-30 08:33:12 +0300 | [diff] [blame] | 6687 | return ret; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6688 | } |
| 6689 | |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 6690 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
| 6691 | struct intel_crtc_state *pipe_config) |
| 6692 | { |
| 6693 | if (pipe_config->pipe_bpp > 24) |
| 6694 | return false; |
| 6695 | |
| 6696 | /* HSW can handle pixel rate up to cdclk? */ |
| 6697 | if (IS_HASWELL(dev_priv->dev)) |
| 6698 | return true; |
| 6699 | |
| 6700 | /* |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 6701 | * We compare against max which means we must take |
| 6702 | * the increased cdclk requirement into account when |
| 6703 | * calculating the new cdclk. |
| 6704 | * |
| 6705 | * Should measure whether using a lower cdclk w/o IPS |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 6706 | */ |
| 6707 | return ilk_pipe_pixel_rate(pipe_config) <= |
| 6708 | dev_priv->max_cdclk_freq * 95 / 100; |
| 6709 | } |
| 6710 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 6711 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 6712 | struct intel_crtc_state *pipe_config) |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 6713 | { |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 6714 | struct drm_device *dev = crtc->base.dev; |
| 6715 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6716 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 6717 | pipe_config->ips_enabled = i915.enable_ips && |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 6718 | hsw_crtc_supports_ips(crtc) && |
| 6719 | pipe_config_supports_ips(dev_priv, pipe_config); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 6720 | } |
| 6721 | |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 6722 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
| 6723 | { |
| 6724 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 6725 | |
| 6726 | /* GDG double wide on either pipe, otherwise pipe A only */ |
| 6727 | return INTEL_INFO(dev_priv)->gen < 4 && |
| 6728 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); |
| 6729 | } |
| 6730 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 6731 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 6732 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6733 | { |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 6734 | struct drm_device *dev = crtc->base.dev; |
Ander Conselvan de Oliveira | 8bd31e6 | 2014-10-29 11:32:33 +0200 | [diff] [blame] | 6735 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 6736 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 6737 | |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 6738 | /* FIXME should check pixel clock limits on all platforms */ |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 6739 | if (INTEL_INFO(dev)->gen < 4) { |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 6740 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 6741 | |
| 6742 | /* |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 6743 | * Enable double wide mode when the dot clock |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 6744 | * is > 90% of the (display) core speed. |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 6745 | */ |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 6746 | if (intel_crtc_supports_double_wide(crtc) && |
| 6747 | adjusted_mode->crtc_clock > clock_limit) { |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 6748 | clock_limit *= 2; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 6749 | pipe_config->double_wide = true; |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 6750 | } |
| 6751 | |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 6752 | if (adjusted_mode->crtc_clock > clock_limit) { |
| 6753 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", |
| 6754 | adjusted_mode->crtc_clock, clock_limit, |
| 6755 | yesno(pipe_config->double_wide)); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 6756 | return -EINVAL; |
Ville Syrjälä | 39acb4a | 2015-10-30 23:39:38 +0200 | [diff] [blame] | 6757 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6758 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 6759 | |
Ville Syrjälä | 1d1d0e2 | 2013-09-04 18:30:05 +0300 | [diff] [blame] | 6760 | /* |
| 6761 | * Pipe horizontal size must be even in: |
| 6762 | * - DVO ganged mode |
| 6763 | * - LVDS dual channel mode |
| 6764 | * - Double wide pipe |
| 6765 | */ |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 6766 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
Ville Syrjälä | 1d1d0e2 | 2013-09-04 18:30:05 +0300 | [diff] [blame] | 6767 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
| 6768 | pipe_config->pipe_src_w &= ~1; |
| 6769 | |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 6770 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
| 6771 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 6772 | */ |
| 6773 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 6774 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 6775 | return -EINVAL; |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 6776 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 6777 | if (HAS_IPS(dev)) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 6778 | hsw_compute_ips_config(crtc, pipe_config); |
| 6779 | |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6780 | if (pipe_config->has_pch_encoder) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 6781 | return ironlake_fdi_compute_config(crtc, pipe_config); |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 6782 | |
Maarten Lankhorst | cf5a15b | 2015-06-15 12:33:41 +0200 | [diff] [blame] | 6783 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6784 | } |
| 6785 | |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 6786 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
| 6787 | { |
| 6788 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 6789 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
| 6790 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 6791 | uint32_t linkrate; |
| 6792 | |
Damien Lespiau | 414355a | 2015-06-04 18:21:31 +0100 | [diff] [blame] | 6793 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 6794 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 6795 | |
| 6796 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) |
| 6797 | return 540000; |
| 6798 | |
| 6799 | linkrate = (I915_READ(DPLL_CTRL1) & |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 6800 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 6801 | |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 6802 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
| 6803 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 6804 | /* vco 8640 */ |
| 6805 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 6806 | case CDCLK_FREQ_450_432: |
| 6807 | return 432000; |
| 6808 | case CDCLK_FREQ_337_308: |
| 6809 | return 308570; |
| 6810 | case CDCLK_FREQ_675_617: |
| 6811 | return 617140; |
| 6812 | default: |
| 6813 | WARN(1, "Unknown cd freq selection\n"); |
| 6814 | } |
| 6815 | } else { |
| 6816 | /* vco 8100 */ |
| 6817 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 6818 | case CDCLK_FREQ_450_432: |
| 6819 | return 450000; |
| 6820 | case CDCLK_FREQ_337_308: |
| 6821 | return 337500; |
| 6822 | case CDCLK_FREQ_675_617: |
| 6823 | return 675000; |
| 6824 | default: |
| 6825 | WARN(1, "Unknown cd freq selection\n"); |
| 6826 | } |
| 6827 | } |
| 6828 | |
| 6829 | /* error case, do as if DPLL0 isn't enabled */ |
| 6830 | return 24000; |
| 6831 | } |
| 6832 | |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 6833 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
| 6834 | { |
| 6835 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 6836 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 6837 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; |
| 6838 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); |
| 6839 | int cdclk; |
| 6840 | |
| 6841 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) |
| 6842 | return 19200; |
| 6843 | |
| 6844 | cdclk = 19200 * pll_ratio / 2; |
| 6845 | |
| 6846 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { |
| 6847 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
| 6848 | return cdclk; /* 576MHz or 624MHz */ |
| 6849 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
| 6850 | return cdclk * 2 / 3; /* 384MHz */ |
| 6851 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
| 6852 | return cdclk / 2; /* 288MHz */ |
| 6853 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
| 6854 | return cdclk / 4; /* 144MHz */ |
| 6855 | } |
| 6856 | |
| 6857 | /* error case, do as if DE PLL isn't enabled */ |
| 6858 | return 19200; |
| 6859 | } |
| 6860 | |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 6861 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
| 6862 | { |
| 6863 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6864 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 6865 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 6866 | |
| 6867 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 6868 | return 800000; |
| 6869 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 6870 | return 450000; |
| 6871 | else if (freq == LCPLL_CLK_FREQ_450) |
| 6872 | return 450000; |
| 6873 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
| 6874 | return 540000; |
| 6875 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
| 6876 | return 337500; |
| 6877 | else |
| 6878 | return 675000; |
| 6879 | } |
| 6880 | |
| 6881 | static int haswell_get_display_clock_speed(struct drm_device *dev) |
| 6882 | { |
| 6883 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6884 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 6885 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 6886 | |
| 6887 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 6888 | return 800000; |
| 6889 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 6890 | return 450000; |
| 6891 | else if (freq == LCPLL_CLK_FREQ_450) |
| 6892 | return 450000; |
| 6893 | else if (IS_HSW_ULT(dev)) |
| 6894 | return 337500; |
| 6895 | else |
| 6896 | return 540000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6897 | } |
| 6898 | |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 6899 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
| 6900 | { |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 6901 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
| 6902 | CCK_DISPLAY_CLOCK_CONTROL); |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 6903 | } |
| 6904 | |
Ville Syrjälä | b37a643 | 2015-03-31 14:11:54 +0300 | [diff] [blame] | 6905 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
| 6906 | { |
| 6907 | return 450000; |
| 6908 | } |
| 6909 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6910 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6911 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6912 | return 400000; |
| 6913 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6914 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6915 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 6916 | { |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6917 | return 333333; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6918 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6919 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6920 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 6921 | { |
| 6922 | return 200000; |
| 6923 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6924 | |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 6925 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
| 6926 | { |
| 6927 | u16 gcfgc = 0; |
| 6928 | |
| 6929 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 6930 | |
| 6931 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 6932 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6933 | return 266667; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 6934 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6935 | return 333333; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 6936 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6937 | return 444444; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 6938 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
| 6939 | return 200000; |
| 6940 | default: |
| 6941 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
| 6942 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6943 | return 133333; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 6944 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6945 | return 166667; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 6946 | } |
| 6947 | } |
| 6948 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6949 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 6950 | { |
| 6951 | u16 gcfgc = 0; |
| 6952 | |
| 6953 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 6954 | |
| 6955 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6956 | return 133333; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6957 | else { |
| 6958 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 6959 | case GC_DISPLAY_CLOCK_333_MHZ: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6960 | return 333333; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6961 | default: |
| 6962 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 6963 | return 190000; |
| 6964 | } |
| 6965 | } |
| 6966 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6967 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6968 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 6969 | { |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6970 | return 266667; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6971 | } |
| 6972 | |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 6973 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6974 | { |
| 6975 | u16 hpllcc = 0; |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 6976 | |
Ville Syrjälä | 65cd2b3 | 2015-05-22 11:22:32 +0300 | [diff] [blame] | 6977 | /* |
| 6978 | * 852GM/852GMV only supports 133 MHz and the HPLLCC |
| 6979 | * encoding is different :( |
| 6980 | * FIXME is this the right way to detect 852GM/852GMV? |
| 6981 | */ |
| 6982 | if (dev->pdev->revision == 0x1) |
| 6983 | return 133333; |
| 6984 | |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 6985 | pci_bus_read_config_word(dev->pdev->bus, |
| 6986 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
| 6987 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6988 | /* Assume that the hardware is in the high speed state. This |
| 6989 | * should be the default. |
| 6990 | */ |
| 6991 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 6992 | case GC_CLOCK_133_200: |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 6993 | case GC_CLOCK_133_200_2: |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6994 | case GC_CLOCK_100_200: |
| 6995 | return 200000; |
| 6996 | case GC_CLOCK_166_250: |
| 6997 | return 250000; |
| 6998 | case GC_CLOCK_100_133: |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 6999 | return 133333; |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 7000 | case GC_CLOCK_133_266: |
| 7001 | case GC_CLOCK_133_266_2: |
| 7002 | case GC_CLOCK_166_266: |
| 7003 | return 266667; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 7004 | } |
| 7005 | |
| 7006 | /* Shouldn't happen */ |
| 7007 | return 0; |
| 7008 | } |
| 7009 | |
| 7010 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 7011 | { |
Ville Syrjälä | e907f17 | 2015-03-31 14:09:47 +0300 | [diff] [blame] | 7012 | return 133333; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7013 | } |
| 7014 | |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7015 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
| 7016 | { |
| 7017 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7018 | static const unsigned int blb_vco[8] = { |
| 7019 | [0] = 3200000, |
| 7020 | [1] = 4000000, |
| 7021 | [2] = 5333333, |
| 7022 | [3] = 4800000, |
| 7023 | [4] = 6400000, |
| 7024 | }; |
| 7025 | static const unsigned int pnv_vco[8] = { |
| 7026 | [0] = 3200000, |
| 7027 | [1] = 4000000, |
| 7028 | [2] = 5333333, |
| 7029 | [3] = 4800000, |
| 7030 | [4] = 2666667, |
| 7031 | }; |
| 7032 | static const unsigned int cl_vco[8] = { |
| 7033 | [0] = 3200000, |
| 7034 | [1] = 4000000, |
| 7035 | [2] = 5333333, |
| 7036 | [3] = 6400000, |
| 7037 | [4] = 3333333, |
| 7038 | [5] = 3566667, |
| 7039 | [6] = 4266667, |
| 7040 | }; |
| 7041 | static const unsigned int elk_vco[8] = { |
| 7042 | [0] = 3200000, |
| 7043 | [1] = 4000000, |
| 7044 | [2] = 5333333, |
| 7045 | [3] = 4800000, |
| 7046 | }; |
| 7047 | static const unsigned int ctg_vco[8] = { |
| 7048 | [0] = 3200000, |
| 7049 | [1] = 4000000, |
| 7050 | [2] = 5333333, |
| 7051 | [3] = 6400000, |
| 7052 | [4] = 2666667, |
| 7053 | [5] = 4266667, |
| 7054 | }; |
| 7055 | const unsigned int *vco_table; |
| 7056 | unsigned int vco; |
| 7057 | uint8_t tmp = 0; |
| 7058 | |
| 7059 | /* FIXME other chipsets? */ |
| 7060 | if (IS_GM45(dev)) |
| 7061 | vco_table = ctg_vco; |
| 7062 | else if (IS_G4X(dev)) |
| 7063 | vco_table = elk_vco; |
| 7064 | else if (IS_CRESTLINE(dev)) |
| 7065 | vco_table = cl_vco; |
| 7066 | else if (IS_PINEVIEW(dev)) |
| 7067 | vco_table = pnv_vco; |
| 7068 | else if (IS_G33(dev)) |
| 7069 | vco_table = blb_vco; |
| 7070 | else |
| 7071 | return 0; |
| 7072 | |
| 7073 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); |
| 7074 | |
| 7075 | vco = vco_table[tmp & 0x7]; |
| 7076 | if (vco == 0) |
| 7077 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); |
| 7078 | else |
| 7079 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); |
| 7080 | |
| 7081 | return vco; |
| 7082 | } |
| 7083 | |
| 7084 | static int gm45_get_display_clock_speed(struct drm_device *dev) |
| 7085 | { |
| 7086 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7087 | uint16_t tmp = 0; |
| 7088 | |
| 7089 | pci_read_config_word(dev->pdev, GCFGC, &tmp); |
| 7090 | |
| 7091 | cdclk_sel = (tmp >> 12) & 0x1; |
| 7092 | |
| 7093 | switch (vco) { |
| 7094 | case 2666667: |
| 7095 | case 4000000: |
| 7096 | case 5333333: |
| 7097 | return cdclk_sel ? 333333 : 222222; |
| 7098 | case 3200000: |
| 7099 | return cdclk_sel ? 320000 : 228571; |
| 7100 | default: |
| 7101 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); |
| 7102 | return 222222; |
| 7103 | } |
| 7104 | } |
| 7105 | |
| 7106 | static int i965gm_get_display_clock_speed(struct drm_device *dev) |
| 7107 | { |
| 7108 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
| 7109 | static const uint8_t div_4000[] = { 20, 12, 10 }; |
| 7110 | static const uint8_t div_5333[] = { 24, 16, 14 }; |
| 7111 | const uint8_t *div_table; |
| 7112 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7113 | uint16_t tmp = 0; |
| 7114 | |
| 7115 | pci_read_config_word(dev->pdev, GCFGC, &tmp); |
| 7116 | |
| 7117 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; |
| 7118 | |
| 7119 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 7120 | goto fail; |
| 7121 | |
| 7122 | switch (vco) { |
| 7123 | case 3200000: |
| 7124 | div_table = div_3200; |
| 7125 | break; |
| 7126 | case 4000000: |
| 7127 | div_table = div_4000; |
| 7128 | break; |
| 7129 | case 5333333: |
| 7130 | div_table = div_5333; |
| 7131 | break; |
| 7132 | default: |
| 7133 | goto fail; |
| 7134 | } |
| 7135 | |
| 7136 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 7137 | |
Damien Lespiau | caf4e25 | 2015-06-04 16:56:18 +0100 | [diff] [blame] | 7138 | fail: |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7139 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
| 7140 | return 200000; |
| 7141 | } |
| 7142 | |
| 7143 | static int g33_get_display_clock_speed(struct drm_device *dev) |
| 7144 | { |
| 7145 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
| 7146 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; |
| 7147 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; |
| 7148 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; |
| 7149 | const uint8_t *div_table; |
| 7150 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7151 | uint16_t tmp = 0; |
| 7152 | |
| 7153 | pci_read_config_word(dev->pdev, GCFGC, &tmp); |
| 7154 | |
| 7155 | cdclk_sel = (tmp >> 4) & 0x7; |
| 7156 | |
| 7157 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 7158 | goto fail; |
| 7159 | |
| 7160 | switch (vco) { |
| 7161 | case 3200000: |
| 7162 | div_table = div_3200; |
| 7163 | break; |
| 7164 | case 4000000: |
| 7165 | div_table = div_4000; |
| 7166 | break; |
| 7167 | case 4800000: |
| 7168 | div_table = div_4800; |
| 7169 | break; |
| 7170 | case 5333333: |
| 7171 | div_table = div_5333; |
| 7172 | break; |
| 7173 | default: |
| 7174 | goto fail; |
| 7175 | } |
| 7176 | |
| 7177 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 7178 | |
Damien Lespiau | caf4e25 | 2015-06-04 16:56:18 +0100 | [diff] [blame] | 7179 | fail: |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 7180 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
| 7181 | return 190476; |
| 7182 | } |
| 7183 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7184 | static void |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7185 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7186 | { |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7187 | while (*num > DATA_LINK_M_N_MASK || |
| 7188 | *den > DATA_LINK_M_N_MASK) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7189 | *num >>= 1; |
| 7190 | *den >>= 1; |
| 7191 | } |
| 7192 | } |
| 7193 | |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7194 | static void compute_m_n(unsigned int m, unsigned int n, |
| 7195 | uint32_t *ret_m, uint32_t *ret_n) |
| 7196 | { |
| 7197 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
| 7198 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
| 7199 | intel_reduce_m_n_ratio(ret_m, ret_n); |
| 7200 | } |
| 7201 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 7202 | void |
| 7203 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
| 7204 | int pixel_clock, int link_clock, |
| 7205 | struct intel_link_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7206 | { |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 7207 | m_n->tu = 64; |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 7208 | |
| 7209 | compute_m_n(bits_per_pixel * pixel_clock, |
| 7210 | link_clock * nlanes * 8, |
| 7211 | &m_n->gmch_m, &m_n->gmch_n); |
| 7212 | |
| 7213 | compute_m_n(pixel_clock, link_clock, |
| 7214 | &m_n->link_m, &m_n->link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 7215 | } |
| 7216 | |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 7217 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 7218 | { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 7219 | if (i915.panel_use_ssc >= 0) |
| 7220 | return i915.panel_use_ssc != 0; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 7221 | return dev_priv->vbt.lvds_use_ssc |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 7222 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 7223 | } |
| 7224 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7225 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
| 7226 | int num_connectors) |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7227 | { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7228 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7229 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7230 | int refclk; |
| 7231 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7232 | WARN_ON(!crtc_state->base.state); |
| 7233 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 7234 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
Daniel Vetter | 9a0ea49 | 2013-09-16 11:29:34 +0200 | [diff] [blame] | 7235 | refclk = 100000; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7236 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7237 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 7238 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 7239 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7240 | } else if (!IS_GEN2(dev)) { |
| 7241 | refclk = 96000; |
| 7242 | } else { |
| 7243 | refclk = 48000; |
| 7244 | } |
| 7245 | |
| 7246 | return refclk; |
| 7247 | } |
| 7248 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7249 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7250 | { |
Daniel Vetter | 7df00d7 | 2013-05-21 21:54:55 +0200 | [diff] [blame] | 7251 | return (1 << dpll->n) << 16 | dpll->m2; |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7252 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7253 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7254 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
| 7255 | { |
| 7256 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 7257 | } |
| 7258 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7259 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7260 | struct intel_crtc_state *crtc_state, |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7261 | intel_clock_t *reduced_clock) |
| 7262 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7263 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7264 | u32 fp, fp2 = 0; |
| 7265 | |
| 7266 | if (IS_PINEVIEW(dev)) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7267 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7268 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7269 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7270 | } else { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7271 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7272 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 7273 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7274 | } |
| 7275 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7276 | crtc_state->dpll_hw_state.fp0 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7277 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7278 | crtc->lowfreq_avail = false; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7279 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Rodrigo Vivi | ab585de | 2015-03-24 12:40:09 -0700 | [diff] [blame] | 7280 | reduced_clock) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7281 | crtc_state->dpll_hw_state.fp1 = fp2; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7282 | crtc->lowfreq_avail = true; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7283 | } else { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7284 | crtc_state->dpll_hw_state.fp1 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 7285 | } |
| 7286 | } |
| 7287 | |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 7288 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
| 7289 | pipe) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7290 | { |
| 7291 | u32 reg_val; |
| 7292 | |
| 7293 | /* |
| 7294 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
| 7295 | * and set it to a reasonable value instead. |
| 7296 | */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7297 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7298 | reg_val &= 0xffffff00; |
| 7299 | reg_val |= 0x00000030; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7300 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7301 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7302 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7303 | reg_val &= 0x8cffffff; |
| 7304 | reg_val = 0x8c000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7305 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7306 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7307 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7308 | reg_val &= 0xffffff00; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7309 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7310 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7311 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7312 | reg_val &= 0x00ffffff; |
| 7313 | reg_val |= 0xb0000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7314 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7315 | } |
| 7316 | |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7317 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
| 7318 | struct intel_link_m_n *m_n) |
| 7319 | { |
| 7320 | struct drm_device *dev = crtc->base.dev; |
| 7321 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7322 | int pipe = crtc->pipe; |
| 7323 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 7324 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7325 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
| 7326 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
| 7327 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7328 | } |
| 7329 | |
| 7330 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 7331 | struct intel_link_m_n *m_n, |
| 7332 | struct intel_link_m_n *m2_n2) |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7333 | { |
| 7334 | struct drm_device *dev = crtc->base.dev; |
| 7335 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7336 | int pipe = crtc->pipe; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7337 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7338 | |
| 7339 | if (INTEL_INFO(dev)->gen >= 5) { |
| 7340 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7341 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
| 7342 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
| 7343 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 7344 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
| 7345 | * for gen < 8) and if DRRS is supported (to make sure the |
| 7346 | * registers are not unnecessarily accessed). |
| 7347 | */ |
Durgadoss R | 44395bf | 2015-02-13 15:33:02 +0530 | [diff] [blame] | 7348 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7349 | crtc->config->has_drrs) { |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 7350 | I915_WRITE(PIPE_DATA_M2(transcoder), |
| 7351 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); |
| 7352 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); |
| 7353 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); |
| 7354 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); |
| 7355 | } |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7356 | } else { |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 7357 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7358 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
| 7359 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
| 7360 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 7361 | } |
| 7362 | } |
| 7363 | |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 7364 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7365 | { |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 7366 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
| 7367 | |
| 7368 | if (m_n == M1_N1) { |
| 7369 | dp_m_n = &crtc->config->dp_m_n; |
| 7370 | dp_m2_n2 = &crtc->config->dp_m2_n2; |
| 7371 | } else if (m_n == M2_N2) { |
| 7372 | |
| 7373 | /* |
| 7374 | * M2_N2 registers are not supported. Hence m2_n2 divider value |
| 7375 | * needs to be programmed into M1_N1. |
| 7376 | */ |
| 7377 | dp_m_n = &crtc->config->dp_m2_n2; |
| 7378 | } else { |
| 7379 | DRM_ERROR("Unsupported divider value\n"); |
| 7380 | return; |
| 7381 | } |
| 7382 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7383 | if (crtc->config->has_pch_encoder) |
| 7384 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7385 | else |
Ramalingam C | fe3cd48 | 2015-02-13 15:32:59 +0530 | [diff] [blame] | 7386 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7387 | } |
| 7388 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7389 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
| 7390 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7391 | { |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7392 | u32 dpll, dpll_md; |
| 7393 | |
| 7394 | /* |
| 7395 | * Enable DPIO clock input. We should never disable the reference |
| 7396 | * clock for pipe B, since VGA hotplug / manual detection depends |
| 7397 | * on it. |
| 7398 | */ |
Ville Syrjälä | 60bfe44 | 2015-06-29 15:25:49 +0300 | [diff] [blame] | 7399 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
| 7400 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7401 | /* We should never disable this, set it here for state tracking */ |
| 7402 | if (crtc->pipe == PIPE_B) |
| 7403 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 7404 | dpll |= DPLL_VCO_ENABLE; |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7405 | pipe_config->dpll_hw_state.dpll = dpll; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7406 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7407 | dpll_md = (pipe_config->pixel_multiplier - 1) |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7408 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7409 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7410 | } |
| 7411 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7412 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7413 | const struct intel_crtc_state *pipe_config) |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7414 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7415 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7416 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7417 | int pipe = crtc->pipe; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7418 | u32 mdiv; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7419 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7420 | u32 coreclk, reg_val; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7421 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 7422 | mutex_lock(&dev_priv->sb_lock); |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 7423 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7424 | bestn = pipe_config->dpll.n; |
| 7425 | bestm1 = pipe_config->dpll.m1; |
| 7426 | bestm2 = pipe_config->dpll.m2; |
| 7427 | bestp1 = pipe_config->dpll.p1; |
| 7428 | bestp2 = pipe_config->dpll.p2; |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7429 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7430 | /* See eDP HDMI DPIO driver vbios notes doc */ |
| 7431 | |
| 7432 | /* PLL B needs special handling */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7433 | if (pipe == PIPE_B) |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 7434 | vlv_pllb_recal_opamp(dev_priv, pipe); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7435 | |
| 7436 | /* Set up Tx target for periodic Rcomp update */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7437 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7438 | |
| 7439 | /* Disable target IRef on PLL */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7440 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7441 | reg_val &= 0x00ffffff; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7442 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7443 | |
| 7444 | /* Disable fast lock */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7445 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7446 | |
| 7447 | /* Set idtafcrecal before PLL is enabled */ |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7448 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
| 7449 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
| 7450 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7451 | mdiv |= (1 << DPIO_K_SHIFT); |
Jesse Barnes | 7df5080 | 2013-05-02 10:48:09 -0700 | [diff] [blame] | 7452 | |
| 7453 | /* |
| 7454 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| 7455 | * but we don't support that). |
| 7456 | * Note: don't use the DAC post divider as it seems unstable. |
| 7457 | */ |
| 7458 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7459 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7460 | |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7461 | mdiv |= DPIO_ENABLE_CALIBRATION; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7462 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7463 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7464 | /* Set HBR and RBR LPF coefficients */ |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7465 | if (pipe_config->port_clock == 162000 || |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 7466 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
| 7467 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7468 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Ville Syrjälä | 885b0120 | 2013-07-05 19:21:38 +0300 | [diff] [blame] | 7469 | 0x009f0003); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7470 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7471 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7472 | 0x00d0000f); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7473 | |
Ander Conselvan de Oliveira | 681a850 | 2015-01-15 14:55:24 +0200 | [diff] [blame] | 7474 | if (pipe_config->has_dp_encoder) { |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7475 | /* Use SSC source */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7476 | if (pipe == PIPE_A) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7477 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7478 | 0x0df40000); |
| 7479 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7480 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7481 | 0x0df70000); |
| 7482 | } else { /* HDMI or VGA */ |
| 7483 | /* Use bend source */ |
Daniel Vetter | bdd4b6a | 2014-04-24 23:55:11 +0200 | [diff] [blame] | 7484 | if (pipe == PIPE_A) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7485 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7486 | 0x0df70000); |
| 7487 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7488 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7489 | 0x0df40000); |
| 7490 | } |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7491 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7492 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7493 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 7494 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 7495 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7496 | coreclk |= 0x01000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7497 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 7498 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 7499 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 7500 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | a0c4da24 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 7501 | } |
| 7502 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7503 | static void chv_compute_dpll(struct intel_crtc *crtc, |
| 7504 | struct intel_crtc_state *pipe_config) |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7505 | { |
Ville Syrjälä | 60bfe44 | 2015-06-29 15:25:49 +0300 | [diff] [blame] | 7506 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
| 7507 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 7508 | DPLL_VCO_ENABLE; |
| 7509 | if (crtc->pipe != PIPE_A) |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7510 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 7511 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7512 | pipe_config->dpll_hw_state.dpll_md = |
| 7513 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 7514 | } |
| 7515 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7516 | static void chv_prepare_pll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7517 | const struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 1ae0d13 | 2014-06-28 02:04:00 +0300 | [diff] [blame] | 7518 | { |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7519 | struct drm_device *dev = crtc->base.dev; |
| 7520 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7521 | int pipe = crtc->pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 7522 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7523 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7524 | u32 loopfilter, tribuf_calcntr; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7525 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
Vijay Purushothaman | a945ce7e | 2015-03-05 19:30:57 +0530 | [diff] [blame] | 7526 | u32 dpio_val; |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7527 | int vco; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7528 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7529 | bestn = pipe_config->dpll.n; |
| 7530 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; |
| 7531 | bestm1 = pipe_config->dpll.m1; |
| 7532 | bestm2 = pipe_config->dpll.m2 >> 22; |
| 7533 | bestp1 = pipe_config->dpll.p1; |
| 7534 | bestp2 = pipe_config->dpll.p2; |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7535 | vco = pipe_config->dpll.vco; |
Vijay Purushothaman | a945ce7e | 2015-03-05 19:30:57 +0530 | [diff] [blame] | 7536 | dpio_val = 0; |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7537 | loopfilter = 0; |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7538 | |
| 7539 | /* |
| 7540 | * Enable Refclk and SSC |
| 7541 | */ |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 7542 | I915_WRITE(dpll_reg, |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7543 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
Ville Syrjälä | a11b070 | 2014-04-09 13:28:57 +0300 | [diff] [blame] | 7544 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 7545 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7546 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7547 | /* p1 and p2 divider */ |
| 7548 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
| 7549 | 5 << DPIO_CHV_S1_DIV_SHIFT | |
| 7550 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | |
| 7551 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | |
| 7552 | 1 << DPIO_CHV_K_DIV_SHIFT); |
| 7553 | |
| 7554 | /* Feedback post-divider - m2 */ |
| 7555 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); |
| 7556 | |
| 7557 | /* Feedback refclk divider - n and m1 */ |
| 7558 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), |
| 7559 | DPIO_CHV_M1_DIV_BY_2 | |
| 7560 | 1 << DPIO_CHV_N_DIV_SHIFT); |
| 7561 | |
| 7562 | /* M2 fraction division */ |
Ville Syrjälä | 25a25df | 2015-07-08 23:45:47 +0300 | [diff] [blame] | 7563 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7564 | |
| 7565 | /* M2 fraction division enable */ |
Vijay Purushothaman | a945ce7e | 2015-03-05 19:30:57 +0530 | [diff] [blame] | 7566 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
| 7567 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); |
| 7568 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); |
| 7569 | if (bestm2_frac) |
| 7570 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; |
| 7571 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7572 | |
Vijay Purushothaman | de3a0fd | 2015-03-05 19:32:06 +0530 | [diff] [blame] | 7573 | /* Program digital lock detect threshold */ |
| 7574 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); |
| 7575 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | |
| 7576 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); |
| 7577 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); |
| 7578 | if (!bestm2_frac) |
| 7579 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; |
| 7580 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); |
| 7581 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7582 | /* Loop filter */ |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7583 | if (vco == 5400000) { |
| 7584 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7585 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); |
| 7586 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7587 | tribuf_calcntr = 0x9; |
| 7588 | } else if (vco <= 6200000) { |
| 7589 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7590 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); |
| 7591 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7592 | tribuf_calcntr = 0x9; |
| 7593 | } else if (vco <= 6480000) { |
| 7594 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7595 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
| 7596 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7597 | tribuf_calcntr = 0x8; |
| 7598 | } else { |
| 7599 | /* Not supported. Apply the same limits as in the max case */ |
| 7600 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7601 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
| 7602 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7603 | tribuf_calcntr = 0; |
| 7604 | } |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7605 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
| 7606 | |
Ville Syrjälä | 968040b | 2015-03-11 22:52:08 +0200 | [diff] [blame] | 7607 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
Vijay Purushothaman | 9cbe40c | 2015-03-05 19:33:08 +0530 | [diff] [blame] | 7608 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
| 7609 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); |
| 7610 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); |
| 7611 | |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7612 | /* AFC Recal */ |
| 7613 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
| 7614 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
| 7615 | DPIO_AFC_RECAL); |
| 7616 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 7617 | mutex_unlock(&dev_priv->sb_lock); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 7618 | } |
| 7619 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7620 | /** |
| 7621 | * vlv_force_pll_on - forcibly enable just the PLL |
| 7622 | * @dev_priv: i915 private structure |
| 7623 | * @pipe: pipe PLL to enable |
| 7624 | * @dpll: PLL configuration |
| 7625 | * |
| 7626 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
| 7627 | * in cases where we need the PLL enabled even when @pipe is not going to |
| 7628 | * be enabled. |
| 7629 | */ |
| 7630 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
| 7631 | const struct dpll *dpll) |
| 7632 | { |
| 7633 | struct intel_crtc *crtc = |
| 7634 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7635 | struct intel_crtc_state pipe_config = { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7636 | .base.crtc = &crtc->base, |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7637 | .pixel_multiplier = 1, |
| 7638 | .dpll = *dpll, |
| 7639 | }; |
| 7640 | |
| 7641 | if (IS_CHERRYVIEW(dev)) { |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7642 | chv_compute_dpll(crtc, &pipe_config); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7643 | chv_prepare_pll(crtc, &pipe_config); |
| 7644 | chv_enable_pll(crtc, &pipe_config); |
| 7645 | } else { |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7646 | vlv_compute_dpll(crtc, &pipe_config); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 7647 | vlv_prepare_pll(crtc, &pipe_config); |
| 7648 | vlv_enable_pll(crtc, &pipe_config); |
| 7649 | } |
| 7650 | } |
| 7651 | |
| 7652 | /** |
| 7653 | * vlv_force_pll_off - forcibly disable just the PLL |
| 7654 | * @dev_priv: i915 private structure |
| 7655 | * @pipe: pipe PLL to disable |
| 7656 | * |
| 7657 | * Disable the PLL for @pipe. To be used in cases where we need |
| 7658 | * the PLL enabled even when @pipe is not going to be enabled. |
| 7659 | */ |
| 7660 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) |
| 7661 | { |
| 7662 | if (IS_CHERRYVIEW(dev)) |
| 7663 | chv_disable_pll(to_i915(dev), pipe); |
| 7664 | else |
| 7665 | vlv_disable_pll(to_i915(dev), pipe); |
| 7666 | } |
| 7667 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7668 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
| 7669 | struct intel_crtc_state *crtc_state, |
| 7670 | intel_clock_t *reduced_clock, |
| 7671 | int num_connectors) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7672 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7673 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7674 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7675 | u32 dpll; |
| 7676 | bool is_sdvo; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7677 | struct dpll *clock = &crtc_state->dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7678 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7679 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 7680 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7681 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
| 7682 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7683 | |
| 7684 | dpll = DPLL_VGA_MODE_DIS; |
| 7685 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7686 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7687 | dpll |= DPLLB_MODE_LVDS; |
| 7688 | else |
| 7689 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 7690 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 7691 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7692 | dpll |= (crtc_state->pixel_multiplier - 1) |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 7693 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7694 | } |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 7695 | |
| 7696 | if (is_sdvo) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 7697 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 7698 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7699 | if (crtc_state->has_dp_encoder) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 7700 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7701 | |
| 7702 | /* compute bitmask from p1 value */ |
| 7703 | if (IS_PINEVIEW(dev)) |
| 7704 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 7705 | else { |
| 7706 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 7707 | if (IS_G4X(dev) && reduced_clock) |
| 7708 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 7709 | } |
| 7710 | switch (clock->p2) { |
| 7711 | case 5: |
| 7712 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 7713 | break; |
| 7714 | case 7: |
| 7715 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 7716 | break; |
| 7717 | case 10: |
| 7718 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 7719 | break; |
| 7720 | case 14: |
| 7721 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 7722 | break; |
| 7723 | } |
| 7724 | if (INTEL_INFO(dev)->gen >= 4) |
| 7725 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 7726 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7727 | if (crtc_state->sdvo_tv_clock) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7728 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7729 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7730 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 7731 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 7732 | else |
| 7733 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 7734 | |
| 7735 | dpll |= DPLL_VCO_ENABLE; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7736 | crtc_state->dpll_hw_state.dpll = dpll; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 7737 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7738 | if (INTEL_INFO(dev)->gen >= 4) { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7739 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 7740 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7741 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7742 | } |
| 7743 | } |
| 7744 | |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 7745 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
| 7746 | struct intel_crtc_state *crtc_state, |
| 7747 | intel_clock_t *reduced_clock, |
| 7748 | int num_connectors) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7749 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 7750 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7751 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7752 | u32 dpll; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7753 | struct dpll *clock = &crtc_state->dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7754 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7755 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 7756 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7757 | dpll = DPLL_VGA_MODE_DIS; |
| 7758 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7759 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7760 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 7761 | } else { |
| 7762 | if (clock->p1 == 2) |
| 7763 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 7764 | else |
| 7765 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 7766 | if (clock->p2 == 4) |
| 7767 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 7768 | } |
| 7769 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7770 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 7771 | dpll |= DPLL_DVO_2X_MODE; |
| 7772 | |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 7773 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7774 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 7775 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 7776 | else |
| 7777 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 7778 | |
| 7779 | dpll |= DPLL_VCO_ENABLE; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7780 | crtc_state->dpll_hw_state.dpll = dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 7781 | } |
| 7782 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 7783 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7784 | { |
| 7785 | struct drm_device *dev = intel_crtc->base.dev; |
| 7786 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7787 | enum pipe pipe = intel_crtc->pipe; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7788 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 7789 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
Ville Syrjälä | 1caea6e | 2014-03-28 23:29:32 +0200 | [diff] [blame] | 7790 | uint32_t crtc_vtotal, crtc_vblank_end; |
| 7791 | int vsyncshift = 0; |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 7792 | |
| 7793 | /* We need to be careful not to changed the adjusted mode, for otherwise |
| 7794 | * the hw state checker will get angry at the mismatch. */ |
| 7795 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
| 7796 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7797 | |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 7798 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7799 | /* the chip adds 2 halflines automatically */ |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 7800 | crtc_vtotal -= 1; |
| 7801 | crtc_vblank_end -= 1; |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 7802 | |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 7803 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
Ville Syrjälä | 609aeac | 2014-03-28 23:29:30 +0200 | [diff] [blame] | 7804 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
| 7805 | else |
| 7806 | vsyncshift = adjusted_mode->crtc_hsync_start - |
| 7807 | adjusted_mode->crtc_htotal / 2; |
Ville Syrjälä | 1caea6e | 2014-03-28 23:29:32 +0200 | [diff] [blame] | 7808 | if (vsyncshift < 0) |
| 7809 | vsyncshift += adjusted_mode->crtc_htotal; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7810 | } |
| 7811 | |
| 7812 | if (INTEL_INFO(dev)->gen > 3) |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7813 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7814 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7815 | I915_WRITE(HTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7816 | (adjusted_mode->crtc_hdisplay - 1) | |
| 7817 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7818 | I915_WRITE(HBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7819 | (adjusted_mode->crtc_hblank_start - 1) | |
| 7820 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7821 | I915_WRITE(HSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7822 | (adjusted_mode->crtc_hsync_start - 1) | |
| 7823 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 7824 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7825 | I915_WRITE(VTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7826 | (adjusted_mode->crtc_vdisplay - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 7827 | ((crtc_vtotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7828 | I915_WRITE(VBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7829 | (adjusted_mode->crtc_vblank_start - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 7830 | ((crtc_vblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 7831 | I915_WRITE(VSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7832 | (adjusted_mode->crtc_vsync_start - 1) | |
| 7833 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 7834 | |
Paulo Zanoni | b5e508d | 2012-10-24 11:34:43 -0200 | [diff] [blame] | 7835 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
| 7836 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
| 7837 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
| 7838 | * bits. */ |
| 7839 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
| 7840 | (pipe == PIPE_B || pipe == PIPE_C)) |
| 7841 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
| 7842 | |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7843 | /* pipesrc controls the size that is scaled from, which should |
| 7844 | * always be the user's requested size. |
| 7845 | */ |
| 7846 | I915_WRITE(PIPESRC(pipe), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7847 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
| 7848 | (intel_crtc->config->pipe_src_h - 1)); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 7849 | } |
| 7850 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7851 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7852 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7853 | { |
| 7854 | struct drm_device *dev = crtc->base.dev; |
| 7855 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7856 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 7857 | uint32_t tmp; |
| 7858 | |
| 7859 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7860 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
| 7861 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7862 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7863 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
| 7864 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7865 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7866 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
| 7867 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7868 | |
| 7869 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7870 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
| 7871 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7872 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7873 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
| 7874 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7875 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7876 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
| 7877 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7878 | |
| 7879 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7880 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 7881 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; |
| 7882 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7883 | } |
| 7884 | |
| 7885 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 7886 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
| 7887 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
| 7888 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7889 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
| 7890 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7891 | } |
| 7892 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 7893 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 7894 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 7895 | { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7896 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
| 7897 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; |
| 7898 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; |
| 7899 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 7900 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7901 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
| 7902 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; |
| 7903 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; |
| 7904 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 7905 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7906 | mode->flags = pipe_config->base.adjusted_mode.flags; |
Maarten Lankhorst | cd13f5a | 2015-07-14 14:12:02 +0200 | [diff] [blame] | 7907 | mode->type = DRM_MODE_TYPE_DRIVER; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 7908 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 7909 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
| 7910 | mode->flags |= pipe_config->base.adjusted_mode.flags; |
Maarten Lankhorst | cd13f5a | 2015-07-14 14:12:02 +0200 | [diff] [blame] | 7911 | |
| 7912 | mode->hsync = drm_mode_hsync(mode); |
| 7913 | mode->vrefresh = drm_mode_vrefresh(mode); |
| 7914 | drm_mode_set_name(mode); |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 7915 | } |
| 7916 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7917 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
| 7918 | { |
| 7919 | struct drm_device *dev = intel_crtc->base.dev; |
| 7920 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7921 | uint32_t pipeconf; |
| 7922 | |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 7923 | pipeconf = 0; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7924 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 7925 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 7926 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 7927 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
Daniel Vetter | 67c72a1 | 2013-09-24 11:46:14 +0200 | [diff] [blame] | 7928 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7929 | if (intel_crtc->config->double_wide) |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 7930 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7931 | |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 7932 | /* only g4x and later have fancy bpc/dither controls */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 7933 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 7934 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7935 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 7936 | pipeconf |= PIPECONF_DITHER_EN | |
| 7937 | PIPECONF_DITHER_TYPE_SP; |
| 7938 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7939 | switch (intel_crtc->config->pipe_bpp) { |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 7940 | case 18: |
| 7941 | pipeconf |= PIPECONF_6BPC; |
| 7942 | break; |
| 7943 | case 24: |
| 7944 | pipeconf |= PIPECONF_8BPC; |
| 7945 | break; |
| 7946 | case 30: |
| 7947 | pipeconf |= PIPECONF_10BPC; |
| 7948 | break; |
| 7949 | default: |
| 7950 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 7951 | BUG(); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7952 | } |
| 7953 | } |
| 7954 | |
| 7955 | if (HAS_PIPE_CXSR(dev)) { |
| 7956 | if (intel_crtc->lowfreq_avail) { |
| 7957 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 7958 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 7959 | } else { |
| 7960 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7961 | } |
| 7962 | } |
| 7963 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 7964 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
Ville Syrjälä | efc2cff | 2014-03-28 23:29:31 +0200 | [diff] [blame] | 7965 | if (INTEL_INFO(dev)->gen < 4 || |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 7966 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
Ville Syrjälä | efc2cff | 2014-03-28 23:29:31 +0200 | [diff] [blame] | 7967 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 7968 | else |
| 7969 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
| 7970 | } else |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7971 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 7972 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 7973 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 7974 | intel_crtc->config->limited_color_range) |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 7975 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 9c8e09b | 2013-04-02 16:10:09 +0300 | [diff] [blame] | 7976 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 7977 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
| 7978 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
| 7979 | } |
| 7980 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 7981 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
| 7982 | struct intel_crtc_state *crtc_state) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7983 | { |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 7984 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7985 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 7986 | int refclk, num_connectors = 0; |
Daniel Vetter | c329a4e | 2015-06-18 10:30:23 +0200 | [diff] [blame] | 7987 | intel_clock_t clock; |
| 7988 | bool ok; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 7989 | const intel_limit_t *limit; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 7990 | struct drm_atomic_state *state = crtc_state->base.state; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 7991 | struct drm_connector *connector; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 7992 | struct drm_connector_state *connector_state; |
| 7993 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7994 | |
Ander Conselvan de Oliveira | dd3cd74 | 2015-05-15 13:34:29 +0300 | [diff] [blame] | 7995 | memset(&crtc_state->dpll_hw_state, 0, |
| 7996 | sizeof(crtc_state->dpll_hw_state)); |
| 7997 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 7998 | if (crtc_state->has_dsi_encoder) |
Daniel Vetter | 5b18e57 | 2014-04-24 23:55:06 +0200 | [diff] [blame] | 7999 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8000 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 8001 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 8002 | if (connector_state->crtc == &crtc->base) |
| 8003 | num_connectors++; |
| 8004 | } |
| 8005 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8006 | if (!crtc_state->clock_set) { |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 8007 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 8008 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8009 | /* |
| 8010 | * Returns a set of divisors for the desired target clock with |
| 8011 | * the given refclk, or FALSE. The returned values represent |
| 8012 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
| 8013 | * 2) / p1 / p2. |
| 8014 | */ |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 8015 | limit = intel_limit(crtc_state, refclk); |
| 8016 | ok = dev_priv->display.find_dpll(limit, crtc_state, |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8017 | crtc_state->port_clock, |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8018 | refclk, NULL, &clock); |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 8019 | if (!ok) { |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8020 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8021 | return -EINVAL; |
| 8022 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8023 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 8024 | /* Compat-code for transition, will disappear. */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8025 | crtc_state->dpll.n = clock.n; |
| 8026 | crtc_state->dpll.m1 = clock.m1; |
| 8027 | crtc_state->dpll.m2 = clock.m2; |
| 8028 | crtc_state->dpll.p1 = clock.p1; |
| 8029 | crtc_state->dpll.p2 = clock.p2; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 8030 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8031 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8032 | if (IS_GEN2(dev)) { |
Daniel Vetter | c329a4e | 2015-06-18 10:30:23 +0200 | [diff] [blame] | 8033 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 8034 | num_connectors); |
Chon Ming Lee | 9d556c9 | 2014-05-02 14:27:47 +0300 | [diff] [blame] | 8035 | } else if (IS_CHERRYVIEW(dev)) { |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 8036 | chv_compute_dpll(crtc, crtc_state); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8037 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 8038 | vlv_compute_dpll(crtc, crtc_state); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8039 | } else { |
Daniel Vetter | c329a4e | 2015-06-18 10:30:23 +0200 | [diff] [blame] | 8040 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
Daniel Vetter | 251ac86 | 2015-06-18 10:30:24 +0200 | [diff] [blame] | 8041 | num_connectors); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 8042 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8043 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 8044 | return 0; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 8045 | } |
| 8046 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8047 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8048 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8049 | { |
| 8050 | struct drm_device *dev = crtc->base.dev; |
| 8051 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8052 | uint32_t tmp; |
| 8053 | |
Ville Syrjälä | dc9e7dec | 2014-01-10 14:06:45 +0200 | [diff] [blame] | 8054 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
| 8055 | return; |
| 8056 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8057 | tmp = I915_READ(PFIT_CONTROL); |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 8058 | if (!(tmp & PFIT_ENABLE)) |
| 8059 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8060 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 8061 | /* Check whether the pfit is attached to our pipe. */ |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8062 | if (INTEL_INFO(dev)->gen < 4) { |
| 8063 | if (crtc->pipe != PIPE_B) |
| 8064 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8065 | } else { |
| 8066 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
| 8067 | return; |
| 8068 | } |
| 8069 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 8070 | pipe_config->gmch_pfit.control = tmp; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8071 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
| 8072 | if (INTEL_INFO(dev)->gen < 5) |
| 8073 | pipe_config->gmch_pfit.lvds_border_bits = |
| 8074 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
| 8075 | } |
| 8076 | |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8077 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8078 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8079 | { |
| 8080 | struct drm_device *dev = crtc->base.dev; |
| 8081 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8082 | int pipe = pipe_config->cpu_transcoder; |
| 8083 | intel_clock_t clock; |
| 8084 | u32 mdiv; |
Chris Wilson | 662c6ec | 2013-09-25 14:24:01 -0700 | [diff] [blame] | 8085 | int refclk = 100000; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8086 | |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 8087 | /* In case of MIPI DPLL will not even be used */ |
| 8088 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) |
| 8089 | return; |
| 8090 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8091 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 8092 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8093 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8094 | |
| 8095 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
| 8096 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
| 8097 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
| 8098 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
| 8099 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
| 8100 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 8101 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8102 | } |
| 8103 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 8104 | static void |
| 8105 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, |
| 8106 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8107 | { |
| 8108 | struct drm_device *dev = crtc->base.dev; |
| 8109 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8110 | u32 val, base, offset; |
| 8111 | int pipe = crtc->pipe, plane = crtc->plane; |
| 8112 | int fourcc, pixel_format; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 8113 | unsigned int aligned_height; |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8114 | struct drm_framebuffer *fb; |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 8115 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8116 | |
Damien Lespiau | 42a7b08 | 2015-02-05 19:35:13 +0000 | [diff] [blame] | 8117 | val = I915_READ(DSPCNTR(plane)); |
| 8118 | if (!(val & DISPLAY_PLANE_ENABLE)) |
| 8119 | return; |
| 8120 | |
Damien Lespiau | d9806c9 | 2015-01-21 14:07:19 +0000 | [diff] [blame] | 8121 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 8122 | if (!intel_fb) { |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8123 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 8124 | return; |
| 8125 | } |
| 8126 | |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 8127 | fb = &intel_fb->base; |
| 8128 | |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 8129 | if (INTEL_INFO(dev)->gen >= 4) { |
| 8130 | if (val & DISPPLANE_TILED) { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 8131 | plane_config->tiling = I915_TILING_X; |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 8132 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 8133 | } |
| 8134 | } |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8135 | |
| 8136 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
Damien Lespiau | b35d63f | 2015-01-20 12:51:50 +0000 | [diff] [blame] | 8137 | fourcc = i9xx_format_to_fourcc(pixel_format); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8138 | fb->pixel_format = fourcc; |
| 8139 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8140 | |
| 8141 | if (INTEL_INFO(dev)->gen >= 4) { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 8142 | if (plane_config->tiling) |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8143 | offset = I915_READ(DSPTILEOFF(plane)); |
| 8144 | else |
| 8145 | offset = I915_READ(DSPLINOFF(plane)); |
| 8146 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 8147 | } else { |
| 8148 | base = I915_READ(DSPADDR(plane)); |
| 8149 | } |
| 8150 | plane_config->base = base; |
| 8151 | |
| 8152 | val = I915_READ(PIPESRC(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8153 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 8154 | fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8155 | |
| 8156 | val = I915_READ(DSPSTRIDE(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8157 | fb->pitches[0] = val & 0xffffffc0; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8158 | |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 8159 | aligned_height = intel_fb_align_height(dev, fb->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 8160 | fb->pixel_format, |
| 8161 | fb->modifier[0]); |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8162 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 8163 | plane_config->size = fb->pitches[0] * aligned_height; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8164 | |
Damien Lespiau | 2844a92 | 2015-01-20 12:51:48 +0000 | [diff] [blame] | 8165 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 8166 | pipe_name(pipe), plane, fb->width, fb->height, |
| 8167 | fb->bits_per_pixel, base, fb->pitches[0], |
| 8168 | plane_config->size); |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8169 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 8170 | plane_config->fb = intel_fb; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 8171 | } |
| 8172 | |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8173 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8174 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8175 | { |
| 8176 | struct drm_device *dev = crtc->base.dev; |
| 8177 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8178 | int pipe = pipe_config->cpu_transcoder; |
| 8179 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 8180 | intel_clock_t clock; |
Imre Deak | 0d7b6b1 | 2015-07-02 14:29:58 +0300 | [diff] [blame] | 8181 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8182 | int refclk = 100000; |
| 8183 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8184 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8185 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
| 8186 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
| 8187 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
| 8188 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
Imre Deak | 0d7b6b1 | 2015-07-02 14:29:58 +0300 | [diff] [blame] | 8189 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8190 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8191 | |
| 8192 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
Imre Deak | 0d7b6b1 | 2015-07-02 14:29:58 +0300 | [diff] [blame] | 8193 | clock.m2 = (pll_dw0 & 0xff) << 22; |
| 8194 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) |
| 8195 | clock.m2 |= pll_dw2 & 0x3fffff; |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8196 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
| 8197 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
| 8198 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
| 8199 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 8200 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8201 | } |
| 8202 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8203 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 8204 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8205 | { |
| 8206 | struct drm_device *dev = crtc->base.dev; |
| 8207 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8208 | uint32_t tmp; |
| 8209 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 8210 | if (!intel_display_power_is_enabled(dev_priv, |
| 8211 | POWER_DOMAIN_PIPE(crtc->pipe))) |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 8212 | return false; |
| 8213 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 8214 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 8215 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 8216 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8217 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 8218 | if (!(tmp & PIPECONF_ENABLE)) |
| 8219 | return false; |
| 8220 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8221 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 8222 | switch (tmp & PIPECONF_BPC_MASK) { |
| 8223 | case PIPECONF_6BPC: |
| 8224 | pipe_config->pipe_bpp = 18; |
| 8225 | break; |
| 8226 | case PIPECONF_8BPC: |
| 8227 | pipe_config->pipe_bpp = 24; |
| 8228 | break; |
| 8229 | case PIPECONF_10BPC: |
| 8230 | pipe_config->pipe_bpp = 30; |
| 8231 | break; |
| 8232 | default: |
| 8233 | break; |
| 8234 | } |
| 8235 | } |
| 8236 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8237 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 8238 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 8239 | pipe_config->limited_color_range = true; |
| 8240 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 8241 | if (INTEL_INFO(dev)->gen < 4) |
| 8242 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
| 8243 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 8244 | intel_get_pipe_timings(crtc, pipe_config); |
| 8245 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 8246 | i9xx_get_pfit_config(crtc, pipe_config); |
| 8247 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8248 | if (INTEL_INFO(dev)->gen >= 4) { |
| 8249 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
| 8250 | pipe_config->pixel_multiplier = |
| 8251 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
| 8252 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8253 | pipe_config->dpll_hw_state.dpll_md = tmp; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8254 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 8255 | tmp = I915_READ(DPLL(crtc->pipe)); |
| 8256 | pipe_config->pixel_multiplier = |
| 8257 | ((tmp & SDVO_MULTIPLIER_MASK) |
| 8258 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
| 8259 | } else { |
| 8260 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
| 8261 | * port and will be fixed up in the encoder->get_config |
| 8262 | * function. */ |
| 8263 | pipe_config->pixel_multiplier = 1; |
| 8264 | } |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8265 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 8266 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 1c4e027 | 2014-09-05 21:52:42 +0300 | [diff] [blame] | 8267 | /* |
| 8268 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs |
| 8269 | * on 830. Filter it out here so that we don't |
| 8270 | * report errors due to that. |
| 8271 | */ |
| 8272 | if (IS_I830(dev)) |
| 8273 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
| 8274 | |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8275 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
| 8276 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
Ville Syrjälä | 165e901 | 2013-06-26 17:44:15 +0300 | [diff] [blame] | 8277 | } else { |
| 8278 | /* Mask out read-only status bits. */ |
| 8279 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
| 8280 | DPLL_PORTC_READY_MASK | |
| 8281 | DPLL_PORTB_READY_MASK); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 8282 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 8283 | |
Ville Syrjälä | 70b23a9 | 2014-04-09 13:28:22 +0300 | [diff] [blame] | 8284 | if (IS_CHERRYVIEW(dev)) |
| 8285 | chv_crtc_clock_get(crtc, pipe_config); |
| 8286 | else if (IS_VALLEYVIEW(dev)) |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 8287 | vlv_crtc_clock_get(crtc, pipe_config); |
| 8288 | else |
| 8289 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8290 | |
Ville Syrjälä | 0f64614 | 2015-08-26 19:39:18 +0300 | [diff] [blame] | 8291 | /* |
| 8292 | * Normally the dotclock is filled in by the encoder .get_config() |
| 8293 | * but in case the pipe is enabled w/o any ports we need a sane |
| 8294 | * default. |
| 8295 | */ |
| 8296 | pipe_config->base.adjusted_mode.crtc_clock = |
| 8297 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
| 8298 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 8299 | return true; |
| 8300 | } |
| 8301 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8302 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8303 | { |
| 8304 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8305 | struct intel_encoder *encoder; |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8306 | u32 val, final; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8307 | bool has_lvds = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8308 | bool has_cpu_edp = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8309 | bool has_panel = false; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8310 | bool has_ck505 = false; |
| 8311 | bool can_ssc = false; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8312 | |
| 8313 | /* We need to take the global config into account */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 8314 | for_each_intel_encoder(dev, encoder) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8315 | switch (encoder->type) { |
| 8316 | case INTEL_OUTPUT_LVDS: |
| 8317 | has_panel = true; |
| 8318 | has_lvds = true; |
| 8319 | break; |
| 8320 | case INTEL_OUTPUT_EDP: |
| 8321 | has_panel = true; |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 8322 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8323 | has_cpu_edp = true; |
| 8324 | break; |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 8325 | default: |
| 8326 | break; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8327 | } |
| 8328 | } |
| 8329 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8330 | if (HAS_PCH_IBX(dev)) { |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 8331 | has_ck505 = dev_priv->vbt.display_clock_mode; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8332 | can_ssc = has_ck505; |
| 8333 | } else { |
| 8334 | has_ck505 = false; |
| 8335 | can_ssc = true; |
| 8336 | } |
| 8337 | |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 8338 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
| 8339 | has_panel, has_lvds, has_ck505); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8340 | |
| 8341 | /* Ironlake: try to setup display ref clock before DPLL |
| 8342 | * enabling. This is only under driver's control after |
| 8343 | * PCH B stepping, previous chipset stepping should be |
| 8344 | * ignoring this setting. |
| 8345 | */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8346 | val = I915_READ(PCH_DREF_CONTROL); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8347 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8348 | /* As we must carefully and slowly disable/enable each source in turn, |
| 8349 | * compute the final state we want first and check if we need to |
| 8350 | * make any changes at all. |
| 8351 | */ |
| 8352 | final = val; |
| 8353 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8354 | if (has_ck505) |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8355 | final |= DREF_NONSPREAD_CK505_ENABLE; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8356 | else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8357 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 8358 | |
| 8359 | final &= ~DREF_SSC_SOURCE_MASK; |
| 8360 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 8361 | final &= ~DREF_SSC1_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8362 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8363 | if (has_panel) { |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8364 | final |= DREF_SSC_SOURCE_ENABLE; |
| 8365 | |
| 8366 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 8367 | final |= DREF_SSC1_ENABLE; |
| 8368 | |
| 8369 | if (has_cpu_edp) { |
| 8370 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 8371 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 8372 | else |
| 8373 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 8374 | } else |
| 8375 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 8376 | } else { |
| 8377 | final |= DREF_SSC_SOURCE_DISABLE; |
| 8378 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 8379 | } |
| 8380 | |
| 8381 | if (final == val) |
| 8382 | return; |
| 8383 | |
| 8384 | /* Always enable nonspread source */ |
| 8385 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 8386 | |
| 8387 | if (has_ck505) |
| 8388 | val |= DREF_NONSPREAD_CK505_ENABLE; |
| 8389 | else |
| 8390 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 8391 | |
| 8392 | if (has_panel) { |
| 8393 | val &= ~DREF_SSC_SOURCE_MASK; |
| 8394 | val |= DREF_SSC_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8395 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8396 | /* SSC must be turned on before enabling the CPU output */ |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8397 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8398 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8399 | val |= DREF_SSC1_ENABLE; |
Daniel Vetter | e77166b | 2012-03-30 22:14:05 +0200 | [diff] [blame] | 8400 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8401 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8402 | |
| 8403 | /* Get SSC going before enabling the outputs */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8404 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8405 | POSTING_READ(PCH_DREF_CONTROL); |
| 8406 | udelay(200); |
| 8407 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8408 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8409 | |
| 8410 | /* Enable CPU source on CPU attached eDP */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8411 | if (has_cpu_edp) { |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 8412 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8413 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8414 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 8415 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8416 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8417 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8418 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8419 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8420 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8421 | POSTING_READ(PCH_DREF_CONTROL); |
| 8422 | udelay(200); |
| 8423 | } else { |
| 8424 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
| 8425 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8426 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8427 | |
| 8428 | /* Turn off CPU output */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8429 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8430 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8431 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8432 | POSTING_READ(PCH_DREF_CONTROL); |
| 8433 | udelay(200); |
| 8434 | |
| 8435 | /* Turn off the SSC source */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8436 | val &= ~DREF_SSC_SOURCE_MASK; |
| 8437 | val |= DREF_SSC_SOURCE_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8438 | |
| 8439 | /* Turn off SSC1 */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8440 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 8441 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8442 | I915_WRITE(PCH_DREF_CONTROL, val); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8443 | POSTING_READ(PCH_DREF_CONTROL); |
| 8444 | udelay(200); |
| 8445 | } |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 8446 | |
| 8447 | BUG_ON(val != final); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 8448 | } |
| 8449 | |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8450 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8451 | { |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8452 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8453 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8454 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 8455 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
| 8456 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8457 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8458 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
| 8459 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
| 8460 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8461 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8462 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 8463 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
| 8464 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8465 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8466 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
| 8467 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
| 8468 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8469 | } |
| 8470 | |
| 8471 | /* WaMPhyProgramming:hsw */ |
| 8472 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
| 8473 | { |
| 8474 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8475 | |
| 8476 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
| 8477 | tmp &= ~(0xFF << 24); |
| 8478 | tmp |= (0x12 << 24); |
| 8479 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
| 8480 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8481 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
| 8482 | tmp |= (1 << 11); |
| 8483 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
| 8484 | |
| 8485 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
| 8486 | tmp |= (1 << 11); |
| 8487 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
| 8488 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8489 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
| 8490 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 8491 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
| 8492 | |
| 8493 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
| 8494 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 8495 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
| 8496 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8497 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
| 8498 | tmp &= ~(7 << 13); |
| 8499 | tmp |= (5 << 13); |
| 8500 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8501 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8502 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
| 8503 | tmp &= ~(7 << 13); |
| 8504 | tmp |= (5 << 13); |
| 8505 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8506 | |
| 8507 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
| 8508 | tmp &= ~0xFF; |
| 8509 | tmp |= 0x1C; |
| 8510 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
| 8511 | |
| 8512 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
| 8513 | tmp &= ~0xFF; |
| 8514 | tmp |= 0x1C; |
| 8515 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
| 8516 | |
| 8517 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
| 8518 | tmp &= ~(0xFF << 16); |
| 8519 | tmp |= (0x1C << 16); |
| 8520 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
| 8521 | |
| 8522 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
| 8523 | tmp &= ~(0xFF << 16); |
| 8524 | tmp |= (0x1C << 16); |
| 8525 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
| 8526 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8527 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
| 8528 | tmp |= (1 << 27); |
| 8529 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8530 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8531 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
| 8532 | tmp |= (1 << 27); |
| 8533 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8534 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8535 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
| 8536 | tmp &= ~(0xF << 28); |
| 8537 | tmp |= (4 << 28); |
| 8538 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8539 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 8540 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
| 8541 | tmp &= ~(0xF << 28); |
| 8542 | tmp |= (4 << 28); |
| 8543 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8544 | } |
| 8545 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 8546 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
| 8547 | * Programming" based on the parameters passed: |
| 8548 | * - Sequence to enable CLKOUT_DP |
| 8549 | * - Sequence to enable CLKOUT_DP without spread |
| 8550 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
| 8551 | */ |
| 8552 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
| 8553 | bool with_fdi) |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8554 | { |
| 8555 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 8556 | uint32_t reg, tmp; |
| 8557 | |
| 8558 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
| 8559 | with_spread = true; |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 8560 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 8561 | with_fdi = false; |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8562 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8563 | mutex_lock(&dev_priv->sb_lock); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8564 | |
| 8565 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 8566 | tmp &= ~SBI_SSCCTL_DISABLE; |
| 8567 | tmp |= SBI_SSCCTL_PATHALT; |
| 8568 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8569 | |
| 8570 | udelay(24); |
| 8571 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 8572 | if (with_spread) { |
| 8573 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 8574 | tmp &= ~SBI_SSCCTL_PATHALT; |
| 8575 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 8576 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 8577 | if (with_fdi) { |
| 8578 | lpt_reset_fdi_mphy(dev_priv); |
| 8579 | lpt_program_fdi_mphy(dev_priv); |
| 8580 | } |
| 8581 | } |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8582 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 8583 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 8584 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 8585 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 8586 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
Daniel Vetter | c00db24 | 2013-01-22 15:33:27 +0100 | [diff] [blame] | 8587 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8588 | mutex_unlock(&dev_priv->sb_lock); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8589 | } |
| 8590 | |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 8591 | /* Sequence to disable CLKOUT_DP */ |
| 8592 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
| 8593 | { |
| 8594 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8595 | uint32_t reg, tmp; |
| 8596 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8597 | mutex_lock(&dev_priv->sb_lock); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 8598 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 8599 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 8600 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 8601 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 8602 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 8603 | |
| 8604 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 8605 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
| 8606 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
| 8607 | tmp |= SBI_SSCCTL_PATHALT; |
| 8608 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8609 | udelay(32); |
| 8610 | } |
| 8611 | tmp |= SBI_SSCCTL_DISABLE; |
| 8612 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8613 | } |
| 8614 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 8615 | mutex_unlock(&dev_priv->sb_lock); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 8616 | } |
| 8617 | |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 8618 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
| 8619 | |
| 8620 | static const uint16_t sscdivintphase[] = { |
| 8621 | [BEND_IDX( 50)] = 0x3B23, |
| 8622 | [BEND_IDX( 45)] = 0x3B23, |
| 8623 | [BEND_IDX( 40)] = 0x3C23, |
| 8624 | [BEND_IDX( 35)] = 0x3C23, |
| 8625 | [BEND_IDX( 30)] = 0x3D23, |
| 8626 | [BEND_IDX( 25)] = 0x3D23, |
| 8627 | [BEND_IDX( 20)] = 0x3E23, |
| 8628 | [BEND_IDX( 15)] = 0x3E23, |
| 8629 | [BEND_IDX( 10)] = 0x3F23, |
| 8630 | [BEND_IDX( 5)] = 0x3F23, |
| 8631 | [BEND_IDX( 0)] = 0x0025, |
| 8632 | [BEND_IDX( -5)] = 0x0025, |
| 8633 | [BEND_IDX(-10)] = 0x0125, |
| 8634 | [BEND_IDX(-15)] = 0x0125, |
| 8635 | [BEND_IDX(-20)] = 0x0225, |
| 8636 | [BEND_IDX(-25)] = 0x0225, |
| 8637 | [BEND_IDX(-30)] = 0x0325, |
| 8638 | [BEND_IDX(-35)] = 0x0325, |
| 8639 | [BEND_IDX(-40)] = 0x0425, |
| 8640 | [BEND_IDX(-45)] = 0x0425, |
| 8641 | [BEND_IDX(-50)] = 0x0525, |
| 8642 | }; |
| 8643 | |
| 8644 | /* |
| 8645 | * Bend CLKOUT_DP |
| 8646 | * steps -50 to 50 inclusive, in steps of 5 |
| 8647 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) |
| 8648 | * change in clock period = -(steps / 10) * 5.787 ps |
| 8649 | */ |
| 8650 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) |
| 8651 | { |
| 8652 | uint32_t tmp; |
| 8653 | int idx = BEND_IDX(steps); |
| 8654 | |
| 8655 | if (WARN_ON(steps % 5 != 0)) |
| 8656 | return; |
| 8657 | |
| 8658 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) |
| 8659 | return; |
| 8660 | |
| 8661 | mutex_lock(&dev_priv->sb_lock); |
| 8662 | |
| 8663 | if (steps % 10 != 0) |
| 8664 | tmp = 0xAAAAAAAB; |
| 8665 | else |
| 8666 | tmp = 0x00000000; |
| 8667 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); |
| 8668 | |
| 8669 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); |
| 8670 | tmp &= 0xffff0000; |
| 8671 | tmp |= sscdivintphase[idx]; |
| 8672 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); |
| 8673 | |
| 8674 | mutex_unlock(&dev_priv->sb_lock); |
| 8675 | } |
| 8676 | |
| 8677 | #undef BEND_IDX |
| 8678 | |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 8679 | static void lpt_init_pch_refclk(struct drm_device *dev) |
| 8680 | { |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 8681 | struct intel_encoder *encoder; |
| 8682 | bool has_vga = false; |
| 8683 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 8684 | for_each_intel_encoder(dev, encoder) { |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 8685 | switch (encoder->type) { |
| 8686 | case INTEL_OUTPUT_ANALOG: |
| 8687 | has_vga = true; |
| 8688 | break; |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 8689 | default: |
| 8690 | break; |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 8691 | } |
| 8692 | } |
| 8693 | |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 8694 | if (has_vga) { |
| 8695 | lpt_bend_clkout_dp(to_i915(dev), 0); |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 8696 | lpt_enable_clkout_dp(dev, true, true); |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 8697 | } else { |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 8698 | lpt_disable_clkout_dp(dev); |
Ville Syrjälä | f7be2c2 | 2015-12-04 22:19:39 +0200 | [diff] [blame] | 8699 | } |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 8700 | } |
| 8701 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 8702 | /* |
| 8703 | * Initialize reference clocks when the driver loads |
| 8704 | */ |
| 8705 | void intel_init_pch_refclk(struct drm_device *dev) |
| 8706 | { |
| 8707 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 8708 | ironlake_init_pch_refclk(dev); |
| 8709 | else if (HAS_PCH_LPT(dev)) |
| 8710 | lpt_init_pch_refclk(dev); |
| 8711 | } |
| 8712 | |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8713 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8714 | { |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8715 | struct drm_device *dev = crtc_state->base.crtc->dev; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8716 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8717 | struct drm_atomic_state *state = crtc_state->base.state; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 8718 | struct drm_connector *connector; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8719 | struct drm_connector_state *connector_state; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8720 | struct intel_encoder *encoder; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8721 | int num_connectors = 0, i; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8722 | bool is_lvds = false; |
| 8723 | |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 8724 | for_each_connector_in_state(state, connector, connector_state, i) { |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8725 | if (connector_state->crtc != crtc_state->base.crtc) |
| 8726 | continue; |
| 8727 | |
| 8728 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 8729 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8730 | switch (encoder->type) { |
| 8731 | case INTEL_OUTPUT_LVDS: |
| 8732 | is_lvds = true; |
| 8733 | break; |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 8734 | default: |
| 8735 | break; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8736 | } |
| 8737 | num_connectors++; |
| 8738 | } |
| 8739 | |
| 8740 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 8741 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 8742 | dev_priv->vbt.lvds_ssc_freq); |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 8743 | return dev_priv->vbt.lvds_ssc_freq; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 8744 | } |
| 8745 | |
| 8746 | return 120000; |
| 8747 | } |
| 8748 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 8749 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8750 | { |
| 8751 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 8752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8753 | int pipe = intel_crtc->pipe; |
| 8754 | uint32_t val; |
| 8755 | |
Daniel Vetter | 7811407 | 2013-06-13 00:54:57 +0200 | [diff] [blame] | 8756 | val = 0; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8757 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8758 | switch (intel_crtc->config->pipe_bpp) { |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8759 | case 18: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 8760 | val |= PIPECONF_6BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8761 | break; |
| 8762 | case 24: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 8763 | val |= PIPECONF_8BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8764 | break; |
| 8765 | case 30: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 8766 | val |= PIPECONF_10BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8767 | break; |
| 8768 | case 36: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 8769 | val |= PIPECONF_12BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8770 | break; |
| 8771 | default: |
Paulo Zanoni | cc769b6 | 2012-09-20 18:36:03 -0300 | [diff] [blame] | 8772 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 8773 | BUG(); |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8774 | } |
| 8775 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8776 | if (intel_crtc->config->dither) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8777 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 8778 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8779 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8780 | val |= PIPECONF_INTERLACED_ILK; |
| 8781 | else |
| 8782 | val |= PIPECONF_PROGRESSIVE; |
| 8783 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8784 | if (intel_crtc->config->limited_color_range) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 8785 | val |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 8786 | |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 8787 | I915_WRITE(PIPECONF(pipe), val); |
| 8788 | POSTING_READ(PIPECONF(pipe)); |
| 8789 | } |
| 8790 | |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 8791 | /* |
| 8792 | * Set up the pipe CSC unit. |
| 8793 | * |
| 8794 | * Currently only full range RGB to limited range RGB conversion |
| 8795 | * is supported, but eventually this should handle various |
| 8796 | * RGB<->YCbCr scenarios as well. |
| 8797 | */ |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 8798 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 8799 | { |
| 8800 | struct drm_device *dev = crtc->dev; |
| 8801 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8803 | int pipe = intel_crtc->pipe; |
| 8804 | uint16_t coeff = 0x7800; /* 1.0 */ |
| 8805 | |
| 8806 | /* |
| 8807 | * TODO: Check what kind of values actually come out of the pipe |
| 8808 | * with these coeff/postoff values and adjust to get the best |
| 8809 | * accuracy. Perhaps we even need to take the bpc value into |
| 8810 | * consideration. |
| 8811 | */ |
| 8812 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8813 | if (intel_crtc->config->limited_color_range) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 8814 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
| 8815 | |
| 8816 | /* |
| 8817 | * GY/GU and RY/RU should be the other way around according |
| 8818 | * to BSpec, but reality doesn't agree. Just set them up in |
| 8819 | * a way that results in the correct picture. |
| 8820 | */ |
| 8821 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
| 8822 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
| 8823 | |
| 8824 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
| 8825 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
| 8826 | |
| 8827 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
| 8828 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
| 8829 | |
| 8830 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
| 8831 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
| 8832 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
| 8833 | |
| 8834 | if (INTEL_INFO(dev)->gen > 6) { |
| 8835 | uint16_t postoff = 0; |
| 8836 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8837 | if (intel_crtc->config->limited_color_range) |
Ville Syrjälä | 32cf0cb | 2013-11-28 22:10:38 +0200 | [diff] [blame] | 8838 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 8839 | |
| 8840 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
| 8841 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
| 8842 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
| 8843 | |
| 8844 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
| 8845 | } else { |
| 8846 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
| 8847 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8848 | if (intel_crtc->config->limited_color_range) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 8849 | mode |= CSC_BLACK_SCREEN_OFFSET; |
| 8850 | |
| 8851 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
| 8852 | } |
| 8853 | } |
| 8854 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 8855 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8856 | { |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 8857 | struct drm_device *dev = crtc->dev; |
| 8858 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 8860 | enum pipe pipe = intel_crtc->pipe; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8861 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8862 | uint32_t val; |
| 8863 | |
Daniel Vetter | 3eff4fa | 2013-06-13 00:54:59 +0200 | [diff] [blame] | 8864 | val = 0; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8865 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8866 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8867 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 8868 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8869 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8870 | val |= PIPECONF_INTERLACED_ILK; |
| 8871 | else |
| 8872 | val |= PIPECONF_PROGRESSIVE; |
| 8873 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 8874 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
| 8875 | POSTING_READ(PIPECONF(cpu_transcoder)); |
Daniel Vetter | 3eff4fa | 2013-06-13 00:54:59 +0200 | [diff] [blame] | 8876 | |
| 8877 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
| 8878 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 8879 | |
Satheeshakrishna M | 3cdf122c | 2014-04-08 15:46:53 +0530 | [diff] [blame] | 8880 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 8881 | val = 0; |
| 8882 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8883 | switch (intel_crtc->config->pipe_bpp) { |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 8884 | case 18: |
| 8885 | val |= PIPEMISC_DITHER_6_BPC; |
| 8886 | break; |
| 8887 | case 24: |
| 8888 | val |= PIPEMISC_DITHER_8_BPC; |
| 8889 | break; |
| 8890 | case 30: |
| 8891 | val |= PIPEMISC_DITHER_10_BPC; |
| 8892 | break; |
| 8893 | case 36: |
| 8894 | val |= PIPEMISC_DITHER_12_BPC; |
| 8895 | break; |
| 8896 | default: |
| 8897 | /* Case prevented by pipe_config_set_bpp. */ |
| 8898 | BUG(); |
| 8899 | } |
| 8900 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 8901 | if (intel_crtc->config->dither) |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 8902 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
| 8903 | |
| 8904 | I915_WRITE(PIPEMISC(pipe), val); |
| 8905 | } |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 8906 | } |
| 8907 | |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8908 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8909 | struct intel_crtc_state *crtc_state, |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8910 | intel_clock_t *clock, |
| 8911 | bool *has_reduced_clock, |
| 8912 | intel_clock_t *reduced_clock) |
| 8913 | { |
| 8914 | struct drm_device *dev = crtc->dev; |
| 8915 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8916 | int refclk; |
| 8917 | const intel_limit_t *limit; |
Daniel Vetter | c329a4e | 2015-06-18 10:30:23 +0200 | [diff] [blame] | 8918 | bool ret; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8919 | |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8920 | refclk = ironlake_get_refclk(crtc_state); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8921 | |
| 8922 | /* |
| 8923 | * Returns a set of divisors for the desired target clock with the given |
| 8924 | * refclk, or FALSE. The returned values represent the clock equation: |
| 8925 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 8926 | */ |
Ander Conselvan de Oliveira | a93e255 | 2015-03-20 16:18:17 +0200 | [diff] [blame] | 8927 | limit = intel_limit(crtc_state, refclk); |
| 8928 | ret = dev_priv->display.find_dpll(limit, crtc_state, |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8929 | crtc_state->port_clock, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 8930 | refclk, NULL, clock); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8931 | if (!ret) |
| 8932 | return false; |
| 8933 | |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 8934 | return true; |
| 8935 | } |
| 8936 | |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 8937 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
| 8938 | { |
| 8939 | /* |
| 8940 | * Account for spread spectrum to avoid |
| 8941 | * oversubscribing the link. Max center spread |
| 8942 | * is 2.5%; use 5% for safety's sake. |
| 8943 | */ |
| 8944 | u32 bps = target_clock * bpp * 21 / 20; |
Ville Syrjälä | 619d4d0 | 2014-02-27 14:23:14 +0200 | [diff] [blame] | 8945 | return DIV_ROUND_UP(bps, link_bw * 8); |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 8946 | } |
| 8947 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 8948 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 8949 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 8950 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
Paulo Zanoni | f48d8f2 | 2012-09-20 18:36:04 -0300 | [diff] [blame] | 8951 | } |
| 8952 | |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8953 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8954 | struct intel_crtc_state *crtc_state, |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 8955 | u32 *fp, |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 8956 | intel_clock_t *reduced_clock, u32 *fp2) |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8957 | { |
| 8958 | struct drm_crtc *crtc = &intel_crtc->base; |
| 8959 | struct drm_device *dev = crtc->dev; |
| 8960 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8961 | struct drm_atomic_state *state = crtc_state->base.state; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 8962 | struct drm_connector *connector; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8963 | struct drm_connector_state *connector_state; |
| 8964 | struct intel_encoder *encoder; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8965 | uint32_t dpll; |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8966 | int factor, num_connectors = 0, i; |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 8967 | bool is_lvds = false, is_sdvo = false; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8968 | |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 8969 | for_each_connector_in_state(state, connector, connector_state, i) { |
Ander Conselvan de Oliveira | 55bb999 | 2015-03-20 16:18:19 +0200 | [diff] [blame] | 8970 | if (connector_state->crtc != crtc_state->base.crtc) |
| 8971 | continue; |
| 8972 | |
| 8973 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 8974 | |
| 8975 | switch (encoder->type) { |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8976 | case INTEL_OUTPUT_LVDS: |
| 8977 | is_lvds = true; |
| 8978 | break; |
| 8979 | case INTEL_OUTPUT_SDVO: |
| 8980 | case INTEL_OUTPUT_HDMI: |
| 8981 | is_sdvo = true; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8982 | break; |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 8983 | default: |
| 8984 | break; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 8985 | } |
| 8986 | |
| 8987 | num_connectors++; |
| 8988 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8989 | |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 8990 | /* Enable autotuning of the PLL clock (if permissible) */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 8991 | factor = 21; |
| 8992 | if (is_lvds) { |
| 8993 | if ((intel_panel_use_ssc(dev_priv) && |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 8994 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
Daniel Vetter | f0b4405 | 2013-04-04 22:20:33 +0200 | [diff] [blame] | 8995 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 8996 | factor = 25; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 8997 | } else if (crtc_state->sdvo_tv_clock) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 8998 | factor = 20; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 8999 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9000 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
Daniel Vetter | 7d0ac5b | 2013-04-04 22:20:32 +0200 | [diff] [blame] | 9001 | *fp |= FP_CB_TUNE; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 9002 | |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 9003 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
| 9004 | *fp2 |= FP_CB_TUNE; |
| 9005 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 9006 | dpll = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 9007 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9008 | if (is_lvds) |
| 9009 | dpll |= DPLLB_MODE_LVDS; |
| 9010 | else |
| 9011 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 9012 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9013 | dpll |= (crtc_state->pixel_multiplier - 1) |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 9014 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 9015 | |
| 9016 | if (is_sdvo) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 9017 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9018 | if (crtc_state->has_dp_encoder) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 9019 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9020 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9021 | /* compute bitmask from p1 value */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9022 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9023 | /* also FPA1 */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9024 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9025 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9026 | switch (crtc_state->dpll.p2) { |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 9027 | case 5: |
| 9028 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 9029 | break; |
| 9030 | case 7: |
| 9031 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 9032 | break; |
| 9033 | case 10: |
| 9034 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 9035 | break; |
| 9036 | case 14: |
| 9037 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 9038 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9039 | } |
| 9040 | |
Daniel Vetter | b4c09f3 | 2013-04-30 14:01:42 +0200 | [diff] [blame] | 9041 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 9042 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9043 | else |
| 9044 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 9045 | |
Daniel Vetter | 959e16d | 2013-06-05 13:34:21 +0200 | [diff] [blame] | 9046 | return dpll | DPLL_VCO_ENABLE; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 9047 | } |
| 9048 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9049 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
| 9050 | struct intel_crtc_state *crtc_state) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9051 | { |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 9052 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9053 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 9054 | u32 dpll = 0, fp = 0, fp2 = 0; |
Paulo Zanoni | e2f12b0 | 2012-09-20 18:36:06 -0300 | [diff] [blame] | 9055 | bool ok, has_reduced_clock = false; |
Daniel Vetter | 8b47047 | 2013-03-28 10:41:59 +0100 | [diff] [blame] | 9056 | bool is_lvds = false; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 9057 | struct intel_shared_dpll *pll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9058 | |
Ander Conselvan de Oliveira | dd3cd74 | 2015-05-15 13:34:29 +0300 | [diff] [blame] | 9059 | memset(&crtc_state->dpll_hw_state, 0, |
| 9060 | sizeof(crtc_state->dpll_hw_state)); |
| 9061 | |
Ville Syrjälä | 7905df2 | 2015-11-25 16:35:30 +0200 | [diff] [blame] | 9062 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9063 | |
Paulo Zanoni | 5dc5298 | 2012-10-05 12:05:56 -0300 | [diff] [blame] | 9064 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
| 9065 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
| 9066 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9067 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 9068 | &has_reduced_clock, &reduced_clock); |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9069 | if (!ok && !crtc_state->clock_set) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9070 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 9071 | return -EINVAL; |
| 9072 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 9073 | /* Compat-code for transition, will disappear. */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9074 | if (!crtc_state->clock_set) { |
| 9075 | crtc_state->dpll.n = clock.n; |
| 9076 | crtc_state->dpll.m1 = clock.m1; |
| 9077 | crtc_state->dpll.m2 = clock.m2; |
| 9078 | crtc_state->dpll.p1 = clock.p1; |
| 9079 | crtc_state->dpll.p2 = clock.p2; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 9080 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9081 | |
Paulo Zanoni | 5dc5298 | 2012-10-05 12:05:56 -0300 | [diff] [blame] | 9082 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9083 | if (crtc_state->has_pch_encoder) { |
| 9084 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 9085 | if (has_reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 9086 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 9087 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9088 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 9089 | &fp, &reduced_clock, |
| 9090 | has_reduced_clock ? &fp2 : NULL); |
| 9091 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9092 | crtc_state->dpll_hw_state.dpll = dpll; |
| 9093 | crtc_state->dpll_hw_state.fp0 = fp; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9094 | if (has_reduced_clock) |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9095 | crtc_state->dpll_hw_state.fp1 = fp2; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9096 | else |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9097 | crtc_state->dpll_hw_state.fp1 = fp; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9098 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9099 | pll = intel_get_shared_dpll(crtc, crtc_state); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 9100 | if (pll == NULL) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 9101 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 9102 | pipe_name(crtc->pipe)); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 9103 | return -EINVAL; |
| 9104 | } |
Ander Conselvan de Oliveira | 3fb3770 | 2014-10-29 11:32:35 +0200 | [diff] [blame] | 9105 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9106 | |
Rodrigo Vivi | ab585de | 2015-03-24 12:40:09 -0700 | [diff] [blame] | 9107 | if (is_lvds && has_reduced_clock) |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 9108 | crtc->lowfreq_avail = true; |
Daniel Vetter | bcd644e | 2013-06-05 13:34:22 +0200 | [diff] [blame] | 9109 | else |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 9110 | crtc->lowfreq_avail = false; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 9111 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 9112 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9113 | } |
| 9114 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9115 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
| 9116 | struct intel_link_m_n *m_n) |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9117 | { |
| 9118 | struct drm_device *dev = crtc->base.dev; |
| 9119 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9120 | enum pipe pipe = crtc->pipe; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9121 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9122 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
| 9123 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
| 9124 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 9125 | & ~TU_SIZE_MASK; |
| 9126 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
| 9127 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 9128 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9129 | } |
| 9130 | |
| 9131 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
| 9132 | enum transcoder transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9133 | struct intel_link_m_n *m_n, |
| 9134 | struct intel_link_m_n *m2_n2) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9135 | { |
| 9136 | struct drm_device *dev = crtc->base.dev; |
| 9137 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9138 | enum pipe pipe = crtc->pipe; |
| 9139 | |
| 9140 | if (INTEL_INFO(dev)->gen >= 5) { |
| 9141 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
| 9142 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
| 9143 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
| 9144 | & ~TU_SIZE_MASK; |
| 9145 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
| 9146 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
| 9147 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9148 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
| 9149 | * gen < 8) and if DRRS is supported (to make sure the |
| 9150 | * registers are not unnecessarily read). |
| 9151 | */ |
| 9152 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 9153 | crtc->config->has_drrs) { |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9154 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
| 9155 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); |
| 9156 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) |
| 9157 | & ~TU_SIZE_MASK; |
| 9158 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); |
| 9159 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) |
| 9160 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9161 | } |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9162 | } else { |
| 9163 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
| 9164 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
| 9165 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 9166 | & ~TU_SIZE_MASK; |
| 9167 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
| 9168 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 9169 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9170 | } |
| 9171 | } |
| 9172 | |
| 9173 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9174 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9175 | { |
Ander Conselvan de Oliveira | 681a850 | 2015-01-15 14:55:24 +0200 | [diff] [blame] | 9176 | if (pipe_config->has_pch_encoder) |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9177 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
| 9178 | else |
| 9179 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9180 | &pipe_config->dp_m_n, |
| 9181 | &pipe_config->dp_m2_n2); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9182 | } |
| 9183 | |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9184 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9185 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9186 | { |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9187 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 9188 | &pipe_config->fdi_m_n, NULL); |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9189 | } |
| 9190 | |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9191 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9192 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9193 | { |
| 9194 | struct drm_device *dev = crtc->base.dev; |
| 9195 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 9196 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
| 9197 | uint32_t ps_ctrl = 0; |
| 9198 | int id = -1; |
| 9199 | int i; |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9200 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 9201 | /* find scaler attached to this pipe */ |
| 9202 | for (i = 0; i < crtc->num_scalers; i++) { |
| 9203 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); |
| 9204 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { |
| 9205 | id = i; |
| 9206 | pipe_config->pch_pfit.enabled = true; |
| 9207 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); |
| 9208 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); |
| 9209 | break; |
| 9210 | } |
| 9211 | } |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9212 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 9213 | scaler_state->scaler_id = id; |
| 9214 | if (id >= 0) { |
| 9215 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); |
| 9216 | } else { |
| 9217 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 9218 | } |
| 9219 | } |
| 9220 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 9221 | static void |
| 9222 | skylake_get_initial_plane_config(struct intel_crtc *crtc, |
| 9223 | struct intel_initial_plane_config *plane_config) |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9224 | { |
| 9225 | struct drm_device *dev = crtc->base.dev; |
| 9226 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 40f4628 | 2015-02-27 11:15:21 +0000 | [diff] [blame] | 9227 | u32 val, base, offset, stride_mult, tiling; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9228 | int pipe = crtc->pipe; |
| 9229 | int fourcc, pixel_format; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 9230 | unsigned int aligned_height; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9231 | struct drm_framebuffer *fb; |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9232 | struct intel_framebuffer *intel_fb; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9233 | |
Damien Lespiau | d9806c9 | 2015-01-21 14:07:19 +0000 | [diff] [blame] | 9234 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9235 | if (!intel_fb) { |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9236 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 9237 | return; |
| 9238 | } |
| 9239 | |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9240 | fb = &intel_fb->base; |
| 9241 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9242 | val = I915_READ(PLANE_CTL(pipe, 0)); |
Damien Lespiau | 42a7b08 | 2015-02-05 19:35:13 +0000 | [diff] [blame] | 9243 | if (!(val & PLANE_CTL_ENABLE)) |
| 9244 | goto error; |
| 9245 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9246 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
| 9247 | fourcc = skl_format_to_fourcc(pixel_format, |
| 9248 | val & PLANE_CTL_ORDER_RGBX, |
| 9249 | val & PLANE_CTL_ALPHA_MASK); |
| 9250 | fb->pixel_format = fourcc; |
| 9251 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
| 9252 | |
Damien Lespiau | 40f4628 | 2015-02-27 11:15:21 +0000 | [diff] [blame] | 9253 | tiling = val & PLANE_CTL_TILED_MASK; |
| 9254 | switch (tiling) { |
| 9255 | case PLANE_CTL_TILED_LINEAR: |
| 9256 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; |
| 9257 | break; |
| 9258 | case PLANE_CTL_TILED_X: |
| 9259 | plane_config->tiling = I915_TILING_X; |
| 9260 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 9261 | break; |
| 9262 | case PLANE_CTL_TILED_Y: |
| 9263 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; |
| 9264 | break; |
| 9265 | case PLANE_CTL_TILED_YF: |
| 9266 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; |
| 9267 | break; |
| 9268 | default: |
| 9269 | MISSING_CASE(tiling); |
| 9270 | goto error; |
| 9271 | } |
| 9272 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9273 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
| 9274 | plane_config->base = base; |
| 9275 | |
| 9276 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); |
| 9277 | |
| 9278 | val = I915_READ(PLANE_SIZE(pipe, 0)); |
| 9279 | fb->height = ((val >> 16) & 0xfff) + 1; |
| 9280 | fb->width = ((val >> 0) & 0x1fff) + 1; |
| 9281 | |
| 9282 | val = I915_READ(PLANE_STRIDE(pipe, 0)); |
Damien Lespiau | 40f4628 | 2015-02-27 11:15:21 +0000 | [diff] [blame] | 9283 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
| 9284 | fb->pixel_format); |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9285 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
| 9286 | |
| 9287 | aligned_height = intel_fb_align_height(dev, fb->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 9288 | fb->pixel_format, |
| 9289 | fb->modifier[0]); |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9290 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 9291 | plane_config->size = fb->pitches[0] * aligned_height; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9292 | |
| 9293 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 9294 | pipe_name(pipe), fb->width, fb->height, |
| 9295 | fb->bits_per_pixel, base, fb->pitches[0], |
| 9296 | plane_config->size); |
| 9297 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 9298 | plane_config->fb = intel_fb; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 9299 | return; |
| 9300 | |
| 9301 | error: |
| 9302 | kfree(fb); |
| 9303 | } |
| 9304 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9305 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9306 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9307 | { |
| 9308 | struct drm_device *dev = crtc->base.dev; |
| 9309 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9310 | uint32_t tmp; |
| 9311 | |
| 9312 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
| 9313 | |
| 9314 | if (tmp & PF_ENABLE) { |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 9315 | pipe_config->pch_pfit.enabled = true; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9316 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
| 9317 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
Daniel Vetter | cb8b2a3 | 2013-06-01 17:16:23 +0200 | [diff] [blame] | 9318 | |
| 9319 | /* We currently do not free assignements of panel fitters on |
| 9320 | * ivb/hsw (since we don't use the higher upscaling modes which |
| 9321 | * differentiates them) so just WARN about this case for now. */ |
| 9322 | if (IS_GEN7(dev)) { |
| 9323 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
| 9324 | PF_PIPE_SEL_IVB(crtc->pipe)); |
| 9325 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9326 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9327 | } |
| 9328 | |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 9329 | static void |
| 9330 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, |
| 9331 | struct intel_initial_plane_config *plane_config) |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9332 | { |
| 9333 | struct drm_device *dev = crtc->base.dev; |
| 9334 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9335 | u32 val, base, offset; |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9336 | int pipe = crtc->pipe; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9337 | int fourcc, pixel_format; |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 9338 | unsigned int aligned_height; |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9339 | struct drm_framebuffer *fb; |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9340 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9341 | |
Damien Lespiau | 42a7b08 | 2015-02-05 19:35:13 +0000 | [diff] [blame] | 9342 | val = I915_READ(DSPCNTR(pipe)); |
| 9343 | if (!(val & DISPLAY_PLANE_ENABLE)) |
| 9344 | return; |
| 9345 | |
Damien Lespiau | d9806c9 | 2015-01-21 14:07:19 +0000 | [diff] [blame] | 9346 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9347 | if (!intel_fb) { |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9348 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 9349 | return; |
| 9350 | } |
| 9351 | |
Damien Lespiau | 1b842c8 | 2015-01-21 13:50:54 +0000 | [diff] [blame] | 9352 | fb = &intel_fb->base; |
| 9353 | |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 9354 | if (INTEL_INFO(dev)->gen >= 4) { |
| 9355 | if (val & DISPPLANE_TILED) { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 9356 | plane_config->tiling = I915_TILING_X; |
Daniel Vetter | 18c5247 | 2015-02-10 17:16:09 +0000 | [diff] [blame] | 9357 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 9358 | } |
| 9359 | } |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9360 | |
| 9361 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
Damien Lespiau | b35d63f | 2015-01-20 12:51:50 +0000 | [diff] [blame] | 9362 | fourcc = i9xx_format_to_fourcc(pixel_format); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9363 | fb->pixel_format = fourcc; |
| 9364 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9365 | |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9366 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9367 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9368 | offset = I915_READ(DSPOFFSET(pipe)); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9369 | } else { |
Damien Lespiau | 49af449 | 2015-01-20 12:51:44 +0000 | [diff] [blame] | 9370 | if (plane_config->tiling) |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9371 | offset = I915_READ(DSPTILEOFF(pipe)); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9372 | else |
Damien Lespiau | aeee5a4 | 2015-01-20 12:51:47 +0000 | [diff] [blame] | 9373 | offset = I915_READ(DSPLINOFF(pipe)); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9374 | } |
| 9375 | plane_config->base = base; |
| 9376 | |
| 9377 | val = I915_READ(PIPESRC(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9378 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 9379 | fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9380 | |
| 9381 | val = I915_READ(DSPSTRIDE(pipe)); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9382 | fb->pitches[0] = val & 0xffffffc0; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9383 | |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9384 | aligned_height = intel_fb_align_height(dev, fb->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 9385 | fb->pixel_format, |
| 9386 | fb->modifier[0]); |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9387 | |
Daniel Vetter | f37b5c2 | 2015-02-10 23:12:27 +0100 | [diff] [blame] | 9388 | plane_config->size = fb->pitches[0] * aligned_height; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9389 | |
Damien Lespiau | 2844a92 | 2015-01-20 12:51:48 +0000 | [diff] [blame] | 9390 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 9391 | pipe_name(pipe), fb->width, fb->height, |
| 9392 | fb->bits_per_pixel, base, fb->pitches[0], |
| 9393 | plane_config->size); |
Damien Lespiau | b113d5e | 2015-01-20 12:51:46 +0000 | [diff] [blame] | 9394 | |
Damien Lespiau | 2d14030 | 2015-02-05 17:22:18 +0000 | [diff] [blame] | 9395 | plane_config->fb = intel_fb; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 9396 | } |
| 9397 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9398 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9399 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9400 | { |
| 9401 | struct drm_device *dev = crtc->base.dev; |
| 9402 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9403 | uint32_t tmp; |
| 9404 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 9405 | if (!intel_display_power_is_enabled(dev_priv, |
| 9406 | POWER_DOMAIN_PIPE(crtc->pipe))) |
Paulo Zanoni | 930e8c9 | 2014-07-04 13:38:34 -0300 | [diff] [blame] | 9407 | return false; |
| 9408 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 9409 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9410 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 9411 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9412 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 9413 | if (!(tmp & PIPECONF_ENABLE)) |
| 9414 | return false; |
| 9415 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 9416 | switch (tmp & PIPECONF_BPC_MASK) { |
| 9417 | case PIPECONF_6BPC: |
| 9418 | pipe_config->pipe_bpp = 18; |
| 9419 | break; |
| 9420 | case PIPECONF_8BPC: |
| 9421 | pipe_config->pipe_bpp = 24; |
| 9422 | break; |
| 9423 | case PIPECONF_10BPC: |
| 9424 | pipe_config->pipe_bpp = 30; |
| 9425 | break; |
| 9426 | case PIPECONF_12BPC: |
| 9427 | pipe_config->pipe_bpp = 36; |
| 9428 | break; |
| 9429 | default: |
| 9430 | break; |
| 9431 | } |
| 9432 | |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 9433 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
| 9434 | pipe_config->limited_color_range = true; |
| 9435 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 9436 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9437 | struct intel_shared_dpll *pll; |
| 9438 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 9439 | pipe_config->has_pch_encoder = true; |
| 9440 | |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 9441 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
| 9442 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 9443 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9444 | |
| 9445 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9446 | |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9447 | if (HAS_PCH_IBX(dev_priv->dev)) { |
Daniel Vetter | d94ab06 | 2013-07-04 12:01:16 +0200 | [diff] [blame] | 9448 | pipe_config->shared_dpll = |
| 9449 | (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9450 | } else { |
| 9451 | tmp = I915_READ(PCH_DPLL_SEL); |
| 9452 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
| 9453 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
| 9454 | else |
| 9455 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
| 9456 | } |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9457 | |
| 9458 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 9459 | |
| 9460 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 9461 | &pipe_config->dpll_hw_state)); |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 9462 | |
| 9463 | tmp = pipe_config->dpll_hw_state.dpll; |
| 9464 | pipe_config->pixel_multiplier = |
| 9465 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
| 9466 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 9467 | |
| 9468 | ironlake_pch_clock_get(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9469 | } else { |
| 9470 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 9471 | } |
| 9472 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9473 | intel_get_pipe_timings(crtc, pipe_config); |
| 9474 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9475 | ironlake_get_pfit_config(crtc, pipe_config); |
| 9476 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9477 | return true; |
| 9478 | } |
| 9479 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9480 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
| 9481 | { |
| 9482 | struct drm_device *dev = dev_priv->dev; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9483 | struct intel_crtc *crtc; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9484 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 9485 | for_each_intel_crtc(dev, crtc) |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9486 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9487 | pipe_name(crtc->pipe)); |
| 9488 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9489 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
| 9490 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
Ville Syrjälä | 01403de | 2015-09-18 20:03:33 +0300 | [diff] [blame] | 9491 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
| 9492 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9493 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
| 9494 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9495 | "CPU PWM1 enabled\n"); |
Paulo Zanoni | c5107b8 | 2014-07-04 11:50:30 -0300 | [diff] [blame] | 9496 | if (IS_HASWELL(dev)) |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9497 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
Paulo Zanoni | c5107b8 | 2014-07-04 11:50:30 -0300 | [diff] [blame] | 9498 | "CPU PWM2 enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9499 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9500 | "PCH PWM1 enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9501 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9502 | "Utility pin enabled\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9503 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9504 | |
Paulo Zanoni | 9926ada | 2014-04-01 19:39:47 -0300 | [diff] [blame] | 9505 | /* |
| 9506 | * In theory we can still leave IRQs enabled, as long as only the HPD |
| 9507 | * interrupts remain enabled. We used to check for that, but since it's |
| 9508 | * gen-specific and since we only disable LCPLL after we fully disable |
| 9509 | * the interrupts, the check below should be enough. |
| 9510 | */ |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 9511 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9512 | } |
| 9513 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 9514 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
| 9515 | { |
| 9516 | struct drm_device *dev = dev_priv->dev; |
| 9517 | |
| 9518 | if (IS_HASWELL(dev)) |
| 9519 | return I915_READ(D_COMP_HSW); |
| 9520 | else |
| 9521 | return I915_READ(D_COMP_BDW); |
| 9522 | } |
| 9523 | |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 9524 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
| 9525 | { |
| 9526 | struct drm_device *dev = dev_priv->dev; |
| 9527 | |
| 9528 | if (IS_HASWELL(dev)) { |
| 9529 | mutex_lock(&dev_priv->rps.hw_lock); |
| 9530 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
| 9531 | val)) |
Paulo Zanoni | f475dad | 2014-07-04 11:59:57 -0300 | [diff] [blame] | 9532 | DRM_ERROR("Failed to write to D_COMP\n"); |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 9533 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 9534 | } else { |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 9535 | I915_WRITE(D_COMP_BDW, val); |
| 9536 | POSTING_READ(D_COMP_BDW); |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 9537 | } |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9538 | } |
| 9539 | |
| 9540 | /* |
| 9541 | * This function implements pieces of two sequences from BSpec: |
| 9542 | * - Sequence for display software to disable LCPLL |
| 9543 | * - Sequence for display software to allow package C8+ |
| 9544 | * The steps implemented here are just the steps that actually touch the LCPLL |
| 9545 | * register. Callers should take care of disabling all the display engine |
| 9546 | * functions, doing the mode unset, fixing interrupts, etc. |
| 9547 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 9548 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
| 9549 | bool switch_to_fclk, bool allow_power_down) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9550 | { |
| 9551 | uint32_t val; |
| 9552 | |
| 9553 | assert_can_disable_lcpll(dev_priv); |
| 9554 | |
| 9555 | val = I915_READ(LCPLL_CTL); |
| 9556 | |
| 9557 | if (switch_to_fclk) { |
| 9558 | val |= LCPLL_CD_SOURCE_FCLK; |
| 9559 | I915_WRITE(LCPLL_CTL, val); |
| 9560 | |
| 9561 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
| 9562 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 9563 | DRM_ERROR("Switching to FCLK failed\n"); |
| 9564 | |
| 9565 | val = I915_READ(LCPLL_CTL); |
| 9566 | } |
| 9567 | |
| 9568 | val |= LCPLL_PLL_DISABLE; |
| 9569 | I915_WRITE(LCPLL_CTL, val); |
| 9570 | POSTING_READ(LCPLL_CTL); |
| 9571 | |
| 9572 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
| 9573 | DRM_ERROR("LCPLL still locked\n"); |
| 9574 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 9575 | val = hsw_read_dcomp(dev_priv); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9576 | val |= D_COMP_COMP_DISABLE; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 9577 | hsw_write_dcomp(dev_priv, val); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9578 | ndelay(100); |
| 9579 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 9580 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
| 9581 | 1)) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9582 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
| 9583 | |
| 9584 | if (allow_power_down) { |
| 9585 | val = I915_READ(LCPLL_CTL); |
| 9586 | val |= LCPLL_POWER_DOWN_ALLOW; |
| 9587 | I915_WRITE(LCPLL_CTL, val); |
| 9588 | POSTING_READ(LCPLL_CTL); |
| 9589 | } |
| 9590 | } |
| 9591 | |
| 9592 | /* |
| 9593 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
| 9594 | * source. |
| 9595 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 9596 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9597 | { |
| 9598 | uint32_t val; |
| 9599 | |
| 9600 | val = I915_READ(LCPLL_CTL); |
| 9601 | |
| 9602 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
| 9603 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
| 9604 | return; |
| 9605 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 9606 | /* |
| 9607 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
| 9608 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 9609 | */ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 9610 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 9611 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9612 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
| 9613 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
| 9614 | I915_WRITE(LCPLL_CTL, val); |
Daniel Vetter | 35d8f2e | 2013-08-21 23:38:08 +0200 | [diff] [blame] | 9615 | POSTING_READ(LCPLL_CTL); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9616 | } |
| 9617 | |
Paulo Zanoni | 9ccd5ae | 2014-07-04 11:59:58 -0300 | [diff] [blame] | 9618 | val = hsw_read_dcomp(dev_priv); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9619 | val |= D_COMP_COMP_FORCE; |
| 9620 | val &= ~D_COMP_COMP_DISABLE; |
Paulo Zanoni | 3c4c9b8 | 2014-03-07 20:12:36 -0300 | [diff] [blame] | 9621 | hsw_write_dcomp(dev_priv, val); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9622 | |
| 9623 | val = I915_READ(LCPLL_CTL); |
| 9624 | val &= ~LCPLL_PLL_DISABLE; |
| 9625 | I915_WRITE(LCPLL_CTL, val); |
| 9626 | |
| 9627 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
| 9628 | DRM_ERROR("LCPLL not locked yet\n"); |
| 9629 | |
| 9630 | if (val & LCPLL_CD_SOURCE_FCLK) { |
| 9631 | val = I915_READ(LCPLL_CTL); |
| 9632 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 9633 | I915_WRITE(LCPLL_CTL, val); |
| 9634 | |
| 9635 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
| 9636 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 9637 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 9638 | } |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 9639 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 9640 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 9641 | intel_update_cdclk(dev_priv->dev); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 9642 | } |
| 9643 | |
Paulo Zanoni | 765dab67 | 2014-03-07 20:08:18 -0300 | [diff] [blame] | 9644 | /* |
| 9645 | * Package states C8 and deeper are really deep PC states that can only be |
| 9646 | * reached when all the devices on the system allow it, so even if the graphics |
| 9647 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 9648 | * states. Our driver only allows PC8+ when going into runtime PM. |
| 9649 | * |
| 9650 | * The requirements for PC8+ are that all the outputs are disabled, the power |
| 9651 | * well is disabled and most interrupts are disabled, and these are also |
| 9652 | * requirements for runtime PM. When these conditions are met, we manually do |
| 9653 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
| 9654 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
| 9655 | * hang the machine. |
| 9656 | * |
| 9657 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 9658 | * the state of some registers, so when we come back from PC8+ we need to |
| 9659 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 9660 | * need to take care of the registers kept by RC6. Notice that this happens even |
| 9661 | * if we don't put the device in PCI D3 state (which is what currently happens |
| 9662 | * because of the runtime PM support). |
| 9663 | * |
| 9664 | * For more, read "Display Sequences for Package C8" on the hardware |
| 9665 | * documentation. |
| 9666 | */ |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 9667 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9668 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9669 | struct drm_device *dev = dev_priv->dev; |
| 9670 | uint32_t val; |
| 9671 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9672 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
| 9673 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 9674 | if (HAS_PCH_LPT_LP(dev)) { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9675 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 9676 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 9677 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 9678 | } |
| 9679 | |
| 9680 | lpt_disable_clkout_dp(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9681 | hsw_disable_lcpll(dev_priv, true, true); |
| 9682 | } |
| 9683 | |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 9684 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9685 | { |
| 9686 | struct drm_device *dev = dev_priv->dev; |
| 9687 | uint32_t val; |
| 9688 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9689 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
| 9690 | |
| 9691 | hsw_restore_lcpll(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9692 | lpt_init_pch_refclk(dev); |
| 9693 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 9694 | if (HAS_PCH_LPT_LP(dev)) { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9695 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 9696 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
| 9697 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 9698 | } |
| 9699 | |
| 9700 | intel_prepare_ddi(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 9701 | } |
| 9702 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9703 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 9704 | { |
Ander Conselvan de Oliveira | a821fc4 | 2015-04-21 17:13:23 +0300 | [diff] [blame] | 9705 | struct drm_device *dev = old_state->dev; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 9706 | struct intel_atomic_state *old_intel_state = |
| 9707 | to_intel_atomic_state(old_state); |
| 9708 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 9709 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9710 | broxton_set_cdclk(dev, req_cdclk); |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 9711 | } |
| 9712 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9713 | /* compute the max rate for new configuration */ |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9714 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9715 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9716 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 9717 | struct drm_i915_private *dev_priv = state->dev->dev_private; |
| 9718 | struct drm_crtc *crtc; |
| 9719 | struct drm_crtc_state *cstate; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9720 | struct intel_crtc_state *crtc_state; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9721 | unsigned max_pixel_rate = 0, i; |
| 9722 | enum pipe pipe; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9723 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9724 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 9725 | sizeof(intel_state->min_pixclk)); |
| 9726 | |
| 9727 | for_each_crtc_in_state(state, crtc, cstate, i) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9728 | int pixel_rate; |
| 9729 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9730 | crtc_state = to_intel_crtc_state(cstate); |
| 9731 | if (!crtc_state->base.enable) { |
| 9732 | intel_state->min_pixclk[i] = 0; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9733 | continue; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9734 | } |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9735 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9736 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9737 | |
| 9738 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9739 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9740 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
| 9741 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9742 | intel_state->min_pixclk[i] = pixel_rate; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9743 | } |
| 9744 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 9745 | if (!intel_state->active_crtcs) |
| 9746 | return 0; |
| 9747 | |
| 9748 | for_each_pipe(dev_priv, pipe) |
| 9749 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); |
| 9750 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9751 | return max_pixel_rate; |
| 9752 | } |
| 9753 | |
| 9754 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) |
| 9755 | { |
| 9756 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9757 | uint32_t val, data; |
| 9758 | int ret; |
| 9759 | |
| 9760 | if (WARN((I915_READ(LCPLL_CTL) & |
| 9761 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | |
| 9762 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | |
| 9763 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | |
| 9764 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, |
| 9765 | "trying to change cdclk frequency with cdclk not enabled\n")) |
| 9766 | return; |
| 9767 | |
| 9768 | mutex_lock(&dev_priv->rps.hw_lock); |
| 9769 | ret = sandybridge_pcode_write(dev_priv, |
| 9770 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); |
| 9771 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 9772 | if (ret) { |
| 9773 | DRM_ERROR("failed to inform pcode about cdclk change\n"); |
| 9774 | return; |
| 9775 | } |
| 9776 | |
| 9777 | val = I915_READ(LCPLL_CTL); |
| 9778 | val |= LCPLL_CD_SOURCE_FCLK; |
| 9779 | I915_WRITE(LCPLL_CTL, val); |
| 9780 | |
| 9781 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
| 9782 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 9783 | DRM_ERROR("Switching to FCLK failed\n"); |
| 9784 | |
| 9785 | val = I915_READ(LCPLL_CTL); |
| 9786 | val &= ~LCPLL_CLK_FREQ_MASK; |
| 9787 | |
| 9788 | switch (cdclk) { |
| 9789 | case 450000: |
| 9790 | val |= LCPLL_CLK_FREQ_450; |
| 9791 | data = 0; |
| 9792 | break; |
| 9793 | case 540000: |
| 9794 | val |= LCPLL_CLK_FREQ_54O_BDW; |
| 9795 | data = 1; |
| 9796 | break; |
| 9797 | case 337500: |
| 9798 | val |= LCPLL_CLK_FREQ_337_5_BDW; |
| 9799 | data = 2; |
| 9800 | break; |
| 9801 | case 675000: |
| 9802 | val |= LCPLL_CLK_FREQ_675_BDW; |
| 9803 | data = 3; |
| 9804 | break; |
| 9805 | default: |
| 9806 | WARN(1, "invalid cdclk frequency\n"); |
| 9807 | return; |
| 9808 | } |
| 9809 | |
| 9810 | I915_WRITE(LCPLL_CTL, val); |
| 9811 | |
| 9812 | val = I915_READ(LCPLL_CTL); |
| 9813 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 9814 | I915_WRITE(LCPLL_CTL, val); |
| 9815 | |
| 9816 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
| 9817 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 9818 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 9819 | |
| 9820 | mutex_lock(&dev_priv->rps.hw_lock); |
| 9821 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); |
| 9822 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 9823 | |
| 9824 | intel_update_cdclk(dev); |
| 9825 | |
| 9826 | WARN(cdclk != dev_priv->cdclk_freq, |
| 9827 | "cdclk requested %d kHz but got %d kHz\n", |
| 9828 | cdclk, dev_priv->cdclk_freq); |
| 9829 | } |
| 9830 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9831 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9832 | { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9833 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 9834 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9835 | int max_pixclk = ilk_max_pixel_rate(state); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9836 | int cdclk; |
| 9837 | |
| 9838 | /* |
| 9839 | * FIXME should also account for plane ratio |
| 9840 | * once 64bpp pixel formats are supported. |
| 9841 | */ |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9842 | if (max_pixclk > 540000) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9843 | cdclk = 675000; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9844 | else if (max_pixclk > 450000) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9845 | cdclk = 540000; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9846 | else if (max_pixclk > 337500) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9847 | cdclk = 450000; |
| 9848 | else |
| 9849 | cdclk = 337500; |
| 9850 | |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9851 | if (cdclk > dev_priv->max_cdclk_freq) { |
Maarten Lankhorst | 63ba534 | 2015-11-24 11:29:03 +0100 | [diff] [blame] | 9852 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
| 9853 | cdclk, dev_priv->max_cdclk_freq); |
| 9854 | return -EINVAL; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9855 | } |
| 9856 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 9857 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 9858 | if (!intel_state->active_crtcs) |
| 9859 | intel_state->dev_cdclk = 337500; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9860 | |
| 9861 | return 0; |
| 9862 | } |
| 9863 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9864 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9865 | { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9866 | struct drm_device *dev = old_state->dev; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 9867 | struct intel_atomic_state *old_intel_state = |
| 9868 | to_intel_atomic_state(old_state); |
| 9869 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9870 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 9871 | broadwell_set_cdclk(dev, req_cdclk); |
Ville Syrjälä | b432e5c | 2015-06-03 15:45:13 +0300 | [diff] [blame] | 9872 | } |
| 9873 | |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9874 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
| 9875 | struct intel_crtc_state *crtc_state) |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 9876 | { |
Ander Conselvan de Oliveira | 190f68c | 2015-01-15 14:55:23 +0200 | [diff] [blame] | 9877 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 9878 | return -EINVAL; |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 9879 | |
Ander Conselvan de Oliveira | c765319 | 2014-10-20 13:46:44 +0300 | [diff] [blame] | 9880 | crtc->lowfreq_avail = false; |
Daniel Vetter | 644cef3 | 2014-04-24 23:55:07 +0200 | [diff] [blame] | 9881 | |
Daniel Vetter | c8f7a0d | 2014-04-24 23:55:04 +0200 | [diff] [blame] | 9882 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 9883 | } |
| 9884 | |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 9885 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 9886 | enum port port, |
| 9887 | struct intel_crtc_state *pipe_config) |
| 9888 | { |
| 9889 | switch (port) { |
| 9890 | case PORT_A: |
| 9891 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
| 9892 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; |
| 9893 | break; |
| 9894 | case PORT_B: |
| 9895 | pipe_config->ddi_pll_sel = SKL_DPLL1; |
| 9896 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; |
| 9897 | break; |
| 9898 | case PORT_C: |
| 9899 | pipe_config->ddi_pll_sel = SKL_DPLL2; |
| 9900 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; |
| 9901 | break; |
| 9902 | default: |
| 9903 | DRM_ERROR("Incorrect port type\n"); |
| 9904 | } |
| 9905 | } |
| 9906 | |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9907 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 9908 | enum port port, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9909 | struct intel_crtc_state *pipe_config) |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9910 | { |
Damien Lespiau | 3148ade | 2014-11-21 16:14:56 +0000 | [diff] [blame] | 9911 | u32 temp, dpll_ctl1; |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9912 | |
| 9913 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); |
| 9914 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); |
| 9915 | |
| 9916 | switch (pipe_config->ddi_pll_sel) { |
Damien Lespiau | 3148ade | 2014-11-21 16:14:56 +0000 | [diff] [blame] | 9917 | case SKL_DPLL0: |
| 9918 | /* |
| 9919 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part |
| 9920 | * of the shared DPLL framework and thus needs to be read out |
| 9921 | * separately |
| 9922 | */ |
| 9923 | dpll_ctl1 = I915_READ(DPLL_CTRL1); |
| 9924 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; |
| 9925 | break; |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9926 | case SKL_DPLL1: |
| 9927 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; |
| 9928 | break; |
| 9929 | case SKL_DPLL2: |
| 9930 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; |
| 9931 | break; |
| 9932 | case SKL_DPLL3: |
| 9933 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; |
| 9934 | break; |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9935 | } |
| 9936 | } |
| 9937 | |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 9938 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 9939 | enum port port, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9940 | struct intel_crtc_state *pipe_config) |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 9941 | { |
| 9942 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
| 9943 | |
| 9944 | switch (pipe_config->ddi_pll_sel) { |
| 9945 | case PORT_CLK_SEL_WRPLL1: |
| 9946 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; |
| 9947 | break; |
| 9948 | case PORT_CLK_SEL_WRPLL2: |
| 9949 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
| 9950 | break; |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 9951 | case PORT_CLK_SEL_SPLL: |
| 9952 | pipe_config->shared_dpll = DPLL_ID_SPLL; |
Ville Syrjälä | 79bd23d | 2015-12-01 23:32:07 +0200 | [diff] [blame] | 9953 | break; |
Damien Lespiau | 7d2c817 | 2014-07-29 18:06:18 +0100 | [diff] [blame] | 9954 | } |
| 9955 | } |
| 9956 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 9957 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 9958 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 9959 | { |
| 9960 | struct drm_device *dev = crtc->base.dev; |
| 9961 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 9962 | struct intel_shared_dpll *pll; |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 9963 | enum port port; |
| 9964 | uint32_t tmp; |
| 9965 | |
| 9966 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
| 9967 | |
| 9968 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
| 9969 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 9970 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9971 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
Satheeshakrishna M | 3760b59 | 2014-08-22 09:49:11 +0530 | [diff] [blame] | 9972 | else if (IS_BROXTON(dev)) |
| 9973 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 9974 | else |
| 9975 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 9976 | |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 9977 | if (pipe_config->shared_dpll >= 0) { |
| 9978 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 9979 | |
| 9980 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 9981 | &pipe_config->dpll_hw_state)); |
| 9982 | } |
| 9983 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 9984 | /* |
| 9985 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
| 9986 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
| 9987 | * the PCH transcoder is on. |
| 9988 | */ |
Damien Lespiau | ca37045 | 2013-12-03 13:56:24 +0000 | [diff] [blame] | 9989 | if (INTEL_INFO(dev)->gen < 9 && |
| 9990 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 9991 | pipe_config->has_pch_encoder = true; |
| 9992 | |
| 9993 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 9994 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 9995 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
| 9996 | |
| 9997 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
| 9998 | } |
| 9999 | } |
| 10000 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10001 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10002 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10003 | { |
| 10004 | struct drm_device *dev = crtc->base.dev; |
| 10005 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 10006 | enum intel_display_power_domain pfit_domain; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10007 | uint32_t tmp; |
| 10008 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 10009 | if (!intel_display_power_is_enabled(dev_priv, |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 10010 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 10011 | return false; |
| 10012 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 10013 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 10014 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
| 10015 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 10016 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
| 10017 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
| 10018 | enum pipe trans_edp_pipe; |
| 10019 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 10020 | default: |
| 10021 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
| 10022 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 10023 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 10024 | trans_edp_pipe = PIPE_A; |
| 10025 | break; |
| 10026 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 10027 | trans_edp_pipe = PIPE_B; |
| 10028 | break; |
| 10029 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 10030 | trans_edp_pipe = PIPE_C; |
| 10031 | break; |
| 10032 | } |
| 10033 | |
| 10034 | if (trans_edp_pipe == crtc->pipe) |
| 10035 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 10036 | } |
| 10037 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 10038 | if (!intel_display_power_is_enabled(dev_priv, |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 10039 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
Paulo Zanoni | 2bfce95 | 2013-04-18 16:35:40 -0300 | [diff] [blame] | 10040 | return false; |
| 10041 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 10042 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10043 | if (!(tmp & PIPECONF_ENABLE)) |
| 10044 | return false; |
| 10045 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 10046 | haswell_get_ddi_port_state(crtc, pipe_config); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 10047 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 10048 | intel_get_pipe_timings(crtc, pipe_config); |
| 10049 | |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 10050 | if (INTEL_INFO(dev)->gen >= 9) { |
| 10051 | skl_init_scalers(dev, crtc, pipe_config); |
| 10052 | } |
| 10053 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 10054 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
Chandra Konduru | af99ced | 2015-05-11 14:35:47 -0700 | [diff] [blame] | 10055 | |
| 10056 | if (INTEL_INFO(dev)->gen >= 9) { |
| 10057 | pipe_config->scaler_state.scaler_id = -1; |
| 10058 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |
| 10059 | } |
| 10060 | |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 10061 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 10062 | if (INTEL_INFO(dev)->gen >= 9) |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 10063 | skylake_get_pfit_config(crtc, pipe_config); |
Jesse Barnes | ff6d9f5 | 2015-01-21 17:19:54 -0800 | [diff] [blame] | 10064 | else |
Rodrigo Vivi | 1c132b4 | 2015-09-02 15:19:26 -0700 | [diff] [blame] | 10065 | ironlake_get_pfit_config(crtc, pipe_config); |
Jesse Barnes | bd2e244 | 2014-11-13 17:51:47 +0000 | [diff] [blame] | 10066 | } |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 10067 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 10068 | if (IS_HASWELL(dev)) |
| 10069 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
| 10070 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 10071 | |
Clint Taylor | ebb69c9 | 2014-09-30 10:30:22 -0700 | [diff] [blame] | 10072 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
| 10073 | pipe_config->pixel_multiplier = |
| 10074 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; |
| 10075 | } else { |
| 10076 | pipe_config->pixel_multiplier = 1; |
| 10077 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 10078 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10079 | return true; |
| 10080 | } |
| 10081 | |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10082 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10083 | { |
| 10084 | struct drm_device *dev = crtc->dev; |
| 10085 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10087 | uint32_t cntl = 0, size = 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10088 | |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10089 | if (on) { |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 10090 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
| 10091 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10092 | unsigned int stride = roundup_pow_of_two(width) * 4; |
| 10093 | |
| 10094 | switch (stride) { |
| 10095 | default: |
| 10096 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", |
| 10097 | width, stride); |
| 10098 | stride = 256; |
| 10099 | /* fallthrough */ |
| 10100 | case 256: |
| 10101 | case 512: |
| 10102 | case 1024: |
| 10103 | case 2048: |
| 10104 | break; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10105 | } |
| 10106 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10107 | cntl |= CURSOR_ENABLE | |
| 10108 | CURSOR_GAMMA_ENABLE | |
| 10109 | CURSOR_FORMAT_ARGB | |
| 10110 | CURSOR_STRIDE(stride); |
| 10111 | |
| 10112 | size = (height << 12) | width; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10113 | } |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10114 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10115 | if (intel_crtc->cursor_cntl != 0 && |
| 10116 | (intel_crtc->cursor_base != base || |
| 10117 | intel_crtc->cursor_size != size || |
| 10118 | intel_crtc->cursor_cntl != cntl)) { |
| 10119 | /* On these chipsets we can only modify the base/size/stride |
| 10120 | * whilst the cursor is disabled. |
| 10121 | */ |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 10122 | I915_WRITE(CURCNTR(PIPE_A), 0); |
| 10123 | POSTING_READ(CURCNTR(PIPE_A)); |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10124 | intel_crtc->cursor_cntl = 0; |
| 10125 | } |
| 10126 | |
Ville Syrjälä | 99d1f38 | 2014-09-12 20:53:32 +0300 | [diff] [blame] | 10127 | if (intel_crtc->cursor_base != base) { |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 10128 | I915_WRITE(CURBASE(PIPE_A), base); |
Ville Syrjälä | 99d1f38 | 2014-09-12 20:53:32 +0300 | [diff] [blame] | 10129 | intel_crtc->cursor_base = base; |
| 10130 | } |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10131 | |
| 10132 | if (intel_crtc->cursor_size != size) { |
| 10133 | I915_WRITE(CURSIZE, size); |
| 10134 | intel_crtc->cursor_size = size; |
| 10135 | } |
| 10136 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10137 | if (intel_crtc->cursor_cntl != cntl) { |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 10138 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
| 10139 | POSTING_READ(CURCNTR(PIPE_A)); |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10140 | intel_crtc->cursor_cntl = cntl; |
| 10141 | } |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10142 | } |
| 10143 | |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10144 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10145 | { |
| 10146 | struct drm_device *dev = crtc->dev; |
| 10147 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10149 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10150 | uint32_t cntl = 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10151 | |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10152 | if (on) { |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10153 | cntl = MCURSOR_GAMMA_ENABLE; |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 10154 | switch (intel_crtc->base.cursor->state->crtc_w) { |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 10155 | case 64: |
| 10156 | cntl |= CURSOR_MODE_64_ARGB_AX; |
| 10157 | break; |
| 10158 | case 128: |
| 10159 | cntl |= CURSOR_MODE_128_ARGB_AX; |
| 10160 | break; |
| 10161 | case 256: |
| 10162 | cntl |= CURSOR_MODE_256_ARGB_AX; |
| 10163 | break; |
| 10164 | default: |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 10165 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 10166 | return; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10167 | } |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10168 | cntl |= pipe << 28; /* Connect to correct pipe */ |
Ville Syrjälä | 47bf17a | 2014-09-12 20:53:33 +0300 | [diff] [blame] | 10169 | |
Bob Paauwe | fc6f93b | 2015-08-31 14:03:30 -0700 | [diff] [blame] | 10170 | if (HAS_DDI(dev)) |
Ville Syrjälä | 47bf17a | 2014-09-12 20:53:33 +0300 | [diff] [blame] | 10171 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 10172 | } |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10173 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 10174 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 10175 | cntl |= CURSOR_ROTATE_180; |
| 10176 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 10177 | if (intel_crtc->cursor_cntl != cntl) { |
| 10178 | I915_WRITE(CURCNTR(pipe), cntl); |
| 10179 | POSTING_READ(CURCNTR(pipe)); |
| 10180 | intel_crtc->cursor_cntl = cntl; |
| 10181 | } |
| 10182 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 10183 | /* and commit changes on next vblank */ |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 10184 | I915_WRITE(CURBASE(pipe), base); |
| 10185 | POSTING_READ(CURBASE(pipe)); |
Ville Syrjälä | 99d1f38 | 2014-09-12 20:53:32 +0300 | [diff] [blame] | 10186 | |
| 10187 | intel_crtc->cursor_base = base; |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 10188 | } |
| 10189 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10190 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 10191 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 10192 | bool on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10193 | { |
| 10194 | struct drm_device *dev = crtc->dev; |
| 10195 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10197 | int pipe = intel_crtc->pipe; |
Maarten Lankhorst | 9b4101b | 2015-09-10 16:07:59 +0200 | [diff] [blame] | 10198 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
| 10199 | int x = cursor_state->crtc_x; |
| 10200 | int y = cursor_state->crtc_y; |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 10201 | u32 base = 0, pos = 0; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10202 | |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10203 | base = intel_crtc->cursor_addr; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10204 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 10205 | if (x >= intel_crtc->config->pipe_src_w) |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10206 | on = false; |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 10207 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 10208 | if (y >= intel_crtc->config->pipe_src_h) |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10209 | on = false; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10210 | |
| 10211 | if (x < 0) { |
Maarten Lankhorst | 9b4101b | 2015-09-10 16:07:59 +0200 | [diff] [blame] | 10212 | if (x + cursor_state->crtc_w <= 0) |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10213 | on = false; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10214 | |
| 10215 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 10216 | x = -x; |
| 10217 | } |
| 10218 | pos |= x << CURSOR_X_SHIFT; |
| 10219 | |
| 10220 | if (y < 0) { |
Maarten Lankhorst | 9b4101b | 2015-09-10 16:07:59 +0200 | [diff] [blame] | 10221 | if (y + cursor_state->crtc_h <= 0) |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10222 | on = false; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10223 | |
| 10224 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 10225 | y = -y; |
| 10226 | } |
| 10227 | pos |= y << CURSOR_Y_SHIFT; |
| 10228 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 10229 | I915_WRITE(CURPOS(pipe), pos); |
| 10230 | |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 10231 | /* ILK+ do this automagically */ |
| 10232 | if (HAS_GMCH_DISPLAY(dev) && |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 10233 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
Maarten Lankhorst | 9b4101b | 2015-09-10 16:07:59 +0200 | [diff] [blame] | 10234 | base += (cursor_state->crtc_h * |
| 10235 | cursor_state->crtc_w - 1) * 4; |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 10236 | } |
| 10237 | |
Ville Syrjälä | 8ac5466 | 2014-08-12 19:39:54 +0300 | [diff] [blame] | 10238 | if (IS_845G(dev) || IS_I865G(dev)) |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10239 | i845_update_cursor(crtc, base, on); |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 10240 | else |
Ville Syrjälä | 663f312 | 2015-12-14 13:16:48 +0200 | [diff] [blame] | 10241 | i9xx_update_cursor(crtc, base, on); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 10242 | } |
| 10243 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 10244 | static bool cursor_size_ok(struct drm_device *dev, |
| 10245 | uint32_t width, uint32_t height) |
| 10246 | { |
| 10247 | if (width == 0 || height == 0) |
| 10248 | return false; |
| 10249 | |
| 10250 | /* |
| 10251 | * 845g/865g are special in that they are only limited by |
| 10252 | * the width of their cursors, the height is arbitrary up to |
| 10253 | * the precision of the register. Everything else requires |
| 10254 | * square cursors, limited to a few power-of-two sizes. |
| 10255 | */ |
| 10256 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 10257 | if ((width & 63) != 0) |
| 10258 | return false; |
| 10259 | |
| 10260 | if (width > (IS_845G(dev) ? 64 : 512)) |
| 10261 | return false; |
| 10262 | |
| 10263 | if (height > 1023) |
| 10264 | return false; |
| 10265 | } else { |
| 10266 | switch (width | height) { |
| 10267 | case 256: |
| 10268 | case 128: |
| 10269 | if (IS_GEN2(dev)) |
| 10270 | return false; |
| 10271 | case 64: |
| 10272 | break; |
| 10273 | default: |
| 10274 | return false; |
| 10275 | } |
| 10276 | } |
| 10277 | |
| 10278 | return true; |
| 10279 | } |
| 10280 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10281 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 10282 | u16 *blue, uint32_t start, uint32_t size) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10283 | { |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 10284 | int end = (start + size > 256) ? 256 : start + size, i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10286 | |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 10287 | for (i = start; i < end; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10288 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 10289 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 10290 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 10291 | } |
| 10292 | |
| 10293 | intel_crtc_load_lut(crtc); |
| 10294 | } |
| 10295 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10296 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 10297 | static struct drm_display_mode load_detect_mode = { |
| 10298 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 10299 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 10300 | }; |
| 10301 | |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 10302 | struct drm_framebuffer * |
| 10303 | __intel_framebuffer_create(struct drm_device *dev, |
| 10304 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10305 | struct drm_i915_gem_object *obj) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10306 | { |
| 10307 | struct intel_framebuffer *intel_fb; |
| 10308 | int ret; |
| 10309 | |
| 10310 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10311 | if (!intel_fb) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10312 | return ERR_PTR(-ENOMEM); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10313 | |
| 10314 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10315 | if (ret) |
| 10316 | goto err; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10317 | |
| 10318 | return &intel_fb->base; |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10319 | |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10320 | err: |
| 10321 | kfree(intel_fb); |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10322 | return ERR_PTR(ret); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10323 | } |
| 10324 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 10325 | static struct drm_framebuffer * |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 10326 | intel_framebuffer_create(struct drm_device *dev, |
| 10327 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10328 | struct drm_i915_gem_object *obj) |
| 10329 | { |
| 10330 | struct drm_framebuffer *fb; |
| 10331 | int ret; |
| 10332 | |
| 10333 | ret = i915_mutex_lock_interruptible(dev); |
| 10334 | if (ret) |
| 10335 | return ERR_PTR(ret); |
| 10336 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
| 10337 | mutex_unlock(&dev->struct_mutex); |
| 10338 | |
| 10339 | return fb; |
| 10340 | } |
| 10341 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10342 | static u32 |
| 10343 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 10344 | { |
| 10345 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 10346 | return ALIGN(pitch, 64); |
| 10347 | } |
| 10348 | |
| 10349 | static u32 |
| 10350 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 10351 | { |
| 10352 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
Fabian Frederick | 1267a26 | 2014-07-01 20:39:41 +0200 | [diff] [blame] | 10353 | return PAGE_ALIGN(pitch * mode->vdisplay); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10354 | } |
| 10355 | |
| 10356 | static struct drm_framebuffer * |
| 10357 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 10358 | struct drm_display_mode *mode, |
| 10359 | int depth, int bpp) |
| 10360 | { |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10361 | struct drm_framebuffer *fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10362 | struct drm_i915_gem_object *obj; |
Chris Wilson | 0fed39b | 2012-11-05 22:25:07 +0000 | [diff] [blame] | 10363 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10364 | |
| 10365 | obj = i915_gem_alloc_object(dev, |
| 10366 | intel_framebuffer_size_for_mode(mode, bpp)); |
| 10367 | if (obj == NULL) |
| 10368 | return ERR_PTR(-ENOMEM); |
| 10369 | |
| 10370 | mode_cmd.width = mode->hdisplay; |
| 10371 | mode_cmd.height = mode->vdisplay; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 10372 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 10373 | bpp); |
Dave Airlie | 5ca0c34 | 2012-02-23 15:33:40 +0000 | [diff] [blame] | 10374 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10375 | |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 10376 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
| 10377 | if (IS_ERR(fb)) |
| 10378 | drm_gem_object_unreference_unlocked(&obj->base); |
| 10379 | |
| 10380 | return fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10381 | } |
| 10382 | |
| 10383 | static struct drm_framebuffer * |
| 10384 | mode_fits_in_fbdev(struct drm_device *dev, |
| 10385 | struct drm_display_mode *mode) |
| 10386 | { |
Daniel Vetter | 0695726 | 2015-08-10 13:34:08 +0200 | [diff] [blame] | 10387 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10388 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10389 | struct drm_i915_gem_object *obj; |
| 10390 | struct drm_framebuffer *fb; |
| 10391 | |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 10392 | if (!dev_priv->fbdev) |
| 10393 | return NULL; |
| 10394 | |
| 10395 | if (!dev_priv->fbdev->fb) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10396 | return NULL; |
| 10397 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 10398 | obj = dev_priv->fbdev->fb->obj; |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 10399 | BUG_ON(!obj); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10400 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 10401 | fb = &dev_priv->fbdev->fb->base; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 10402 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 10403 | fb->bits_per_pixel)) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10404 | return NULL; |
| 10405 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 10406 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10407 | return NULL; |
| 10408 | |
| 10409 | return fb; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 10410 | #else |
| 10411 | return NULL; |
| 10412 | #endif |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10413 | } |
| 10414 | |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 10415 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
| 10416 | struct drm_crtc *crtc, |
| 10417 | struct drm_display_mode *mode, |
| 10418 | struct drm_framebuffer *fb, |
| 10419 | int x, int y) |
| 10420 | { |
| 10421 | struct drm_plane_state *plane_state; |
| 10422 | int hdisplay, vdisplay; |
| 10423 | int ret; |
| 10424 | |
| 10425 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); |
| 10426 | if (IS_ERR(plane_state)) |
| 10427 | return PTR_ERR(plane_state); |
| 10428 | |
| 10429 | if (mode) |
| 10430 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
| 10431 | else |
| 10432 | hdisplay = vdisplay = 0; |
| 10433 | |
| 10434 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); |
| 10435 | if (ret) |
| 10436 | return ret; |
| 10437 | drm_atomic_set_fb_for_plane(plane_state, fb); |
| 10438 | plane_state->crtc_x = 0; |
| 10439 | plane_state->crtc_y = 0; |
| 10440 | plane_state->crtc_w = hdisplay; |
| 10441 | plane_state->crtc_h = vdisplay; |
| 10442 | plane_state->src_x = x << 16; |
| 10443 | plane_state->src_y = y << 16; |
| 10444 | plane_state->src_w = hdisplay << 16; |
| 10445 | plane_state->src_h = vdisplay << 16; |
| 10446 | |
| 10447 | return 0; |
| 10448 | } |
| 10449 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 10450 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 10451 | struct drm_display_mode *mode, |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10452 | struct intel_load_detect_pipe *old, |
| 10453 | struct drm_modeset_acquire_ctx *ctx) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10454 | { |
| 10455 | struct intel_crtc *intel_crtc; |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 10456 | struct intel_encoder *intel_encoder = |
| 10457 | intel_attached_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10458 | struct drm_crtc *possible_crtc; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 10459 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10460 | struct drm_crtc *crtc = NULL; |
| 10461 | struct drm_device *dev = encoder->dev; |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 10462 | struct drm_framebuffer *fb; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10463 | struct drm_mode_config *config = &dev->mode_config; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10464 | struct drm_atomic_state *state = NULL; |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10465 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 10466 | struct intel_crtc_state *crtc_state; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10467 | int ret, i = -1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10468 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10469 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 10470 | connector->base.id, connector->name, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 10471 | encoder->base.id, encoder->name); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10472 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10473 | retry: |
| 10474 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
| 10475 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10476 | goto fail; |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 10477 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10478 | /* |
| 10479 | * Algorithm gets a little messy: |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 10480 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10481 | * - if the connector already has an assigned crtc, use it (but make |
| 10482 | * sure it's on first) |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 10483 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10484 | * - try to find the first unused crtc that can drive this connector, |
| 10485 | * and use that if we find one |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10486 | */ |
| 10487 | |
| 10488 | /* See if we already have a CRTC for this connector */ |
| 10489 | if (encoder->crtc) { |
| 10490 | crtc = encoder->crtc; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 10491 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10492 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 10493 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10494 | goto fail; |
Daniel Vetter | 4d02e2d | 2014-11-11 10:12:00 +0100 | [diff] [blame] | 10495 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
| 10496 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10497 | goto fail; |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 10498 | |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 10499 | old->dpms_mode = connector->dpms; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 10500 | old->load_detect_temp = false; |
| 10501 | |
| 10502 | /* Make sure the crtc and connector are running */ |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 10503 | if (connector->dpms != DRM_MODE_DPMS_ON) |
| 10504 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 10505 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 10506 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10507 | } |
| 10508 | |
| 10509 | /* Find an unused one (if possible) */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 10510 | for_each_crtc(dev, possible_crtc) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10511 | i++; |
| 10512 | if (!(encoder->possible_crtcs & (1 << i))) |
| 10513 | continue; |
Matt Roper | 83d6573 | 2015-02-25 13:12:16 -0800 | [diff] [blame] | 10514 | if (possible_crtc->state->enable) |
Ville Syrjälä | a459249 | 2014-08-11 13:15:36 +0300 | [diff] [blame] | 10515 | continue; |
Ville Syrjälä | a459249 | 2014-08-11 13:15:36 +0300 | [diff] [blame] | 10516 | |
| 10517 | crtc = possible_crtc; |
| 10518 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10519 | } |
| 10520 | |
| 10521 | /* |
| 10522 | * If we didn't find an unused CRTC, don't use any. |
| 10523 | */ |
| 10524 | if (!crtc) { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 10525 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10526 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10527 | } |
| 10528 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10529 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 10530 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10531 | goto fail; |
Daniel Vetter | 4d02e2d | 2014-11-11 10:12:00 +0100 | [diff] [blame] | 10532 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
| 10533 | if (ret) |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10534 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10535 | |
| 10536 | intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 10537 | old->dpms_mode = connector->dpms; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 10538 | old->load_detect_temp = true; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10539 | old->release_fb = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10540 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10541 | state = drm_atomic_state_alloc(dev); |
| 10542 | if (!state) |
| 10543 | return false; |
| 10544 | |
| 10545 | state->acquire_ctx = ctx; |
| 10546 | |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10547 | connector_state = drm_atomic_get_connector_state(state, connector); |
| 10548 | if (IS_ERR(connector_state)) { |
| 10549 | ret = PTR_ERR(connector_state); |
| 10550 | goto fail; |
| 10551 | } |
| 10552 | |
| 10553 | connector_state->crtc = crtc; |
| 10554 | connector_state->best_encoder = &intel_encoder->base; |
| 10555 | |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 10556 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 10557 | if (IS_ERR(crtc_state)) { |
| 10558 | ret = PTR_ERR(crtc_state); |
| 10559 | goto fail; |
| 10560 | } |
| 10561 | |
Maarten Lankhorst | 49d6fa2 | 2015-05-11 10:45:15 +0200 | [diff] [blame] | 10562 | crtc_state->base.active = crtc_state->base.enable = true; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 10563 | |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 10564 | if (!mode) |
| 10565 | mode = &load_detect_mode; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10566 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10567 | /* We need a framebuffer large enough to accommodate all accesses |
| 10568 | * that the plane may generate whilst we perform load detection. |
| 10569 | * We can not rely on the fbcon either being present (we get called |
| 10570 | * during its initialisation to detect all boot displays, or it may |
| 10571 | * not even exist) or that it is large enough to satisfy the |
| 10572 | * requested mode. |
| 10573 | */ |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 10574 | fb = mode_fits_in_fbdev(dev, mode); |
| 10575 | if (fb == NULL) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10576 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 10577 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
| 10578 | old->release_fb = fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10579 | } else |
| 10580 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 10581 | if (IS_ERR(fb)) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10582 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 10583 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10584 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10585 | |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 10586 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
| 10587 | if (ret) |
| 10588 | goto fail; |
| 10589 | |
Ander Conselvan de Oliveira | 8c7b5cc | 2015-04-21 17:13:19 +0300 | [diff] [blame] | 10590 | drm_mode_copy(&crtc_state->base.mode, mode); |
| 10591 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 10592 | if (drm_atomic_commit(state)) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 10593 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10594 | if (old->release_fb) |
| 10595 | old->release_fb->funcs->destroy(old->release_fb); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 10596 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10597 | } |
Daniel Vetter | 9128b04 | 2015-03-03 17:31:21 +0100 | [diff] [blame] | 10598 | crtc->primary->crtc = crtc; |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 10599 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10600 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 10601 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 10602 | return true; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 10603 | |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 10604 | fail: |
Ander Conselvan de Oliveira | e5d958e | 2015-04-21 17:12:57 +0300 | [diff] [blame] | 10605 | drm_atomic_state_free(state); |
| 10606 | state = NULL; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10607 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 10608 | if (ret == -EDEADLK) { |
| 10609 | drm_modeset_backoff(ctx); |
| 10610 | goto retry; |
| 10611 | } |
| 10612 | |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 10613 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10614 | } |
| 10615 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 10616 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
Ander Conselvan de Oliveira | 49172fe | 2015-03-20 16:18:02 +0200 | [diff] [blame] | 10617 | struct intel_load_detect_pipe *old, |
| 10618 | struct drm_modeset_acquire_ctx *ctx) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10619 | { |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10620 | struct drm_device *dev = connector->dev; |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 10621 | struct intel_encoder *intel_encoder = |
| 10622 | intel_attached_encoder(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 10623 | struct drm_encoder *encoder = &intel_encoder->base; |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 10624 | struct drm_crtc *crtc = encoder->crtc; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 10625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10626 | struct drm_atomic_state *state; |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10627 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 10628 | struct intel_crtc_state *crtc_state; |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 10629 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10630 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10631 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 10632 | connector->base.id, connector->name, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 10633 | encoder->base.id, encoder->name); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10634 | |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 10635 | if (old->load_detect_temp) { |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10636 | state = drm_atomic_state_alloc(dev); |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10637 | if (!state) |
| 10638 | goto fail; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 10639 | |
| 10640 | state->acquire_ctx = ctx; |
| 10641 | |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10642 | connector_state = drm_atomic_get_connector_state(state, connector); |
| 10643 | if (IS_ERR(connector_state)) |
| 10644 | goto fail; |
| 10645 | |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 10646 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 10647 | if (IS_ERR(crtc_state)) |
| 10648 | goto fail; |
| 10649 | |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10650 | connector_state->best_encoder = NULL; |
| 10651 | connector_state->crtc = NULL; |
| 10652 | |
Maarten Lankhorst | 49d6fa2 | 2015-05-11 10:45:15 +0200 | [diff] [blame] | 10653 | crtc_state->base.enable = crtc_state->base.active = false; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 10654 | |
Ander Conselvan de Oliveira | d3a40d1 | 2015-04-21 17:13:09 +0300 | [diff] [blame] | 10655 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
| 10656 | 0, 0); |
| 10657 | if (ret) |
| 10658 | goto fail; |
| 10659 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 10660 | ret = drm_atomic_commit(state); |
Ander Conselvan de Oliveira | 2bfb462 | 2015-04-21 17:13:20 +0300 | [diff] [blame] | 10661 | if (ret) |
| 10662 | goto fail; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10663 | |
Daniel Vetter | 3620636 | 2012-12-10 20:42:17 +0100 | [diff] [blame] | 10664 | if (old->release_fb) { |
| 10665 | drm_framebuffer_unregister_private(old->release_fb); |
| 10666 | drm_framebuffer_unreference(old->release_fb); |
| 10667 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10668 | |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 10669 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10670 | } |
| 10671 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 10672 | /* Switch crtc and encoder back off if necessary */ |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 10673 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
| 10674 | connector->funcs->dpms(connector, old->dpms_mode); |
Ander Conselvan de Oliveira | 944b0c7 | 2015-03-20 16:18:07 +0200 | [diff] [blame] | 10675 | |
| 10676 | return; |
| 10677 | fail: |
| 10678 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); |
| 10679 | drm_atomic_state_free(state); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10680 | } |
| 10681 | |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 10682 | static int i9xx_pll_refclk(struct drm_device *dev, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10683 | const struct intel_crtc_state *pipe_config) |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 10684 | { |
| 10685 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10686 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 10687 | |
| 10688 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 10689 | return dev_priv->vbt.lvds_ssc_freq; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 10690 | else if (HAS_PCH_SPLIT(dev)) |
| 10691 | return 120000; |
| 10692 | else if (!IS_GEN2(dev)) |
| 10693 | return 96000; |
| 10694 | else |
| 10695 | return 48000; |
| 10696 | } |
| 10697 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10698 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10699 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10700 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10701 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10702 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10703 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10704 | int pipe = pipe_config->cpu_transcoder; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 10705 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10706 | u32 fp; |
| 10707 | intel_clock_t clock; |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 10708 | int port_clock; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 10709 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10710 | |
| 10711 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 10712 | fp = pipe_config->dpll_hw_state.fp0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10713 | else |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 10714 | fp = pipe_config->dpll_hw_state.fp1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10715 | |
| 10716 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 10717 | if (IS_PINEVIEW(dev)) { |
| 10718 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 10719 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 10720 | } else { |
| 10721 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 10722 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 10723 | } |
| 10724 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 10725 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 10726 | if (IS_PINEVIEW(dev)) |
| 10727 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 10728 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 10729 | else |
| 10730 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10731 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 10732 | |
| 10733 | switch (dpll & DPLL_MODE_MASK) { |
| 10734 | case DPLLB_MODE_DAC_SERIAL: |
| 10735 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 10736 | 5 : 10; |
| 10737 | break; |
| 10738 | case DPLLB_MODE_LVDS: |
| 10739 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 10740 | 7 : 14; |
| 10741 | break; |
| 10742 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 10743 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10744 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10745 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10746 | } |
| 10747 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 10748 | if (IS_PINEVIEW(dev)) |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 10749 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 10750 | else |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 10751 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10752 | } else { |
Ville Syrjälä | 0fb5822 | 2014-01-10 14:06:46 +0200 | [diff] [blame] | 10753 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 10754 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10755 | |
| 10756 | if (is_lvds) { |
| 10757 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 10758 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 10759 | |
| 10760 | if (lvds & LVDS_CLKB_POWER_UP) |
| 10761 | clock.p2 = 7; |
| 10762 | else |
| 10763 | clock.p2 = 14; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10764 | } else { |
| 10765 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 10766 | clock.p1 = 2; |
| 10767 | else { |
| 10768 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 10769 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 10770 | } |
| 10771 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 10772 | clock.p2 = 4; |
| 10773 | else |
| 10774 | clock.p2 = 2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10775 | } |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 10776 | |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 10777 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10778 | } |
| 10779 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10780 | /* |
| 10781 | * This value includes pixel_multiplier. We will use |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 10782 | * port_clock to compute adjusted_mode.crtc_clock in the |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10783 | * encoder's get_config() function. |
| 10784 | */ |
Imre Deak | dccbea3 | 2015-06-22 23:35:51 +0300 | [diff] [blame] | 10785 | pipe_config->port_clock = port_clock; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10786 | } |
| 10787 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 10788 | int intel_dotclock_calculate(int link_freq, |
| 10789 | const struct intel_link_m_n *m_n) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10790 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10791 | /* |
| 10792 | * The calculation for the data clock is: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 10793 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10794 | * But we want to avoid losing precison if possible, so: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 10795 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10796 | * |
| 10797 | * and the link clock is simpler: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 10798 | * link_clock = (m * link_clock) / n |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10799 | */ |
| 10800 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 10801 | if (!m_n->link_n) |
| 10802 | return 0; |
| 10803 | |
| 10804 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
| 10805 | } |
| 10806 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10807 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10808 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 10809 | { |
| 10810 | struct drm_device *dev = crtc->base.dev; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10811 | |
| 10812 | /* read out port_clock from the DPLL */ |
| 10813 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 10814 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10815 | /* |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10816 | * This value does not include pixel_multiplier. |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 10817 | * We will check that port_clock and adjusted_mode.crtc_clock |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10818 | * agree once we know their relationship in the encoder's |
| 10819 | * get_config() function. |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10820 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 10821 | pipe_config->base.adjusted_mode.crtc_clock = |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 10822 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
| 10823 | &pipe_config->fdi_m_n); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10824 | } |
| 10825 | |
| 10826 | /** Returns the currently programmed mode of the given pipe. */ |
| 10827 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 10828 | struct drm_crtc *crtc) |
| 10829 | { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 10830 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 10832 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10833 | struct drm_display_mode *mode; |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 10834 | struct intel_crtc_state pipe_config; |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 10835 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
| 10836 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 10837 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
| 10838 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 10839 | enum pipe pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10840 | |
| 10841 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 10842 | if (!mode) |
| 10843 | return NULL; |
| 10844 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10845 | /* |
| 10846 | * Construct a pipe_config sufficient for getting the clock info |
| 10847 | * back out of crtc_clock_get. |
| 10848 | * |
| 10849 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
| 10850 | * to use a real value here instead. |
| 10851 | */ |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 10852 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10853 | pipe_config.pixel_multiplier = 1; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 10854 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
| 10855 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
| 10856 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 10857 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
| 10858 | |
Ville Syrjälä | 773ae03 | 2013-09-23 17:48:20 +0300 | [diff] [blame] | 10859 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10860 | mode->hdisplay = (htot & 0xffff) + 1; |
| 10861 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 10862 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 10863 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 10864 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 10865 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 10866 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 10867 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 10868 | |
| 10869 | drm_mode_set_name(mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10870 | |
| 10871 | return mode; |
| 10872 | } |
| 10873 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 10874 | void intel_mark_busy(struct drm_device *dev) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 10875 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10876 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10877 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 10878 | if (dev_priv->mm.busy) |
| 10879 | return; |
| 10880 | |
Paulo Zanoni | 43694d6 | 2014-03-07 20:08:08 -0300 | [diff] [blame] | 10881 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10882 | i915_update_gfx_val(dev_priv); |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 10883 | if (INTEL_INFO(dev)->gen >= 6) |
| 10884 | gen6_rps_busy(dev_priv); |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 10885 | dev_priv->mm.busy = true; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 10886 | } |
| 10887 | |
| 10888 | void intel_mark_idle(struct drm_device *dev) |
| 10889 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 10890 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 725a5b5 | 2013-01-08 11:02:57 +0000 | [diff] [blame] | 10891 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 10892 | if (!dev_priv->mm.busy) |
| 10893 | return; |
| 10894 | |
| 10895 | dev_priv->mm.busy = false; |
| 10896 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 10897 | if (INTEL_INFO(dev)->gen >= 6) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 10898 | gen6_rps_idle(dev->dev_private); |
Paulo Zanoni | bb4cdd5 | 2014-02-21 13:52:19 -0300 | [diff] [blame] | 10899 | |
Paulo Zanoni | 43694d6 | 2014-03-07 20:08:08 -0300 | [diff] [blame] | 10900 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 10901 | } |
| 10902 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10903 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 10904 | { |
| 10905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 10906 | struct drm_device *dev = crtc->dev; |
| 10907 | struct intel_unpin_work *work; |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 10908 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 10909 | spin_lock_irq(&dev->event_lock); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 10910 | work = intel_crtc->unpin_work; |
| 10911 | intel_crtc->unpin_work = NULL; |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 10912 | spin_unlock_irq(&dev->event_lock); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 10913 | |
| 10914 | if (work) { |
| 10915 | cancel_work_sync(&work->work); |
| 10916 | kfree(work); |
| 10917 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10918 | |
| 10919 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 10920 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10921 | kfree(intel_crtc); |
| 10922 | } |
| 10923 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10924 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 10925 | { |
| 10926 | struct intel_unpin_work *work = |
| 10927 | container_of(__work, struct intel_unpin_work, work); |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 10928 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
| 10929 | struct drm_device *dev = crtc->base.dev; |
| 10930 | struct drm_plane *primary = crtc->base.primary; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10931 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 10932 | mutex_lock(&dev->struct_mutex); |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 10933 | intel_unpin_fb_obj(work->old_fb, primary->state); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10934 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 10935 | |
John Harrison | f06cc1b | 2014-11-24 18:49:37 +0000 | [diff] [blame] | 10936 | if (work->flip_queued_req) |
John Harrison | 146d84f | 2014-12-05 13:49:33 +0000 | [diff] [blame] | 10937 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 10938 | mutex_unlock(&dev->struct_mutex); |
| 10939 | |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 10940 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
Chris Wilson | 89ed88b | 2015-02-16 14:31:49 +0000 | [diff] [blame] | 10941 | drm_framebuffer_unreference(work->old_fb); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 10942 | |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 10943 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
| 10944 | atomic_dec(&crtc->unpin_work_count); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 10945 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10946 | kfree(work); |
| 10947 | } |
| 10948 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 10949 | static void do_intel_finish_page_flip(struct drm_device *dev, |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 10950 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10951 | { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10953 | struct intel_unpin_work *work; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10954 | unsigned long flags; |
| 10955 | |
| 10956 | /* Ignore early vblank irqs */ |
| 10957 | if (intel_crtc == NULL) |
| 10958 | return; |
| 10959 | |
Daniel Vetter | f326038 | 2014-09-15 14:55:23 +0200 | [diff] [blame] | 10960 | /* |
| 10961 | * This is called both by irq handlers and the reset code (to complete |
| 10962 | * lost pageflips) so needs the full irqsave spinlocks. |
| 10963 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10964 | spin_lock_irqsave(&dev->event_lock, flags); |
| 10965 | work = intel_crtc->unpin_work; |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 10966 | |
| 10967 | /* Ensure we don't miss a work->pending update ... */ |
| 10968 | smp_rmb(); |
| 10969 | |
| 10970 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10971 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 10972 | return; |
| 10973 | } |
| 10974 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 10975 | page_flip_completed(intel_crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 10976 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10977 | spin_unlock_irqrestore(&dev->event_lock, flags); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 10978 | } |
| 10979 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 10980 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 10981 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 10982 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 10983 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 10984 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 10985 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 10986 | } |
| 10987 | |
| 10988 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 10989 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 10990 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 10991 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 10992 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 10993 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 10994 | } |
| 10995 | |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 10996 | /* Is 'a' after or equal to 'b'? */ |
| 10997 | static bool g4x_flip_count_after_eq(u32 a, u32 b) |
| 10998 | { |
| 10999 | return !((a - b) & 0x80000000); |
| 11000 | } |
| 11001 | |
| 11002 | static bool page_flip_finished(struct intel_crtc *crtc) |
| 11003 | { |
| 11004 | struct drm_device *dev = crtc->base.dev; |
| 11005 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11006 | |
Ville Syrjälä | bdfa754 | 2014-05-27 21:33:09 +0300 | [diff] [blame] | 11007 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
| 11008 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 11009 | return true; |
| 11010 | |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11011 | /* |
| 11012 | * The relevant registers doen't exist on pre-ctg. |
| 11013 | * As the flip done interrupt doesn't trigger for mmio |
| 11014 | * flips on gmch platforms, a flip count check isn't |
| 11015 | * really needed there. But since ctg has the registers, |
| 11016 | * include it in the check anyway. |
| 11017 | */ |
| 11018 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
| 11019 | return true; |
| 11020 | |
| 11021 | /* |
| 11022 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
| 11023 | * used the same base address. In that case the mmio flip might |
| 11024 | * have completed, but the CS hasn't even executed the flip yet. |
| 11025 | * |
| 11026 | * A flip count check isn't enough as the CS might have updated |
| 11027 | * the base address just after start of vblank, but before we |
| 11028 | * managed to process the interrupt. This means we'd complete the |
| 11029 | * CS flip too soon. |
| 11030 | * |
| 11031 | * Combining both checks should get us a good enough result. It may |
| 11032 | * still happen that the CS flip has been executed, but has not |
| 11033 | * yet actually completed. But in case the base address is the same |
| 11034 | * anyway, we don't really care. |
| 11035 | */ |
| 11036 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
| 11037 | crtc->unpin_work->gtt_offset && |
Ville Syrjälä | fd8f507c | 2015-09-18 20:03:42 +0300 | [diff] [blame] | 11038 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11039 | crtc->unpin_work->flip_count); |
| 11040 | } |
| 11041 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11042 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 11043 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 11044 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11045 | struct intel_crtc *intel_crtc = |
| 11046 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 11047 | unsigned long flags; |
| 11048 | |
Daniel Vetter | f326038 | 2014-09-15 14:55:23 +0200 | [diff] [blame] | 11049 | |
| 11050 | /* |
| 11051 | * This is called both by irq handlers and the reset code (to complete |
| 11052 | * lost pageflips) so needs the full irqsave spinlocks. |
| 11053 | * |
| 11054 | * NB: An MMIO update of the plane base pointer will also |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11055 | * generate a page-flip completion irq, i.e. every modeset |
| 11056 | * is also accompanied by a spurious intel_prepare_page_flip(). |
| 11057 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11058 | spin_lock_irqsave(&dev->event_lock, flags); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11059 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11060 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11061 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 11062 | } |
| 11063 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11064 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11065 | { |
| 11066 | /* Ensure that the work item is consistent when activating it ... */ |
| 11067 | smp_wmb(); |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11068 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11069 | /* and that it is marked active as soon as the irq could fire. */ |
| 11070 | smp_wmb(); |
| 11071 | } |
| 11072 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11073 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 11074 | struct drm_crtc *crtc, |
| 11075 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11076 | struct drm_i915_gem_object *obj, |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11077 | struct drm_i915_gem_request *req, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11078 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11079 | { |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11080 | struct intel_engine_cs *ring = req->ring; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11082 | u32 flip_mask; |
| 11083 | int ret; |
| 11084 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 11085 | ret = intel_ring_begin(req, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11086 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11087 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11088 | |
| 11089 | /* Can't queue multiple flips, so wait for the previous |
| 11090 | * one to finish before executing the next. |
| 11091 | */ |
| 11092 | if (intel_crtc->plane) |
| 11093 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 11094 | else |
| 11095 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11096 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 11097 | intel_ring_emit(ring, MI_NOOP); |
| 11098 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 11099 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11100 | intel_ring_emit(ring, fb->pitches[0]); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11101 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11102 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11103 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11104 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 11105 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11106 | } |
| 11107 | |
| 11108 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 11109 | struct drm_crtc *crtc, |
| 11110 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11111 | struct drm_i915_gem_object *obj, |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11112 | struct drm_i915_gem_request *req, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11113 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11114 | { |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11115 | struct intel_engine_cs *ring = req->ring; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11117 | u32 flip_mask; |
| 11118 | int ret; |
| 11119 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 11120 | ret = intel_ring_begin(req, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11121 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11122 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11123 | |
| 11124 | if (intel_crtc->plane) |
| 11125 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 11126 | else |
| 11127 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11128 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 11129 | intel_ring_emit(ring, MI_NOOP); |
| 11130 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
| 11131 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11132 | intel_ring_emit(ring, fb->pitches[0]); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11133 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11134 | intel_ring_emit(ring, MI_NOOP); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11135 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11136 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 11137 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11138 | } |
| 11139 | |
| 11140 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 11141 | struct drm_crtc *crtc, |
| 11142 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11143 | struct drm_i915_gem_object *obj, |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11144 | struct drm_i915_gem_request *req, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11145 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11146 | { |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11147 | struct intel_engine_cs *ring = req->ring; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11148 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11150 | uint32_t pf, pipesrc; |
| 11151 | int ret; |
| 11152 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 11153 | ret = intel_ring_begin(req, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11154 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11155 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11156 | |
| 11157 | /* i965+ uses the linear or tiled offsets from the |
| 11158 | * Display Registers (which do not change across a page-flip) |
| 11159 | * so we need only reprogram the base address. |
| 11160 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11161 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 11162 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11163 | intel_ring_emit(ring, fb->pitches[0]); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11164 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 11165 | obj->tiling_mode); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11166 | |
| 11167 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 11168 | * untested on non-native modes, so ignore it for now. |
| 11169 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 11170 | */ |
| 11171 | pf = 0; |
| 11172 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11173 | intel_ring_emit(ring, pf | pipesrc); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11174 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11175 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 11176 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11177 | } |
| 11178 | |
| 11179 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 11180 | struct drm_crtc *crtc, |
| 11181 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11182 | struct drm_i915_gem_object *obj, |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11183 | struct drm_i915_gem_request *req, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11184 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11185 | { |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11186 | struct intel_engine_cs *ring = req->ring; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11187 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11189 | uint32_t pf, pipesrc; |
| 11190 | int ret; |
| 11191 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 11192 | ret = intel_ring_begin(req, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11193 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11194 | return ret; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11195 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11196 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 11197 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11198 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11199 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11200 | |
Chris Wilson | 99d9acd | 2012-04-17 20:37:00 +0100 | [diff] [blame] | 11201 | /* Contrary to the suggestions in the documentation, |
| 11202 | * "Enable Panel Fitter" does not seem to be required when page |
| 11203 | * flipping with a non-native mode, and worse causes a normal |
| 11204 | * modeset to fail. |
| 11205 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 11206 | */ |
| 11207 | pf = 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11208 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 11209 | intel_ring_emit(ring, pf | pipesrc); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11210 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11211 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 11212 | return 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11213 | } |
| 11214 | |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11215 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 11216 | struct drm_crtc *crtc, |
| 11217 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11218 | struct drm_i915_gem_object *obj, |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11219 | struct drm_i915_gem_request *req, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11220 | uint32_t flags) |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11221 | { |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11222 | struct intel_engine_cs *ring = req->ring; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 11224 | uint32_t plane_bit = 0; |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11225 | int len, ret; |
| 11226 | |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 11227 | switch (intel_crtc->plane) { |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 11228 | case PLANE_A: |
| 11229 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
| 11230 | break; |
| 11231 | case PLANE_B: |
| 11232 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
| 11233 | break; |
| 11234 | case PLANE_C: |
| 11235 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
| 11236 | break; |
| 11237 | default: |
| 11238 | WARN_ONCE(1, "unknown plane in flip command\n"); |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11239 | return -ENODEV; |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 11240 | } |
| 11241 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11242 | len = 4; |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 11243 | if (ring->id == RCS) { |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11244 | len += 6; |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 11245 | /* |
| 11246 | * On Gen 8, SRM is now taking an extra dword to accommodate |
| 11247 | * 48bits addresses, and we need a NOOP for the batch size to |
| 11248 | * stay even. |
| 11249 | */ |
| 11250 | if (IS_GEN8(dev)) |
| 11251 | len += 2; |
| 11252 | } |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11253 | |
Ville Syrjälä | f66fab8 | 2014-02-11 19:52:06 +0200 | [diff] [blame] | 11254 | /* |
| 11255 | * BSpec MI_DISPLAY_FLIP for IVB: |
| 11256 | * "The full packet must be contained within the same cache line." |
| 11257 | * |
| 11258 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
| 11259 | * cacheline, if we ever start emitting more commands before |
| 11260 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
| 11261 | * then do the cacheline alignment, and finally emit the |
| 11262 | * MI_DISPLAY_FLIP. |
| 11263 | */ |
John Harrison | bba09b1 | 2015-05-29 17:44:06 +0100 | [diff] [blame] | 11264 | ret = intel_ring_cacheline_align(req); |
Ville Syrjälä | f66fab8 | 2014-02-11 19:52:06 +0200 | [diff] [blame] | 11265 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11266 | return ret; |
Ville Syrjälä | f66fab8 | 2014-02-11 19:52:06 +0200 | [diff] [blame] | 11267 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 11268 | ret = intel_ring_begin(req, len); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11269 | if (ret) |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11270 | return ret; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11271 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11272 | /* Unmask the flip-done completion message. Note that the bspec says that |
| 11273 | * we should do this for both the BCS and RCS, and that we must not unmask |
| 11274 | * more than one flip event at any time (or ensure that one flip message |
| 11275 | * can be sent by waiting for flip-done prior to queueing new flips). |
| 11276 | * Experimentation says that BCS works despite DERRMR masking all |
| 11277 | * flip-done completion events and that unmasking all planes at once |
| 11278 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
| 11279 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
| 11280 | */ |
| 11281 | if (ring->id == RCS) { |
| 11282 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 11283 | intel_ring_emit_reg(ring, DERRMR); |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11284 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
| 11285 | DERRMR_PIPEB_PRI_FLIP_DONE | |
| 11286 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 11287 | if (IS_GEN8(dev)) |
Arun Siluvery | f1afe24 | 2015-08-04 16:22:20 +0100 | [diff] [blame] | 11288 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 11289 | MI_SRM_LRM_GLOBAL_GTT); |
| 11290 | else |
Arun Siluvery | f1afe24 | 2015-08-04 16:22:20 +0100 | [diff] [blame] | 11291 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 11292 | MI_SRM_LRM_GLOBAL_GTT); |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 11293 | intel_ring_emit_reg(ring, DERRMR); |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11294 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
Damien Lespiau | f476828 | 2014-04-07 20:24:34 +0100 | [diff] [blame] | 11295 | if (IS_GEN8(dev)) { |
| 11296 | intel_ring_emit(ring, 0); |
| 11297 | intel_ring_emit(ring, MI_NOOP); |
| 11298 | } |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 11299 | } |
| 11300 | |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 11301 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 11302 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11303 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11304 | intel_ring_emit(ring, (MI_NOOP)); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 11305 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11306 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 11307 | return 0; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11308 | } |
| 11309 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11310 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
| 11311 | struct drm_i915_gem_object *obj) |
| 11312 | { |
| 11313 | /* |
| 11314 | * This is not being used for older platforms, because |
| 11315 | * non-availability of flip done interrupt forces us to use |
| 11316 | * CS flips. Older platforms derive flip done using some clever |
| 11317 | * tricks involving the flip_pending status bits and vblank irqs. |
| 11318 | * So using MMIO flips there would disrupt this mechanism. |
| 11319 | */ |
| 11320 | |
Chris Wilson | 8e09bf8 | 2014-07-08 10:40:30 +0100 | [diff] [blame] | 11321 | if (ring == NULL) |
| 11322 | return true; |
| 11323 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11324 | if (INTEL_INFO(ring->dev)->gen < 5) |
| 11325 | return false; |
| 11326 | |
| 11327 | if (i915.use_mmio_flip < 0) |
| 11328 | return false; |
| 11329 | else if (i915.use_mmio_flip > 0) |
| 11330 | return true; |
Oscar Mateo | 14bf993 | 2014-07-24 17:04:34 +0100 | [diff] [blame] | 11331 | else if (i915.enable_execlists) |
| 11332 | return true; |
Alex Goins | fd8e058 | 2015-11-25 18:43:38 -0800 | [diff] [blame] | 11333 | else if (obj->base.dma_buf && |
| 11334 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, |
| 11335 | false)) |
| 11336 | return true; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11337 | else |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 11338 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11339 | } |
| 11340 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11341 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11342 | unsigned int rotation, |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11343 | struct intel_unpin_work *work) |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11344 | { |
| 11345 | struct drm_device *dev = intel_crtc->base.dev; |
| 11346 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11347 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11348 | const enum pipe pipe = intel_crtc->pipe; |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11349 | u32 ctl, stride, tile_height; |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11350 | |
| 11351 | ctl = I915_READ(PLANE_CTL(pipe, 0)); |
| 11352 | ctl &= ~PLANE_CTL_TILED_MASK; |
Tvrtko Ursulin | 2ebef63 | 2015-04-20 16:22:48 +0100 | [diff] [blame] | 11353 | switch (fb->modifier[0]) { |
| 11354 | case DRM_FORMAT_MOD_NONE: |
| 11355 | break; |
| 11356 | case I915_FORMAT_MOD_X_TILED: |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11357 | ctl |= PLANE_CTL_TILED_X; |
Tvrtko Ursulin | 2ebef63 | 2015-04-20 16:22:48 +0100 | [diff] [blame] | 11358 | break; |
| 11359 | case I915_FORMAT_MOD_Y_TILED: |
| 11360 | ctl |= PLANE_CTL_TILED_Y; |
| 11361 | break; |
| 11362 | case I915_FORMAT_MOD_Yf_TILED: |
| 11363 | ctl |= PLANE_CTL_TILED_YF; |
| 11364 | break; |
| 11365 | default: |
| 11366 | MISSING_CASE(fb->modifier[0]); |
| 11367 | } |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11368 | |
| 11369 | /* |
| 11370 | * The stride is either expressed as a multiple of 64 bytes chunks for |
| 11371 | * linear buffers or in number of tiles for tiled buffers. |
| 11372 | */ |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11373 | if (intel_rotation_90_or_270(rotation)) { |
| 11374 | /* stride = Surface height in tiles */ |
| 11375 | tile_height = intel_tile_height(dev, fb->pixel_format, |
| 11376 | fb->modifier[0], 0); |
| 11377 | stride = DIV_ROUND_UP(fb->height, tile_height); |
| 11378 | } else { |
| 11379 | stride = fb->pitches[0] / |
| 11380 | intel_fb_stride_alignment(dev, fb->modifier[0], |
| 11381 | fb->pixel_format); |
| 11382 | } |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11383 | |
| 11384 | /* |
| 11385 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on |
| 11386 | * PLANE_SURF updates, the update is then guaranteed to be atomic. |
| 11387 | */ |
| 11388 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); |
| 11389 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
| 11390 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11391 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11392 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 11393 | } |
| 11394 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11395 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
| 11396 | struct intel_unpin_work *work) |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11397 | { |
| 11398 | struct drm_device *dev = intel_crtc->base.dev; |
| 11399 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11400 | struct intel_framebuffer *intel_fb = |
| 11401 | to_intel_framebuffer(intel_crtc->base.primary->fb); |
| 11402 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 11403 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11404 | u32 dspcntr; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11405 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11406 | dspcntr = I915_READ(reg); |
| 11407 | |
Damien Lespiau | c5d9747 | 2014-10-25 00:11:11 +0100 | [diff] [blame] | 11408 | if (obj->tiling_mode != I915_TILING_NONE) |
| 11409 | dspcntr |= DISPPLANE_TILED; |
| 11410 | else |
| 11411 | dspcntr &= ~DISPPLANE_TILED; |
| 11412 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11413 | I915_WRITE(reg, dspcntr); |
| 11414 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11415 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11416 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11417 | } |
| 11418 | |
| 11419 | /* |
| 11420 | * XXX: This is the temporary way to update the plane registers until we get |
| 11421 | * around to using the usual plane update functions for MMIO flips |
| 11422 | */ |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11423 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11424 | { |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11425 | struct intel_crtc *crtc = mmio_flip->crtc; |
| 11426 | struct intel_unpin_work *work; |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11427 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11428 | spin_lock_irq(&crtc->base.dev->event_lock); |
| 11429 | work = crtc->unpin_work; |
| 11430 | spin_unlock_irq(&crtc->base.dev->event_lock); |
| 11431 | if (work == NULL) |
| 11432 | return; |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11433 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11434 | intel_mark_page_flip_active(work); |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11435 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11436 | intel_pipe_update_start(crtc); |
| 11437 | |
| 11438 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11439 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11440 | else |
| 11441 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11442 | ilk_do_mmio_flip(crtc, work); |
Damien Lespiau | ff94456 | 2014-11-20 14:58:16 +0000 | [diff] [blame] | 11443 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11444 | intel_pipe_update_end(crtc); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11445 | } |
| 11446 | |
Ander Conselvan de Oliveira | 9362c7c | 2014-10-28 15:10:14 +0200 | [diff] [blame] | 11447 | static void intel_mmio_flip_work_func(struct work_struct *work) |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11448 | { |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11449 | struct intel_mmio_flip *mmio_flip = |
| 11450 | container_of(work, struct intel_mmio_flip, work); |
Alex Goins | fd8e058 | 2015-11-25 18:43:38 -0800 | [diff] [blame] | 11451 | struct intel_framebuffer *intel_fb = |
| 11452 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); |
| 11453 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11454 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11455 | if (mmio_flip->req) { |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 11456 | WARN_ON(__i915_wait_request(mmio_flip->req, |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11457 | mmio_flip->crtc->reset_counter, |
Chris Wilson | bcafc4e | 2015-04-27 13:41:21 +0100 | [diff] [blame] | 11458 | false, NULL, |
| 11459 | &mmio_flip->i915->rps.mmioflips)); |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11460 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
| 11461 | } |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11462 | |
Alex Goins | fd8e058 | 2015-11-25 18:43:38 -0800 | [diff] [blame] | 11463 | /* For framebuffer backed by dmabuf, wait for fence */ |
| 11464 | if (obj->base.dma_buf) |
| 11465 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, |
| 11466 | false, false, |
| 11467 | MAX_SCHEDULE_TIMEOUT) < 0); |
| 11468 | |
Chris Wilson | 6042639 | 2015-10-10 10:44:32 +0100 | [diff] [blame] | 11469 | intel_do_mmio_flip(mmio_flip); |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11470 | kfree(mmio_flip); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11471 | } |
| 11472 | |
| 11473 | static int intel_queue_mmio_flip(struct drm_device *dev, |
| 11474 | struct drm_crtc *crtc, |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11475 | struct drm_i915_gem_object *obj) |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11476 | { |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11477 | struct intel_mmio_flip *mmio_flip; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11478 | |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11479 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); |
| 11480 | if (mmio_flip == NULL) |
| 11481 | return -ENOMEM; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11482 | |
Chris Wilson | bcafc4e | 2015-04-27 13:41:21 +0100 | [diff] [blame] | 11483 | mmio_flip->i915 = to_i915(dev); |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 11484 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11485 | mmio_flip->crtc = to_intel_crtc(crtc); |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11486 | mmio_flip->rotation = crtc->primary->state->rotation; |
Chris Wilson | b2cfe0a | 2015-04-27 13:41:16 +0100 | [diff] [blame] | 11487 | |
| 11488 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
| 11489 | schedule_work(&mmio_flip->work); |
Ander Conselvan de Oliveira | 536f5b5 | 2014-11-06 11:03:40 +0200 | [diff] [blame] | 11490 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 11491 | return 0; |
| 11492 | } |
| 11493 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11494 | static int intel_default_queue_flip(struct drm_device *dev, |
| 11495 | struct drm_crtc *crtc, |
| 11496 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11497 | struct drm_i915_gem_object *obj, |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11498 | struct drm_i915_gem_request *req, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11499 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11500 | { |
| 11501 | return -ENODEV; |
| 11502 | } |
| 11503 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11504 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
| 11505 | struct drm_crtc *crtc) |
| 11506 | { |
| 11507 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11509 | struct intel_unpin_work *work = intel_crtc->unpin_work; |
| 11510 | u32 addr; |
| 11511 | |
| 11512 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) |
| 11513 | return true; |
| 11514 | |
Chris Wilson | 908565c | 2015-08-12 13:08:22 +0100 | [diff] [blame] | 11515 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
| 11516 | return false; |
| 11517 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11518 | if (!work->enable_stall_check) |
| 11519 | return false; |
| 11520 | |
| 11521 | if (work->flip_ready_vblank == 0) { |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 11522 | if (work->flip_queued_req && |
| 11523 | !i915_gem_request_completed(work->flip_queued_req, true)) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11524 | return false; |
| 11525 | |
Daniel Vetter | 1e3feef | 2015-02-13 21:03:45 +0100 | [diff] [blame] | 11526 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11527 | } |
| 11528 | |
Daniel Vetter | 1e3feef | 2015-02-13 21:03:45 +0100 | [diff] [blame] | 11529 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11530 | return false; |
| 11531 | |
| 11532 | /* Potential stall - if we see that the flip has happened, |
| 11533 | * assume a missed interrupt. */ |
| 11534 | if (INTEL_INFO(dev)->gen >= 4) |
| 11535 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); |
| 11536 | else |
| 11537 | addr = I915_READ(DSPADDR(intel_crtc->plane)); |
| 11538 | |
| 11539 | /* There is a potential issue here with a false positive after a flip |
| 11540 | * to the same address. We could address this by checking for a |
| 11541 | * non-incrementing frame counter. |
| 11542 | */ |
| 11543 | return addr == work->gtt_offset; |
| 11544 | } |
| 11545 | |
| 11546 | void intel_check_page_flip(struct drm_device *dev, int pipe) |
| 11547 | { |
| 11548 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11549 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 11550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 11551 | struct intel_unpin_work *work; |
Daniel Vetter | f326038 | 2014-09-15 14:55:23 +0200 | [diff] [blame] | 11552 | |
Dave Gordon | 6c51d46 | 2015-03-06 15:34:26 +0000 | [diff] [blame] | 11553 | WARN_ON(!in_interrupt()); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11554 | |
| 11555 | if (crtc == NULL) |
| 11556 | return; |
| 11557 | |
Daniel Vetter | f326038 | 2014-09-15 14:55:23 +0200 | [diff] [blame] | 11558 | spin_lock(&dev->event_lock); |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 11559 | work = intel_crtc->unpin_work; |
| 11560 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11561 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 11562 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11563 | page_flip_completed(intel_crtc); |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 11564 | work = NULL; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11565 | } |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 11566 | if (work != NULL && |
| 11567 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) |
| 11568 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); |
Daniel Vetter | f326038 | 2014-09-15 14:55:23 +0200 | [diff] [blame] | 11569 | spin_unlock(&dev->event_lock); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11570 | } |
| 11571 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11572 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 11573 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 11574 | struct drm_pending_vblank_event *event, |
| 11575 | uint32_t page_flip_flags) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11576 | { |
| 11577 | struct drm_device *dev = crtc->dev; |
| 11578 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11579 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 11580 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Gustavo Padovan | 455a680 | 2014-12-01 15:40:11 -0800 | [diff] [blame] | 11582 | struct drm_plane *primary = crtc->primary; |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11583 | enum pipe pipe = intel_crtc->pipe; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11584 | struct intel_unpin_work *work; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 11585 | struct intel_engine_cs *ring; |
Chris Wilson | cf5d8a4 | 2015-04-07 16:20:26 +0100 | [diff] [blame] | 11586 | bool mmio_flip; |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 11587 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 11588 | int ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11589 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 11590 | /* |
| 11591 | * drm_mode_page_flip_ioctl() should already catch this, but double |
| 11592 | * check to be safe. In the future we may enable pageflipping from |
| 11593 | * a disabled primary plane. |
| 11594 | */ |
| 11595 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) |
| 11596 | return -EBUSY; |
| 11597 | |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 11598 | /* Can't change pixel format via MI display flips. */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11599 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 11600 | return -EINVAL; |
| 11601 | |
| 11602 | /* |
| 11603 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
| 11604 | * Note that pitch changes could also affect these register. |
| 11605 | */ |
| 11606 | if (INTEL_INFO(dev)->gen > 3 && |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11607 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
| 11608 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 11609 | return -EINVAL; |
| 11610 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 11611 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 11612 | goto out_hang; |
| 11613 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 11614 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11615 | if (work == NULL) |
| 11616 | return -ENOMEM; |
| 11617 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11618 | work->event = event; |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 11619 | work->crtc = crtc; |
Tvrtko Ursulin | ab8d667 | 2015-02-02 15:44:15 +0000 | [diff] [blame] | 11620 | work->old_fb = old_fb; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11621 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 11622 | |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 11623 | ret = drm_crtc_vblank_get(crtc); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 11624 | if (ret) |
| 11625 | goto free_work; |
| 11626 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11627 | /* We borrow the event spin lock for protecting unpin_work */ |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11628 | spin_lock_irq(&dev->event_lock); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11629 | if (intel_crtc->unpin_work) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11630 | /* Before declaring the flip queue wedged, check if |
| 11631 | * the hardware completed the operation behind our backs. |
| 11632 | */ |
| 11633 | if (__intel_pageflip_stall_check(dev, crtc)) { |
| 11634 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); |
| 11635 | page_flip_completed(intel_crtc); |
| 11636 | } else { |
| 11637 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11638 | spin_unlock_irq(&dev->event_lock); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 11639 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11640 | drm_crtc_vblank_put(crtc); |
| 11641 | kfree(work); |
| 11642 | return -EBUSY; |
| 11643 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11644 | } |
| 11645 | intel_crtc->unpin_work = work; |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11646 | spin_unlock_irq(&dev->event_lock); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11647 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 11648 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
| 11649 | flush_workqueue(dev_priv->wq); |
| 11650 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 11651 | /* Reference the objects for the scheduled work. */ |
Tvrtko Ursulin | ab8d667 | 2015-02-02 15:44:15 +0000 | [diff] [blame] | 11652 | drm_framebuffer_reference(work->old_fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 11653 | drm_gem_object_reference(&obj->base); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11654 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11655 | crtc->primary->fb = fb; |
Matt Roper | afd65eb | 2015-02-03 13:10:04 -0800 | [diff] [blame] | 11656 | update_state_fb(crtc->primary); |
Matt Roper | 1ed1f96 | 2015-01-30 16:22:36 -0800 | [diff] [blame] | 11657 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 11658 | work->pending_flip_obj = obj; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 11659 | |
Chris Wilson | 89ed88b | 2015-02-16 14:31:49 +0000 | [diff] [blame] | 11660 | ret = i915_mutex_lock_interruptible(dev); |
| 11661 | if (ret) |
| 11662 | goto cleanup; |
| 11663 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 11664 | atomic_inc(&intel_crtc->unpin_work_count); |
Ville Syrjälä | 10d8373 | 2013-01-29 18:13:34 +0200 | [diff] [blame] | 11665 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 11666 | |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11667 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
Ville Syrjälä | fd8f507c | 2015-09-18 20:03:42 +0300 | [diff] [blame] | 11668 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 11669 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 11670 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11671 | ring = &dev_priv->ring[BCS]; |
Tvrtko Ursulin | ab8d667 | 2015-02-02 15:44:15 +0000 | [diff] [blame] | 11672 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
Chris Wilson | 8e09bf8 | 2014-07-08 10:40:30 +0100 | [diff] [blame] | 11673 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
| 11674 | ring = NULL; |
Chris Wilson | 48bf5b2 | 2014-12-27 09:48:28 +0000 | [diff] [blame] | 11675 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
Chris Wilson | 2a92d5b | 2014-07-08 10:40:29 +0100 | [diff] [blame] | 11676 | ring = &dev_priv->ring[BCS]; |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11677 | } else if (INTEL_INFO(dev)->gen >= 7) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 11678 | ring = i915_gem_request_get_ring(obj->last_write_req); |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11679 | if (ring == NULL || ring->id != RCS) |
| 11680 | ring = &dev_priv->ring[BCS]; |
| 11681 | } else { |
| 11682 | ring = &dev_priv->ring[RCS]; |
| 11683 | } |
| 11684 | |
Chris Wilson | cf5d8a4 | 2015-04-07 16:20:26 +0100 | [diff] [blame] | 11685 | mmio_flip = use_mmio_flip(ring, obj); |
| 11686 | |
| 11687 | /* When using CS flips, we want to emit semaphores between rings. |
| 11688 | * However, when using mmio flips we will create a task to do the |
| 11689 | * synchronisation, so all we want here is to pin the framebuffer |
| 11690 | * into the display plane and skip any waits. |
| 11691 | */ |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 11692 | if (!mmio_flip) { |
| 11693 | ret = i915_gem_object_sync(obj, ring, &request); |
| 11694 | if (ret) |
| 11695 | goto cleanup_pending; |
| 11696 | } |
| 11697 | |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 11698 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 11699 | crtc->primary->state); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11700 | if (ret) |
| 11701 | goto cleanup_pending; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11702 | |
Tvrtko Ursulin | dedf278 | 2015-09-21 10:45:35 +0100 | [diff] [blame] | 11703 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
| 11704 | obj, 0); |
| 11705 | work->gtt_offset += intel_crtc->dspaddr_offset; |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11706 | |
Chris Wilson | cf5d8a4 | 2015-04-07 16:20:26 +0100 | [diff] [blame] | 11707 | if (mmio_flip) { |
Tvrtko Ursulin | 86efe24 | 2015-10-20 16:20:21 +0100 | [diff] [blame] | 11708 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11709 | if (ret) |
| 11710 | goto cleanup_unpin; |
| 11711 | |
John Harrison | f06cc1b | 2014-11-24 18:49:37 +0000 | [diff] [blame] | 11712 | i915_gem_request_assign(&work->flip_queued_req, |
| 11713 | obj->last_write_req); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11714 | } else { |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11715 | if (!request) { |
| 11716 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); |
| 11717 | if (ret) |
| 11718 | goto cleanup_unpin; |
| 11719 | } |
| 11720 | |
| 11721 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11722 | page_flip_flags); |
| 11723 | if (ret) |
| 11724 | goto cleanup_unpin; |
| 11725 | |
John Harrison | 6258fbe | 2015-05-29 17:43:48 +0100 | [diff] [blame] | 11726 | i915_gem_request_assign(&work->flip_queued_req, request); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11727 | } |
| 11728 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 11729 | if (request) |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 11730 | i915_add_request_no_flush(request); |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 11731 | |
Daniel Vetter | 1e3feef | 2015-02-13 21:03:45 +0100 | [diff] [blame] | 11732 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 11733 | work->enable_stall_check = true; |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11734 | |
Tvrtko Ursulin | ab8d667 | 2015-02-02 15:44:15 +0000 | [diff] [blame] | 11735 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 11736 | to_intel_plane(primary)->frontbuffer_bit); |
Paulo Zanoni | c80ac85 | 2015-07-02 19:25:13 -0300 | [diff] [blame] | 11737 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11738 | |
Paulo Zanoni | d029bca | 2015-10-15 10:44:46 -0300 | [diff] [blame] | 11739 | intel_fbc_deactivate(intel_crtc); |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 11740 | intel_frontbuffer_flip_prepare(dev, |
| 11741 | to_intel_plane(primary)->frontbuffer_bit); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11742 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 11743 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 11744 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11745 | return 0; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 11746 | |
Ville Syrjälä | 4fa62c8 | 2014-04-15 21:41:38 +0300 | [diff] [blame] | 11747 | cleanup_unpin: |
Tvrtko Ursulin | 82bc3b2 | 2015-03-23 11:10:34 +0000 | [diff] [blame] | 11748 | intel_unpin_fb_obj(fb, crtc->primary->state); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11749 | cleanup_pending: |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 11750 | if (request) |
| 11751 | i915_gem_request_cancel(request); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 11752 | atomic_dec(&intel_crtc->unpin_work_count); |
Chris Wilson | 89ed88b | 2015-02-16 14:31:49 +0000 | [diff] [blame] | 11753 | mutex_unlock(&dev->struct_mutex); |
| 11754 | cleanup: |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 11755 | crtc->primary->fb = old_fb; |
Matt Roper | afd65eb | 2015-02-03 13:10:04 -0800 | [diff] [blame] | 11756 | update_state_fb(crtc->primary); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 11757 | |
Chris Wilson | 89ed88b | 2015-02-16 14:31:49 +0000 | [diff] [blame] | 11758 | drm_gem_object_unreference_unlocked(&obj->base); |
| 11759 | drm_framebuffer_unreference(work->old_fb); |
| 11760 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11761 | spin_lock_irq(&dev->event_lock); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 11762 | intel_crtc->unpin_work = NULL; |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11763 | spin_unlock_irq(&dev->event_lock); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 11764 | |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 11765 | drm_crtc_vblank_put(crtc); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 11766 | free_work: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 11767 | kfree(work); |
| 11768 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 11769 | if (ret == -EIO) { |
Maarten Lankhorst | 02e0efb | 2015-06-12 11:15:40 +0200 | [diff] [blame] | 11770 | struct drm_atomic_state *state; |
| 11771 | struct drm_plane_state *plane_state; |
| 11772 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 11773 | out_hang: |
Maarten Lankhorst | 02e0efb | 2015-06-12 11:15:40 +0200 | [diff] [blame] | 11774 | state = drm_atomic_state_alloc(dev); |
| 11775 | if (!state) |
| 11776 | return -ENOMEM; |
| 11777 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
| 11778 | |
| 11779 | retry: |
| 11780 | plane_state = drm_atomic_get_plane_state(state, primary); |
| 11781 | ret = PTR_ERR_OR_ZERO(plane_state); |
| 11782 | if (!ret) { |
| 11783 | drm_atomic_set_fb_for_plane(plane_state, fb); |
| 11784 | |
| 11785 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); |
| 11786 | if (!ret) |
| 11787 | ret = drm_atomic_commit(state); |
| 11788 | } |
| 11789 | |
| 11790 | if (ret == -EDEADLK) { |
| 11791 | drm_modeset_backoff(state->acquire_ctx); |
| 11792 | drm_atomic_state_clear(state); |
| 11793 | goto retry; |
| 11794 | } |
| 11795 | |
| 11796 | if (ret) |
| 11797 | drm_atomic_state_free(state); |
| 11798 | |
Chris Wilson | f0d3dad | 2014-09-07 16:51:12 +0100 | [diff] [blame] | 11799 | if (ret == 0 && event) { |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11800 | spin_lock_irq(&dev->event_lock); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 11801 | drm_send_vblank_event(dev, pipe, event); |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 11802 | spin_unlock_irq(&dev->event_lock); |
Chris Wilson | f0d3dad | 2014-09-07 16:51:12 +0100 | [diff] [blame] | 11803 | } |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 11804 | } |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 11805 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 11806 | } |
| 11807 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11808 | |
| 11809 | /** |
| 11810 | * intel_wm_need_update - Check whether watermarks need updating |
| 11811 | * @plane: drm plane |
| 11812 | * @state: new plane state |
| 11813 | * |
| 11814 | * Check current plane state versus the new one to determine whether |
| 11815 | * watermarks need to be recalculated. |
| 11816 | * |
| 11817 | * Returns true or false. |
| 11818 | */ |
| 11819 | static bool intel_wm_need_update(struct drm_plane *plane, |
| 11820 | struct drm_plane_state *state) |
| 11821 | { |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 11822 | struct intel_plane_state *new = to_intel_plane_state(state); |
| 11823 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); |
| 11824 | |
| 11825 | /* Update watermarks on tiling or size changes. */ |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 11826 | if (new->visible != cur->visible) |
| 11827 | return true; |
| 11828 | |
| 11829 | if (!cur->base.fb || !new->base.fb) |
| 11830 | return false; |
| 11831 | |
| 11832 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || |
| 11833 | cur->base.rotation != new->base.rotation || |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 11834 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
| 11835 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || |
| 11836 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || |
| 11837 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11838 | return true; |
| 11839 | |
| 11840 | return false; |
| 11841 | } |
| 11842 | |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 11843 | static bool needs_scaling(struct intel_plane_state *state) |
| 11844 | { |
| 11845 | int src_w = drm_rect_width(&state->src) >> 16; |
| 11846 | int src_h = drm_rect_height(&state->src) >> 16; |
| 11847 | int dst_w = drm_rect_width(&state->dst); |
| 11848 | int dst_h = drm_rect_height(&state->dst); |
| 11849 | |
| 11850 | return (src_w != dst_w || src_h != dst_h); |
| 11851 | } |
| 11852 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11853 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
| 11854 | struct drm_plane_state *plane_state) |
| 11855 | { |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 11856 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11857 | struct drm_crtc *crtc = crtc_state->crtc; |
| 11858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11859 | struct drm_plane *plane = plane_state->plane; |
| 11860 | struct drm_device *dev = crtc->dev; |
| 11861 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11862 | struct intel_plane_state *old_plane_state = |
| 11863 | to_intel_plane_state(plane->state); |
| 11864 | int idx = intel_crtc->base.base.id, ret; |
| 11865 | int i = drm_plane_index(plane); |
| 11866 | bool mode_changed = needs_modeset(crtc_state); |
| 11867 | bool was_crtc_enabled = crtc->state->active; |
| 11868 | bool is_crtc_enabled = crtc_state->active; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11869 | bool turn_off, turn_on, visible, was_visible; |
| 11870 | struct drm_framebuffer *fb = plane_state->fb; |
| 11871 | |
| 11872 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && |
| 11873 | plane->type != DRM_PLANE_TYPE_CURSOR) { |
| 11874 | ret = skl_update_scaler_plane( |
| 11875 | to_intel_crtc_state(crtc_state), |
| 11876 | to_intel_plane_state(plane_state)); |
| 11877 | if (ret) |
| 11878 | return ret; |
| 11879 | } |
| 11880 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11881 | was_visible = old_plane_state->visible; |
| 11882 | visible = to_intel_plane_state(plane_state)->visible; |
| 11883 | |
| 11884 | if (!was_crtc_enabled && WARN_ON(was_visible)) |
| 11885 | was_visible = false; |
| 11886 | |
Maarten Lankhorst | 35c08f4 | 2015-12-03 14:31:07 +0100 | [diff] [blame] | 11887 | /* |
| 11888 | * Visibility is calculated as if the crtc was on, but |
| 11889 | * after scaler setup everything depends on it being off |
| 11890 | * when the crtc isn't active. |
| 11891 | */ |
| 11892 | if (!is_crtc_enabled) |
| 11893 | to_intel_plane_state(plane_state)->visible = visible = false; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11894 | |
| 11895 | if (!was_visible && !visible) |
| 11896 | return 0; |
| 11897 | |
| 11898 | turn_off = was_visible && (!visible || mode_changed); |
| 11899 | turn_on = visible && (!was_visible || mode_changed); |
| 11900 | |
| 11901 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, |
| 11902 | plane->base.id, fb ? fb->base.id : -1); |
| 11903 | |
| 11904 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", |
| 11905 | plane->base.id, was_visible, visible, |
| 11906 | turn_off, turn_on, mode_changed); |
| 11907 | |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 11908 | if (turn_on || turn_off) { |
| 11909 | pipe_config->wm_changed = true; |
| 11910 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 11911 | /* must disable cxsr around plane enable/disable */ |
| 11912 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
| 11913 | if (is_crtc_enabled) |
| 11914 | intel_crtc->atomic.wait_vblank = true; |
Maarten Lankhorst | ab1d3a0 | 2015-11-19 16:07:14 +0100 | [diff] [blame] | 11915 | pipe_config->disable_cxsr = true; |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 11916 | } |
| 11917 | } else if (intel_wm_need_update(plane, plane_state)) { |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 11918 | pipe_config->wm_changed = true; |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 11919 | } |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11920 | |
Rodrigo Vivi | 8be6ca8 | 2015-08-24 16:38:23 -0700 | [diff] [blame] | 11921 | if (visible || was_visible) |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 11922 | intel_crtc->atomic.fb_bits |= |
| 11923 | to_intel_plane(plane)->frontbuffer_bit; |
| 11924 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11925 | switch (plane->type) { |
| 11926 | case DRM_PLANE_TYPE_PRIMARY: |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11927 | intel_crtc->atomic.pre_disable_primary = turn_off; |
| 11928 | intel_crtc->atomic.post_enable_primary = turn_on; |
| 11929 | |
Rodrigo Vivi | 066cf55 | 2015-06-26 13:55:54 -0700 | [diff] [blame] | 11930 | if (turn_off) { |
| 11931 | /* |
| 11932 | * FIXME: Actually if we will still have any other |
| 11933 | * plane enabled on the pipe we could let IPS enabled |
| 11934 | * still, but for now lets consider that when we make |
| 11935 | * primary invisible by setting DSPCNTR to 0 on |
| 11936 | * update_primary_plane function IPS needs to be |
| 11937 | * disable. |
| 11938 | */ |
| 11939 | intel_crtc->atomic.disable_ips = true; |
| 11940 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11941 | intel_crtc->atomic.disable_fbc = true; |
Rodrigo Vivi | 066cf55 | 2015-06-26 13:55:54 -0700 | [diff] [blame] | 11942 | } |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11943 | |
| 11944 | /* |
| 11945 | * FBC does not work on some platforms for rotated |
| 11946 | * planes, so disable it when rotation is not 0 and |
| 11947 | * update it when rotation is set back to 0. |
| 11948 | * |
| 11949 | * FIXME: This is redundant with the fbc update done in |
| 11950 | * the primary plane enable function except that that |
| 11951 | * one is done too late. We eventually need to unify |
| 11952 | * this. |
| 11953 | */ |
| 11954 | |
| 11955 | if (visible && |
| 11956 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
| 11957 | dev_priv->fbc.crtc == intel_crtc && |
| 11958 | plane_state->rotation != BIT(DRM_ROTATE_0)) |
| 11959 | intel_crtc->atomic.disable_fbc = true; |
| 11960 | |
| 11961 | /* |
| 11962 | * BDW signals flip done immediately if the plane |
| 11963 | * is disabled, even if the plane enable is already |
| 11964 | * armed to occur at the next vblank :( |
| 11965 | */ |
| 11966 | if (turn_on && IS_BROADWELL(dev)) |
| 11967 | intel_crtc->atomic.wait_vblank = true; |
| 11968 | |
| 11969 | intel_crtc->atomic.update_fbc |= visible || mode_changed; |
| 11970 | break; |
| 11971 | case DRM_PLANE_TYPE_CURSOR: |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11972 | break; |
| 11973 | case DRM_PLANE_TYPE_OVERLAY: |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 11974 | /* |
| 11975 | * WaCxSRDisabledForSpriteScaling:ivb |
| 11976 | * |
| 11977 | * cstate->update_wm was already set above, so this flag will |
| 11978 | * take effect when we commit and program watermarks. |
| 11979 | */ |
| 11980 | if (IS_IVYBRIDGE(dev) && |
| 11981 | needs_scaling(to_intel_plane_state(plane_state)) && |
| 11982 | !needs_scaling(old_plane_state)) { |
| 11983 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; |
| 11984 | } else if (turn_off && !mode_changed) { |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11985 | intel_crtc->atomic.wait_vblank = true; |
| 11986 | intel_crtc->atomic.update_sprite_watermarks |= |
| 11987 | 1 << i; |
| 11988 | } |
Matt Roper | d21fbe8 | 2015-09-24 15:53:12 -0700 | [diff] [blame] | 11989 | |
| 11990 | break; |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 11991 | } |
| 11992 | return 0; |
| 11993 | } |
| 11994 | |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 11995 | static bool encoders_cloneable(const struct intel_encoder *a, |
| 11996 | const struct intel_encoder *b) |
| 11997 | { |
| 11998 | /* masks could be asymmetric, so check both ways */ |
| 11999 | return a == b || (a->cloneable & (1 << b->type) && |
| 12000 | b->cloneable & (1 << a->type)); |
| 12001 | } |
| 12002 | |
| 12003 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
| 12004 | struct intel_crtc *crtc, |
| 12005 | struct intel_encoder *encoder) |
| 12006 | { |
| 12007 | struct intel_encoder *source_encoder; |
| 12008 | struct drm_connector *connector; |
| 12009 | struct drm_connector_state *connector_state; |
| 12010 | int i; |
| 12011 | |
| 12012 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12013 | if (connector_state->crtc != &crtc->base) |
| 12014 | continue; |
| 12015 | |
| 12016 | source_encoder = |
| 12017 | to_intel_encoder(connector_state->best_encoder); |
| 12018 | if (!encoders_cloneable(encoder, source_encoder)) |
| 12019 | return false; |
| 12020 | } |
| 12021 | |
| 12022 | return true; |
| 12023 | } |
| 12024 | |
| 12025 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
| 12026 | struct intel_crtc *crtc) |
| 12027 | { |
| 12028 | struct intel_encoder *encoder; |
| 12029 | struct drm_connector *connector; |
| 12030 | struct drm_connector_state *connector_state; |
| 12031 | int i; |
| 12032 | |
| 12033 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12034 | if (connector_state->crtc != &crtc->base) |
| 12035 | continue; |
| 12036 | |
| 12037 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12038 | if (!check_single_encoder_cloning(state, crtc, encoder)) |
| 12039 | return false; |
| 12040 | } |
| 12041 | |
| 12042 | return true; |
| 12043 | } |
| 12044 | |
| 12045 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
| 12046 | struct drm_crtc_state *crtc_state) |
| 12047 | { |
Maarten Lankhorst | cf5a15b | 2015-06-15 12:33:41 +0200 | [diff] [blame] | 12048 | struct drm_device *dev = crtc->dev; |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 12049 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | cf5a15b | 2015-06-15 12:33:41 +0200 | [diff] [blame] | 12051 | struct intel_crtc_state *pipe_config = |
| 12052 | to_intel_crtc_state(crtc_state); |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12053 | struct drm_atomic_state *state = crtc_state->state; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12054 | int ret; |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12055 | bool mode_changed = needs_modeset(crtc_state); |
| 12056 | |
| 12057 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { |
| 12058 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
| 12059 | return -EINVAL; |
| 12060 | } |
| 12061 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 12062 | if (mode_changed && !crtc_state->active) |
Maarten Lankhorst | 92826fc | 2015-12-03 13:49:13 +0100 | [diff] [blame] | 12063 | pipe_config->wm_changed = true; |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 12064 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 12065 | if (mode_changed && crtc_state->enable && |
| 12066 | dev_priv->display.crtc_compute_clock && |
| 12067 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { |
| 12068 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
| 12069 | pipe_config); |
| 12070 | if (ret) |
| 12071 | return ret; |
| 12072 | } |
| 12073 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 12074 | ret = 0; |
Matt Roper | 86c8bbb | 2015-09-24 15:53:16 -0700 | [diff] [blame] | 12075 | if (dev_priv->display.compute_pipe_wm) { |
| 12076 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); |
| 12077 | if (ret) |
| 12078 | return ret; |
| 12079 | } |
| 12080 | |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 12081 | if (INTEL_INFO(dev)->gen >= 9) { |
| 12082 | if (mode_changed) |
| 12083 | ret = skl_update_scaler_crtc(pipe_config); |
| 12084 | |
| 12085 | if (!ret) |
| 12086 | ret = intel_atomic_setup_scalers(dev, intel_crtc, |
| 12087 | pipe_config); |
| 12088 | } |
| 12089 | |
| 12090 | return ret; |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12091 | } |
| 12092 | |
Jani Nikula | 65b38e0 | 2015-04-13 11:26:56 +0300 | [diff] [blame] | 12093 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 12094 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
| 12095 | .load_lut = intel_crtc_load_lut, |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 12096 | .atomic_begin = intel_begin_crtc_commit, |
| 12097 | .atomic_flush = intel_finish_crtc_commit, |
Maarten Lankhorst | 6d3a1ce | 2015-06-15 12:33:40 +0200 | [diff] [blame] | 12098 | .atomic_check = intel_crtc_atomic_check, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 12099 | }; |
| 12100 | |
Ander Conselvan de Oliveira | d29b2f9 | 2015-03-20 16:18:05 +0200 | [diff] [blame] | 12101 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
| 12102 | { |
| 12103 | struct intel_connector *connector; |
| 12104 | |
| 12105 | for_each_intel_connector(dev, connector) { |
| 12106 | if (connector->base.encoder) { |
| 12107 | connector->base.state->best_encoder = |
| 12108 | connector->base.encoder; |
| 12109 | connector->base.state->crtc = |
| 12110 | connector->base.encoder->crtc; |
| 12111 | } else { |
| 12112 | connector->base.state->best_encoder = NULL; |
| 12113 | connector->base.state->crtc = NULL; |
| 12114 | } |
| 12115 | } |
| 12116 | } |
| 12117 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12118 | static void |
Robin Schroer | eba905b | 2014-05-18 02:24:50 +0200 | [diff] [blame] | 12119 | connected_sink_compute_bpp(struct intel_connector *connector, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12120 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12121 | { |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12122 | int bpp = pipe_config->pipe_bpp; |
| 12123 | |
| 12124 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
| 12125 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 12126 | connector->base.name); |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12127 | |
| 12128 | /* Don't use an invalid EDID bpc value */ |
| 12129 | if (connector->base.display_info.bpc && |
| 12130 | connector->base.display_info.bpc * 3 < bpp) { |
| 12131 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
| 12132 | bpp, connector->base.display_info.bpc*3); |
| 12133 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
| 12134 | } |
| 12135 | |
| 12136 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
| 12137 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
| 12138 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
| 12139 | bpp); |
| 12140 | pipe_config->pipe_bpp = 24; |
| 12141 | } |
| 12142 | } |
| 12143 | |
| 12144 | static int |
| 12145 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12146 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 12147 | { |
| 12148 | struct drm_device *dev = crtc->base.dev; |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12149 | struct drm_atomic_state *state; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12150 | struct drm_connector *connector; |
| 12151 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12152 | int bpp, i; |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12153 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 12154 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12155 | bpp = 10*3; |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12156 | else if (INTEL_INFO(dev)->gen >= 5) |
| 12157 | bpp = 12*3; |
| 12158 | else |
| 12159 | bpp = 8*3; |
| 12160 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12161 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12162 | pipe_config->pipe_bpp = bpp; |
| 12163 | |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12164 | state = pipe_config->base.state; |
| 12165 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12166 | /* Clamp display bpp to EDID value */ |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12167 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12168 | if (connector_state->crtc != &crtc->base) |
Ander Conselvan de Oliveira | 1486017 | 2015-03-20 16:18:09 +0200 | [diff] [blame] | 12169 | continue; |
| 12170 | |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12171 | connected_sink_compute_bpp(to_intel_connector(connector), |
| 12172 | pipe_config); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12173 | } |
| 12174 | |
| 12175 | return bpp; |
| 12176 | } |
| 12177 | |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 12178 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
| 12179 | { |
| 12180 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
| 12181 | "type: 0x%x flags: 0x%x\n", |
Damien Lespiau | 1342830 | 2013-09-25 16:45:36 +0100 | [diff] [blame] | 12182 | mode->crtc_clock, |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 12183 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
| 12184 | mode->crtc_hsync_end, mode->crtc_htotal, |
| 12185 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
| 12186 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
| 12187 | } |
| 12188 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12189 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12190 | struct intel_crtc_state *pipe_config, |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12191 | const char *context) |
| 12192 | { |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12193 | struct drm_device *dev = crtc->base.dev; |
| 12194 | struct drm_plane *plane; |
| 12195 | struct intel_plane *intel_plane; |
| 12196 | struct intel_plane_state *state; |
| 12197 | struct drm_framebuffer *fb; |
| 12198 | |
| 12199 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, |
| 12200 | context, pipe_config, pipe_name(crtc->pipe)); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12201 | |
| 12202 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
| 12203 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
| 12204 | pipe_config->pipe_bpp, pipe_config->dither); |
| 12205 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 12206 | pipe_config->has_pch_encoder, |
| 12207 | pipe_config->fdi_lanes, |
| 12208 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
| 12209 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
| 12210 | pipe_config->fdi_m_n.tu); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12211 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 12212 | pipe_config->has_dp_encoder, |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12213 | pipe_config->lane_count, |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 12214 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
| 12215 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
| 12216 | pipe_config->dp_m_n.tu); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12217 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12218 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12219 | pipe_config->has_dp_encoder, |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12220 | pipe_config->lane_count, |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12221 | pipe_config->dp_m2_n2.gmch_m, |
| 12222 | pipe_config->dp_m2_n2.gmch_n, |
| 12223 | pipe_config->dp_m2_n2.link_m, |
| 12224 | pipe_config->dp_m2_n2.link_n, |
| 12225 | pipe_config->dp_m2_n2.tu); |
| 12226 | |
Daniel Vetter | 55072d1 | 2014-11-20 16:10:28 +0100 | [diff] [blame] | 12227 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
| 12228 | pipe_config->has_audio, |
| 12229 | pipe_config->has_infoframe); |
| 12230 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12231 | DRM_DEBUG_KMS("requested mode:\n"); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12232 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12233 | DRM_DEBUG_KMS("adjusted mode:\n"); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12234 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
| 12235 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); |
Ville Syrjälä | d71b8d4 | 2013-09-06 23:29:08 +0300 | [diff] [blame] | 12236 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 12237 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
| 12238 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
Tvrtko Ursulin | 0ec463d | 2015-05-13 16:51:08 +0100 | [diff] [blame] | 12239 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
| 12240 | crtc->num_scalers, |
| 12241 | pipe_config->scaler_state.scaler_users, |
| 12242 | pipe_config->scaler_state.scaler_id); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12243 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
| 12244 | pipe_config->gmch_pfit.control, |
| 12245 | pipe_config->gmch_pfit.pgm_ratios, |
| 12246 | pipe_config->gmch_pfit.lvds_border_bits); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 12247 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12248 | pipe_config->pch_pfit.pos, |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 12249 | pipe_config->pch_pfit.size, |
| 12250 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 12251 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 12252 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12253 | |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12254 | if (IS_BROXTON(dev)) { |
Imre Deak | 05712c1 | 2015-06-18 17:25:54 +0300 | [diff] [blame] | 12255 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12256 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
Imre Deak | c845333 | 2015-06-18 17:25:55 +0300 | [diff] [blame] | 12257 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12258 | pipe_config->ddi_pll_sel, |
| 12259 | pipe_config->dpll_hw_state.ebb0, |
Imre Deak | 05712c1 | 2015-06-18 17:25:54 +0300 | [diff] [blame] | 12260 | pipe_config->dpll_hw_state.ebb4, |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12261 | pipe_config->dpll_hw_state.pll0, |
| 12262 | pipe_config->dpll_hw_state.pll1, |
| 12263 | pipe_config->dpll_hw_state.pll2, |
| 12264 | pipe_config->dpll_hw_state.pll3, |
| 12265 | pipe_config->dpll_hw_state.pll6, |
| 12266 | pipe_config->dpll_hw_state.pll8, |
Imre Deak | 05712c1 | 2015-06-18 17:25:54 +0300 | [diff] [blame] | 12267 | pipe_config->dpll_hw_state.pll9, |
Imre Deak | c845333 | 2015-06-18 17:25:55 +0300 | [diff] [blame] | 12268 | pipe_config->dpll_hw_state.pll10, |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12269 | pipe_config->dpll_hw_state.pcsdw12); |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 12270 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12271 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
| 12272 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
| 12273 | pipe_config->ddi_pll_sel, |
| 12274 | pipe_config->dpll_hw_state.ctrl1, |
| 12275 | pipe_config->dpll_hw_state.cfgcr1, |
| 12276 | pipe_config->dpll_hw_state.cfgcr2); |
| 12277 | } else if (HAS_DDI(dev)) { |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 12278 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12279 | pipe_config->ddi_pll_sel, |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 12280 | pipe_config->dpll_hw_state.wrpll, |
| 12281 | pipe_config->dpll_hw_state.spll); |
Tvrtko Ursulin | 415ff0f | 2015-05-14 13:38:31 +0100 | [diff] [blame] | 12282 | } else { |
| 12283 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " |
| 12284 | "fp0: 0x%x, fp1: 0x%x\n", |
| 12285 | pipe_config->dpll_hw_state.dpll, |
| 12286 | pipe_config->dpll_hw_state.dpll_md, |
| 12287 | pipe_config->dpll_hw_state.fp0, |
| 12288 | pipe_config->dpll_hw_state.fp1); |
| 12289 | } |
| 12290 | |
Chandra Konduru | 6a60cd8 | 2015-04-07 15:28:40 -0700 | [diff] [blame] | 12291 | DRM_DEBUG_KMS("planes on this crtc\n"); |
| 12292 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
| 12293 | intel_plane = to_intel_plane(plane); |
| 12294 | if (intel_plane->pipe != crtc->pipe) |
| 12295 | continue; |
| 12296 | |
| 12297 | state = to_intel_plane_state(plane->state); |
| 12298 | fb = state->base.fb; |
| 12299 | if (!fb) { |
| 12300 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " |
| 12301 | "disabled, scaler_id = %d\n", |
| 12302 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", |
| 12303 | plane->base.id, intel_plane->pipe, |
| 12304 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, |
| 12305 | drm_plane_index(plane), state->scaler_id); |
| 12306 | continue; |
| 12307 | } |
| 12308 | |
| 12309 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", |
| 12310 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", |
| 12311 | plane->base.id, intel_plane->pipe, |
| 12312 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, |
| 12313 | drm_plane_index(plane)); |
| 12314 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", |
| 12315 | fb->base.id, fb->width, fb->height, fb->pixel_format); |
| 12316 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", |
| 12317 | state->scaler_id, |
| 12318 | state->src.x1 >> 16, state->src.y1 >> 16, |
| 12319 | drm_rect_width(&state->src) >> 16, |
| 12320 | drm_rect_height(&state->src) >> 16, |
| 12321 | state->dst.x1, state->dst.y1, |
| 12322 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); |
| 12323 | } |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 12324 | } |
| 12325 | |
Ander Conselvan de Oliveira | 5448a00 | 2015-04-02 14:47:59 +0300 | [diff] [blame] | 12326 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12327 | { |
Ander Conselvan de Oliveira | 5448a00 | 2015-04-02 14:47:59 +0300 | [diff] [blame] | 12328 | struct drm_device *dev = state->dev; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12329 | struct drm_connector *connector; |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12330 | unsigned int used_ports = 0; |
| 12331 | |
| 12332 | /* |
| 12333 | * Walk the connector list instead of the encoder |
| 12334 | * list to detect the problem on ddi platforms |
| 12335 | * where there's just one encoder per digital port. |
| 12336 | */ |
Ville Syrjälä | 0bff485 | 2015-12-10 18:22:31 +0200 | [diff] [blame] | 12337 | drm_for_each_connector(connector, dev) { |
| 12338 | struct drm_connector_state *connector_state; |
| 12339 | struct intel_encoder *encoder; |
| 12340 | |
| 12341 | connector_state = drm_atomic_get_existing_connector_state(state, connector); |
| 12342 | if (!connector_state) |
| 12343 | connector_state = connector->state; |
| 12344 | |
Ander Conselvan de Oliveira | 5448a00 | 2015-04-02 14:47:59 +0300 | [diff] [blame] | 12345 | if (!connector_state->best_encoder) |
| 12346 | continue; |
| 12347 | |
| 12348 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12349 | |
| 12350 | WARN_ON(!connector_state->crtc); |
Ville Syrjälä | 00f0b37 | 2014-12-02 14:10:46 +0200 | [diff] [blame] | 12351 | |
| 12352 | switch (encoder->type) { |
| 12353 | unsigned int port_mask; |
| 12354 | case INTEL_OUTPUT_UNKNOWN: |
| 12355 | if (WARN_ON(!HAS_DDI(dev))) |
| 12356 | break; |
| 12357 | case INTEL_OUTPUT_DISPLAYPORT: |
| 12358 | case INTEL_OUTPUT_HDMI: |
| 12359 | case INTEL_OUTPUT_EDP: |
| 12360 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; |
| 12361 | |
| 12362 | /* the same port mustn't appear more than once */ |
| 12363 | if (used_ports & port_mask) |
| 12364 | return false; |
| 12365 | |
| 12366 | used_ports |= port_mask; |
| 12367 | default: |
| 12368 | break; |
| 12369 | } |
| 12370 | } |
| 12371 | |
| 12372 | return true; |
| 12373 | } |
| 12374 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12375 | static void |
| 12376 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) |
| 12377 | { |
| 12378 | struct drm_crtc_state tmp_state; |
Chandra Konduru | 663a364 | 2015-04-07 15:28:41 -0700 | [diff] [blame] | 12379 | struct intel_crtc_scaler_state scaler_state; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12380 | struct intel_dpll_hw_state dpll_hw_state; |
| 12381 | enum intel_dpll_id shared_dpll; |
Ander Conselvan de Oliveira | 8504c74 | 2015-05-15 11:51:50 +0300 | [diff] [blame] | 12382 | uint32_t ddi_pll_sel; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 12383 | bool force_thru; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12384 | |
Ander Conselvan de Oliveira | 7546a38 | 2015-05-20 09:03:27 +0300 | [diff] [blame] | 12385 | /* FIXME: before the switch to atomic started, a new pipe_config was |
| 12386 | * kzalloc'd. Code that depends on any field being zero should be |
| 12387 | * fixed, so that the crtc_state can be safely duplicated. For now, |
| 12388 | * only fields that are know to not cause problems are preserved. */ |
| 12389 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12390 | tmp_state = crtc_state->base; |
Chandra Konduru | 663a364 | 2015-04-07 15:28:41 -0700 | [diff] [blame] | 12391 | scaler_state = crtc_state->scaler_state; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12392 | shared_dpll = crtc_state->shared_dpll; |
| 12393 | dpll_hw_state = crtc_state->dpll_hw_state; |
Ander Conselvan de Oliveira | 8504c74 | 2015-05-15 11:51:50 +0300 | [diff] [blame] | 12394 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 12395 | force_thru = crtc_state->pch_pfit.force_thru; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12396 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12397 | memset(crtc_state, 0, sizeof *crtc_state); |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12398 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12399 | crtc_state->base = tmp_state; |
Chandra Konduru | 663a364 | 2015-04-07 15:28:41 -0700 | [diff] [blame] | 12400 | crtc_state->scaler_state = scaler_state; |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 12401 | crtc_state->shared_dpll = shared_dpll; |
| 12402 | crtc_state->dpll_hw_state = dpll_hw_state; |
Ander Conselvan de Oliveira | 8504c74 | 2015-05-15 11:51:50 +0300 | [diff] [blame] | 12403 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 12404 | crtc_state->pch_pfit.force_thru = force_thru; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12405 | } |
| 12406 | |
Ander Conselvan de Oliveira | 548ee15 | 2015-04-21 17:13:02 +0300 | [diff] [blame] | 12407 | static int |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 12408 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 12409 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12410 | { |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 12411 | struct drm_atomic_state *state = pipe_config->base.state; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12412 | struct intel_encoder *encoder; |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12413 | struct drm_connector *connector; |
Ander Conselvan de Oliveira | 0b90187 | 2015-03-20 16:18:08 +0200 | [diff] [blame] | 12414 | struct drm_connector_state *connector_state; |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12415 | int base_bpp, ret = -EINVAL; |
Ander Conselvan de Oliveira | 0b90187 | 2015-03-20 16:18:08 +0200 | [diff] [blame] | 12416 | int i; |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 12417 | bool retry = true; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12418 | |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 12419 | clear_intel_crtc_state(pipe_config); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12420 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 12421 | pipe_config->cpu_transcoder = |
| 12422 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 12423 | |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12424 | /* |
| 12425 | * Sanitize sync polarity flags based on requested ones. If neither |
| 12426 | * positive or negative polarity is requested, treat this as meaning |
| 12427 | * negative polarity. |
| 12428 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12429 | if (!(pipe_config->base.adjusted_mode.flags & |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12430 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12431 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12432 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12433 | if (!(pipe_config->base.adjusted_mode.flags & |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12434 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12435 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 12436 | |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12437 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
| 12438 | pipe_config); |
| 12439 | if (base_bpp < 0) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12440 | goto fail; |
| 12441 | |
Ville Syrjälä | e41a56b | 2013-10-01 22:52:14 +0300 | [diff] [blame] | 12442 | /* |
| 12443 | * Determine the real pipe dimensions. Note that stereo modes can |
| 12444 | * increase the actual pipe size due to the frame doubling and |
| 12445 | * insertion of additional space for blanks between the frame. This |
| 12446 | * is stored in the crtc timings. We use the requested mode to do this |
| 12447 | * computation to clearly distinguish it from the adjusted mode, which |
| 12448 | * can be changed by the connectors in the below retry loop. |
| 12449 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12450 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
Gustavo Padovan | ecb7e16 | 2014-12-01 15:40:09 -0800 | [diff] [blame] | 12451 | &pipe_config->pipe_src_w, |
| 12452 | &pipe_config->pipe_src_h); |
Ville Syrjälä | e41a56b | 2013-10-01 22:52:14 +0300 | [diff] [blame] | 12453 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 12454 | encoder_retry: |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 12455 | /* Ensure the port clock defaults are reset when retrying. */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 12456 | pipe_config->port_clock = 0; |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 12457 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 12458 | |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 12459 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12460 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
| 12461 | CRTC_STEREO_DOUBLE); |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 12462 | |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12463 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
| 12464 | * adjust it according to limitations or connector properties, and also |
| 12465 | * a chance to reject the mode entirely. |
| 12466 | */ |
Ander Conselvan de Oliveira | da3ced298 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 12467 | for_each_connector_in_state(state, connector, connector_state, i) { |
Ander Conselvan de Oliveira | 0b90187 | 2015-03-20 16:18:08 +0200 | [diff] [blame] | 12468 | if (connector_state->crtc != crtc) |
| 12469 | continue; |
| 12470 | |
| 12471 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12472 | |
Daniel Vetter | efea6e8 | 2013-07-21 21:36:59 +0200 | [diff] [blame] | 12473 | if (!(encoder->compute_config(encoder, pipe_config))) { |
| 12474 | DRM_DEBUG_KMS("Encoder config failure\n"); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12475 | goto fail; |
| 12476 | } |
| 12477 | } |
| 12478 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 12479 | /* Set default port clock if not overwritten by the encoder. Needs to be |
| 12480 | * done afterwards in case the encoder adjusts the mode. */ |
| 12481 | if (!pipe_config->port_clock) |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12482 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 12483 | * pipe_config->pixel_multiplier; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 12484 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 12485 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 12486 | if (ret < 0) { |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12487 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
| 12488 | goto fail; |
| 12489 | } |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 12490 | |
| 12491 | if (ret == RETRY) { |
| 12492 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
| 12493 | ret = -EINVAL; |
| 12494 | goto fail; |
| 12495 | } |
| 12496 | |
| 12497 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
| 12498 | retry = false; |
| 12499 | goto encoder_retry; |
| 12500 | } |
| 12501 | |
Daniel Vetter | e8fa427 | 2015-08-12 11:43:34 +0200 | [diff] [blame] | 12502 | /* Dithering seems to not pass-through bits correctly when it should, so |
| 12503 | * only enable it on 6bpc panels. */ |
| 12504 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; |
Daniel Vetter | 62f0ace | 2015-08-26 18:57:26 +0200 | [diff] [blame] | 12505 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
Daniel Vetter | d328c9d | 2015-04-10 16:22:37 +0200 | [diff] [blame] | 12506 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 12507 | |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12508 | fail: |
Ander Conselvan de Oliveira | 548ee15 | 2015-04-21 17:13:02 +0300 | [diff] [blame] | 12509 | return ret; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 12510 | } |
| 12511 | |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 12512 | static void |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 12513 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 12514 | { |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 12515 | struct drm_crtc *crtc; |
| 12516 | struct drm_crtc_state *crtc_state; |
Maarten Lankhorst | 8a75d15 | 2015-07-13 16:30:14 +0200 | [diff] [blame] | 12517 | int i; |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 12518 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 12519 | /* Double check state. */ |
Maarten Lankhorst | 8a75d15 | 2015-07-13 16:30:14 +0200 | [diff] [blame] | 12520 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | 3cb480b | 2015-06-01 12:49:49 +0200 | [diff] [blame] | 12521 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
Maarten Lankhorst | fc467a22 | 2015-06-01 12:50:07 +0200 | [diff] [blame] | 12522 | |
| 12523 | /* Update hwmode for vblank functions */ |
| 12524 | if (crtc->state->active) |
| 12525 | crtc->hwmode = crtc->state->adjusted_mode; |
| 12526 | else |
| 12527 | crtc->hwmode.crtc_clock = 0; |
Maarten Lankhorst | 61067a5 | 2015-09-23 16:29:36 +0200 | [diff] [blame] | 12528 | |
| 12529 | /* |
| 12530 | * Update legacy state to satisfy fbc code. This can |
| 12531 | * be removed when fbc uses the atomic state. |
| 12532 | */ |
| 12533 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { |
| 12534 | struct drm_plane_state *plane_state = crtc->primary->state; |
| 12535 | |
| 12536 | crtc->primary->fb = plane_state->fb; |
| 12537 | crtc->x = plane_state->src_x >> 16; |
| 12538 | crtc->y = plane_state->src_y >> 16; |
| 12539 | } |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 12540 | } |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 12541 | } |
| 12542 | |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 12543 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 12544 | { |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 12545 | int diff; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 12546 | |
| 12547 | if (clock1 == clock2) |
| 12548 | return true; |
| 12549 | |
| 12550 | if (!clock1 || !clock2) |
| 12551 | return false; |
| 12552 | |
| 12553 | diff = abs(clock1 - clock2); |
| 12554 | |
| 12555 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
| 12556 | return true; |
| 12557 | |
| 12558 | return false; |
| 12559 | } |
| 12560 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 12561 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
| 12562 | list_for_each_entry((intel_crtc), \ |
| 12563 | &(dev)->mode_config.crtc_list, \ |
| 12564 | base.head) \ |
Jani Nikula | 95150bd | 2015-11-24 21:21:56 +0200 | [diff] [blame] | 12565 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 12566 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12567 | static bool |
| 12568 | intel_compare_m_n(unsigned int m, unsigned int n, |
| 12569 | unsigned int m2, unsigned int n2, |
| 12570 | bool exact) |
| 12571 | { |
| 12572 | if (m == m2 && n == n2) |
| 12573 | return true; |
| 12574 | |
| 12575 | if (exact || !m || !n || !m2 || !n2) |
| 12576 | return false; |
| 12577 | |
| 12578 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); |
| 12579 | |
| 12580 | if (m > m2) { |
| 12581 | while (m > m2) { |
| 12582 | m2 <<= 1; |
| 12583 | n2 <<= 1; |
| 12584 | } |
| 12585 | } else if (m < m2) { |
| 12586 | while (m < m2) { |
| 12587 | m <<= 1; |
| 12588 | n <<= 1; |
| 12589 | } |
| 12590 | } |
| 12591 | |
| 12592 | return m == m2 && n == n2; |
| 12593 | } |
| 12594 | |
| 12595 | static bool |
| 12596 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, |
| 12597 | struct intel_link_m_n *m2_n2, |
| 12598 | bool adjust) |
| 12599 | { |
| 12600 | if (m_n->tu == m2_n2->tu && |
| 12601 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, |
| 12602 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && |
| 12603 | intel_compare_m_n(m_n->link_m, m_n->link_n, |
| 12604 | m2_n2->link_m, m2_n2->link_n, !adjust)) { |
| 12605 | if (adjust) |
| 12606 | *m2_n2 = *m_n; |
| 12607 | |
| 12608 | return true; |
| 12609 | } |
| 12610 | |
| 12611 | return false; |
| 12612 | } |
| 12613 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 12614 | static bool |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 12615 | intel_pipe_config_compare(struct drm_device *dev, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 12616 | struct intel_crtc_state *current_config, |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12617 | struct intel_crtc_state *pipe_config, |
| 12618 | bool adjust) |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 12619 | { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12620 | bool ret = true; |
| 12621 | |
| 12622 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ |
| 12623 | do { \ |
| 12624 | if (!adjust) \ |
| 12625 | DRM_ERROR(fmt, ##__VA_ARGS__); \ |
| 12626 | else \ |
| 12627 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ |
| 12628 | } while (0) |
| 12629 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 12630 | #define PIPE_CONF_CHECK_X(name) \ |
| 12631 | if (current_config->name != pipe_config->name) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12632 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 12633 | "(expected 0x%08x, found 0x%08x)\n", \ |
| 12634 | current_config->name, \ |
| 12635 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12636 | ret = false; \ |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 12637 | } |
| 12638 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 12639 | #define PIPE_CONF_CHECK_I(name) \ |
| 12640 | if (current_config->name != pipe_config->name) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12641 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 12642 | "(expected %i, found %i)\n", \ |
| 12643 | current_config->name, \ |
| 12644 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12645 | ret = false; \ |
| 12646 | } |
| 12647 | |
| 12648 | #define PIPE_CONF_CHECK_M_N(name) \ |
| 12649 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 12650 | &pipe_config->name,\ |
| 12651 | adjust)) { \ |
| 12652 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12653 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 12654 | "found tu %i, gmch %i/%i link %i/%i)\n", \ |
| 12655 | current_config->name.tu, \ |
| 12656 | current_config->name.gmch_m, \ |
| 12657 | current_config->name.gmch_n, \ |
| 12658 | current_config->name.link_m, \ |
| 12659 | current_config->name.link_n, \ |
| 12660 | pipe_config->name.tu, \ |
| 12661 | pipe_config->name.gmch_m, \ |
| 12662 | pipe_config->name.gmch_n, \ |
| 12663 | pipe_config->name.link_m, \ |
| 12664 | pipe_config->name.link_n); \ |
| 12665 | ret = false; \ |
| 12666 | } |
| 12667 | |
| 12668 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
| 12669 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 12670 | &pipe_config->name, adjust) && \ |
| 12671 | !intel_compare_link_m_n(¤t_config->alt_name, \ |
| 12672 | &pipe_config->name, adjust)) { \ |
| 12673 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12674 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 12675 | "or tu %i gmch %i/%i link %i/%i, " \ |
| 12676 | "found tu %i, gmch %i/%i link %i/%i)\n", \ |
| 12677 | current_config->name.tu, \ |
| 12678 | current_config->name.gmch_m, \ |
| 12679 | current_config->name.gmch_n, \ |
| 12680 | current_config->name.link_m, \ |
| 12681 | current_config->name.link_n, \ |
| 12682 | current_config->alt_name.tu, \ |
| 12683 | current_config->alt_name.gmch_m, \ |
| 12684 | current_config->alt_name.gmch_n, \ |
| 12685 | current_config->alt_name.link_m, \ |
| 12686 | current_config->alt_name.link_n, \ |
| 12687 | pipe_config->name.tu, \ |
| 12688 | pipe_config->name.gmch_m, \ |
| 12689 | pipe_config->name.gmch_n, \ |
| 12690 | pipe_config->name.link_m, \ |
| 12691 | pipe_config->name.link_n); \ |
| 12692 | ret = false; \ |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 12693 | } |
| 12694 | |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12695 | /* This is required for BDW+ where there is only one set of registers for |
| 12696 | * switching between high and low RR. |
| 12697 | * This macro can be used whenever a comparison has to be made between one |
| 12698 | * hw state and multiple sw state variables. |
| 12699 | */ |
| 12700 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ |
| 12701 | if ((current_config->name != pipe_config->name) && \ |
| 12702 | (current_config->alt_name != pipe_config->name)) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12703 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12704 | "(expected %i or %i, found %i)\n", \ |
| 12705 | current_config->name, \ |
| 12706 | current_config->alt_name, \ |
| 12707 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12708 | ret = false; \ |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12709 | } |
| 12710 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12711 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
| 12712 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12713 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12714 | "(expected %i, found %i)\n", \ |
| 12715 | current_config->name & (mask), \ |
| 12716 | pipe_config->name & (mask)); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12717 | ret = false; \ |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12718 | } |
| 12719 | |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 12720 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
| 12721 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12722 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 12723 | "(expected %i, found %i)\n", \ |
| 12724 | current_config->name, \ |
| 12725 | pipe_config->name); \ |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12726 | ret = false; \ |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 12727 | } |
| 12728 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12729 | #define PIPE_CONF_QUIRK(quirk) \ |
| 12730 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
| 12731 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 12732 | PIPE_CONF_CHECK_I(cpu_transcoder); |
| 12733 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 12734 | PIPE_CONF_CHECK_I(has_pch_encoder); |
| 12735 | PIPE_CONF_CHECK_I(fdi_lanes); |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12736 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 12737 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 12738 | PIPE_CONF_CHECK_I(has_dp_encoder); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 12739 | PIPE_CONF_CHECK_I(lane_count); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12740 | |
| 12741 | if (INTEL_INFO(dev)->gen < 8) { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12742 | PIPE_CONF_CHECK_M_N(dp_m_n); |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12743 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12744 | if (current_config->has_drrs) |
| 12745 | PIPE_CONF_CHECK_M_N(dp_m2_n2); |
| 12746 | } else |
| 12747 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 12748 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 12749 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
| 12750 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12751 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
| 12752 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); |
| 12753 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); |
| 12754 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); |
| 12755 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); |
| 12756 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12757 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12758 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
| 12759 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); |
| 12760 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); |
| 12761 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); |
| 12762 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); |
| 12763 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12764 | |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 12765 | PIPE_CONF_CHECK_I(pixel_multiplier); |
Daniel Vetter | 6897b4b5 | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 12766 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 12767 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 12768 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Daniel Vetter | b5a9fa0 | 2014-04-24 23:54:49 +0200 | [diff] [blame] | 12769 | PIPE_CONF_CHECK_I(limited_color_range); |
Jesse Barnes | e43823e | 2014-11-05 14:26:08 -0800 | [diff] [blame] | 12770 | PIPE_CONF_CHECK_I(has_infoframe); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 12771 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 12772 | PIPE_CONF_CHECK_I(has_audio); |
| 12773 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12774 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12775 | DRM_MODE_FLAG_INTERLACE); |
| 12776 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12777 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12778 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12779 | DRM_MODE_FLAG_PHSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12780 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12781 | DRM_MODE_FLAG_NHSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12782 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12783 | DRM_MODE_FLAG_PVSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12784 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12785 | DRM_MODE_FLAG_NVSYNC); |
| 12786 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 12787 | |
Ville Syrjälä | 333b8ca | 2015-09-03 21:50:16 +0300 | [diff] [blame] | 12788 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
Daniel Vetter | e2ff2d4 | 2015-07-15 14:15:50 +0200 | [diff] [blame] | 12789 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
| 12790 | if (INTEL_INFO(dev)->gen < 4) |
| 12791 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
Ville Syrjälä | 333b8ca | 2015-09-03 21:50:16 +0300 | [diff] [blame] | 12792 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
Daniel Vetter | 9953599 | 2014-04-13 12:00:33 +0200 | [diff] [blame] | 12793 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 12794 | if (!adjust) { |
| 12795 | PIPE_CONF_CHECK_I(pipe_src_w); |
| 12796 | PIPE_CONF_CHECK_I(pipe_src_h); |
| 12797 | |
| 12798 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
| 12799 | if (current_config->pch_pfit.enabled) { |
| 12800 | PIPE_CONF_CHECK_X(pch_pfit.pos); |
| 12801 | PIPE_CONF_CHECK_X(pch_pfit.size); |
| 12802 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 12803 | |
Maarten Lankhorst | 7aefe2b | 2015-09-14 11:30:10 +0200 | [diff] [blame] | 12804 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
| 12805 | } |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 12806 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 12807 | /* BDW+ don't expose a synchronous way to read the state */ |
| 12808 | if (IS_HASWELL(dev)) |
| 12809 | PIPE_CONF_CHECK_I(ips_enabled); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 12810 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 12811 | PIPE_CONF_CHECK_I(double_wide); |
| 12812 | |
Daniel Vetter | 26804af | 2014-06-25 22:01:55 +0300 | [diff] [blame] | 12813 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
| 12814 | |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 12815 | PIPE_CONF_CHECK_I(shared_dpll); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 12816 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 12817 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 12818 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
| 12819 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 12820 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 12821 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
Damien Lespiau | 3f4cd19 | 2014-11-13 14:55:21 +0000 | [diff] [blame] | 12822 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
| 12823 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); |
| 12824 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 12825 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 12826 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
| 12827 | PIPE_CONF_CHECK_I(pipe_bpp); |
| 12828 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 12829 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
Jesse Barnes | a9a7e98 | 2014-01-20 14:18:04 -0800 | [diff] [blame] | 12830 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 12831 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 12832 | #undef PIPE_CONF_CHECK_X |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 12833 | #undef PIPE_CONF_CHECK_I |
Vandana Kannan | b95af8b | 2014-08-05 07:51:23 -0700 | [diff] [blame] | 12834 | #undef PIPE_CONF_CHECK_I_ALT |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 12835 | #undef PIPE_CONF_CHECK_FLAGS |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 12836 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 12837 | #undef PIPE_CONF_QUIRK |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12838 | #undef INTEL_ERR_OR_DBG_KMS |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 12839 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12840 | return ret; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 12841 | } |
| 12842 | |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 12843 | static void check_wm_state(struct drm_device *dev) |
| 12844 | { |
| 12845 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12846 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
| 12847 | struct intel_crtc *intel_crtc; |
| 12848 | int plane; |
| 12849 | |
| 12850 | if (INTEL_INFO(dev)->gen < 9) |
| 12851 | return; |
| 12852 | |
| 12853 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
| 12854 | sw_ddb = &dev_priv->wm.skl_hw.ddb; |
| 12855 | |
| 12856 | for_each_intel_crtc(dev, intel_crtc) { |
| 12857 | struct skl_ddb_entry *hw_entry, *sw_entry; |
| 12858 | const enum pipe pipe = intel_crtc->pipe; |
| 12859 | |
| 12860 | if (!intel_crtc->active) |
| 12861 | continue; |
| 12862 | |
| 12863 | /* planes */ |
Damien Lespiau | dd74078 | 2015-02-28 14:54:08 +0000 | [diff] [blame] | 12864 | for_each_plane(dev_priv, pipe, plane) { |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 12865 | hw_entry = &hw_ddb.plane[pipe][plane]; |
| 12866 | sw_entry = &sw_ddb->plane[pipe][plane]; |
| 12867 | |
| 12868 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
| 12869 | continue; |
| 12870 | |
| 12871 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
| 12872 | "(expected (%u,%u), found (%u,%u))\n", |
| 12873 | pipe_name(pipe), plane + 1, |
| 12874 | sw_entry->start, sw_entry->end, |
| 12875 | hw_entry->start, hw_entry->end); |
| 12876 | } |
| 12877 | |
| 12878 | /* cursor */ |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 12879 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
| 12880 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 12881 | |
| 12882 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
| 12883 | continue; |
| 12884 | |
| 12885 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
| 12886 | "(expected (%u,%u), found (%u,%u))\n", |
| 12887 | pipe_name(pipe), |
| 12888 | sw_entry->start, sw_entry->end, |
| 12889 | hw_entry->start, hw_entry->end); |
| 12890 | } |
| 12891 | } |
| 12892 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 12893 | static void |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 12894 | check_connector_state(struct drm_device *dev, |
| 12895 | struct drm_atomic_state *old_state) |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12896 | { |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 12897 | struct drm_connector_state *old_conn_state; |
| 12898 | struct drm_connector *connector; |
| 12899 | int i; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12900 | |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 12901 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
| 12902 | struct drm_encoder *encoder = connector->encoder; |
| 12903 | struct drm_connector_state *state = connector->state; |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 12904 | |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12905 | /* This also checks the encoder/connector hw state with the |
| 12906 | * ->get_hw_state callbacks. */ |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 12907 | intel_connector_check_state(to_intel_connector(connector)); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12908 | |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 12909 | I915_STATE_WARN(state->best_encoder != encoder, |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 12910 | "connector's atomic encoder doesn't match legacy encoder\n"); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12911 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 12912 | } |
| 12913 | |
| 12914 | static void |
| 12915 | check_encoder_state(struct drm_device *dev) |
| 12916 | { |
| 12917 | struct intel_encoder *encoder; |
| 12918 | struct intel_connector *connector; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12919 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 12920 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12921 | bool enabled = false; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12922 | enum pipe pipe; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12923 | |
| 12924 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
| 12925 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 12926 | encoder->base.name); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12927 | |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 12928 | for_each_intel_connector(dev, connector) { |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12929 | if (connector->base.state->best_encoder != &encoder->base) |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12930 | continue; |
| 12931 | enabled = true; |
Maarten Lankhorst | ad3c558 | 2015-07-13 16:30:26 +0200 | [diff] [blame] | 12932 | |
| 12933 | I915_STATE_WARN(connector->base.state->crtc != |
| 12934 | encoder->base.crtc, |
| 12935 | "connector's crtc doesn't match encoder crtc\n"); |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12936 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 12937 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 12938 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12939 | "encoder's enabled state mismatch " |
| 12940 | "(expected %i, found %i)\n", |
| 12941 | !!encoder->base.crtc, enabled); |
Maarten Lankhorst | 7c60d19 | 2015-08-05 12:37:04 +0200 | [diff] [blame] | 12942 | |
| 12943 | if (!encoder->base.crtc) { |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12944 | bool active; |
| 12945 | |
| 12946 | active = encoder->get_hw_state(encoder, &pipe); |
Maarten Lankhorst | 7c60d19 | 2015-08-05 12:37:04 +0200 | [diff] [blame] | 12947 | I915_STATE_WARN(active, |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12948 | "encoder detached but still enabled on pipe %c.\n", |
| 12949 | pipe_name(pipe)); |
Maarten Lankhorst | 7c60d19 | 2015-08-05 12:37:04 +0200 | [diff] [blame] | 12950 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12951 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 12952 | } |
| 12953 | |
| 12954 | static void |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12955 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 12956 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 12957 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 12958 | struct intel_encoder *encoder; |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12959 | struct drm_crtc_state *old_crtc_state; |
| 12960 | struct drm_crtc *crtc; |
| 12961 | int i; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12962 | |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12963 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
| 12964 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 12965 | struct intel_crtc_state *pipe_config, *sw_config; |
Maarten Lankhorst | 7b89b8d | 2015-08-05 12:37:03 +0200 | [diff] [blame] | 12966 | bool active; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 12967 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 12968 | if (!needs_modeset(crtc->state) && |
| 12969 | !to_intel_crtc_state(crtc->state)->update_pipe) |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 12970 | continue; |
| 12971 | |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 12972 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
| 12973 | pipe_config = to_intel_crtc_state(old_crtc_state); |
| 12974 | memset(pipe_config, 0, sizeof(*pipe_config)); |
| 12975 | pipe_config->base.crtc = crtc; |
| 12976 | pipe_config->base.state = old_state; |
| 12977 | |
| 12978 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
| 12979 | crtc->base.id); |
| 12980 | |
| 12981 | active = dev_priv->display.get_pipe_config(intel_crtc, |
| 12982 | pipe_config); |
| 12983 | |
| 12984 | /* hw state is inconsistent with the pipe quirk */ |
| 12985 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 12986 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 12987 | active = crtc->state->active; |
| 12988 | |
| 12989 | I915_STATE_WARN(crtc->state->active != active, |
| 12990 | "crtc active state doesn't match with hw state " |
| 12991 | "(expected %i, found %i)\n", crtc->state->active, active); |
| 12992 | |
| 12993 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
| 12994 | "transitional active state does not match atomic hw state " |
| 12995 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
| 12996 | |
| 12997 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 12998 | enum pipe pipe; |
| 12999 | |
| 13000 | active = encoder->get_hw_state(encoder, &pipe); |
| 13001 | I915_STATE_WARN(active != crtc->state->active, |
| 13002 | "[ENCODER:%i] active %i with crtc active %i\n", |
| 13003 | encoder->base.base.id, active, crtc->state->active); |
| 13004 | |
| 13005 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
| 13006 | "Encoder connected to wrong pipe %c\n", |
| 13007 | pipe_name(pipe)); |
| 13008 | |
| 13009 | if (active) |
| 13010 | encoder->get_config(encoder, pipe_config); |
| 13011 | } |
| 13012 | |
| 13013 | if (!crtc->state->active) |
| 13014 | continue; |
| 13015 | |
| 13016 | sw_config = to_intel_crtc_state(crtc->state); |
| 13017 | if (!intel_pipe_config_compare(dev, sw_config, |
| 13018 | pipe_config, false)) { |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13019 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13020 | intel_dump_pipe_config(intel_crtc, pipe_config, |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 13021 | "[hw state]"); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13022 | intel_dump_pipe_config(intel_crtc, sw_config, |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 13023 | "[sw state]"); |
| 13024 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 13025 | } |
| 13026 | } |
| 13027 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13028 | static void |
| 13029 | check_shared_dpll_state(struct drm_device *dev) |
| 13030 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 13031 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13032 | struct intel_crtc *crtc; |
| 13033 | struct intel_dpll_hw_state dpll_hw_state; |
| 13034 | int i; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13035 | |
| 13036 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 13037 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 13038 | int enabled_crtcs = 0, active_crtcs = 0; |
| 13039 | bool active; |
| 13040 | |
| 13041 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
| 13042 | |
| 13043 | DRM_DEBUG_KMS("%s\n", pll->name); |
| 13044 | |
| 13045 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
| 13046 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13047 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13048 | "more active pll users than references: %i vs %i\n", |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 13049 | pll->active, hweight32(pll->config.crtc_mask)); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13050 | I915_STATE_WARN(pll->active && !pll->on, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13051 | "pll in active use but not on in sw tracking\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13052 | I915_STATE_WARN(pll->on && !pll->active, |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 13053 | "pll in on but not on in use in sw tracking\n"); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13054 | I915_STATE_WARN(pll->on != active, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13055 | "pll on state mismatch (expected %i, found %i)\n", |
| 13056 | pll->on, active); |
| 13057 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 13058 | for_each_intel_crtc(dev, crtc) { |
Matt Roper | 83d6573 | 2015-02-25 13:12:16 -0800 | [diff] [blame] | 13059 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13060 | enabled_crtcs++; |
| 13061 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
| 13062 | active_crtcs++; |
| 13063 | } |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13064 | I915_STATE_WARN(pll->active != active_crtcs, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13065 | "pll active crtcs mismatch (expected %i, found %i)\n", |
| 13066 | pll->active, active_crtcs); |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13067 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13068 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 13069 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13070 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 13071 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13072 | sizeof(dpll_hw_state)), |
| 13073 | "pll hw state mismatch\n"); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13074 | } |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 13075 | } |
| 13076 | |
Maarten Lankhorst | ee165b1 | 2015-08-05 12:37:00 +0200 | [diff] [blame] | 13077 | static void |
| 13078 | intel_modeset_check_state(struct drm_device *dev, |
| 13079 | struct drm_atomic_state *old_state) |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13080 | { |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 13081 | check_wm_state(dev); |
Maarten Lankhorst | 35dd3c6 | 2015-08-06 13:49:22 +0200 | [diff] [blame] | 13082 | check_connector_state(dev, old_state); |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13083 | check_encoder_state(dev); |
Maarten Lankhorst | 4d20cd8 | 2015-08-05 12:37:05 +0200 | [diff] [blame] | 13084 | check_crtc_state(dev, old_state); |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 13085 | check_shared_dpll_state(dev); |
| 13086 | } |
| 13087 | |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 13088 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 13089 | int dotclock) |
| 13090 | { |
| 13091 | /* |
| 13092 | * FDI already provided one idea for the dotclock. |
| 13093 | * Yell if the encoder disagrees. |
| 13094 | */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13095 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 13096 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 13097 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 13098 | } |
| 13099 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13100 | static void update_scanline_offset(struct intel_crtc *crtc) |
| 13101 | { |
| 13102 | struct drm_device *dev = crtc->base.dev; |
| 13103 | |
| 13104 | /* |
| 13105 | * The scanline counter increments at the leading edge of hsync. |
| 13106 | * |
| 13107 | * On most platforms it starts counting from vtotal-1 on the |
| 13108 | * first active line. That means the scanline counter value is |
| 13109 | * always one less than what we would expect. Ie. just after |
| 13110 | * start of vblank, which also occurs at start of hsync (on the |
| 13111 | * last active line), the scanline counter will read vblank_start-1. |
| 13112 | * |
| 13113 | * On gen2 the scanline counter starts counting from 1 instead |
| 13114 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
| 13115 | * to keep the value positive), instead of adding one. |
| 13116 | * |
| 13117 | * On HSW+ the behaviour of the scanline counter depends on the output |
| 13118 | * type. For DP ports it behaves like most other platforms, but on HDMI |
| 13119 | * there's an extra 1 line difference. So we need to add two instead of |
| 13120 | * one to the value. |
| 13121 | */ |
| 13122 | if (IS_GEN2(dev)) { |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 13123 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13124 | int vtotal; |
| 13125 | |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 13126 | vtotal = adjusted_mode->crtc_vtotal; |
| 13127 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13128 | vtotal /= 2; |
| 13129 | |
| 13130 | crtc->scanline_offset = vtotal - 1; |
| 13131 | } else if (HAS_DDI(dev) && |
Ander Conselvan de Oliveira | 409ee76 | 2014-10-20 13:46:45 +0300 | [diff] [blame] | 13132 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13133 | crtc->scanline_offset = 2; |
| 13134 | } else |
| 13135 | crtc->scanline_offset = 1; |
| 13136 | } |
| 13137 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13138 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13139 | { |
Ander Conselvan de Oliveira | 225da59 | 2015-04-02 14:47:57 +0300 | [diff] [blame] | 13140 | struct drm_device *dev = state->dev; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13141 | struct drm_i915_private *dev_priv = to_i915(dev); |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13142 | struct intel_shared_dpll_config *shared_dpll = NULL; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13143 | struct intel_crtc *intel_crtc; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13144 | struct intel_crtc_state *intel_crtc_state; |
| 13145 | struct drm_crtc *crtc; |
| 13146 | struct drm_crtc_state *crtc_state; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13147 | int i; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13148 | |
| 13149 | if (!dev_priv->display.crtc_compute_clock) |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13150 | return; |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13151 | |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13152 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13153 | int dpll; |
| 13154 | |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13155 | intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 4978cc9 | 2015-04-21 17:13:21 +0300 | [diff] [blame] | 13156 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13157 | dpll = intel_crtc_state->shared_dpll; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13158 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13159 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
Ander Conselvan de Oliveira | 225da59 | 2015-04-02 14:47:57 +0300 | [diff] [blame] | 13160 | continue; |
| 13161 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13162 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13163 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13164 | if (!shared_dpll) |
| 13165 | shared_dpll = intel_atomic_get_shared_dpll_state(state); |
| 13166 | |
| 13167 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13168 | } |
Ander Conselvan de Oliveira | ed6739e | 2015-01-29 16:55:08 +0200 | [diff] [blame] | 13169 | } |
| 13170 | |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 13171 | /* |
| 13172 | * This implements the workaround described in the "notes" section of the mode |
| 13173 | * set sequence documentation. When going from no pipes or single pipe to |
| 13174 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
| 13175 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
| 13176 | */ |
| 13177 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) |
| 13178 | { |
| 13179 | struct drm_crtc_state *crtc_state; |
| 13180 | struct intel_crtc *intel_crtc; |
| 13181 | struct drm_crtc *crtc; |
| 13182 | struct intel_crtc_state *first_crtc_state = NULL; |
| 13183 | struct intel_crtc_state *other_crtc_state = NULL; |
| 13184 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; |
| 13185 | int i; |
| 13186 | |
| 13187 | /* look at all crtc's that are going to be enabled in during modeset */ |
| 13188 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13189 | intel_crtc = to_intel_crtc(crtc); |
| 13190 | |
| 13191 | if (!crtc_state->active || !needs_modeset(crtc_state)) |
| 13192 | continue; |
| 13193 | |
| 13194 | if (first_crtc_state) { |
| 13195 | other_crtc_state = to_intel_crtc_state(crtc_state); |
| 13196 | break; |
| 13197 | } else { |
| 13198 | first_crtc_state = to_intel_crtc_state(crtc_state); |
| 13199 | first_pipe = intel_crtc->pipe; |
| 13200 | } |
| 13201 | } |
| 13202 | |
| 13203 | /* No workaround needed? */ |
| 13204 | if (!first_crtc_state) |
| 13205 | return 0; |
| 13206 | |
| 13207 | /* w/a possibly needed, check how many crtc's are already enabled. */ |
| 13208 | for_each_intel_crtc(state->dev, intel_crtc) { |
| 13209 | struct intel_crtc_state *pipe_config; |
| 13210 | |
| 13211 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); |
| 13212 | if (IS_ERR(pipe_config)) |
| 13213 | return PTR_ERR(pipe_config); |
| 13214 | |
| 13215 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; |
| 13216 | |
| 13217 | if (!pipe_config->base.active || |
| 13218 | needs_modeset(&pipe_config->base)) |
| 13219 | continue; |
| 13220 | |
| 13221 | /* 2 or more enabled crtcs means no need for w/a */ |
| 13222 | if (enabled_pipe != INVALID_PIPE) |
| 13223 | return 0; |
| 13224 | |
| 13225 | enabled_pipe = intel_crtc->pipe; |
| 13226 | } |
| 13227 | |
| 13228 | if (enabled_pipe != INVALID_PIPE) |
| 13229 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; |
| 13230 | else if (other_crtc_state) |
| 13231 | other_crtc_state->hsw_workaround_pipe = first_pipe; |
| 13232 | |
| 13233 | return 0; |
| 13234 | } |
| 13235 | |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13236 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
| 13237 | { |
| 13238 | struct drm_crtc *crtc; |
| 13239 | struct drm_crtc_state *crtc_state; |
| 13240 | int ret = 0; |
| 13241 | |
| 13242 | /* add all active pipes to the state */ |
| 13243 | for_each_crtc(state->dev, crtc) { |
| 13244 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 13245 | if (IS_ERR(crtc_state)) |
| 13246 | return PTR_ERR(crtc_state); |
| 13247 | |
| 13248 | if (!crtc_state->active || needs_modeset(crtc_state)) |
| 13249 | continue; |
| 13250 | |
| 13251 | crtc_state->mode_changed = true; |
| 13252 | |
| 13253 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 13254 | if (ret) |
| 13255 | break; |
| 13256 | |
| 13257 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 13258 | if (ret) |
| 13259 | break; |
| 13260 | } |
| 13261 | |
| 13262 | return ret; |
| 13263 | } |
| 13264 | |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13265 | static int intel_modeset_checks(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13266 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13267 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 13268 | struct drm_i915_private *dev_priv = state->dev->dev_private; |
| 13269 | struct drm_crtc *crtc; |
| 13270 | struct drm_crtc_state *crtc_state; |
| 13271 | int ret = 0, i; |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13272 | |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 13273 | if (!check_digital_port_conflicts(state)) { |
| 13274 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
| 13275 | return -EINVAL; |
| 13276 | } |
| 13277 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13278 | intel_state->modeset = true; |
| 13279 | intel_state->active_crtcs = dev_priv->active_crtcs; |
| 13280 | |
| 13281 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13282 | if (crtc_state->active) |
| 13283 | intel_state->active_crtcs |= 1 << i; |
| 13284 | else |
| 13285 | intel_state->active_crtcs &= ~(1 << i); |
| 13286 | } |
| 13287 | |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13288 | /* |
| 13289 | * See if the config requires any additional preparation, e.g. |
| 13290 | * to adjust global state with pipes off. We need to do this |
| 13291 | * here so we can get the modeset_pipe updated config for the new |
| 13292 | * mode set on this crtc. For other crtcs we need to use the |
| 13293 | * adjusted_mode bits in the crtc directly. |
| 13294 | */ |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13295 | if (dev_priv->display.modeset_calc_cdclk) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13296 | ret = dev_priv->display.modeset_calc_cdclk(state); |
| 13297 | |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 13298 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13299 | ret = intel_modeset_all_pipes(state); |
| 13300 | |
| 13301 | if (ret < 0) |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13302 | return ret; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13303 | } else |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 13304 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13305 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13306 | intel_modeset_clear_plls(state); |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13307 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13308 | if (IS_HASWELL(dev_priv)) |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13309 | return haswell_mode_set_planes_workaround(state); |
Maarten Lankhorst | 99d736a | 2015-06-01 12:50:09 +0200 | [diff] [blame] | 13310 | |
Maarten Lankhorst | ad42137 | 2015-06-15 12:33:42 +0200 | [diff] [blame] | 13311 | return 0; |
Ander Conselvan de Oliveira | 054518d | 2015-04-21 17:13:06 +0300 | [diff] [blame] | 13312 | } |
| 13313 | |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13314 | /* |
| 13315 | * Handle calculation of various watermark data at the end of the atomic check |
| 13316 | * phase. The code here should be run after the per-crtc and per-plane 'check' |
| 13317 | * handlers to ensure that all derived state has been updated. |
| 13318 | */ |
| 13319 | static void calc_watermark_data(struct drm_atomic_state *state) |
| 13320 | { |
| 13321 | struct drm_device *dev = state->dev; |
| 13322 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 13323 | struct drm_crtc *crtc; |
| 13324 | struct drm_crtc_state *cstate; |
| 13325 | struct drm_plane *plane; |
| 13326 | struct drm_plane_state *pstate; |
| 13327 | |
| 13328 | /* |
| 13329 | * Calculate watermark configuration details now that derived |
| 13330 | * plane/crtc state is all properly updated. |
| 13331 | */ |
| 13332 | drm_for_each_crtc(crtc, dev) { |
| 13333 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: |
| 13334 | crtc->state; |
| 13335 | |
| 13336 | if (cstate->active) |
| 13337 | intel_state->wm_config.num_pipes_active++; |
| 13338 | } |
| 13339 | drm_for_each_legacy_plane(plane, dev) { |
| 13340 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: |
| 13341 | plane->state; |
| 13342 | |
| 13343 | if (!to_intel_plane_state(pstate)->visible) |
| 13344 | continue; |
| 13345 | |
| 13346 | intel_state->wm_config.sprites_enabled = true; |
| 13347 | if (pstate->crtc_w != pstate->src_w >> 16 || |
| 13348 | pstate->crtc_h != pstate->src_h >> 16) |
| 13349 | intel_state->wm_config.sprites_scaled = true; |
| 13350 | } |
| 13351 | } |
| 13352 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13353 | /** |
| 13354 | * intel_atomic_check - validate state object |
| 13355 | * @dev: drm device |
| 13356 | * @state: state to validate |
| 13357 | */ |
| 13358 | static int intel_atomic_check(struct drm_device *dev, |
| 13359 | struct drm_atomic_state *state) |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13360 | { |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13361 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13362 | struct drm_crtc *crtc; |
| 13363 | struct drm_crtc_state *crtc_state; |
| 13364 | int ret, i; |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13365 | bool any_ms = false; |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13366 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13367 | ret = drm_atomic_helper_check_modeset(dev, state); |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13368 | if (ret) |
| 13369 | return ret; |
| 13370 | |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13371 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13372 | struct intel_crtc_state *pipe_config = |
| 13373 | to_intel_crtc_state(crtc_state); |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 13374 | |
Maarten Lankhorst | ba8af3e | 2015-11-16 12:49:14 +0100 | [diff] [blame] | 13375 | memset(&to_intel_crtc(crtc)->atomic, 0, |
| 13376 | sizeof(struct intel_crtc_atomic_commit)); |
| 13377 | |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 13378 | /* Catch I915_MODE_FLAG_INHERITED */ |
| 13379 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) |
| 13380 | crtc_state->mode_changed = true; |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13381 | |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13382 | if (!crtc_state->enable) { |
| 13383 | if (needs_modeset(crtc_state)) |
| 13384 | any_ms = true; |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13385 | continue; |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13386 | } |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13387 | |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13388 | if (!needs_modeset(crtc_state)) |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13389 | continue; |
| 13390 | |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13391 | /* FIXME: For only active_changed we shouldn't need to do any |
| 13392 | * state recomputation at all. */ |
| 13393 | |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 13394 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 13395 | if (ret) |
| 13396 | return ret; |
Maarten Lankhorst | b359283 | 2015-06-15 12:33:38 +0200 | [diff] [blame] | 13397 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13398 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13399 | if (ret) |
| 13400 | return ret; |
| 13401 | |
Jani Nikula | 7383123 | 2015-11-19 10:26:30 +0200 | [diff] [blame] | 13402 | if (i915.fastboot && |
| 13403 | intel_pipe_config_compare(state->dev, |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13404 | to_intel_crtc_state(crtc->state), |
Daniel Vetter | 1ed51de | 2015-07-15 14:15:51 +0200 | [diff] [blame] | 13405 | pipe_config, true)) { |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13406 | crtc_state->mode_changed = false; |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 13407 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13408 | } |
| 13409 | |
| 13410 | if (needs_modeset(crtc_state)) { |
| 13411 | any_ms = true; |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13412 | |
Maarten Lankhorst | cfb23ed | 2015-07-14 12:17:40 +0200 | [diff] [blame] | 13413 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 13414 | if (ret) |
| 13415 | return ret; |
| 13416 | } |
| 13417 | |
Daniel Vetter | 2649548 | 2015-07-15 14:15:52 +0200 | [diff] [blame] | 13418 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
| 13419 | needs_modeset(crtc_state) ? |
| 13420 | "[modeset]" : "[fastset]"); |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13421 | } |
| 13422 | |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13423 | if (any_ms) { |
| 13424 | ret = intel_modeset_checks(state); |
| 13425 | |
| 13426 | if (ret) |
| 13427 | return ret; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13428 | } else |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13429 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
Ander Conselvan de Oliveira | c347a67 | 2015-06-01 12:50:02 +0200 | [diff] [blame] | 13430 | |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13431 | ret = drm_atomic_helper_check_planes(state->dev, state); |
| 13432 | if (ret) |
| 13433 | return ret; |
| 13434 | |
| 13435 | calc_watermark_data(state); |
| 13436 | |
| 13437 | return 0; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13438 | } |
| 13439 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13440 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
| 13441 | struct drm_atomic_state *state, |
| 13442 | bool async) |
| 13443 | { |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13444 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13445 | struct drm_plane_state *plane_state; |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13446 | struct drm_crtc_state *crtc_state; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13447 | struct drm_plane *plane; |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13448 | struct drm_crtc *crtc; |
| 13449 | int i, ret; |
| 13450 | |
| 13451 | if (async) { |
| 13452 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); |
| 13453 | return -EINVAL; |
| 13454 | } |
| 13455 | |
| 13456 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13457 | ret = intel_crtc_wait_for_pending_flips(crtc); |
| 13458 | if (ret) |
| 13459 | return ret; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13460 | |
| 13461 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
| 13462 | flush_workqueue(dev_priv->wq); |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13463 | } |
| 13464 | |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13465 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 13466 | if (ret) |
| 13467 | return ret; |
| 13468 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13469 | ret = drm_atomic_helper_prepare_planes(dev, state); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13470 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 13471 | u32 reset_counter; |
| 13472 | |
| 13473 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 13474 | mutex_unlock(&dev->struct_mutex); |
| 13475 | |
| 13476 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 13477 | struct intel_plane_state *intel_plane_state = |
| 13478 | to_intel_plane_state(plane_state); |
| 13479 | |
| 13480 | if (!intel_plane_state->wait_req) |
| 13481 | continue; |
| 13482 | |
| 13483 | ret = __i915_wait_request(intel_plane_state->wait_req, |
| 13484 | reset_counter, true, |
| 13485 | NULL, NULL); |
| 13486 | |
| 13487 | /* Swallow -EIO errors to allow updates during hw lockup. */ |
| 13488 | if (ret == -EIO) |
| 13489 | ret = 0; |
| 13490 | |
| 13491 | if (ret) |
| 13492 | break; |
| 13493 | } |
| 13494 | |
| 13495 | if (!ret) |
| 13496 | return 0; |
| 13497 | |
| 13498 | mutex_lock(&dev->struct_mutex); |
| 13499 | drm_atomic_helper_cleanup_planes(dev, state); |
| 13500 | } |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13501 | |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13502 | mutex_unlock(&dev->struct_mutex); |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13503 | return ret; |
| 13504 | } |
| 13505 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13506 | /** |
| 13507 | * intel_atomic_commit - commit validated state object |
| 13508 | * @dev: DRM device |
| 13509 | * @state: the top-level driver state object |
| 13510 | * @async: asynchronous commit |
| 13511 | * |
| 13512 | * This function commits a top-level state object that has been validated |
| 13513 | * with drm_atomic_helper_check(). |
| 13514 | * |
| 13515 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment |
| 13516 | * we can only handle plane-related operations and do not yet support |
| 13517 | * asynchronous commit. |
| 13518 | * |
| 13519 | * RETURNS |
| 13520 | * Zero for success or -errno. |
| 13521 | */ |
| 13522 | static int intel_atomic_commit(struct drm_device *dev, |
| 13523 | struct drm_atomic_state *state, |
| 13524 | bool async) |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13525 | { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13526 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 13527 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13528 | struct drm_crtc_state *crtc_state; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13529 | struct drm_crtc *crtc; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13530 | int ret = 0, i; |
| 13531 | bool hw_check = intel_state->modeset; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13532 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13533 | ret = intel_atomic_prepare_commit(dev, state, async); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13534 | if (ret) { |
| 13535 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); |
Ander Conselvan de Oliveira | d4afb8c | 2015-04-21 17:13:22 +0300 | [diff] [blame] | 13536 | return ret; |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13537 | } |
Ander Conselvan de Oliveira | d4afb8c | 2015-04-21 17:13:22 +0300 | [diff] [blame] | 13538 | |
Maarten Lankhorst | 1c5e19f | 2015-06-01 12:50:06 +0200 | [diff] [blame] | 13539 | drm_atomic_helper_swap_state(dev, state); |
Matt Roper | aa36313 | 2015-09-24 15:53:18 -0700 | [diff] [blame] | 13540 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
Maarten Lankhorst | 1c5e19f | 2015-06-01 12:50:06 +0200 | [diff] [blame] | 13541 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13542 | if (intel_state->modeset) { |
| 13543 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, |
| 13544 | sizeof(intel_state->min_pixclk)); |
| 13545 | dev_priv->active_crtcs = intel_state->active_crtcs; |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 13546 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13547 | } |
| 13548 | |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13549 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 13550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13551 | |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13552 | if (!needs_modeset(crtc->state)) |
| 13553 | continue; |
| 13554 | |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 13555 | intel_pre_plane_update(intel_crtc); |
Daniel Vetter | 460da916 | 2013-03-27 00:44:51 +0100 | [diff] [blame] | 13556 | |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 13557 | if (crtc_state->active) { |
| 13558 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
| 13559 | dev_priv->display.crtc_disable(crtc); |
Maarten Lankhorst | eddfcbc | 2015-06-15 12:33:53 +0200 | [diff] [blame] | 13560 | intel_crtc->active = false; |
| 13561 | intel_disable_shared_dpll(intel_crtc); |
Ville Syrjälä | 9bbc8258a | 2015-11-20 22:09:20 +0200 | [diff] [blame] | 13562 | |
| 13563 | /* |
| 13564 | * Underruns don't always raise |
| 13565 | * interrupts, so check manually. |
| 13566 | */ |
| 13567 | intel_check_cpu_fifo_underruns(dev_priv); |
| 13568 | intel_check_pch_fifo_underruns(dev_priv); |
Maarten Lankhorst | b900111 | 2015-11-19 16:07:16 +0100 | [diff] [blame] | 13569 | |
| 13570 | if (!crtc->state->active) |
| 13571 | intel_update_watermarks(crtc); |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 13572 | } |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 13573 | } |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 13574 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 13575 | /* Only after disabling all output pipelines that will be changed can we |
| 13576 | * update the the output configuration. */ |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 13577 | intel_modeset_update_crtc_state(state); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 13578 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13579 | if (intel_state->modeset) { |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 13580 | intel_shared_dpll_commit(state); |
| 13581 | |
| 13582 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
Maarten Lankhorst | 61333b6 | 2015-06-15 12:33:50 +0200 | [diff] [blame] | 13583 | modeset_update_crtc_power_domains(state); |
Maarten Lankhorst | 4740b0f | 2015-08-05 12:37:10 +0200 | [diff] [blame] | 13584 | } |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 13585 | |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13586 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
Ander Conselvan de Oliveira | 0a9ab30 | 2015-04-21 17:13:04 +0300 | [diff] [blame] | 13587 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
Maarten Lankhorst | f6ac4b2 | 2015-07-13 16:30:31 +0200 | [diff] [blame] | 13588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13589 | bool modeset = needs_modeset(crtc->state); |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 13590 | bool update_pipe = !modeset && |
| 13591 | to_intel_crtc_state(crtc->state)->update_pipe; |
| 13592 | unsigned long put_domains = 0; |
Maarten Lankhorst | f6ac4b2 | 2015-07-13 16:30:31 +0200 | [diff] [blame] | 13593 | |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 13594 | if (modeset) |
| 13595 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
| 13596 | |
Maarten Lankhorst | f6ac4b2 | 2015-07-13 16:30:31 +0200 | [diff] [blame] | 13597 | if (modeset && crtc->state->active) { |
Maarten Lankhorst | a539205 | 2015-06-15 12:33:52 +0200 | [diff] [blame] | 13598 | update_scanline_offset(to_intel_crtc(crtc)); |
| 13599 | dev_priv->display.crtc_enable(crtc); |
| 13600 | } |
| 13601 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 13602 | if (update_pipe) { |
| 13603 | put_domains = modeset_get_crtc_power_domains(crtc); |
| 13604 | |
| 13605 | /* make sure intel_modeset_check_state runs */ |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13606 | hw_check = true; |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 13607 | } |
| 13608 | |
Maarten Lankhorst | f6ac4b2 | 2015-07-13 16:30:31 +0200 | [diff] [blame] | 13609 | if (!modeset) |
| 13610 | intel_pre_plane_update(intel_crtc); |
| 13611 | |
Maarten Lankhorst | 6173ee2 | 2015-09-23 16:29:39 +0200 | [diff] [blame] | 13612 | if (crtc->state->active && |
| 13613 | (crtc->state->planes_changed || update_pipe)) |
Maarten Lankhorst | 6285262 | 2015-09-23 16:29:38 +0200 | [diff] [blame] | 13614 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 13615 | |
| 13616 | if (put_domains) |
| 13617 | modeset_put_power_domains(dev_priv, put_domains); |
| 13618 | |
Maarten Lankhorst | f6ac4b2 | 2015-07-13 16:30:31 +0200 | [diff] [blame] | 13619 | intel_post_plane_update(intel_crtc); |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 13620 | |
| 13621 | if (modeset) |
| 13622 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 13623 | } |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13624 | |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 13625 | /* FIXME: add subpixel order */ |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13626 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13627 | drm_atomic_helper_wait_for_vblanks(dev, state); |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13628 | |
| 13629 | mutex_lock(&dev->struct_mutex); |
Ander Conselvan de Oliveira | d4afb8c | 2015-04-21 17:13:22 +0300 | [diff] [blame] | 13630 | drm_atomic_helper_cleanup_planes(dev, state); |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13631 | mutex_unlock(&dev->struct_mutex); |
Ander Conselvan de Oliveira | 2bfb462 | 2015-04-21 17:13:20 +0300 | [diff] [blame] | 13632 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 13633 | if (hw_check) |
Maarten Lankhorst | ee165b1 | 2015-08-05 12:37:00 +0200 | [diff] [blame] | 13634 | intel_modeset_check_state(dev, state); |
| 13635 | |
| 13636 | drm_atomic_state_free(state); |
Jesse Barnes | 7f27126e | 2014-11-05 14:26:06 -0800 | [diff] [blame] | 13637 | |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13638 | return 0; |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 13639 | } |
| 13640 | |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 13641 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
| 13642 | { |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13643 | struct drm_device *dev = crtc->dev; |
| 13644 | struct drm_atomic_state *state; |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13645 | struct drm_crtc_state *crtc_state; |
Ander Conselvan de Oliveira | 2bfb462 | 2015-04-21 17:13:20 +0300 | [diff] [blame] | 13646 | int ret; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13647 | |
| 13648 | state = drm_atomic_state_alloc(dev); |
| 13649 | if (!state) { |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13650 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13651 | crtc->base.id); |
| 13652 | return; |
| 13653 | } |
| 13654 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13655 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13656 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13657 | retry: |
| 13658 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 13659 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 13660 | if (!ret) { |
| 13661 | if (!crtc_state->active) |
| 13662 | goto out; |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13663 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13664 | crtc_state->mode_changed = true; |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13665 | ret = drm_atomic_commit(state); |
Ander Conselvan de Oliveira | 83a5715 | 2015-03-20 16:18:03 +0200 | [diff] [blame] | 13666 | } |
| 13667 | |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13668 | if (ret == -EDEADLK) { |
| 13669 | drm_atomic_state_clear(state); |
| 13670 | drm_modeset_backoff(state->acquire_ctx); |
| 13671 | goto retry; |
Ander Conselvan de Oliveira | 4be0731 | 2015-04-21 17:13:01 +0300 | [diff] [blame] | 13672 | } |
| 13673 | |
Ander Conselvan de Oliveira | 2bfb462 | 2015-04-21 17:13:20 +0300 | [diff] [blame] | 13674 | if (ret) |
Maarten Lankhorst | e694eb0 | 2015-07-14 16:19:12 +0200 | [diff] [blame] | 13675 | out: |
Ander Conselvan de Oliveira | 2bfb462 | 2015-04-21 17:13:20 +0300 | [diff] [blame] | 13676 | drm_atomic_state_free(state); |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 13677 | } |
| 13678 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 13679 | #undef for_each_intel_crtc_masked |
| 13680 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 13681 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 13682 | .gamma_set = intel_crtc_gamma_set, |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 13683 | .set_config = drm_atomic_helper_set_config, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 13684 | .destroy = intel_crtc_destroy, |
| 13685 | .page_flip = intel_crtc_page_flip, |
Matt Roper | 1356837 | 2015-01-21 16:35:47 -0800 | [diff] [blame] | 13686 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
| 13687 | .atomic_destroy_state = intel_crtc_destroy_state, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 13688 | }; |
| 13689 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13690 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 13691 | struct intel_shared_dpll *pll, |
| 13692 | struct intel_dpll_hw_state *hw_state) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 13693 | { |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13694 | uint32_t val; |
| 13695 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 13696 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 13697 | return false; |
| 13698 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13699 | val = I915_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 13700 | hw_state->dpll = val; |
| 13701 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
| 13702 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13703 | |
| 13704 | return val & DPLL_VCO_ENABLE; |
| 13705 | } |
| 13706 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 13707 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
| 13708 | struct intel_shared_dpll *pll) |
| 13709 | { |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 13710 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
| 13711 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 13712 | } |
| 13713 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13714 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
| 13715 | struct intel_shared_dpll *pll) |
| 13716 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13717 | /* PCH refclock must be enabled first */ |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 13718 | ibx_assert_pch_refclk_enabled(dev_priv); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13719 | |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 13720 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 13721 | |
| 13722 | /* Wait for the clocks to stabilize. */ |
| 13723 | POSTING_READ(PCH_DPLL(pll->id)); |
| 13724 | udelay(150); |
| 13725 | |
| 13726 | /* The pixel multiplier can only be updated once the |
| 13727 | * DPLL is enabled and the clocks are stable. |
| 13728 | * |
| 13729 | * So write it again. |
| 13730 | */ |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 13731 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 13732 | POSTING_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13733 | udelay(200); |
| 13734 | } |
| 13735 | |
| 13736 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
| 13737 | struct intel_shared_dpll *pll) |
| 13738 | { |
| 13739 | struct drm_device *dev = dev_priv->dev; |
| 13740 | struct intel_crtc *crtc; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13741 | |
| 13742 | /* Make sure no transcoder isn't still depending on us. */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 13743 | for_each_intel_crtc(dev, crtc) { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13744 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
| 13745 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
| 13746 | } |
| 13747 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 13748 | I915_WRITE(PCH_DPLL(pll->id), 0); |
| 13749 | POSTING_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13750 | udelay(200); |
| 13751 | } |
| 13752 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 13753 | static char *ibx_pch_dpll_names[] = { |
| 13754 | "PCH DPLL A", |
| 13755 | "PCH DPLL B", |
| 13756 | }; |
| 13757 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 13758 | static void ibx_pch_dpll_init(struct drm_device *dev) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 13759 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13760 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 13761 | int i; |
| 13762 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 13763 | dev_priv->num_shared_dpll = 2; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 13764 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 13765 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 13766 | dev_priv->shared_dplls[i].id = i; |
| 13767 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 13768 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13769 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
| 13770 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 13771 | dev_priv->shared_dplls[i].get_hw_state = |
| 13772 | ibx_pch_dpll_get_hw_state; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 13773 | } |
| 13774 | } |
| 13775 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 13776 | static void intel_shared_dpll_init(struct drm_device *dev) |
| 13777 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 13778 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 13779 | |
Daniel Vetter | 9cd8693 | 2014-06-25 22:01:57 +0300 | [diff] [blame] | 13780 | if (HAS_DDI(dev)) |
| 13781 | intel_ddi_pll_init(dev); |
| 13782 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 13783 | ibx_pch_dpll_init(dev); |
| 13784 | else |
| 13785 | dev_priv->num_shared_dpll = 0; |
| 13786 | |
| 13787 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 13788 | } |
| 13789 | |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13790 | /** |
| 13791 | * intel_prepare_plane_fb - Prepare fb for usage on plane |
| 13792 | * @plane: drm plane to prepare for |
| 13793 | * @fb: framebuffer to prepare for presentation |
| 13794 | * |
| 13795 | * Prepares a framebuffer for usage on a display plane. Generally this |
| 13796 | * involves pinning the underlying object and updating the frontbuffer tracking |
| 13797 | * bits. Some older platforms need special physical address handling for |
| 13798 | * cursor planes. |
| 13799 | * |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13800 | * Must be called with struct_mutex held. |
| 13801 | * |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13802 | * Returns 0 on success, negative error code on failure. |
| 13803 | */ |
| 13804 | int |
| 13805 | intel_prepare_plane_fb(struct drm_plane *plane, |
Tvrtko Ursulin | d136dfe | 2015-03-03 14:22:31 +0000 | [diff] [blame] | 13806 | const struct drm_plane_state *new_state) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13807 | { |
| 13808 | struct drm_device *dev = plane->dev; |
Maarten Lankhorst | 844f911 | 2015-09-02 10:42:40 +0200 | [diff] [blame] | 13809 | struct drm_framebuffer *fb = new_state->fb; |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13810 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13811 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13812 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13813 | int ret = 0; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13814 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13815 | if (!obj && !old_obj) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13816 | return 0; |
| 13817 | |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13818 | if (old_obj) { |
| 13819 | struct drm_crtc_state *crtc_state = |
| 13820 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); |
| 13821 | |
| 13822 | /* Big Hammer, we also need to ensure that any pending |
| 13823 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 13824 | * current scanout is retired before unpinning the old |
| 13825 | * framebuffer. Note that we rely on userspace rendering |
| 13826 | * into the buffer attached to the pipe they are waiting |
| 13827 | * on. If not, userspace generates a GPU hang with IPEHR |
| 13828 | * point to the MI_WAIT_FOR_EVENT. |
| 13829 | * |
| 13830 | * This should only fail upon a hung GPU, in which case we |
| 13831 | * can safely continue. |
| 13832 | */ |
| 13833 | if (needs_modeset(crtc_state)) |
| 13834 | ret = i915_gem_object_wait_rendering(old_obj, true); |
| 13835 | |
| 13836 | /* Swallow -EIO errors to allow updates during hw lockup. */ |
| 13837 | if (ret && ret != -EIO) |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13838 | return ret; |
Maarten Lankhorst | 5008e87 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13839 | } |
| 13840 | |
Alex Goins | 3c28ff2 | 2015-11-25 18:43:39 -0800 | [diff] [blame] | 13841 | /* For framebuffer backed by dmabuf, wait for fence */ |
| 13842 | if (obj && obj->base.dma_buf) { |
| 13843 | ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, |
| 13844 | false, true, |
| 13845 | MAX_SCHEDULE_TIMEOUT); |
| 13846 | if (ret == -ERESTARTSYS) |
| 13847 | return ret; |
| 13848 | |
| 13849 | WARN_ON(ret < 0); |
| 13850 | } |
| 13851 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13852 | if (!obj) { |
| 13853 | ret = 0; |
| 13854 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13855 | INTEL_INFO(dev)->cursor_needs_physical) { |
| 13856 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
| 13857 | ret = i915_gem_object_attach_phys(obj, align); |
| 13858 | if (ret) |
| 13859 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
| 13860 | } else { |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13861 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13862 | } |
| 13863 | |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13864 | if (ret == 0) { |
| 13865 | if (obj) { |
| 13866 | struct intel_plane_state *plane_state = |
| 13867 | to_intel_plane_state(new_state); |
| 13868 | |
| 13869 | i915_gem_request_assign(&plane_state->wait_req, |
| 13870 | obj->last_write_req); |
| 13871 | } |
| 13872 | |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 13873 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13874 | } |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13875 | |
Matt Roper | 6beb8c23 | 2014-12-01 15:40:14 -0800 | [diff] [blame] | 13876 | return ret; |
| 13877 | } |
| 13878 | |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 13879 | /** |
| 13880 | * intel_cleanup_plane_fb - Cleans up an fb after plane use |
| 13881 | * @plane: drm plane to clean up for |
| 13882 | * @fb: old framebuffer that was on plane |
| 13883 | * |
| 13884 | * Cleans up a framebuffer that has just been removed from a plane. |
Maarten Lankhorst | f935675 | 2015-08-18 13:40:05 +0200 | [diff] [blame] | 13885 | * |
| 13886 | * Must be called with struct_mutex held. |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 13887 | */ |
| 13888 | void |
| 13889 | intel_cleanup_plane_fb(struct drm_plane *plane, |
Tvrtko Ursulin | d136dfe | 2015-03-03 14:22:31 +0000 | [diff] [blame] | 13890 | const struct drm_plane_state *old_state) |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 13891 | { |
| 13892 | struct drm_device *dev = plane->dev; |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13893 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13894 | struct intel_plane_state *old_intel_state; |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13895 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
| 13896 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 13897 | |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13898 | old_intel_state = to_intel_plane_state(old_state); |
| 13899 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13900 | if (!obj && !old_obj) |
Matt Roper | 38f3ce3 | 2014-12-02 07:45:25 -0800 | [diff] [blame] | 13901 | return; |
| 13902 | |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13903 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
| 13904 | !INTEL_INFO(dev)->cursor_needs_physical)) |
Maarten Lankhorst | 844f911 | 2015-09-02 10:42:40 +0200 | [diff] [blame] | 13905 | intel_unpin_fb_obj(old_state->fb, old_state); |
Maarten Lankhorst | 1ee4939 | 2015-09-23 13:27:08 +0200 | [diff] [blame] | 13906 | |
| 13907 | /* prepare_fb aborted? */ |
| 13908 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || |
| 13909 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) |
| 13910 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 13911 | |
| 13912 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
| 13913 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13914 | } |
| 13915 | |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 13916 | int |
| 13917 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) |
| 13918 | { |
| 13919 | int max_scale; |
| 13920 | struct drm_device *dev; |
| 13921 | struct drm_i915_private *dev_priv; |
| 13922 | int crtc_clock, cdclk; |
| 13923 | |
Maarten Lankhorst | bf8a0af | 2015-11-24 11:29:02 +0100 | [diff] [blame] | 13924 | if (!intel_crtc || !crtc_state->base.enable) |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 13925 | return DRM_PLANE_HELPER_NO_SCALING; |
| 13926 | |
| 13927 | dev = intel_crtc->base.dev; |
| 13928 | dev_priv = dev->dev_private; |
| 13929 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 13930 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 13931 | |
Tvrtko Ursulin | 54bf1ce | 2015-10-20 17:17:07 +0100 | [diff] [blame] | 13932 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 13933 | return DRM_PLANE_HELPER_NO_SCALING; |
| 13934 | |
| 13935 | /* |
| 13936 | * skl max scale is lower of: |
| 13937 | * close to 3 but not 3, -1 is for that purpose |
| 13938 | * or |
| 13939 | * cdclk/crtc_clock |
| 13940 | */ |
| 13941 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); |
| 13942 | |
| 13943 | return max_scale; |
| 13944 | } |
| 13945 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13946 | static int |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 13947 | intel_check_primary_plane(struct drm_plane *plane, |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 13948 | struct intel_crtc_state *crtc_state, |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 13949 | struct intel_plane_state *state) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13950 | { |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 13951 | struct drm_crtc *crtc = state->base.crtc; |
| 13952 | struct drm_framebuffer *fb = state->base.fb; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 13953 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 13954 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
| 13955 | bool can_position = false; |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 13956 | |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 13957 | /* use scaler when colorkey is not required */ |
| 13958 | if (INTEL_INFO(plane->dev)->gen >= 9 && |
Maarten Lankhorst | 818ed96 | 2015-06-15 12:33:54 +0200 | [diff] [blame] | 13959 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 13960 | min_scale = 1; |
| 13961 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); |
Sonika Jindal | d810636 | 2015-04-10 14:37:28 +0530 | [diff] [blame] | 13962 | can_position = true; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 13963 | } |
Sonika Jindal | d810636 | 2015-04-10 14:37:28 +0530 | [diff] [blame] | 13964 | |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 13965 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
| 13966 | &state->dst, &state->clip, |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 13967 | min_scale, max_scale, |
| 13968 | can_position, true, |
| 13969 | &state->visible); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 13970 | } |
| 13971 | |
Gustavo Padovan | 14af293 | 2014-10-24 14:51:31 +0100 | [diff] [blame] | 13972 | static void |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 13973 | intel_commit_primary_plane(struct drm_plane *plane, |
| 13974 | struct intel_plane_state *state) |
| 13975 | { |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 13976 | struct drm_crtc *crtc = state->base.crtc; |
| 13977 | struct drm_framebuffer *fb = state->base.fb; |
| 13978 | struct drm_device *dev = plane->dev; |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 13979 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 13980 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 13981 | crtc = crtc ? crtc : plane->crtc; |
Gustavo Padovan | ccc759dc | 2014-09-24 14:20:22 -0300 | [diff] [blame] | 13982 | |
Maarten Lankhorst | d4b0863 | 2015-09-10 16:07:56 +0200 | [diff] [blame] | 13983 | dev_priv->display.update_primary_plane(crtc, fb, |
| 13984 | state->src.x1 >> 16, |
| 13985 | state->src.y1 >> 16); |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 13986 | } |
Gustavo Padovan | ccc759dc | 2014-09-24 14:20:22 -0300 | [diff] [blame] | 13987 | |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 13988 | static void |
| 13989 | intel_disable_primary_plane(struct drm_plane *plane, |
Maarten Lankhorst | 7fabf5e | 2015-06-15 12:33:47 +0200 | [diff] [blame] | 13990 | struct drm_crtc *crtc) |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 13991 | { |
| 13992 | struct drm_device *dev = plane->dev; |
| 13993 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13994 | |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 13995 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
| 13996 | } |
| 13997 | |
Maarten Lankhorst | 613d2b2 | 2015-07-21 13:28:58 +0200 | [diff] [blame] | 13998 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
| 13999 | struct drm_crtc_state *old_crtc_state) |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 14000 | { |
| 14001 | struct drm_device *dev = crtc->dev; |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 14002 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 14003 | struct intel_crtc_state *old_intel_state = |
| 14004 | to_intel_crtc_state(old_crtc_state); |
| 14005 | bool modeset = needs_modeset(crtc->state); |
Gustavo Padovan | ccc759dc | 2014-09-24 14:20:22 -0300 | [diff] [blame] | 14006 | |
Matt Roper | c34c9ee | 2014-12-23 10:41:50 -0800 | [diff] [blame] | 14007 | /* Perform vblank evasion around commit operation */ |
Maarten Lankhorst | 6285262 | 2015-09-23 16:29:38 +0200 | [diff] [blame] | 14008 | intel_pipe_update_start(intel_crtc); |
Maarten Lankhorst | 0583236 | 2015-06-15 12:33:48 +0200 | [diff] [blame] | 14009 | |
Maarten Lankhorst | bfd16b2 | 2015-08-27 15:44:05 +0200 | [diff] [blame] | 14010 | if (modeset) |
| 14011 | return; |
| 14012 | |
| 14013 | if (to_intel_crtc_state(crtc->state)->update_pipe) |
| 14014 | intel_update_pipe_config(intel_crtc, old_intel_state); |
| 14015 | else if (INTEL_INFO(dev)->gen >= 9) |
Maarten Lankhorst | 0583236 | 2015-06-15 12:33:48 +0200 | [diff] [blame] | 14016 | skl_detach_scalers(intel_crtc); |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 14017 | } |
| 14018 | |
Maarten Lankhorst | 613d2b2 | 2015-07-21 13:28:58 +0200 | [diff] [blame] | 14019 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
| 14020 | struct drm_crtc_state *old_crtc_state) |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 14021 | { |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 14022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 14023 | |
Maarten Lankhorst | 6285262 | 2015-09-23 16:29:38 +0200 | [diff] [blame] | 14024 | intel_pipe_update_end(intel_crtc); |
Gustavo Padovan | 3c692a4 | 2014-09-05 17:04:49 -0300 | [diff] [blame] | 14025 | } |
| 14026 | |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 14027 | /** |
Matt Roper | 4a3b876 | 2014-12-23 10:41:51 -0800 | [diff] [blame] | 14028 | * intel_plane_destroy - destroy a plane |
| 14029 | * @plane: plane to destroy |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 14030 | * |
Matt Roper | 4a3b876 | 2014-12-23 10:41:51 -0800 | [diff] [blame] | 14031 | * Common destruction function for all types of planes (primary, cursor, |
| 14032 | * sprite). |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 14033 | */ |
Matt Roper | 4a3b876 | 2014-12-23 10:41:51 -0800 | [diff] [blame] | 14034 | void intel_plane_destroy(struct drm_plane *plane) |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14035 | { |
| 14036 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 14037 | drm_plane_cleanup(plane); |
| 14038 | kfree(intel_plane); |
| 14039 | } |
| 14040 | |
Matt Roper | 65a3fea | 2015-01-21 16:35:42 -0800 | [diff] [blame] | 14041 | const struct drm_plane_funcs intel_plane_funcs = { |
Matt Roper | 70a101f | 2015-04-08 18:56:53 -0700 | [diff] [blame] | 14042 | .update_plane = drm_atomic_helper_update_plane, |
| 14043 | .disable_plane = drm_atomic_helper_disable_plane, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14044 | .destroy = intel_plane_destroy, |
Matt Roper | c196e1d | 2015-01-21 16:35:48 -0800 | [diff] [blame] | 14045 | .set_property = drm_atomic_helper_plane_set_property, |
Matt Roper | a98b343 | 2015-01-21 16:35:43 -0800 | [diff] [blame] | 14046 | .atomic_get_property = intel_plane_atomic_get_property, |
| 14047 | .atomic_set_property = intel_plane_atomic_set_property, |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14048 | .atomic_duplicate_state = intel_plane_duplicate_state, |
| 14049 | .atomic_destroy_state = intel_plane_destroy_state, |
| 14050 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14051 | }; |
| 14052 | |
| 14053 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
| 14054 | int pipe) |
| 14055 | { |
| 14056 | struct intel_plane *primary; |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14057 | struct intel_plane_state *state; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14058 | const uint32_t *intel_primary_formats; |
Thierry Reding | 45e3743 | 2015-08-12 16:54:28 +0200 | [diff] [blame] | 14059 | unsigned int num_formats; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14060 | |
| 14061 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
| 14062 | if (primary == NULL) |
| 14063 | return NULL; |
| 14064 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14065 | state = intel_create_plane_state(&primary->base); |
| 14066 | if (!state) { |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14067 | kfree(primary); |
| 14068 | return NULL; |
| 14069 | } |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14070 | primary->base.state = &state->base; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14071 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14072 | primary->can_scale = false; |
| 14073 | primary->max_downscale = 1; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14074 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14075 | primary->can_scale = true; |
Chandra Konduru | af99ced | 2015-05-11 14:35:47 -0700 | [diff] [blame] | 14076 | state->scaler_id = -1; |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 14077 | } |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14078 | primary->pipe = pipe; |
| 14079 | primary->plane = pipe; |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 14080 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
Matt Roper | c59cb17 | 2014-12-01 15:40:16 -0800 | [diff] [blame] | 14081 | primary->check_plane = intel_check_primary_plane; |
| 14082 | primary->commit_plane = intel_commit_primary_plane; |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 14083 | primary->disable_plane = intel_disable_primary_plane; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14084 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
| 14085 | primary->plane = !pipe; |
| 14086 | |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 14087 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14088 | intel_primary_formats = skl_primary_formats; |
| 14089 | num_formats = ARRAY_SIZE(skl_primary_formats); |
| 14090 | } else if (INTEL_INFO(dev)->gen >= 4) { |
Damien Lespiau | 568db4f | 2015-05-12 16:13:18 +0100 | [diff] [blame] | 14091 | intel_primary_formats = i965_primary_formats; |
| 14092 | num_formats = ARRAY_SIZE(i965_primary_formats); |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 14093 | } else { |
| 14094 | intel_primary_formats = i8xx_primary_formats; |
| 14095 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14096 | } |
| 14097 | |
| 14098 | drm_universal_plane_init(dev, &primary->base, 0, |
Matt Roper | 65a3fea | 2015-01-21 16:35:42 -0800 | [diff] [blame] | 14099 | &intel_plane_funcs, |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14100 | intel_primary_formats, num_formats, |
| 14101 | DRM_PLANE_TYPE_PRIMARY); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 14102 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 14103 | if (INTEL_INFO(dev)->gen >= 4) |
| 14104 | intel_create_rotation_property(dev, primary); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 14105 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14106 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
| 14107 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14108 | return &primary->base; |
| 14109 | } |
| 14110 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 14111 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
| 14112 | { |
| 14113 | if (!dev->mode_config.rotation_property) { |
| 14114 | unsigned long flags = BIT(DRM_ROTATE_0) | |
| 14115 | BIT(DRM_ROTATE_180); |
| 14116 | |
| 14117 | if (INTEL_INFO(dev)->gen >= 9) |
| 14118 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); |
| 14119 | |
| 14120 | dev->mode_config.rotation_property = |
| 14121 | drm_mode_create_rotation_property(dev, flags); |
| 14122 | } |
| 14123 | if (dev->mode_config.rotation_property) |
| 14124 | drm_object_attach_property(&plane->base.base, |
| 14125 | dev->mode_config.rotation_property, |
| 14126 | plane->base.state->rotation); |
| 14127 | } |
| 14128 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14129 | static int |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14130 | intel_check_cursor_plane(struct drm_plane *plane, |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14131 | struct intel_crtc_state *crtc_state, |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14132 | struct intel_plane_state *state) |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14133 | { |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14134 | struct drm_crtc *crtc = crtc_state->base.crtc; |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 14135 | struct drm_framebuffer *fb = state->base.fb; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14136 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Ville Syrjälä | b29ec92 | 2015-12-18 19:24:39 +0200 | [diff] [blame] | 14137 | enum pipe pipe = to_intel_plane(plane)->pipe; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14138 | unsigned stride; |
| 14139 | int ret; |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14140 | |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14141 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
| 14142 | &state->dst, &state->clip, |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14143 | DRM_PLANE_HELPER_NO_SCALING, |
| 14144 | DRM_PLANE_HELPER_NO_SCALING, |
| 14145 | true, true, &state->visible); |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14146 | if (ret) |
| 14147 | return ret; |
| 14148 | |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14149 | /* if we want to turn off the cursor ignore width and height */ |
| 14150 | if (!obj) |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 14151 | return 0; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14152 | |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14153 | /* Check for which cursor types we support */ |
Maarten Lankhorst | 061e4b8 | 2015-06-15 12:33:46 +0200 | [diff] [blame] | 14154 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14155 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
| 14156 | state->base.crtc_w, state->base.crtc_h); |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14157 | return -EINVAL; |
| 14158 | } |
| 14159 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14160 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
| 14161 | if (obj->base.size < stride * state->base.crtc_h) { |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14162 | DRM_DEBUG_KMS("buffer is too small\n"); |
| 14163 | return -ENOMEM; |
| 14164 | } |
| 14165 | |
Ville Syrjälä | 3a656b5 | 2015-03-09 21:08:37 +0200 | [diff] [blame] | 14166 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14167 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 14168 | return -EINVAL; |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14169 | } |
Gustavo Padovan | 757f9a3 | 2014-09-24 14:20:24 -0300 | [diff] [blame] | 14170 | |
Ville Syrjälä | b29ec92 | 2015-12-18 19:24:39 +0200 | [diff] [blame] | 14171 | /* |
| 14172 | * There's something wrong with the cursor on CHV pipe C. |
| 14173 | * If it straddles the left edge of the screen then |
| 14174 | * moving it away from the edge or disabling it often |
| 14175 | * results in a pipe underrun, and often that can lead to |
| 14176 | * dead pipe (constant underrun reported, and it scans |
| 14177 | * out just a solid color). To recover from that, the |
| 14178 | * display power well must be turned off and on again. |
| 14179 | * Refuse the put the cursor into that compromised position. |
| 14180 | */ |
| 14181 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && |
| 14182 | state->visible && state->base.crtc_x < 0) { |
| 14183 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
| 14184 | return -EINVAL; |
| 14185 | } |
| 14186 | |
Maarten Lankhorst | da20eab | 2015-06-15 12:33:44 +0200 | [diff] [blame] | 14187 | return 0; |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14188 | } |
| 14189 | |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 14190 | static void |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 14191 | intel_disable_cursor_plane(struct drm_plane *plane, |
Maarten Lankhorst | 7fabf5e | 2015-06-15 12:33:47 +0200 | [diff] [blame] | 14192 | struct drm_crtc *crtc) |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 14193 | { |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 14194 | intel_crtc_update_cursor(crtc, false); |
| 14195 | } |
| 14196 | |
| 14197 | static void |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14198 | intel_commit_cursor_plane(struct drm_plane *plane, |
| 14199 | struct intel_plane_state *state) |
| 14200 | { |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 14201 | struct drm_crtc *crtc = state->base.crtc; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14202 | struct drm_device *dev = plane->dev; |
| 14203 | struct intel_crtc *intel_crtc; |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 14204 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14205 | uint32_t addr; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14206 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14207 | crtc = crtc ? crtc : plane->crtc; |
| 14208 | intel_crtc = to_intel_crtc(crtc); |
Sonika Jindal | a919db9 | 2014-10-23 07:41:33 -0700 | [diff] [blame] | 14209 | |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 14210 | if (!obj) |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14211 | addr = 0; |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 14212 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14213 | addr = i915_gem_obj_ggtt_offset(obj); |
Matt Roper | f4a2cf2 | 2014-12-01 15:40:12 -0800 | [diff] [blame] | 14214 | else |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14215 | addr = obj->phys_handle->busaddr; |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14216 | |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14217 | intel_crtc->cursor_addr = addr; |
Gustavo Padovan | a912f12 | 2014-12-01 15:40:10 -0800 | [diff] [blame] | 14218 | |
Maarten Lankhorst | 6285262 | 2015-09-23 16:29:38 +0200 | [diff] [blame] | 14219 | intel_crtc_update_cursor(crtc, state->visible); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14220 | } |
Gustavo Padovan | 852e787 | 2014-09-05 17:22:31 -0300 | [diff] [blame] | 14221 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14222 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
| 14223 | int pipe) |
| 14224 | { |
| 14225 | struct intel_plane *cursor; |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14226 | struct intel_plane_state *state; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14227 | |
| 14228 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
| 14229 | if (cursor == NULL) |
| 14230 | return NULL; |
| 14231 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14232 | state = intel_create_plane_state(&cursor->base); |
| 14233 | if (!state) { |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14234 | kfree(cursor); |
| 14235 | return NULL; |
| 14236 | } |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14237 | cursor->base.state = &state->base; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14238 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14239 | cursor->can_scale = false; |
| 14240 | cursor->max_downscale = 1; |
| 14241 | cursor->pipe = pipe; |
| 14242 | cursor->plane = pipe; |
Ville Syrjälä | a9ff871 | 2015-06-24 21:59:34 +0300 | [diff] [blame] | 14243 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
Matt Roper | c59cb17 | 2014-12-01 15:40:16 -0800 | [diff] [blame] | 14244 | cursor->check_plane = intel_check_cursor_plane; |
| 14245 | cursor->commit_plane = intel_commit_cursor_plane; |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 14246 | cursor->disable_plane = intel_disable_cursor_plane; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14247 | |
| 14248 | drm_universal_plane_init(dev, &cursor->base, 0, |
Matt Roper | 65a3fea | 2015-01-21 16:35:42 -0800 | [diff] [blame] | 14249 | &intel_plane_funcs, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14250 | intel_cursor_formats, |
| 14251 | ARRAY_SIZE(intel_cursor_formats), |
| 14252 | DRM_PLANE_TYPE_CURSOR); |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 14253 | |
| 14254 | if (INTEL_INFO(dev)->gen >= 4) { |
| 14255 | if (!dev->mode_config.rotation_property) |
| 14256 | dev->mode_config.rotation_property = |
| 14257 | drm_mode_create_rotation_property(dev, |
| 14258 | BIT(DRM_ROTATE_0) | |
| 14259 | BIT(DRM_ROTATE_180)); |
| 14260 | if (dev->mode_config.rotation_property) |
| 14261 | drm_object_attach_property(&cursor->base.base, |
| 14262 | dev->mode_config.rotation_property, |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 14263 | state->base.rotation); |
Ville Syrjälä | 4398ad4 | 2014-10-23 07:41:34 -0700 | [diff] [blame] | 14264 | } |
| 14265 | |
Chandra Konduru | af99ced | 2015-05-11 14:35:47 -0700 | [diff] [blame] | 14266 | if (INTEL_INFO(dev)->gen >=9) |
| 14267 | state->scaler_id = -1; |
| 14268 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 14269 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
| 14270 | |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14271 | return &cursor->base; |
| 14272 | } |
| 14273 | |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 14274 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
| 14275 | struct intel_crtc_state *crtc_state) |
| 14276 | { |
| 14277 | int i; |
| 14278 | struct intel_scaler *intel_scaler; |
| 14279 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; |
| 14280 | |
| 14281 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
| 14282 | intel_scaler = &scaler_state->scalers[i]; |
| 14283 | intel_scaler->in_use = 0; |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 14284 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
| 14285 | } |
| 14286 | |
| 14287 | scaler_state->scaler_id = -1; |
| 14288 | } |
| 14289 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 14290 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14291 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 14292 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14293 | struct intel_crtc *intel_crtc; |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 14294 | struct intel_crtc_state *crtc_state = NULL; |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14295 | struct drm_plane *primary = NULL; |
| 14296 | struct drm_plane *cursor = NULL; |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14297 | int i, ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14298 | |
Daniel Vetter | 955382f | 2013-09-19 14:05:45 +0200 | [diff] [blame] | 14299 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14300 | if (intel_crtc == NULL) |
| 14301 | return; |
| 14302 | |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 14303 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
| 14304 | if (!crtc_state) |
| 14305 | goto fail; |
Ander Conselvan de Oliveira | 550acef | 2015-04-21 17:13:24 +0300 | [diff] [blame] | 14306 | intel_crtc->config = crtc_state; |
| 14307 | intel_crtc->base.state = &crtc_state->base; |
Matt Roper | 0787824 | 2015-02-25 11:43:26 -0800 | [diff] [blame] | 14308 | crtc_state->base.crtc = &intel_crtc->base; |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 14309 | |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 14310 | /* initialize shared scalers */ |
| 14311 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14312 | if (pipe == PIPE_C) |
| 14313 | intel_crtc->num_scalers = 1; |
| 14314 | else |
| 14315 | intel_crtc->num_scalers = SKL_NUM_SCALERS; |
| 14316 | |
| 14317 | skl_init_scalers(dev, intel_crtc, crtc_state); |
| 14318 | } |
| 14319 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14320 | primary = intel_primary_plane_create(dev, pipe); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14321 | if (!primary) |
| 14322 | goto fail; |
| 14323 | |
| 14324 | cursor = intel_cursor_plane_create(dev, pipe); |
| 14325 | if (!cursor) |
| 14326 | goto fail; |
| 14327 | |
Matt Roper | 465c120 | 2014-05-29 08:06:54 -0700 | [diff] [blame] | 14328 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14329 | cursor, &intel_crtc_funcs); |
| 14330 | if (ret) |
| 14331 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14332 | |
| 14333 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14334 | for (i = 0; i < 256; i++) { |
| 14335 | intel_crtc->lut_r[i] = i; |
| 14336 | intel_crtc->lut_g[i] = i; |
| 14337 | intel_crtc->lut_b[i] = i; |
| 14338 | } |
| 14339 | |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 14340 | /* |
| 14341 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
Daniel Vetter | 8c0f92e | 2014-06-16 02:08:26 +0200 | [diff] [blame] | 14342 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 14343 | */ |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 14344 | intel_crtc->pipe = pipe; |
| 14345 | intel_crtc->plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 14346 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 14347 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 14348 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 14349 | } |
| 14350 | |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 14351 | intel_crtc->cursor_base = ~0; |
| 14352 | intel_crtc->cursor_cntl = ~0; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 14353 | intel_crtc->cursor_size = ~0; |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 14354 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 14355 | intel_crtc->wm.cxsr_allowed = true; |
| 14356 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 14357 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 14358 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 14359 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 14360 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 14361 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14362 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
Daniel Vetter | 87b6b10 | 2014-05-15 15:33:46 +0200 | [diff] [blame] | 14363 | |
| 14364 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14365 | return; |
| 14366 | |
| 14367 | fail: |
| 14368 | if (primary) |
| 14369 | drm_plane_cleanup(primary); |
| 14370 | if (cursor) |
| 14371 | drm_plane_cleanup(cursor); |
Ander Conselvan de Oliveira | f5de6e0 | 2015-01-15 14:55:26 +0200 | [diff] [blame] | 14372 | kfree(crtc_state); |
Matt Roper | 3d7d651 | 2014-06-10 08:28:13 -0700 | [diff] [blame] | 14373 | kfree(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14374 | } |
| 14375 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 14376 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
| 14377 | { |
| 14378 | struct drm_encoder *encoder = connector->base.encoder; |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 14379 | struct drm_device *dev = connector->base.dev; |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 14380 | |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 14381 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 14382 | |
Ville Syrjälä | d3babd3 | 2014-11-07 11:16:01 +0200 | [diff] [blame] | 14383 | if (!encoder || WARN_ON(!encoder->crtc)) |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 14384 | return INVALID_PIPE; |
| 14385 | |
| 14386 | return to_intel_crtc(encoder->crtc)->pipe; |
| 14387 | } |
| 14388 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14389 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 14390 | struct drm_file *file) |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14391 | { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14392 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 14393 | struct drm_crtc *drmmode_crtc; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 14394 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14395 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 14396 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14397 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 14398 | if (!drmmode_crtc) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14399 | DRM_ERROR("no such CRTC id\n"); |
Ville Syrjälä | 3f2c205 | 2013-10-17 13:35:03 +0300 | [diff] [blame] | 14400 | return -ENOENT; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14401 | } |
| 14402 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 14403 | crtc = to_intel_crtc(drmmode_crtc); |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 14404 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14405 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 14406 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 14407 | } |
| 14408 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 14409 | static int intel_encoder_clones(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14410 | { |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 14411 | struct drm_device *dev = encoder->base.dev; |
| 14412 | struct intel_encoder *source_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14413 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14414 | int entry = 0; |
| 14415 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 14416 | for_each_intel_encoder(dev, source_encoder) { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 14417 | if (encoders_cloneable(encoder, source_encoder)) |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 14418 | index_mask |= (1 << entry); |
| 14419 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14420 | entry++; |
| 14421 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 14422 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14423 | return index_mask; |
| 14424 | } |
| 14425 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 14426 | static bool has_edp_a(struct drm_device *dev) |
| 14427 | { |
| 14428 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14429 | |
| 14430 | if (!IS_MOBILE(dev)) |
| 14431 | return false; |
| 14432 | |
| 14433 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 14434 | return false; |
| 14435 | |
Damien Lespiau | e358990 | 2014-02-07 19:12:50 +0000 | [diff] [blame] | 14436 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 14437 | return false; |
| 14438 | |
| 14439 | return true; |
| 14440 | } |
| 14441 | |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 14442 | static bool intel_crt_present(struct drm_device *dev) |
| 14443 | { |
| 14444 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14445 | |
Damien Lespiau | 884497e | 2013-12-03 13:56:23 +0000 | [diff] [blame] | 14446 | if (INTEL_INFO(dev)->gen >= 9) |
| 14447 | return false; |
| 14448 | |
Damien Lespiau | cf404ce | 2014-10-01 20:04:15 +0100 | [diff] [blame] | 14449 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 14450 | return false; |
| 14451 | |
| 14452 | if (IS_CHERRYVIEW(dev)) |
| 14453 | return false; |
| 14454 | |
Ville Syrjälä | 65e472e | 2015-12-01 23:28:55 +0200 | [diff] [blame] | 14455 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
| 14456 | return false; |
| 14457 | |
Ville Syrjälä | 70ac54d | 2015-12-01 23:29:56 +0200 | [diff] [blame] | 14458 | /* DDI E can't be used if DDI A requires 4 lanes */ |
| 14459 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
| 14460 | return false; |
| 14461 | |
Ville Syrjälä | e4abb73 | 2015-12-01 23:31:33 +0200 | [diff] [blame] | 14462 | if (!dev_priv->vbt.int_crt_support) |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 14463 | return false; |
| 14464 | |
| 14465 | return true; |
| 14466 | } |
| 14467 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14468 | static void intel_setup_outputs(struct drm_device *dev) |
| 14469 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 14470 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 14471 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 14472 | bool dpd_is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14473 | |
Daniel Vetter | c909335 | 2013-06-06 22:22:47 +0200 | [diff] [blame] | 14474 | intel_lvds_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14475 | |
Jesse Barnes | 84b4e04 | 2014-06-25 08:24:29 -0700 | [diff] [blame] | 14476 | if (intel_crt_present(dev)) |
Paulo Zanoni | 79935fc | 2012-11-20 13:27:40 -0200 | [diff] [blame] | 14477 | intel_crt_init(dev); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 14478 | |
Vandana Kannan | c776eb2 | 2014-08-19 12:05:01 +0530 | [diff] [blame] | 14479 | if (IS_BROXTON(dev)) { |
| 14480 | /* |
| 14481 | * FIXME: Broxton doesn't support port detection via the |
| 14482 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to |
| 14483 | * detect the ports. |
| 14484 | */ |
| 14485 | intel_ddi_init(dev, PORT_A); |
| 14486 | intel_ddi_init(dev, PORT_B); |
| 14487 | intel_ddi_init(dev, PORT_C); |
| 14488 | } else if (HAS_DDI(dev)) { |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 14489 | int found; |
| 14490 | |
Jesse Barnes | de31fac | 2015-03-06 15:53:32 -0800 | [diff] [blame] | 14491 | /* |
| 14492 | * Haswell uses DDI functions to detect digital outputs. |
| 14493 | * On SKL pre-D0 the strap isn't connected, so we assume |
| 14494 | * it's there. |
| 14495 | */ |
Ville Syrjälä | 7717940 | 2015-09-18 20:03:35 +0300 | [diff] [blame] | 14496 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
Jesse Barnes | de31fac | 2015-03-06 15:53:32 -0800 | [diff] [blame] | 14497 | /* WaIgnoreDDIAStrap: skl */ |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 14498 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 14499 | intel_ddi_init(dev, PORT_A); |
| 14500 | |
| 14501 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
| 14502 | * register */ |
| 14503 | found = I915_READ(SFUSE_STRAP); |
| 14504 | |
| 14505 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
| 14506 | intel_ddi_init(dev, PORT_B); |
| 14507 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
| 14508 | intel_ddi_init(dev, PORT_C); |
| 14509 | if (found & SFUSE_STRAP_DDID_DETECTED) |
| 14510 | intel_ddi_init(dev, PORT_D); |
Rodrigo Vivi | 2800e4c | 2015-08-07 17:35:21 -0700 | [diff] [blame] | 14511 | /* |
| 14512 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. |
| 14513 | */ |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 14514 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
Rodrigo Vivi | 2800e4c | 2015-08-07 17:35:21 -0700 | [diff] [blame] | 14515 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
| 14516 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || |
| 14517 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) |
| 14518 | intel_ddi_init(dev, PORT_E); |
| 14519 | |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 14520 | } else if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 14521 | int found; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 14522 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 14523 | |
| 14524 | if (has_edp_a(dev)) |
| 14525 | intel_dp_init(dev, DP_A, PORT_A); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 14526 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 14527 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 14528 | /* PCH SDVOB multiplex with HDMIB */ |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 14529 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 14530 | if (!found) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14531 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 14532 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 14533 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 14534 | } |
| 14535 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 14536 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14537 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 14538 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 14539 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14540 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 14541 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 14542 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 14543 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 14544 | |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 14545 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 14546 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 14547 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e17ac6d | 2014-10-09 19:37:15 +0300 | [diff] [blame] | 14548 | /* |
| 14549 | * The DP_DETECTED bit is the latched state of the DDC |
| 14550 | * SDA pin at boot. However since eDP doesn't require DDC |
| 14551 | * (no way to plug in a DP->HDMI dongle) the DDC pins for |
| 14552 | * eDP ports may have been muxed to an alternate function. |
| 14553 | * Thus we can't rely on the DP_DETECTED bit alone to detect |
| 14554 | * eDP ports. Consult the VBT as well as DP_DETECTED to |
| 14555 | * detect eDP ports. |
| 14556 | */ |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14557 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
Ville Syrjälä | d2182a6 | 2015-01-09 14:21:14 +0200 | [diff] [blame] | 14558 | !intel_dp_is_edp(dev, PORT_B)) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14559 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
| 14560 | if (I915_READ(VLV_DP_B) & DP_DETECTED || |
Ville Syrjälä | e17ac6d | 2014-10-09 19:37:15 +0300 | [diff] [blame] | 14561 | intel_dp_is_edp(dev, PORT_B)) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14562 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
Artem Bityutskiy | 585a94b | 2013-10-16 18:10:41 +0300 | [diff] [blame] | 14563 | |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14564 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
Ville Syrjälä | d2182a6 | 2015-01-09 14:21:14 +0200 | [diff] [blame] | 14565 | !intel_dp_is_edp(dev, PORT_C)) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14566 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
| 14567 | if (I915_READ(VLV_DP_C) & DP_DETECTED || |
Ville Syrjälä | e17ac6d | 2014-10-09 19:37:15 +0300 | [diff] [blame] | 14568 | intel_dp_is_edp(dev, PORT_C)) |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14569 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 14570 | |
Ville Syrjälä | 9418c1f | 2014-04-09 13:28:56 +0300 | [diff] [blame] | 14571 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e17ac6d | 2014-10-09 19:37:15 +0300 | [diff] [blame] | 14572 | /* eDP not supported on port D, so don't check VBT */ |
Ville Syrjälä | e66eb81 | 2015-09-18 20:03:34 +0300 | [diff] [blame] | 14573 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
| 14574 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); |
| 14575 | if (I915_READ(CHV_DP_D) & DP_DETECTED) |
| 14576 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
Ville Syrjälä | 9418c1f | 2014-04-09 13:28:56 +0300 | [diff] [blame] | 14577 | } |
| 14578 | |
Jani Nikula | 3cfca97 | 2013-08-27 15:12:26 +0300 | [diff] [blame] | 14579 | intel_dsi_init(dev); |
Daniel Vetter | 09da55d | 2015-07-07 11:44:32 +0200 | [diff] [blame] | 14580 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 14581 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 14582 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14583 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14584 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 14585 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 14586 | if (!found && IS_G4X(dev)) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14587 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14588 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14589 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 14590 | |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 14591 | if (!found && IS_G4X(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 14592 | intel_dp_init(dev, DP_B, PORT_B); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 14593 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 14594 | |
| 14595 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 14596 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14597 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14598 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Ville Syrjälä | 2a5c083 | 2015-11-06 21:29:59 +0200 | [diff] [blame] | 14599 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14600 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 14601 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14602 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 14603 | |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 14604 | if (IS_G4X(dev)) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14605 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 14606 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 14607 | } |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 14608 | if (IS_G4X(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 14609 | intel_dp_init(dev, DP_C, PORT_C); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 14610 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 14611 | |
Daniel Vetter | 3fec3d2 | 2015-07-07 09:10:07 +0200 | [diff] [blame] | 14612 | if (IS_G4X(dev) && |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 14613 | (I915_READ(DP_D) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 14614 | intel_dp_init(dev, DP_D, PORT_D); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 14615 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14616 | intel_dvo_init(dev); |
| 14617 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 14618 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14619 | intel_tv_init(dev); |
| 14620 | |
Rodrigo Vivi | 0bc12bc | 2014-11-14 08:52:28 -0800 | [diff] [blame] | 14621 | intel_psr_init(dev); |
Rodrigo Vivi | 7c8f8a7 | 2014-06-13 05:10:03 -0700 | [diff] [blame] | 14622 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 14623 | for_each_intel_encoder(dev, encoder) { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 14624 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 14625 | encoder->base.possible_clones = |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 14626 | intel_encoder_clones(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14627 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 14628 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 14629 | intel_init_pch_refclk(dev); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 14630 | |
| 14631 | drm_helper_move_panel_connectors_to_head(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14632 | } |
| 14633 | |
| 14634 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 14635 | { |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 14636 | struct drm_device *dev = fb->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14637 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14638 | |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 14639 | drm_framebuffer_cleanup(fb); |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 14640 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 14641 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
Ville Syrjälä | 60a5ca0 | 2014-06-13 11:10:53 +0300 | [diff] [blame] | 14642 | drm_gem_object_unreference(&intel_fb->obj->base); |
| 14643 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14644 | kfree(intel_fb); |
| 14645 | } |
| 14646 | |
| 14647 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 14648 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14649 | unsigned int *handle) |
| 14650 | { |
| 14651 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 14652 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14653 | |
Chris Wilson | cc917ab | 2015-10-13 14:22:26 +0100 | [diff] [blame] | 14654 | if (obj->userptr.mm) { |
| 14655 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); |
| 14656 | return -EINVAL; |
| 14657 | } |
| 14658 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 14659 | return drm_gem_handle_create(file, &obj->base, handle); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14660 | } |
| 14661 | |
Rodrigo Vivi | 86c9858 | 2015-07-08 16:22:45 -0700 | [diff] [blame] | 14662 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
| 14663 | struct drm_file *file, |
| 14664 | unsigned flags, unsigned color, |
| 14665 | struct drm_clip_rect *clips, |
| 14666 | unsigned num_clips) |
| 14667 | { |
| 14668 | struct drm_device *dev = fb->dev; |
| 14669 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 14670 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 14671 | |
| 14672 | mutex_lock(&dev->struct_mutex); |
Paulo Zanoni | 74b4ea1 | 2015-07-14 16:29:14 -0300 | [diff] [blame] | 14673 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
Rodrigo Vivi | 86c9858 | 2015-07-08 16:22:45 -0700 | [diff] [blame] | 14674 | mutex_unlock(&dev->struct_mutex); |
| 14675 | |
| 14676 | return 0; |
| 14677 | } |
| 14678 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14679 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 14680 | .destroy = intel_user_framebuffer_destroy, |
| 14681 | .create_handle = intel_user_framebuffer_create_handle, |
Rodrigo Vivi | 86c9858 | 2015-07-08 16:22:45 -0700 | [diff] [blame] | 14682 | .dirty = intel_user_framebuffer_dirty, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14683 | }; |
| 14684 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 14685 | static |
| 14686 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, |
| 14687 | uint32_t pixel_format) |
| 14688 | { |
| 14689 | u32 gen = INTEL_INFO(dev)->gen; |
| 14690 | |
| 14691 | if (gen >= 9) { |
| 14692 | /* "The stride in bytes must not exceed the of the size of 8K |
| 14693 | * pixels and 32K bytes." |
| 14694 | */ |
| 14695 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 14696 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 14697 | return 32*1024; |
| 14698 | } else if (gen >= 4) { |
| 14699 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
| 14700 | return 16*1024; |
| 14701 | else |
| 14702 | return 32*1024; |
| 14703 | } else if (gen >= 3) { |
| 14704 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
| 14705 | return 8*1024; |
| 14706 | else |
| 14707 | return 16*1024; |
| 14708 | } else { |
| 14709 | /* XXX DSPC is limited to 4k tiled */ |
| 14710 | return 8*1024; |
| 14711 | } |
| 14712 | } |
| 14713 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 14714 | static int intel_framebuffer_init(struct drm_device *dev, |
| 14715 | struct intel_framebuffer *intel_fb, |
| 14716 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 14717 | struct drm_i915_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14718 | { |
Tvrtko Ursulin | 6761dd3 | 2015-03-23 11:10:32 +0000 | [diff] [blame] | 14719 | unsigned int aligned_height; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14720 | int ret; |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 14721 | u32 pitch_limit, stride_alignment; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14722 | |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 14723 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 14724 | |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 14725 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
| 14726 | /* Enforce that fb modifier and tiling mode match, but only for |
| 14727 | * X-tiled. This is needed for FBC. */ |
| 14728 | if (!!(obj->tiling_mode == I915_TILING_X) != |
| 14729 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { |
| 14730 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
| 14731 | return -EINVAL; |
| 14732 | } |
| 14733 | } else { |
| 14734 | if (obj->tiling_mode == I915_TILING_X) |
| 14735 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 14736 | else if (obj->tiling_mode == I915_TILING_Y) { |
| 14737 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
| 14738 | return -EINVAL; |
| 14739 | } |
| 14740 | } |
| 14741 | |
Tvrtko Ursulin | 9a8f0a1 | 2015-02-27 11:15:24 +0000 | [diff] [blame] | 14742 | /* Passed in modifier sanity checking. */ |
| 14743 | switch (mode_cmd->modifier[0]) { |
| 14744 | case I915_FORMAT_MOD_Y_TILED: |
| 14745 | case I915_FORMAT_MOD_Yf_TILED: |
| 14746 | if (INTEL_INFO(dev)->gen < 9) { |
| 14747 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
| 14748 | mode_cmd->modifier[0]); |
| 14749 | return -EINVAL; |
| 14750 | } |
| 14751 | case DRM_FORMAT_MOD_NONE: |
| 14752 | case I915_FORMAT_MOD_X_TILED: |
| 14753 | break; |
| 14754 | default: |
Jesse Barnes | c0f4042 | 2015-03-23 12:43:50 -0700 | [diff] [blame] | 14755 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
| 14756 | mode_cmd->modifier[0]); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 14757 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14758 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 14759 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 14760 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
| 14761 | mode_cmd->pixel_format); |
| 14762 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { |
| 14763 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", |
| 14764 | mode_cmd->pitches[0], stride_alignment); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 14765 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14766 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 14767 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 14768 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
| 14769 | mode_cmd->pixel_format); |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 14770 | if (mode_cmd->pitches[0] > pitch_limit) { |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 14771 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
| 14772 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 14773 | "tiled" : "linear", |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 14774 | mode_cmd->pitches[0], pitch_limit); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 14775 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14776 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 14777 | |
Daniel Vetter | 2a80ead | 2015-02-10 17:16:06 +0000 | [diff] [blame] | 14778 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14779 | mode_cmd->pitches[0] != obj->stride) { |
| 14780 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
| 14781 | mode_cmd->pitches[0], obj->stride); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 14782 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14783 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 14784 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14785 | /* Reject formats not supported by any plane early. */ |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 14786 | switch (mode_cmd->pixel_format) { |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14787 | case DRM_FORMAT_C8: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 14788 | case DRM_FORMAT_RGB565: |
| 14789 | case DRM_FORMAT_XRGB8888: |
| 14790 | case DRM_FORMAT_ARGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14791 | break; |
| 14792 | case DRM_FORMAT_XRGB1555: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14793 | if (INTEL_INFO(dev)->gen > 3) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 14794 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14795 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14796 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14797 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14798 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14799 | case DRM_FORMAT_ABGR8888: |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 14800 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 14801 | INTEL_INFO(dev)->gen < 9) { |
Damien Lespiau | 6c0fd45 | 2015-05-19 12:29:16 +0100 | [diff] [blame] | 14802 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14803 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14804 | return -EINVAL; |
| 14805 | } |
| 14806 | break; |
| 14807 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 14808 | case DRM_FORMAT_XRGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14809 | case DRM_FORMAT_XBGR2101010: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14810 | if (INTEL_INFO(dev)->gen < 4) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 14811 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14812 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14813 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14814 | } |
Jesse Barnes | b562674 | 2011-06-24 12:19:27 -0700 | [diff] [blame] | 14815 | break; |
Damien Lespiau | 7531208 | 2015-05-15 19:06:01 +0100 | [diff] [blame] | 14816 | case DRM_FORMAT_ABGR2101010: |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 14817 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
Damien Lespiau | 7531208 | 2015-05-15 19:06:01 +0100 | [diff] [blame] | 14818 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14819 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14820 | return -EINVAL; |
| 14821 | } |
| 14822 | break; |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 14823 | case DRM_FORMAT_YUYV: |
| 14824 | case DRM_FORMAT_UYVY: |
| 14825 | case DRM_FORMAT_YVYU: |
| 14826 | case DRM_FORMAT_VYUY: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14827 | if (INTEL_INFO(dev)->gen < 5) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 14828 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14829 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 14830 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 14831 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 14832 | break; |
| 14833 | default: |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 14834 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14835 | drm_get_format_name(mode_cmd->pixel_format)); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 14836 | return -EINVAL; |
| 14837 | } |
| 14838 | |
Ville Syrjälä | 90f9a33 | 2012-10-31 17:50:19 +0200 | [diff] [blame] | 14839 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 14840 | if (mode_cmd->offsets[0] != 0) |
| 14841 | return -EINVAL; |
| 14842 | |
Damien Lespiau | ec2c981 | 2015-01-20 12:51:45 +0000 | [diff] [blame] | 14843 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
Daniel Vetter | 091df6c | 2015-02-10 17:16:10 +0000 | [diff] [blame] | 14844 | mode_cmd->pixel_format, |
| 14845 | mode_cmd->modifier[0]); |
Daniel Vetter | 53155c0 | 2013-10-09 21:55:33 +0200 | [diff] [blame] | 14846 | /* FIXME drm helper for size checks (especially planar formats)? */ |
| 14847 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
| 14848 | return -EINVAL; |
| 14849 | |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 14850 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
| 14851 | intel_fb->obj = obj; |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 14852 | intel_fb->obj->framebuffer_references++; |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 14853 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14854 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 14855 | if (ret) { |
| 14856 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 14857 | return ret; |
| 14858 | } |
| 14859 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14860 | return 0; |
| 14861 | } |
| 14862 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14863 | static struct drm_framebuffer * |
| 14864 | intel_user_framebuffer_create(struct drm_device *dev, |
| 14865 | struct drm_file *filp, |
Ville Syrjälä | 1eb83451 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 14866 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14867 | { |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 14868 | struct drm_framebuffer *fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 14869 | struct drm_i915_gem_object *obj; |
Ville Syrjälä | 76dc376 | 2015-11-11 19:11:28 +0200 | [diff] [blame] | 14870 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14871 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 14872 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
Ville Syrjälä | 76dc376 | 2015-11-11 19:11:28 +0200 | [diff] [blame] | 14873 | mode_cmd.handles[0])); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 14874 | if (&obj->base == NULL) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 14875 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14876 | |
Daniel Vetter | 92907cb | 2015-11-23 09:04:05 +0100 | [diff] [blame] | 14877 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
Lukas Wunner | dcb1394 | 2015-07-04 11:50:58 +0200 | [diff] [blame] | 14878 | if (IS_ERR(fb)) |
| 14879 | drm_gem_object_unreference_unlocked(&obj->base); |
| 14880 | |
| 14881 | return fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14882 | } |
| 14883 | |
Daniel Vetter | 0695726 | 2015-08-10 13:34:08 +0200 | [diff] [blame] | 14884 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 14885 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 14886 | { |
| 14887 | } |
| 14888 | #endif |
| 14889 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14890 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14891 | .fb_create = intel_user_framebuffer_create, |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 14892 | .output_poll_changed = intel_fbdev_output_poll_changed, |
Matt Roper | 5ee67f1 | 2015-01-21 16:35:44 -0800 | [diff] [blame] | 14893 | .atomic_check = intel_atomic_check, |
| 14894 | .atomic_commit = intel_atomic_commit, |
Maarten Lankhorst | de419ab | 2015-06-04 10:21:28 +0200 | [diff] [blame] | 14895 | .atomic_state_alloc = intel_atomic_state_alloc, |
| 14896 | .atomic_state_clear = intel_atomic_state_clear, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 14897 | }; |
| 14898 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 14899 | /* Set up chip specific display functions */ |
| 14900 | static void intel_init_display(struct drm_device *dev) |
| 14901 | { |
| 14902 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14903 | |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 14904 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
| 14905 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 14906 | else if (IS_CHERRYVIEW(dev)) |
| 14907 | dev_priv->display.find_dpll = chv_find_best_dpll; |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 14908 | else if (IS_VALLEYVIEW(dev)) |
| 14909 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
| 14910 | else if (IS_PINEVIEW(dev)) |
| 14911 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
| 14912 | else |
| 14913 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
| 14914 | |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 14915 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14916 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 14917 | dev_priv->display.get_initial_plane_config = |
| 14918 | skylake_get_initial_plane_config; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 14919 | dev_priv->display.crtc_compute_clock = |
| 14920 | haswell_crtc_compute_clock; |
| 14921 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 14922 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 14923 | dev_priv->display.update_primary_plane = |
| 14924 | skylake_update_primary_plane; |
| 14925 | } else if (HAS_DDI(dev)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 14926 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 14927 | dev_priv->display.get_initial_plane_config = |
| 14928 | ironlake_get_initial_plane_config; |
Ander Conselvan de Oliveira | 797d025 | 2014-10-29 11:32:34 +0200 | [diff] [blame] | 14929 | dev_priv->display.crtc_compute_clock = |
| 14930 | haswell_crtc_compute_clock; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 14931 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 14932 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
Damien Lespiau | bc8d7df | 2015-01-20 12:51:51 +0000 | [diff] [blame] | 14933 | dev_priv->display.update_primary_plane = |
| 14934 | ironlake_update_primary_plane; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 14935 | } else if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 14936 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 14937 | dev_priv->display.get_initial_plane_config = |
| 14938 | ironlake_get_initial_plane_config; |
Ander Conselvan de Oliveira | 3fb3770 | 2014-10-29 11:32:35 +0200 | [diff] [blame] | 14939 | dev_priv->display.crtc_compute_clock = |
| 14940 | ironlake_crtc_compute_clock; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 14941 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
| 14942 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 14943 | dev_priv->display.update_primary_plane = |
| 14944 | ironlake_update_primary_plane; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 14945 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 14946 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 14947 | dev_priv->display.get_initial_plane_config = |
| 14948 | i9xx_get_initial_plane_config; |
Ander Conselvan de Oliveira | d6dfee7 | 2014-10-29 11:32:36 +0200 | [diff] [blame] | 14949 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 14950 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 14951 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 14952 | dev_priv->display.update_primary_plane = |
| 14953 | i9xx_update_primary_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 14954 | } else { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 14955 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Damien Lespiau | 5724dbd | 2015-01-20 12:51:52 +0000 | [diff] [blame] | 14956 | dev_priv->display.get_initial_plane_config = |
| 14957 | i9xx_get_initial_plane_config; |
Ander Conselvan de Oliveira | d6dfee7 | 2014-10-29 11:32:36 +0200 | [diff] [blame] | 14958 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 14959 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 14960 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 14961 | dev_priv->display.update_primary_plane = |
| 14962 | i9xx_update_primary_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 14963 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 14964 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 14965 | /* Returns the core display clock speed */ |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 14966 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 14967 | dev_priv->display.get_display_clock_speed = |
| 14968 | skylake_get_display_clock_speed; |
Bob Paauwe | acd3f3d | 2015-06-23 14:14:26 -0700 | [diff] [blame] | 14969 | else if (IS_BROXTON(dev)) |
| 14970 | dev_priv->display.get_display_clock_speed = |
| 14971 | broxton_get_display_clock_speed; |
Ville Syrjälä | 1652d19 | 2015-03-31 14:12:01 +0300 | [diff] [blame] | 14972 | else if (IS_BROADWELL(dev)) |
| 14973 | dev_priv->display.get_display_clock_speed = |
| 14974 | broadwell_get_display_clock_speed; |
| 14975 | else if (IS_HASWELL(dev)) |
| 14976 | dev_priv->display.get_display_clock_speed = |
| 14977 | haswell_get_display_clock_speed; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 14978 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 14979 | dev_priv->display.get_display_clock_speed = |
| 14980 | valleyview_get_display_clock_speed; |
Ville Syrjälä | b37a643 | 2015-03-31 14:11:54 +0300 | [diff] [blame] | 14981 | else if (IS_GEN5(dev)) |
| 14982 | dev_priv->display.get_display_clock_speed = |
| 14983 | ilk_get_display_clock_speed; |
Ville Syrjälä | a7c66cd | 2015-03-31 14:11:56 +0300 | [diff] [blame] | 14984 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 14985 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 14986 | dev_priv->display.get_display_clock_speed = |
| 14987 | i945_get_display_clock_speed; |
Ville Syrjälä | 34edce2 | 2015-05-22 11:22:33 +0300 | [diff] [blame] | 14988 | else if (IS_GM45(dev)) |
| 14989 | dev_priv->display.get_display_clock_speed = |
| 14990 | gm45_get_display_clock_speed; |
| 14991 | else if (IS_CRESTLINE(dev)) |
| 14992 | dev_priv->display.get_display_clock_speed = |
| 14993 | i965gm_get_display_clock_speed; |
| 14994 | else if (IS_PINEVIEW(dev)) |
| 14995 | dev_priv->display.get_display_clock_speed = |
| 14996 | pnv_get_display_clock_speed; |
| 14997 | else if (IS_G33(dev) || IS_G4X(dev)) |
| 14998 | dev_priv->display.get_display_clock_speed = |
| 14999 | g33_get_display_clock_speed; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15000 | else if (IS_I915G(dev)) |
| 15001 | dev_priv->display.get_display_clock_speed = |
| 15002 | i915_get_display_clock_speed; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 15003 | else if (IS_I945GM(dev) || IS_845G(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15004 | dev_priv->display.get_display_clock_speed = |
| 15005 | i9xx_misc_get_display_clock_speed; |
| 15006 | else if (IS_I915GM(dev)) |
| 15007 | dev_priv->display.get_display_clock_speed = |
| 15008 | i915gm_get_display_clock_speed; |
| 15009 | else if (IS_I865G(dev)) |
| 15010 | dev_priv->display.get_display_clock_speed = |
| 15011 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 15012 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15013 | dev_priv->display.get_display_clock_speed = |
Ville Syrjälä | 1b1d271 | 2015-05-22 11:22:31 +0300 | [diff] [blame] | 15014 | i85x_get_display_clock_speed; |
Ville Syrjälä | 623e01e | 2015-05-22 11:22:34 +0300 | [diff] [blame] | 15015 | else { /* 830 */ |
| 15016 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15017 | dev_priv->display.get_display_clock_speed = |
| 15018 | i830_get_display_clock_speed; |
Ville Syrjälä | 623e01e | 2015-05-22 11:22:34 +0300 | [diff] [blame] | 15019 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15020 | |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 15021 | if (IS_GEN5(dev)) { |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15022 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15023 | } else if (IS_GEN6(dev)) { |
| 15024 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15025 | } else if (IS_IVYBRIDGE(dev)) { |
| 15026 | /* FIXME: detect B0+ stepping and use auto training */ |
| 15027 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
Paulo Zanoni | 059b2fe | 2014-09-02 16:53:57 -0300 | [diff] [blame] | 15028 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Sonika Jindal | 3bb11b5 | 2014-08-11 09:06:39 +0530 | [diff] [blame] | 15029 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 15030 | if (IS_BROADWELL(dev)) { |
| 15031 | dev_priv->display.modeset_commit_cdclk = |
| 15032 | broadwell_modeset_commit_cdclk; |
| 15033 | dev_priv->display.modeset_calc_cdclk = |
| 15034 | broadwell_modeset_calc_cdclk; |
| 15035 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 15036 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 15037 | dev_priv->display.modeset_commit_cdclk = |
| 15038 | valleyview_modeset_commit_cdclk; |
| 15039 | dev_priv->display.modeset_calc_cdclk = |
| 15040 | valleyview_modeset_calc_cdclk; |
Vandana Kannan | f8437dd1 | 2014-11-24 13:37:39 +0530 | [diff] [blame] | 15041 | } else if (IS_BROXTON(dev)) { |
Maarten Lankhorst | 27c329e | 2015-06-15 12:33:56 +0200 | [diff] [blame] | 15042 | dev_priv->display.modeset_commit_cdclk = |
| 15043 | broxton_modeset_commit_cdclk; |
| 15044 | dev_priv->display.modeset_calc_cdclk = |
| 15045 | broxton_modeset_calc_cdclk; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15046 | } |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 15047 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 15048 | switch (INTEL_INFO(dev)->gen) { |
| 15049 | case 2: |
| 15050 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 15051 | break; |
| 15052 | |
| 15053 | case 3: |
| 15054 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 15055 | break; |
| 15056 | |
| 15057 | case 4: |
| 15058 | case 5: |
| 15059 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 15060 | break; |
| 15061 | |
| 15062 | case 6: |
| 15063 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 15064 | break; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 15065 | case 7: |
Ben Widawsky | 4e0bbc3 | 2013-11-02 21:07:07 -0700 | [diff] [blame] | 15066 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 15067 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 15068 | break; |
Damien Lespiau | 830c81d | 2014-11-13 17:51:46 +0000 | [diff] [blame] | 15069 | case 9: |
Tvrtko Ursulin | ba343e0 | 2015-02-10 17:16:12 +0000 | [diff] [blame] | 15070 | /* Drop through - unsupported since execlist only. */ |
| 15071 | default: |
| 15072 | /* Default just returns -ENODEV to indicate unsupported */ |
| 15073 | dev_priv->display.queue_flip = intel_default_queue_flip; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 15074 | } |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 15075 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 15076 | mutex_init(&dev_priv->pps_mutex); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15077 | } |
| 15078 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15079 | /* |
| 15080 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 15081 | * resume, or other times. This quirk makes sure that's the case for |
| 15082 | * affected systems. |
| 15083 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 15084 | static void quirk_pipea_force(struct drm_device *dev) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15085 | { |
| 15086 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15087 | |
| 15088 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 15089 | DRM_INFO("applying pipe a force quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15090 | } |
| 15091 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 15092 | static void quirk_pipeb_force(struct drm_device *dev) |
| 15093 | { |
| 15094 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15095 | |
| 15096 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; |
| 15097 | DRM_INFO("applying pipe b force quirk\n"); |
| 15098 | } |
| 15099 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 15100 | /* |
| 15101 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 15102 | */ |
| 15103 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 15104 | { |
| 15105 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15106 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 15107 | DRM_INFO("applying lvds SSC disable quirk\n"); |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 15108 | } |
| 15109 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 15110 | /* |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 15111 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
| 15112 | * brightness value |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 15113 | */ |
| 15114 | static void quirk_invert_brightness(struct drm_device *dev) |
| 15115 | { |
| 15116 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15117 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 15118 | DRM_INFO("applying inverted panel brightness quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15119 | } |
| 15120 | |
Scot Doyle | 9c72cc6 | 2014-07-03 23:27:50 +0000 | [diff] [blame] | 15121 | /* Some VBT's incorrectly indicate no backlight is present */ |
| 15122 | static void quirk_backlight_present(struct drm_device *dev) |
| 15123 | { |
| 15124 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15125 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
| 15126 | DRM_INFO("applying backlight present quirk\n"); |
| 15127 | } |
| 15128 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15129 | struct intel_quirk { |
| 15130 | int device; |
| 15131 | int subsystem_vendor; |
| 15132 | int subsystem_device; |
| 15133 | void (*hook)(struct drm_device *dev); |
| 15134 | }; |
| 15135 | |
Egbert Eich | 5f85f17 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 15136 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
| 15137 | struct intel_dmi_quirk { |
| 15138 | void (*hook)(struct drm_device *dev); |
| 15139 | const struct dmi_system_id (*dmi_id_list)[]; |
| 15140 | }; |
| 15141 | |
| 15142 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
| 15143 | { |
| 15144 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
| 15145 | return 1; |
| 15146 | } |
| 15147 | |
| 15148 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
| 15149 | { |
| 15150 | .dmi_id_list = &(const struct dmi_system_id[]) { |
| 15151 | { |
| 15152 | .callback = intel_dmi_reverse_brightness, |
| 15153 | .ident = "NCR Corporation", |
| 15154 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
| 15155 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
| 15156 | }, |
| 15157 | }, |
| 15158 | { } /* terminating entry */ |
| 15159 | }, |
| 15160 | .hook = quirk_invert_brightness, |
| 15161 | }, |
| 15162 | }; |
| 15163 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 15164 | static struct intel_quirk intel_quirks[] = { |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15165 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 15166 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 15167 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15168 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 15169 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 15170 | |
Ville Syrjälä | 5f080c0 | 2014-08-15 01:22:06 +0300 | [diff] [blame] | 15171 | /* 830 needs to leave pipe A & dpll A up */ |
| 15172 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 15173 | |
Ville Syrjälä | b6b5d04 | 2014-08-15 01:22:07 +0300 | [diff] [blame] | 15174 | /* 830 needs to leave pipe B & dpll B up */ |
| 15175 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, |
| 15176 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 15177 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 15178 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Michel Alexandre Salim | 070d329 | 2011-07-28 18:52:06 +0200 | [diff] [blame] | 15179 | |
| 15180 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 15181 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 15182 | |
Alexander van Heukelum | be505f6 | 2013-12-28 21:00:39 +0100 | [diff] [blame] | 15183 | /* Acer Aspire 5734Z must invert backlight brightness */ |
| 15184 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
| 15185 | |
| 15186 | /* Acer/eMachines G725 */ |
| 15187 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
| 15188 | |
| 15189 | /* Acer/eMachines e725 */ |
| 15190 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
| 15191 | |
| 15192 | /* Acer/Packard Bell NCL20 */ |
| 15193 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
| 15194 | |
| 15195 | /* Acer Aspire 4736Z */ |
| 15196 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
Jani Nikula | 0f540c3 | 2014-01-13 17:30:34 +0200 | [diff] [blame] | 15197 | |
| 15198 | /* Acer Aspire 5336 */ |
| 15199 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
Scot Doyle | 2e93a1a | 2014-07-03 23:27:51 +0000 | [diff] [blame] | 15200 | |
| 15201 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
| 15202 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
Scot Doyle | d4967d8 | 2014-07-03 23:27:52 +0000 | [diff] [blame] | 15203 | |
Scot Doyle | dfb3d47b | 2014-08-21 16:08:02 +0000 | [diff] [blame] | 15204 | /* Acer C720 Chromebook (Core i3 4005U) */ |
| 15205 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, |
| 15206 | |
jens stein | b2a9601 | 2014-10-28 20:25:53 +0100 | [diff] [blame] | 15207 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
| 15208 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, |
| 15209 | |
Jani Nikula | 1b9448b0 | 2015-11-05 11:49:59 +0200 | [diff] [blame] | 15210 | /* Apple Macbook 4,1 */ |
| 15211 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, |
| 15212 | |
Scot Doyle | d4967d8 | 2014-07-03 23:27:52 +0000 | [diff] [blame] | 15213 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
| 15214 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
Scot Doyle | 724cb06 | 2014-07-11 22:16:30 +0000 | [diff] [blame] | 15215 | |
| 15216 | /* HP Chromebook 14 (Celeron 2955U) */ |
| 15217 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
Jani Nikula | cf6f0af | 2015-02-19 10:53:39 +0200 | [diff] [blame] | 15218 | |
| 15219 | /* Dell Chromebook 11 */ |
| 15220 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, |
Jani Nikula | 9be64ee | 2015-10-30 14:50:24 +0200 | [diff] [blame] | 15221 | |
| 15222 | /* Dell Chromebook 11 (2015 version) */ |
| 15223 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15224 | }; |
| 15225 | |
| 15226 | static void intel_init_quirks(struct drm_device *dev) |
| 15227 | { |
| 15228 | struct pci_dev *d = dev->pdev; |
| 15229 | int i; |
| 15230 | |
| 15231 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 15232 | struct intel_quirk *q = &intel_quirks[i]; |
| 15233 | |
| 15234 | if (d->device == q->device && |
| 15235 | (d->subsystem_vendor == q->subsystem_vendor || |
| 15236 | q->subsystem_vendor == PCI_ANY_ID) && |
| 15237 | (d->subsystem_device == q->subsystem_device || |
| 15238 | q->subsystem_device == PCI_ANY_ID)) |
| 15239 | q->hook(dev); |
| 15240 | } |
Egbert Eich | 5f85f17 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 15241 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
| 15242 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
| 15243 | intel_dmi_quirks[i].hook(dev); |
| 15244 | } |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15245 | } |
| 15246 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 15247 | /* Disable the VGA plane that we never use */ |
| 15248 | static void i915_disable_vga(struct drm_device *dev) |
| 15249 | { |
| 15250 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15251 | u8 sr1; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 15252 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 15253 | |
Ville Syrjälä | 2b37c61 | 2014-01-22 21:32:38 +0200 | [diff] [blame] | 15254 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 15255 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
Jesse Barnes | 3fdcf43 | 2012-04-06 11:46:27 -0700 | [diff] [blame] | 15256 | outb(SR01, VGA_SR_INDEX); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 15257 | sr1 = inb(VGA_SR_DATA); |
| 15258 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 15259 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 15260 | udelay(300); |
| 15261 | |
Ville Syrjälä | 01f5a62 | 2014-12-16 18:38:37 +0200 | [diff] [blame] | 15262 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 15263 | POSTING_READ(vga_reg); |
| 15264 | } |
| 15265 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 15266 | void intel_modeset_init_hw(struct drm_device *dev) |
| 15267 | { |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 15268 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15269 | |
Ville Syrjälä | b628305 | 2015-06-03 15:45:07 +0300 | [diff] [blame] | 15270 | intel_update_cdclk(dev); |
Maarten Lankhorst | 1a617b7 | 2015-12-03 14:31:06 +0100 | [diff] [blame] | 15271 | |
| 15272 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
| 15273 | |
Eugeni Dodonov | a8f78b5 | 2012-06-28 15:55:35 -0300 | [diff] [blame] | 15274 | intel_prepare_ddi(dev); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 15275 | intel_init_clock_gating(dev); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 15276 | intel_enable_gt_powersave(dev); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 15277 | } |
| 15278 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15279 | void intel_modeset_init(struct drm_device *dev) |
| 15280 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 15281 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 15282 | int sprite, ret; |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 15283 | enum pipe pipe; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 15284 | struct intel_crtc *crtc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15285 | |
| 15286 | drm_mode_config_init(dev); |
| 15287 | |
| 15288 | dev->mode_config.min_width = 0; |
| 15289 | dev->mode_config.min_height = 0; |
| 15290 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 15291 | dev->mode_config.preferred_depth = 24; |
| 15292 | dev->mode_config.prefer_shadow = 1; |
| 15293 | |
Tvrtko Ursulin | 25bab38 | 2015-02-10 17:16:16 +0000 | [diff] [blame] | 15294 | dev->mode_config.allow_fb_modifiers = true; |
| 15295 | |
Laurent Pinchart | e6ecefa | 2012-05-17 13:27:23 +0200 | [diff] [blame] | 15296 | dev->mode_config.funcs = &intel_mode_funcs; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15297 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 15298 | intel_init_quirks(dev); |
| 15299 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 15300 | intel_init_pm(dev); |
| 15301 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 15302 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 15303 | return; |
| 15304 | |
Lukas Wunner | 69f92f6 | 2015-07-15 13:57:35 +0200 | [diff] [blame] | 15305 | /* |
| 15306 | * There may be no VBT; and if the BIOS enabled SSC we can |
| 15307 | * just keep using it to avoid unnecessary flicker. Whereas if the |
| 15308 | * BIOS isn't using it, don't assume it will work even if the VBT |
| 15309 | * indicates as much. |
| 15310 | */ |
| 15311 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 15312 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
| 15313 | DREF_SSC1_ENABLE); |
| 15314 | |
| 15315 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { |
| 15316 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", |
| 15317 | bios_lvds_use_ssc ? "en" : "dis", |
| 15318 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); |
| 15319 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
| 15320 | } |
| 15321 | } |
| 15322 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15323 | intel_init_display(dev); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 15324 | intel_init_audio(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 15325 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 15326 | if (IS_GEN2(dev)) { |
| 15327 | dev->mode_config.max_width = 2048; |
| 15328 | dev->mode_config.max_height = 2048; |
| 15329 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 15330 | dev->mode_config.max_width = 4096; |
| 15331 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15332 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 15333 | dev->mode_config.max_width = 8192; |
| 15334 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15335 | } |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 15336 | |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 15337 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 15338 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; |
| 15339 | dev->mode_config.cursor_height = 1023; |
| 15340 | } else if (IS_GEN2(dev)) { |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 15341 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
| 15342 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; |
| 15343 | } else { |
| 15344 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; |
| 15345 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; |
| 15346 | } |
| 15347 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 15348 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15349 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 15350 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 15351 | INTEL_INFO(dev)->num_pipes, |
| 15352 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15353 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 15354 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 15355 | intel_crtc_init(dev, pipe); |
Damien Lespiau | 3bdcfc0 | 2015-02-28 14:54:09 +0000 | [diff] [blame] | 15356 | for_each_sprite(dev_priv, pipe, sprite) { |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 15357 | ret = intel_plane_init(dev, pipe, sprite); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 15358 | if (ret) |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 15359 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 15360 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 15361 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15362 | } |
| 15363 | |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 15364 | intel_update_czclk(dev_priv); |
| 15365 | intel_update_cdclk(dev); |
| 15366 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 15367 | intel_shared_dpll_init(dev); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 15368 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 15369 | /* Just disable it once at startup */ |
| 15370 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15371 | intel_setup_outputs(dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 15372 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 15373 | drm_modeset_lock_all(dev); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15374 | intel_modeset_setup_hw_state(dev); |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 15375 | drm_modeset_unlock_all(dev); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 15376 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 15377 | for_each_intel_crtc(dev, crtc) { |
Maarten Lankhorst | eeebeac | 2015-07-14 12:33:29 +0200 | [diff] [blame] | 15378 | struct intel_initial_plane_config plane_config = {}; |
| 15379 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 15380 | if (!crtc->active) |
| 15381 | continue; |
| 15382 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 15383 | /* |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 15384 | * Note that reserving the BIOS fb up front prevents us |
| 15385 | * from stuffing other stolen allocations like the ring |
| 15386 | * on top. This prevents some ugliness at boot time, and |
| 15387 | * can even allow for smooth boot transitions if the BIOS |
| 15388 | * fb is large enough for the active pipe configuration. |
| 15389 | */ |
Maarten Lankhorst | eeebeac | 2015-07-14 12:33:29 +0200 | [diff] [blame] | 15390 | dev_priv->display.get_initial_plane_config(crtc, |
| 15391 | &plane_config); |
| 15392 | |
| 15393 | /* |
| 15394 | * If the fb is shared between multiple heads, we'll |
| 15395 | * just get the first one. |
| 15396 | */ |
| 15397 | intel_find_initial_plane_obj(crtc, &plane_config); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 15398 | } |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 15399 | } |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 15400 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 15401 | static void intel_enable_pipe_a(struct drm_device *dev) |
| 15402 | { |
| 15403 | struct intel_connector *connector; |
| 15404 | struct drm_connector *crt = NULL; |
| 15405 | struct intel_load_detect_pipe load_detect_temp; |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 15406 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 15407 | |
| 15408 | /* We can't just switch on the pipe A, we need to set things up with a |
| 15409 | * proper mode and output configuration. As a gross hack, enable pipe A |
| 15410 | * by enabling the load detect pipe once. */ |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 15411 | for_each_intel_connector(dev, connector) { |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 15412 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
| 15413 | crt = &connector->base; |
| 15414 | break; |
| 15415 | } |
| 15416 | } |
| 15417 | |
| 15418 | if (!crt) |
| 15419 | return; |
| 15420 | |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 15421 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
Ander Conselvan de Oliveira | 49172fe | 2015-03-20 16:18:02 +0200 | [diff] [blame] | 15422 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 15423 | } |
| 15424 | |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 15425 | static bool |
| 15426 | intel_check_plane_mapping(struct intel_crtc *crtc) |
| 15427 | { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 15428 | struct drm_device *dev = crtc->base.dev; |
| 15429 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 15430 | u32 val; |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 15431 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 15432 | if (INTEL_INFO(dev)->num_pipes == 1) |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 15433 | return true; |
| 15434 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 15435 | val = I915_READ(DSPCNTR(!crtc->plane)); |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 15436 | |
| 15437 | if ((val & DISPLAY_PLANE_ENABLE) && |
| 15438 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
| 15439 | return false; |
| 15440 | |
| 15441 | return true; |
| 15442 | } |
| 15443 | |
Ville Syrjälä | 02e93c3 | 2015-08-26 19:39:19 +0300 | [diff] [blame] | 15444 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
| 15445 | { |
| 15446 | struct drm_device *dev = crtc->base.dev; |
| 15447 | struct intel_encoder *encoder; |
| 15448 | |
| 15449 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
| 15450 | return true; |
| 15451 | |
| 15452 | return false; |
| 15453 | } |
| 15454 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15455 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
| 15456 | { |
| 15457 | struct drm_device *dev = crtc->base.dev; |
| 15458 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 15459 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15460 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15461 | /* Clear any frame start delays used for debugging left by the BIOS */ |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15462 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 15463 | |
Ville Syrjälä | d3eaf88 | 2014-05-20 17:20:05 +0300 | [diff] [blame] | 15464 | /* restore vblank interrupts to correct state */ |
Daniel Vetter | 9625604 | 2015-02-13 21:03:42 +0100 | [diff] [blame] | 15465 | drm_crtc_vblank_reset(&crtc->base); |
Ville Syrjälä | d297e10 | 2014-08-06 14:50:01 +0300 | [diff] [blame] | 15466 | if (crtc->active) { |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15467 | struct intel_plane *plane; |
| 15468 | |
Daniel Vetter | 9625604 | 2015-02-13 21:03:42 +0100 | [diff] [blame] | 15469 | drm_crtc_vblank_on(&crtc->base); |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15470 | |
| 15471 | /* Disable everything but the primary plane */ |
| 15472 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 15473 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
| 15474 | continue; |
| 15475 | |
| 15476 | plane->disable_plane(&plane->base, &crtc->base); |
| 15477 | } |
Daniel Vetter | 9625604 | 2015-02-13 21:03:42 +0100 | [diff] [blame] | 15478 | } |
Ville Syrjälä | d3eaf88 | 2014-05-20 17:20:05 +0300 | [diff] [blame] | 15479 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15480 | /* We need to sanitize the plane -> pipe mapping first because this will |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 15481 | * disable the crtc (and hence change the state) if it is wrong. Note |
| 15482 | * that gen4+ has a fixed plane -> pipe mapping. */ |
| 15483 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15484 | bool plane; |
| 15485 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15486 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
| 15487 | crtc->base.base.id); |
| 15488 | |
| 15489 | /* Pipe has the wrong plane attached and the plane is active. |
| 15490 | * Temporarily change the plane mapping and disable everything |
| 15491 | * ... */ |
| 15492 | plane = crtc->plane; |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 15493 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15494 | crtc->plane = !plane; |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 15495 | intel_crtc_disable_noatomic(&crtc->base); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15496 | crtc->plane = plane; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15497 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15498 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 15499 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 15500 | crtc->pipe == PIPE_A && !crtc->active) { |
| 15501 | /* BIOS forgot to enable pipe A, this mostly happens after |
| 15502 | * resume. Force-enable the pipe to fix this, the update_dpms |
| 15503 | * call below we restore the pipe to the right state, but leave |
| 15504 | * the required bits on. */ |
| 15505 | intel_enable_pipe_a(dev); |
| 15506 | } |
| 15507 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15508 | /* Adjust the state of the output pipe according to whether we |
| 15509 | * have active connectors/encoders. */ |
Ville Syrjälä | 02e93c3 | 2015-08-26 19:39:19 +0300 | [diff] [blame] | 15510 | if (!intel_crtc_has_encoders(crtc)) |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 15511 | intel_crtc_disable_noatomic(&crtc->base); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15512 | |
Maarten Lankhorst | 53d9f4e | 2015-06-01 12:49:52 +0200 | [diff] [blame] | 15513 | if (crtc->active != crtc->base.state->active) { |
Ville Syrjälä | 02e93c3 | 2015-08-26 19:39:19 +0300 | [diff] [blame] | 15514 | struct intel_encoder *encoder; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15515 | |
| 15516 | /* This can happen either due to bugs in the get_hw_state |
Maarten Lankhorst | b17d48e | 2015-06-12 11:15:39 +0200 | [diff] [blame] | 15517 | * functions or because of calls to intel_crtc_disable_noatomic, |
| 15518 | * or because the pipe is force-enabled due to the |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15519 | * pipe A quirk. */ |
| 15520 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
| 15521 | crtc->base.base.id, |
Matt Roper | 83d6573 | 2015-02-25 13:12:16 -0800 | [diff] [blame] | 15522 | crtc->base.state->enable ? "enabled" : "disabled", |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15523 | crtc->active ? "enabled" : "disabled"); |
| 15524 | |
Maarten Lankhorst | 4be40c9 | 2015-07-14 13:45:32 +0200 | [diff] [blame] | 15525 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
Maarten Lankhorst | 49d6fa2 | 2015-05-11 10:45:15 +0200 | [diff] [blame] | 15526 | crtc->base.state->active = crtc->active; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15527 | crtc->base.enabled = crtc->active; |
| 15528 | |
| 15529 | /* Because we only establish the connector -> encoder -> |
| 15530 | * crtc links if something is active, this means the |
| 15531 | * crtc is now deactivated. Break the links. connector |
| 15532 | * -> encoder links are only establish when things are |
| 15533 | * actually up, hence no need to break them. */ |
| 15534 | WARN_ON(crtc->active); |
| 15535 | |
Maarten Lankhorst | 2d406bb | 2015-08-05 12:37:09 +0200 | [diff] [blame] | 15536 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15537 | encoder->base.crtc = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15538 | } |
Daniel Vetter | c5ab3bc | 2014-05-14 15:40:34 +0200 | [diff] [blame] | 15539 | |
Ville Syrjälä | a3ed6aa | 2014-09-03 14:09:52 +0300 | [diff] [blame] | 15540 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 15541 | /* |
| 15542 | * We start out with underrun reporting disabled to avoid races. |
| 15543 | * For correct bookkeeping mark this on active crtcs. |
| 15544 | * |
Daniel Vetter | c5ab3bc | 2014-05-14 15:40:34 +0200 | [diff] [blame] | 15545 | * Also on gmch platforms we dont have any hardware bits to |
| 15546 | * disable the underrun reporting. Which means we need to start |
| 15547 | * out with underrun reporting disabled also on inactive pipes, |
| 15548 | * since otherwise we'll complain about the garbage we read when |
| 15549 | * e.g. coming up after runtime pm. |
| 15550 | * |
Daniel Vetter | 4cc3148 | 2014-03-24 00:01:41 +0100 | [diff] [blame] | 15551 | * No protection against concurrent access is required - at |
| 15552 | * worst a fifo underrun happens which also sets this to false. |
| 15553 | */ |
| 15554 | crtc->cpu_fifo_underrun_disabled = true; |
| 15555 | crtc->pch_fifo_underrun_disabled = true; |
| 15556 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15557 | } |
| 15558 | |
| 15559 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
| 15560 | { |
| 15561 | struct intel_connector *connector; |
| 15562 | struct drm_device *dev = encoder->base.dev; |
Maarten Lankhorst | 873ffe6 | 2015-08-05 12:37:07 +0200 | [diff] [blame] | 15563 | bool active = false; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15564 | |
| 15565 | /* We need to check both for a crtc link (meaning that the |
| 15566 | * encoder is active and trying to read from a pipe) and the |
| 15567 | * pipe itself being active. */ |
| 15568 | bool has_active_crtc = encoder->base.crtc && |
| 15569 | to_intel_crtc(encoder->base.crtc)->active; |
| 15570 | |
Maarten Lankhorst | 873ffe6 | 2015-08-05 12:37:07 +0200 | [diff] [blame] | 15571 | for_each_intel_connector(dev, connector) { |
| 15572 | if (connector->base.encoder != &encoder->base) |
| 15573 | continue; |
| 15574 | |
| 15575 | active = true; |
| 15576 | break; |
| 15577 | } |
| 15578 | |
| 15579 | if (active && !has_active_crtc) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15580 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
| 15581 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 15582 | encoder->base.name); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15583 | |
| 15584 | /* Connector is active, but has no active pipe. This is |
| 15585 | * fallout from our resume register restoring. Disable |
| 15586 | * the encoder manually again. */ |
| 15587 | if (encoder->base.crtc) { |
| 15588 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
| 15589 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 15590 | encoder->base.name); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15591 | encoder->disable(encoder); |
Ville Syrjälä | a62d149 | 2014-06-28 02:04:01 +0300 | [diff] [blame] | 15592 | if (encoder->post_disable) |
| 15593 | encoder->post_disable(encoder); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15594 | } |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 15595 | encoder->base.crtc = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15596 | |
| 15597 | /* Inconsistent output/port/pipe state happens presumably due to |
| 15598 | * a bug in one of the get_hw_state functions. Or someplace else |
| 15599 | * in our code, like the register restore mess on resume. Clamp |
| 15600 | * things to off as a safer default. */ |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 15601 | for_each_intel_connector(dev, connector) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15602 | if (connector->encoder != encoder) |
| 15603 | continue; |
Egbert Eich | 7f1950f | 2014-04-25 10:56:22 +0200 | [diff] [blame] | 15604 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 15605 | connector->base.encoder = NULL; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15606 | } |
| 15607 | } |
| 15608 | /* Enabled encoders without active connectors will be fixed in |
| 15609 | * the crtc fixup. */ |
| 15610 | } |
| 15611 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 15612 | void i915_redisable_vga_power_on(struct drm_device *dev) |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 15613 | { |
| 15614 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 15615 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 15616 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 15617 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
| 15618 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
| 15619 | i915_disable_vga(dev); |
| 15620 | } |
| 15621 | } |
| 15622 | |
| 15623 | void i915_redisable_vga(struct drm_device *dev) |
| 15624 | { |
| 15625 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15626 | |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 15627 | /* This function can be called both from intel_modeset_setup_hw_state or |
| 15628 | * at a very early point in our resume sequence, where the power well |
| 15629 | * structures are not yet restored. Since this function is at a very |
| 15630 | * paranoid "someone might have enabled VGA while we were not looking" |
| 15631 | * level, just check if the power well is enabled instead of trying to |
| 15632 | * follow the "don't touch the power well if we don't need it" policy |
| 15633 | * the rest of the driver uses. */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 15634 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 15635 | return; |
| 15636 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 15637 | i915_redisable_vga_power_on(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 15638 | } |
| 15639 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15640 | static bool primary_get_hw_state(struct intel_plane *plane) |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 15641 | { |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15642 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 15643 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15644 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 15645 | } |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 15646 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15647 | /* FIXME read out full plane state for all planes */ |
| 15648 | static void readout_plane_state(struct intel_crtc *crtc) |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 15649 | { |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 15650 | struct drm_plane *primary = crtc->base.primary; |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15651 | struct intel_plane_state *plane_state = |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 15652 | to_intel_plane_state(primary->state); |
Maarten Lankhorst | d032ffa | 2015-06-15 12:33:51 +0200 | [diff] [blame] | 15653 | |
Matt Roper | 19b8d38 | 2015-09-24 15:53:17 -0700 | [diff] [blame] | 15654 | plane_state->visible = crtc->active && |
Maarten Lankhorst | b26d3ea | 2015-09-23 16:11:41 +0200 | [diff] [blame] | 15655 | primary_get_hw_state(to_intel_plane(primary)); |
| 15656 | |
| 15657 | if (plane_state->visible) |
| 15658 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
Ville Syrjälä | 98ec773 | 2014-04-30 17:43:01 +0300 | [diff] [blame] | 15659 | } |
| 15660 | |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 15661 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15662 | { |
| 15663 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15664 | enum pipe pipe; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15665 | struct intel_crtc *crtc; |
| 15666 | struct intel_encoder *encoder; |
| 15667 | struct intel_connector *connector; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15668 | int i; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15669 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 15670 | dev_priv->active_crtcs = 0; |
| 15671 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 15672 | for_each_intel_crtc(dev, crtc) { |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 15673 | struct intel_crtc_state *crtc_state = crtc->config; |
| 15674 | int pixclk = 0; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 15675 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 15676 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
| 15677 | memset(crtc_state, 0, sizeof(*crtc_state)); |
| 15678 | crtc_state->base.crtc = &crtc->base; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15679 | |
Maarten Lankhorst | 565602d | 2015-12-10 12:33:57 +0100 | [diff] [blame] | 15680 | crtc_state->base.active = crtc_state->base.enable = |
| 15681 | dev_priv->display.get_pipe_config(crtc, crtc_state); |
| 15682 | |
| 15683 | crtc->base.enabled = crtc_state->base.enable; |
| 15684 | crtc->active = crtc_state->base.active; |
| 15685 | |
| 15686 | if (crtc_state->base.active) { |
| 15687 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
| 15688 | |
| 15689 | if (IS_BROADWELL(dev_priv)) { |
| 15690 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
| 15691 | |
| 15692 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
| 15693 | if (crtc_state->ips_enabled) |
| 15694 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
| 15695 | } else if (IS_VALLEYVIEW(dev_priv) || |
| 15696 | IS_CHERRYVIEW(dev_priv) || |
| 15697 | IS_BROXTON(dev_priv)) |
| 15698 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
| 15699 | else |
| 15700 | WARN_ON(dev_priv->display.modeset_calc_cdclk); |
| 15701 | } |
| 15702 | |
| 15703 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 15704 | |
Ville Syrjälä | f9cd7b8 | 2015-09-10 18:59:08 +0300 | [diff] [blame] | 15705 | readout_plane_state(crtc); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15706 | |
| 15707 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
| 15708 | crtc->base.base.id, |
| 15709 | crtc->active ? "enabled" : "disabled"); |
| 15710 | } |
| 15711 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15712 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 15713 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 15714 | |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 15715 | pll->on = pll->get_hw_state(dev_priv, pll, |
| 15716 | &pll->config.hw_state); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15717 | pll->active = 0; |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 15718 | pll->config.crtc_mask = 0; |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 15719 | for_each_intel_crtc(dev, crtc) { |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 15720 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15721 | pll->active++; |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 15722 | pll->config.crtc_mask |= 1 << crtc->pipe; |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 15723 | } |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15724 | } |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15725 | |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 15726 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 15727 | pll->name, pll->config.crtc_mask, pll->on); |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 15728 | |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 15729 | if (pll->config.crtc_mask) |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 15730 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 15731 | } |
| 15732 | |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 15733 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15734 | pipe = 0; |
| 15735 | |
| 15736 | if (encoder->get_hw_state(encoder, &pipe)) { |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 15737 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 15738 | encoder->base.crtc = &crtc->base; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 15739 | encoder->get_config(encoder, crtc->config); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15740 | } else { |
| 15741 | encoder->base.crtc = NULL; |
| 15742 | } |
| 15743 | |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 15744 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15745 | encoder->base.base.id, |
Jani Nikula | 8e329a03 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 15746 | encoder->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15747 | encoder->base.crtc ? "enabled" : "disabled", |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 15748 | pipe_name(pipe)); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15749 | } |
| 15750 | |
Ander Conselvan de Oliveira | 3a3371f | 2015-03-03 15:21:56 +0200 | [diff] [blame] | 15751 | for_each_intel_connector(dev, connector) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15752 | if (connector->get_hw_state(connector)) { |
| 15753 | connector->base.dpms = DRM_MODE_DPMS_ON; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15754 | connector->base.encoder = &connector->encoder->base; |
| 15755 | } else { |
| 15756 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 15757 | connector->base.encoder = NULL; |
| 15758 | } |
| 15759 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
| 15760 | connector->base.base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 15761 | connector->base.name, |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15762 | connector->base.encoder ? "enabled" : "disabled"); |
| 15763 | } |
Ville Syrjälä | 7f4c628 | 2015-09-10 18:59:07 +0300 | [diff] [blame] | 15764 | |
| 15765 | for_each_intel_crtc(dev, crtc) { |
| 15766 | crtc->base.hwmode = crtc->config->base.adjusted_mode; |
| 15767 | |
| 15768 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
| 15769 | if (crtc->base.state->active) { |
| 15770 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); |
| 15771 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); |
| 15772 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
| 15773 | |
| 15774 | /* |
| 15775 | * The initial mode needs to be set in order to keep |
| 15776 | * the atomic core happy. It wants a valid mode if the |
| 15777 | * crtc's enabled, so we do the above call. |
| 15778 | * |
| 15779 | * At this point some state updated by the connectors |
| 15780 | * in their ->detect() callback has not run yet, so |
| 15781 | * no recalculation can be done yet. |
| 15782 | * |
| 15783 | * Even if we could do a recalculation and modeset |
| 15784 | * right now it would cause a double modeset if |
| 15785 | * fbdev or userspace chooses a different initial mode. |
| 15786 | * |
| 15787 | * If that happens, someone indicated they wanted a |
| 15788 | * mode change, which means it's safe to do a full |
| 15789 | * recalculation. |
| 15790 | */ |
| 15791 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; |
Ville Syrjälä | 9eca6832 | 2015-09-10 18:59:10 +0300 | [diff] [blame] | 15792 | |
| 15793 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
| 15794 | update_scanline_offset(crtc); |
Ville Syrjälä | 7f4c628 | 2015-09-10 18:59:07 +0300 | [diff] [blame] | 15795 | } |
| 15796 | } |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 15797 | } |
| 15798 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15799 | /* Scan out the current hw modeset state, |
| 15800 | * and sanitizes it to the current state |
| 15801 | */ |
| 15802 | static void |
| 15803 | intel_modeset_setup_hw_state(struct drm_device *dev) |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 15804 | { |
| 15805 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15806 | enum pipe pipe; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 15807 | struct intel_crtc *crtc; |
| 15808 | struct intel_encoder *encoder; |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 15809 | int i; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 15810 | |
| 15811 | intel_modeset_readout_hw_state(dev); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15812 | |
| 15813 | /* HW state is read out, now we need to sanitize this mess. */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 15814 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15815 | intel_sanitize_encoder(encoder); |
| 15816 | } |
| 15817 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 15818 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15819 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 15820 | intel_sanitize_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 15821 | intel_dump_pipe_config(crtc, crtc->config, |
| 15822 | "[setup_hw_state]"); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 15823 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 15824 | |
Ander Conselvan de Oliveira | d29b2f9 | 2015-03-20 16:18:05 +0200 | [diff] [blame] | 15825 | intel_modeset_update_connector_atomic_state(dev); |
| 15826 | |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 15827 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 15828 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 15829 | |
| 15830 | if (!pll->on || pll->active) |
| 15831 | continue; |
| 15832 | |
| 15833 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
| 15834 | |
| 15835 | pll->disable(dev_priv, pll); |
| 15836 | pll->on = false; |
| 15837 | } |
| 15838 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 15839 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 15840 | vlv_wm_get_hw_state(dev); |
| 15841 | else if (IS_GEN9(dev)) |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 15842 | skl_wm_get_hw_state(dev); |
| 15843 | else if (HAS_PCH_SPLIT(dev)) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 15844 | ilk_wm_get_hw_state(dev); |
Maarten Lankhorst | 292b990 | 2015-07-13 16:30:27 +0200 | [diff] [blame] | 15845 | |
| 15846 | for_each_intel_crtc(dev, crtc) { |
| 15847 | unsigned long put_domains; |
| 15848 | |
| 15849 | put_domains = modeset_get_crtc_power_domains(&crtc->base); |
| 15850 | if (WARN_ON(put_domains)) |
| 15851 | modeset_put_power_domains(dev_priv, put_domains); |
| 15852 | } |
| 15853 | intel_display_set_init_power(dev_priv, false); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15854 | } |
Ville Syrjälä | 7d0bc1e | 2013-09-16 17:38:33 +0300 | [diff] [blame] | 15855 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15856 | void intel_display_resume(struct drm_device *dev) |
| 15857 | { |
| 15858 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); |
| 15859 | struct intel_connector *conn; |
| 15860 | struct intel_plane *plane; |
| 15861 | struct drm_crtc *crtc; |
| 15862 | int ret; |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 15863 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15864 | if (!state) |
| 15865 | return; |
| 15866 | |
| 15867 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
| 15868 | |
| 15869 | /* preserve complete old state, including dpll */ |
| 15870 | intel_atomic_get_shared_dpll_state(state); |
| 15871 | |
| 15872 | for_each_crtc(dev, crtc) { |
| 15873 | struct drm_crtc_state *crtc_state = |
| 15874 | drm_atomic_get_crtc_state(state, crtc); |
| 15875 | |
| 15876 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 15877 | if (ret) |
| 15878 | goto err; |
| 15879 | |
| 15880 | /* force a restore */ |
| 15881 | crtc_state->mode_changed = true; |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 15882 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 15883 | |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15884 | for_each_intel_plane(dev, plane) { |
| 15885 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); |
| 15886 | if (ret) |
| 15887 | goto err; |
| 15888 | } |
| 15889 | |
| 15890 | for_each_intel_connector(dev, conn) { |
| 15891 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); |
| 15892 | if (ret) |
| 15893 | goto err; |
| 15894 | } |
| 15895 | |
| 15896 | intel_modeset_setup_hw_state(dev); |
| 15897 | |
| 15898 | i915_redisable_vga(dev); |
Maarten Lankhorst | 74c090b | 2015-07-13 16:30:30 +0200 | [diff] [blame] | 15899 | ret = drm_atomic_commit(state); |
Maarten Lankhorst | 043e9bd | 2015-07-13 16:30:25 +0200 | [diff] [blame] | 15900 | if (!ret) |
| 15901 | return; |
| 15902 | |
| 15903 | err: |
| 15904 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
| 15905 | drm_atomic_state_free(state); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 15906 | } |
| 15907 | |
| 15908 | void intel_modeset_gem_init(struct drm_device *dev) |
| 15909 | { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 15910 | struct drm_crtc *c; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 15911 | struct drm_i915_gem_object *obj; |
Tvrtko Ursulin | e0d6149 | 2015-04-13 16:03:03 +0100 | [diff] [blame] | 15912 | int ret; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 15913 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 15914 | mutex_lock(&dev->struct_mutex); |
| 15915 | intel_init_gt_powersave(dev); |
| 15916 | mutex_unlock(&dev->struct_mutex); |
| 15917 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 15918 | intel_modeset_init_hw(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 15919 | |
| 15920 | intel_setup_overlay(dev); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 15921 | |
| 15922 | /* |
| 15923 | * Make sure any fbs we allocated at startup are properly |
| 15924 | * pinned & fenced. When we do the allocation it's too early |
| 15925 | * for this. |
| 15926 | */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 15927 | for_each_crtc(dev, c) { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 15928 | obj = intel_fb_obj(c->primary->fb); |
| 15929 | if (obj == NULL) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 15930 | continue; |
| 15931 | |
Tvrtko Ursulin | e0d6149 | 2015-04-13 16:03:03 +0100 | [diff] [blame] | 15932 | mutex_lock(&dev->struct_mutex); |
| 15933 | ret = intel_pin_and_fence_fb_obj(c->primary, |
| 15934 | c->primary->fb, |
Maarten Lankhorst | 7580d77 | 2015-08-18 13:40:06 +0200 | [diff] [blame] | 15935 | c->primary->state); |
Tvrtko Ursulin | e0d6149 | 2015-04-13 16:03:03 +0100 | [diff] [blame] | 15936 | mutex_unlock(&dev->struct_mutex); |
| 15937 | if (ret) { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 15938 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
| 15939 | to_intel_crtc(c)->pipe); |
Dave Airlie | 66e514c | 2014-04-03 07:51:54 +1000 | [diff] [blame] | 15940 | drm_framebuffer_unreference(c->primary->fb); |
| 15941 | c->primary->fb = NULL; |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 15942 | c->primary->crtc = c->primary->state->crtc = NULL; |
Matt Roper | afd65eb | 2015-02-03 13:10:04 -0800 | [diff] [blame] | 15943 | update_state_fb(c->primary); |
Maarten Lankhorst | 36750f2 | 2015-06-01 12:49:54 +0200 | [diff] [blame] | 15944 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 15945 | } |
| 15946 | } |
Ville Syrjälä | 0962c3c | 2014-11-07 15:19:46 +0200 | [diff] [blame] | 15947 | |
| 15948 | intel_backlight_register(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15949 | } |
| 15950 | |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 15951 | void intel_connector_unregister(struct intel_connector *intel_connector) |
| 15952 | { |
| 15953 | struct drm_connector *connector = &intel_connector->base; |
| 15954 | |
| 15955 | intel_panel_destroy_backlight(connector); |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 15956 | drm_connector_unregister(connector); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 15957 | } |
| 15958 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15959 | void intel_modeset_cleanup(struct drm_device *dev) |
| 15960 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 15961 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 15962 | struct intel_connector *connector; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 15963 | |
Imre Deak | 2eb5252 | 2014-11-19 15:30:05 +0200 | [diff] [blame] | 15964 | intel_disable_gt_powersave(dev); |
| 15965 | |
Ville Syrjälä | 0962c3c | 2014-11-07 15:19:46 +0200 | [diff] [blame] | 15966 | intel_backlight_unregister(dev); |
| 15967 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 15968 | /* |
| 15969 | * Interrupts and polling as the first thing to avoid creating havoc. |
Imre Deak | 2eb5252 | 2014-11-19 15:30:05 +0200 | [diff] [blame] | 15970 | * Too much stuff here (turning of connectors, ...) would |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 15971 | * experience fancy races otherwise. |
| 15972 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 15973 | intel_irq_uninstall(dev_priv); |
Jesse Barnes | eb21b92 | 2014-06-20 11:57:33 -0700 | [diff] [blame] | 15974 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 15975 | /* |
| 15976 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
| 15977 | * poll handlers. Hence disable polling after hpd handling is shut down. |
| 15978 | */ |
Keith Packard | f87ea76 | 2010-10-03 19:36:26 -0700 | [diff] [blame] | 15979 | drm_kms_helper_poll_fini(dev); |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 15980 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 15981 | intel_unregister_dsm_handler(); |
| 15982 | |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 15983 | intel_fbc_disable(dev_priv); |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 15984 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 15985 | /* flush any delayed tasks or pending work */ |
| 15986 | flush_scheduled_work(); |
| 15987 | |
Jani Nikula | db31af1d | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 15988 | /* destroy the backlight and sysfs files before encoders/connectors */ |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 15989 | for_each_intel_connector(dev, connector) |
| 15990 | connector->unregister(connector); |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 15991 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15992 | drm_mode_config_cleanup(dev); |
Daniel Vetter | 4d7bb01 | 2012-12-18 15:24:37 +0100 | [diff] [blame] | 15993 | |
| 15994 | intel_cleanup_overlay(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 15995 | |
| 15996 | mutex_lock(&dev->struct_mutex); |
| 15997 | intel_cleanup_gt_powersave(dev); |
| 15998 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 15999 | } |
| 16000 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 16001 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 16002 | * Return which encoder is currently attached for connector. |
| 16003 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 16004 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16005 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 16006 | return &intel_attached_encoder(connector)->base; |
| 16007 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16008 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 16009 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 16010 | struct intel_encoder *encoder) |
| 16011 | { |
| 16012 | connector->encoder = encoder; |
| 16013 | drm_mode_connector_attach_encoder(&connector->base, |
| 16014 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 16015 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 16016 | |
| 16017 | /* |
| 16018 | * set vga decode state - true == enable VGA decode |
| 16019 | */ |
| 16020 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 16021 | { |
| 16022 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a885b3c | 2013-12-17 14:34:50 +0000 | [diff] [blame] | 16023 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 16024 | u16 gmch_ctrl; |
| 16025 | |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 16026 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
| 16027 | DRM_ERROR("failed to read control word\n"); |
| 16028 | return -EIO; |
| 16029 | } |
| 16030 | |
Chris Wilson | c0cc8a5 | 2014-02-07 18:37:03 -0200 | [diff] [blame] | 16031 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
| 16032 | return 0; |
| 16033 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 16034 | if (state) |
| 16035 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 16036 | else |
| 16037 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 16038 | |
| 16039 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
| 16040 | DRM_ERROR("failed to write control word\n"); |
| 16041 | return -EIO; |
| 16042 | } |
| 16043 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 16044 | return 0; |
| 16045 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16046 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16047 | struct intel_display_error_state { |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 16048 | |
| 16049 | u32 power_well_driver; |
| 16050 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16051 | int num_transcoders; |
| 16052 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16053 | struct intel_cursor_error_state { |
| 16054 | u32 control; |
| 16055 | u32 position; |
| 16056 | u32 base; |
| 16057 | u32 size; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 16058 | } cursor[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16059 | |
| 16060 | struct intel_pipe_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16061 | bool power_domain_on; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16062 | u32 source; |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 16063 | u32 stat; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 16064 | } pipe[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16065 | |
| 16066 | struct intel_plane_error_state { |
| 16067 | u32 control; |
| 16068 | u32 stride; |
| 16069 | u32 size; |
| 16070 | u32 pos; |
| 16071 | u32 addr; |
| 16072 | u32 surface; |
| 16073 | u32 tile_offset; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 16074 | } plane[I915_MAX_PIPES]; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16075 | |
| 16076 | struct intel_transcoder_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16077 | bool power_domain_on; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16078 | enum transcoder cpu_transcoder; |
| 16079 | |
| 16080 | u32 conf; |
| 16081 | |
| 16082 | u32 htotal; |
| 16083 | u32 hblank; |
| 16084 | u32 hsync; |
| 16085 | u32 vtotal; |
| 16086 | u32 vblank; |
| 16087 | u32 vsync; |
| 16088 | } transcoder[4]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16089 | }; |
| 16090 | |
| 16091 | struct intel_display_error_state * |
| 16092 | intel_display_capture_error_state(struct drm_device *dev) |
| 16093 | { |
Jani Nikula | fbee40d | 2014-03-31 14:27:18 +0300 | [diff] [blame] | 16094 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16095 | struct intel_display_error_state *error; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16096 | int transcoders[] = { |
| 16097 | TRANSCODER_A, |
| 16098 | TRANSCODER_B, |
| 16099 | TRANSCODER_C, |
| 16100 | TRANSCODER_EDP, |
| 16101 | }; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16102 | int i; |
| 16103 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16104 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 16105 | return NULL; |
| 16106 | |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 16107 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16108 | if (error == NULL) |
| 16109 | return NULL; |
| 16110 | |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 16111 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 16112 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
| 16113 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 16114 | for_each_pipe(dev_priv, i) { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16115 | error->pipe[i].power_domain_on = |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 16116 | __intel_display_power_is_enabled(dev_priv, |
| 16117 | POWER_DOMAIN_PIPE(i)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16118 | if (!error->pipe[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 16119 | continue; |
| 16120 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 16121 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 16122 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 16123 | error->cursor[i].base = I915_READ(CURBASE(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16124 | |
| 16125 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 16126 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 16127 | if (INTEL_INFO(dev)->gen <= 3) { |
Paulo Zanoni | 51889b3 | 2013-03-06 20:03:13 -0300 | [diff] [blame] | 16128 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 16129 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
| 16130 | } |
Paulo Zanoni | ca29136 | 2013-03-06 20:03:14 -0300 | [diff] [blame] | 16131 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
| 16132 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16133 | if (INTEL_INFO(dev)->gen >= 4) { |
| 16134 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 16135 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 16136 | } |
| 16137 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16138 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 16139 | |
Sonika Jindal | 3abfce7 | 2014-07-21 15:23:43 +0530 | [diff] [blame] | 16140 | if (HAS_GMCH_DISPLAY(dev)) |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 16141 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16142 | } |
| 16143 | |
| 16144 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
| 16145 | if (HAS_DDI(dev_priv->dev)) |
| 16146 | error->num_transcoders++; /* Account for eDP. */ |
| 16147 | |
| 16148 | for (i = 0; i < error->num_transcoders; i++) { |
| 16149 | enum transcoder cpu_transcoder = transcoders[i]; |
| 16150 | |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16151 | error->transcoder[i].power_domain_on = |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 16152 | __intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 38cc1da | 2013-12-20 15:09:41 -0200 | [diff] [blame] | 16153 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16154 | if (!error->transcoder[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 16155 | continue; |
| 16156 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16157 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 16158 | |
| 16159 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
| 16160 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
| 16161 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
| 16162 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 16163 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
| 16164 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
| 16165 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16166 | } |
| 16167 | |
| 16168 | return error; |
| 16169 | } |
| 16170 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16171 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 16172 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16173 | void |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16174 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16175 | struct drm_device *dev, |
| 16176 | struct intel_display_error_state *error) |
| 16177 | { |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 16178 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16179 | int i; |
| 16180 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16181 | if (!error) |
| 16182 | return; |
| 16183 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16184 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 16185 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16186 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 16187 | error->power_well_driver); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 16188 | for_each_pipe(dev_priv, i) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16189 | err_printf(m, "Pipe [%d]:\n", i); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16190 | err_printf(m, " Power: %s\n", |
| 16191 | error->pipe[i].power_domain_on ? "on" : "off"); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16192 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
Imre Deak | f301b1e1 | 2014-04-18 15:55:04 +0300 | [diff] [blame] | 16193 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16194 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16195 | err_printf(m, "Plane [%d]:\n", i); |
| 16196 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 16197 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 16198 | if (INTEL_INFO(dev)->gen <= 3) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16199 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 16200 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 16201 | } |
Paulo Zanoni | 4b71a57 | 2013-03-22 14:19:21 -0300 | [diff] [blame] | 16202 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16203 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16204 | if (INTEL_INFO(dev)->gen >= 4) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16205 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 16206 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16207 | } |
| 16208 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 16209 | err_printf(m, "Cursor [%d]:\n", i); |
| 16210 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 16211 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 16212 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16213 | } |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16214 | |
| 16215 | for (i = 0; i < error->num_transcoders; i++) { |
Chris Wilson | 1cf84bb | 2013-10-21 09:10:33 +0100 | [diff] [blame] | 16216 | err_printf(m, "CPU transcoder: %c\n", |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16217 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 16218 | err_printf(m, " Power: %s\n", |
| 16219 | error->transcoder[i].power_domain_on ? "on" : "off"); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 16220 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
| 16221 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
| 16222 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
| 16223 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
| 16224 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
| 16225 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
| 16226 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
| 16227 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 16228 | } |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 16229 | |
| 16230 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) |
| 16231 | { |
| 16232 | struct intel_crtc *crtc; |
| 16233 | |
| 16234 | for_each_intel_crtc(dev, crtc) { |
| 16235 | struct intel_unpin_work *work; |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 16236 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 16237 | spin_lock_irq(&dev->event_lock); |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 16238 | |
| 16239 | work = crtc->unpin_work; |
| 16240 | |
| 16241 | if (work && work->event && |
| 16242 | work->event->base.file_priv == file) { |
| 16243 | kfree(work->event); |
| 16244 | work->event = NULL; |
| 16245 | } |
| 16246 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 16247 | spin_unlock_irq(&dev->event_lock); |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 16248 | } |
| 16249 | } |