blob: 659f295824069dcd1cd69432efed01e080f81b2a [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00002/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04003 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00005 * Copyright (c) 2008 Marvell Semiconductor
6 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02007 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
Vivien Didelot4333d612017-03-28 15:10:36 -04009 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 */
12
Vivien Didelot19fb7f62019-08-09 18:47:55 -040013#include <linux/bitfield.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000014#include <linux/delay.h>
Vladimir Oltean5bded822021-10-07 19:47:11 +030015#include <linux/dsa/mv88e6xxx.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070016#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020017#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070018#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020019#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000022#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000023#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020024#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000025#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040026#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020027#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020028#include <linux/of_mdio.h>
Andrew Lunn877b7cb2018-05-19 22:31:34 +020029#include <linux/platform_data/mv88e6xxx.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000030#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010031#include <linux/gpio/consumer.h>
Russell Kingc9a23562018-05-10 13:17:35 -070032#include <linux/phylink.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000033#include <net/dsa.h>
Vivien Didelotec561272016-09-02 14:45:33 -040034
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -040035#include "chip.h"
Andrew Lunn9dd43aa2020-09-18 21:11:05 +020036#include "devlink.h"
Vivien Didelota935c052016-09-29 12:21:53 -040037#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040038#include "global2.h"
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +010039#include "hwtstamp.h"
Andrew Lunn10fa5bf2017-05-26 01:03:20 +020040#include "phy.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010041#include "port.h"
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +010042#include "ptp.h"
Andrew Lunn6d917822017-05-26 01:03:21 +020043#include "serdes.h"
Vivien Didelote7ba0fa2019-05-03 19:28:22 -040044#include "smi.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000045
Vivien Didelotfad09c72016-06-21 12:28:20 -040046static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040047{
Vivien Didelotfad09c72016-06-21 12:28:20 -040048 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040050 dump_stack();
51 }
52}
53
Vivien Didelotec561272016-09-02 14:45:33 -040054int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040055{
56 int err;
57
Vivien Didelotfad09c72016-06-21 12:28:20 -040058 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040059
Vivien Didelotfad09c72016-06-21 12:28:20 -040060 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040061 if (err)
62 return err;
63
Vivien Didelotfad09c72016-06-21 12:28:20 -040064 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040065 addr, reg, *val);
66
67 return 0;
68}
69
Vivien Didelotec561272016-09-02 14:45:33 -040070int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040071{
72 int err;
73
Vivien Didelotfad09c72016-06-21 12:28:20 -040074 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040075
Vivien Didelotfad09c72016-06-21 12:28:20 -040076 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040077 if (err)
78 return err;
79
Vivien Didelotfad09c72016-06-21 12:28:20 -040080 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040081 addr, reg, val);
82
83 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000084}
85
Vivien Didelot683f2242019-08-09 18:47:54 -040086int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88{
89 u16 data;
90 int err;
91 int i;
92
93 /* There's no bus specific operation to wait for a mask */
94 for (i = 0; i < 16; i++) {
95 err = mv88e6xxx_read(chip, addr, reg, &data);
96 if (err)
97 return err;
98
99 if ((data & mask) == val)
100 return 0;
101
102 usleep_range(1000, 2000);
103 }
104
105 dev_err(chip->dev, "Timeout while waiting for switch\n");
106 return -ETIMEDOUT;
107}
108
Vivien Didelot19fb7f62019-08-09 18:47:55 -0400109int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
110 int bit, int val)
111{
112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
113 val ? BIT(bit) : 0x0000);
114}
115
Andrew Lunn10fa5bf2017-05-26 01:03:20 +0200116struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
Andrew Lunna3c53be52017-01-24 14:53:50 +0100117{
118 struct mv88e6xxx_mdio_bus *mdio_bus;
119
120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
121 list);
122 if (!mdio_bus)
123 return NULL;
124
125 return mdio_bus->bus;
126}
127
Andrew Lunndc30c352016-10-16 19:56:49 +0200128static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
129{
130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
131 unsigned int n = d->hwirq;
132
133 chip->g1_irq.masked |= (1 << n);
134}
135
136static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
137{
138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
139 unsigned int n = d->hwirq;
140
141 chip->g1_irq.masked &= ~(1 << n);
142}
143
Andrew Lunn294d7112018-02-22 22:58:32 +0100144static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200145{
Andrew Lunndc30c352016-10-16 19:56:49 +0200146 unsigned int nhandled = 0;
147 unsigned int sub_irq;
148 unsigned int n;
149 u16 reg;
John David Anglin7c0db242019-02-11 13:40:21 -0500150 u16 ctl1;
Andrew Lunndc30c352016-10-16 19:56:49 +0200151 int err;
152
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000153 mv88e6xxx_reg_lock(chip);
Vivien Didelot82466922017-06-15 12:13:59 -0400154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000155 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200156
157 if (err)
158 goto out;
159
John David Anglin7c0db242019-02-11 13:40:21 -0500160 do {
161 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
162 if (reg & (1 << n)) {
163 sub_irq = irq_find_mapping(chip->g1_irq.domain,
164 n);
165 handle_nested_irq(sub_irq);
166 ++nhandled;
167 }
Andrew Lunndc30c352016-10-16 19:56:49 +0200168 }
John David Anglin7c0db242019-02-11 13:40:21 -0500169
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000170 mv88e6xxx_reg_lock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
172 if (err)
173 goto unlock;
174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
175unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000176 mv88e6xxx_reg_unlock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500177 if (err)
178 goto out;
179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
180 } while (reg & ctl1);
181
Andrew Lunndc30c352016-10-16 19:56:49 +0200182out:
183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
184}
185
Andrew Lunn294d7112018-02-22 22:58:32 +0100186static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
187{
188 struct mv88e6xxx_chip *chip = dev_id;
189
190 return mv88e6xxx_g1_irq_thread_work(chip);
191}
192
Andrew Lunndc30c352016-10-16 19:56:49 +0200193static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
194{
195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
196
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000197 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200198}
199
200static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
201{
202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
204 u16 reg;
205 int err;
206
Vivien Didelotd77f4322017-06-15 12:14:03 -0400207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200208 if (err)
209 goto out;
210
211 reg &= ~mask;
212 reg |= (~chip->g1_irq.masked & mask);
213
Vivien Didelotd77f4322017-06-15 12:14:03 -0400214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200215 if (err)
216 goto out;
217
218out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000219 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200220}
221
Bhumika Goyal6eb15e22017-08-19 16:25:52 +0530222static const struct irq_chip mv88e6xxx_g1_irq_chip = {
Andrew Lunndc30c352016-10-16 19:56:49 +0200223 .name = "mv88e6xxx-g1",
224 .irq_mask = mv88e6xxx_g1_irq_mask,
225 .irq_unmask = mv88e6xxx_g1_irq_unmask,
226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
228};
229
230static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
231 unsigned int irq,
232 irq_hw_number_t hwirq)
233{
234 struct mv88e6xxx_chip *chip = d->host_data;
235
236 irq_set_chip_data(irq, d->host_data);
237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
238 irq_set_noprobe(irq);
239
240 return 0;
241}
242
243static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
244 .map = mv88e6xxx_g1_irq_domain_map,
245 .xlate = irq_domain_xlate_twocell,
246};
247
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200248/* To be called with reg_lock held */
Andrew Lunn294d7112018-02-22 22:58:32 +0100249static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200250{
251 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100252 u16 mask;
253
Vivien Didelotd77f4322017-06-15 12:14:03 -0400254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3460a572016-11-20 20:14:16 +0100257
Andreas Färber5edef2f2016-11-27 23:26:28 +0100258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100259 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200260 irq_dispose_mapping(virq);
261 }
262
Andrew Lunna3db3d32016-11-20 20:14:14 +0100263 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200264}
265
Andrew Lunn294d7112018-02-22 22:58:32 +0100266static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
267{
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200268 /*
269 * free_irq must be called without reg_lock taken because the irq
270 * handler takes this lock, too.
271 */
Andrew Lunn294d7112018-02-22 22:58:32 +0100272 free_irq(chip->irq, chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200273
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000274 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200275 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000276 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100277}
278
279static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200280{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100281 int err, irq, virq;
282 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200283
284 chip->g1_irq.nirqs = chip->info->g1_irqs;
285 chip->g1_irq.domain = irq_domain_add_simple(
286 NULL, chip->g1_irq.nirqs, 0,
287 &mv88e6xxx_g1_irq_domain_ops, chip);
288 if (!chip->g1_irq.domain)
289 return -ENOMEM;
290
291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
292 irq_create_mapping(chip->g1_irq.domain, irq);
293
294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
295 chip->g1_irq.masked = ~0;
296
Vivien Didelotd77f4322017-06-15 12:14:03 -0400297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200298 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100299 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200300
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200302
Vivien Didelotd77f4322017-06-15 12:14:03 -0400303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200304 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100305 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200306
307 /* Reading the interrupt status clears (most of) them */
Vivien Didelot82466922017-06-15 12:13:59 -0400308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200309 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100310 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200311
Andrew Lunndc30c352016-10-16 19:56:49 +0200312 return 0;
313
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100314out_disable:
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100317
318out_mapping:
319 for (irq = 0; irq < 16; irq++) {
320 virq = irq_find_mapping(chip->g1_irq.domain, irq);
321 irq_dispose_mapping(virq);
322 }
323
324 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200325
326 return err;
327}
328
Andrew Lunn294d7112018-02-22 22:58:32 +0100329static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
330{
Andrew Lunnf6d97582019-02-23 17:43:56 +0100331 static struct lock_class_key lock_key;
332 static struct lock_class_key request_key;
Andrew Lunn294d7112018-02-22 22:58:32 +0100333 int err;
334
335 err = mv88e6xxx_g1_irq_setup_common(chip);
336 if (err)
337 return err;
338
Andrew Lunnf6d97582019-02-23 17:43:56 +0100339 /* These lock classes tells lockdep that global 1 irqs are in
340 * a different category than their parent GPIO, so it won't
341 * report false recursion.
342 */
343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
344
Andrew Lunn30953832020-01-06 17:13:48 +0100345 snprintf(chip->irq_name, sizeof(chip->irq_name),
346 "mv88e6xxx-%s", dev_name(chip->dev));
347
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000348 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100349 err = request_threaded_irq(chip->irq, NULL,
350 mv88e6xxx_g1_irq_thread_fn,
Marek Behún03403762018-08-30 02:13:50 +0200351 IRQF_ONESHOT | IRQF_SHARED,
Andrew Lunn30953832020-01-06 17:13:48 +0100352 chip->irq_name, chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000353 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100354 if (err)
355 mv88e6xxx_g1_irq_free_common(chip);
356
357 return err;
358}
359
360static void mv88e6xxx_irq_poll(struct kthread_work *work)
361{
362 struct mv88e6xxx_chip *chip = container_of(work,
363 struct mv88e6xxx_chip,
364 irq_poll_work.work);
365 mv88e6xxx_g1_irq_thread_work(chip);
366
367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
368 msecs_to_jiffies(100));
369}
370
371static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
372{
373 int err;
374
375 err = mv88e6xxx_g1_irq_setup_common(chip);
376 if (err)
377 return err;
378
379 kthread_init_delayed_work(&chip->irq_poll_work,
380 mv88e6xxx_irq_poll);
381
Florian Fainelli3f8b8692019-02-21 20:09:27 -0800382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
Andrew Lunn294d7112018-02-22 22:58:32 +0100383 if (IS_ERR(chip->kworker))
384 return PTR_ERR(chip->kworker);
385
386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
387 msecs_to_jiffies(100));
388
389 return 0;
390}
391
392static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
393{
394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
395 kthread_destroy_worker(chip->kworker);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200396
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000397 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200398 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000399 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100400}
401
Russell King64d47d52020-03-14 10:15:38 +0000402static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
403 int port, phy_interface_t interface)
404{
405 int err;
406
407 if (chip->info->ops->port_set_rgmii_delay) {
408 err = chip->info->ops->port_set_rgmii_delay(chip, port,
409 interface);
410 if (err && err != -EOPNOTSUPP)
411 return err;
412 }
413
414 if (chip->info->ops->port_set_cmode) {
415 err = chip->info->ops->port_set_cmode(chip, port,
416 interface);
417 if (err && err != -EOPNOTSUPP)
418 return err;
419 }
420
421 return 0;
422}
423
Russell Kinga5a68582020-03-14 10:15:43 +0000424static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
425 int link, int speed, int duplex, int pause,
426 phy_interface_t mode)
Vivien Didelotd78343d2016-11-04 03:23:36 +0100427{
428 int err;
429
430 if (!chip->info->ops->port_set_link)
431 return 0;
432
433 /* Port's MAC control must not be changed unless the link is down */
Hubert Feurstein43c8e0a2019-07-30 12:11:42 +0200434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100435 if (err)
436 return err;
437
Russell Kingf365c6f2020-03-14 10:15:53 +0000438 if (chip->info->ops->port_set_speed_duplex) {
439 err = chip->info->ops->port_set_speed_duplex(chip, port,
440 speed, duplex);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100441 if (err && err != -EOPNOTSUPP)
442 goto restore_link;
443 }
444
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
446 mode = chip->info->ops->port_max_speed_mode(port);
447
Andrew Lunn54186b92018-08-09 15:38:37 +0200448 if (chip->info->ops->port_set_pause) {
449 err = chip->info->ops->port_set_pause(chip, port, pause);
450 if (err)
451 goto restore_link;
452 }
453
Russell King64d47d52020-03-14 10:15:38 +0000454 err = mv88e6xxx_port_config_interface(chip, port, mode);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100455restore_link:
456 if (chip->info->ops->port_set_link(chip, port, link))
Vivien Didelot774439e52017-06-08 18:34:08 -0400457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100458
459 return err;
460}
461
Marek Vasutd700ec42018-09-12 00:15:24 +0200462static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
463{
464 struct mv88e6xxx_chip *chip = ds->priv;
465
466 return port < chip->info->num_internal_phys;
467}
468
Russell King5d5b2312020-03-14 10:16:03 +0000469static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
470{
471 u16 reg;
472 int err;
473
Russell King (Oracle)2b29cb92021-12-07 10:32:43 +0000474 /* The 88e6250 family does not have the PHY detect bit. Instead,
475 * report whether the port is internal.
476 */
477 if (chip->info->family == MV88E6XXX_FAMILY_6250)
478 return port < chip->info->num_internal_phys;
479
Russell King5d5b2312020-03-14 10:16:03 +0000480 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
481 if (err) {
482 dev_err(chip->dev,
483 "p%d: %s: failed to read port status\n",
484 port, __func__);
485 return err;
486 }
487
488 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
489}
490
Russell Kinga5a68582020-03-14 10:15:43 +0000491static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
492 struct phylink_link_state *state)
493{
494 struct mv88e6xxx_chip *chip = ds->priv;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100495 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000496 int err;
497
498 mv88e6xxx_reg_lock(chip);
499 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100500 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
Russell Kinga5a68582020-03-14 10:15:43 +0000501 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
502 state);
503 else
504 err = -EOPNOTSUPP;
505 mv88e6xxx_reg_unlock(chip);
506
507 return err;
508}
509
510static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
511 unsigned int mode,
512 phy_interface_t interface,
513 const unsigned long *advertise)
514{
515 const struct mv88e6xxx_ops *ops = chip->info->ops;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100516 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000517
518 if (ops->serdes_pcs_config) {
519 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100520 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000521 return ops->serdes_pcs_config(chip, port, lane, mode,
522 interface, advertise);
523 }
524
525 return 0;
526}
527
528static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
529{
530 struct mv88e6xxx_chip *chip = ds->priv;
531 const struct mv88e6xxx_ops *ops;
532 int err = 0;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100533 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000534
535 ops = chip->info->ops;
536
537 if (ops->serdes_pcs_an_restart) {
538 mv88e6xxx_reg_lock(chip);
539 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100540 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000541 err = ops->serdes_pcs_an_restart(chip, port, lane);
542 mv88e6xxx_reg_unlock(chip);
543
544 if (err)
545 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
546 }
547}
548
549static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
550 unsigned int mode,
551 int speed, int duplex)
552{
553 const struct mv88e6xxx_ops *ops = chip->info->ops;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100554 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000555
556 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
557 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100558 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000559 return ops->serdes_pcs_link_up(chip, port, lane,
560 speed, duplex);
561 }
562
563 return 0;
564}
565
Russell King6c422e32018-08-09 15:38:39 +0200566static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
567 unsigned long *mask,
568 struct phylink_link_state *state)
569{
570 if (!phy_interface_mode_is_8023z(state->interface)) {
571 /* 10M and 100M are only supported in non-802.3z mode */
572 phylink_set(mask, 10baseT_Half);
573 phylink_set(mask, 10baseT_Full);
574 phylink_set(mask, 100baseT_Half);
575 phylink_set(mask, 100baseT_Full);
576 }
577}
578
579static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
580 unsigned long *mask,
581 struct phylink_link_state *state)
582{
583 /* FIXME: if the port is in 1000Base-X mode, then it only supports
584 * 1000M FD speeds. In this case, CMODE will indicate 5.
585 */
586 phylink_set(mask, 1000baseT_Full);
587 phylink_set(mask, 1000baseX_Full);
588
589 mv88e6065_phylink_validate(chip, port, mask, state);
590}
591
Marek Behúne3af71a2019-02-25 12:39:55 +0100592static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
593 unsigned long *mask,
594 struct phylink_link_state *state)
595{
596 if (port >= 5)
597 phylink_set(mask, 2500baseX_Full);
598
599 /* No ethtool bits for 200Mbps */
600 phylink_set(mask, 1000baseT_Full);
601 phylink_set(mask, 1000baseX_Full);
602
603 mv88e6065_phylink_validate(chip, port, mask, state);
604}
605
Russell King6c422e32018-08-09 15:38:39 +0200606static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
607 unsigned long *mask,
608 struct phylink_link_state *state)
609{
610 /* No ethtool bits for 200Mbps */
611 phylink_set(mask, 1000baseT_Full);
612 phylink_set(mask, 1000baseX_Full);
613
614 mv88e6065_phylink_validate(chip, port, mask, state);
615}
616
617static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
618 unsigned long *mask,
619 struct phylink_link_state *state)
620{
Andrew Lunnec260162019-02-08 22:25:44 +0100621 if (port >= 9) {
Russell King6c422e32018-08-09 15:38:39 +0200622 phylink_set(mask, 2500baseX_Full);
Andrew Lunnec260162019-02-08 22:25:44 +0100623 phylink_set(mask, 2500baseT_Full);
624 }
Russell King6c422e32018-08-09 15:38:39 +0200625
626 /* No ethtool bits for 200Mbps */
627 phylink_set(mask, 1000baseT_Full);
628 phylink_set(mask, 1000baseX_Full);
629
630 mv88e6065_phylink_validate(chip, port, mask, state);
631}
632
633static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
634 unsigned long *mask,
635 struct phylink_link_state *state)
636{
637 if (port >= 9) {
638 phylink_set(mask, 10000baseT_Full);
639 phylink_set(mask, 10000baseKR_Full);
640 }
641
642 mv88e6390_phylink_validate(chip, port, mask, state);
643}
644
Pavana Sharmade776d02021-03-17 14:46:42 +0100645static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
646 unsigned long *mask,
647 struct phylink_link_state *state)
648{
Marek Behúndc2fc9f2021-11-04 18:17:47 +0100649 bool is_6191x =
650 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
651
652 if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
Pavana Sharmade776d02021-03-17 14:46:42 +0100653 phylink_set(mask, 10000baseT_Full);
654 phylink_set(mask, 10000baseKR_Full);
655 phylink_set(mask, 10000baseCR_Full);
656 phylink_set(mask, 10000baseSR_Full);
657 phylink_set(mask, 10000baseLR_Full);
658 phylink_set(mask, 10000baseLRM_Full);
659 phylink_set(mask, 10000baseER_Full);
660 phylink_set(mask, 5000baseT_Full);
661 phylink_set(mask, 2500baseX_Full);
662 phylink_set(mask, 2500baseT_Full);
663 }
664
665 phylink_set(mask, 1000baseT_Full);
666 phylink_set(mask, 1000baseX_Full);
667
668 mv88e6065_phylink_validate(chip, port, mask, state);
669}
670
Russell Kingc9a23562018-05-10 13:17:35 -0700671static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
672 unsigned long *supported,
673 struct phylink_link_state *state)
674{
Russell King6c422e32018-08-09 15:38:39 +0200675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
676 struct mv88e6xxx_chip *chip = ds->priv;
677
678 /* Allow all the expected bits */
679 phylink_set(mask, Autoneg);
680 phylink_set(mask, Pause);
681 phylink_set_port_modes(mask);
682
683 if (chip->info->ops->phylink_validate)
684 chip->info->ops->phylink_validate(chip, port, mask, state);
685
Sean Anderson49730562021-10-22 18:41:04 -0400686 linkmode_and(supported, supported, mask);
687 linkmode_and(state->advertising, state->advertising, mask);
Russell King6c422e32018-08-09 15:38:39 +0200688
689 /* We can only operate at 2500BaseX or 1000BaseX. If requested
690 * to advertise both, only report advertising at 2500BaseX.
691 */
692 phylink_helper_basex_speed(state);
Russell Kingc9a23562018-05-10 13:17:35 -0700693}
694
Russell Kingc9a23562018-05-10 13:17:35 -0700695static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
696 unsigned int mode,
697 const struct phylink_link_state *state)
698{
699 struct mv88e6xxx_chip *chip = ds->priv;
Russell Kingfad58192020-07-19 12:00:35 +0100700 struct mv88e6xxx_port *p;
Russell King (Oracle)04ec4e62021-12-09 09:26:47 +0000701 int err = 0;
Russell Kingc9a23562018-05-10 13:17:35 -0700702
Russell Kingfad58192020-07-19 12:00:35 +0100703 p = &chip->ports[port];
704
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000705 mv88e6xxx_reg_lock(chip);
Russell Kingfad58192020-07-19 12:00:35 +0100706
Russell King (Oracle)04ec4e62021-12-09 09:26:47 +0000707 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
708 /* In inband mode, the link may come up at any time while the
709 * link is not forced down. Force the link down while we
710 * reconfigure the interface mode.
711 */
712 if (mode == MLO_AN_INBAND &&
713 p->interface != state->interface &&
714 chip->info->ops->port_set_link)
715 chip->info->ops->port_set_link(chip, port,
716 LINK_FORCED_DOWN);
Russell Kinga5a68582020-03-14 10:15:43 +0000717
Russell King (Oracle)04ec4e62021-12-09 09:26:47 +0000718 err = mv88e6xxx_port_config_interface(chip, port,
719 state->interface);
720 if (err && err != -EOPNOTSUPP)
721 goto err_unlock;
722
723 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
724 state->interface,
725 state->advertising);
726 /* FIXME: we should restart negotiation if something changed -
727 * which is something we get if we convert to using phylinks
728 * PCS operations.
729 */
730 if (err > 0)
731 err = 0;
732 }
Russell Kinga5a68582020-03-14 10:15:43 +0000733
Russell Kingfad58192020-07-19 12:00:35 +0100734 /* Undo the forced down state above after completing configuration
Russell King (Oracle)04ec4e62021-12-09 09:26:47 +0000735 * irrespective of its state on entry, which allows the link to come
736 * up in the in-band case where there is no separate SERDES. Also
737 * ensure that the link can come up if the PPU is in use and we are
738 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
Russell Kingfad58192020-07-19 12:00:35 +0100739 */
Russell King (Oracle)04ec4e62021-12-09 09:26:47 +0000740 if (chip->info->ops->port_set_link &&
741 ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
742 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
Russell Kingfad58192020-07-19 12:00:35 +0100743 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
744
745 p->interface = state->interface;
746
Russell Kinga5a68582020-03-14 10:15:43 +0000747err_unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000748 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700749
750 if (err && err != -EOPNOTSUPP)
Russell King64d47d52020-03-14 10:15:38 +0000751 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700752}
753
Russell Kingc9a23562018-05-10 13:17:35 -0700754static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
755 unsigned int mode,
756 phy_interface_t interface)
757{
Russell King30c4a5b2020-02-26 10:23:51 +0000758 struct mv88e6xxx_chip *chip = ds->priv;
759 const struct mv88e6xxx_ops *ops;
760 int err = 0;
761
762 ops = chip->info->ops;
763
Russell King5d5b2312020-03-14 10:16:03 +0000764 mv88e6xxx_reg_lock(chip);
Russell King (Oracle)2b29cb92021-12-07 10:32:43 +0000765 /* Force the link down if we know the port may not be automatically
766 * updated by the switch or if we are using fixed-link mode.
Maarten Zanders4a3e0ae2021-10-11 16:27:20 +0200767 */
Russell King (Oracle)2b29cb92021-12-07 10:32:43 +0000768 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
Chris Packham4efe76622020-11-24 17:34:37 +1300769 mode == MLO_AN_FIXED) && ops->port_sync_link)
770 err = ops->port_sync_link(chip, port, mode, false);
Marek Behún9d591fc2021-12-11 23:51:41 +0100771
772 if (!err && ops->port_set_speed_duplex)
773 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
774 DUPLEX_UNFORCED);
Russell King5d5b2312020-03-14 10:16:03 +0000775 mv88e6xxx_reg_unlock(chip);
Russell King30c4a5b2020-02-26 10:23:51 +0000776
Russell King5d5b2312020-03-14 10:16:03 +0000777 if (err)
778 dev_err(chip->dev,
779 "p%d: failed to force MAC link down\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700780}
781
782static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
783 unsigned int mode, phy_interface_t interface,
Russell King5b502a72020-02-26 10:23:46 +0000784 struct phy_device *phydev,
785 int speed, int duplex,
786 bool tx_pause, bool rx_pause)
Russell Kingc9a23562018-05-10 13:17:35 -0700787{
Russell King30c4a5b2020-02-26 10:23:51 +0000788 struct mv88e6xxx_chip *chip = ds->priv;
789 const struct mv88e6xxx_ops *ops;
790 int err = 0;
791
792 ops = chip->info->ops;
793
Russell King5d5b2312020-03-14 10:16:03 +0000794 mv88e6xxx_reg_lock(chip);
Russell King (Oracle)2b29cb92021-12-07 10:32:43 +0000795 /* Configure and force the link up if we know that the port may not
796 * automatically updated by the switch or if we are using fixed-link
797 * mode.
Maarten Zanders4a3e0ae2021-10-11 16:27:20 +0200798 */
Russell King (Oracle)2b29cb92021-12-07 10:32:43 +0000799 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
Maarten Zanders4a3e0ae2021-10-11 16:27:20 +0200800 mode == MLO_AN_FIXED) {
Russell King30c4a5b2020-02-26 10:23:51 +0000801 /* FIXME: for an automedia port, should we force the link
802 * down here - what if the link comes up due to "other" media
803 * while we're bringing the port up, how is the exclusivity
Russell Kinga5a68582020-03-14 10:15:43 +0000804 * handled in the Marvell hardware? E.g. port 2 on 88E6390
Russell King30c4a5b2020-02-26 10:23:51 +0000805 * shared between internal PHY and Serdes.
806 */
Russell Kinga5a68582020-03-14 10:15:43 +0000807 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
808 duplex);
809 if (err)
810 goto error;
811
Russell Kingf365c6f2020-03-14 10:15:53 +0000812 if (ops->port_set_speed_duplex) {
813 err = ops->port_set_speed_duplex(chip, port,
814 speed, duplex);
Russell King30c4a5b2020-02-26 10:23:51 +0000815 if (err && err != -EOPNOTSUPP)
816 goto error;
817 }
818
Chris Packham4efe76622020-11-24 17:34:37 +1300819 if (ops->port_sync_link)
820 err = ops->port_sync_link(chip, port, mode, true);
Russell King30c4a5b2020-02-26 10:23:51 +0000821 }
Russell King5d5b2312020-03-14 10:16:03 +0000822error:
823 mv88e6xxx_reg_unlock(chip);
824
825 if (err && err != -EOPNOTSUPP)
826 dev_err(ds->dev,
827 "p%d: failed to configure MAC link up\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700828}
829
Andrew Lunna605a0f2016-11-21 23:26:58 +0100830static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000831{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100832 if (!chip->info->ops->stats_snapshot)
833 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000834
Andrew Lunna605a0f2016-11-21 23:26:58 +0100835 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000836}
837
Andrew Lunne413e7e2015-04-02 04:06:38 +0200838static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100839 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
840 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
841 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
842 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
843 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
844 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
845 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
846 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
847 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
848 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
849 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
850 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
851 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
852 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
853 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
854 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
855 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
856 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
857 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
858 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
859 { "single", 4, 0x14, STATS_TYPE_BANK0, },
860 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
861 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
862 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
863 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
864 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
865 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
866 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
867 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
868 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
869 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
870 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
871 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
872 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
873 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
874 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
875 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
876 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
877 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
878 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
879 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
880 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
881 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
882 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
883 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
884 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
885 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
886 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
887 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
888 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
889 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
890 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
891 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
892 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
893 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
894 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
895 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
896 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
897 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200898};
899
Vivien Didelotfad09c72016-06-21 12:28:20 -0400900static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100901 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100902 int port, u16 bank1_select,
903 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200904{
Andrew Lunn80c46272015-06-20 18:42:30 +0200905 u32 low;
906 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100907 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200908 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200909 u64 value;
910
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100911 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100912 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200913 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
914 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800915 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200916
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200917 low = reg;
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100918 if (s->size == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200919 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
920 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800921 return U64_MAX;
Rasmus Villemoes84b3fd12019-05-29 07:02:11 +0000922 low |= ((u32)reg) << 16;
Andrew Lunn80c46272015-06-20 18:42:30 +0200923 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100924 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100925 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100926 reg = bank1_select;
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -0500927 fallthrough;
Andrew Lunndfafe442016-11-21 23:27:02 +0100928 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100929 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100930 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100931 if (s->size == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100932 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Gustavo A. R. Silva9fc3e4d2017-05-11 22:11:29 -0500933 break;
934 default:
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800935 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200936 }
Andrew Lunn6e46e2d2019-02-28 18:14:03 +0100937 value = (((u64)high) << 32) | low;
Andrew Lunn80c46272015-06-20 18:42:30 +0200938 return value;
939}
940
Andrew Lunn436fe172018-03-01 02:02:29 +0100941static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
942 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100943{
944 struct mv88e6xxx_hw_stat *stat;
945 int i, j;
946
947 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
948 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100949 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100950 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
951 ETH_GSTRING_LEN);
952 j++;
953 }
954 }
Andrew Lunn436fe172018-03-01 02:02:29 +0100955
956 return j;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100957}
958
Andrew Lunn436fe172018-03-01 02:02:29 +0100959static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
960 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100961{
Andrew Lunn436fe172018-03-01 02:02:29 +0100962 return mv88e6xxx_stats_get_strings(chip, data,
963 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
Andrew Lunndfafe442016-11-21 23:27:02 +0100964}
965
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000966static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
967 uint8_t *data)
968{
969 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
970}
971
Andrew Lunn436fe172018-03-01 02:02:29 +0100972static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
973 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100974{
Andrew Lunn436fe172018-03-01 02:02:29 +0100975 return mv88e6xxx_stats_get_strings(chip, data,
976 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
Andrew Lunndfafe442016-11-21 23:27:02 +0100977}
978
Andrew Lunn65f60e42018-03-28 23:50:28 +0200979static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
980 "atu_member_violation",
981 "atu_miss_violation",
982 "atu_full_violation",
983 "vtu_member_violation",
984 "vtu_miss_violation",
985};
986
987static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
988{
989 unsigned int i;
990
991 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
992 strlcpy(data + i * ETH_GSTRING_LEN,
993 mv88e6xxx_atu_vtu_stats_strings[i],
994 ETH_GSTRING_LEN);
995}
996
Andrew Lunndfafe442016-11-21 23:27:02 +0100997static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
Florian Fainelli89f09042018-04-25 12:12:50 -0700998 u32 stringset, uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100999{
Vivien Didelot04bed142016-08-31 18:06:13 -04001000 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +01001001 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +01001002
Florian Fainelli89f09042018-04-25 12:12:50 -07001003 if (stringset != ETH_SS_STATS)
1004 return;
1005
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001006 mv88e6xxx_reg_lock(chip);
Andrew Lunnc6c8cd52018-03-01 02:02:28 +01001007
Andrew Lunndfafe442016-11-21 23:27:02 +01001008 if (chip->info->ops->stats_get_strings)
Andrew Lunn436fe172018-03-01 02:02:29 +01001009 count = chip->info->ops->stats_get_strings(chip, data);
1010
1011 if (chip->info->ops->serdes_get_strings) {
1012 data += count * ETH_GSTRING_LEN;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001013 count = chip->info->ops->serdes_get_strings(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001014 }
Andrew Lunnc6c8cd52018-03-01 02:02:28 +01001015
Andrew Lunn65f60e42018-03-28 23:50:28 +02001016 data += count * ETH_GSTRING_LEN;
1017 mv88e6xxx_atu_vtu_get_strings(data);
1018
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001019 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001020}
1021
1022static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1023 int types)
1024{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +01001025 struct mv88e6xxx_hw_stat *stat;
1026 int i, j;
1027
1028 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1029 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +01001030 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +01001031 j++;
1032 }
1033 return j;
1034}
1035
Andrew Lunndfafe442016-11-21 23:27:02 +01001036static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1037{
1038 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1039 STATS_TYPE_PORT);
1040}
1041
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001042static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1043{
1044 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1045}
1046
Andrew Lunndfafe442016-11-21 23:27:02 +01001047static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1048{
1049 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1050 STATS_TYPE_BANK1);
1051}
1052
Florian Fainelli89f09042018-04-25 12:12:50 -07001053static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
Andrew Lunndfafe442016-11-21 23:27:02 +01001054{
1055 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +01001056 int serdes_count = 0;
1057 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +01001058
Florian Fainelli89f09042018-04-25 12:12:50 -07001059 if (sset != ETH_SS_STATS)
1060 return 0;
1061
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001062 mv88e6xxx_reg_lock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001063 if (chip->info->ops->stats_get_sset_count)
Andrew Lunn436fe172018-03-01 02:02:29 +01001064 count = chip->info->ops->stats_get_sset_count(chip);
1065 if (count < 0)
1066 goto out;
1067
1068 if (chip->info->ops->serdes_get_sset_count)
1069 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1070 port);
Andrew Lunn65f60e42018-03-28 23:50:28 +02001071 if (serdes_count < 0) {
Andrew Lunn436fe172018-03-01 02:02:29 +01001072 count = serdes_count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001073 goto out;
1074 }
1075 count += serdes_count;
1076 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1077
Andrew Lunn436fe172018-03-01 02:02:29 +01001078out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001079 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001080
Andrew Lunn436fe172018-03-01 02:02:29 +01001081 return count;
Andrew Lunndfafe442016-11-21 23:27:02 +01001082}
1083
Andrew Lunn436fe172018-03-01 02:02:29 +01001084static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1085 uint64_t *data, int types,
1086 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +01001087{
1088 struct mv88e6xxx_hw_stat *stat;
1089 int i, j;
1090
1091 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1092 stat = &mv88e6xxx_hw_stats[i];
1093 if (stat->type & types) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001094 mv88e6xxx_reg_lock(chip);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001095 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1096 bank1_select,
1097 histogram);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001098 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001099
Andrew Lunn052f9472016-11-21 23:27:03 +01001100 j++;
1101 }
1102 }
Andrew Lunn436fe172018-03-01 02:02:29 +01001103 return j;
Andrew Lunn052f9472016-11-21 23:27:03 +01001104}
1105
Andrew Lunn436fe172018-03-01 02:02:29 +01001106static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1107 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001108{
1109 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001110 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001111 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +01001112}
1113
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001114static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1115 uint64_t *data)
1116{
1117 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1118 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1119}
1120
Andrew Lunn436fe172018-03-01 02:02:29 +01001121static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1122 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001123{
1124 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001126 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1127 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001128}
1129
Andrew Lunn436fe172018-03-01 02:02:29 +01001130static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1131 uint64_t *data)
Andrew Lunne0d8b612016-11-21 23:27:04 +01001132{
1133 return mv88e6xxx_stats_get_stats(chip, port, data,
1134 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001135 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1136 0);
Andrew Lunn052f9472016-11-21 23:27:03 +01001137}
1138
Andrew Lunn65f60e42018-03-28 23:50:28 +02001139static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1140 uint64_t *data)
1141{
1142 *data++ = chip->ports[port].atu_member_violation;
1143 *data++ = chip->ports[port].atu_miss_violation;
1144 *data++ = chip->ports[port].atu_full_violation;
1145 *data++ = chip->ports[port].vtu_member_violation;
1146 *data++ = chip->ports[port].vtu_miss_violation;
1147}
1148
Andrew Lunn052f9472016-11-21 23:27:03 +01001149static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1150 uint64_t *data)
1151{
Andrew Lunn436fe172018-03-01 02:02:29 +01001152 int count = 0;
1153
Andrew Lunn052f9472016-11-21 23:27:03 +01001154 if (chip->info->ops->stats_get_stats)
Andrew Lunn436fe172018-03-01 02:02:29 +01001155 count = chip->info->ops->stats_get_stats(chip, port, data);
1156
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001157 mv88e6xxx_reg_lock(chip);
Andrew Lunn436fe172018-03-01 02:02:29 +01001158 if (chip->info->ops->serdes_get_stats) {
1159 data += count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001160 count = chip->info->ops->serdes_get_stats(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001161 }
Andrew Lunn65f60e42018-03-28 23:50:28 +02001162 data += count;
1163 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001164 mv88e6xxx_reg_unlock(chip);
Andrew Lunn052f9472016-11-21 23:27:03 +01001165}
1166
Vivien Didelotf81ec902016-05-09 13:22:58 -04001167static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1168 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001169{
Vivien Didelot04bed142016-08-31 18:06:13 -04001170 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001171 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001172
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001173 mv88e6xxx_reg_lock(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001174
Andrew Lunna605a0f2016-11-21 23:26:58 +01001175 ret = mv88e6xxx_stats_snapshot(chip, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001176 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001177
1178 if (ret < 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001179 return;
Andrew Lunn052f9472016-11-21 23:27:03 +01001180
1181 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001182
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001183}
Ben Hutchings98e67302011-11-25 14:36:19 +00001184
Vivien Didelotf81ec902016-05-09 13:22:58 -04001185static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001186{
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001187 struct mv88e6xxx_chip *chip = ds->priv;
1188 int len;
1189
1190 len = 32 * sizeof(u16);
1191 if (chip->info->ops->serdes_get_regs_len)
1192 len += chip->info->ops->serdes_get_regs_len(chip, port);
1193
1194 return len;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001195}
1196
Vivien Didelotf81ec902016-05-09 13:22:58 -04001197static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1198 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001199{
Vivien Didelot04bed142016-08-31 18:06:13 -04001200 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001201 int err;
1202 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001203 u16 *p = _p;
1204 int i;
1205
Vivien Didelota5f39322018-12-17 16:05:21 -05001206 regs->version = chip->info->prod_num;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001207
1208 memset(p, 0xff, 32 * sizeof(u16));
1209
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001210 mv88e6xxx_reg_lock(chip);
Vivien Didelot23062512016-05-09 13:22:45 -04001211
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001212 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001213
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001214 err = mv88e6xxx_port_read(chip, port, i, &reg);
1215 if (!err)
1216 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001217 }
Vivien Didelot23062512016-05-09 13:22:45 -04001218
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001219 if (chip->info->ops->serdes_get_regs)
1220 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1221
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001222 mv88e6xxx_reg_unlock(chip);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001223}
1224
Vivien Didelot08f50062017-08-01 16:32:41 -04001225static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1226 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001227{
Vivien Didelot5480db62017-08-01 16:32:40 -04001228 /* Nothing to do on the port's MAC */
1229 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001230}
1231
Vivien Didelot08f50062017-08-01 16:32:41 -04001232static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1233 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001234{
Vivien Didelot5480db62017-08-01 16:32:40 -04001235 /* Nothing to do on the port's MAC */
1236 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001237}
1238
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001239/* Mask of the local ports allowed to receive frames from a given fabric port */
Vivien Didelote5887a22017-03-30 17:37:11 -04001240static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001241{
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001242 struct dsa_switch *ds = chip->ds;
1243 struct dsa_switch_tree *dst = ds->dst;
Vladimir Oltean65144062021-12-06 18:57:51 +02001244 struct dsa_port *dp, *other_dp;
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001245 bool found = false;
Vivien Didelote5887a22017-03-30 17:37:11 -04001246 u16 pvlan;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001247
Vladimir Olteance5df682021-07-22 18:55:41 +03001248 /* dev is a physical switch */
1249 if (dev <= dst->last_switch) {
1250 list_for_each_entry(dp, &dst->ports, list) {
1251 if (dp->ds->index == dev && dp->index == port) {
1252 /* dp might be a DSA link or a user port, so it
Vladimir Oltean65144062021-12-06 18:57:51 +02001253 * might or might not have a bridge.
1254 * Use the "found" variable for both cases.
Vladimir Olteance5df682021-07-22 18:55:41 +03001255 */
Vladimir Olteance5df682021-07-22 18:55:41 +03001256 found = true;
1257 break;
1258 }
1259 }
1260 /* dev is a virtual bridge */
1261 } else {
1262 list_for_each_entry(dp, &dst->ports, list) {
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001263 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1264
1265 if (!bridge_num)
Vladimir Olteance5df682021-07-22 18:55:41 +03001266 continue;
1267
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001268 if (bridge_num + dst->last_switch != dev)
Vladimir Olteance5df682021-07-22 18:55:41 +03001269 continue;
1270
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001271 found = true;
1272 break;
1273 }
1274 }
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001275
Vladimir Olteance5df682021-07-22 18:55:41 +03001276 /* Prevent frames from unknown switch or virtual bridge */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001277 if (!found)
Vivien Didelote5887a22017-03-30 17:37:11 -04001278 return 0;
1279
1280 /* Frames from DSA links and CPU ports can egress any local port */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001281 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
Vivien Didelote5887a22017-03-30 17:37:11 -04001282 return mv88e6xxx_port_mask(chip);
1283
Vivien Didelote5887a22017-03-30 17:37:11 -04001284 pvlan = 0;
1285
1286 /* Frames from user ports can egress any local DSA links and CPU ports,
1287 * as well as any local member of their bridge group.
1288 */
Vladimir Oltean65144062021-12-06 18:57:51 +02001289 dsa_switch_for_each_port(other_dp, ds)
1290 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1291 other_dp->type == DSA_PORT_TYPE_DSA ||
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001292 dsa_port_bridge_same(dp, other_dp))
Vladimir Oltean65144062021-12-06 18:57:51 +02001293 pvlan |= BIT(other_dp->index);
Vivien Didelote5887a22017-03-30 17:37:11 -04001294
1295 return pvlan;
1296}
1297
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001298static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
Vivien Didelote5887a22017-03-30 17:37:11 -04001299{
1300 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001301
1302 /* prevent frames from going back out of the port they came in on */
1303 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001304
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001305 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001306}
1307
Vivien Didelotf81ec902016-05-09 13:22:58 -04001308static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1309 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001310{
Vivien Didelot04bed142016-08-31 18:06:13 -04001311 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot553eb542016-05-13 20:38:23 -04001312 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001313
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001314 mv88e6xxx_reg_lock(chip);
Vivien Didelotf894c292017-06-08 18:34:10 -04001315 err = mv88e6xxx_port_set_state(chip, port, state);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001316 mv88e6xxx_reg_unlock(chip);
Vivien Didelot553eb542016-05-13 20:38:23 -04001317
1318 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001319 dev_err(ds->dev, "p%d: failed to update state\n", port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001320}
1321
Vivien Didelot93e18d62018-05-11 17:16:35 -04001322static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1323{
1324 int err;
1325
1326 if (chip->info->ops->ieee_pri_map) {
1327 err = chip->info->ops->ieee_pri_map(chip);
1328 if (err)
1329 return err;
1330 }
1331
1332 if (chip->info->ops->ip_pri_map) {
1333 err = chip->info->ops->ip_pri_map(chip);
1334 if (err)
1335 return err;
1336 }
1337
1338 return 0;
1339}
1340
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001341static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1342{
Vivien Didelotc5f51762019-10-30 22:09:13 -04001343 struct dsa_switch *ds = chip->ds;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001344 int target, port;
1345 int err;
1346
1347 if (!chip->info->global2_addr)
1348 return 0;
1349
1350 /* Initialize the routing port to the 32 possible target devices */
1351 for (target = 0; target < 32; target++) {
Vivien Didelotc5f51762019-10-30 22:09:13 -04001352 port = dsa_routing_port(ds, target);
1353 if (port == ds->num_ports)
1354 port = 0x1f;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001355
1356 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1357 if (err)
1358 return err;
1359 }
1360
Vivien Didelot02317e62018-05-09 11:38:49 -04001361 if (chip->info->ops->set_cascade_port) {
1362 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1363 err = chip->info->ops->set_cascade_port(chip, port);
1364 if (err)
1365 return err;
1366 }
1367
Vivien Didelot23c98912018-05-09 11:38:50 -04001368 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1369 if (err)
1370 return err;
1371
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001372 return 0;
1373}
1374
Vivien Didelotb28f8722018-04-26 21:56:44 -04001375static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1376{
1377 /* Clear all trunk masks and mapping */
1378 if (chip->info->global2_addr)
1379 return mv88e6xxx_g2_trunk_clear(chip);
1380
1381 return 0;
1382}
1383
Vivien Didelot9e5baf92018-05-09 11:38:51 -04001384static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1385{
1386 if (chip->info->ops->rmu_disable)
1387 return chip->info->ops->rmu_disable(chip);
1388
1389 return 0;
1390}
1391
Vivien Didelot9e907d72017-07-17 13:03:43 -04001392static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1393{
1394 if (chip->info->ops->pot_clear)
1395 return chip->info->ops->pot_clear(chip);
1396
1397 return 0;
1398}
1399
Vivien Didelot51c901a2017-07-17 13:03:41 -04001400static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1401{
1402 if (chip->info->ops->mgmt_rsvd2cpu)
1403 return chip->info->ops->mgmt_rsvd2cpu(chip);
1404
1405 return 0;
1406}
1407
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001408static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1409{
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001410 int err;
1411
Vivien Didelotdaefc942017-03-11 16:12:54 -05001412 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1413 if (err)
1414 return err;
1415
Rasmus Villemoes49506a92020-12-10 12:06:44 +01001416 /* The chips that have a "learn2all" bit in Global1, ATU
1417 * Control are precisely those whose port registers have a
1418 * Message Port bit in Port Control 1 and hence implement
1419 * ->port_setup_message_port.
1420 */
1421 if (chip->info->ops->port_setup_message_port) {
1422 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1423 if (err)
1424 return err;
1425 }
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001426
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001427 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1428}
1429
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04001430static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1431{
1432 int port;
1433 int err;
1434
1435 if (!chip->info->ops->irl_init_all)
1436 return 0;
1437
1438 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1439 /* Disable ingress rate limiting by resetting all per port
1440 * ingress rate limit resources to their initial state.
1441 */
1442 err = chip->info->ops->irl_init_all(chip, port);
1443 if (err)
1444 return err;
1445 }
1446
1447 return 0;
1448}
1449
Vivien Didelot04a69a12017-10-13 14:18:05 -04001450static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1451{
1452 if (chip->info->ops->set_switch_mac) {
1453 u8 addr[ETH_ALEN];
1454
1455 eth_random_addr(addr);
1456
1457 return chip->info->ops->set_switch_mac(chip, addr);
1458 }
1459
1460 return 0;
1461}
1462
Vivien Didelot17a15942017-03-30 17:37:09 -04001463static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1464{
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001465 struct dsa_switch_tree *dst = chip->ds->dst;
1466 struct dsa_switch *ds;
1467 struct dsa_port *dp;
Vivien Didelot17a15942017-03-30 17:37:09 -04001468 u16 pvlan = 0;
1469
1470 if (!mv88e6xxx_has_pvt(chip))
Vivien Didelotd14939b2019-10-21 16:51:25 -04001471 return 0;
Vivien Didelot17a15942017-03-30 17:37:09 -04001472
1473 /* Skip the local source device, which uses in-chip port VLAN */
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001474 if (dev != chip->ds->index) {
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001475 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
Vivien Didelot17a15942017-03-30 17:37:09 -04001476
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001477 ds = dsa_switch_find(dst->index, dev);
1478 dp = ds ? dsa_to_port(ds, port) : NULL;
1479 if (dp && dp->lag_dev) {
1480 /* As the PVT is used to limit flooding of
1481 * FORWARD frames, which use the LAG ID as the
1482 * source port, we must translate dev/port to
1483 * the special "LAG device" in the PVT, using
1484 * the LAG ID as the port number.
1485 */
Tobias Waldekranz78e70db2021-04-21 14:04:52 +02001486 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001487 port = dsa_lag_id(dst, dp->lag_dev);
1488 }
1489 }
1490
Vivien Didelot17a15942017-03-30 17:37:09 -04001491 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1492}
1493
Vivien Didelot81228992017-03-30 17:37:08 -04001494static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1495{
Vivien Didelot17a15942017-03-30 17:37:09 -04001496 int dev, port;
1497 int err;
1498
Vivien Didelot81228992017-03-30 17:37:08 -04001499 if (!mv88e6xxx_has_pvt(chip))
1500 return 0;
1501
1502 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1503 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1504 */
Vivien Didelot17a15942017-03-30 17:37:09 -04001505 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1506 if (err)
1507 return err;
1508
1509 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1510 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1511 err = mv88e6xxx_pvt_map(chip, dev, port);
1512 if (err)
1513 return err;
1514 }
1515 }
1516
1517 return 0;
Vivien Didelot81228992017-03-30 17:37:08 -04001518}
1519
Vivien Didelot749efcb2016-09-22 16:49:24 -04001520static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1521{
1522 struct mv88e6xxx_chip *chip = ds->priv;
1523 int err;
1524
Tobias Waldekranzffcec3f2021-03-18 20:25:34 +01001525 if (dsa_to_port(ds, port)->lag_dev)
1526 /* Hardware is incapable of fast-aging a LAG through a
1527 * regular ATU move operation. Until we have something
1528 * more fancy in place this is a no-op.
1529 */
1530 return;
1531
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001532 mv88e6xxx_reg_lock(chip);
Vivien Didelote606ca32017-03-11 16:12:55 -05001533 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001534 mv88e6xxx_reg_unlock(chip);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001535
1536 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001537 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001538}
1539
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001540static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1541{
Tobias Waldekranze545f862020-11-10 19:57:20 +01001542 if (!mv88e6xxx_max_vid(chip))
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001543 return 0;
1544
1545 return mv88e6xxx_g1_vtu_flush(chip);
1546}
1547
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001548static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1549 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelotf1394b782017-05-01 14:05:22 -04001550{
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001551 int err;
1552
Vivien Didelotf1394b782017-05-01 14:05:22 -04001553 if (!chip->info->ops->vtu_getnext)
1554 return -EOPNOTSUPP;
1555
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001556 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1557 entry->valid = false;
1558
1559 err = chip->info->ops->vtu_getnext(chip, entry);
1560
1561 if (entry->vid != vid)
1562 entry->valid = false;
1563
1564 return err;
Vivien Didelotf1394b782017-05-01 14:05:22 -04001565}
1566
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001567static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1568 int (*cb)(struct mv88e6xxx_chip *chip,
1569 const struct mv88e6xxx_vtu_entry *entry,
1570 void *priv),
1571 void *priv)
1572{
1573 struct mv88e6xxx_vtu_entry entry = {
1574 .vid = mv88e6xxx_max_vid(chip),
1575 .valid = false,
1576 };
1577 int err;
1578
1579 if (!chip->info->ops->vtu_getnext)
1580 return -EOPNOTSUPP;
1581
1582 do {
1583 err = chip->info->ops->vtu_getnext(chip, &entry);
1584 if (err)
1585 return err;
1586
1587 if (!entry.valid)
1588 break;
1589
1590 err = cb(chip, &entry, priv);
1591 if (err)
1592 return err;
1593 } while (entry.vid < mv88e6xxx_max_vid(chip));
1594
1595 return 0;
1596}
1597
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04001598static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1599 struct mv88e6xxx_vtu_entry *entry)
1600{
1601 if (!chip->info->ops->vtu_loadpurge)
1602 return -EOPNOTSUPP;
1603
1604 return chip->info->ops->vtu_loadpurge(chip, entry);
1605}
1606
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001607static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1608 const struct mv88e6xxx_vtu_entry *entry,
1609 void *_fid_bitmap)
1610{
1611 unsigned long *fid_bitmap = _fid_bitmap;
1612
1613 set_bit(entry->fid, fid_bitmap);
1614 return 0;
1615}
1616
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001617int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001618{
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001619 int i, err;
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001620 u16 fid;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001621
1622 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1623
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001624 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001625 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001626 err = mv88e6xxx_port_get_fid(chip, i, &fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001627 if (err)
1628 return err;
1629
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001630 set_bit(fid, fid_bitmap);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001631 }
1632
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001633 /* Set every FID bit used by the VLAN entries */
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001634 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001635}
1636
1637static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1638{
1639 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1640 int err;
1641
1642 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1643 if (err)
1644 return err;
1645
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001646 /* The reset value 0x000 is used to indicate that multiple address
1647 * databases are not needed. Return the next positive available.
1648 */
1649 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001650 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001651 return -ENOSPC;
1652
1653 /* Clear the database */
Vivien Didelotdaefc942017-03-11 16:12:54 -05001654 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001655}
1656
Vivien Didelotda9c3592016-02-12 12:09:40 -05001657static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001658 u16 vid)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001659{
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001660 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
Vivien Didelot04bed142016-08-31 18:06:13 -04001661 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot425d2d32019-08-01 14:36:34 -04001662 struct mv88e6xxx_vtu_entry vlan;
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001663 int err;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001664
Andrew Lunndb06ae412017-09-25 23:32:20 +02001665 /* DSA and CPU ports have to be members of multiple vlans */
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001666 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
Andrew Lunndb06ae412017-09-25 23:32:20 +02001667 return 0;
1668
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001669 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001670 if (err)
1671 return err;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001672
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001673 if (!vlan.valid)
1674 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001675
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001676 dsa_switch_for_each_user_port(other_dp, ds) {
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001677 struct net_device *other_br;
1678
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001679 if (vlan.member[other_dp->index] ==
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001680 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1681 continue;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001682
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001683 if (dsa_port_bridge_same(dp, other_dp))
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001684 break; /* same bridge, check next VLAN */
Vivien Didelotda9c3592016-02-12 12:09:40 -05001685
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001686 other_br = dsa_port_bridge_dev_get(other_dp);
1687 if (!other_br)
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001688 continue;
Andrew Lunn66e28092016-12-11 21:07:19 +01001689
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001690 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001691 port, vlan.vid, other_dp->index, netdev_name(other_br));
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001692 return -EOPNOTSUPP;
1693 }
Vivien Didelotda9c3592016-02-12 12:09:40 -05001694
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001695 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001696}
1697
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001698static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
1699{
1700 struct dsa_port *dp = dsa_to_port(chip->ds, port);
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001701 struct net_device *br = dsa_port_bridge_dev_get(dp);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001702 struct mv88e6xxx_port *p = &chip->ports[port];
Vladimir Oltean5bded822021-10-07 19:47:11 +03001703 u16 pvid = MV88E6XXX_VID_STANDALONE;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001704 bool drop_untagged = false;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001705 int err;
1706
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001707 if (br) {
1708 if (br_vlan_enabled(br)) {
Vladimir Oltean5bded822021-10-07 19:47:11 +03001709 pvid = p->bridge_pvid.vid;
1710 drop_untagged = !p->bridge_pvid.valid;
1711 } else {
1712 pvid = MV88E6XXX_VID_BRIDGED;
1713 }
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001714 }
1715
1716 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
1717 if (err)
1718 return err;
1719
1720 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
1721}
1722
Vivien Didelotf81ec902016-05-09 13:22:58 -04001723static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
Vladimir Oltean89153ed2021-02-13 22:43:19 +02001724 bool vlan_filtering,
1725 struct netlink_ext_ack *extack)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001726{
Vivien Didelot04bed142016-08-31 18:06:13 -04001727 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot81c6edb2017-06-12 12:37:41 -04001728 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1729 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001730 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001731
Vladimir Olteanbae33f22021-01-09 02:01:50 +02001732 if (!mv88e6xxx_max_vid(chip))
1733 return -EOPNOTSUPP;
Vivien Didelot54d77b52016-05-09 13:22:47 -04001734
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001735 mv88e6xxx_reg_lock(chip);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001736
Vivien Didelot385a0992016-11-04 03:23:31 +01001737 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001738 if (err)
1739 goto unlock;
1740
1741 err = mv88e6xxx_port_commit_pvid(chip, port);
1742 if (err)
1743 goto unlock;
1744
1745unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001746 mv88e6xxx_reg_unlock(chip);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001747
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001748 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001749}
1750
Vivien Didelot57d32312016-06-20 13:13:58 -04001751static int
1752mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001753 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001754{
Vivien Didelot04bed142016-08-31 18:06:13 -04001755 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001756 int err;
1757
Tobias Waldekranze545f862020-11-10 19:57:20 +01001758 if (!mv88e6xxx_max_vid(chip))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001759 return -EOPNOTSUPP;
1760
Vivien Didelotda9c3592016-02-12 12:09:40 -05001761 /* If the requested port doesn't belong to the same bridge as the VLAN
1762 * members, do not support it (yet) and fallback to software VLAN.
1763 */
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001764 mv88e6xxx_reg_lock(chip);
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001765 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001766 mv88e6xxx_reg_unlock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001767
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001768 return err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001769}
1770
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001771static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1772 const unsigned char *addr, u16 vid,
1773 u8 state)
1774{
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001775 struct mv88e6xxx_atu_entry entry;
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001776 struct mv88e6xxx_vtu_entry vlan;
1777 u16 fid;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001778 int err;
1779
Vladimir Oltean5bded822021-10-07 19:47:11 +03001780 /* Ports have two private address databases: one for when the port is
1781 * standalone and one for when the port is under a bridge and the
1782 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
1783 * address database to remain 100% empty, so we never load an ATU entry
1784 * into a standalone port's database. Therefore, translate the null
1785 * VLAN ID into the port's database used for VLAN-unaware bridging.
1786 */
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001787 if (vid == 0) {
Vladimir Oltean5bded822021-10-07 19:47:11 +03001788 fid = MV88E6XXX_FID_BRIDGED;
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001789 } else {
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001790 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001791 if (err)
1792 return err;
1793
1794 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001795 if (!vlan.valid)
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001796 return -EOPNOTSUPP;
1797
1798 fid = vlan.fid;
1799 }
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001800
Vivien Didelotd8291a92019-09-07 16:00:47 -04001801 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001802 ether_addr_copy(entry.mac, addr);
1803 eth_addr_dec(entry.mac);
1804
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001805 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001806 if (err)
1807 return err;
1808
1809 /* Initialize a fresh ATU entry if it isn't found */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001810 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001811 memset(&entry, 0, sizeof(entry));
1812 ether_addr_copy(entry.mac, addr);
1813 }
1814
1815 /* Purge the ATU entry only if no port is using it anymore */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001816 if (!state) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001817 entry.portvec &= ~BIT(port);
1818 if (!entry.portvec)
Vivien Didelotd8291a92019-09-07 16:00:47 -04001819 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001820 } else {
DENG Qingfangf72f2fb2021-01-30 21:43:34 +08001821 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1822 entry.portvec = BIT(port);
1823 else
1824 entry.portvec |= BIT(port);
1825
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001826 entry.state = state;
1827 }
1828
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001829 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001830}
1831
Vivien Didelotda7dc872019-09-07 16:00:49 -04001832static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1833 const struct mv88e6xxx_policy *policy)
1834{
1835 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1836 enum mv88e6xxx_policy_action action = policy->action;
1837 const u8 *addr = policy->addr;
1838 u16 vid = policy->vid;
1839 u8 state;
1840 int err;
1841 int id;
1842
1843 if (!chip->info->ops->port_set_policy)
1844 return -EOPNOTSUPP;
1845
1846 switch (mapping) {
1847 case MV88E6XXX_POLICY_MAPPING_DA:
1848 case MV88E6XXX_POLICY_MAPPING_SA:
1849 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1850 state = 0; /* Dissociate the port and address */
1851 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1852 is_multicast_ether_addr(addr))
1853 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1854 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1855 is_unicast_ether_addr(addr))
1856 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1857 else
1858 return -EOPNOTSUPP;
1859
1860 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1861 state);
1862 if (err)
1863 return err;
1864 break;
1865 default:
1866 return -EOPNOTSUPP;
1867 }
1868
1869 /* Skip the port's policy clearing if the mapping is still in use */
1870 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1871 idr_for_each_entry(&chip->policies, policy, id)
1872 if (policy->port == port &&
1873 policy->mapping == mapping &&
1874 policy->action != action)
1875 return 0;
1876
1877 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1878}
1879
1880static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1881 struct ethtool_rx_flow_spec *fs)
1882{
1883 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1884 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1885 enum mv88e6xxx_policy_mapping mapping;
1886 enum mv88e6xxx_policy_action action;
1887 struct mv88e6xxx_policy *policy;
1888 u16 vid = 0;
1889 u8 *addr;
1890 int err;
1891 int id;
1892
1893 if (fs->location != RX_CLS_LOC_ANY)
1894 return -EINVAL;
1895
1896 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1897 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1898 else
1899 return -EOPNOTSUPP;
1900
1901 switch (fs->flow_type & ~FLOW_EXT) {
1902 case ETHER_FLOW:
1903 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1904 is_zero_ether_addr(mac_mask->h_source)) {
1905 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1906 addr = mac_entry->h_dest;
1907 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1908 !is_zero_ether_addr(mac_mask->h_source)) {
1909 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1910 addr = mac_entry->h_source;
1911 } else {
1912 /* Cannot support DA and SA mapping in the same rule */
1913 return -EOPNOTSUPP;
1914 }
1915 break;
1916 default:
1917 return -EOPNOTSUPP;
1918 }
1919
1920 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
Andrew Lunn04844282020-07-05 21:38:08 +02001921 if (fs->m_ext.vlan_tci != htons(0xffff))
Vivien Didelotda7dc872019-09-07 16:00:49 -04001922 return -EOPNOTSUPP;
1923 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1924 }
1925
1926 idr_for_each_entry(&chip->policies, policy, id) {
1927 if (policy->port == port && policy->mapping == mapping &&
1928 policy->action == action && policy->vid == vid &&
1929 ether_addr_equal(policy->addr, addr))
1930 return -EEXIST;
1931 }
1932
1933 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1934 if (!policy)
1935 return -ENOMEM;
1936
1937 fs->location = 0;
1938 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1939 GFP_KERNEL);
1940 if (err) {
1941 devm_kfree(chip->dev, policy);
1942 return err;
1943 }
1944
1945 memcpy(&policy->fs, fs, sizeof(*fs));
1946 ether_addr_copy(policy->addr, addr);
1947 policy->mapping = mapping;
1948 policy->action = action;
1949 policy->port = port;
1950 policy->vid = vid;
1951
1952 err = mv88e6xxx_policy_apply(chip, port, policy);
1953 if (err) {
1954 idr_remove(&chip->policies, fs->location);
1955 devm_kfree(chip->dev, policy);
1956 return err;
1957 }
1958
1959 return 0;
1960}
1961
1962static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1963 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1964{
1965 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1966 struct mv88e6xxx_chip *chip = ds->priv;
1967 struct mv88e6xxx_policy *policy;
1968 int err;
1969 int id;
1970
1971 mv88e6xxx_reg_lock(chip);
1972
1973 switch (rxnfc->cmd) {
1974 case ETHTOOL_GRXCLSRLCNT:
1975 rxnfc->data = 0;
1976 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1977 rxnfc->rule_cnt = 0;
1978 idr_for_each_entry(&chip->policies, policy, id)
1979 if (policy->port == port)
1980 rxnfc->rule_cnt++;
1981 err = 0;
1982 break;
1983 case ETHTOOL_GRXCLSRULE:
1984 err = -ENOENT;
1985 policy = idr_find(&chip->policies, fs->location);
1986 if (policy) {
1987 memcpy(fs, &policy->fs, sizeof(*fs));
1988 err = 0;
1989 }
1990 break;
1991 case ETHTOOL_GRXCLSRLALL:
1992 rxnfc->data = 0;
1993 rxnfc->rule_cnt = 0;
1994 idr_for_each_entry(&chip->policies, policy, id)
1995 if (policy->port == port)
1996 rule_locs[rxnfc->rule_cnt++] = id;
1997 err = 0;
1998 break;
1999 default:
2000 err = -EOPNOTSUPP;
2001 break;
2002 }
2003
2004 mv88e6xxx_reg_unlock(chip);
2005
2006 return err;
2007}
2008
2009static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2010 struct ethtool_rxnfc *rxnfc)
2011{
2012 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2013 struct mv88e6xxx_chip *chip = ds->priv;
2014 struct mv88e6xxx_policy *policy;
2015 int err;
2016
2017 mv88e6xxx_reg_lock(chip);
2018
2019 switch (rxnfc->cmd) {
2020 case ETHTOOL_SRXCLSRLINS:
2021 err = mv88e6xxx_policy_insert(chip, port, fs);
2022 break;
2023 case ETHTOOL_SRXCLSRLDEL:
2024 err = -ENOENT;
2025 policy = idr_remove(&chip->policies, fs->location);
2026 if (policy) {
2027 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2028 err = mv88e6xxx_policy_apply(chip, port, policy);
2029 devm_kfree(chip->dev, policy);
2030 }
2031 break;
2032 default:
2033 err = -EOPNOTSUPP;
2034 break;
2035 }
2036
2037 mv88e6xxx_reg_unlock(chip);
2038
2039 return err;
2040}
2041
Andrew Lunn87fa8862017-11-09 22:29:56 +01002042static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2043 u16 vid)
2044{
Andrew Lunn87fa8862017-11-09 22:29:56 +01002045 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
Tobias Waldekranz0806dd462021-03-18 20:25:37 +01002046 u8 broadcast[ETH_ALEN];
2047
2048 eth_broadcast_addr(broadcast);
Andrew Lunn87fa8862017-11-09 22:29:56 +01002049
2050 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2051}
2052
2053static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2054{
2055 int port;
2056 int err;
2057
2058 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01002059 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2060 struct net_device *brport;
2061
2062 if (dsa_is_unused_port(chip->ds, port))
2063 continue;
2064
2065 brport = dsa_port_to_bridge_port(dp);
2066 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2067 /* Skip bridged user ports where broadcast
2068 * flooding is disabled.
2069 */
2070 continue;
2071
Andrew Lunn87fa8862017-11-09 22:29:56 +01002072 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2073 if (err)
2074 return err;
2075 }
2076
2077 return 0;
2078}
2079
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01002080struct mv88e6xxx_port_broadcast_sync_ctx {
2081 int port;
2082 bool flood;
2083};
2084
2085static int
2086mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2087 const struct mv88e6xxx_vtu_entry *vlan,
2088 void *_ctx)
2089{
2090 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2091 u8 broadcast[ETH_ALEN];
2092 u8 state;
2093
2094 if (ctx->flood)
2095 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2096 else
2097 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2098
2099 eth_broadcast_addr(broadcast);
2100
2101 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2102 vlan->vid, state);
2103}
2104
2105static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2106 bool flood)
2107{
2108 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2109 .port = port,
2110 .flood = flood,
2111 };
2112 struct mv88e6xxx_vtu_entry vid0 = {
2113 .vid = 0,
2114 };
2115 int err;
2116
2117 /* Update the port's private database... */
2118 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2119 if (err)
2120 return err;
2121
2122 /* ...and the database for all VLANs. */
2123 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2124 &ctx);
2125}
2126
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002127static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
Russell King933b4422020-02-26 17:14:26 +00002128 u16 vid, u8 member, bool warn)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002129{
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002130 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002131 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002132 int i, err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002133
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002134 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002135 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002136 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002137
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002138 if (!vlan.valid) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002139 memset(&vlan, 0, sizeof(vlan));
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002140
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002141 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2142 if (err)
2143 return err;
Andrew Lunn87fa8862017-11-09 22:29:56 +01002144
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002145 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2146 if (i == port)
2147 vlan.member[i] = member;
2148 else
2149 vlan.member[i] = non_member;
2150
2151 vlan.vid = vid;
2152 vlan.valid = true;
2153
2154 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2155 if (err)
2156 return err;
2157
2158 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2159 if (err)
2160 return err;
2161 } else if (vlan.member[port] != member) {
2162 vlan.member[port] = member;
2163
2164 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2165 if (err)
2166 return err;
Russell King933b4422020-02-26 17:14:26 +00002167 } else if (warn) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002168 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2169 port, vid);
2170 }
2171
2172 return 0;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002173}
2174
Vladimir Oltean1958d582021-01-09 02:01:53 +02002175static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
Vladimir Oltean31046a52021-02-13 22:43:18 +02002176 const struct switchdev_obj_port_vlan *vlan,
2177 struct netlink_ext_ack *extack)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002178{
Vivien Didelot04bed142016-08-31 18:06:13 -04002179 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002180 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2181 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002182 struct mv88e6xxx_port *p = &chip->ports[port];
Russell King933b4422020-02-26 17:14:26 +00002183 bool warn;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002184 u8 member;
Vladimir Oltean1958d582021-01-09 02:01:53 +02002185 int err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002186
Eldar Gasanovb8b79c42021-06-21 11:54:38 +03002187 if (!vlan->vid)
2188 return 0;
2189
Vladimir Oltean1958d582021-01-09 02:01:53 +02002190 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2191 if (err)
2192 return err;
Vivien Didelot54d77b52016-05-09 13:22:47 -04002193
Vivien Didelotc91498e2017-06-07 18:12:13 -04002194 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002195 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002196 else if (untagged)
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002197 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002198 else
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002199 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002200
Russell King933b4422020-02-26 17:14:26 +00002201 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2202 * and then the CPU port. Do not warn for duplicates for the CPU port.
2203 */
2204 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2205
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002206 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002207
Vladimir Oltean1958d582021-01-09 02:01:53 +02002208 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2209 if (err) {
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002210 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2211 vlan->vid, untagged ? 'u' : 't');
Vladimir Oltean1958d582021-01-09 02:01:53 +02002212 goto out;
2213 }
Vivien Didelot76e398a2015-11-01 12:33:55 -05002214
Vladimir Oltean1958d582021-01-09 02:01:53 +02002215 if (pvid) {
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002216 p->bridge_pvid.vid = vlan->vid;
2217 p->bridge_pvid.valid = true;
2218
2219 err = mv88e6xxx_port_commit_pvid(chip, port);
2220 if (err)
Vladimir Oltean1958d582021-01-09 02:01:53 +02002221 goto out;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002222 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2223 /* The old pvid was reinstalled as a non-pvid VLAN */
2224 p->bridge_pvid.valid = false;
2225
2226 err = mv88e6xxx_port_commit_pvid(chip, port);
2227 if (err)
2228 goto out;
Vladimir Oltean1958d582021-01-09 02:01:53 +02002229 }
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002230
Vladimir Oltean1958d582021-01-09 02:01:53 +02002231out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002232 mv88e6xxx_reg_unlock(chip);
Vladimir Oltean1958d582021-01-09 02:01:53 +02002233
2234 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002235}
2236
Vivien Didelot521098922019-08-01 14:36:36 -04002237static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2238 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002239{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002240 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002241 int i, err;
2242
Vivien Didelot521098922019-08-01 14:36:36 -04002243 if (!vid)
Vladimir Olteanc92c7412021-07-22 16:05:51 +03002244 return 0;
Vivien Didelot521098922019-08-01 14:36:36 -04002245
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002246 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002247 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002248 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002249
Vivien Didelot521098922019-08-01 14:36:36 -04002250 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2251 * tell switchdev that this VLAN is likely handled in software.
2252 */
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002253 if (!vlan.valid ||
Vivien Didelot521098922019-08-01 14:36:36 -04002254 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05002255 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002256
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002257 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002258
2259 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002260 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002261 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002262 if (vlan.member[i] !=
2263 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002264 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002265 break;
2266 }
2267 }
2268
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002269 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002270 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002271 return err;
2272
Vivien Didelote606ca32017-03-11 16:12:55 -05002273 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002274}
2275
Vivien Didelotf81ec902016-05-09 13:22:58 -04002276static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2277 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002278{
Vivien Didelot04bed142016-08-31 18:06:13 -04002279 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002280 struct mv88e6xxx_port *p = &chip->ports[port];
Vivien Didelot76e398a2015-11-01 12:33:55 -05002281 int err = 0;
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002282 u16 pvid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002283
Tobias Waldekranze545f862020-11-10 19:57:20 +01002284 if (!mv88e6xxx_max_vid(chip))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002285 return -EOPNOTSUPP;
2286
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002287 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002288
Vivien Didelot77064f32016-11-04 03:23:30 +01002289 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002290 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002291 goto unlock;
2292
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002293 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2294 if (err)
2295 goto unlock;
2296
2297 if (vlan->vid == pvid) {
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002298 p->bridge_pvid.valid = false;
2299
2300 err = mv88e6xxx_port_commit_pvid(chip, port);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002301 if (err)
2302 goto unlock;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002303 }
2304
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002305unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002306 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002307
2308 return err;
2309}
2310
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002311static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2312 const unsigned char *addr, u16 vid)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002313{
Vivien Didelot04bed142016-08-31 18:06:13 -04002314 struct mv88e6xxx_chip *chip = ds->priv;
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002315 int err;
Vivien Didelot6630e232015-08-06 01:44:07 -04002316
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002317 mv88e6xxx_reg_lock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002318 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2319 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002320 mv88e6xxx_reg_unlock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002321
2322 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002323}
2324
Vivien Didelotf81ec902016-05-09 13:22:58 -04002325static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
Arkadi Sharshevsky6c2c1dc2017-08-06 16:15:39 +03002326 const unsigned char *addr, u16 vid)
David S. Millercdf09692015-08-11 12:00:37 -07002327{
Vivien Didelot04bed142016-08-31 18:06:13 -04002328 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002329 int err;
David S. Millercdf09692015-08-11 12:00:37 -07002330
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002331 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04002332 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002333 mv88e6xxx_reg_unlock(chip);
David S. Millercdf09692015-08-11 12:00:37 -07002334
Vivien Didelot83dabd12016-08-31 11:50:04 -04002335 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002336}
2337
Vivien Didelot83dabd12016-08-31 11:50:04 -04002338static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2339 u16 fid, u16 vid, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002340 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002341{
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002342 struct mv88e6xxx_atu_entry addr;
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002343 bool is_static;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002344 int err;
2345
Vivien Didelotd8291a92019-09-07 16:00:47 -04002346 addr.state = 0;
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002347 eth_broadcast_addr(addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002348
2349 do {
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002350 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002351 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002352 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002353
Vivien Didelotd8291a92019-09-07 16:00:47 -04002354 if (!addr.state)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002355 break;
2356
Vivien Didelot01bd96c2017-03-11 16:12:57 -05002357 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002358 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002359
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002360 if (!is_unicast_ether_addr(addr.mac))
2361 continue;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002362
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002363 is_static = (addr.state ==
2364 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2365 err = cb(addr.mac, vid, is_static, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002366 if (err)
2367 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002368 } while (!is_broadcast_ether_addr(addr.mac));
2369
2370 return err;
2371}
2372
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002373struct mv88e6xxx_port_db_dump_vlan_ctx {
2374 int port;
2375 dsa_fdb_dump_cb_t *cb;
2376 void *data;
2377};
2378
2379static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2380 const struct mv88e6xxx_vtu_entry *entry,
2381 void *_data)
2382{
2383 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2384
2385 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2386 ctx->port, ctx->cb, ctx->data);
2387}
2388
Vivien Didelot83dabd12016-08-31 11:50:04 -04002389static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002390 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002391{
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002392 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2393 .port = port,
2394 .cb = cb,
2395 .data = data,
2396 };
Vivien Didelot83dabd12016-08-31 11:50:04 -04002397 u16 fid;
2398 int err;
2399
2400 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002401 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002402 if (err)
2403 return err;
2404
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002405 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002406 if (err)
2407 return err;
2408
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002409 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002410}
2411
Vivien Didelotf81ec902016-05-09 13:22:58 -04002412static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002413 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelotf33475b2015-10-22 09:34:41 -04002414{
Vivien Didelot04bed142016-08-31 18:06:13 -04002415 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotfcf15362019-06-12 12:42:47 -04002416 int err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002417
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002418 mv88e6xxx_reg_lock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002419 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002420 mv88e6xxx_reg_unlock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002421
2422 return err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002423}
2424
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002425static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002426 struct dsa_bridge bridge)
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002427{
Vivien Didelotef2025e2019-10-21 16:51:27 -04002428 struct dsa_switch *ds = chip->ds;
2429 struct dsa_switch_tree *dst = ds->dst;
2430 struct dsa_port *dp;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002431 int err;
2432
Vivien Didelotef2025e2019-10-21 16:51:27 -04002433 list_for_each_entry(dp, &dst->ports, list) {
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002434 if (dsa_port_offloads_bridge(dp, &bridge)) {
Vivien Didelotef2025e2019-10-21 16:51:27 -04002435 if (dp->ds == ds) {
2436 /* This is a local bridge group member,
2437 * remap its Port VLAN Map.
2438 */
2439 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2440 if (err)
2441 return err;
2442 } else {
2443 /* This is an external bridge group member,
2444 * remap its cross-chip Port VLAN Table entry.
2445 */
2446 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2447 dp->index);
Vivien Didelote96a6e02017-03-30 17:37:13 -04002448 if (err)
2449 return err;
2450 }
2451 }
2452 }
2453
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002454 return 0;
2455}
2456
Vladimir Oltean857fdd72021-12-06 18:57:58 +02002457/* Treat the software bridge as a virtual single-port switch behind the
2458 * CPU and map in the PVT. First dst->last_switch elements are taken by
2459 * physical switches, so start from beyond that range.
2460 */
2461static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2462 unsigned int bridge_num)
2463{
2464 u8 dev = bridge_num + ds->dst->last_switch;
2465 struct mv88e6xxx_chip *chip = ds->priv;
2466
2467 return mv88e6xxx_pvt_map(chip, dev, 0);
2468}
2469
Vivien Didelotf81ec902016-05-09 13:22:58 -04002470static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vladimir Olteanb0799222021-12-06 18:57:57 +02002471 struct dsa_bridge bridge,
2472 bool *tx_fwd_offload)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002473{
Vivien Didelot04bed142016-08-31 18:06:13 -04002474 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002475 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002476
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002477 mv88e6xxx_reg_lock(chip);
Vladimir Oltean5bded822021-10-07 19:47:11 +03002478
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002479 err = mv88e6xxx_bridge_map(chip, bridge);
Vladimir Oltean5bded822021-10-07 19:47:11 +03002480 if (err)
2481 goto unlock;
2482
2483 err = mv88e6xxx_port_commit_pvid(chip, port);
2484 if (err)
2485 goto unlock;
2486
Vladimir Oltean857fdd72021-12-06 18:57:58 +02002487 if (mv88e6xxx_has_pvt(chip)) {
2488 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2489 if (err)
2490 goto unlock;
2491
2492 *tx_fwd_offload = true;
2493 }
2494
Vladimir Oltean5bded822021-10-07 19:47:11 +03002495unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002496 mv88e6xxx_reg_unlock(chip);
Vivien Didelota6692752016-02-12 12:09:39 -05002497
Vivien Didelot466dfa02016-02-26 13:16:05 -05002498 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002499}
2500
Vivien Didelotf123f2f2017-01-27 15:29:41 -05002501static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002502 struct dsa_bridge bridge)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002503{
Vivien Didelot04bed142016-08-31 18:06:13 -04002504 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Oltean5bded822021-10-07 19:47:11 +03002505 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002506
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002507 mv88e6xxx_reg_lock(chip);
Vladimir Oltean5bded822021-10-07 19:47:11 +03002508
Vladimir Oltean857fdd72021-12-06 18:57:58 +02002509 if (bridge.tx_fwd_offload &&
2510 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2511 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2512
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002513 if (mv88e6xxx_bridge_map(chip, bridge) ||
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002514 mv88e6xxx_port_vlan_map(chip, port))
2515 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
Vladimir Oltean5bded822021-10-07 19:47:11 +03002516
2517 err = mv88e6xxx_port_commit_pvid(chip, port);
2518 if (err)
2519 dev_err(ds->dev,
2520 "port %d failed to restore standalone pvid: %pe\n",
2521 port, ERR_PTR(err));
2522
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002523 mv88e6xxx_reg_unlock(chip);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05002524}
2525
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002526static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2527 int tree_index, int sw_index,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002528 int port, struct dsa_bridge bridge)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002529{
2530 struct mv88e6xxx_chip *chip = ds->priv;
2531 int err;
2532
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002533 if (tree_index != ds->dst->index)
2534 return 0;
2535
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002536 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002537 err = mv88e6xxx_pvt_map(chip, sw_index, port);
Tobias Waldekranze0068622021-12-09 23:24:24 +01002538 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002539 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002540
2541 return err;
2542}
2543
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002544static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2545 int tree_index, int sw_index,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002546 int port, struct dsa_bridge bridge)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002547{
2548 struct mv88e6xxx_chip *chip = ds->priv;
2549
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002550 if (tree_index != ds->dst->index)
2551 return;
2552
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002553 mv88e6xxx_reg_lock(chip);
Tobias Waldekranze0068622021-12-09 23:24:24 +01002554 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2555 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002556 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002557 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002558}
2559
Vivien Didelot17e708b2016-12-05 17:30:27 -05002560static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2561{
2562 if (chip->info->ops->reset)
2563 return chip->info->ops->reset(chip);
2564
2565 return 0;
2566}
2567
Vivien Didelot309eca62016-12-05 17:30:26 -05002568static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2569{
2570 struct gpio_desc *gpiod = chip->reset;
2571
2572 /* If there is a GPIO connected to the reset pin, toggle it */
2573 if (gpiod) {
2574 gpiod_set_value_cansleep(gpiod, 1);
2575 usleep_range(10000, 20000);
2576 gpiod_set_value_cansleep(gpiod, 0);
2577 usleep_range(10000, 20000);
Andrew Lunna3dcb3e2020-11-16 08:43:01 -08002578
2579 mv88e6xxx_g1_wait_eeprom_done(chip);
Vivien Didelot309eca62016-12-05 17:30:26 -05002580 }
2581}
2582
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002583static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2584{
2585 int i, err;
2586
2587 /* Set all ports to the Disabled state */
2588 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotf894c292017-06-08 18:34:10 -04002589 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002590 if (err)
2591 return err;
2592 }
2593
2594 /* Wait for transmit queues to drain,
2595 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2596 */
2597 usleep_range(2000, 4000);
2598
2599 return 0;
2600}
2601
Vivien Didelotfad09c72016-06-21 12:28:20 -04002602static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002603{
Vivien Didelota935c052016-09-29 12:21:53 -04002604 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002605
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002606 err = mv88e6xxx_disable_ports(chip);
2607 if (err)
2608 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002609
Vivien Didelot309eca62016-12-05 17:30:26 -05002610 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002611
Vivien Didelot17e708b2016-12-05 17:30:27 -05002612 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002613}
2614
Vivien Didelot43145572017-03-11 16:12:59 -05002615static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002616 enum mv88e6xxx_frame_mode frame,
2617 enum mv88e6xxx_egress_mode egress, u16 etype)
Andrew Lunn56995cb2016-12-03 04:35:19 +01002618{
2619 int err;
2620
Vivien Didelot43145572017-03-11 16:12:59 -05002621 if (!chip->info->ops->port_set_frame_mode)
2622 return -EOPNOTSUPP;
2623
2624 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002625 if (err)
2626 return err;
2627
Vivien Didelot43145572017-03-11 16:12:59 -05002628 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2629 if (err)
2630 return err;
2631
2632 if (chip->info->ops->port_set_ether_type)
2633 return chip->info->ops->port_set_ether_type(chip, port, etype);
2634
2635 return 0;
2636}
2637
2638static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2639{
2640 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002641 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002642 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002643}
2644
2645static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2646{
2647 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002648 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002649 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002650}
2651
2652static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2653{
2654 return mv88e6xxx_set_port_mode(chip, port,
2655 MV88E6XXX_FRAME_MODE_ETHERTYPE,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002656 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2657 ETH_P_EDSA);
Vivien Didelot43145572017-03-11 16:12:59 -05002658}
2659
2660static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2661{
2662 if (dsa_is_dsa_port(chip->ds, port))
2663 return mv88e6xxx_set_port_mode_dsa(chip, port);
2664
Vivien Didelot2b3e9892017-10-26 11:22:54 -04002665 if (dsa_is_user_port(chip->ds, port))
Vivien Didelot43145572017-03-11 16:12:59 -05002666 return mv88e6xxx_set_port_mode_normal(chip, port);
2667
2668 /* Setup CPU port mode depending on its supported tag format */
Tobias Waldekranz670bb802021-04-20 20:53:07 +02002669 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
Vivien Didelot43145572017-03-11 16:12:59 -05002670 return mv88e6xxx_set_port_mode_dsa(chip, port);
2671
Tobias Waldekranz670bb802021-04-20 20:53:07 +02002672 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
Vivien Didelot43145572017-03-11 16:12:59 -05002673 return mv88e6xxx_set_port_mode_edsa(chip, port);
2674
2675 return -EINVAL;
2676}
2677
Vivien Didelotea698f42017-03-11 16:12:50 -05002678static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2679{
2680 bool message = dsa_is_dsa_port(chip->ds, port);
2681
2682 return mv88e6xxx_port_set_message_port(chip, port, message);
2683}
2684
Vivien Didelot601aeed2017-03-11 16:13:00 -05002685static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2686{
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002687 int err;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002688
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002689 if (chip->info->ops->port_set_ucast_flood) {
Tobias Waldekranz7b9f16f2021-03-18 20:25:38 +01002690 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002691 if (err)
2692 return err;
2693 }
2694 if (chip->info->ops->port_set_mcast_flood) {
Tobias Waldekranz7b9f16f2021-03-18 20:25:38 +01002695 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002696 if (err)
2697 return err;
2698 }
Vivien Didelot601aeed2017-03-11 16:13:00 -05002699
David S. Miller407308f2019-06-15 13:35:29 -07002700 return 0;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002701}
2702
Vivien Didelot45de77f2019-08-31 16:18:36 -04002703static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2704{
2705 struct mv88e6xxx_port *mvp = dev_id;
2706 struct mv88e6xxx_chip *chip = mvp->chip;
2707 irqreturn_t ret = IRQ_NONE;
2708 int port = mvp->port;
Pavana Sharma193c5b22021-03-17 14:46:40 +01002709 int lane;
Vivien Didelot45de77f2019-08-31 16:18:36 -04002710
2711 mv88e6xxx_reg_lock(chip);
2712 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +01002713 if (lane >= 0)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002714 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2715 mv88e6xxx_reg_unlock(chip);
2716
2717 return ret;
2718}
2719
2720static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
Pavana Sharma193c5b22021-03-17 14:46:40 +01002721 int lane)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002722{
2723 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2724 unsigned int irq;
2725 int err;
2726
2727 /* Nothing to request if this SERDES port has no IRQ */
2728 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2729 if (!irq)
2730 return 0;
2731
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002732 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2733 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2734
Vivien Didelot45de77f2019-08-31 16:18:36 -04002735 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2736 mv88e6xxx_reg_unlock(chip);
2737 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002738 IRQF_ONESHOT, dev_id->serdes_irq_name,
2739 dev_id);
Vivien Didelot45de77f2019-08-31 16:18:36 -04002740 mv88e6xxx_reg_lock(chip);
2741 if (err)
2742 return err;
2743
2744 dev_id->serdes_irq = irq;
2745
2746 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2747}
2748
2749static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
Pavana Sharma193c5b22021-03-17 14:46:40 +01002750 int lane)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002751{
2752 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2753 unsigned int irq = dev_id->serdes_irq;
2754 int err;
2755
2756 /* Nothing to free if no IRQ has been requested */
2757 if (!irq)
2758 return 0;
2759
2760 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2761
2762 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2763 mv88e6xxx_reg_unlock(chip);
2764 free_irq(irq, dev_id);
2765 mv88e6xxx_reg_lock(chip);
2766
2767 dev_id->serdes_irq = 0;
2768
2769 return err;
2770}
2771
Andrew Lunn6d917822017-05-26 01:03:21 +02002772static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2773 bool on)
2774{
Pavana Sharma193c5b22021-03-17 14:46:40 +01002775 int lane;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002776 int err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002777
Vivien Didelotdc272f62019-08-31 16:18:33 -04002778 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +01002779 if (lane < 0)
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002780 return 0;
2781
2782 if (on) {
Vivien Didelotdc272f62019-08-31 16:18:33 -04002783 err = mv88e6xxx_serdes_power_up(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002784 if (err)
2785 return err;
2786
Vivien Didelot45de77f2019-08-31 16:18:36 -04002787 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002788 } else {
Vivien Didelot45de77f2019-08-31 16:18:36 -04002789 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2790 if (err)
2791 return err;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002792
Vivien Didelotdc272f62019-08-31 16:18:33 -04002793 err = mv88e6xxx_serdes_power_down(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002794 }
2795
2796 return err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002797}
2798
Marek Behún2fda45f2021-03-17 14:46:41 +01002799static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2800 enum mv88e6xxx_egress_direction direction,
2801 int port)
2802{
2803 int err;
2804
2805 if (!chip->info->ops->set_egress_port)
2806 return -EOPNOTSUPP;
2807
2808 err = chip->info->ops->set_egress_port(chip, direction, port);
2809 if (err)
2810 return err;
2811
2812 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2813 chip->ingress_dest_port = port;
2814 else
2815 chip->egress_dest_port = port;
2816
2817 return 0;
2818}
2819
Vivien Didelotfa371c82017-12-05 15:34:10 -05002820static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2821{
2822 struct dsa_switch *ds = chip->ds;
2823 int upstream_port;
2824 int err;
2825
Vivien Didelot07073c72017-12-05 15:34:13 -05002826 upstream_port = dsa_upstream_port(ds, port);
Vivien Didelotfa371c82017-12-05 15:34:10 -05002827 if (chip->info->ops->port_set_upstream_port) {
2828 err = chip->info->ops->port_set_upstream_port(chip, port,
2829 upstream_port);
2830 if (err)
2831 return err;
2832 }
2833
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002834 if (port == upstream_port) {
2835 if (chip->info->ops->set_cpu_port) {
2836 err = chip->info->ops->set_cpu_port(chip,
2837 upstream_port);
2838 if (err)
2839 return err;
2840 }
2841
Marek Behún2fda45f2021-03-17 14:46:41 +01002842 err = mv88e6xxx_set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002843 MV88E6XXX_EGRESS_DIR_INGRESS,
2844 upstream_port);
Marek Behún2fda45f2021-03-17 14:46:41 +01002845 if (err && err != -EOPNOTSUPP)
2846 return err;
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002847
Marek Behún2fda45f2021-03-17 14:46:41 +01002848 err = mv88e6xxx_set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002849 MV88E6XXX_EGRESS_DIR_EGRESS,
2850 upstream_port);
Marek Behún2fda45f2021-03-17 14:46:41 +01002851 if (err && err != -EOPNOTSUPP)
2852 return err;
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002853 }
2854
Vivien Didelotfa371c82017-12-05 15:34:10 -05002855 return 0;
2856}
2857
Vivien Didelotfad09c72016-06-21 12:28:20 -04002858static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002859{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002860 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002861 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002862 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002863
Andrew Lunn7b898462018-08-09 15:38:47 +02002864 chip->ports[port].chip = chip;
2865 chip->ports[port].port = port;
2866
Vivien Didelotd78343d2016-11-04 03:23:36 +01002867 /* MAC Forcing register: don't force link, speed, duplex or flow control
2868 * state to any particular values on physical ports, but force the CPU
2869 * port and all DSA ports to their maximum bandwidth and full duplex.
2870 */
2871 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2872 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2873 SPEED_MAX, DUPLEX_FULL,
Andrew Lunn54186b92018-08-09 15:38:37 +02002874 PAUSE_OFF,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002875 PHY_INTERFACE_MODE_NA);
2876 else
2877 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2878 SPEED_UNFORCED, DUPLEX_UNFORCED,
Andrew Lunn54186b92018-08-09 15:38:37 +02002879 PAUSE_ON,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002880 PHY_INTERFACE_MODE_NA);
2881 if (err)
2882 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002883
2884 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2885 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2886 * tunneling, determine priority by looking at 802.1p and IP
2887 * priority fields (IP prio has precedence), and set STP state
2888 * to Forwarding.
2889 *
2890 * If this is the CPU link, use DSA or EDSA tagging depending
2891 * on which tagging mode was configured.
2892 *
2893 * If this is a link to another switch, use DSA tagging mode.
2894 *
2895 * If this is the upstream port for this switch, enable
2896 * forwarding of unknown unicasts and multicasts.
2897 */
Vivien Didelota89b433be2017-06-12 12:37:37 -04002898 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2899 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2900 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2901 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002902 if (err)
2903 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002904
Vivien Didelot601aeed2017-03-11 16:13:00 -05002905 err = mv88e6xxx_setup_port_mode(chip, port);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002906 if (err)
2907 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002908
Vivien Didelot601aeed2017-03-11 16:13:00 -05002909 err = mv88e6xxx_setup_egress_floods(chip, port);
Vivien Didelot43145572017-03-11 16:12:59 -05002910 if (err)
2911 return err;
2912
Andrew Lunnb92ce2f2021-09-26 19:41:25 +02002913 /* Port Control 2: don't force a good FCS, set the MTU size to
2914 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002915 * untagged frames on this port, do a destination address lookup on all
2916 * received packets as usual, disable ARP mirroring and don't send a
2917 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002918 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002919 err = mv88e6xxx_port_set_map_da(chip, port);
2920 if (err)
2921 return err;
2922
Vivien Didelotfa371c82017-12-05 15:34:10 -05002923 err = mv88e6xxx_setup_upstream_port(chip, port);
2924 if (err)
2925 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002926
Andrew Lunna23b2962017-02-04 20:15:28 +01002927 err = mv88e6xxx_port_set_8021q_mode(chip, port,
Vivien Didelot81c6edb2017-06-12 12:37:41 -04002928 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
Andrew Lunna23b2962017-02-04 20:15:28 +01002929 if (err)
2930 return err;
2931
Vladimir Oltean5bded822021-10-07 19:47:11 +03002932 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
2933 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
2934 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
2935 * as the private PVID on ports under a VLAN-unaware bridge.
2936 * Shared (DSA and CPU) ports must also be members of it, to translate
2937 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
2938 * relying on their port default FID.
2939 */
2940 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
2941 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED,
2942 false);
2943 if (err)
2944 return err;
2945
Vivien Didelotcd782652017-06-08 18:34:13 -04002946 if (chip->info->ops->port_set_jumbo_size) {
Andrew Lunnb92ce2f2021-09-26 19:41:25 +02002947 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
Andrew Lunn5f436662016-12-03 04:45:17 +01002948 if (err)
2949 return err;
2950 }
2951
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002952 /* Port Association Vector: disable automatic address learning
2953 * on all user ports since they start out in standalone
2954 * mode. When joining a bridge, learning will be configured to
2955 * match the bridge port settings. Enable learning on all
2956 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2957 * learning process.
2958 *
2959 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2960 * and RefreshLocked. I.e. setup standard automatic learning.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002961 */
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002962 if (dsa_is_user_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002963 reg = 0;
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002964 else
2965 reg = 1 << port;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002966
Vivien Didelot2a4614e2017-06-12 12:37:43 -04002967 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2968 reg);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002969 if (err)
2970 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002971
2972 /* Egress rate control 2: disable egress rate control. */
Vivien Didelot2cb8cb12017-06-12 12:37:42 -04002973 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2974 0x0000);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002975 if (err)
2976 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002977
Vivien Didelot08984322017-06-08 18:34:12 -04002978 if (chip->info->ops->port_pause_limit) {
2979 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002980 if (err)
2981 return err;
2982 }
2983
Vivien Didelotc8c94892017-03-11 16:13:01 -05002984 if (chip->info->ops->port_disable_learn_limit) {
2985 err = chip->info->ops->port_disable_learn_limit(chip, port);
2986 if (err)
2987 return err;
2988 }
2989
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002990 if (chip->info->ops->port_disable_pri_override) {
2991 err = chip->info->ops->port_disable_pri_override(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002992 if (err)
2993 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002994 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002995
Andrew Lunnef0a7312016-12-03 04:35:16 +01002996 if (chip->info->ops->port_tag_remap) {
2997 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002998 if (err)
2999 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003000 }
3001
Andrew Lunnef70b112016-12-03 04:45:18 +01003002 if (chip->info->ops->port_egress_rate_limiting) {
3003 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02003004 if (err)
3005 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003006 }
3007
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003008 if (chip->info->ops->port_setup_message_port) {
3009 err = chip->info->ops->port_setup_message_port(chip, port);
3010 if (err)
3011 return err;
3012 }
Guenter Roeckd827e882015-03-26 18:36:29 -07003013
Vivien Didelot207afda2016-04-14 14:42:09 -04003014 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05003015 * database, and allow bidirectional communication between the
3016 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07003017 */
Vladimir Oltean5bded822021-10-07 19:47:11 +03003018 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02003019 if (err)
3020 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05003021
Vivien Didelot240ea3e2017-03-30 17:37:12 -04003022 err = mv88e6xxx_port_vlan_map(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02003023 if (err)
3024 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07003025
3026 /* Default VLAN ID and priority: don't set a default VLAN
3027 * ID, and set the default packet priority to zero.
3028 */
Vivien Didelotb7929fb2017-06-12 12:37:40 -04003029 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
Andrew Lunndbde9e62015-05-06 01:09:48 +02003030}
3031
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003032static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3033{
3034 struct mv88e6xxx_chip *chip = ds->priv;
3035
3036 if (chip->info->ops->port_set_jumbo_size)
Andrew Lunnb9c587f2021-09-26 19:41:26 +02003037 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
Chris Packham1baf0fa2020-07-24 11:21:22 +12003038 else if (chip->info->ops->set_max_frame_size)
Andrew Lunnb9c587f2021-09-26 19:41:26 +02003039 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3040 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003041}
3042
3043static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3044{
3045 struct mv88e6xxx_chip *chip = ds->priv;
3046 int ret = 0;
3047
Andrew Lunnb9c587f2021-09-26 19:41:26 +02003048 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3049 new_mtu += EDSA_HLEN;
3050
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003051 mv88e6xxx_reg_lock(chip);
3052 if (chip->info->ops->port_set_jumbo_size)
3053 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
Chris Packham1baf0fa2020-07-24 11:21:22 +12003054 else if (chip->info->ops->set_max_frame_size)
3055 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003056 else
3057 if (new_mtu > 1522)
3058 ret = -EINVAL;
3059 mv88e6xxx_reg_unlock(chip);
3060
3061 return ret;
3062}
3063
Andrew Lunn04aca992017-05-26 01:03:24 +02003064static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3065 struct phy_device *phydev)
3066{
3067 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot523a8902017-05-26 18:02:42 -04003068 int err;
Andrew Lunn04aca992017-05-26 01:03:24 +02003069
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003070 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04003071 err = mv88e6xxx_serdes_power(chip, port, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003072 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02003073
3074 return err;
3075}
3076
Andrew Lunn75104db2019-02-24 20:44:43 +01003077static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
Andrew Lunn04aca992017-05-26 01:03:24 +02003078{
3079 struct mv88e6xxx_chip *chip = ds->priv;
3080
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003081 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04003082 if (mv88e6xxx_serdes_power(chip, port, false))
3083 dev_err(chip->dev, "failed to power off SERDES\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003084 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02003085}
3086
Vivien Didelot2cfcd962016-07-18 20:45:40 -04003087static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3088 unsigned int ageing_time)
3089{
Vivien Didelot04bed142016-08-31 18:06:13 -04003090 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04003091 int err;
3092
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003093 mv88e6xxx_reg_lock(chip);
Vivien Didelot720c6342017-03-11 16:12:48 -05003094 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003095 mv88e6xxx_reg_unlock(chip);
Vivien Didelot2cfcd962016-07-18 20:45:40 -04003096
3097 return err;
3098}
3099
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003100static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04003101{
3102 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04003103
Andrew Lunnde2273872016-11-21 23:27:01 +01003104 /* Initialize the statistics unit */
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003105 if (chip->info->ops->stats_set_histogram) {
3106 err = chip->info->ops->stats_set_histogram(chip);
3107 if (err)
3108 return err;
3109 }
Andrew Lunnde2273872016-11-21 23:27:01 +01003110
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003111 return mv88e6xxx_g1_stats_clear(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04003112}
3113
Andrew Lunnea890982019-01-09 00:24:03 +01003114/* Check if the errata has already been applied. */
3115static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3116{
3117 int port;
3118 int err;
3119 u16 val;
3120
3121 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02003122 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
Andrew Lunnea890982019-01-09 00:24:03 +01003123 if (err) {
3124 dev_err(chip->dev,
3125 "Error reading hidden register: %d\n", err);
3126 return false;
3127 }
3128 if (val != 0x01c0)
3129 return false;
3130 }
3131
3132 return true;
3133}
3134
3135/* The 6390 copper ports have an errata which require poking magic
3136 * values into undocumented hidden registers and then performing a
3137 * software reset.
3138 */
3139static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3140{
3141 int port;
3142 int err;
3143
3144 if (mv88e6390_setup_errata_applied(chip))
3145 return 0;
3146
3147 /* Set the ports into blocking mode */
3148 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3149 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3150 if (err)
3151 return err;
3152 }
3153
3154 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02003155 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
Andrew Lunnea890982019-01-09 00:24:03 +01003156 if (err)
3157 return err;
3158 }
3159
3160 return mv88e6xxx_software_reset(chip);
3161}
3162
Andrew Lunn23e8b472019-10-25 01:03:52 +02003163static void mv88e6xxx_teardown(struct dsa_switch *ds)
3164{
3165 mv88e6xxx_teardown_devlink_params(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003166 dsa_devlink_resources_unregister(ds);
Vladimir Olteanfd292c12021-09-17 17:29:16 +03003167 mv88e6xxx_teardown_devlink_regions_global(ds);
Andrew Lunn23e8b472019-10-25 01:03:52 +02003168}
3169
Vivien Didelotf81ec902016-05-09 13:22:58 -04003170static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07003171{
Vivien Didelot04bed142016-08-31 18:06:13 -04003172 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003173 u8 cmode;
Vivien Didelot552238b2016-05-09 13:22:49 -04003174 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04003175 int i;
3176
Vivien Didelotfad09c72016-06-21 12:28:20 -04003177 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003178 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04003179
Vladimir Olteance5df682021-07-22 18:55:41 +03003180 /* Since virtual bridges are mapped in the PVT, the number we support
3181 * depends on the physical switch topology. We need to let DSA figure
3182 * that out and therefore we cannot set this at dsa_register_switch()
3183 * time.
3184 */
3185 if (mv88e6xxx_has_pvt(chip))
Vladimir Oltean947c8742021-12-06 18:57:48 +02003186 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3187 ds->dst->last_switch - 1;
Vladimir Olteance5df682021-07-22 18:55:41 +03003188
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003189 mv88e6xxx_reg_lock(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04003190
Andrew Lunnea890982019-01-09 00:24:03 +01003191 if (chip->info->ops->setup_errata) {
3192 err = chip->info->ops->setup_errata(chip);
3193 if (err)
3194 goto unlock;
3195 }
3196
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003197 /* Cache the cmode of each port. */
3198 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3199 if (chip->info->ops->port_get_cmode) {
3200 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3201 if (err)
Dan Carpentere29129f2018-08-14 12:09:05 +03003202 goto unlock;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003203
3204 chip->ports[i].cmode = cmode;
3205 }
3206 }
3207
Vladimir Oltean5bded822021-10-07 19:47:11 +03003208 err = mv88e6xxx_vtu_setup(chip);
3209 if (err)
3210 goto unlock;
3211
Vivien Didelot97299342016-07-18 20:45:30 -04003212 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04003213 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotb759f522019-08-19 16:00:52 -04003214 if (dsa_is_unused_port(ds, i))
3215 continue;
3216
Hubert Feursteinc8574862019-07-31 10:23:48 +02003217 /* Prevent the use of an invalid port. */
Vivien Didelotb759f522019-08-19 16:00:52 -04003218 if (mv88e6xxx_is_invalid_port(chip, i)) {
Hubert Feursteinc8574862019-07-31 10:23:48 +02003219 dev_err(chip->dev, "port %d is invalid\n", i);
3220 err = -EINVAL;
3221 goto unlock;
3222 }
3223
Vivien Didelot97299342016-07-18 20:45:30 -04003224 err = mv88e6xxx_setup_port(chip, i);
3225 if (err)
3226 goto unlock;
3227 }
3228
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003229 err = mv88e6xxx_irl_setup(chip);
3230 if (err)
3231 goto unlock;
3232
Vivien Didelot04a69a12017-10-13 14:18:05 -04003233 err = mv88e6xxx_mac_setup(chip);
3234 if (err)
3235 goto unlock;
3236
Vivien Didelot1b17aed2017-05-26 18:03:05 -04003237 err = mv88e6xxx_phy_setup(chip);
3238 if (err)
3239 goto unlock;
3240
Vivien Didelot81228992017-03-30 17:37:08 -04003241 err = mv88e6xxx_pvt_setup(chip);
3242 if (err)
3243 goto unlock;
3244
Vivien Didelota2ac29d2017-03-11 16:12:49 -05003245 err = mv88e6xxx_atu_setup(chip);
3246 if (err)
3247 goto unlock;
3248
Andrew Lunn87fa8862017-11-09 22:29:56 +01003249 err = mv88e6xxx_broadcast_setup(chip, 0);
3250 if (err)
3251 goto unlock;
3252
Vivien Didelot9e907d72017-07-17 13:03:43 -04003253 err = mv88e6xxx_pot_setup(chip);
3254 if (err)
3255 goto unlock;
3256
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003257 err = mv88e6xxx_rmu_setup(chip);
3258 if (err)
3259 goto unlock;
3260
Vivien Didelot51c901a2017-07-17 13:03:41 -04003261 err = mv88e6xxx_rsvd2cpu_setup(chip);
3262 if (err)
3263 goto unlock;
Andrew Lunn6e55f692016-12-03 04:45:16 +01003264
Vivien Didelotb28f8722018-04-26 21:56:44 -04003265 err = mv88e6xxx_trunk_setup(chip);
3266 if (err)
3267 goto unlock;
3268
Vivien Didelotc7f047b2018-04-26 21:56:45 -04003269 err = mv88e6xxx_devmap_setup(chip);
3270 if (err)
3271 goto unlock;
3272
Vivien Didelot93e18d62018-05-11 17:16:35 -04003273 err = mv88e6xxx_pri_setup(chip);
3274 if (err)
3275 goto unlock;
3276
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01003277 /* Setup PTP Hardware Clock and timestamping */
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01003278 if (chip->info->ptp_support) {
3279 err = mv88e6xxx_ptp_setup(chip);
3280 if (err)
3281 goto unlock;
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01003282
3283 err = mv88e6xxx_hwtstamp_setup(chip);
3284 if (err)
3285 goto unlock;
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01003286 }
3287
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003288 err = mv88e6xxx_stats_setup(chip);
3289 if (err)
3290 goto unlock;
3291
Vivien Didelot6b17e862015-08-13 12:52:18 -04003292unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003293 mv88e6xxx_reg_unlock(chip);
Andrew Lunndb687a52015-06-20 21:31:29 +02003294
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003295 if (err)
3296 return err;
3297
3298 /* Have to be called without holding the register lock, since
3299 * they take the devlink lock, and we later take the locks in
3300 * the reverse order when getting/setting parameters or
3301 * resource occupancy.
Andrew Lunn23e8b472019-10-25 01:03:52 +02003302 */
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003303 err = mv88e6xxx_setup_devlink_resources(ds);
3304 if (err)
3305 return err;
3306
3307 err = mv88e6xxx_setup_devlink_params(ds);
3308 if (err)
Andrew Lunnbfb25542020-09-18 21:11:07 +02003309 goto out_resources;
3310
Vladimir Olteanfd292c12021-09-17 17:29:16 +03003311 err = mv88e6xxx_setup_devlink_regions_global(ds);
Andrew Lunnbfb25542020-09-18 21:11:07 +02003312 if (err)
3313 goto out_params;
3314
3315 return 0;
3316
3317out_params:
3318 mv88e6xxx_teardown_devlink_params(ds);
3319out_resources:
3320 dsa_devlink_resources_unregister(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003321
3322 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003323}
3324
Vladimir Olteanfd292c12021-09-17 17:29:16 +03003325static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3326{
3327 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3328}
3329
3330static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3331{
3332 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3333}
3334
Pali Rohár1fe976d2021-04-12 18:57:39 +02003335/* prod_id for switch families which do not have a PHY model number */
3336static const u16 family_prod_id_table[] = {
3337 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3338 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Marek Behúnc5d015b2021-04-20 09:54:02 +02003339 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
Pali Rohár1fe976d2021-04-12 18:57:39 +02003340};
3341
Vivien Didelote57e5e72016-08-15 17:19:00 -04003342static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003343{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003344 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3345 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Pali Rohár1fe976d2021-04-12 18:57:39 +02003346 u16 prod_id;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003347 u16 val;
3348 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003349
Andrew Lunnee26a222017-01-24 14:53:48 +01003350 if (!chip->info->ops->phy_read)
3351 return -EOPNOTSUPP;
3352
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003353 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003354 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003355 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003356
Pali Rohár1fe976d2021-04-12 18:57:39 +02003357 /* Some internal PHYs don't have a model number. */
3358 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3359 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3360 prod_id = family_prod_id_table[chip->info->family];
3361 if (prod_id)
3362 val |= prod_id >> 4;
Andrew Lunnda9f3302017-02-01 03:40:05 +01003363 }
3364
Vivien Didelote57e5e72016-08-15 17:19:00 -04003365 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003366}
3367
Vivien Didelote57e5e72016-08-15 17:19:00 -04003368static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003369{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003370 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3371 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003372 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003373
Andrew Lunnee26a222017-01-24 14:53:48 +01003374 if (!chip->info->ops->phy_write)
3375 return -EOPNOTSUPP;
3376
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003377 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003378 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003379 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003380
3381 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003382}
3383
Vivien Didelotfad09c72016-06-21 12:28:20 -04003384static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01003385 struct device_node *np,
3386 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02003387{
3388 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003389 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003390 struct mii_bus *bus;
3391 int err;
3392
Andrew Lunn2510bab2018-02-22 01:51:49 +01003393 if (external) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003394 mv88e6xxx_reg_lock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003395 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003396 mv88e6xxx_reg_unlock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003397
3398 if (err)
3399 return err;
3400 }
3401
Vladimir Olteanf53a2ce2022-02-07 18:15:47 +02003402 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02003403 if (!bus)
3404 return -ENOMEM;
3405
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003406 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003407 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003408 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003409 INIT_LIST_HEAD(&mdio_bus->list);
3410 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003411
Andrew Lunnb516d452016-06-04 21:17:06 +02003412 if (np) {
3413 bus->name = np->full_name;
Rob Herringf7ce9102017-07-18 16:43:19 -05003414 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003415 } else {
3416 bus->name = "mv88e6xxx SMI";
3417 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3418 }
3419
3420 bus->read = mv88e6xxx_mdio_read;
3421 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003422 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02003423
Andrew Lunn6f882842018-03-17 20:32:05 +01003424 if (!external) {
3425 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3426 if (err)
Vladimir Olteanf53a2ce2022-02-07 18:15:47 +02003427 goto out;
Andrew Lunn6f882842018-03-17 20:32:05 +01003428 }
3429
Florian Fainelli00e798c2018-05-15 16:56:19 -07003430 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003431 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003432 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunn6f882842018-03-17 20:32:05 +01003433 mv88e6xxx_g2_irq_mdio_free(chip, bus);
Vladimir Olteanf53a2ce2022-02-07 18:15:47 +02003434 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02003435 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003436
3437 if (external)
3438 list_add_tail(&mdio_bus->list, &chip->mdios);
3439 else
3440 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02003441
3442 return 0;
Vladimir Olteanf53a2ce2022-02-07 18:15:47 +02003443
3444out:
3445 mdiobus_free(bus);
3446 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02003447}
3448
Andrew Lunn3126aee2017-12-07 01:05:57 +01003449static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3450
3451{
3452 struct mv88e6xxx_mdio_bus *mdio_bus;
3453 struct mii_bus *bus;
3454
3455 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3456 bus = mdio_bus->bus;
3457
Andrew Lunn6f882842018-03-17 20:32:05 +01003458 if (!mdio_bus->external)
3459 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3460
Andrew Lunn3126aee2017-12-07 01:05:57 +01003461 mdiobus_unregister(bus);
Vladimir Olteanf53a2ce2022-02-07 18:15:47 +02003462 mdiobus_free(bus);
Andrew Lunn3126aee2017-12-07 01:05:57 +01003463 }
3464}
3465
Andrew Lunna3c53be52017-01-24 14:53:50 +01003466static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3467 struct device_node *np)
3468{
Andrew Lunna3c53be52017-01-24 14:53:50 +01003469 struct device_node *child;
3470 int err;
3471
3472 /* Always register one mdio bus for the internal/default mdio
3473 * bus. This maybe represented in the device tree, but is
3474 * optional.
3475 */
3476 child = of_get_child_by_name(np, "mdio");
3477 err = mv88e6xxx_mdio_register(chip, child, false);
3478 if (err)
3479 return err;
3480
3481 /* Walk the device tree, and see if there are any other nodes
3482 * which say they are compatible with the external mdio
3483 * bus.
3484 */
3485 for_each_available_child_of_node(np, child) {
Andrew Lunnceb96fa2020-09-01 04:32:57 +02003486 if (of_device_is_compatible(
3487 child, "marvell,mv88e6xxx-mdio-external")) {
Andrew Lunna3c53be52017-01-24 14:53:50 +01003488 err = mv88e6xxx_mdio_register(chip, child, true);
Andrew Lunn3126aee2017-12-07 01:05:57 +01003489 if (err) {
3490 mv88e6xxx_mdios_unregister(chip);
Nishka Dasgupta78e42042019-07-23 16:13:07 +05303491 of_node_put(child);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003492 return err;
Andrew Lunn3126aee2017-12-07 01:05:57 +01003493 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003494 }
3495 }
3496
3497 return 0;
3498}
3499
Vivien Didelot855b1932016-07-20 18:18:35 -04003500static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3501{
Vivien Didelot04bed142016-08-31 18:06:13 -04003502 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003503
3504 return chip->eeprom_len;
3505}
3506
Vivien Didelot855b1932016-07-20 18:18:35 -04003507static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3508 struct ethtool_eeprom *eeprom, u8 *data)
3509{
Vivien Didelot04bed142016-08-31 18:06:13 -04003510 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003511 int err;
3512
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003513 if (!chip->info->ops->get_eeprom)
3514 return -EOPNOTSUPP;
3515
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003516 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003517 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003518 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003519
3520 if (err)
3521 return err;
3522
3523 eeprom->magic = 0xc3ec4951;
3524
3525 return 0;
3526}
3527
Vivien Didelot855b1932016-07-20 18:18:35 -04003528static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3529 struct ethtool_eeprom *eeprom, u8 *data)
3530{
Vivien Didelot04bed142016-08-31 18:06:13 -04003531 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003532 int err;
3533
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003534 if (!chip->info->ops->set_eeprom)
3535 return -EOPNOTSUPP;
3536
Vivien Didelot855b1932016-07-20 18:18:35 -04003537 if (eeprom->magic != 0xc3ec4951)
3538 return -EINVAL;
3539
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003540 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003541 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003542 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003543
3544 return err;
3545}
3546
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003547static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003548 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003549 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3550 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003551 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003552 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003553 .phy_read = mv88e6185_phy_ppu_read,
3554 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003555 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003556 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003557 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003558 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003559 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003560 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3561 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003562 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003563 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003564 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003565 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003566 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003567 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003568 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003569 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003570 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003571 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3572 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003573 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003574 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3575 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003576 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003577 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003578 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003579 .ppu_enable = mv88e6185_g1_ppu_enable,
3580 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003581 .reset = mv88e6185_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003582 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003583 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003584 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003585 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003586 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003587};
3588
3589static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003590 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003591 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3592 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003593 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003594 .phy_read = mv88e6185_phy_ppu_read,
3595 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003596 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003597 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003598 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003599 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003600 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3601 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunna23b2962017-02-04 20:15:28 +01003602 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003603 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003604 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003605 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003606 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003607 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3608 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003609 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003610 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003611 .serdes_power = mv88e6185_serdes_power,
3612 .serdes_get_lane = mv88e6185_serdes_get_lane,
3613 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003614 .ppu_enable = mv88e6185_g1_ppu_enable,
3615 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003616 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003617 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003618 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003619 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003620 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003621};
3622
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003623static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01003624 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003625 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3626 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003627 .irl_init_all = mv88e6352_g2_irl_init_all,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003628 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3629 .phy_read = mv88e6xxx_g2_smi_phy_read,
3630 .phy_write = mv88e6xxx_g2_smi_phy_write,
3631 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003632 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003633 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003634 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003635 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003636 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3637 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003638 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003639 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003640 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003641 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003642 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003643 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003644 .port_setup_message_port = mv88e6xxx_setup_message_port,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003645 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003646 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003647 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3648 .stats_get_strings = mv88e6095_stats_get_strings,
3649 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003650 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3651 .set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01003652 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003653 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003654 .serdes_power = mv88e6185_serdes_power,
3655 .serdes_get_lane = mv88e6185_serdes_get_lane,
3656 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Chris Packham5c19bc82020-11-24 17:34:39 +13003657 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3658 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3659 .serdes_irq_status = mv88e6097_serdes_irq_status,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003660 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003661 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003662 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003663 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003664 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003665 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003666 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003667};
3668
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003669static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003670 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003671 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3672 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003673 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003674 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003675 .phy_read = mv88e6xxx_g2_smi_phy_read,
3676 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003677 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003678 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003679 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003680 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003681 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3682 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003683 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003684 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003685 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003686 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn0ac64c32017-06-02 23:22:46 +02003687 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003688 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003689 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3690 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003691 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003692 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3693 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003694 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003695 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003696 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003697 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003698 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3699 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003700 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003701 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003702 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003703 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003704};
3705
3706static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003707 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003708 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3709 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003710 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003711 .phy_read = mv88e6185_phy_ppu_read,
3712 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003713 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003714 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003715 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003716 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003717 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003718 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3719 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003720 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01003721 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Vivien Didelotcd782652017-06-08 18:34:13 -04003722 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003724 .port_pause_limit = mv88e6097_port_pause_limit,
Andrew Lunn54186b92018-08-09 15:38:37 +02003725 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003726 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003727 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003728 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003729 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003730 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3731 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003732 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003733 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3734 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003735 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003736 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003737 .ppu_enable = mv88e6185_g1_ppu_enable,
Vivien Didelot02317e62018-05-09 11:38:49 -04003738 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003739 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003740 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003741 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003742 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003743 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003744};
3745
Vivien Didelot990e27b2017-03-28 13:50:32 -04003746static const struct mv88e6xxx_ops mv88e6141_ops = {
3747 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003748 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3749 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003750 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003751 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3752 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3754 .phy_read = mv88e6xxx_g2_smi_phy_read,
3755 .phy_write = mv88e6xxx_g2_smi_phy_write,
3756 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003757 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003758 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003759 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003760 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003761 .port_tag_remap = mv88e6095_port_tag_remap,
Marek Behún7da467d2021-07-01 00:22:26 +02003762 .port_set_policy = mv88e6352_port_set_policy,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003763 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003764 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3765 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003766 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003767 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003768 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003769 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003770 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3771 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003772 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02003773 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003774 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003775 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Marek Behún11527f32021-07-01 00:22:27 +02003776 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003777 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3778 .stats_get_strings = mv88e6320_stats_get_strings,
3779 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003780 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3781 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003782 .watchdog_ops = &mv88e6390_watchdog_ops,
3783 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003784 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003785 .reset = mv88e6352_g1_reset,
Marek Behún37094882021-07-01 00:22:28 +02003786 .rmu_disable = mv88e6390_g1_rmu_disable,
Marek Behúnc07fff32021-07-01 00:22:29 +02003787 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3788 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003789 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003790 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02003791 .serdes_power = mv88e6390_serdes_power,
3792 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003793 /* Check status register pause & lpa register */
3794 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3795 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3796 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3797 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003798 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003799 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003800 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003801 .gpio_ops = &mv88e6352_gpio_ops,
Marek Behúna03b98d2021-07-01 00:22:30 +02003802 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3803 .serdes_get_strings = mv88e6390_serdes_get_strings,
3804 .serdes_get_stats = mv88e6390_serdes_get_stats,
Marek Behún953b0dc2021-07-01 00:22:31 +02003805 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3806 .serdes_get_regs = mv88e6390_serdes_get_regs,
Marek Behúne3af71a2019-02-25 12:39:55 +01003807 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003808};
3809
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003810static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003811 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003812 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3813 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003814 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003815 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003816 .phy_read = mv88e6xxx_g2_smi_phy_read,
3817 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003818 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003819 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003820 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003821 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003822 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003823 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3824 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003825 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003826 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003827 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003828 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003829 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003830 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003831 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna6da21b2019-03-01 23:43:39 +01003832 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003833 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003834 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3835 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003836 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003837 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3838 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003839 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003840 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003841 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003842 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003843 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3844 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003845 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003846 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003847 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003848 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003849 .phylink_validate = mv88e6185_phylink_validate,
Andrew Lunnfe230362021-09-26 19:41:24 +02003850 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003851};
3852
3853static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003854 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003855 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3856 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003857 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003858 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003859 .phy_read = mv88e6165_phy_read,
3860 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003861 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003862 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003863 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003864 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003865 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003866 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003867 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003868 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003869 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003870 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3871 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003872 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003873 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3874 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003875 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003876 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003877 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003878 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003879 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3880 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003881 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003882 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003883 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003884 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003885 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003886};
3887
3888static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003889 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003890 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3891 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003892 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003893 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003894 .phy_read = mv88e6xxx_g2_smi_phy_read,
3895 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003896 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003897 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003898 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003899 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003900 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003901 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003902 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3903 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003904 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003905 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003906 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003907 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003908 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003909 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003910 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003911 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003912 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003913 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003914 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3915 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003916 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003917 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3918 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003919 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003920 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003921 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003922 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003923 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3924 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003925 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003926 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003927 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003928};
3929
3930static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003931 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003932 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3933 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003934 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003935 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3936 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003937 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003938 .phy_read = mv88e6xxx_g2_smi_phy_read,
3939 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003940 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003941 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003942 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003943 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003944 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003945 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003946 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003947 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3948 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003949 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003950 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003951 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003952 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003953 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003954 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003955 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003956 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003957 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003958 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003959 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3960 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003961 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003962 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3963 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003964 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003965 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003966 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003967 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003968 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003969 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3970 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003971 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003972 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003973 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003974 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3975 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3976 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3977 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003978 .serdes_power = mv88e6352_serdes_power,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003979 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3980 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003981 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003982 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003983};
3984
3985static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003986 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003987 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3988 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003989 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003990 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003991 .phy_read = mv88e6xxx_g2_smi_phy_read,
3992 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003993 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003994 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003995 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003996 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003997 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003998 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003999 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4000 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004001 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004002 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004003 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004004 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004005 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004006 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004007 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004008 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004009 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004010 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004011 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4012 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004013 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004014 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4015 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004016 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004017 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004018 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004019 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004020 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4021 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004022 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004023 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004024 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004025};
4026
4027static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004028 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004029 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4030 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004031 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004032 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4033 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004035 .phy_read = mv88e6xxx_g2_smi_phy_read,
4036 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004037 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004038 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004039 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004040 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004041 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004042 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004043 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004044 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4045 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004046 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004047 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004048 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004049 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004050 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004051 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004052 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004053 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004054 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004055 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004056 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4057 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004058 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004059 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4060 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004061 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004062 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004063 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004064 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004065 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004066 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4067 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004068 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004069 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004070 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004071 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4072 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4073 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4074 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004075 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004076 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004077 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004078 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004079 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4080 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004081 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004082 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004083};
4084
4085static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004086 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004087 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4088 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004089 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04004090 .phy_read = mv88e6185_phy_ppu_read,
4091 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004092 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004093 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004094 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004095 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004096 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4097 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunnef70b112016-12-03 04:45:18 +01004098 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01004099 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn54186b92018-08-09 15:38:37 +02004100 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004101 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004102 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004103 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004104 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004105 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4106 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004107 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004108 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4109 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004110 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004111 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13004112 .serdes_power = mv88e6185_serdes_power,
4113 .serdes_get_lane = mv88e6185_serdes_get_lane,
4114 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Vivien Didelot02317e62018-05-09 11:38:49 -04004115 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05004116 .ppu_enable = mv88e6185_g1_ppu_enable,
4117 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004118 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004119 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004120 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004121 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12004122 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004123};
4124
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004125static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004126 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004127 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004128 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004129 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4130 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004131 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4132 .phy_read = mv88e6xxx_g2_smi_phy_read,
4133 .phy_write = mv88e6xxx_g2_smi_phy_write,
4134 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004135 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004136 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004137 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004138 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004139 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004140 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004141 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004142 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4143 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004144 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12004145 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04004146 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004147 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004148 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004149 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004150 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004151 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004152 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004153 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004154 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4155 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004156 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004157 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4158 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004159 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004160 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004161 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004162 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004163 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004164 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4165 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004166 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4167 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004168 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004169 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004170 /* Check status register pause & lpa register */
4171 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4172 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4173 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4174 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004175 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004176 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004177 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004178 .serdes_get_strings = mv88e6390_serdes_get_strings,
4179 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004180 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4181 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004182 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004183 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004184};
4185
4186static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004187 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004188 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004189 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004190 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4191 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004192 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4193 .phy_read = mv88e6xxx_g2_smi_phy_read,
4194 .phy_write = mv88e6xxx_g2_smi_phy_write,
4195 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004196 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004197 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004198 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004199 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004200 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004201 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004202 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004203 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4204 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004205 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12004206 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04004207 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004208 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004209 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004210 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004211 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004212 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004213 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004214 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004215 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4216 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004217 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004218 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4219 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004220 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004221 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004222 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004223 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004224 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004225 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4226 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004227 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4228 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004229 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004230 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004231 /* Check status register pause & lpa register */
4232 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4233 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4234 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4235 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004236 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004237 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004238 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004239 .serdes_get_strings = mv88e6390_serdes_get_strings,
4240 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004241 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4242 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004243 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004244 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004245};
4246
4247static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004248 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004249 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004250 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004251 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4252 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004253 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4254 .phy_read = mv88e6xxx_g2_smi_phy_read,
4255 .phy_write = mv88e6xxx_g2_smi_phy_write,
4256 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004257 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004258 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004259 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004260 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004261 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004262 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004263 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4264 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004265 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004266 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004267 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004268 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004269 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004270 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004271 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004272 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004273 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004274 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4275 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004276 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004277 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4278 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004279 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004280 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004281 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004282 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004283 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004284 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4285 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004286 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4287 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004288 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004289 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004290 /* Check status register pause & lpa register */
4291 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4292 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4293 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4294 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004295 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004296 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004297 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004298 .serdes_get_strings = mv88e6390_serdes_get_strings,
4299 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004300 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4301 .serdes_get_regs = mv88e6390_serdes_get_regs,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004302 .avb_ops = &mv88e6390_avb_ops,
4303 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004304 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004305};
4306
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004307static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004308 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004309 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4310 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004311 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004312 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4313 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004315 .phy_read = mv88e6xxx_g2_smi_phy_read,
4316 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004317 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004318 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004319 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004320 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004321 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004322 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004323 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004324 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4325 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004326 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004327 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004328 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004329 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004330 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004331 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004332 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004333 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004334 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004335 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004336 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4337 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004338 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004339 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4340 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004341 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004342 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004343 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004344 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004345 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004346 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4347 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004348 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004349 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004350 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004351 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4352 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4353 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4354 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004355 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004356 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004357 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004358 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004359 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4360 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004361 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004362 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004363 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004364 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004365};
4366
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004367static const struct mv88e6xxx_ops mv88e6250_ops = {
4368 /* MV88E6XXX_FAMILY_6250 */
4369 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4370 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4371 .irl_init_all = mv88e6352_g2_irl_init_all,
4372 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4373 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4374 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4375 .phy_read = mv88e6xxx_g2_smi_phy_read,
4376 .phy_write = mv88e6xxx_g2_smi_phy_write,
4377 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004378 .port_sync_link = mv88e6xxx_port_sync_link,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004379 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004380 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004381 .port_tag_remap = mv88e6095_port_tag_remap,
4382 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004383 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4384 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004385 .port_set_ether_type = mv88e6351_port_set_ether_type,
4386 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4387 .port_pause_limit = mv88e6097_port_pause_limit,
4388 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004389 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4390 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4391 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4392 .stats_get_strings = mv88e6250_stats_get_strings,
4393 .stats_get_stats = mv88e6250_stats_get_stats,
4394 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4395 .set_egress_port = mv88e6095_g1_set_egress_port,
4396 .watchdog_ops = &mv88e6250_watchdog_ops,
4397 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4398 .pot_clear = mv88e6xxx_g2_pot_clear,
4399 .reset = mv88e6250_g1_reset,
Rasmus Villemoes67c9ed12021-01-25 16:04:48 +01004400 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Rasmus Villemoesb28f3f32021-01-25 16:04:49 +01004401 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Hubert Feurstein71509612019-07-31 10:23:51 +02004402 .avb_ops = &mv88e6352_avb_ops,
4403 .ptp_ops = &mv88e6250_ptp_ops,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004404 .phylink_validate = mv88e6065_phylink_validate,
4405};
4406
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004407static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004408 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004409 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004410 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004411 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4412 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4414 .phy_read = mv88e6xxx_g2_smi_phy_read,
4415 .phy_write = mv88e6xxx_g2_smi_phy_write,
4416 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004417 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004418 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004419 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004420 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004421 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004422 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004423 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004424 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4425 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004426 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004427 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004428 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004429 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004430 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004431 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004432 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004433 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004434 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004435 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4436 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004437 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004438 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4439 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004440 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004441 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004442 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004443 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004444 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004445 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4446 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004447 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4448 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004449 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004450 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004451 /* Check status register pause & lpa register */
4452 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4453 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4454 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4455 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004456 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004457 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004458 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004459 .serdes_get_strings = mv88e6390_serdes_get_strings,
4460 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004461 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4462 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004463 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004464 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004465 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004466 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004467};
4468
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004469static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004470 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004471 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4472 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004473 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004474 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4475 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004476 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004477 .phy_read = mv88e6xxx_g2_smi_phy_read,
4478 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004479 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004480 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004481 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004482 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004483 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004484 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4485 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004486 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004487 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004488 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004489 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004492 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004493 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004494 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004496 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4497 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004498 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004499 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4500 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004501 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004503 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004504 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004505 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004506 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004507 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004508 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004509 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004510 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004511};
4512
4513static const struct mv88e6xxx_ops mv88e6321_ops = {
Vivien Didelotbd807202017-07-17 13:03:37 -04004514 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004515 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4516 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004517 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004518 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4519 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004520 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004521 .phy_read = mv88e6xxx_g2_smi_phy_read,
4522 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004523 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004524 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004525 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004526 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004527 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004528 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4529 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004530 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004531 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004532 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004533 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004534 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004535 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004536 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004537 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004538 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004539 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004540 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4541 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004542 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004543 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4544 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004545 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004546 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004547 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004548 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004549 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004550 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004551 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004552 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004553};
4554
Vivien Didelot16e329a2017-03-28 13:50:33 -04004555static const struct mv88e6xxx_ops mv88e6341_ops = {
4556 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004557 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4558 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004559 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004560 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4561 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4562 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4563 .phy_read = mv88e6xxx_g2_smi_phy_read,
4564 .phy_write = mv88e6xxx_g2_smi_phy_write,
4565 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004566 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004567 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004568 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004569 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004570 .port_tag_remap = mv88e6095_port_tag_remap,
Marek Behún7da467d2021-07-01 00:22:26 +02004571 .port_set_policy = mv88e6352_port_set_policy,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004572 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004573 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4574 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004575 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004576 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004577 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004578 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004579 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4580 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004581 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02004582 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004583 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004584 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Marek Behún11527f32021-07-01 00:22:27 +02004585 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004586 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4587 .stats_get_strings = mv88e6320_stats_get_strings,
4588 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004589 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4590 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004591 .watchdog_ops = &mv88e6390_watchdog_ops,
4592 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004593 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004594 .reset = mv88e6352_g1_reset,
Marek Behún37094882021-07-01 00:22:28 +02004595 .rmu_disable = mv88e6390_g1_rmu_disable,
Marek Behúnc07fff32021-07-01 00:22:29 +02004596 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4597 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004598 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004599 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004600 .serdes_power = mv88e6390_serdes_power,
4601 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004602 /* Check status register pause & lpa register */
4603 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4604 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4605 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4606 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004607 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004608 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004609 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004610 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004611 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004612 .ptp_ops = &mv88e6352_ptp_ops,
Marek Behúna03b98d2021-07-01 00:22:30 +02004613 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4614 .serdes_get_strings = mv88e6390_serdes_get_strings,
4615 .serdes_get_stats = mv88e6390_serdes_get_stats,
Marek Behún953b0dc2021-07-01 00:22:31 +02004616 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4617 .serdes_get_regs = mv88e6390_serdes_get_regs,
Marek Behúne3af71a2019-02-25 12:39:55 +01004618 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004619};
4620
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004621static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004622 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004623 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4624 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004625 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004626 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004627 .phy_read = mv88e6xxx_g2_smi_phy_read,
4628 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004629 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004630 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004631 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004632 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004633 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004634 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004635 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4636 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004637 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004638 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004639 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004640 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004641 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004642 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004643 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004644 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004645 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004646 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004647 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4648 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004649 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004650 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4651 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004652 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004653 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004654 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004655 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004656 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4657 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004658 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004660 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004661};
4662
4663static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004664 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004665 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4666 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004667 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004668 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004669 .phy_read = mv88e6xxx_g2_smi_phy_read,
4670 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004671 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004672 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004673 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004674 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004675 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004676 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004677 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4678 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004679 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004680 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004681 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004682 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004683 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004684 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004685 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004686 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004687 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004688 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004689 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4690 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004691 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004692 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4693 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004694 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004695 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004696 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004697 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004698 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4699 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004700 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004701 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004702 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004703 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004704 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004705};
4706
4707static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004708 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004709 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4710 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004711 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004712 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4713 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004714 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004715 .phy_read = mv88e6xxx_g2_smi_phy_read,
4716 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004717 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004718 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004719 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004720 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004721 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004722 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004723 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004724 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4725 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004726 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004727 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004728 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004729 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004730 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004731 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004732 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004733 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004734 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004735 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004736 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4737 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004738 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004739 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4740 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004741 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004742 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004743 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004744 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004745 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004746 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4747 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004748 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004749 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004750 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004751 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4752 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4753 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4754 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004755 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004756 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004757 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004758 .serdes_irq_status = mv88e6352_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004759 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004760 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004761 .ptp_ops = &mv88e6352_ptp_ops,
Andrew Lunncda9f4a2018-03-01 02:02:31 +01004762 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4763 .serdes_get_strings = mv88e6352_serdes_get_strings,
4764 .serdes_get_stats = mv88e6352_serdes_get_stats,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004765 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4766 .serdes_get_regs = mv88e6352_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004767 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004768};
4769
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004770static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004771 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004772 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004773 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004774 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4775 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004776 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4777 .phy_read = mv88e6xxx_g2_smi_phy_read,
4778 .phy_write = mv88e6xxx_g2_smi_phy_write,
4779 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004780 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004781 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004782 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004783 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004784 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004785 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004786 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004787 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4788 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004789 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004790 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004791 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004792 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004793 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004794 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004795 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004796 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004797 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004798 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004799 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004800 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4801 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004802 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004803 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4804 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004805 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004806 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004807 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004808 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004809 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004810 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4811 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004812 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4813 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004814 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004815 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004816 /* Check status register pause & lpa register */
4817 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4818 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4819 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4820 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004821 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004822 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004823 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004824 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004825 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004826 .ptp_ops = &mv88e6352_ptp_ops,
Nikita Yushchenko0df95282019-12-25 08:22:38 +03004827 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4828 .serdes_get_strings = mv88e6390_serdes_get_strings,
4829 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004830 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4831 .serdes_get_regs = mv88e6390_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004832 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004833};
4834
4835static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004836 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004837 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004838 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004839 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4840 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004841 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4842 .phy_read = mv88e6xxx_g2_smi_phy_read,
4843 .phy_write = mv88e6xxx_g2_smi_phy_write,
4844 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004845 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004846 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004847 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004848 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004849 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004850 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004851 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004852 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4853 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004854 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004855 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004856 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004857 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004858 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004859 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004860 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnb3dce4d2018-11-11 00:32:14 +01004861 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004862 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004863 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004864 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004865 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4866 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004867 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004868 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4869 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004870 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004871 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004872 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004873 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004874 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004875 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4876 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004877 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4878 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004879 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004880 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004881 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4882 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4883 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4884 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004885 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004886 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004887 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004888 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4889 .serdes_get_strings = mv88e6390_serdes_get_strings,
4890 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004891 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4892 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004893 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004894 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004895 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004896 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004897};
4898
Pavana Sharmade776d02021-03-17 14:46:42 +01004899static const struct mv88e6xxx_ops mv88e6393x_ops = {
4900 /* MV88E6XXX_FAMILY_6393 */
4901 .setup_errata = mv88e6393x_serdes_setup_errata,
4902 .irl_init_all = mv88e6390_g2_irl_init_all,
4903 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4904 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4905 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4906 .phy_read = mv88e6xxx_g2_smi_phy_read,
4907 .phy_write = mv88e6xxx_g2_smi_phy_write,
4908 .port_set_link = mv88e6xxx_port_set_link,
4909 .port_sync_link = mv88e6xxx_port_sync_link,
4910 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4911 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4912 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4913 .port_tag_remap = mv88e6390_port_tag_remap,
Marek Behún6584b262021-03-17 14:46:43 +01004914 .port_set_policy = mv88e6393x_port_set_policy,
Pavana Sharmade776d02021-03-17 14:46:42 +01004915 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4916 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4917 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4918 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4919 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4920 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4921 .port_pause_limit = mv88e6390_port_pause_limit,
4922 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4923 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4924 .port_get_cmode = mv88e6352_port_get_cmode,
4925 .port_set_cmode = mv88e6393x_port_set_cmode,
4926 .port_setup_message_port = mv88e6xxx_setup_message_port,
4927 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4928 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4929 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4930 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4931 .stats_get_strings = mv88e6320_stats_get_strings,
4932 .stats_get_stats = mv88e6390_stats_get_stats,
4933 /* .set_cpu_port is missing because this family does not support a global
4934 * CPU port, only per port CPU port which is set via
4935 * .port_set_upstream_port method.
4936 */
4937 .set_egress_port = mv88e6393x_set_egress_port,
4938 .watchdog_ops = &mv88e6390_watchdog_ops,
4939 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4940 .pot_clear = mv88e6xxx_g2_pot_clear,
4941 .reset = mv88e6352_g1_reset,
4942 .rmu_disable = mv88e6390_g1_rmu_disable,
4943 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4944 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4945 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4946 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4947 .serdes_power = mv88e6393x_serdes_power,
4948 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4949 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4950 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4951 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4952 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4953 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4954 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4955 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4956 /* TODO: serdes stats */
4957 .gpio_ops = &mv88e6352_gpio_ops,
4958 .avb_ops = &mv88e6390_avb_ops,
4959 .ptp_ops = &mv88e6352_ptp_ops,
4960 .phylink_validate = mv88e6393x_phylink_validate,
4961};
4962
Vivien Didelotf81ec902016-05-09 13:22:58 -04004963static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4964 [MV88E6085] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004965 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004966 .family = MV88E6XXX_FAMILY_6097,
4967 .name = "Marvell 88E6085",
4968 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004969 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004970 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01004971 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004972 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004973 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004974 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004975 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004976 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004977 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004978 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004979 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004980 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004981 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004982 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004983 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004984 },
4985
4986 [MV88E6095] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004987 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004988 .family = MV88E6XXX_FAMILY_6095,
4989 .name = "Marvell 88E6095/88E6095F",
4990 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004991 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004992 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01004993 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004994 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004995 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004996 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004997 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004998 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004999 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005000 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05005001 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005002 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005003 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005004 },
5005
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005006 [MV88E6097] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005007 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005008 .family = MV88E6XXX_FAMILY_6097,
5009 .name = "Marvell 88E6097/88E6097F",
5010 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005011 .num_macs = 8192,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005012 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01005013 .num_internal_phys = 8,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005014 .max_vid = 4095,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005015 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005016 .phy_base_addr = 0x0,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005017 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005018 .global2_addr = 0x1c,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005019 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01005020 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005021 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005022 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005023 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005024 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005025 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005026 .ops = &mv88e6097_ops,
5027 },
5028
Vivien Didelotf81ec902016-05-09 13:22:58 -04005029 [MV88E6123] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005030 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005031 .family = MV88E6XXX_FAMILY_6165,
5032 .name = "Marvell 88E6123",
5033 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005034 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005035 .num_ports = 3,
Andrew Lunnbc393152018-03-17 20:32:04 +01005036 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005037 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005038 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005039 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005040 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005041 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005042 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005043 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005044 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005045 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005046 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005047 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005048 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005049 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005050 },
5051
5052 [MV88E6131] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005053 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005054 .family = MV88E6XXX_FAMILY_6185,
5055 .name = "Marvell 88E6131",
5056 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005057 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005058 .num_ports = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005059 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005060 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005061 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005062 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005063 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005064 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005065 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005066 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05005067 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005068 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005069 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005070 },
5071
Vivien Didelot990e27b2017-03-28 13:50:32 -04005072 [MV88E6141] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005073 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005074 .family = MV88E6XXX_FAMILY_6341,
Uwe Kleine-König79a68b22018-03-20 10:44:40 +01005075 .name = "Marvell 88E6141",
Vivien Didelot990e27b2017-03-28 13:50:32 -04005076 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005077 .num_macs = 2048,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005078 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01005079 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005080 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005081 .max_vid = 4095,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005082 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005083 .phy_base_addr = 0x10,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005084 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005085 .global2_addr = 0x1c,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005086 .age_time_coeff = 3750,
5087 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01005088 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005089 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04005090 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005091 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005092 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005093 .ops = &mv88e6141_ops,
5094 },
5095
Vivien Didelotf81ec902016-05-09 13:22:58 -04005096 [MV88E6161] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005097 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005098 .family = MV88E6XXX_FAMILY_6165,
5099 .name = "Marvell 88E6161",
5100 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005101 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005102 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01005103 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005104 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005105 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005106 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005107 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005108 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005109 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005110 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005111 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005112 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005113 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005114 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005115 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Andrew Lunndfa54342018-07-18 22:38:22 +02005116 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005117 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005118 },
5119
5120 [MV88E6165] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005121 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005122 .family = MV88E6XXX_FAMILY_6165,
5123 .name = "Marvell 88E6165",
5124 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005125 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005126 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01005127 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005128 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005129 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005130 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005131 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005132 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005133 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005134 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005135 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005136 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005137 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005138 .multi_chip = true,
Andrew Lunndfa54342018-07-18 22:38:22 +02005139 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005140 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005141 },
5142
5143 [MV88E6171] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005144 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005145 .family = MV88E6XXX_FAMILY_6351,
5146 .name = "Marvell 88E6171",
5147 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005148 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005149 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005150 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005151 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005152 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005153 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005154 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005155 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005156 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005157 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005158 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005159 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005160 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005161 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005162 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005163 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005164 },
5165
5166 [MV88E6172] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005167 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005168 .family = MV88E6XXX_FAMILY_6352,
5169 .name = "Marvell 88E6172",
5170 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005171 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005172 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005173 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005174 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005175 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005176 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005177 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005178 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005179 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005180 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005181 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005182 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005183 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005184 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005185 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005186 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005187 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005188 },
5189
5190 [MV88E6175] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005191 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005192 .family = MV88E6XXX_FAMILY_6351,
5193 .name = "Marvell 88E6175",
5194 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005195 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005196 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005197 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005198 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005199 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005200 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005201 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005202 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005203 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005204 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005205 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005206 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005207 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005208 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005209 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005210 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005211 },
5212
5213 [MV88E6176] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005214 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005215 .family = MV88E6XXX_FAMILY_6352,
5216 .name = "Marvell 88E6176",
5217 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005218 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005219 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005220 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005221 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005222 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005223 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005224 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005225 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005226 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005227 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005228 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005229 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005230 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005231 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005232 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005233 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005234 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005235 },
5236
5237 [MV88E6185] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005238 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005239 .family = MV88E6XXX_FAMILY_6185,
5240 .name = "Marvell 88E6185",
5241 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005242 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005243 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01005244 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005245 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005246 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005247 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005248 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005249 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005250 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005251 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05005252 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005253 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005254 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005255 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005256 },
5257
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005258 [MV88E6190] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005259 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005260 .family = MV88E6XXX_FAMILY_6390,
5261 .name = "Marvell 88E6190",
5262 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005263 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005264 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005265 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005266 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005267 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005268 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005269 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005270 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005271 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005272 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005273 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005274 .g2_irqs = 14,
Vivien Didelotf3645652017-03-30 17:37:07 -04005275 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005276 .multi_chip = true,
Vivien Didelote606ca32017-03-11 16:12:55 -05005277 .atu_move_port_mask = 0x1f,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005278 .ops = &mv88e6190_ops,
5279 },
5280
5281 [MV88E6190X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005282 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005283 .family = MV88E6XXX_FAMILY_6390,
5284 .name = "Marvell 88E6190X",
5285 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005286 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005287 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005288 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005289 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005290 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005291 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005292 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005293 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005294 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005295 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005296 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005297 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005298 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005299 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005300 .multi_chip = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005301 .ops = &mv88e6190x_ops,
5302 },
5303
5304 [MV88E6191] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005305 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005306 .family = MV88E6XXX_FAMILY_6390,
5307 .name = "Marvell 88E6191",
5308 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005309 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005310 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005311 .num_internal_phys = 9,
Vivien Didelot931d1822017-05-01 14:05:27 -04005312 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005313 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005314 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005315 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005316 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005317 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005318 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005319 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005320 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005321 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005322 .multi_chip = true,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005323 .ptp_support = true,
Vivien Didelot2cf4cefb2017-03-28 13:50:34 -04005324 .ops = &mv88e6191_ops,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005325 },
5326
Pavana Sharmade776d02021-03-17 14:46:42 +01005327 [MV88E6191X] = {
5328 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5329 .family = MV88E6XXX_FAMILY_6393,
5330 .name = "Marvell 88E6191X",
5331 .num_databases = 4096,
5332 .num_ports = 11, /* 10 + Z80 */
5333 .num_internal_phys = 9,
5334 .max_vid = 8191,
5335 .port_base_addr = 0x0,
5336 .phy_base_addr = 0x0,
5337 .global1_addr = 0x1b,
5338 .global2_addr = 0x1c,
5339 .age_time_coeff = 3750,
5340 .g1_irqs = 10,
5341 .g2_irqs = 14,
5342 .atu_move_port_mask = 0x1f,
5343 .pvt = true,
5344 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005345 .ptp_support = true,
5346 .ops = &mv88e6393x_ops,
5347 },
5348
5349 [MV88E6193X] = {
5350 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5351 .family = MV88E6XXX_FAMILY_6393,
5352 .name = "Marvell 88E6193X",
5353 .num_databases = 4096,
5354 .num_ports = 11, /* 10 + Z80 */
5355 .num_internal_phys = 9,
5356 .max_vid = 8191,
5357 .port_base_addr = 0x0,
5358 .phy_base_addr = 0x0,
5359 .global1_addr = 0x1b,
5360 .global2_addr = 0x1c,
5361 .age_time_coeff = 3750,
5362 .g1_irqs = 10,
5363 .g2_irqs = 14,
5364 .atu_move_port_mask = 0x1f,
5365 .pvt = true,
5366 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005367 .ptp_support = true,
5368 .ops = &mv88e6393x_ops,
5369 },
5370
Hubert Feurstein49022642019-07-31 10:23:46 +02005371 [MV88E6220] = {
5372 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5373 .family = MV88E6XXX_FAMILY_6250,
5374 .name = "Marvell 88E6220",
5375 .num_databases = 64,
5376
5377 /* Ports 2-4 are not routed to pins
5378 * => usable ports 0, 1, 5, 6
5379 */
5380 .num_ports = 7,
5381 .num_internal_phys = 2,
Hubert Feursteinc8574862019-07-31 10:23:48 +02005382 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
Hubert Feurstein49022642019-07-31 10:23:46 +02005383 .max_vid = 4095,
5384 .port_base_addr = 0x08,
5385 .phy_base_addr = 0x00,
5386 .global1_addr = 0x0f,
5387 .global2_addr = 0x07,
5388 .age_time_coeff = 15000,
5389 .g1_irqs = 9,
5390 .g2_irqs = 10,
5391 .atu_move_port_mask = 0xf,
5392 .dual_chip = true,
Hubert Feurstein71509612019-07-31 10:23:51 +02005393 .ptp_support = true,
Hubert Feurstein49022642019-07-31 10:23:46 +02005394 .ops = &mv88e6250_ops,
5395 },
5396
Vivien Didelotf81ec902016-05-09 13:22:58 -04005397 [MV88E6240] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005398 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005399 .family = MV88E6XXX_FAMILY_6352,
5400 .name = "Marvell 88E6240",
5401 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005402 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005403 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005404 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005405 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005406 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005407 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005408 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005409 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005410 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005411 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005412 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005413 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005414 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005415 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005416 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005417 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005418 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005419 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005420 },
5421
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005422 [MV88E6250] = {
5423 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5424 .family = MV88E6XXX_FAMILY_6250,
5425 .name = "Marvell 88E6250",
5426 .num_databases = 64,
5427 .num_ports = 7,
5428 .num_internal_phys = 5,
5429 .max_vid = 4095,
5430 .port_base_addr = 0x08,
5431 .phy_base_addr = 0x00,
5432 .global1_addr = 0x0f,
5433 .global2_addr = 0x07,
5434 .age_time_coeff = 15000,
5435 .g1_irqs = 9,
5436 .g2_irqs = 10,
5437 .atu_move_port_mask = 0xf,
5438 .dual_chip = true,
Hubert Feurstein71509612019-07-31 10:23:51 +02005439 .ptp_support = true,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005440 .ops = &mv88e6250_ops,
5441 },
5442
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005443 [MV88E6290] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005444 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005445 .family = MV88E6XXX_FAMILY_6390,
5446 .name = "Marvell 88E6290",
5447 .num_databases = 4096,
5448 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005449 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005450 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005451 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005452 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005453 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005454 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005455 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005456 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005457 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005458 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005459 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005460 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005461 .multi_chip = true,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005462 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005463 .ops = &mv88e6290_ops,
5464 },
5465
Vivien Didelotf81ec902016-05-09 13:22:58 -04005466 [MV88E6320] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005467 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005468 .family = MV88E6XXX_FAMILY_6320,
5469 .name = "Marvell 88E6320",
5470 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005471 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005472 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005473 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005474 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005475 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005476 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005477 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005478 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005479 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005480 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005481 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005482 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005483 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005484 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005485 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005486 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005487 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005488 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005489 },
5490
5491 [MV88E6321] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005492 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005493 .family = MV88E6XXX_FAMILY_6320,
5494 .name = "Marvell 88E6321",
5495 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005496 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005497 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005498 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005499 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005500 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005501 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005502 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005503 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005504 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005505 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005506 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005507 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005508 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005509 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005510 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005511 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005512 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005513 },
5514
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005515 [MV88E6341] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005517 .family = MV88E6XXX_FAMILY_6341,
5518 .name = "Marvell 88E6341",
5519 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005520 .num_macs = 2048,
Andrew Lunnbc393152018-03-17 20:32:04 +01005521 .num_internal_phys = 5,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005522 .num_ports = 6,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005523 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005524 .max_vid = 4095,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005525 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005526 .phy_base_addr = 0x10,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005527 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005528 .global2_addr = 0x1c,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005529 .age_time_coeff = 3750,
Vivien Didelote606ca32017-03-11 16:12:55 -05005530 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01005531 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005532 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04005533 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005534 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005535 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005536 .ptp_support = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005537 .ops = &mv88e6341_ops,
5538 },
5539
Vivien Didelotf81ec902016-05-09 13:22:58 -04005540 [MV88E6350] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005541 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005542 .family = MV88E6XXX_FAMILY_6351,
5543 .name = "Marvell 88E6350",
5544 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005545 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005546 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005547 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005548 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005549 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005550 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005551 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005552 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005553 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005554 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005555 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005556 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005557 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005558 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005559 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005560 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005561 },
5562
5563 [MV88E6351] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005564 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005565 .family = MV88E6XXX_FAMILY_6351,
5566 .name = "Marvell 88E6351",
5567 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005568 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005569 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005570 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005571 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005572 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005573 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005574 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005575 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005576 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005577 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005578 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005579 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005580 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005581 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005582 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005583 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005584 },
5585
5586 [MV88E6352] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005587 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005588 .family = MV88E6XXX_FAMILY_6352,
5589 .name = "Marvell 88E6352",
5590 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005591 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005592 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005593 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005594 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005595 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005596 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005597 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005598 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005599 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005600 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005601 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005602 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005603 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005604 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005605 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005606 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005607 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005608 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005609 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005610 [MV88E6390] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005611 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005612 .family = MV88E6XXX_FAMILY_6390,
5613 .name = "Marvell 88E6390",
5614 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005615 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005616 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005617 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005618 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005619 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005620 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005621 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005622 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005623 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005624 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005625 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005626 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005627 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005628 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005629 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005630 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005631 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005632 .ops = &mv88e6390_ops,
5633 },
5634 [MV88E6390X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005635 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005636 .family = MV88E6XXX_FAMILY_6390,
5637 .name = "Marvell 88E6390X",
5638 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005639 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005640 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005641 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005642 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005643 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005644 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005645 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005646 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005647 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005648 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005649 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005650 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005651 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005652 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005653 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005654 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005655 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005656 .ops = &mv88e6390x_ops,
5657 },
Pavana Sharmade776d02021-03-17 14:46:42 +01005658
5659 [MV88E6393X] = {
5660 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5661 .family = MV88E6XXX_FAMILY_6393,
5662 .name = "Marvell 88E6393X",
5663 .num_databases = 4096,
5664 .num_ports = 11, /* 10 + Z80 */
5665 .num_internal_phys = 9,
5666 .max_vid = 8191,
5667 .port_base_addr = 0x0,
5668 .phy_base_addr = 0x0,
5669 .global1_addr = 0x1b,
5670 .global2_addr = 0x1c,
5671 .age_time_coeff = 3750,
5672 .g1_irqs = 10,
5673 .g2_irqs = 14,
5674 .atu_move_port_mask = 0x1f,
5675 .pvt = true,
5676 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005677 .ptp_support = true,
5678 .ops = &mv88e6393x_ops,
5679 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04005680};
5681
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005682static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04005683{
Vivien Didelota439c062016-04-17 13:23:58 -04005684 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04005685
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005686 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5687 if (mv88e6xxx_table[i].prod_num == prod_num)
5688 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04005689
Vivien Didelotb9b37712015-10-30 19:39:48 -04005690 return NULL;
5691}
5692
Vivien Didelotfad09c72016-06-21 12:28:20 -04005693static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005694{
5695 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005696 unsigned int prod_num, rev;
5697 u16 id;
5698 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005699
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005700 mv88e6xxx_reg_lock(chip);
Vivien Didelot107fcc12017-06-12 12:37:36 -04005701 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005702 mv88e6xxx_reg_unlock(chip);
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005703 if (err)
5704 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005705
Vivien Didelot107fcc12017-06-12 12:37:36 -04005706 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5707 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005708
5709 info = mv88e6xxx_lookup_info(prod_num);
5710 if (!info)
5711 return -ENODEV;
5712
Vivien Didelotcaac8542016-06-20 13:14:09 -04005713 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04005714 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005715
Vivien Didelotfad09c72016-06-21 12:28:20 -04005716 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5717 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005718
5719 return 0;
5720}
5721
Vivien Didelotfad09c72016-06-21 12:28:20 -04005722static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04005723{
Vivien Didelotfad09c72016-06-21 12:28:20 -04005724 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005725
Vivien Didelotfad09c72016-06-21 12:28:20 -04005726 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5727 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04005728 return NULL;
5729
Vivien Didelotfad09c72016-06-21 12:28:20 -04005730 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04005731
Vivien Didelotfad09c72016-06-21 12:28:20 -04005732 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01005733 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelotda7dc872019-09-07 16:00:49 -04005734 idr_init(&chip->policies);
Vivien Didelot469d7292016-06-20 13:14:06 -04005735
Vivien Didelotfad09c72016-06-21 12:28:20 -04005736 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005737}
5738
Florian Fainelli5ed4e3e2017-11-10 15:22:52 -08005739static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
Florian Fainelli4d776482020-01-07 21:06:05 -08005740 int port,
5741 enum dsa_tag_protocol m)
Andrew Lunn7b314362016-08-22 16:01:01 +02005742{
Vivien Didelot04bed142016-08-31 18:06:13 -04005743 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02005744
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005745 return chip->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02005746}
5747
Tobias Waldekranz9a99bef2021-04-20 20:53:08 +02005748static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5749 enum dsa_tag_protocol proto)
5750{
5751 struct mv88e6xxx_chip *chip = ds->priv;
5752 enum dsa_tag_protocol old_protocol;
5753 int err;
5754
5755 switch (proto) {
5756 case DSA_TAG_PROTO_EDSA:
5757 switch (chip->info->edsa_support) {
5758 case MV88E6XXX_EDSA_UNSUPPORTED:
5759 return -EPROTONOSUPPORT;
5760 case MV88E6XXX_EDSA_UNDOCUMENTED:
5761 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5762 fallthrough;
5763 case MV88E6XXX_EDSA_SUPPORTED:
5764 break;
5765 }
5766 break;
5767 case DSA_TAG_PROTO_DSA:
5768 break;
5769 default:
5770 return -EPROTONOSUPPORT;
5771 }
5772
5773 old_protocol = chip->tag_protocol;
5774 chip->tag_protocol = proto;
5775
5776 mv88e6xxx_reg_lock(chip);
5777 err = mv88e6xxx_setup_port_mode(chip, port);
5778 mv88e6xxx_reg_unlock(chip);
5779
5780 if (err)
5781 chip->tag_protocol = old_protocol;
5782
5783 return err;
5784}
5785
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005786static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5787 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005788{
Vivien Didelot04bed142016-08-31 18:06:13 -04005789 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005790 int err;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005791
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005792 mv88e6xxx_reg_lock(chip);
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005793 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5794 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005795 mv88e6xxx_reg_unlock(chip);
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005796
5797 return err;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005798}
5799
5800static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5801 const struct switchdev_obj_port_mdb *mdb)
5802{
Vivien Didelot04bed142016-08-31 18:06:13 -04005803 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005804 int err;
5805
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005806 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04005807 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005808 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005809
5810 return err;
5811}
5812
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005813static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5814 struct dsa_mall_mirror_tc_entry *mirror,
5815 bool ingress)
5816{
5817 enum mv88e6xxx_egress_direction direction = ingress ?
5818 MV88E6XXX_EGRESS_DIR_INGRESS :
5819 MV88E6XXX_EGRESS_DIR_EGRESS;
5820 struct mv88e6xxx_chip *chip = ds->priv;
5821 bool other_mirrors = false;
5822 int i;
5823 int err;
5824
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005825 mutex_lock(&chip->reg_lock);
5826 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5827 mirror->to_local_port) {
5828 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5829 other_mirrors |= ingress ?
5830 chip->ports[i].mirror_ingress :
5831 chip->ports[i].mirror_egress;
5832
5833 /* Can't change egress port when other mirror is active */
5834 if (other_mirrors) {
5835 err = -EBUSY;
5836 goto out;
5837 }
5838
Marek Behún2fda45f2021-03-17 14:46:41 +01005839 err = mv88e6xxx_set_egress_port(chip, direction,
5840 mirror->to_local_port);
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005841 if (err)
5842 goto out;
5843 }
5844
5845 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5846out:
5847 mutex_unlock(&chip->reg_lock);
5848
5849 return err;
5850}
5851
5852static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5853 struct dsa_mall_mirror_tc_entry *mirror)
5854{
5855 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5856 MV88E6XXX_EGRESS_DIR_INGRESS :
5857 MV88E6XXX_EGRESS_DIR_EGRESS;
5858 struct mv88e6xxx_chip *chip = ds->priv;
5859 bool other_mirrors = false;
5860 int i;
5861
5862 mutex_lock(&chip->reg_lock);
5863 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5864 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5865
5866 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5867 other_mirrors |= mirror->ingress ?
5868 chip->ports[i].mirror_ingress :
5869 chip->ports[i].mirror_egress;
5870
5871 /* Reset egress port when no other mirror is active */
5872 if (!other_mirrors) {
Marek Behún2fda45f2021-03-17 14:46:41 +01005873 if (mv88e6xxx_set_egress_port(chip, direction,
5874 dsa_upstream_port(ds, port)))
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005875 dev_err(ds->dev, "failed to set egress port\n");
5876 }
5877
5878 mutex_unlock(&chip->reg_lock);
5879}
5880
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005881static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5882 struct switchdev_brport_flags flags,
5883 struct netlink_ext_ack *extack)
5884{
5885 struct mv88e6xxx_chip *chip = ds->priv;
5886 const struct mv88e6xxx_ops *ops;
5887
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01005888 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5889 BR_BCAST_FLOOD))
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005890 return -EINVAL;
5891
5892 ops = chip->info->ops;
5893
5894 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5895 return -EINVAL;
5896
5897 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5898 return -EINVAL;
5899
5900 return 0;
5901}
5902
5903static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5904 struct switchdev_brport_flags flags,
5905 struct netlink_ext_ack *extack)
Russell King4f859012019-02-20 15:35:05 -08005906{
5907 struct mv88e6xxx_chip *chip = ds->priv;
5908 int err = -EOPNOTSUPP;
5909
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005910 mv88e6xxx_reg_lock(chip);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005911
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005912 if (flags.mask & BR_LEARNING) {
5913 bool learning = !!(flags.val & BR_LEARNING);
5914 u16 pav = learning ? (1 << port) : 0;
5915
5916 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5917 if (err)
5918 goto out;
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005919 }
5920
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005921 if (flags.mask & BR_FLOOD) {
5922 bool unicast = !!(flags.val & BR_FLOOD);
5923
5924 err = chip->info->ops->port_set_ucast_flood(chip, port,
5925 unicast);
5926 if (err)
5927 goto out;
5928 }
5929
5930 if (flags.mask & BR_MCAST_FLOOD) {
5931 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5932
5933 err = chip->info->ops->port_set_mcast_flood(chip, port,
5934 multicast);
5935 if (err)
5936 goto out;
5937 }
5938
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01005939 if (flags.mask & BR_BCAST_FLOOD) {
5940 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5941
5942 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5943 if (err)
5944 goto out;
5945 }
5946
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005947out:
5948 mv88e6xxx_reg_unlock(chip);
5949
5950 return err;
5951}
5952
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005953static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5954 struct net_device *lag,
5955 struct netdev_lag_upper_info *info)
5956{
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01005957 struct mv88e6xxx_chip *chip = ds->priv;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005958 struct dsa_port *dp;
5959 int id, members = 0;
5960
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01005961 if (!mv88e6xxx_has_lag(chip))
5962 return false;
5963
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005964 id = dsa_lag_id(ds->dst, lag);
5965 if (id < 0 || id >= ds->num_lag_ids)
5966 return false;
5967
5968 dsa_lag_foreach_port(dp, ds->dst, lag)
5969 /* Includes the port joining the LAG */
5970 members++;
5971
5972 if (members > 8)
5973 return false;
5974
5975 /* We could potentially relax this to include active
5976 * backup in the future.
5977 */
5978 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5979 return false;
5980
5981 /* Ideally we would also validate that the hash type matches
5982 * the hardware. Alas, this is always set to unknown on team
5983 * interfaces.
5984 */
5985 return true;
5986}
5987
5988static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5989{
5990 struct mv88e6xxx_chip *chip = ds->priv;
5991 struct dsa_port *dp;
5992 u16 map = 0;
5993 int id;
5994
5995 id = dsa_lag_id(ds->dst, lag);
5996
5997 /* Build the map of all ports to distribute flows destined for
5998 * this LAG. This can be either a local user port, or a DSA
5999 * port if the LAG port is on a remote chip.
6000 */
6001 dsa_lag_foreach_port(dp, ds->dst, lag)
6002 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6003
6004 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6005}
6006
6007static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6008 /* Row number corresponds to the number of active members in a
6009 * LAG. Each column states which of the eight hash buckets are
6010 * mapped to the column:th port in the LAG.
6011 *
6012 * Example: In a LAG with three active ports, the second port
6013 * ([2][1]) would be selected for traffic mapped to buckets
6014 * 3,4,5 (0x38).
6015 */
6016 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6017 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6018 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6019 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6020 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6021 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6022 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6023 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6024};
6025
6026static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6027 int num_tx, int nth)
6028{
6029 u8 active = 0;
6030 int i;
6031
6032 num_tx = num_tx <= 8 ? num_tx : 8;
6033 if (nth < num_tx)
6034 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6035
6036 for (i = 0; i < 8; i++) {
6037 if (BIT(i) & active)
6038 mask[i] |= BIT(port);
6039 }
6040}
6041
6042static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6043{
6044 struct mv88e6xxx_chip *chip = ds->priv;
6045 unsigned int id, num_tx;
6046 struct net_device *lag;
6047 struct dsa_port *dp;
6048 int i, err, nth;
6049 u16 mask[8];
6050 u16 ivec;
6051
6052 /* Assume no port is a member of any LAG. */
6053 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6054
6055 /* Disable all masks for ports that _are_ members of a LAG. */
6056 list_for_each_entry(dp, &ds->dst->ports, list) {
6057 if (!dp->lag_dev || dp->ds != ds)
6058 continue;
6059
6060 ivec &= ~BIT(dp->index);
6061 }
6062
6063 for (i = 0; i < 8; i++)
6064 mask[i] = ivec;
6065
6066 /* Enable the correct subset of masks for all LAG ports that
6067 * are in the Tx set.
6068 */
6069 dsa_lags_foreach_id(id, ds->dst) {
6070 lag = dsa_lag_dev(ds->dst, id);
6071 if (!lag)
6072 continue;
6073
6074 num_tx = 0;
6075 dsa_lag_foreach_port(dp, ds->dst, lag) {
6076 if (dp->lag_tx_enabled)
6077 num_tx++;
6078 }
6079
6080 if (!num_tx)
6081 continue;
6082
6083 nth = 0;
6084 dsa_lag_foreach_port(dp, ds->dst, lag) {
6085 if (!dp->lag_tx_enabled)
6086 continue;
6087
6088 if (dp->ds == ds)
6089 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6090 num_tx, nth);
6091
6092 nth++;
6093 }
6094 }
6095
6096 for (i = 0; i < 8; i++) {
6097 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6098 if (err)
6099 return err;
6100 }
6101
6102 return 0;
6103}
6104
6105static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6106 struct net_device *lag)
6107{
6108 int err;
6109
6110 err = mv88e6xxx_lag_sync_masks(ds);
6111
6112 if (!err)
6113 err = mv88e6xxx_lag_sync_map(ds, lag);
6114
6115 return err;
6116}
6117
6118static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6119{
6120 struct mv88e6xxx_chip *chip = ds->priv;
6121 int err;
6122
6123 mv88e6xxx_reg_lock(chip);
6124 err = mv88e6xxx_lag_sync_masks(ds);
6125 mv88e6xxx_reg_unlock(chip);
6126 return err;
6127}
6128
6129static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6130 struct net_device *lag,
6131 struct netdev_lag_upper_info *info)
6132{
6133 struct mv88e6xxx_chip *chip = ds->priv;
6134 int err, id;
6135
6136 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6137 return -EOPNOTSUPP;
6138
6139 id = dsa_lag_id(ds->dst, lag);
6140
6141 mv88e6xxx_reg_lock(chip);
6142
6143 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6144 if (err)
6145 goto err_unlock;
6146
6147 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6148 if (err)
6149 goto err_clear_trunk;
6150
6151 mv88e6xxx_reg_unlock(chip);
6152 return 0;
6153
6154err_clear_trunk:
6155 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6156err_unlock:
6157 mv88e6xxx_reg_unlock(chip);
6158 return err;
6159}
6160
6161static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6162 struct net_device *lag)
6163{
6164 struct mv88e6xxx_chip *chip = ds->priv;
6165 int err_sync, err_trunk;
6166
6167 mv88e6xxx_reg_lock(chip);
6168 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6169 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6170 mv88e6xxx_reg_unlock(chip);
6171 return err_sync ? : err_trunk;
6172}
6173
6174static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6175 int port)
6176{
6177 struct mv88e6xxx_chip *chip = ds->priv;
6178 int err;
6179
6180 mv88e6xxx_reg_lock(chip);
6181 err = mv88e6xxx_lag_sync_masks(ds);
6182 mv88e6xxx_reg_unlock(chip);
6183 return err;
6184}
6185
6186static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6187 int port, struct net_device *lag,
6188 struct netdev_lag_upper_info *info)
6189{
6190 struct mv88e6xxx_chip *chip = ds->priv;
6191 int err;
6192
6193 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6194 return -EOPNOTSUPP;
6195
6196 mv88e6xxx_reg_lock(chip);
6197
6198 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6199 if (err)
6200 goto unlock;
6201
6202 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6203
6204unlock:
6205 mv88e6xxx_reg_unlock(chip);
6206 return err;
6207}
6208
6209static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6210 int port, struct net_device *lag)
6211{
6212 struct mv88e6xxx_chip *chip = ds->priv;
6213 int err_sync, err_pvt;
6214
6215 mv88e6xxx_reg_lock(chip);
6216 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6217 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6218 mv88e6xxx_reg_unlock(chip);
6219 return err_sync ? : err_pvt;
6220}
6221
Florian Fainellia82f67a2017-01-08 14:52:08 -08006222static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunn7b314362016-08-22 16:01:01 +02006223 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Tobias Waldekranz9a99bef2021-04-20 20:53:08 +02006224 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006225 .setup = mv88e6xxx_setup,
Andrew Lunn23e8b472019-10-25 01:03:52 +02006226 .teardown = mv88e6xxx_teardown,
Vladimir Olteanfd292c12021-09-17 17:29:16 +03006227 .port_setup = mv88e6xxx_port_setup,
6228 .port_teardown = mv88e6xxx_port_teardown,
Russell Kingc9a23562018-05-10 13:17:35 -07006229 .phylink_validate = mv88e6xxx_validate,
Russell Kinga5a68582020-03-14 10:15:43 +00006230 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
Russell Kingc9a23562018-05-10 13:17:35 -07006231 .phylink_mac_config = mv88e6xxx_mac_config,
Russell Kinga5a68582020-03-14 10:15:43 +00006232 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
Russell Kingc9a23562018-05-10 13:17:35 -07006233 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6234 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006235 .get_strings = mv88e6xxx_get_strings,
6236 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6237 .get_sset_count = mv88e6xxx_get_sset_count,
Andrew Lunn04aca992017-05-26 01:03:24 +02006238 .port_enable = mv88e6xxx_port_enable,
6239 .port_disable = mv88e6xxx_port_disable,
Andrew Lunn2a550ae2020-07-11 22:32:05 +02006240 .port_max_mtu = mv88e6xxx_get_max_mtu,
6241 .port_change_mtu = mv88e6xxx_change_mtu,
Vivien Didelot08f50062017-08-01 16:32:41 -04006242 .get_mac_eee = mv88e6xxx_get_mac_eee,
6243 .set_mac_eee = mv88e6xxx_set_mac_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006244 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006245 .get_eeprom = mv88e6xxx_get_eeprom,
6246 .set_eeprom = mv88e6xxx_set_eeprom,
6247 .get_regs_len = mv88e6xxx_get_regs_len,
6248 .get_regs = mv88e6xxx_get_regs,
Vivien Didelotda7dc872019-09-07 16:00:49 -04006249 .get_rxnfc = mv88e6xxx_get_rxnfc,
6250 .set_rxnfc = mv88e6xxx_set_rxnfc,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04006251 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006252 .port_bridge_join = mv88e6xxx_port_bridge_join,
6253 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02006254 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6255 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006256 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04006257 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006258 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006259 .port_vlan_add = mv88e6xxx_port_vlan_add,
6260 .port_vlan_del = mv88e6xxx_port_vlan_del,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006261 .port_fdb_add = mv88e6xxx_port_fdb_add,
6262 .port_fdb_del = mv88e6xxx_port_fdb_del,
6263 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04006264 .port_mdb_add = mv88e6xxx_port_mdb_add,
6265 .port_mdb_del = mv88e6xxx_port_mdb_del,
Iwan R Timmerf0942e02019-11-07 22:11:14 +01006266 .port_mirror_add = mv88e6xxx_port_mirror_add,
6267 .port_mirror_del = mv88e6xxx_port_mirror_del,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04006268 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6269 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006270 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6271 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6272 .port_txtstamp = mv88e6xxx_port_txtstamp,
6273 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6274 .get_ts_info = mv88e6xxx_get_ts_info,
Andrew Lunn23e8b472019-10-25 01:03:52 +02006275 .devlink_param_get = mv88e6xxx_devlink_param_get,
6276 .devlink_param_set = mv88e6xxx_devlink_param_set,
Andrew Lunn93157302020-09-18 21:11:09 +02006277 .devlink_info_get = mv88e6xxx_devlink_info_get,
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006278 .port_lag_change = mv88e6xxx_port_lag_change,
6279 .port_lag_join = mv88e6xxx_port_lag_join,
6280 .port_lag_leave = mv88e6xxx_port_lag_leave,
6281 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6282 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6283 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006284};
6285
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08006286static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006287{
Vivien Didelotfad09c72016-06-21 12:28:20 -04006288 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006289 struct dsa_switch *ds;
6290
Vivien Didelot7e99e342019-10-21 16:51:30 -04006291 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006292 if (!ds)
6293 return -ENOMEM;
6294
Vivien Didelot7e99e342019-10-21 16:51:30 -04006295 ds->dev = dev;
6296 ds->num_ports = mv88e6xxx_num_ports(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04006297 ds->priv = chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006298 ds->dev = dev;
Vivien Didelot9d490b42016-08-23 12:38:56 -04006299 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelot9ff74f22017-03-15 15:53:50 -04006300 ds->ageing_time_min = chip->info->age_time_coeff;
6301 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006302
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006303 /* Some chips support up to 32, but that requires enabling the
6304 * 5-bit port mode, which we do not support. 640k^W16 ought to
6305 * be enough for anyone.
6306 */
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01006307 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006308
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006309 dev_set_drvdata(dev, ds);
6310
Vivien Didelot23c9ee42017-05-26 18:12:51 -04006311 return dsa_register_switch(ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006312}
6313
Vivien Didelotfad09c72016-06-21 12:28:20 -04006314static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006315{
Vivien Didelotfad09c72016-06-21 12:28:20 -04006316 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006317}
6318
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006319static const void *pdata_device_get_match_data(struct device *dev)
6320{
6321 const struct of_device_id *matches = dev->driver->of_match_table;
6322 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6323
6324 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6325 matches++) {
6326 if (!strcmp(pdata->compatible, matches->compatible))
6327 return matches->data;
6328 }
6329 return NULL;
6330}
6331
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01006332/* There is no suspend to RAM support at DSA level yet, the switch configuration
6333 * would be lost after a power cycle so prevent it to be suspended.
6334 */
6335static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6336{
6337 return -EOPNOTSUPP;
6338}
6339
6340static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6341{
6342 return 0;
6343}
6344
6345static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6346
Vivien Didelot57d32312016-06-20 13:13:58 -04006347static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006348{
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006349 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
David S. Miller7ddae242018-05-20 19:04:24 -04006350 const struct mv88e6xxx_info *compat_info = NULL;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006351 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006352 struct device_node *np = dev->of_node;
Vivien Didelotfad09c72016-06-21 12:28:20 -04006353 struct mv88e6xxx_chip *chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006354 int port;
Andrew Lunn52638f72016-05-10 23:27:22 +02006355 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006356
Andrew Lunn7bb8c992018-05-31 00:15:42 +02006357 if (!np && !pdata)
6358 return -EINVAL;
6359
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006360 if (np)
6361 compat_info = of_device_get_match_data(dev);
6362
6363 if (pdata) {
6364 compat_info = pdata_device_get_match_data(dev);
6365
6366 if (!pdata->netdev)
6367 return -EINVAL;
6368
6369 for (port = 0; port < DSA_MAX_PORTS; port++) {
6370 if (!(pdata->enabled_ports & (1 << port)))
6371 continue;
6372 if (strcmp(pdata->cd.port_names[port], "cpu"))
6373 continue;
6374 pdata->cd.netdev[port] = &pdata->netdev->dev;
6375 break;
6376 }
6377 }
6378
Vivien Didelotcaac8542016-06-20 13:14:09 -04006379 if (!compat_info)
6380 return -EINVAL;
6381
Vivien Didelotfad09c72016-06-21 12:28:20 -04006382 chip = mv88e6xxx_alloc_chip(dev);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006383 if (!chip) {
6384 err = -ENOMEM;
6385 goto out;
6386 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006387
Vivien Didelotfad09c72016-06-21 12:28:20 -04006388 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04006389
Vivien Didelotfad09c72016-06-21 12:28:20 -04006390 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04006391 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006392 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006393
Andrew Lunnb4308f02016-11-21 23:26:55 +01006394 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006395 if (IS_ERR(chip->reset)) {
6396 err = PTR_ERR(chip->reset);
6397 goto out;
6398 }
Baruch Siach7b75e492019-06-27 21:17:39 +03006399 if (chip->reset)
6400 usleep_range(1000, 2000);
Andrew Lunnb4308f02016-11-21 23:26:55 +01006401
Vivien Didelotfad09c72016-06-21 12:28:20 -04006402 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04006403 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006404 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006405
Tobias Waldekranz670bb802021-04-20 20:53:07 +02006406 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6407 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6408 else
6409 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6410
Vivien Didelote57e5e72016-08-15 17:19:00 -04006411 mv88e6xxx_phy_init(chip);
6412
Andrew Lunn00baabe2018-05-19 22:31:35 +02006413 if (chip->info->ops->get_eeprom) {
6414 if (np)
6415 of_property_read_u32(np, "eeprom-length",
6416 &chip->eeprom_len);
6417 else
6418 chip->eeprom_len = pdata->eeprom_len;
6419 }
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006420
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006421 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006422 err = mv88e6xxx_switch_reset(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006423 mv88e6xxx_reg_unlock(chip);
Andrew Lunnb516d452016-06-04 21:17:06 +02006424 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02006425 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02006426
Andrew Lunna27415d2019-05-01 00:10:50 +02006427 if (np) {
6428 chip->irq = of_irq_get(np, 0);
6429 if (chip->irq == -EPROBE_DEFER) {
6430 err = chip->irq;
6431 goto out;
6432 }
Andrew Lunn83c0afa2016-06-04 21:17:07 +02006433 }
6434
Andrew Lunna27415d2019-05-01 00:10:50 +02006435 if (pdata)
6436 chip->irq = pdata->irq;
6437
Andrew Lunn294d7112018-02-22 22:58:32 +01006438 /* Has to be performed before the MDIO bus is created, because
Uwe Kleine-Königa7087672018-03-20 10:44:41 +01006439 * the PHYs will link their interrupts to these interrupt
Andrew Lunn294d7112018-02-22 22:58:32 +01006440 * controllers
6441 */
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006442 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006443 if (chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02006444 err = mv88e6xxx_g1_irq_setup(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006445 else
6446 err = mv88e6xxx_irq_poll_setup(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006447 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006448
Andrew Lunn294d7112018-02-22 22:58:32 +01006449 if (err)
6450 goto out;
6451
6452 if (chip->info->g2_irqs > 0) {
6453 err = mv88e6xxx_g2_irq_setup(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006454 if (err)
Andrew Lunn294d7112018-02-22 22:58:32 +01006455 goto out_g1_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02006456 }
6457
Andrew Lunn294d7112018-02-22 22:58:32 +01006458 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6459 if (err)
6460 goto out_g2_irq;
6461
6462 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6463 if (err)
6464 goto out_g1_atu_prob_irq;
6465
Andrew Lunna3c53be52017-01-24 14:53:50 +01006466 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02006467 if (err)
Andrew Lunn62eb1162018-01-14 02:32:45 +01006468 goto out_g1_vtu_prob_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02006469
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08006470 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006471 if (err)
6472 goto out_mdio;
6473
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006474 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02006475
6476out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01006477 mv88e6xxx_mdios_unregister(chip);
Andrew Lunn62eb1162018-01-14 02:32:45 +01006478out_g1_vtu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006479 mv88e6xxx_g1_vtu_prob_irq_free(chip);
Andrew Lunn09776442018-01-14 02:32:44 +01006480out_g1_atu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006481 mv88e6xxx_g1_atu_prob_irq_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006482out_g2_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006483 if (chip->info->g2_irqs > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02006484 mv88e6xxx_g2_irq_free(chip);
6485out_g1_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006486 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01006487 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006488 else
6489 mv88e6xxx_irq_poll_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006490out:
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006491 if (pdata)
6492 dev_put(pdata->netdev);
6493
Andrew Lunndc30c352016-10-16 19:56:49 +02006494 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006495}
6496
6497static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6498{
6499 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vladimir Oltean0650bf52021-09-17 16:34:33 +03006500 struct mv88e6xxx_chip *chip;
6501
6502 if (!ds)
6503 return;
6504
6505 chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006506
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006507 if (chip->info->ptp_support) {
6508 mv88e6xxx_hwtstamp_free(chip);
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01006509 mv88e6xxx_ptp_free(chip);
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006510 }
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01006511
Andrew Lunn930188c2016-08-22 16:01:03 +02006512 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04006513 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01006514 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006515
Andrew Lunn76f38f12018-03-17 20:21:09 +01006516 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6517 mv88e6xxx_g1_atu_prob_irq_free(chip);
6518
6519 if (chip->info->g2_irqs > 0)
6520 mv88e6xxx_g2_irq_free(chip);
6521
Andrew Lunn76f38f12018-03-17 20:21:09 +01006522 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01006523 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn76f38f12018-03-17 20:21:09 +01006524 else
6525 mv88e6xxx_irq_poll_free(chip);
Vladimir Oltean0650bf52021-09-17 16:34:33 +03006526
6527 dev_set_drvdata(&mdiodev->dev, NULL);
6528}
6529
6530static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
6531{
6532 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6533
6534 if (!ds)
6535 return;
6536
6537 dsa_switch_shutdown(ds);
6538
6539 dev_set_drvdata(&mdiodev->dev, NULL);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006540}
6541
6542static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04006543 {
6544 .compatible = "marvell,mv88e6085",
6545 .data = &mv88e6xxx_table[MV88E6085],
6546 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01006547 {
6548 .compatible = "marvell,mv88e6190",
6549 .data = &mv88e6xxx_table[MV88E6190],
6550 },
Rasmus Villemoes1f718362019-06-04 07:34:32 +00006551 {
6552 .compatible = "marvell,mv88e6250",
6553 .data = &mv88e6xxx_table[MV88E6250],
6554 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006555 { /* sentinel */ },
6556};
6557
6558MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6559
6560static struct mdio_driver mv88e6xxx_driver = {
6561 .probe = mv88e6xxx_probe,
6562 .remove = mv88e6xxx_remove,
Vladimir Oltean0650bf52021-09-17 16:34:33 +03006563 .shutdown = mv88e6xxx_shutdown,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006564 .mdiodrv.driver = {
6565 .name = "mv88e6085",
6566 .of_match_table = mv88e6xxx_of_match,
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01006567 .pm = &mv88e6xxx_pm_ops,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006568 },
6569};
6570
Andrew Lunn7324d502019-04-27 19:19:10 +02006571mdio_module_driver(mv88e6xxx_driver);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00006572
6573MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6574MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6575MODULE_LICENSE("GPL");