Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1 | /* |
Vivien Didelot | 0d3cd4b | 2016-06-21 12:28:19 -0400 | [diff] [blame] | 2 | * Marvell 88e6xxx Ethernet switch single-chip support |
| 3 | * |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 4 | * Copyright (c) 2008 Marvell Semiconductor |
| 5 | * |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 6 | * Copyright (c) 2015 CMC Electronics, Inc. |
| 7 | * Added support for VLAN Table Unit operations |
| 8 | * |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 9 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
| 10 | * |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | */ |
| 16 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 17 | #include <linux/delay.h> |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 18 | #include <linux/etherdevice.h> |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 19 | #include <linux/ethtool.h> |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 20 | #include <linux/if_bridge.h> |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 21 | #include <linux/jiffies.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 22 | #include <linux/list.h> |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 23 | #include <linux/mdio.h> |
Paul Gortmaker | 2bbba27 | 2012-01-24 10:41:40 +0000 | [diff] [blame] | 24 | #include <linux/module.h> |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 25 | #include <linux/of_device.h> |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 26 | #include <linux/of_mdio.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 27 | #include <linux/netdevice.h> |
Andrew Lunn | c8c1b39a | 2015-11-20 03:56:24 +0100 | [diff] [blame] | 28 | #include <linux/gpio/consumer.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 29 | #include <linux/phy.h> |
Ben Hutchings | c8f0b86 | 2011-11-27 17:06:08 +0000 | [diff] [blame] | 30 | #include <net/dsa.h> |
Vivien Didelot | 1f36faf | 2015-10-08 11:35:13 -0400 | [diff] [blame] | 31 | #include <net/switchdev.h> |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 32 | |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 33 | #include "mv88e6xxx.h" |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 34 | #include "global2.h" |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 35 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 36 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 37 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 38 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
| 39 | dev_err(chip->dev, "Switch registers lock not held!\n"); |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 40 | dump_stack(); |
| 41 | } |
| 42 | } |
| 43 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 44 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
| 45 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). |
| 46 | * |
| 47 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it |
| 48 | * is the only device connected to the SMI master. In this mode it responds to |
| 49 | * all 32 possible SMI addresses, and thus maps directly the internal devices. |
| 50 | * |
| 51 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing |
| 52 | * multiple devices to share the SMI interface. In this mode it responds to only |
| 53 | * 2 registers, used to indirectly access the internal SMI devices. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 54 | */ |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 55 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 56 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 57 | int addr, int reg, u16 *val) |
| 58 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 59 | if (!chip->smi_ops) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 60 | return -EOPNOTSUPP; |
| 61 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 62 | return chip->smi_ops->read(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 63 | } |
| 64 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 65 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 66 | int addr, int reg, u16 val) |
| 67 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 68 | if (!chip->smi_ops) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 69 | return -EOPNOTSUPP; |
| 70 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 71 | return chip->smi_ops->write(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 72 | } |
| 73 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 74 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 75 | int addr, int reg, u16 *val) |
| 76 | { |
| 77 | int ret; |
| 78 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 79 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 80 | if (ret < 0) |
| 81 | return ret; |
| 82 | |
| 83 | *val = ret & 0xffff; |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 88 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 89 | int addr, int reg, u16 val) |
| 90 | { |
| 91 | int ret; |
| 92 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 93 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 94 | if (ret < 0) |
| 95 | return ret; |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = { |
| 101 | .read = mv88e6xxx_smi_single_chip_read, |
| 102 | .write = mv88e6xxx_smi_single_chip_write, |
| 103 | }; |
| 104 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 105 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 106 | { |
| 107 | int ret; |
| 108 | int i; |
| 109 | |
| 110 | for (i = 0; i < 16; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 111 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 112 | if (ret < 0) |
| 113 | return ret; |
| 114 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 115 | if ((ret & SMI_CMD_BUSY) == 0) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | return -ETIMEDOUT; |
| 120 | } |
| 121 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 122 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 123 | int addr, int reg, u16 *val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 124 | { |
| 125 | int ret; |
| 126 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 127 | /* Wait for the bus to become free. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 128 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 129 | if (ret < 0) |
| 130 | return ret; |
| 131 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 132 | /* Transmit the read command. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 133 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
Neil Armstrong | 6e899e6 | 2015-10-22 10:37:53 +0200 | [diff] [blame] | 134 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 135 | if (ret < 0) |
| 136 | return ret; |
| 137 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 138 | /* Wait for the read command to complete. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 139 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 140 | if (ret < 0) |
| 141 | return ret; |
| 142 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 143 | /* Read the data. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 144 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 145 | if (ret < 0) |
| 146 | return ret; |
| 147 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 148 | *val = ret & 0xffff; |
| 149 | |
| 150 | return 0; |
| 151 | } |
| 152 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 153 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 154 | int addr, int reg, u16 val) |
| 155 | { |
| 156 | int ret; |
| 157 | |
| 158 | /* Wait for the bus to become free. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 159 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 160 | if (ret < 0) |
| 161 | return ret; |
| 162 | |
| 163 | /* Transmit the data to write. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 164 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 165 | if (ret < 0) |
| 166 | return ret; |
| 167 | |
| 168 | /* Transmit the write command. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 169 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 170 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
| 171 | if (ret < 0) |
| 172 | return ret; |
| 173 | |
| 174 | /* Wait for the write command to complete. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 175 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 176 | if (ret < 0) |
| 177 | return ret; |
| 178 | |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = { |
| 183 | .read = mv88e6xxx_smi_multi_chip_read, |
| 184 | .write = mv88e6xxx_smi_multi_chip_write, |
| 185 | }; |
| 186 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 187 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 188 | { |
| 189 | int err; |
| 190 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 191 | assert_reg_lock(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 192 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 193 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 194 | if (err) |
| 195 | return err; |
| 196 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 197 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 198 | addr, reg, *val); |
| 199 | |
| 200 | return 0; |
| 201 | } |
| 202 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 203 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 204 | { |
| 205 | int err; |
| 206 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 207 | assert_reg_lock(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 208 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 209 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 210 | if (err) |
| 211 | return err; |
| 212 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 213 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 214 | addr, reg, val); |
| 215 | |
| 216 | return 0; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 219 | int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, |
| 220 | u16 *val) |
| 221 | { |
| 222 | int addr = chip->info->port_base_addr + port; |
| 223 | |
| 224 | return mv88e6xxx_read(chip, addr, reg, val); |
| 225 | } |
| 226 | |
| 227 | int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, |
| 228 | u16 val) |
| 229 | { |
| 230 | int addr = chip->info->port_base_addr + port; |
| 231 | |
| 232 | return mv88e6xxx_write(chip, addr, reg, val); |
| 233 | } |
| 234 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 235 | static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, |
| 236 | int reg, u16 *val) |
| 237 | { |
| 238 | int addr = phy; /* PHY devices addresses start at 0x0 */ |
| 239 | |
| 240 | if (!chip->phy_ops) |
| 241 | return -EOPNOTSUPP; |
| 242 | |
| 243 | return chip->phy_ops->read(chip, addr, reg, val); |
| 244 | } |
| 245 | |
| 246 | static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, |
| 247 | int reg, u16 val) |
| 248 | { |
| 249 | int addr = phy; /* PHY devices addresses start at 0x0 */ |
| 250 | |
| 251 | if (!chip->phy_ops) |
| 252 | return -EOPNOTSUPP; |
| 253 | |
| 254 | return chip->phy_ops->write(chip, addr, reg, val); |
| 255 | } |
| 256 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 257 | static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) |
| 258 | { |
| 259 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) |
| 260 | return -EOPNOTSUPP; |
| 261 | |
| 262 | return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); |
| 263 | } |
| 264 | |
| 265 | static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) |
| 266 | { |
| 267 | int err; |
| 268 | |
| 269 | /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ |
| 270 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); |
| 271 | if (unlikely(err)) { |
| 272 | dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", |
| 273 | phy, err); |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, |
| 278 | u8 page, int reg, u16 *val) |
| 279 | { |
| 280 | int err; |
| 281 | |
| 282 | /* There is no paging for registers 22 */ |
| 283 | if (reg == PHY_PAGE) |
| 284 | return -EINVAL; |
| 285 | |
| 286 | err = mv88e6xxx_phy_page_get(chip, phy, page); |
| 287 | if (!err) { |
| 288 | err = mv88e6xxx_phy_read(chip, phy, reg, val); |
| 289 | mv88e6xxx_phy_page_put(chip, phy); |
| 290 | } |
| 291 | |
| 292 | return err; |
| 293 | } |
| 294 | |
| 295 | static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, |
| 296 | u8 page, int reg, u16 val) |
| 297 | { |
| 298 | int err; |
| 299 | |
| 300 | /* There is no paging for registers 22 */ |
| 301 | if (reg == PHY_PAGE) |
| 302 | return -EINVAL; |
| 303 | |
| 304 | err = mv88e6xxx_phy_page_get(chip, phy, page); |
| 305 | if (!err) { |
| 306 | err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); |
| 307 | mv88e6xxx_phy_page_put(chip, phy); |
| 308 | } |
| 309 | |
| 310 | return err; |
| 311 | } |
| 312 | |
| 313 | static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) |
| 314 | { |
| 315 | return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, |
| 316 | reg, val); |
| 317 | } |
| 318 | |
| 319 | static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) |
| 320 | { |
| 321 | return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, |
| 322 | reg, val); |
| 323 | } |
| 324 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 325 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) |
Vivien Didelot | 2d79af6 | 2016-08-15 17:18:57 -0400 | [diff] [blame] | 326 | { |
Andrew Lunn | 6441e669 | 2016-08-19 00:01:55 +0200 | [diff] [blame] | 327 | int i; |
Vivien Didelot | 2d79af6 | 2016-08-15 17:18:57 -0400 | [diff] [blame] | 328 | |
Andrew Lunn | 6441e669 | 2016-08-19 00:01:55 +0200 | [diff] [blame] | 329 | for (i = 0; i < 16; i++) { |
Vivien Didelot | 2d79af6 | 2016-08-15 17:18:57 -0400 | [diff] [blame] | 330 | u16 val; |
| 331 | int err; |
| 332 | |
| 333 | err = mv88e6xxx_read(chip, addr, reg, &val); |
| 334 | if (err) |
| 335 | return err; |
| 336 | |
| 337 | if (!(val & mask)) |
| 338 | return 0; |
| 339 | |
| 340 | usleep_range(1000, 2000); |
| 341 | } |
| 342 | |
Andrew Lunn | 3085355 | 2016-08-19 00:01:57 +0200 | [diff] [blame] | 343 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
Vivien Didelot | 2d79af6 | 2016-08-15 17:18:57 -0400 | [diff] [blame] | 344 | return -ETIMEDOUT; |
| 345 | } |
| 346 | |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 347 | /* Indirect write to single pointer-data register with an Update bit */ |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 348 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 349 | { |
| 350 | u16 val; |
Andrew Lunn | 0f02b4f | 2016-08-19 00:01:56 +0200 | [diff] [blame] | 351 | int err; |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 352 | |
| 353 | /* Wait until the previous operation is completed */ |
Andrew Lunn | 0f02b4f | 2016-08-19 00:01:56 +0200 | [diff] [blame] | 354 | err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); |
| 355 | if (err) |
| 356 | return err; |
Vivien Didelot | f22ab64 | 2016-07-18 20:45:31 -0400 | [diff] [blame] | 357 | |
| 358 | /* Set the Update bit to trigger a write operation */ |
| 359 | val = BIT(15) | update; |
| 360 | |
| 361 | return mv88e6xxx_write(chip, addr, reg, val); |
| 362 | } |
| 363 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 364 | static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 365 | { |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 366 | u16 val; |
| 367 | int err; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 368 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 369 | err = mv88e6xxx_read(chip, addr, reg, &val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 370 | if (err) |
| 371 | return err; |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 372 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 373 | return val; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 376 | static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 377 | int reg, u16 val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 378 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 379 | return mv88e6xxx_write(chip, addr, reg, val); |
Guenter Roeck | 8d6d09e | 2015-03-26 18:36:31 -0700 | [diff] [blame] | 380 | } |
| 381 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 382 | static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 383 | { |
| 384 | int ret; |
Andrew Lunn | 6441e669 | 2016-08-19 00:01:55 +0200 | [diff] [blame] | 385 | int i; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 386 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 387 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 388 | if (ret < 0) |
| 389 | return ret; |
| 390 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 391 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 392 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 393 | if (ret) |
| 394 | return ret; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 395 | |
Andrew Lunn | 6441e669 | 2016-08-19 00:01:55 +0200 | [diff] [blame] | 396 | for (i = 0; i < 16; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 397 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 398 | if (ret < 0) |
| 399 | return ret; |
| 400 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 401 | usleep_range(1000, 2000); |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 402 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
| 403 | GLOBAL_STATUS_PPU_POLLING) |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 404 | return 0; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | return -ETIMEDOUT; |
| 408 | } |
| 409 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 410 | static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 411 | { |
Andrew Lunn | 6441e669 | 2016-08-19 00:01:55 +0200 | [diff] [blame] | 412 | int ret, err, i; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 413 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 414 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 415 | if (ret < 0) |
| 416 | return ret; |
| 417 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 418 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 419 | ret | GLOBAL_CONTROL_PPU_ENABLE); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 420 | if (err) |
| 421 | return err; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 422 | |
Andrew Lunn | 6441e669 | 2016-08-19 00:01:55 +0200 | [diff] [blame] | 423 | for (i = 0; i < 16; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 424 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 425 | if (ret < 0) |
| 426 | return ret; |
| 427 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 428 | usleep_range(1000, 2000); |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 429 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
| 430 | GLOBAL_STATUS_PPU_POLLING) |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 431 | return 0; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | return -ETIMEDOUT; |
| 435 | } |
| 436 | |
| 437 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) |
| 438 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 439 | struct mv88e6xxx_chip *chip; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 440 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 441 | chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 442 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 443 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 444 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 445 | if (mutex_trylock(&chip->ppu_mutex)) { |
| 446 | if (mv88e6xxx_ppu_enable(chip) == 0) |
| 447 | chip->ppu_disabled = 0; |
| 448 | mutex_unlock(&chip->ppu_mutex); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 449 | } |
Vivien Didelot | 762eb67 | 2016-06-04 21:16:54 +0200 | [diff] [blame] | 450 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 451 | mutex_unlock(&chip->reg_lock); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 452 | } |
| 453 | |
| 454 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) |
| 455 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 456 | struct mv88e6xxx_chip *chip = (void *)_ps; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 457 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 458 | schedule_work(&chip->ppu_work); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 459 | } |
| 460 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 461 | static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 462 | { |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 463 | int ret; |
| 464 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 465 | mutex_lock(&chip->ppu_mutex); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 466 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 467 | /* If the PHY polling unit is enabled, disable it so that |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 468 | * we can access the PHY registers. If it was already |
| 469 | * disabled, cancel the timer that is going to re-enable |
| 470 | * it. |
| 471 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 472 | if (!chip->ppu_disabled) { |
| 473 | ret = mv88e6xxx_ppu_disable(chip); |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 474 | if (ret < 0) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 475 | mutex_unlock(&chip->ppu_mutex); |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 476 | return ret; |
| 477 | } |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 478 | chip->ppu_disabled = 1; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 479 | } else { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 480 | del_timer(&chip->ppu_timer); |
Barry Grussling | 8568658 | 2013-01-08 16:05:56 +0000 | [diff] [blame] | 481 | ret = 0; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | return ret; |
| 485 | } |
| 486 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 487 | static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 488 | { |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 489 | /* Schedule a timer to re-enable the PHY polling unit. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 490 | mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); |
| 491 | mutex_unlock(&chip->ppu_mutex); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 492 | } |
| 493 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 494 | static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 495 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 496 | mutex_init(&chip->ppu_mutex); |
| 497 | INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); |
| 498 | init_timer(&chip->ppu_timer); |
| 499 | chip->ppu_timer.data = (unsigned long)chip; |
| 500 | chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 501 | } |
| 502 | |
Andrew Lunn | 930188c | 2016-08-22 16:01:03 +0200 | [diff] [blame] | 503 | static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) |
| 504 | { |
| 505 | del_timer_sync(&chip->ppu_timer); |
| 506 | } |
| 507 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 508 | static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, |
| 509 | int reg, u16 *val) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 510 | { |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 511 | int err; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 512 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 513 | err = mv88e6xxx_ppu_access_get(chip); |
| 514 | if (!err) { |
| 515 | err = mv88e6xxx_read(chip, addr, reg, val); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 516 | mv88e6xxx_ppu_access_put(chip); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 517 | } |
| 518 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 519 | return err; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 520 | } |
| 521 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 522 | static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, |
| 523 | int reg, u16 val) |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 524 | { |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 525 | int err; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 526 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 527 | err = mv88e6xxx_ppu_access_get(chip); |
| 528 | if (!err) { |
| 529 | err = mv88e6xxx_write(chip, addr, reg, val); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 530 | mv88e6xxx_ppu_access_put(chip); |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 531 | } |
| 532 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 533 | return err; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 534 | } |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 535 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 536 | static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = { |
| 537 | .read = mv88e6xxx_phy_ppu_read, |
| 538 | .write = mv88e6xxx_phy_ppu_write, |
| 539 | }; |
| 540 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 541 | static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 542 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 543 | return chip->info->family == MV88E6XXX_FAMILY_6065; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 544 | } |
| 545 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 546 | static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 547 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 548 | return chip->info->family == MV88E6XXX_FAMILY_6095; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 549 | } |
| 550 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 551 | static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 552 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 553 | return chip->info->family == MV88E6XXX_FAMILY_6097; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 554 | } |
| 555 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 556 | static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 557 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 558 | return chip->info->family == MV88E6XXX_FAMILY_6165; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 559 | } |
| 560 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 561 | static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 562 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 563 | return chip->info->family == MV88E6XXX_FAMILY_6185; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 564 | } |
| 565 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 566 | static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) |
Aleksey S. Kazantsev | 7c3d0d6 | 2015-07-07 20:38:15 -0700 | [diff] [blame] | 567 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 568 | return chip->info->family == MV88E6XXX_FAMILY_6320; |
Aleksey S. Kazantsev | 7c3d0d6 | 2015-07-07 20:38:15 -0700 | [diff] [blame] | 569 | } |
| 570 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 571 | static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 572 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 573 | return chip->info->family == MV88E6XXX_FAMILY_6351; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 574 | } |
| 575 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 576 | static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) |
Andrew Lunn | f3a8b6b | 2015-04-02 04:06:40 +0200 | [diff] [blame] | 577 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 578 | return chip->info->family == MV88E6XXX_FAMILY_6352; |
Andrew Lunn | f3a8b6b | 2015-04-02 04:06:40 +0200 | [diff] [blame] | 579 | } |
| 580 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 581 | static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 582 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 583 | return chip->info->num_databases; |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 584 | } |
| 585 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 586 | static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip) |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 587 | { |
| 588 | /* Does the device have dedicated FID registers for ATU and VTU ops? */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 589 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
| 590 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 591 | return true; |
| 592 | |
| 593 | return false; |
| 594 | } |
| 595 | |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 596 | /* We expect the switch to perform auto negotiation if there is a real |
| 597 | * phy. However, in the case of a fixed link phy, we force the port |
| 598 | * settings from the fixed link settings. |
| 599 | */ |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 600 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
| 601 | struct phy_device *phydev) |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 602 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 603 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 604 | u16 reg; |
| 605 | int err; |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 606 | |
| 607 | if (!phy_is_pseudo_fixed_link(phydev)) |
| 608 | return; |
| 609 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 610 | mutex_lock(&chip->reg_lock); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 611 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 612 | err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); |
| 613 | if (err) |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 614 | goto out; |
| 615 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 616 | reg &= ~(PORT_PCS_CTRL_LINK_UP | |
| 617 | PORT_PCS_CTRL_FORCE_LINK | |
| 618 | PORT_PCS_CTRL_DUPLEX_FULL | |
| 619 | PORT_PCS_CTRL_FORCE_DUPLEX | |
| 620 | PORT_PCS_CTRL_UNFORCED); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 621 | |
| 622 | reg |= PORT_PCS_CTRL_FORCE_LINK; |
| 623 | if (phydev->link) |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 624 | reg |= PORT_PCS_CTRL_LINK_UP; |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 625 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 626 | if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100) |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 627 | goto out; |
| 628 | |
| 629 | switch (phydev->speed) { |
| 630 | case SPEED_1000: |
| 631 | reg |= PORT_PCS_CTRL_1000; |
| 632 | break; |
| 633 | case SPEED_100: |
| 634 | reg |= PORT_PCS_CTRL_100; |
| 635 | break; |
| 636 | case SPEED_10: |
| 637 | reg |= PORT_PCS_CTRL_10; |
| 638 | break; |
| 639 | default: |
| 640 | pr_info("Unknown speed"); |
| 641 | goto out; |
| 642 | } |
| 643 | |
| 644 | reg |= PORT_PCS_CTRL_FORCE_DUPLEX; |
| 645 | if (phydev->duplex == DUPLEX_FULL) |
| 646 | reg |= PORT_PCS_CTRL_DUPLEX_FULL; |
| 647 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 648 | if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) && |
| 649 | (port >= chip->info->num_ports - 2)) { |
Andrew Lunn | e7e72ac | 2015-08-31 15:56:51 +0200 | [diff] [blame] | 650 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
| 651 | reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; |
| 652 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
| 653 | reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; |
| 654 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
| 655 | reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | |
| 656 | PORT_PCS_CTRL_RGMII_DELAY_TXCLK); |
| 657 | } |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 658 | mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 659 | |
| 660 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 661 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 662 | } |
| 663 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 664 | static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 665 | { |
| 666 | int ret; |
| 667 | int i; |
| 668 | |
| 669 | for (i = 0; i < 10; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 670 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP); |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 671 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 672 | return 0; |
| 673 | } |
| 674 | |
| 675 | return -ETIMEDOUT; |
| 676 | } |
| 677 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 678 | static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 679 | { |
| 680 | int ret; |
| 681 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 682 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
Andrew Lunn | f3a8b6b | 2015-04-02 04:06:40 +0200 | [diff] [blame] | 683 | port = (port + 1) << 5; |
| 684 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 685 | /* Snapshot the hardware statistics counters for this port. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 686 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, |
Andrew Lunn | 3188823 | 2015-05-06 01:09:54 +0200 | [diff] [blame] | 687 | GLOBAL_STATS_OP_CAPTURE_PORT | |
| 688 | GLOBAL_STATS_OP_HIST_RX_TX | port); |
| 689 | if (ret < 0) |
| 690 | return ret; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 691 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 692 | /* Wait for the snapshotting to complete. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 693 | ret = _mv88e6xxx_stats_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 694 | if (ret < 0) |
| 695 | return ret; |
| 696 | |
| 697 | return 0; |
| 698 | } |
| 699 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 700 | static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 701 | int stat, u32 *val) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 702 | { |
| 703 | u32 _val; |
| 704 | int ret; |
| 705 | |
| 706 | *val = 0; |
| 707 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 708 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, |
Andrew Lunn | 3188823 | 2015-05-06 01:09:54 +0200 | [diff] [blame] | 709 | GLOBAL_STATS_OP_READ_CAPTURED | |
| 710 | GLOBAL_STATS_OP_HIST_RX_TX | stat); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 711 | if (ret < 0) |
| 712 | return; |
| 713 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 714 | ret = _mv88e6xxx_stats_wait(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 715 | if (ret < 0) |
| 716 | return; |
| 717 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 718 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 719 | if (ret < 0) |
| 720 | return; |
| 721 | |
| 722 | _val = ret << 16; |
| 723 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 724 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 725 | if (ret < 0) |
| 726 | return; |
| 727 | |
| 728 | *val = _val | ret; |
| 729 | } |
| 730 | |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 731 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 732 | { "in_good_octets", 8, 0x00, BANK0, }, |
| 733 | { "in_bad_octets", 4, 0x02, BANK0, }, |
| 734 | { "in_unicast", 4, 0x04, BANK0, }, |
| 735 | { "in_broadcasts", 4, 0x06, BANK0, }, |
| 736 | { "in_multicasts", 4, 0x07, BANK0, }, |
| 737 | { "in_pause", 4, 0x16, BANK0, }, |
| 738 | { "in_undersize", 4, 0x18, BANK0, }, |
| 739 | { "in_fragments", 4, 0x19, BANK0, }, |
| 740 | { "in_oversize", 4, 0x1a, BANK0, }, |
| 741 | { "in_jabber", 4, 0x1b, BANK0, }, |
| 742 | { "in_rx_error", 4, 0x1c, BANK0, }, |
| 743 | { "in_fcs_error", 4, 0x1d, BANK0, }, |
| 744 | { "out_octets", 8, 0x0e, BANK0, }, |
| 745 | { "out_unicast", 4, 0x10, BANK0, }, |
| 746 | { "out_broadcasts", 4, 0x13, BANK0, }, |
| 747 | { "out_multicasts", 4, 0x12, BANK0, }, |
| 748 | { "out_pause", 4, 0x15, BANK0, }, |
| 749 | { "excessive", 4, 0x11, BANK0, }, |
| 750 | { "collisions", 4, 0x1e, BANK0, }, |
| 751 | { "deferred", 4, 0x05, BANK0, }, |
| 752 | { "single", 4, 0x14, BANK0, }, |
| 753 | { "multiple", 4, 0x17, BANK0, }, |
| 754 | { "out_fcs_error", 4, 0x03, BANK0, }, |
| 755 | { "late", 4, 0x1f, BANK0, }, |
| 756 | { "hist_64bytes", 4, 0x08, BANK0, }, |
| 757 | { "hist_65_127bytes", 4, 0x09, BANK0, }, |
| 758 | { "hist_128_255bytes", 4, 0x0a, BANK0, }, |
| 759 | { "hist_256_511bytes", 4, 0x0b, BANK0, }, |
| 760 | { "hist_512_1023bytes", 4, 0x0c, BANK0, }, |
| 761 | { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, |
| 762 | { "sw_in_discards", 4, 0x10, PORT, }, |
| 763 | { "sw_in_filtered", 2, 0x12, PORT, }, |
| 764 | { "sw_out_filtered", 2, 0x13, PORT, }, |
| 765 | { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 766 | { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 767 | { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 768 | { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 769 | { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 770 | { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 771 | { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 772 | { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 773 | { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 774 | { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 775 | { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 776 | { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 777 | { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 778 | { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 779 | { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 780 | { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 781 | { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 782 | { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 783 | { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 784 | { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 785 | { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 786 | { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 787 | { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 788 | { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 789 | { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
| 790 | { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 791 | }; |
| 792 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 793 | static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip, |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 794 | struct mv88e6xxx_hw_stat *stat) |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 795 | { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 796 | switch (stat->type) { |
| 797 | case BANK0: |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 798 | return true; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 799 | case BANK1: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 800 | return mv88e6xxx_6320_family(chip); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 801 | case PORT: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 802 | return mv88e6xxx_6095_family(chip) || |
| 803 | mv88e6xxx_6185_family(chip) || |
| 804 | mv88e6xxx_6097_family(chip) || |
| 805 | mv88e6xxx_6165_family(chip) || |
| 806 | mv88e6xxx_6351_family(chip) || |
| 807 | mv88e6xxx_6352_family(chip); |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 808 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 809 | return false; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 810 | } |
| 811 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 812 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 813 | struct mv88e6xxx_hw_stat *s, |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 814 | int port) |
| 815 | { |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 816 | u32 low; |
| 817 | u32 high = 0; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 818 | int err; |
| 819 | u16 reg; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 820 | u64 value; |
| 821 | |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 822 | switch (s->type) { |
| 823 | case PORT: |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 824 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
| 825 | if (err) |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 826 | return UINT64_MAX; |
| 827 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 828 | low = reg; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 829 | if (s->sizeof_stat == 4) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 830 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
| 831 | if (err) |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 832 | return UINT64_MAX; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 833 | high = reg; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 834 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 835 | break; |
| 836 | case BANK0: |
| 837 | case BANK1: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 838 | _mv88e6xxx_stats_read(chip, s->reg, &low); |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 839 | if (s->sizeof_stat == 8) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 840 | _mv88e6xxx_stats_read(chip, s->reg + 1, &high); |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 841 | } |
| 842 | value = (((u64)high) << 16) | low; |
| 843 | return value; |
| 844 | } |
| 845 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 846 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
| 847 | uint8_t *data) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 848 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 849 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 850 | struct mv88e6xxx_hw_stat *stat; |
| 851 | int i, j; |
| 852 | |
| 853 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 854 | stat = &mv88e6xxx_hw_stats[i]; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 855 | if (mv88e6xxx_has_stat(chip, stat)) { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 856 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
| 857 | ETH_GSTRING_LEN); |
| 858 | j++; |
| 859 | } |
| 860 | } |
| 861 | } |
| 862 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 863 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 864 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 865 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 866 | struct mv88e6xxx_hw_stat *stat; |
| 867 | int i, j; |
| 868 | |
| 869 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 870 | stat = &mv88e6xxx_hw_stats[i]; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 871 | if (mv88e6xxx_has_stat(chip, stat)) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 872 | j++; |
| 873 | } |
| 874 | return j; |
| 875 | } |
| 876 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 877 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
| 878 | uint64_t *data) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 879 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 880 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 881 | struct mv88e6xxx_hw_stat *stat; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 882 | int ret; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 883 | int i, j; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 884 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 885 | mutex_lock(&chip->reg_lock); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 886 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 887 | ret = _mv88e6xxx_stats_snapshot(chip, port); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 888 | if (ret < 0) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 889 | mutex_unlock(&chip->reg_lock); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 890 | return; |
| 891 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 892 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 893 | stat = &mv88e6xxx_hw_stats[i]; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 894 | if (mv88e6xxx_has_stat(chip, stat)) { |
| 895 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port); |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 896 | j++; |
| 897 | } |
| 898 | } |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 899 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 900 | mutex_unlock(&chip->reg_lock); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 901 | } |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 902 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 903 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 904 | { |
| 905 | return 32 * sizeof(u16); |
| 906 | } |
| 907 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 908 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
| 909 | struct ethtool_regs *regs, void *_p) |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 910 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 911 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 912 | int err; |
| 913 | u16 reg; |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 914 | u16 *p = _p; |
| 915 | int i; |
| 916 | |
| 917 | regs->version = 0; |
| 918 | |
| 919 | memset(p, 0xff, 32 * sizeof(u16)); |
| 920 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 921 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 2306251 | 2016-05-09 13:22:45 -0400 | [diff] [blame] | 922 | |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 923 | for (i = 0; i < 32; i++) { |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 924 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 925 | err = mv88e6xxx_port_read(chip, port, i, ®); |
| 926 | if (!err) |
| 927 | p[i] = reg; |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 928 | } |
Vivien Didelot | 2306251 | 2016-05-09 13:22:45 -0400 | [diff] [blame] | 929 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 930 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 931 | } |
| 932 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 933 | static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 934 | { |
Vivien Didelot | 2d79af6 | 2016-08-15 17:18:57 -0400 | [diff] [blame] | 935 | return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP, |
| 936 | GLOBAL_ATU_OP_BUSY); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 937 | } |
| 938 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 939 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
| 940 | struct ethtool_eee *e) |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 941 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 942 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 943 | u16 reg; |
| 944 | int err; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 945 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 946 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
Vivien Didelot | aadbdb8 | 2016-05-09 13:22:44 -0400 | [diff] [blame] | 947 | return -EOPNOTSUPP; |
| 948 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 949 | mutex_lock(&chip->reg_lock); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 950 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 951 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
| 952 | if (err) |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 953 | goto out; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 954 | |
| 955 | e->eee_enabled = !!(reg & 0x0200); |
| 956 | e->tx_lpi_enabled = !!(reg & 0x0100); |
| 957 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 958 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 959 | if (err) |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 960 | goto out; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 961 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 962 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 963 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 964 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 965 | |
| 966 | return err; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 967 | } |
| 968 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 969 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
| 970 | struct phy_device *phydev, struct ethtool_eee *e) |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 971 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 972 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 973 | u16 reg; |
| 974 | int err; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 975 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 976 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) |
Vivien Didelot | aadbdb8 | 2016-05-09 13:22:44 -0400 | [diff] [blame] | 977 | return -EOPNOTSUPP; |
| 978 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 979 | mutex_lock(&chip->reg_lock); |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 980 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 981 | err = mv88e6xxx_phy_read(chip, port, 16, ®); |
| 982 | if (err) |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 983 | goto out; |
| 984 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 985 | reg &= ~0x0300; |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 986 | if (e->eee_enabled) |
| 987 | reg |= 0x0200; |
| 988 | if (e->tx_lpi_enabled) |
| 989 | reg |= 0x0100; |
| 990 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 991 | err = mv88e6xxx_phy_write(chip, port, 16, reg); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 992 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 993 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | 2f40c69 | 2015-04-02 04:06:37 +0200 | [diff] [blame] | 994 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 995 | return err; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 996 | } |
| 997 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 998 | static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 999 | { |
| 1000 | int ret; |
| 1001 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1002 | if (mv88e6xxx_has_fid_reg(chip)) { |
| 1003 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID, |
| 1004 | fid); |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 1005 | if (ret < 0) |
| 1006 | return ret; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1007 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1008 | /* ATU DBNum[7:4] are located in ATU Control 15:12 */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1009 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL); |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1010 | if (ret < 0) |
| 1011 | return ret; |
| 1012 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1013 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1014 | (ret & 0xfff) | |
| 1015 | ((fid << 8) & 0xf000)); |
| 1016 | if (ret < 0) |
| 1017 | return ret; |
| 1018 | |
| 1019 | /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ |
| 1020 | cmd |= fid & 0xf; |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 1021 | } |
| 1022 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1023 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1024 | if (ret < 0) |
| 1025 | return ret; |
| 1026 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1027 | return _mv88e6xxx_atu_wait(chip); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1028 | } |
| 1029 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1030 | static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 37705b7 | 2015-09-04 14:34:11 -0400 | [diff] [blame] | 1031 | struct mv88e6xxx_atu_entry *entry) |
| 1032 | { |
| 1033 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; |
| 1034 | |
| 1035 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
| 1036 | unsigned int mask, shift; |
| 1037 | |
| 1038 | if (entry->trunk) { |
| 1039 | data |= GLOBAL_ATU_DATA_TRUNK; |
| 1040 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; |
| 1041 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; |
| 1042 | } else { |
| 1043 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; |
| 1044 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; |
| 1045 | } |
| 1046 | |
| 1047 | data |= (entry->portv_trunkid << shift) & mask; |
| 1048 | } |
| 1049 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1050 | return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data); |
Vivien Didelot | 37705b7 | 2015-09-04 14:34:11 -0400 | [diff] [blame] | 1051 | } |
| 1052 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1053 | static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1054 | struct mv88e6xxx_atu_entry *entry, |
| 1055 | bool static_too) |
| 1056 | { |
| 1057 | int op; |
| 1058 | int err; |
| 1059 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1060 | err = _mv88e6xxx_atu_wait(chip); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1061 | if (err) |
| 1062 | return err; |
| 1063 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1064 | err = _mv88e6xxx_atu_data_write(chip, entry); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1065 | if (err) |
| 1066 | return err; |
| 1067 | |
| 1068 | if (entry->fid) { |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1069 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : |
| 1070 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; |
| 1071 | } else { |
| 1072 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : |
| 1073 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; |
| 1074 | } |
| 1075 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1076 | return _mv88e6xxx_atu_cmd(chip, entry->fid, op); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1077 | } |
| 1078 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1079 | static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1080 | u16 fid, bool static_too) |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1081 | { |
| 1082 | struct mv88e6xxx_atu_entry entry = { |
| 1083 | .fid = fid, |
| 1084 | .state = 0, /* EntryState bits must be 0 */ |
| 1085 | }; |
| 1086 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1087 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 1088 | } |
| 1089 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1090 | static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1091 | int from_port, int to_port, bool static_too) |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1092 | { |
| 1093 | struct mv88e6xxx_atu_entry entry = { |
| 1094 | .trunk = false, |
| 1095 | .fid = fid, |
| 1096 | }; |
| 1097 | |
| 1098 | /* EntryState bits must be 0xF */ |
| 1099 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; |
| 1100 | |
| 1101 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ |
| 1102 | entry.portv_trunkid = (to_port & 0x0f) << 4; |
| 1103 | entry.portv_trunkid |= from_port & 0x0f; |
| 1104 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1105 | return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1106 | } |
| 1107 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1108 | static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1109 | int port, bool static_too) |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1110 | { |
| 1111 | /* Destination port 0xF means remove the entries */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1112 | return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); |
Vivien Didelot | 9f4d55d | 2015-09-04 14:34:15 -0400 | [diff] [blame] | 1113 | } |
| 1114 | |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1115 | static const char * const mv88e6xxx_port_state_names[] = { |
| 1116 | [PORT_CONTROL_STATE_DISABLED] = "Disabled", |
| 1117 | [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", |
| 1118 | [PORT_CONTROL_STATE_LEARNING] = "Learning", |
| 1119 | [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", |
| 1120 | }; |
| 1121 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1122 | static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1123 | u8 state) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1124 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1125 | struct dsa_switch *ds = chip->ds; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1126 | u16 reg; |
| 1127 | int err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1128 | u8 oldstate; |
| 1129 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1130 | err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); |
| 1131 | if (err) |
| 1132 | return err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1133 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1134 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1135 | |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1136 | if (oldstate != state) { |
| 1137 | /* Flush forwarding database if we're moving a port |
| 1138 | * from Learning or Forwarding state to Disabled or |
| 1139 | * Blocking or Listening state. |
| 1140 | */ |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1141 | if ((oldstate == PORT_CONTROL_STATE_LEARNING || |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1142 | oldstate == PORT_CONTROL_STATE_FORWARDING) && |
| 1143 | (state == PORT_CONTROL_STATE_DISABLED || |
| 1144 | state == PORT_CONTROL_STATE_BLOCKING)) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1145 | err = _mv88e6xxx_atu_remove(chip, 0, port, false); |
| 1146 | if (err) |
| 1147 | return err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1148 | } |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1149 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1150 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1151 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); |
| 1152 | if (err) |
| 1153 | return err; |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1154 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1155 | netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n", |
Vivien Didelot | 2d9deae | 2016-03-07 18:24:17 -0500 | [diff] [blame] | 1156 | mv88e6xxx_port_state_names[state], |
| 1157 | mv88e6xxx_port_state_names[oldstate]); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1158 | } |
| 1159 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1160 | return err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1161 | } |
| 1162 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1163 | static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1164 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1165 | struct net_device *bridge = chip->ports[port].bridge_dev; |
| 1166 | const u16 mask = (1 << chip->info->num_ports) - 1; |
| 1167 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1168 | u16 output_ports = 0; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1169 | u16 reg; |
| 1170 | int err; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1171 | int i; |
| 1172 | |
| 1173 | /* allow CPU port or DSA link(s) to send frames to every port */ |
| 1174 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
| 1175 | output_ports = mask; |
| 1176 | } else { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1177 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1178 | /* allow sending frames to every group member */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1179 | if (bridge && chip->ports[i].bridge_dev == bridge) |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1180 | output_ports |= BIT(i); |
| 1181 | |
| 1182 | /* allow sending frames to CPU port and DSA link(s) */ |
| 1183 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
| 1184 | output_ports |= BIT(i); |
| 1185 | } |
| 1186 | } |
| 1187 | |
| 1188 | /* prevent frames from going back out of the port they came in on */ |
| 1189 | output_ports &= ~BIT(port); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1190 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1191 | err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); |
| 1192 | if (err) |
| 1193 | return err; |
Vivien Didelot | ede8098 | 2015-10-11 18:08:35 -0400 | [diff] [blame] | 1194 | |
| 1195 | reg &= ~mask; |
| 1196 | reg |= output_ports & mask; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1197 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1198 | return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1199 | } |
| 1200 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1201 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
| 1202 | u8 state) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1203 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1204 | struct mv88e6xxx_chip *chip = ds->priv; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1205 | int stp_state; |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1206 | int err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1207 | |
| 1208 | switch (state) { |
| 1209 | case BR_STATE_DISABLED: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1210 | stp_state = PORT_CONTROL_STATE_DISABLED; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1211 | break; |
| 1212 | case BR_STATE_BLOCKING: |
| 1213 | case BR_STATE_LISTENING: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1214 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1215 | break; |
| 1216 | case BR_STATE_LEARNING: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1217 | stp_state = PORT_CONTROL_STATE_LEARNING; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1218 | break; |
| 1219 | case BR_STATE_FORWARDING: |
| 1220 | default: |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 1221 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1222 | break; |
| 1223 | } |
| 1224 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1225 | mutex_lock(&chip->reg_lock); |
| 1226 | err = _mv88e6xxx_port_state(chip, port, stp_state); |
| 1227 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1228 | |
| 1229 | if (err) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1230 | netdev_err(ds->ports[port].netdev, |
| 1231 | "failed to update state to %s\n", |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1232 | mv88e6xxx_port_state_names[stp_state]); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1233 | } |
| 1234 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1235 | static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1236 | u16 *new, u16 *old) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1237 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1238 | struct dsa_switch *ds = chip->ds; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1239 | u16 pvid, reg; |
| 1240 | int err; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1241 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1242 | err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®); |
| 1243 | if (err) |
| 1244 | return err; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1245 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1246 | pvid = reg & PORT_DEFAULT_VLAN_MASK; |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1247 | |
| 1248 | if (new) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1249 | reg &= ~PORT_DEFAULT_VLAN_MASK; |
| 1250 | reg |= *new & PORT_DEFAULT_VLAN_MASK; |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1251 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1252 | err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg); |
| 1253 | if (err) |
| 1254 | return err; |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1255 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1256 | netdev_dbg(ds->ports[port].netdev, |
| 1257 | "DefaultVID %d (was %d)\n", *new, pvid); |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1258 | } |
| 1259 | |
| 1260 | if (old) |
| 1261 | *old = pvid; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1262 | |
| 1263 | return 0; |
| 1264 | } |
| 1265 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1266 | static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1267 | int port, u16 *pvid) |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1268 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1269 | return _mv88e6xxx_port_pvid(chip, port, NULL, pvid); |
Vivien Didelot | 5da9603 | 2016-03-07 18:24:39 -0500 | [diff] [blame] | 1270 | } |
| 1271 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1272 | static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1273 | int port, u16 pvid) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1274 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1275 | return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1276 | } |
| 1277 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1278 | static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1279 | { |
Vivien Didelot | 2d79af6 | 2016-08-15 17:18:57 -0400 | [diff] [blame] | 1280 | return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP, |
| 1281 | GLOBAL_VTU_OP_BUSY); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1282 | } |
| 1283 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1284 | static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1285 | { |
| 1286 | int ret; |
| 1287 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1288 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1289 | if (ret < 0) |
| 1290 | return ret; |
| 1291 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1292 | return _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1293 | } |
| 1294 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1295 | static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1296 | { |
| 1297 | int ret; |
| 1298 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1299 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1300 | if (ret < 0) |
| 1301 | return ret; |
| 1302 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1303 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 1304 | } |
| 1305 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1306 | static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1307 | struct mv88e6xxx_vtu_stu_entry *entry, |
| 1308 | unsigned int nibble_offset) |
| 1309 | { |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1310 | u16 regs[3]; |
| 1311 | int i; |
| 1312 | int ret; |
| 1313 | |
| 1314 | for (i = 0; i < 3; ++i) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1315 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1316 | GLOBAL_VTU_DATA_0_3 + i); |
| 1317 | if (ret < 0) |
| 1318 | return ret; |
| 1319 | |
| 1320 | regs[i] = ret; |
| 1321 | } |
| 1322 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1323 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1324 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
| 1325 | u16 reg = regs[i / 4]; |
| 1326 | |
| 1327 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; |
| 1328 | } |
| 1329 | |
| 1330 | return 0; |
| 1331 | } |
| 1332 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1333 | static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1334 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1335 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1336 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1337 | } |
| 1338 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1339 | static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1340 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1341 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1342 | return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1343 | } |
| 1344 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1345 | static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1346 | struct mv88e6xxx_vtu_stu_entry *entry, |
| 1347 | unsigned int nibble_offset) |
| 1348 | { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1349 | u16 regs[3] = { 0 }; |
| 1350 | int i; |
| 1351 | int ret; |
| 1352 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1353 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1354 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
| 1355 | u8 data = entry->data[i]; |
| 1356 | |
| 1357 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; |
| 1358 | } |
| 1359 | |
| 1360 | for (i = 0; i < 3; ++i) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1361 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1362 | GLOBAL_VTU_DATA_0_3 + i, regs[i]); |
| 1363 | if (ret < 0) |
| 1364 | return ret; |
| 1365 | } |
| 1366 | |
| 1367 | return 0; |
| 1368 | } |
| 1369 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1370 | static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1371 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1372 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1373 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1374 | } |
| 1375 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1376 | static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1377 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1378 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1379 | return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); |
Vivien Didelot | 15d7d7d | 2016-05-10 15:44:28 -0400 | [diff] [blame] | 1380 | } |
| 1381 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1382 | static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1383 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1384 | return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1385 | vid & GLOBAL_VTU_VID_MASK); |
| 1386 | } |
| 1387 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1388 | static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1389 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1390 | { |
| 1391 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; |
| 1392 | int ret; |
| 1393 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1394 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1395 | if (ret < 0) |
| 1396 | return ret; |
| 1397 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1398 | ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1399 | if (ret < 0) |
| 1400 | return ret; |
| 1401 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1402 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1403 | if (ret < 0) |
| 1404 | return ret; |
| 1405 | |
| 1406 | next.vid = ret & GLOBAL_VTU_VID_MASK; |
| 1407 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); |
| 1408 | |
| 1409 | if (next.valid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1410 | ret = mv88e6xxx_vtu_data_read(chip, &next); |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1411 | if (ret < 0) |
| 1412 | return ret; |
| 1413 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1414 | if (mv88e6xxx_has_fid_reg(chip)) { |
| 1415 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1416 | GLOBAL_VTU_FID); |
| 1417 | if (ret < 0) |
| 1418 | return ret; |
| 1419 | |
| 1420 | next.fid = ret & GLOBAL_VTU_FID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1421 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1422 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
| 1423 | * VTU DBNum[3:0] are located in VTU Operation 3:0 |
| 1424 | */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1425 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1426 | GLOBAL_VTU_OP); |
| 1427 | if (ret < 0) |
| 1428 | return ret; |
| 1429 | |
| 1430 | next.fid = (ret & 0xf00) >> 4; |
| 1431 | next.fid |= ret & 0xf; |
Vivien Didelot | 2e7bd5e | 2016-03-31 16:53:41 -0400 | [diff] [blame] | 1432 | } |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1433 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1434 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
| 1435 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 1436 | GLOBAL_VTU_SID); |
| 1437 | if (ret < 0) |
| 1438 | return ret; |
| 1439 | |
| 1440 | next.sid = ret & GLOBAL_VTU_SID_MASK; |
| 1441 | } |
| 1442 | } |
| 1443 | |
| 1444 | *entry = next; |
| 1445 | return 0; |
| 1446 | } |
| 1447 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1448 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
| 1449 | struct switchdev_obj_port_vlan *vlan, |
| 1450 | int (*cb)(struct switchdev_obj *obj)) |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1451 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1452 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1453 | struct mv88e6xxx_vtu_stu_entry next; |
| 1454 | u16 pvid; |
| 1455 | int err; |
| 1456 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1457 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1458 | return -EOPNOTSUPP; |
| 1459 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1460 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1461 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1462 | err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1463 | if (err) |
| 1464 | goto unlock; |
| 1465 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1466 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1467 | if (err) |
| 1468 | goto unlock; |
| 1469 | |
| 1470 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1471 | err = _mv88e6xxx_vtu_getnext(chip, &next); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1472 | if (err) |
| 1473 | break; |
| 1474 | |
| 1475 | if (!next.valid) |
| 1476 | break; |
| 1477 | |
| 1478 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
| 1479 | continue; |
| 1480 | |
| 1481 | /* reinit and dump this VLAN obj */ |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1482 | vlan->vid_begin = next.vid; |
| 1483 | vlan->vid_end = next.vid; |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1484 | vlan->flags = 0; |
| 1485 | |
| 1486 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) |
| 1487 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; |
| 1488 | |
| 1489 | if (next.vid == pvid) |
| 1490 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; |
| 1491 | |
| 1492 | err = cb(&vlan->obj); |
| 1493 | if (err) |
| 1494 | break; |
| 1495 | } while (next.vid < GLOBAL_VTU_VID_MASK); |
| 1496 | |
| 1497 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1498 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | ceff5ef | 2016-02-23 12:13:55 -0500 | [diff] [blame] | 1499 | |
| 1500 | return err; |
| 1501 | } |
| 1502 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1503 | static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1504 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1505 | { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1506 | u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1507 | u16 reg = 0; |
| 1508 | int ret; |
| 1509 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1510 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1511 | if (ret < 0) |
| 1512 | return ret; |
| 1513 | |
| 1514 | if (!entry->valid) |
| 1515 | goto loadpurge; |
| 1516 | |
| 1517 | /* Write port member tags */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1518 | ret = mv88e6xxx_vtu_data_write(chip, entry); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1519 | if (ret < 0) |
| 1520 | return ret; |
| 1521 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1522 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1523 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1524 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, |
| 1525 | reg); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1526 | if (ret < 0) |
| 1527 | return ret; |
Vivien Didelot | b426e5f | 2016-03-31 16:53:42 -0400 | [diff] [blame] | 1528 | } |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1529 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1530 | if (mv88e6xxx_has_fid_reg(chip)) { |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1531 | reg = entry->fid & GLOBAL_VTU_FID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1532 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID, |
| 1533 | reg); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1534 | if (ret < 0) |
| 1535 | return ret; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1536 | } else if (mv88e6xxx_num_databases(chip) == 256) { |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1537 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
| 1538 | * VTU DBNum[3:0] are located in VTU Operation 3:0 |
| 1539 | */ |
| 1540 | op |= (entry->fid & 0xf0) << 8; |
| 1541 | op |= entry->fid & 0xf; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1542 | } |
| 1543 | |
| 1544 | reg = GLOBAL_VTU_VID_VALID; |
| 1545 | loadpurge: |
| 1546 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1547 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1548 | if (ret < 0) |
| 1549 | return ret; |
| 1550 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1551 | return _mv88e6xxx_vtu_cmd(chip, op); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1552 | } |
| 1553 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1554 | static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1555 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1556 | { |
| 1557 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; |
| 1558 | int ret; |
| 1559 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1560 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1561 | if (ret < 0) |
| 1562 | return ret; |
| 1563 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1564 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1565 | sid & GLOBAL_VTU_SID_MASK); |
| 1566 | if (ret < 0) |
| 1567 | return ret; |
| 1568 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1569 | ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1570 | if (ret < 0) |
| 1571 | return ret; |
| 1572 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1573 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1574 | if (ret < 0) |
| 1575 | return ret; |
| 1576 | |
| 1577 | next.sid = ret & GLOBAL_VTU_SID_MASK; |
| 1578 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1579 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1580 | if (ret < 0) |
| 1581 | return ret; |
| 1582 | |
| 1583 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); |
| 1584 | |
| 1585 | if (next.valid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1586 | ret = mv88e6xxx_stu_data_read(chip, &next); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1587 | if (ret < 0) |
| 1588 | return ret; |
| 1589 | } |
| 1590 | |
| 1591 | *entry = next; |
| 1592 | return 0; |
| 1593 | } |
| 1594 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1595 | static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1596 | struct mv88e6xxx_vtu_stu_entry *entry) |
| 1597 | { |
| 1598 | u16 reg = 0; |
| 1599 | int ret; |
| 1600 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1601 | ret = _mv88e6xxx_vtu_wait(chip); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1602 | if (ret < 0) |
| 1603 | return ret; |
| 1604 | |
| 1605 | if (!entry->valid) |
| 1606 | goto loadpurge; |
| 1607 | |
| 1608 | /* Write port states */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1609 | ret = mv88e6xxx_stu_data_write(chip, entry); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1610 | if (ret < 0) |
| 1611 | return ret; |
| 1612 | |
| 1613 | reg = GLOBAL_VTU_VID_VALID; |
| 1614 | loadpurge: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1615 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1616 | if (ret < 0) |
| 1617 | return ret; |
| 1618 | |
| 1619 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1620 | ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1621 | if (ret < 0) |
| 1622 | return ret; |
| 1623 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1624 | return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1625 | } |
| 1626 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1627 | static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1628 | u16 *new, u16 *old) |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1629 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1630 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1631 | u16 upper_mask; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1632 | u16 fid; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1633 | u16 reg; |
| 1634 | int err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1635 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1636 | if (mv88e6xxx_num_databases(chip) == 4096) |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1637 | upper_mask = 0xff; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1638 | else if (mv88e6xxx_num_databases(chip) == 256) |
Vivien Didelot | 11ea809 | 2016-03-31 16:53:44 -0400 | [diff] [blame] | 1639 | upper_mask = 0xf; |
Vivien Didelot | f74df0b | 2016-03-31 16:53:43 -0400 | [diff] [blame] | 1640 | else |
| 1641 | return -EOPNOTSUPP; |
| 1642 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1643 | /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1644 | err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); |
| 1645 | if (err) |
| 1646 | return err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1647 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1648 | fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1649 | |
| 1650 | if (new) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1651 | reg &= ~PORT_BASE_VLAN_FID_3_0_MASK; |
| 1652 | reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1653 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1654 | err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg); |
| 1655 | if (err) |
| 1656 | return err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1657 | } |
| 1658 | |
| 1659 | /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1660 | err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®); |
| 1661 | if (err) |
| 1662 | return err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1663 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1664 | fid |= (reg & upper_mask) << 4; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1665 | |
| 1666 | if (new) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1667 | reg &= ~upper_mask; |
| 1668 | reg |= (*new >> 4) & upper_mask; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1669 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1670 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg); |
| 1671 | if (err) |
| 1672 | return err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1673 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1674 | netdev_dbg(ds->ports[port].netdev, |
| 1675 | "FID %d (was %d)\n", *new, fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1676 | } |
| 1677 | |
| 1678 | if (old) |
| 1679 | *old = fid; |
| 1680 | |
| 1681 | return 0; |
| 1682 | } |
| 1683 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1684 | static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1685 | int port, u16 *fid) |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1686 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1687 | return _mv88e6xxx_port_fid(chip, port, NULL, fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1688 | } |
| 1689 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1690 | static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1691 | int port, u16 fid) |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1692 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1693 | return _mv88e6xxx_port_fid(chip, port, &fid, NULL); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1694 | } |
| 1695 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1696 | static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1697 | { |
| 1698 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); |
| 1699 | struct mv88e6xxx_vtu_stu_entry vlan; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1700 | int i, err; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1701 | |
| 1702 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); |
| 1703 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1704 | /* Set every FID bit used by the (un)bridged ports */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1705 | for (i = 0; i < chip->info->num_ports; ++i) { |
| 1706 | err = _mv88e6xxx_port_fid_get(chip, i, fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1707 | if (err) |
| 1708 | return err; |
| 1709 | |
| 1710 | set_bit(*fid, fid_bitmap); |
| 1711 | } |
| 1712 | |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1713 | /* Set every FID bit used by the VLAN entries */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1714 | err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1715 | if (err) |
| 1716 | return err; |
| 1717 | |
| 1718 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1719 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1720 | if (err) |
| 1721 | return err; |
| 1722 | |
| 1723 | if (!vlan.valid) |
| 1724 | break; |
| 1725 | |
| 1726 | set_bit(vlan.fid, fid_bitmap); |
| 1727 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
| 1728 | |
| 1729 | /* The reset value 0x000 is used to indicate that multiple address |
| 1730 | * databases are not needed. Return the next positive available. |
| 1731 | */ |
| 1732 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1733 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1734 | return -ENOSPC; |
| 1735 | |
| 1736 | /* Clear the database */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1737 | return _mv88e6xxx_atu_flush(chip, *fid, true); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1738 | } |
| 1739 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1740 | static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1741 | struct mv88e6xxx_vtu_stu_entry *entry) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1742 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1743 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1744 | struct mv88e6xxx_vtu_stu_entry vlan = { |
| 1745 | .valid = true, |
| 1746 | .vid = vid, |
| 1747 | }; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1748 | int i, err; |
| 1749 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1750 | err = _mv88e6xxx_fid_new(chip, &vlan.fid); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1751 | if (err) |
| 1752 | return err; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1753 | |
Vivien Didelot | 3d131f0 | 2015-11-03 10:52:52 -0500 | [diff] [blame] | 1754 | /* exclude all ports except the CPU and DSA ports */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1755 | for (i = 0; i < chip->info->num_ports; ++i) |
Vivien Didelot | 3d131f0 | 2015-11-03 10:52:52 -0500 | [diff] [blame] | 1756 | vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) |
| 1757 | ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED |
| 1758 | : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1759 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1760 | if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || |
| 1761 | mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1762 | struct mv88e6xxx_vtu_stu_entry vstp; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1763 | |
| 1764 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not |
| 1765 | * implemented, only one STU entry is needed to cover all VTU |
| 1766 | * entries. Thus, validate the SID 0. |
| 1767 | */ |
| 1768 | vlan.sid = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1769 | err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1770 | if (err) |
| 1771 | return err; |
| 1772 | |
| 1773 | if (vstp.sid != vlan.sid || !vstp.valid) { |
| 1774 | memset(&vstp, 0, sizeof(vstp)); |
| 1775 | vstp.valid = true; |
| 1776 | vstp.sid = vlan.sid; |
| 1777 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1778 | err = _mv88e6xxx_stu_loadpurge(chip, &vstp); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1779 | if (err) |
| 1780 | return err; |
| 1781 | } |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1782 | } |
| 1783 | |
| 1784 | *entry = vlan; |
| 1785 | return 0; |
| 1786 | } |
| 1787 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1788 | static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1789 | struct mv88e6xxx_vtu_stu_entry *entry, bool creat) |
| 1790 | { |
| 1791 | int err; |
| 1792 | |
| 1793 | if (!vid) |
| 1794 | return -EINVAL; |
| 1795 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1796 | err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1797 | if (err) |
| 1798 | return err; |
| 1799 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1800 | err = _mv88e6xxx_vtu_getnext(chip, entry); |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1801 | if (err) |
| 1802 | return err; |
| 1803 | |
| 1804 | if (entry->vid != vid || !entry->valid) { |
| 1805 | if (!creat) |
| 1806 | return -EOPNOTSUPP; |
| 1807 | /* -ENOENT would've been more appropriate, but switchdev expects |
| 1808 | * -EOPNOTSUPP to inform bridge about an eventual software VLAN. |
| 1809 | */ |
| 1810 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1811 | err = _mv88e6xxx_vtu_new(chip, vid, entry); |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1812 | } |
| 1813 | |
| 1814 | return err; |
| 1815 | } |
| 1816 | |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1817 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
| 1818 | u16 vid_begin, u16 vid_end) |
| 1819 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1820 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1821 | struct mv88e6xxx_vtu_stu_entry vlan; |
| 1822 | int i, err; |
| 1823 | |
| 1824 | if (!vid_begin) |
| 1825 | return -EOPNOTSUPP; |
| 1826 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1827 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1828 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1829 | err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1830 | if (err) |
| 1831 | goto unlock; |
| 1832 | |
| 1833 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1834 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1835 | if (err) |
| 1836 | goto unlock; |
| 1837 | |
| 1838 | if (!vlan.valid) |
| 1839 | break; |
| 1840 | |
| 1841 | if (vlan.vid > vid_end) |
| 1842 | break; |
| 1843 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1844 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1845 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
| 1846 | continue; |
| 1847 | |
| 1848 | if (vlan.data[i] == |
| 1849 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
| 1850 | continue; |
| 1851 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1852 | if (chip->ports[i].bridge_dev == |
| 1853 | chip->ports[port].bridge_dev) |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1854 | break; /* same bridge, check next VLAN */ |
| 1855 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1856 | netdev_warn(ds->ports[port].netdev, |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1857 | "hardware VLAN %d already used by %s\n", |
| 1858 | vlan.vid, |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1859 | netdev_name(chip->ports[i].bridge_dev)); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1860 | err = -EOPNOTSUPP; |
| 1861 | goto unlock; |
| 1862 | } |
| 1863 | } while (vlan.vid < vid_end); |
| 1864 | |
| 1865 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1866 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1867 | |
| 1868 | return err; |
| 1869 | } |
| 1870 | |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1871 | static const char * const mv88e6xxx_port_8021q_mode_names[] = { |
| 1872 | [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", |
| 1873 | [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", |
| 1874 | [PORT_CONTROL_2_8021Q_CHECK] = "Check", |
| 1875 | [PORT_CONTROL_2_8021Q_SECURE] = "Secure", |
| 1876 | }; |
| 1877 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1878 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
| 1879 | bool vlan_filtering) |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1880 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1881 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1882 | u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : |
| 1883 | PORT_CONTROL_2_8021Q_DISABLED; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1884 | u16 reg; |
| 1885 | int err; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1886 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1887 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1888 | return -EOPNOTSUPP; |
| 1889 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1890 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1891 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1892 | err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®); |
| 1893 | if (err) |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1894 | goto unlock; |
| 1895 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1896 | old = reg & PORT_CONTROL_2_8021Q_MASK; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1897 | |
Vivien Didelot | 5220ef1 | 2016-03-07 18:24:52 -0500 | [diff] [blame] | 1898 | if (new != old) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1899 | reg &= ~PORT_CONTROL_2_8021Q_MASK; |
| 1900 | reg |= new & PORT_CONTROL_2_8021Q_MASK; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1901 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1902 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); |
| 1903 | if (err) |
Vivien Didelot | 5220ef1 | 2016-03-07 18:24:52 -0500 | [diff] [blame] | 1904 | goto unlock; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1905 | |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1906 | netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n", |
Vivien Didelot | 5220ef1 | 2016-03-07 18:24:52 -0500 | [diff] [blame] | 1907 | mv88e6xxx_port_8021q_mode_names[new], |
| 1908 | mv88e6xxx_port_8021q_mode_names[old]); |
| 1909 | } |
| 1910 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1911 | err = 0; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1912 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1913 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1914 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 1915 | return err; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1916 | } |
| 1917 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1918 | static int |
| 1919 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
| 1920 | const struct switchdev_obj_port_vlan *vlan, |
| 1921 | struct switchdev_trans *trans) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1922 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1923 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1924 | int err; |
| 1925 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1926 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1927 | return -EOPNOTSUPP; |
| 1928 | |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1929 | /* If the requested port doesn't belong to the same bridge as the VLAN |
| 1930 | * members, do not support it (yet) and fallback to software VLAN. |
| 1931 | */ |
| 1932 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, |
| 1933 | vlan->vid_end); |
| 1934 | if (err) |
| 1935 | return err; |
| 1936 | |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1937 | /* We don't need any dynamic resource from the kernel (yet), |
| 1938 | * so skip the prepare phase. |
| 1939 | */ |
| 1940 | return 0; |
| 1941 | } |
| 1942 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1943 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1944 | u16 vid, bool untagged) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1945 | { |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1946 | struct mv88e6xxx_vtu_stu_entry vlan; |
| 1947 | int err; |
| 1948 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1949 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1950 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1951 | return err; |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1952 | |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1953 | vlan.data[port] = untagged ? |
| 1954 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : |
| 1955 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; |
| 1956 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1957 | return _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1958 | } |
| 1959 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1960 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
| 1961 | const struct switchdev_obj_port_vlan *vlan, |
| 1962 | struct switchdev_trans *trans) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1963 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1964 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1965 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
| 1966 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; |
| 1967 | u16 vid; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1968 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1969 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1970 | return; |
| 1971 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1972 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1973 | |
Vivien Didelot | 4d5770b | 2016-04-06 11:55:05 -0400 | [diff] [blame] | 1974 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1975 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1976 | netdev_err(ds->ports[port].netdev, |
| 1977 | "failed to add VLAN %d%c\n", |
Vivien Didelot | 4d5770b | 2016-04-06 11:55:05 -0400 | [diff] [blame] | 1978 | vid, untagged ? 'u' : 't'); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1979 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1980 | if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 1981 | netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", |
Vivien Didelot | 4d5770b | 2016-04-06 11:55:05 -0400 | [diff] [blame] | 1982 | vlan->vid_end); |
| 1983 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1984 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1985 | } |
| 1986 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1987 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 1988 | int port, u16 vid) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1989 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1990 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1991 | struct mv88e6xxx_vtu_stu_entry vlan; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 1992 | int i, err; |
| 1993 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1994 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1995 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1996 | return err; |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 1997 | |
Vivien Didelot | 2fb5ef0 | 2016-02-26 13:16:01 -0500 | [diff] [blame] | 1998 | /* Tell switchdev if this VLAN is handled in software */ |
| 1999 | if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
Vivien Didelot | 3c06f08 | 2016-02-05 14:04:39 -0500 | [diff] [blame] | 2000 | return -EOPNOTSUPP; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2001 | |
| 2002 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
| 2003 | |
| 2004 | /* keep the VLAN unless all ports are excluded */ |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 2005 | vlan.valid = false; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2006 | for (i = 0; i < chip->info->num_ports; ++i) { |
Vivien Didelot | 3d131f0 | 2015-11-03 10:52:52 -0500 | [diff] [blame] | 2007 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2008 | continue; |
| 2009 | |
| 2010 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 2011 | vlan.valid = true; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2012 | break; |
| 2013 | } |
| 2014 | } |
| 2015 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2016 | err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2017 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2018 | return err; |
| 2019 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2020 | return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2021 | } |
| 2022 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2023 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
| 2024 | const struct switchdev_obj_port_vlan *vlan) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2025 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2026 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2027 | u16 pvid, vid; |
| 2028 | int err = 0; |
| 2029 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2030 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 2031 | return -EOPNOTSUPP; |
| 2032 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2033 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2034 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2035 | err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2036 | if (err) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2037 | goto unlock; |
| 2038 | |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2039 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2040 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2041 | if (err) |
| 2042 | goto unlock; |
| 2043 | |
| 2044 | if (vid == pvid) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2045 | err = _mv88e6xxx_port_pvid_set(chip, port, 0); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2046 | if (err) |
| 2047 | goto unlock; |
| 2048 | } |
| 2049 | } |
| 2050 | |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2051 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2052 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2053 | |
| 2054 | return err; |
| 2055 | } |
| 2056 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2057 | static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | c5723ac | 2015-08-10 09:09:48 -0400 | [diff] [blame] | 2058 | const unsigned char *addr) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2059 | { |
| 2060 | int i, ret; |
| 2061 | |
| 2062 | for (i = 0; i < 3; i++) { |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 2063 | ret = _mv88e6xxx_reg_write( |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2064 | chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 2065 | (addr[i * 2] << 8) | addr[i * 2 + 1]); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2066 | if (ret < 0) |
| 2067 | return ret; |
| 2068 | } |
| 2069 | |
| 2070 | return 0; |
| 2071 | } |
| 2072 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2073 | static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 2074 | unsigned char *addr) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2075 | { |
| 2076 | int i, ret; |
| 2077 | |
| 2078 | for (i = 0; i < 3; i++) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2079 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 2080 | GLOBAL_ATU_MAC_01 + i); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2081 | if (ret < 0) |
| 2082 | return ret; |
| 2083 | addr[i * 2] = ret >> 8; |
| 2084 | addr[i * 2 + 1] = ret & 0xff; |
| 2085 | } |
| 2086 | |
| 2087 | return 0; |
| 2088 | } |
| 2089 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2090 | static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2091 | struct mv88e6xxx_atu_entry *entry) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2092 | { |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2093 | int ret; |
| 2094 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2095 | ret = _mv88e6xxx_atu_wait(chip); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2096 | if (ret < 0) |
| 2097 | return ret; |
| 2098 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2099 | ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2100 | if (ret < 0) |
| 2101 | return ret; |
| 2102 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2103 | ret = _mv88e6xxx_atu_data_write(chip, entry); |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2104 | if (ret < 0) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2105 | return ret; |
| 2106 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2107 | return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2108 | } |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2109 | |
Vivien Didelot | 8847293 | 2016-09-19 19:56:11 -0400 | [diff] [blame] | 2110 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
| 2111 | struct mv88e6xxx_atu_entry *entry); |
| 2112 | |
| 2113 | static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, |
| 2114 | const u8 *addr, struct mv88e6xxx_atu_entry *entry) |
| 2115 | { |
| 2116 | struct mv88e6xxx_atu_entry next; |
| 2117 | int err; |
| 2118 | |
| 2119 | eth_broadcast_addr(next.mac); |
| 2120 | |
| 2121 | err = _mv88e6xxx_atu_mac_write(chip, next.mac); |
| 2122 | if (err) |
| 2123 | return err; |
| 2124 | |
| 2125 | do { |
| 2126 | err = _mv88e6xxx_atu_getnext(chip, fid, &next); |
| 2127 | if (err) |
| 2128 | return err; |
| 2129 | |
| 2130 | if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) |
| 2131 | break; |
| 2132 | |
| 2133 | if (ether_addr_equal(next.mac, addr)) { |
| 2134 | *entry = next; |
| 2135 | return 0; |
| 2136 | } |
| 2137 | } while (!is_broadcast_ether_addr(next.mac)); |
| 2138 | |
| 2139 | memset(entry, 0, sizeof(*entry)); |
| 2140 | entry->fid = fid; |
| 2141 | ether_addr_copy(entry->mac, addr); |
| 2142 | |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2146 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
| 2147 | const unsigned char *addr, u16 vid, |
| 2148 | u8 state) |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2149 | { |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 2150 | struct mv88e6xxx_vtu_stu_entry vlan; |
Vivien Didelot | 8847293 | 2016-09-19 19:56:11 -0400 | [diff] [blame] | 2151 | struct mv88e6xxx_atu_entry entry; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 2152 | int err; |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2153 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2154 | /* Null VLAN ID corresponds to the port private database */ |
| 2155 | if (vid == 0) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2156 | err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2157 | else |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2158 | err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 2159 | if (err) |
| 2160 | return err; |
| 2161 | |
Vivien Didelot | 8847293 | 2016-09-19 19:56:11 -0400 | [diff] [blame] | 2162 | err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); |
| 2163 | if (err) |
| 2164 | return err; |
| 2165 | |
| 2166 | /* Purge the ATU entry only if no port is using it anymore */ |
| 2167 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { |
| 2168 | entry.portv_trunkid &= ~BIT(port); |
| 2169 | if (!entry.portv_trunkid) |
| 2170 | entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; |
| 2171 | } else { |
| 2172 | entry.portv_trunkid |= BIT(port); |
| 2173 | entry.state = state; |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 2174 | } |
| 2175 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2176 | return _mv88e6xxx_atu_load(chip, &entry); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2177 | } |
| 2178 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2179 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
| 2180 | const struct switchdev_obj_port_fdb *fdb, |
| 2181 | struct switchdev_trans *trans) |
Vivien Didelot | 146a320 | 2015-10-08 11:35:12 -0400 | [diff] [blame] | 2182 | { |
| 2183 | /* We don't need any dynamic resource from the kernel (yet), |
| 2184 | * so skip the prepare phase. |
| 2185 | */ |
| 2186 | return 0; |
| 2187 | } |
| 2188 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2189 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
| 2190 | const struct switchdev_obj_port_fdb *fdb, |
| 2191 | struct switchdev_trans *trans) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2192 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2193 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 6630e23 | 2015-08-06 01:44:07 -0400 | [diff] [blame] | 2194 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2195 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2196 | if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
| 2197 | GLOBAL_ATU_DATA_STATE_UC_STATIC)) |
| 2198 | netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2199 | mutex_unlock(&chip->reg_lock); |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2200 | } |
| 2201 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2202 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
| 2203 | const struct switchdev_obj_port_fdb *fdb) |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2204 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2205 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2206 | int err; |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2207 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2208 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2209 | err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, |
| 2210 | GLOBAL_ATU_DATA_STATE_UNUSED); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2211 | mutex_unlock(&chip->reg_lock); |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2212 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2213 | return err; |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2214 | } |
| 2215 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2216 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2217 | struct mv88e6xxx_atu_entry *entry) |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2218 | { |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2219 | struct mv88e6xxx_atu_entry next = { 0 }; |
| 2220 | int ret; |
| 2221 | |
| 2222 | next.fid = fid; |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2223 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2224 | ret = _mv88e6xxx_atu_wait(chip); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2225 | if (ret < 0) |
| 2226 | return ret; |
| 2227 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2228 | ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2229 | if (ret < 0) |
| 2230 | return ret; |
| 2231 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2232 | ret = _mv88e6xxx_atu_mac_read(chip, next.mac); |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2233 | if (ret < 0) |
| 2234 | return ret; |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2235 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2236 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA); |
Vivien Didelot | 1d19404 | 2015-08-10 09:09:51 -0400 | [diff] [blame] | 2237 | if (ret < 0) |
| 2238 | return ret; |
| 2239 | |
| 2240 | next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
| 2241 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { |
| 2242 | unsigned int mask, shift; |
| 2243 | |
| 2244 | if (ret & GLOBAL_ATU_DATA_TRUNK) { |
| 2245 | next.trunk = true; |
| 2246 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; |
| 2247 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; |
| 2248 | } else { |
| 2249 | next.trunk = false; |
| 2250 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; |
| 2251 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; |
| 2252 | } |
| 2253 | |
| 2254 | next.portv_trunkid = (ret & mask) >> shift; |
| 2255 | } |
| 2256 | |
| 2257 | *entry = next; |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2258 | return 0; |
| 2259 | } |
| 2260 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2261 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
| 2262 | u16 fid, u16 vid, int port, |
| 2263 | struct switchdev_obj *obj, |
| 2264 | int (*cb)(struct switchdev_obj *obj)) |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2265 | { |
| 2266 | struct mv88e6xxx_atu_entry addr = { |
| 2267 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, |
| 2268 | }; |
| 2269 | int err; |
| 2270 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2271 | err = _mv88e6xxx_atu_mac_write(chip, addr.mac); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2272 | if (err) |
| 2273 | return err; |
| 2274 | |
| 2275 | do { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2276 | err = _mv88e6xxx_atu_getnext(chip, fid, &addr); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2277 | if (err) |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2278 | return err; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2279 | |
| 2280 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) |
| 2281 | break; |
| 2282 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2283 | if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) |
| 2284 | continue; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2285 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2286 | if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { |
| 2287 | struct switchdev_obj_port_fdb *fdb; |
| 2288 | |
| 2289 | if (!is_unicast_ether_addr(addr.mac)) |
| 2290 | continue; |
| 2291 | |
| 2292 | fdb = SWITCHDEV_OBJ_PORT_FDB(obj); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2293 | fdb->vid = vid; |
| 2294 | ether_addr_copy(fdb->addr, addr.mac); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2295 | if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) |
| 2296 | fdb->ndm_state = NUD_NOARP; |
| 2297 | else |
| 2298 | fdb->ndm_state = NUD_REACHABLE; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 2299 | } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { |
| 2300 | struct switchdev_obj_port_mdb *mdb; |
| 2301 | |
| 2302 | if (!is_multicast_ether_addr(addr.mac)) |
| 2303 | continue; |
| 2304 | |
| 2305 | mdb = SWITCHDEV_OBJ_PORT_MDB(obj); |
| 2306 | mdb->vid = vid; |
| 2307 | ether_addr_copy(mdb->addr, addr.mac); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2308 | } else { |
| 2309 | return -EOPNOTSUPP; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2310 | } |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2311 | |
| 2312 | err = cb(obj); |
| 2313 | if (err) |
| 2314 | return err; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2315 | } while (!is_broadcast_ether_addr(addr.mac)); |
| 2316 | |
| 2317 | return err; |
| 2318 | } |
| 2319 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2320 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
| 2321 | struct switchdev_obj *obj, |
| 2322 | int (*cb)(struct switchdev_obj *obj)) |
| 2323 | { |
| 2324 | struct mv88e6xxx_vtu_stu_entry vlan = { |
| 2325 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ |
| 2326 | }; |
| 2327 | u16 fid; |
| 2328 | int err; |
| 2329 | |
| 2330 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
| 2331 | err = _mv88e6xxx_port_fid_get(chip, port, &fid); |
| 2332 | if (err) |
| 2333 | return err; |
| 2334 | |
| 2335 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); |
| 2336 | if (err) |
| 2337 | return err; |
| 2338 | |
| 2339 | /* Dump VLANs' Filtering Information Databases */ |
| 2340 | err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); |
| 2341 | if (err) |
| 2342 | return err; |
| 2343 | |
| 2344 | do { |
| 2345 | err = _mv88e6xxx_vtu_getnext(chip, &vlan); |
| 2346 | if (err) |
| 2347 | return err; |
| 2348 | |
| 2349 | if (!vlan.valid) |
| 2350 | break; |
| 2351 | |
| 2352 | err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, |
| 2353 | obj, cb); |
| 2354 | if (err) |
| 2355 | return err; |
| 2356 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
| 2357 | |
| 2358 | return err; |
| 2359 | } |
| 2360 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2361 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
| 2362 | struct switchdev_obj_port_fdb *fdb, |
| 2363 | int (*cb)(struct switchdev_obj *obj)) |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2364 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2365 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2366 | int err; |
| 2367 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2368 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2369 | err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2370 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2371 | |
| 2372 | return err; |
| 2373 | } |
| 2374 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2375 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
| 2376 | struct net_device *bridge) |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2377 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2378 | struct mv88e6xxx_chip *chip = ds->priv; |
Colin Ian King | 1d9619d | 2016-04-25 23:11:22 +0100 | [diff] [blame] | 2379 | int i, err = 0; |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2380 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2381 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2382 | |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2383 | /* Assign the bridge and remap each port's VLANTable */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2384 | chip->ports[port].bridge_dev = bridge; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2385 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2386 | for (i = 0; i < chip->info->num_ports; ++i) { |
| 2387 | if (chip->ports[i].bridge_dev == bridge) { |
| 2388 | err = _mv88e6xxx_port_based_vlan_map(chip, i); |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2389 | if (err) |
| 2390 | break; |
| 2391 | } |
| 2392 | } |
| 2393 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2394 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | a669275 | 2016-02-12 12:09:39 -0500 | [diff] [blame] | 2395 | |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2396 | return err; |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2397 | } |
| 2398 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2399 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2400 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2401 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2402 | struct net_device *bridge = chip->ports[port].bridge_dev; |
Vivien Didelot | 16bfa70 | 2016-03-13 16:21:33 -0400 | [diff] [blame] | 2403 | int i; |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2404 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2405 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2406 | |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2407 | /* Unassign the bridge and remap each port's VLANTable */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2408 | chip->ports[port].bridge_dev = NULL; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2409 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2410 | for (i = 0; i < chip->info->num_ports; ++i) |
| 2411 | if (i == port || chip->ports[i].bridge_dev == bridge) |
| 2412 | if (_mv88e6xxx_port_based_vlan_map(chip, i)) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 2413 | netdev_warn(ds->ports[i].netdev, |
| 2414 | "failed to remap\n"); |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2415 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2416 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | 66d9cd0 | 2016-02-05 14:07:14 -0500 | [diff] [blame] | 2417 | } |
| 2418 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2419 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2420 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2421 | bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2422 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2423 | struct gpio_desc *gpiod = chip->reset; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2424 | unsigned long timeout; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2425 | int err, ret; |
| 2426 | u16 reg; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2427 | int i; |
| 2428 | |
| 2429 | /* Set all ports to the disabled state. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2430 | for (i = 0; i < chip->info->num_ports; i++) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2431 | err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, ®); |
| 2432 | if (err) |
| 2433 | return err; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2434 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2435 | err = mv88e6xxx_port_write(chip, i, PORT_CONTROL, |
| 2436 | reg & 0xfffc); |
| 2437 | if (err) |
| 2438 | return err; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2439 | } |
| 2440 | |
| 2441 | /* Wait for transmit queues to drain. */ |
| 2442 | usleep_range(2000, 4000); |
| 2443 | |
| 2444 | /* If there is a gpio connected to the reset pin, toggle it */ |
| 2445 | if (gpiod) { |
| 2446 | gpiod_set_value_cansleep(gpiod, 1); |
| 2447 | usleep_range(10000, 20000); |
| 2448 | gpiod_set_value_cansleep(gpiod, 0); |
| 2449 | usleep_range(10000, 20000); |
| 2450 | } |
| 2451 | |
| 2452 | /* Reset the switch. Keep the PPU active if requested. The PPU |
| 2453 | * needs to be active to support indirect phy register access |
| 2454 | * through global registers 0x18 and 0x19. |
| 2455 | */ |
| 2456 | if (ppu_active) |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2457 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2458 | else |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2459 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400); |
| 2460 | if (err) |
| 2461 | return err; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2462 | |
| 2463 | /* Wait up to one second for reset to complete. */ |
| 2464 | timeout = jiffies + 1 * HZ; |
| 2465 | while (time_before(jiffies, timeout)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2466 | ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2467 | if (ret < 0) |
| 2468 | return ret; |
| 2469 | |
| 2470 | if ((ret & is_reset) == is_reset) |
| 2471 | break; |
| 2472 | usleep_range(1000, 2000); |
| 2473 | } |
| 2474 | if (time_after(jiffies, timeout)) |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2475 | err = -ETIMEDOUT; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2476 | else |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2477 | err = 0; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2478 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2479 | return err; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2480 | } |
| 2481 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 2482 | static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2483 | { |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 2484 | u16 val; |
| 2485 | int err; |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2486 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 2487 | /* Clear Power Down bit */ |
| 2488 | err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); |
| 2489 | if (err) |
| 2490 | return err; |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2491 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 2492 | if (val & BMCR_PDOWN) { |
| 2493 | val &= ~BMCR_PDOWN; |
| 2494 | err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2495 | } |
| 2496 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 2497 | return err; |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2498 | } |
| 2499 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2500 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2501 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2502 | struct dsa_switch *ds = chip->ds; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2503 | int err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2504 | u16 reg; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2505 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2506 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2507 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2508 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || |
| 2509 | mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2510 | /* MAC Forcing register: don't force link, speed, |
| 2511 | * duplex or flow control state to any particular |
| 2512 | * values on physical ports, but force the CPU port |
| 2513 | * and all DSA ports to their maximum bandwidth and |
| 2514 | * full duplex. |
| 2515 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2516 | err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); |
Andrew Lunn | 60045cb | 2015-08-17 23:52:51 +0200 | [diff] [blame] | 2517 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
Russell King | 53adc9e | 2015-09-21 21:42:59 +0100 | [diff] [blame] | 2518 | reg &= ~PORT_PCS_CTRL_UNFORCED; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2519 | reg |= PORT_PCS_CTRL_FORCE_LINK | |
| 2520 | PORT_PCS_CTRL_LINK_UP | |
| 2521 | PORT_PCS_CTRL_DUPLEX_FULL | |
| 2522 | PORT_PCS_CTRL_FORCE_DUPLEX; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2523 | if (mv88e6xxx_6065_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2524 | reg |= PORT_PCS_CTRL_100; |
| 2525 | else |
| 2526 | reg |= PORT_PCS_CTRL_1000; |
| 2527 | } else { |
| 2528 | reg |= PORT_PCS_CTRL_UNFORCED; |
| 2529 | } |
| 2530 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2531 | err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); |
| 2532 | if (err) |
| 2533 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2534 | } |
| 2535 | |
| 2536 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
| 2537 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
| 2538 | * tunneling, determine priority by looking at 802.1p and IP |
| 2539 | * priority fields (IP prio has precedence), and set STP state |
| 2540 | * to Forwarding. |
| 2541 | * |
| 2542 | * If this is the CPU link, use DSA or EDSA tagging depending |
| 2543 | * on which tagging mode was configured. |
| 2544 | * |
| 2545 | * If this is a link to another switch, use DSA tagging mode. |
| 2546 | * |
| 2547 | * If this is the upstream port for this switch, enable |
| 2548 | * forwarding of unknown unicasts and multicasts. |
| 2549 | */ |
| 2550 | reg = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2551 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2552 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2553 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) || |
| 2554 | mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2555 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
| 2556 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | |
| 2557 | PORT_CONTROL_STATE_FORWARDING; |
| 2558 | if (dsa_is_cpu_port(ds, port)) { |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 2559 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) |
Andrew Lunn | 5377b80 | 2016-06-04 21:17:02 +0200 | [diff] [blame] | 2560 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | |
Andrew Lunn | c047a1f | 2015-09-29 01:50:56 +0200 | [diff] [blame] | 2561 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 2562 | else |
| 2563 | reg |= PORT_CONTROL_DSA_TAG; |
Jamie Lentin | f027e0c | 2016-08-22 16:01:04 +0200 | [diff] [blame] | 2564 | reg |= PORT_CONTROL_EGRESS_ADD_TAG | |
| 2565 | PORT_CONTROL_FORWARD_UNKNOWN; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2566 | } |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2567 | if (dsa_is_dsa_port(ds, port)) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2568 | if (mv88e6xxx_6095_family(chip) || |
| 2569 | mv88e6xxx_6185_family(chip)) |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2570 | reg |= PORT_CONTROL_DSA_TAG; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2571 | if (mv88e6xxx_6352_family(chip) || |
| 2572 | mv88e6xxx_6351_family(chip) || |
| 2573 | mv88e6xxx_6165_family(chip) || |
| 2574 | mv88e6xxx_6097_family(chip) || |
| 2575 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2576 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2577 | } |
| 2578 | |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2579 | if (port == dsa_upstream_port(ds)) |
| 2580 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | |
| 2581 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
| 2582 | } |
| 2583 | if (reg) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2584 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); |
| 2585 | if (err) |
| 2586 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2587 | } |
| 2588 | |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2589 | /* If this port is connected to a SerDes, make sure the SerDes is not |
| 2590 | * powered down. |
| 2591 | */ |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 2592 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2593 | err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); |
| 2594 | if (err) |
| 2595 | return err; |
| 2596 | reg &= PORT_STATUS_CMODE_MASK; |
| 2597 | if ((reg == PORT_STATUS_CMODE_100BASE_X) || |
| 2598 | (reg == PORT_STATUS_CMODE_1000BASE_X) || |
| 2599 | (reg == PORT_STATUS_CMODE_SGMII)) { |
| 2600 | err = mv88e6xxx_serdes_power_on(chip); |
| 2601 | if (err < 0) |
| 2602 | return err; |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 2603 | } |
| 2604 | } |
| 2605 | |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2606 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
Vivien Didelot | 46fbe5e | 2016-02-26 13:16:07 -0500 | [diff] [blame] | 2607 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2608 | * untagged frames on this port, do a destination address lookup on all |
| 2609 | * received packets as usual, disable ARP mirroring and don't send a |
| 2610 | * copy of all transmitted/received frames on this port to the CPU. |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2611 | */ |
| 2612 | reg = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2613 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2614 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2615 | mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || |
| 2616 | mv88e6xxx_6185_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2617 | reg = PORT_CONTROL_2_MAP_DA; |
| 2618 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2619 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2620 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip)) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2621 | reg |= PORT_CONTROL_2_JUMBO_10240; |
| 2622 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2623 | if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2624 | /* Set the upstream port this port should use */ |
| 2625 | reg |= dsa_upstream_port(ds); |
| 2626 | /* enable forwarding of unknown multicast addresses to |
| 2627 | * the upstream port |
| 2628 | */ |
| 2629 | if (port == dsa_upstream_port(ds)) |
| 2630 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; |
| 2631 | } |
| 2632 | |
Vivien Didelot | 46fbe5e | 2016-02-26 13:16:07 -0500 | [diff] [blame] | 2633 | reg |= PORT_CONTROL_2_8021Q_DISABLED; |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2634 | |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2635 | if (reg) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2636 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); |
| 2637 | if (err) |
| 2638 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2639 | } |
| 2640 | |
| 2641 | /* Port Association Vector: when learning source addresses |
| 2642 | * of packets, add the address to the address database using |
| 2643 | * a port bitmap that has only the bit for this port set and |
| 2644 | * the other bits clear. |
| 2645 | */ |
Andrew Lunn | 4c7ea3c | 2015-11-03 10:52:36 -0500 | [diff] [blame] | 2646 | reg = 1 << port; |
Vivien Didelot | 996ecb8 | 2016-04-14 14:42:08 -0400 | [diff] [blame] | 2647 | /* Disable learning for CPU port */ |
| 2648 | if (dsa_is_cpu_port(ds, port)) |
Vivien Didelot | 65fa402 | 2016-04-14 14:42:07 -0400 | [diff] [blame] | 2649 | reg = 0; |
Andrew Lunn | 4c7ea3c | 2015-11-03 10:52:36 -0500 | [diff] [blame] | 2650 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2651 | err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); |
| 2652 | if (err) |
| 2653 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2654 | |
| 2655 | /* Egress rate control 2: disable egress rate control. */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2656 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); |
| 2657 | if (err) |
| 2658 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2659 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2660 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2661 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
| 2662 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2663 | /* Do not limit the period of time that this port can |
| 2664 | * be paused for by the remote end or the period of |
| 2665 | * time that this port can pause the remote end. |
| 2666 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2667 | err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000); |
| 2668 | if (err) |
| 2669 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2670 | |
| 2671 | /* Port ATU control: disable limiting the number of |
| 2672 | * address database entries that this port is allowed |
| 2673 | * to use. |
| 2674 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2675 | err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, |
| 2676 | 0x0000); |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2677 | /* Priority Override: disable DA, SA and VTU priority |
| 2678 | * override. |
| 2679 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2680 | err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, |
| 2681 | 0x0000); |
| 2682 | if (err) |
| 2683 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2684 | |
| 2685 | /* Port Ethertype: use the Ethertype DSA Ethertype |
| 2686 | * value. |
| 2687 | */ |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 2688 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2689 | err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, |
| 2690 | ETH_P_EDSA); |
| 2691 | if (err) |
| 2692 | return err; |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 2693 | } |
| 2694 | |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2695 | /* Tag Remap: use an identity 802.1p prio -> switch |
| 2696 | * prio mapping. |
| 2697 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2698 | err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, |
| 2699 | 0x3210); |
| 2700 | if (err) |
| 2701 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2702 | |
| 2703 | /* Tag Remap 2: use an identity 802.1p prio -> switch |
| 2704 | * prio mapping. |
| 2705 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2706 | err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, |
| 2707 | 0x7654); |
| 2708 | if (err) |
| 2709 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2710 | } |
| 2711 | |
Jamie Lentin | 1bc261f | 2016-08-22 22:47:08 +0100 | [diff] [blame] | 2712 | /* Rate Control: disable ingress rate limiting. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2713 | if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || |
| 2714 | mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2715 | mv88e6xxx_6320_family(chip)) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2716 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, |
| 2717 | 0x0001); |
| 2718 | if (err) |
| 2719 | return err; |
Jamie Lentin | 1bc261f | 2016-08-22 22:47:08 +0100 | [diff] [blame] | 2720 | } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2721 | err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, |
| 2722 | 0x0000); |
| 2723 | if (err) |
| 2724 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2725 | } |
| 2726 | |
Guenter Roeck | 366f0a0 | 2015-03-26 18:36:30 -0700 | [diff] [blame] | 2727 | /* Port Control 1: disable trunking, disable sending |
| 2728 | * learning messages to this port. |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2729 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2730 | err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); |
| 2731 | if (err) |
| 2732 | return err; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2733 | |
Vivien Didelot | 207afda | 2016-04-14 14:42:09 -0400 | [diff] [blame] | 2734 | /* Port based VLAN map: give each port the same default address |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2735 | * database, and allow bidirectional communication between the |
| 2736 | * CPU and DSA port(s), and the other ports. |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2737 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2738 | err = _mv88e6xxx_port_fid_set(chip, port, 0); |
| 2739 | if (err) |
| 2740 | return err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2741 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2742 | err = _mv88e6xxx_port_based_vlan_map(chip, port); |
| 2743 | if (err) |
| 2744 | return err; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2745 | |
| 2746 | /* Default VLAN ID and priority: don't set a default VLAN |
| 2747 | * ID, and set the default packet priority to zero. |
| 2748 | */ |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame^] | 2749 | return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); |
Andrew Lunn | dbde9e6 | 2015-05-06 01:09:48 +0200 | [diff] [blame] | 2750 | } |
| 2751 | |
Vivien Didelot | 3b4caa1 | 2016-07-18 20:45:34 -0400 | [diff] [blame] | 2752 | static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) |
| 2753 | { |
| 2754 | int err; |
| 2755 | |
| 2756 | err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01, |
| 2757 | (addr[0] << 8) | addr[1]); |
| 2758 | if (err) |
| 2759 | return err; |
| 2760 | |
| 2761 | err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23, |
| 2762 | (addr[2] << 8) | addr[3]); |
| 2763 | if (err) |
| 2764 | return err; |
| 2765 | |
| 2766 | return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45, |
| 2767 | (addr[4] << 8) | addr[5]); |
| 2768 | } |
| 2769 | |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2770 | static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, |
| 2771 | unsigned int msecs) |
| 2772 | { |
| 2773 | const unsigned int coeff = chip->info->age_time_coeff; |
| 2774 | const unsigned int min = 0x01 * coeff; |
| 2775 | const unsigned int max = 0xff * coeff; |
| 2776 | u8 age_time; |
| 2777 | u16 val; |
| 2778 | int err; |
| 2779 | |
| 2780 | if (msecs < min || msecs > max) |
| 2781 | return -ERANGE; |
| 2782 | |
| 2783 | /* Round to nearest multiple of coeff */ |
| 2784 | age_time = (msecs + coeff / 2) / coeff; |
| 2785 | |
| 2786 | err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val); |
| 2787 | if (err) |
| 2788 | return err; |
| 2789 | |
| 2790 | /* AgeTime is 11:4 bits */ |
| 2791 | val &= ~0xff0; |
| 2792 | val |= age_time << 4; |
| 2793 | |
| 2794 | return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val); |
| 2795 | } |
| 2796 | |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 2797 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
| 2798 | unsigned int ageing_time) |
| 2799 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2800 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 2801 | int err; |
| 2802 | |
| 2803 | mutex_lock(&chip->reg_lock); |
| 2804 | err = mv88e6xxx_g1_set_age_time(chip, ageing_time); |
| 2805 | mutex_unlock(&chip->reg_lock); |
| 2806 | |
| 2807 | return err; |
| 2808 | } |
| 2809 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2810 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2811 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2812 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | b0745e87 | 2016-05-09 13:22:53 -0400 | [diff] [blame] | 2813 | u32 upstream_port = dsa_upstream_port(ds); |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2814 | u16 reg; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2815 | int err; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2816 | |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2817 | /* Enable the PHY Polling Unit if present, don't discard any packets, |
| 2818 | * and mask all interrupt sources. |
| 2819 | */ |
| 2820 | reg = 0; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2821 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || |
| 2822 | mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2823 | reg |= GLOBAL_CONTROL_PPU_ENABLE; |
| 2824 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2825 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg); |
Vivien Didelot | 119477b | 2016-05-09 13:22:51 -0400 | [diff] [blame] | 2826 | if (err) |
| 2827 | return err; |
| 2828 | |
Vivien Didelot | b0745e87 | 2016-05-09 13:22:53 -0400 | [diff] [blame] | 2829 | /* Configure the upstream port, and configure it as the port to which |
| 2830 | * ingress and egress and ARP monitor frames are to be sent. |
| 2831 | */ |
| 2832 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
| 2833 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | |
| 2834 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2835 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, |
| 2836 | reg); |
Vivien Didelot | b0745e87 | 2016-05-09 13:22:53 -0400 | [diff] [blame] | 2837 | if (err) |
| 2838 | return err; |
| 2839 | |
Vivien Didelot | 50484ff | 2016-05-09 13:22:54 -0400 | [diff] [blame] | 2840 | /* Disable remote management, and set the switch's DSA device number. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2841 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2, |
Vivien Didelot | 50484ff | 2016-05-09 13:22:54 -0400 | [diff] [blame] | 2842 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | |
| 2843 | (ds->index & 0x1f)); |
| 2844 | if (err) |
| 2845 | return err; |
| 2846 | |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2847 | /* Clear all the VTU and STU entries */ |
| 2848 | err = _mv88e6xxx_vtu_stu_flush(chip); |
| 2849 | if (err < 0) |
| 2850 | return err; |
| 2851 | |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2852 | /* Set the default address aging time to 5 minutes, and |
| 2853 | * enable address learn messages to be sent to all message |
| 2854 | * ports. |
| 2855 | */ |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2856 | err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
| 2857 | GLOBAL_ATU_CONTROL_LEARN2ALL); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2858 | if (err) |
| 2859 | return err; |
| 2860 | |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 2861 | err = mv88e6xxx_g1_set_age_time(chip, 300000); |
| 2862 | if (err) |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2863 | return err; |
| 2864 | |
| 2865 | /* Clear all ATU entries */ |
| 2866 | err = _mv88e6xxx_atu_flush(chip, 0, true); |
| 2867 | if (err) |
| 2868 | return err; |
| 2869 | |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2870 | /* Configure the IP ToS mapping registers. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2871 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2872 | if (err) |
| 2873 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2874 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2875 | if (err) |
| 2876 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2877 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2878 | if (err) |
| 2879 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2880 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2881 | if (err) |
| 2882 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2883 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2884 | if (err) |
| 2885 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2886 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2887 | if (err) |
| 2888 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2889 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2890 | if (err) |
| 2891 | return err; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2892 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2893 | if (err) |
| 2894 | return err; |
| 2895 | |
| 2896 | /* Configure the IEEE 802.1p priority mapping register. */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2897 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2898 | if (err) |
| 2899 | return err; |
| 2900 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2901 | /* Clear the statistics counters for all ports */ |
| 2902 | err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, |
| 2903 | GLOBAL_STATS_OP_FLUSH_ALL); |
| 2904 | if (err) |
| 2905 | return err; |
| 2906 | |
| 2907 | /* Wait for the flush to complete. */ |
| 2908 | err = _mv88e6xxx_stats_wait(chip); |
| 2909 | if (err) |
| 2910 | return err; |
| 2911 | |
| 2912 | return 0; |
| 2913 | } |
| 2914 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2915 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
Guenter Roeck | acdaffc | 2015-03-26 18:36:28 -0700 | [diff] [blame] | 2916 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2917 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2918 | int err; |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2919 | int i; |
| 2920 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2921 | chip->ds = ds; |
| 2922 | ds->slave_mii_bus = chip->mdio_bus; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2923 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2924 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2925 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2926 | err = mv88e6xxx_switch_reset(chip); |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 2927 | if (err) |
| 2928 | goto unlock; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2929 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2930 | /* Setup Switch Port Registers */ |
| 2931 | for (i = 0; i < chip->info->num_ports; i++) { |
| 2932 | err = mv88e6xxx_setup_port(chip, i); |
| 2933 | if (err) |
| 2934 | goto unlock; |
| 2935 | } |
| 2936 | |
| 2937 | /* Setup Switch Global 1 Registers */ |
| 2938 | err = mv88e6xxx_g1_setup(chip); |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2939 | if (err) |
| 2940 | goto unlock; |
| 2941 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2942 | /* Setup Switch Global 2 Registers */ |
| 2943 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { |
| 2944 | err = mv88e6xxx_g2_setup(chip); |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 2945 | if (err) |
| 2946 | goto unlock; |
| 2947 | } |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2948 | |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 2949 | unlock: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2950 | mutex_unlock(&chip->reg_lock); |
Andrew Lunn | db687a5 | 2015-06-20 21:31:29 +0200 | [diff] [blame] | 2951 | |
Andrew Lunn | 48ace4e | 2016-04-14 23:47:12 +0200 | [diff] [blame] | 2952 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2953 | } |
| 2954 | |
Vivien Didelot | 3b4caa1 | 2016-07-18 20:45:34 -0400 | [diff] [blame] | 2955 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
| 2956 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2957 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 3b4caa1 | 2016-07-18 20:45:34 -0400 | [diff] [blame] | 2958 | int err; |
| 2959 | |
| 2960 | mutex_lock(&chip->reg_lock); |
| 2961 | |
| 2962 | /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */ |
| 2963 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC)) |
| 2964 | err = mv88e6xxx_g2_set_switch_mac(chip, addr); |
| 2965 | else |
| 2966 | err = mv88e6xxx_g1_set_switch_mac(chip, addr); |
| 2967 | |
| 2968 | mutex_unlock(&chip->reg_lock); |
| 2969 | |
| 2970 | return err; |
| 2971 | } |
| 2972 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2973 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2974 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2975 | struct mv88e6xxx_chip *chip = bus->priv; |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2976 | u16 val; |
| 2977 | int err; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2978 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2979 | if (phy >= chip->info->num_ports) |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 2980 | return 0xffff; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2981 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2982 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2983 | err = mv88e6xxx_phy_read(chip, phy, reg, &val); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2984 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2985 | |
| 2986 | return err ? err : val; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2987 | } |
| 2988 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2989 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2990 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2991 | struct mv88e6xxx_chip *chip = bus->priv; |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2992 | int err; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2993 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2994 | if (phy >= chip->info->num_ports) |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 2995 | return 0xffff; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 2996 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2997 | mutex_lock(&chip->reg_lock); |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 2998 | err = mv88e6xxx_phy_write(chip, phy, reg, val); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2999 | mutex_unlock(&chip->reg_lock); |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3000 | |
| 3001 | return err; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3002 | } |
| 3003 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3004 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3005 | struct device_node *np) |
| 3006 | { |
| 3007 | static int index; |
| 3008 | struct mii_bus *bus; |
| 3009 | int err; |
| 3010 | |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3011 | if (np) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3012 | chip->mdio_np = of_get_child_by_name(np, "mdio"); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3013 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3014 | bus = devm_mdiobus_alloc(chip->dev); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3015 | if (!bus) |
| 3016 | return -ENOMEM; |
| 3017 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3018 | bus->priv = (void *)chip; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3019 | if (np) { |
| 3020 | bus->name = np->full_name; |
| 3021 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); |
| 3022 | } else { |
| 3023 | bus->name = "mv88e6xxx SMI"; |
| 3024 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); |
| 3025 | } |
| 3026 | |
| 3027 | bus->read = mv88e6xxx_mdio_read; |
| 3028 | bus->write = mv88e6xxx_mdio_write; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3029 | bus->parent = chip->dev; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3030 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3031 | if (chip->mdio_np) |
| 3032 | err = of_mdiobus_register(bus, chip->mdio_np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3033 | else |
| 3034 | err = mdiobus_register(bus); |
| 3035 | if (err) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3036 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3037 | goto out; |
| 3038 | } |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3039 | chip->mdio_bus = bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3040 | |
| 3041 | return 0; |
| 3042 | |
| 3043 | out: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3044 | if (chip->mdio_np) |
| 3045 | of_node_put(chip->mdio_np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3046 | |
| 3047 | return err; |
| 3048 | } |
| 3049 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3050 | static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3051 | |
| 3052 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3053 | struct mii_bus *bus = chip->mdio_bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3054 | |
| 3055 | mdiobus_unregister(bus); |
| 3056 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3057 | if (chip->mdio_np) |
| 3058 | of_node_put(chip->mdio_np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3059 | } |
| 3060 | |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3061 | #ifdef CONFIG_NET_DSA_HWMON |
| 3062 | |
| 3063 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) |
| 3064 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3065 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3066 | u16 val; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3067 | int ret; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3068 | |
| 3069 | *temp = 0; |
| 3070 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3071 | mutex_lock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3072 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3073 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3074 | if (ret < 0) |
| 3075 | goto error; |
| 3076 | |
| 3077 | /* Enable temperature sensor */ |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3078 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3079 | if (ret < 0) |
| 3080 | goto error; |
| 3081 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3082 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3083 | if (ret < 0) |
| 3084 | goto error; |
| 3085 | |
| 3086 | /* Wait for temperature to stabilize */ |
| 3087 | usleep_range(10000, 12000); |
| 3088 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3089 | ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); |
| 3090 | if (ret < 0) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3091 | goto error; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3092 | |
| 3093 | /* Disable temperature sensor */ |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3094 | ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3095 | if (ret < 0) |
| 3096 | goto error; |
| 3097 | |
| 3098 | *temp = ((val & 0x1f) - 5) * 5; |
| 3099 | |
| 3100 | error: |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3101 | mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3102 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3103 | return ret; |
| 3104 | } |
| 3105 | |
| 3106 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) |
| 3107 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3108 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3109 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3110 | u16 val; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3111 | int ret; |
| 3112 | |
| 3113 | *temp = 0; |
| 3114 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3115 | mutex_lock(&chip->reg_lock); |
| 3116 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); |
| 3117 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3118 | if (ret < 0) |
| 3119 | return ret; |
| 3120 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3121 | *temp = (val & 0xff) - 25; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3122 | |
| 3123 | return 0; |
| 3124 | } |
| 3125 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3126 | static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3127 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3128 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 3129 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3130 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) |
Vivien Didelot | 6594f61 | 2016-05-09 13:22:42 -0400 | [diff] [blame] | 3131 | return -EOPNOTSUPP; |
| 3132 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3133 | if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3134 | return mv88e63xx_get_temp(ds, temp); |
| 3135 | |
| 3136 | return mv88e61xx_get_temp(ds, temp); |
| 3137 | } |
| 3138 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3139 | static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3140 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3141 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3142 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3143 | u16 val; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3144 | int ret; |
| 3145 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3146 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3147 | return -EOPNOTSUPP; |
| 3148 | |
| 3149 | *temp = 0; |
| 3150 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3151 | mutex_lock(&chip->reg_lock); |
| 3152 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); |
| 3153 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3154 | if (ret < 0) |
| 3155 | return ret; |
| 3156 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3157 | *temp = (((val >> 8) & 0x1f) * 5) - 25; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3158 | |
| 3159 | return 0; |
| 3160 | } |
| 3161 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3162 | static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3163 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3164 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3165 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3166 | u16 val; |
| 3167 | int err; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3168 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3169 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3170 | return -EOPNOTSUPP; |
| 3171 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3172 | mutex_lock(&chip->reg_lock); |
| 3173 | err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); |
| 3174 | if (err) |
| 3175 | goto unlock; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3176 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3177 | err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, |
| 3178 | (val & 0xe0ff) | (temp << 8)); |
| 3179 | unlock: |
| 3180 | mutex_unlock(&chip->reg_lock); |
| 3181 | |
| 3182 | return err; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3183 | } |
| 3184 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3185 | static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3186 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3187 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3188 | int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3189 | u16 val; |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3190 | int ret; |
| 3191 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3192 | if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3193 | return -EOPNOTSUPP; |
| 3194 | |
| 3195 | *alarm = false; |
| 3196 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3197 | mutex_lock(&chip->reg_lock); |
| 3198 | ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); |
| 3199 | mutex_unlock(&chip->reg_lock); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3200 | if (ret < 0) |
| 3201 | return ret; |
| 3202 | |
Vivien Didelot | 9c93829 | 2016-08-15 17:19:02 -0400 | [diff] [blame] | 3203 | *alarm = !!(val & 0x40); |
Guenter Roeck | c22995c | 2015-07-25 09:42:28 -0700 | [diff] [blame] | 3204 | |
| 3205 | return 0; |
| 3206 | } |
| 3207 | #endif /* CONFIG_NET_DSA_HWMON */ |
| 3208 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3209 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
| 3210 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3211 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3212 | |
| 3213 | return chip->eeprom_len; |
| 3214 | } |
| 3215 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3216 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
| 3217 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3218 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3219 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3220 | int err; |
| 3221 | |
| 3222 | mutex_lock(&chip->reg_lock); |
| 3223 | |
| 3224 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16)) |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 3225 | err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data); |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3226 | else |
| 3227 | err = -EOPNOTSUPP; |
| 3228 | |
| 3229 | mutex_unlock(&chip->reg_lock); |
| 3230 | |
| 3231 | if (err) |
| 3232 | return err; |
| 3233 | |
| 3234 | eeprom->magic = 0xc3ec4951; |
| 3235 | |
| 3236 | return 0; |
| 3237 | } |
| 3238 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3239 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
| 3240 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3241 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3242 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3243 | int err; |
| 3244 | |
| 3245 | if (eeprom->magic != 0xc3ec4951) |
| 3246 | return -EINVAL; |
| 3247 | |
| 3248 | mutex_lock(&chip->reg_lock); |
| 3249 | |
| 3250 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16)) |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 3251 | err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data); |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3252 | else |
| 3253 | err = -EOPNOTSUPP; |
| 3254 | |
| 3255 | mutex_unlock(&chip->reg_lock); |
| 3256 | |
| 3257 | return err; |
| 3258 | } |
| 3259 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3260 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
| 3261 | [MV88E6085] = { |
| 3262 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, |
| 3263 | .family = MV88E6XXX_FAMILY_6097, |
| 3264 | .name = "Marvell 88E6085", |
| 3265 | .num_databases = 4096, |
| 3266 | .num_ports = 10, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3267 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3268 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3269 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
| 3270 | }, |
| 3271 | |
| 3272 | [MV88E6095] = { |
| 3273 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, |
| 3274 | .family = MV88E6XXX_FAMILY_6095, |
| 3275 | .name = "Marvell 88E6095/88E6095F", |
| 3276 | .num_databases = 256, |
| 3277 | .num_ports = 11, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3278 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3279 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3280 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
| 3281 | }, |
| 3282 | |
| 3283 | [MV88E6123] = { |
| 3284 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, |
| 3285 | .family = MV88E6XXX_FAMILY_6165, |
| 3286 | .name = "Marvell 88E6123", |
| 3287 | .num_databases = 4096, |
| 3288 | .num_ports = 3, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3289 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3290 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3291 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
| 3292 | }, |
| 3293 | |
| 3294 | [MV88E6131] = { |
| 3295 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, |
| 3296 | .family = MV88E6XXX_FAMILY_6185, |
| 3297 | .name = "Marvell 88E6131", |
| 3298 | .num_databases = 256, |
| 3299 | .num_ports = 8, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3300 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3301 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3302 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
| 3303 | }, |
| 3304 | |
| 3305 | [MV88E6161] = { |
| 3306 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, |
| 3307 | .family = MV88E6XXX_FAMILY_6165, |
| 3308 | .name = "Marvell 88E6161", |
| 3309 | .num_databases = 4096, |
| 3310 | .num_ports = 6, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3311 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3312 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3313 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
| 3314 | }, |
| 3315 | |
| 3316 | [MV88E6165] = { |
| 3317 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, |
| 3318 | .family = MV88E6XXX_FAMILY_6165, |
| 3319 | .name = "Marvell 88E6165", |
| 3320 | .num_databases = 4096, |
| 3321 | .num_ports = 6, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3322 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3323 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3324 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
| 3325 | }, |
| 3326 | |
| 3327 | [MV88E6171] = { |
| 3328 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, |
| 3329 | .family = MV88E6XXX_FAMILY_6351, |
| 3330 | .name = "Marvell 88E6171", |
| 3331 | .num_databases = 4096, |
| 3332 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3333 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3334 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3335 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3336 | }, |
| 3337 | |
| 3338 | [MV88E6172] = { |
| 3339 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, |
| 3340 | .family = MV88E6XXX_FAMILY_6352, |
| 3341 | .name = "Marvell 88E6172", |
| 3342 | .num_databases = 4096, |
| 3343 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3344 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3345 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3346 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3347 | }, |
| 3348 | |
| 3349 | [MV88E6175] = { |
| 3350 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, |
| 3351 | .family = MV88E6XXX_FAMILY_6351, |
| 3352 | .name = "Marvell 88E6175", |
| 3353 | .num_databases = 4096, |
| 3354 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3355 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3356 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3357 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3358 | }, |
| 3359 | |
| 3360 | [MV88E6176] = { |
| 3361 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, |
| 3362 | .family = MV88E6XXX_FAMILY_6352, |
| 3363 | .name = "Marvell 88E6176", |
| 3364 | .num_databases = 4096, |
| 3365 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3366 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3367 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3368 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3369 | }, |
| 3370 | |
| 3371 | [MV88E6185] = { |
| 3372 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, |
| 3373 | .family = MV88E6XXX_FAMILY_6185, |
| 3374 | .name = "Marvell 88E6185", |
| 3375 | .num_databases = 256, |
| 3376 | .num_ports = 10, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3377 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3378 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3379 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
| 3380 | }, |
| 3381 | |
| 3382 | [MV88E6240] = { |
| 3383 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, |
| 3384 | .family = MV88E6XXX_FAMILY_6352, |
| 3385 | .name = "Marvell 88E6240", |
| 3386 | .num_databases = 4096, |
| 3387 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3388 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3389 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3390 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3391 | }, |
| 3392 | |
| 3393 | [MV88E6320] = { |
| 3394 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, |
| 3395 | .family = MV88E6XXX_FAMILY_6320, |
| 3396 | .name = "Marvell 88E6320", |
| 3397 | .num_databases = 4096, |
| 3398 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3399 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3400 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3401 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
| 3402 | }, |
| 3403 | |
| 3404 | [MV88E6321] = { |
| 3405 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, |
| 3406 | .family = MV88E6XXX_FAMILY_6320, |
| 3407 | .name = "Marvell 88E6321", |
| 3408 | .num_databases = 4096, |
| 3409 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3410 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3411 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3412 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
| 3413 | }, |
| 3414 | |
| 3415 | [MV88E6350] = { |
| 3416 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, |
| 3417 | .family = MV88E6XXX_FAMILY_6351, |
| 3418 | .name = "Marvell 88E6350", |
| 3419 | .num_databases = 4096, |
| 3420 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3421 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3422 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3423 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3424 | }, |
| 3425 | |
| 3426 | [MV88E6351] = { |
| 3427 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, |
| 3428 | .family = MV88E6XXX_FAMILY_6351, |
| 3429 | .name = "Marvell 88E6351", |
| 3430 | .num_databases = 4096, |
| 3431 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3432 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3433 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3434 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
| 3435 | }, |
| 3436 | |
| 3437 | [MV88E6352] = { |
| 3438 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, |
| 3439 | .family = MV88E6XXX_FAMILY_6352, |
| 3440 | .name = "Marvell 88E6352", |
| 3441 | .num_databases = 4096, |
| 3442 | .num_ports = 7, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 3443 | .port_base_addr = 0x10, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 3444 | .age_time_coeff = 15000, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3445 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
| 3446 | }, |
| 3447 | }; |
| 3448 | |
Vivien Didelot | 5f7c036 | 2016-06-20 13:14:04 -0400 | [diff] [blame] | 3449 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3450 | { |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3451 | int i; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3452 | |
Vivien Didelot | 5f7c036 | 2016-06-20 13:14:04 -0400 | [diff] [blame] | 3453 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
| 3454 | if (mv88e6xxx_table[i].prod_num == prod_num) |
| 3455 | return &mv88e6xxx_table[i]; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3456 | |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 3457 | return NULL; |
| 3458 | } |
| 3459 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3460 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3461 | { |
| 3462 | const struct mv88e6xxx_info *info; |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 3463 | unsigned int prod_num, rev; |
| 3464 | u16 id; |
| 3465 | int err; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3466 | |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 3467 | mutex_lock(&chip->reg_lock); |
| 3468 | err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); |
| 3469 | mutex_unlock(&chip->reg_lock); |
| 3470 | if (err) |
| 3471 | return err; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3472 | |
| 3473 | prod_num = (id & 0xfff0) >> 4; |
| 3474 | rev = id & 0x000f; |
| 3475 | |
| 3476 | info = mv88e6xxx_lookup_info(prod_num); |
| 3477 | if (!info) |
| 3478 | return -ENODEV; |
| 3479 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3480 | /* Update the compatible info with the probed one */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3481 | chip->info = info; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3482 | |
Vivien Didelot | ca070c1 | 2016-09-02 14:45:34 -0400 | [diff] [blame] | 3483 | err = mv88e6xxx_g2_require(chip); |
| 3484 | if (err) |
| 3485 | return err; |
| 3486 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3487 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
| 3488 | chip->info->prod_num, chip->info->name, rev); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3489 | |
| 3490 | return 0; |
| 3491 | } |
| 3492 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3493 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3494 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3495 | struct mv88e6xxx_chip *chip; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3496 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3497 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
| 3498 | if (!chip) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3499 | return NULL; |
| 3500 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3501 | chip->dev = dev; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3502 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3503 | mutex_init(&chip->reg_lock); |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3504 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3505 | return chip; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3506 | } |
| 3507 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 3508 | static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = { |
| 3509 | .read = mv88e6xxx_g2_smi_phy_read, |
| 3510 | .write = mv88e6xxx_g2_smi_phy_write, |
| 3511 | }; |
| 3512 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3513 | static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = { |
| 3514 | .read = mv88e6xxx_read, |
| 3515 | .write = mv88e6xxx_write, |
| 3516 | }; |
| 3517 | |
| 3518 | static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) |
| 3519 | { |
| 3520 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) { |
| 3521 | chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops; |
| 3522 | } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) { |
| 3523 | chip->phy_ops = &mv88e6xxx_phy_ppu_ops; |
| 3524 | mv88e6xxx_ppu_state_init(chip); |
| 3525 | } else { |
| 3526 | chip->phy_ops = &mv88e6xxx_phy_ops; |
| 3527 | } |
| 3528 | } |
| 3529 | |
Andrew Lunn | 930188c | 2016-08-22 16:01:03 +0200 | [diff] [blame] | 3530 | static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) |
| 3531 | { |
| 3532 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) { |
| 3533 | mv88e6xxx_ppu_state_destroy(chip); |
| 3534 | } |
| 3535 | } |
| 3536 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3537 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3538 | struct mii_bus *bus, int sw_addr) |
| 3539 | { |
| 3540 | /* ADDR[0] pin is unavailable externally and considered zero */ |
| 3541 | if (sw_addr & 0x1) |
| 3542 | return -EINVAL; |
| 3543 | |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 3544 | if (sw_addr == 0) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3545 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 3546 | else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3547 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 3548 | else |
| 3549 | return -EINVAL; |
| 3550 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3551 | chip->bus = bus; |
| 3552 | chip->sw_addr = sw_addr; |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3553 | |
| 3554 | return 0; |
| 3555 | } |
| 3556 | |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 3557 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) |
| 3558 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3559 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 3560 | |
| 3561 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) |
| 3562 | return DSA_TAG_PROTO_EDSA; |
| 3563 | |
| 3564 | return DSA_TAG_PROTO_DSA; |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 3565 | } |
| 3566 | |
Andrew Lunn | fcdce7d | 2016-05-10 23:27:20 +0200 | [diff] [blame] | 3567 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
| 3568 | struct device *host_dev, int sw_addr, |
| 3569 | void **priv) |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 3570 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3571 | struct mv88e6xxx_chip *chip; |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3572 | struct mii_bus *bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3573 | int err; |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 3574 | |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3575 | bus = dsa_host_dev_to_mii_bus(host_dev); |
Andrew Lunn | c156913 | 2016-04-13 02:40:45 +0200 | [diff] [blame] | 3576 | if (!bus) |
| 3577 | return NULL; |
| 3578 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3579 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
| 3580 | if (!chip) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3581 | return NULL; |
| 3582 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3583 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3584 | chip->info = &mv88e6xxx_table[MV88E6085]; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3585 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3586 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3587 | if (err) |
| 3588 | goto free; |
| 3589 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3590 | err = mv88e6xxx_detect(chip); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3591 | if (err) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3592 | goto free; |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3593 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3594 | mv88e6xxx_phy_init(chip); |
| 3595 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3596 | err = mv88e6xxx_mdio_register(chip, NULL); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3597 | if (err) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3598 | goto free; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3599 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3600 | *priv = chip; |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 3601 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3602 | return chip->info->name; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3603 | free: |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3604 | devm_kfree(dsa_dev, chip); |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 3605 | |
| 3606 | return NULL; |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 3607 | } |
| 3608 | |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 3609 | static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, |
| 3610 | const struct switchdev_obj_port_mdb *mdb, |
| 3611 | struct switchdev_trans *trans) |
| 3612 | { |
| 3613 | /* We don't need any dynamic resource from the kernel (yet), |
| 3614 | * so skip the prepare phase. |
| 3615 | */ |
| 3616 | |
| 3617 | return 0; |
| 3618 | } |
| 3619 | |
| 3620 | static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, |
| 3621 | const struct switchdev_obj_port_mdb *mdb, |
| 3622 | struct switchdev_trans *trans) |
| 3623 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3624 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 3625 | |
| 3626 | mutex_lock(&chip->reg_lock); |
| 3627 | if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, |
| 3628 | GLOBAL_ATU_DATA_STATE_MC_STATIC)) |
| 3629 | netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); |
| 3630 | mutex_unlock(&chip->reg_lock); |
| 3631 | } |
| 3632 | |
| 3633 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, |
| 3634 | const struct switchdev_obj_port_mdb *mdb) |
| 3635 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3636 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 3637 | int err; |
| 3638 | |
| 3639 | mutex_lock(&chip->reg_lock); |
| 3640 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, |
| 3641 | GLOBAL_ATU_DATA_STATE_UNUSED); |
| 3642 | mutex_unlock(&chip->reg_lock); |
| 3643 | |
| 3644 | return err; |
| 3645 | } |
| 3646 | |
| 3647 | static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, |
| 3648 | struct switchdev_obj_port_mdb *mdb, |
| 3649 | int (*cb)(struct switchdev_obj *obj)) |
| 3650 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3651 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 3652 | int err; |
| 3653 | |
| 3654 | mutex_lock(&chip->reg_lock); |
| 3655 | err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); |
| 3656 | mutex_unlock(&chip->reg_lock); |
| 3657 | |
| 3658 | return err; |
| 3659 | } |
| 3660 | |
Vivien Didelot | 9d490b4 | 2016-08-23 12:38:56 -0400 | [diff] [blame] | 3661 | static struct dsa_switch_ops mv88e6xxx_switch_ops = { |
Andrew Lunn | fcdce7d | 2016-05-10 23:27:20 +0200 | [diff] [blame] | 3662 | .probe = mv88e6xxx_drv_probe, |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 3663 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3664 | .setup = mv88e6xxx_setup, |
| 3665 | .set_addr = mv88e6xxx_set_addr, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3666 | .adjust_link = mv88e6xxx_adjust_link, |
| 3667 | .get_strings = mv88e6xxx_get_strings, |
| 3668 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, |
| 3669 | .get_sset_count = mv88e6xxx_get_sset_count, |
| 3670 | .set_eee = mv88e6xxx_set_eee, |
| 3671 | .get_eee = mv88e6xxx_get_eee, |
| 3672 | #ifdef CONFIG_NET_DSA_HWMON |
| 3673 | .get_temp = mv88e6xxx_get_temp, |
| 3674 | .get_temp_limit = mv88e6xxx_get_temp_limit, |
| 3675 | .set_temp_limit = mv88e6xxx_set_temp_limit, |
| 3676 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, |
| 3677 | #endif |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 3678 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3679 | .get_eeprom = mv88e6xxx_get_eeprom, |
| 3680 | .set_eeprom = mv88e6xxx_set_eeprom, |
| 3681 | .get_regs_len = mv88e6xxx_get_regs_len, |
| 3682 | .get_regs = mv88e6xxx_get_regs, |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 3683 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3684 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
| 3685 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, |
| 3686 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, |
| 3687 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
| 3688 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, |
| 3689 | .port_vlan_add = mv88e6xxx_port_vlan_add, |
| 3690 | .port_vlan_del = mv88e6xxx_port_vlan_del, |
| 3691 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, |
| 3692 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, |
| 3693 | .port_fdb_add = mv88e6xxx_port_fdb_add, |
| 3694 | .port_fdb_del = mv88e6xxx_port_fdb_del, |
| 3695 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 3696 | .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, |
| 3697 | .port_mdb_add = mv88e6xxx_port_mdb_add, |
| 3698 | .port_mdb_del = mv88e6xxx_port_mdb_del, |
| 3699 | .port_mdb_dump = mv88e6xxx_port_mdb_dump, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3700 | }; |
| 3701 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3702 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3703 | struct device_node *np) |
| 3704 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3705 | struct device *dev = chip->dev; |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3706 | struct dsa_switch *ds; |
| 3707 | |
| 3708 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); |
| 3709 | if (!ds) |
| 3710 | return -ENOMEM; |
| 3711 | |
| 3712 | ds->dev = dev; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3713 | ds->priv = chip; |
Vivien Didelot | 9d490b4 | 2016-08-23 12:38:56 -0400 | [diff] [blame] | 3714 | ds->ops = &mv88e6xxx_switch_ops; |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3715 | |
| 3716 | dev_set_drvdata(dev, ds); |
| 3717 | |
| 3718 | return dsa_register_switch(ds, np); |
| 3719 | } |
| 3720 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3721 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3722 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3723 | dsa_unregister_switch(chip->ds); |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 3724 | } |
| 3725 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 3726 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3727 | { |
| 3728 | struct device *dev = &mdiodev->dev; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 3729 | struct device_node *np = dev->of_node; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3730 | const struct mv88e6xxx_info *compat_info; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3731 | struct mv88e6xxx_chip *chip; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 3732 | u32 eeprom_len; |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 3733 | int err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3734 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3735 | compat_info = of_device_get_match_data(dev); |
| 3736 | if (!compat_info) |
| 3737 | return -EINVAL; |
| 3738 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3739 | chip = mv88e6xxx_alloc_chip(dev); |
| 3740 | if (!chip) |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3741 | return -ENOMEM; |
| 3742 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3743 | chip->info = compat_info; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3744 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3745 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 3746 | if (err) |
| 3747 | return err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3748 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3749 | err = mv88e6xxx_detect(chip); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 3750 | if (err) |
| 3751 | return err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3752 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3753 | mv88e6xxx_phy_init(chip); |
| 3754 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3755 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); |
| 3756 | if (IS_ERR(chip->reset)) |
| 3757 | return PTR_ERR(chip->reset); |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 3758 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3759 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) && |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 3760 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3761 | chip->eeprom_len = eeprom_len; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 3762 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3763 | err = mv88e6xxx_mdio_register(chip, np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3764 | if (err) |
| 3765 | return err; |
| 3766 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3767 | err = mv88e6xxx_register_switch(chip, np); |
Andrew Lunn | 83c0afa | 2016-06-04 21:17:07 +0200 | [diff] [blame] | 3768 | if (err) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3769 | mv88e6xxx_mdio_unregister(chip); |
Andrew Lunn | 83c0afa | 2016-06-04 21:17:07 +0200 | [diff] [blame] | 3770 | return err; |
| 3771 | } |
| 3772 | |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3773 | return 0; |
| 3774 | } |
| 3775 | |
| 3776 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) |
| 3777 | { |
| 3778 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3779 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3780 | |
Andrew Lunn | 930188c | 2016-08-22 16:01:03 +0200 | [diff] [blame] | 3781 | mv88e6xxx_phy_destroy(chip); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3782 | mv88e6xxx_unregister_switch(chip); |
| 3783 | mv88e6xxx_mdio_unregister(chip); |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3784 | } |
| 3785 | |
| 3786 | static const struct of_device_id mv88e6xxx_of_match[] = { |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 3787 | { |
| 3788 | .compatible = "marvell,mv88e6085", |
| 3789 | .data = &mv88e6xxx_table[MV88E6085], |
| 3790 | }, |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3791 | { /* sentinel */ }, |
| 3792 | }; |
| 3793 | |
| 3794 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); |
| 3795 | |
| 3796 | static struct mdio_driver mv88e6xxx_driver = { |
| 3797 | .probe = mv88e6xxx_probe, |
| 3798 | .remove = mv88e6xxx_remove, |
| 3799 | .mdiodrv.driver = { |
| 3800 | .name = "mv88e6085", |
| 3801 | .of_match_table = mv88e6xxx_of_match, |
| 3802 | }, |
| 3803 | }; |
| 3804 | |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 3805 | static int __init mv88e6xxx_init(void) |
| 3806 | { |
Vivien Didelot | 9d490b4 | 2016-08-23 12:38:56 -0400 | [diff] [blame] | 3807 | register_switch_driver(&mv88e6xxx_switch_ops); |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3808 | return mdio_driver_register(&mv88e6xxx_driver); |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 3809 | } |
| 3810 | module_init(mv88e6xxx_init); |
| 3811 | |
| 3812 | static void __exit mv88e6xxx_cleanup(void) |
| 3813 | { |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 3814 | mdio_driver_unregister(&mv88e6xxx_driver); |
Vivien Didelot | 9d490b4 | 2016-08-23 12:38:56 -0400 | [diff] [blame] | 3815 | unregister_switch_driver(&mv88e6xxx_switch_ops); |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 3816 | } |
| 3817 | module_exit(mv88e6xxx_cleanup); |
Ben Hutchings | 3d825ed | 2011-11-25 14:37:16 +0000 | [diff] [blame] | 3818 | |
| 3819 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); |
| 3820 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); |
| 3821 | MODULE_LICENSE("GPL"); |