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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00002/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04003 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00005 * Copyright (c) 2008 Marvell Semiconductor
6 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02007 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
Vivien Didelot4333d612017-03-28 15:10:36 -04009 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 */
12
Barry Grussling19b2f972013-01-08 16:05:54 +000013#include <linux/delay.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070014#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020015#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070016#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020017#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000020#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000021#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020022#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000023#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040024#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020025#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020026#include <linux/of_mdio.h>
Andrew Lunn877b7cb2018-05-19 22:31:34 +020027#include <linux/platform_data/mv88e6xxx.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000028#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010029#include <linux/gpio/consumer.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000030#include <linux/phy.h>
Russell Kingc9a23562018-05-10 13:17:35 -070031#include <linux/phylink.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000032#include <net/dsa.h>
Vivien Didelotec561272016-09-02 14:45:33 -040033
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -040034#include "chip.h"
Vivien Didelota935c052016-09-29 12:21:53 -040035#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040036#include "global2.h"
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +010037#include "hwtstamp.h"
Andrew Lunn10fa5bf2017-05-26 01:03:20 +020038#include "phy.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010039#include "port.h"
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +010040#include "ptp.h"
Andrew Lunn6d917822017-05-26 01:03:21 +020041#include "serdes.h"
Vivien Didelote7ba0fa2019-05-03 19:28:22 -040042#include "smi.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000043
Vivien Didelotfad09c72016-06-21 12:28:20 -040044static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040045{
Vivien Didelotfad09c72016-06-21 12:28:20 -040046 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
47 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040048 dump_stack();
49 }
50}
51
Vivien Didelotec561272016-09-02 14:45:33 -040052int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040053{
54 int err;
55
Vivien Didelotfad09c72016-06-21 12:28:20 -040056 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040057
Vivien Didelotfad09c72016-06-21 12:28:20 -040058 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040059 if (err)
60 return err;
61
Vivien Didelotfad09c72016-06-21 12:28:20 -040062 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040063 addr, reg, *val);
64
65 return 0;
66}
67
Vivien Didelotec561272016-09-02 14:45:33 -040068int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040069{
70 int err;
71
Vivien Didelotfad09c72016-06-21 12:28:20 -040072 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040073
Vivien Didelotfad09c72016-06-21 12:28:20 -040074 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040075 if (err)
76 return err;
77
Vivien Didelotfad09c72016-06-21 12:28:20 -040078 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040079 addr, reg, val);
80
81 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000082}
83
Andrew Lunn10fa5bf2017-05-26 01:03:20 +020084struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
Andrew Lunna3c53be52017-01-24 14:53:50 +010085{
86 struct mv88e6xxx_mdio_bus *mdio_bus;
87
88 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
89 list);
90 if (!mdio_bus)
91 return NULL;
92
93 return mdio_bus->bus;
94}
95
Andrew Lunndc30c352016-10-16 19:56:49 +020096static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
97{
98 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
99 unsigned int n = d->hwirq;
100
101 chip->g1_irq.masked |= (1 << n);
102}
103
104static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
105{
106 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
107 unsigned int n = d->hwirq;
108
109 chip->g1_irq.masked &= ~(1 << n);
110}
111
Andrew Lunn294d7112018-02-22 22:58:32 +0100112static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200113{
Andrew Lunndc30c352016-10-16 19:56:49 +0200114 unsigned int nhandled = 0;
115 unsigned int sub_irq;
116 unsigned int n;
117 u16 reg;
John David Anglin7c0db242019-02-11 13:40:21 -0500118 u16 ctl1;
Andrew Lunndc30c352016-10-16 19:56:49 +0200119 int err;
120
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000121 mv88e6xxx_reg_lock(chip);
Vivien Didelot82466922017-06-15 12:13:59 -0400122 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000123 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200124
125 if (err)
126 goto out;
127
John David Anglin7c0db242019-02-11 13:40:21 -0500128 do {
129 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
130 if (reg & (1 << n)) {
131 sub_irq = irq_find_mapping(chip->g1_irq.domain,
132 n);
133 handle_nested_irq(sub_irq);
134 ++nhandled;
135 }
Andrew Lunndc30c352016-10-16 19:56:49 +0200136 }
John David Anglin7c0db242019-02-11 13:40:21 -0500137
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000138 mv88e6xxx_reg_lock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
140 if (err)
141 goto unlock;
142 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
143unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000144 mv88e6xxx_reg_unlock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500145 if (err)
146 goto out;
147 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
148 } while (reg & ctl1);
149
Andrew Lunndc30c352016-10-16 19:56:49 +0200150out:
151 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
152}
153
Andrew Lunn294d7112018-02-22 22:58:32 +0100154static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
155{
156 struct mv88e6xxx_chip *chip = dev_id;
157
158 return mv88e6xxx_g1_irq_thread_work(chip);
159}
160
Andrew Lunndc30c352016-10-16 19:56:49 +0200161static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
162{
163 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
164
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000165 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200166}
167
168static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
169{
170 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
171 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
172 u16 reg;
173 int err;
174
Vivien Didelotd77f4322017-06-15 12:14:03 -0400175 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200176 if (err)
177 goto out;
178
179 reg &= ~mask;
180 reg |= (~chip->g1_irq.masked & mask);
181
Vivien Didelotd77f4322017-06-15 12:14:03 -0400182 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200183 if (err)
184 goto out;
185
186out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000187 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200188}
189
Bhumika Goyal6eb15e22017-08-19 16:25:52 +0530190static const struct irq_chip mv88e6xxx_g1_irq_chip = {
Andrew Lunndc30c352016-10-16 19:56:49 +0200191 .name = "mv88e6xxx-g1",
192 .irq_mask = mv88e6xxx_g1_irq_mask,
193 .irq_unmask = mv88e6xxx_g1_irq_unmask,
194 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
195 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
196};
197
198static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
199 unsigned int irq,
200 irq_hw_number_t hwirq)
201{
202 struct mv88e6xxx_chip *chip = d->host_data;
203
204 irq_set_chip_data(irq, d->host_data);
205 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
206 irq_set_noprobe(irq);
207
208 return 0;
209}
210
211static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
212 .map = mv88e6xxx_g1_irq_domain_map,
213 .xlate = irq_domain_xlate_twocell,
214};
215
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200216/* To be called with reg_lock held */
Andrew Lunn294d7112018-02-22 22:58:32 +0100217static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200218{
219 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100220 u16 mask;
221
Vivien Didelotd77f4322017-06-15 12:14:03 -0400222 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100223 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400224 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3460a572016-11-20 20:14:16 +0100225
Andreas Färber5edef2f2016-11-27 23:26:28 +0100226 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100227 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200228 irq_dispose_mapping(virq);
229 }
230
Andrew Lunna3db3d32016-11-20 20:14:14 +0100231 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200232}
233
Andrew Lunn294d7112018-02-22 22:58:32 +0100234static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
235{
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200236 /*
237 * free_irq must be called without reg_lock taken because the irq
238 * handler takes this lock, too.
239 */
Andrew Lunn294d7112018-02-22 22:58:32 +0100240 free_irq(chip->irq, chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200241
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000242 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200243 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000244 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100245}
246
247static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200248{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100249 int err, irq, virq;
250 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200251
252 chip->g1_irq.nirqs = chip->info->g1_irqs;
253 chip->g1_irq.domain = irq_domain_add_simple(
254 NULL, chip->g1_irq.nirqs, 0,
255 &mv88e6xxx_g1_irq_domain_ops, chip);
256 if (!chip->g1_irq.domain)
257 return -ENOMEM;
258
259 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
260 irq_create_mapping(chip->g1_irq.domain, irq);
261
262 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
263 chip->g1_irq.masked = ~0;
264
Vivien Didelotd77f4322017-06-15 12:14:03 -0400265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200266 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100267 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200268
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200270
Vivien Didelotd77f4322017-06-15 12:14:03 -0400271 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200272 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100273 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200274
275 /* Reading the interrupt status clears (most of) them */
Vivien Didelot82466922017-06-15 12:13:59 -0400276 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200277 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100278 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200279
Andrew Lunndc30c352016-10-16 19:56:49 +0200280 return 0;
281
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100282out_disable:
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100283 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400284 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100285
286out_mapping:
287 for (irq = 0; irq < 16; irq++) {
288 virq = irq_find_mapping(chip->g1_irq.domain, irq);
289 irq_dispose_mapping(virq);
290 }
291
292 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200293
294 return err;
295}
296
Andrew Lunn294d7112018-02-22 22:58:32 +0100297static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
298{
Andrew Lunnf6d97582019-02-23 17:43:56 +0100299 static struct lock_class_key lock_key;
300 static struct lock_class_key request_key;
Andrew Lunn294d7112018-02-22 22:58:32 +0100301 int err;
302
303 err = mv88e6xxx_g1_irq_setup_common(chip);
304 if (err)
305 return err;
306
Andrew Lunnf6d97582019-02-23 17:43:56 +0100307 /* These lock classes tells lockdep that global 1 irqs are in
308 * a different category than their parent GPIO, so it won't
309 * report false recursion.
310 */
311 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
312
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000313 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100314 err = request_threaded_irq(chip->irq, NULL,
315 mv88e6xxx_g1_irq_thread_fn,
Marek Behún03403762018-08-30 02:13:50 +0200316 IRQF_ONESHOT | IRQF_SHARED,
Andrew Lunn294d7112018-02-22 22:58:32 +0100317 dev_name(chip->dev), chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000318 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100319 if (err)
320 mv88e6xxx_g1_irq_free_common(chip);
321
322 return err;
323}
324
325static void mv88e6xxx_irq_poll(struct kthread_work *work)
326{
327 struct mv88e6xxx_chip *chip = container_of(work,
328 struct mv88e6xxx_chip,
329 irq_poll_work.work);
330 mv88e6xxx_g1_irq_thread_work(chip);
331
332 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
333 msecs_to_jiffies(100));
334}
335
336static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
337{
338 int err;
339
340 err = mv88e6xxx_g1_irq_setup_common(chip);
341 if (err)
342 return err;
343
344 kthread_init_delayed_work(&chip->irq_poll_work,
345 mv88e6xxx_irq_poll);
346
Florian Fainelli3f8b8692019-02-21 20:09:27 -0800347 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
Andrew Lunn294d7112018-02-22 22:58:32 +0100348 if (IS_ERR(chip->kworker))
349 return PTR_ERR(chip->kworker);
350
351 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
352 msecs_to_jiffies(100));
353
354 return 0;
355}
356
357static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
358{
359 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
360 kthread_destroy_worker(chip->kworker);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200361
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000362 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200363 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000364 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100365}
366
Vivien Didelotec561272016-09-02 14:45:33 -0400367int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
Vivien Didelot2d79af62016-08-15 17:18:57 -0400368{
Andrew Lunn6441e6692016-08-19 00:01:55 +0200369 int i;
Vivien Didelot2d79af62016-08-15 17:18:57 -0400370
Andrew Lunn6441e6692016-08-19 00:01:55 +0200371 for (i = 0; i < 16; i++) {
Vivien Didelot2d79af62016-08-15 17:18:57 -0400372 u16 val;
373 int err;
374
375 err = mv88e6xxx_read(chip, addr, reg, &val);
376 if (err)
377 return err;
378
379 if (!(val & mask))
380 return 0;
381
382 usleep_range(1000, 2000);
383 }
384
Andrew Lunn30853552016-08-19 00:01:57 +0200385 dev_err(chip->dev, "Timeout while waiting for switch\n");
Vivien Didelot2d79af62016-08-15 17:18:57 -0400386 return -ETIMEDOUT;
387}
388
Vivien Didelotf22ab642016-07-18 20:45:31 -0400389/* Indirect write to single pointer-data register with an Update bit */
Vivien Didelotec561272016-09-02 14:45:33 -0400390int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
Vivien Didelotf22ab642016-07-18 20:45:31 -0400391{
392 u16 val;
Andrew Lunn0f02b4f2016-08-19 00:01:56 +0200393 int err;
Vivien Didelotf22ab642016-07-18 20:45:31 -0400394
395 /* Wait until the previous operation is completed */
Andrew Lunn0f02b4f2016-08-19 00:01:56 +0200396 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
397 if (err)
398 return err;
Vivien Didelotf22ab642016-07-18 20:45:31 -0400399
400 /* Set the Update bit to trigger a write operation */
401 val = BIT(15) | update;
402
403 return mv88e6xxx_write(chip, addr, reg, val);
404}
405
Heiner Kallweit72d8b4f2019-03-01 20:41:00 +0100406int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
407 int speed, int duplex, int pause,
408 phy_interface_t mode)
Vivien Didelotd78343d2016-11-04 03:23:36 +0100409{
Andrew Lunna26deec2019-04-18 03:11:39 +0200410 struct phylink_link_state state;
Vivien Didelotd78343d2016-11-04 03:23:36 +0100411 int err;
412
413 if (!chip->info->ops->port_set_link)
414 return 0;
415
Andrew Lunna26deec2019-04-18 03:11:39 +0200416 if (!chip->info->ops->port_link_state)
417 return 0;
418
419 err = chip->info->ops->port_link_state(chip, port, &state);
420 if (err)
421 return err;
422
423 /* Has anything actually changed? We don't expect the
424 * interface mode to change without one of the other
425 * parameters also changing
426 */
427 if (state.link == link &&
428 state.speed == speed &&
429 state.duplex == duplex)
430 return 0;
431
Vivien Didelotd78343d2016-11-04 03:23:36 +0100432 /* Port's MAC control must not be changed unless the link is down */
Hubert Feurstein43c8e0a2019-07-30 12:11:42 +0200433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100434 if (err)
435 return err;
436
437 if (chip->info->ops->port_set_speed) {
438 err = chip->info->ops->port_set_speed(chip, port, speed);
439 if (err && err != -EOPNOTSUPP)
440 goto restore_link;
441 }
442
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
444 mode = chip->info->ops->port_max_speed_mode(port);
445
Andrew Lunn54186b92018-08-09 15:38:37 +0200446 if (chip->info->ops->port_set_pause) {
447 err = chip->info->ops->port_set_pause(chip, port, pause);
448 if (err)
449 goto restore_link;
450 }
451
Vivien Didelotd78343d2016-11-04 03:23:36 +0100452 if (chip->info->ops->port_set_duplex) {
453 err = chip->info->ops->port_set_duplex(chip, port, duplex);
454 if (err && err != -EOPNOTSUPP)
455 goto restore_link;
456 }
457
458 if (chip->info->ops->port_set_rgmii_delay) {
459 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
460 if (err && err != -EOPNOTSUPP)
461 goto restore_link;
462 }
463
Andrew Lunnf39908d2017-02-04 20:02:50 +0100464 if (chip->info->ops->port_set_cmode) {
465 err = chip->info->ops->port_set_cmode(chip, port, mode);
466 if (err && err != -EOPNOTSUPP)
467 goto restore_link;
468 }
469
Vivien Didelotd78343d2016-11-04 03:23:36 +0100470 err = 0;
471restore_link:
472 if (chip->info->ops->port_set_link(chip, port, link))
Vivien Didelot774439e52017-06-08 18:34:08 -0400473 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100474
475 return err;
476}
477
Marek Vasutd700ec42018-09-12 00:15:24 +0200478static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
479{
480 struct mv88e6xxx_chip *chip = ds->priv;
481
482 return port < chip->info->num_internal_phys;
483}
484
Andrew Lunndea87022015-08-31 15:56:47 +0200485/* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
488 */
Vivien Didelotf81ec902016-05-09 13:22:58 -0400489static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
Andrew Lunndea87022015-08-31 15:56:47 +0200491{
Vivien Didelot04bed142016-08-31 18:06:13 -0400492 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200493 int err;
Andrew Lunndea87022015-08-31 15:56:47 +0200494
Marek Vasutd700ec42018-09-12 00:15:24 +0200495 if (!phy_is_pseudo_fixed_link(phydev) &&
496 mv88e6xxx_phy_is_internal(ds, port))
Andrew Lunndea87022015-08-31 15:56:47 +0200497 return;
498
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000499 mv88e6xxx_reg_lock(chip);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100500 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
Andrew Lunn54186b92018-08-09 15:38:37 +0200501 phydev->duplex, phydev->pause,
502 phydev->interface);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000503 mv88e6xxx_reg_unlock(chip);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100504
505 if (err && err != -EOPNOTSUPP)
Vivien Didelot774439e52017-06-08 18:34:08 -0400506 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
Andrew Lunndea87022015-08-31 15:56:47 +0200507}
508
Russell King6c422e32018-08-09 15:38:39 +0200509static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
510 unsigned long *mask,
511 struct phylink_link_state *state)
512{
513 if (!phy_interface_mode_is_8023z(state->interface)) {
514 /* 10M and 100M are only supported in non-802.3z mode */
515 phylink_set(mask, 10baseT_Half);
516 phylink_set(mask, 10baseT_Full);
517 phylink_set(mask, 100baseT_Half);
518 phylink_set(mask, 100baseT_Full);
519 }
520}
521
522static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
523 unsigned long *mask,
524 struct phylink_link_state *state)
525{
526 /* FIXME: if the port is in 1000Base-X mode, then it only supports
527 * 1000M FD speeds. In this case, CMODE will indicate 5.
528 */
529 phylink_set(mask, 1000baseT_Full);
530 phylink_set(mask, 1000baseX_Full);
531
532 mv88e6065_phylink_validate(chip, port, mask, state);
533}
534
Marek Behúne3af71a2019-02-25 12:39:55 +0100535static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
536 unsigned long *mask,
537 struct phylink_link_state *state)
538{
539 if (port >= 5)
540 phylink_set(mask, 2500baseX_Full);
541
542 /* No ethtool bits for 200Mbps */
543 phylink_set(mask, 1000baseT_Full);
544 phylink_set(mask, 1000baseX_Full);
545
546 mv88e6065_phylink_validate(chip, port, mask, state);
547}
548
Russell King6c422e32018-08-09 15:38:39 +0200549static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
550 unsigned long *mask,
551 struct phylink_link_state *state)
552{
553 /* No ethtool bits for 200Mbps */
554 phylink_set(mask, 1000baseT_Full);
555 phylink_set(mask, 1000baseX_Full);
556
557 mv88e6065_phylink_validate(chip, port, mask, state);
558}
559
560static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
561 unsigned long *mask,
562 struct phylink_link_state *state)
563{
Andrew Lunnec260162019-02-08 22:25:44 +0100564 if (port >= 9) {
Russell King6c422e32018-08-09 15:38:39 +0200565 phylink_set(mask, 2500baseX_Full);
Andrew Lunnec260162019-02-08 22:25:44 +0100566 phylink_set(mask, 2500baseT_Full);
567 }
Russell King6c422e32018-08-09 15:38:39 +0200568
569 /* No ethtool bits for 200Mbps */
570 phylink_set(mask, 1000baseT_Full);
571 phylink_set(mask, 1000baseX_Full);
572
573 mv88e6065_phylink_validate(chip, port, mask, state);
574}
575
576static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
577 unsigned long *mask,
578 struct phylink_link_state *state)
579{
580 if (port >= 9) {
581 phylink_set(mask, 10000baseT_Full);
582 phylink_set(mask, 10000baseKR_Full);
583 }
584
585 mv88e6390_phylink_validate(chip, port, mask, state);
586}
587
Russell Kingc9a23562018-05-10 13:17:35 -0700588static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
589 unsigned long *supported,
590 struct phylink_link_state *state)
591{
Russell King6c422e32018-08-09 15:38:39 +0200592 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
593 struct mv88e6xxx_chip *chip = ds->priv;
594
595 /* Allow all the expected bits */
596 phylink_set(mask, Autoneg);
597 phylink_set(mask, Pause);
598 phylink_set_port_modes(mask);
599
600 if (chip->info->ops->phylink_validate)
601 chip->info->ops->phylink_validate(chip, port, mask, state);
602
603 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
604 bitmap_and(state->advertising, state->advertising, mask,
605 __ETHTOOL_LINK_MODE_MASK_NBITS);
606
607 /* We can only operate at 2500BaseX or 1000BaseX. If requested
608 * to advertise both, only report advertising at 2500BaseX.
609 */
610 phylink_helper_basex_speed(state);
Russell Kingc9a23562018-05-10 13:17:35 -0700611}
612
613static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
614 struct phylink_link_state *state)
615{
616 struct mv88e6xxx_chip *chip = ds->priv;
617 int err;
618
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000619 mv88e6xxx_reg_lock(chip);
Russell King6c422e32018-08-09 15:38:39 +0200620 if (chip->info->ops->port_link_state)
621 err = chip->info->ops->port_link_state(chip, port, state);
622 else
623 err = -EOPNOTSUPP;
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000624 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700625
626 return err;
627}
628
629static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
630 unsigned int mode,
631 const struct phylink_link_state *state)
632{
633 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn54186b92018-08-09 15:38:37 +0200634 int speed, duplex, link, pause, err;
Russell Kingc9a23562018-05-10 13:17:35 -0700635
Marek Vasutd700ec42018-09-12 00:15:24 +0200636 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
Russell Kingc9a23562018-05-10 13:17:35 -0700637 return;
638
639 if (mode == MLO_AN_FIXED) {
640 link = LINK_FORCED_UP;
641 speed = state->speed;
642 duplex = state->duplex;
Marek Vasutd700ec42018-09-12 00:15:24 +0200643 } else if (!mv88e6xxx_phy_is_internal(ds, port)) {
644 link = state->link;
645 speed = state->speed;
646 duplex = state->duplex;
Russell Kingc9a23562018-05-10 13:17:35 -0700647 } else {
648 speed = SPEED_UNFORCED;
649 duplex = DUPLEX_UNFORCED;
650 link = LINK_UNFORCED;
651 }
Andrew Lunn54186b92018-08-09 15:38:37 +0200652 pause = !!phylink_test(state->advertising, Pause);
Russell Kingc9a23562018-05-10 13:17:35 -0700653
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000654 mv88e6xxx_reg_lock(chip);
Andrew Lunn54186b92018-08-09 15:38:37 +0200655 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
Russell Kingc9a23562018-05-10 13:17:35 -0700656 state->interface);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000657 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700658
659 if (err && err != -EOPNOTSUPP)
660 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
661}
662
663static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
664{
665 struct mv88e6xxx_chip *chip = ds->priv;
666 int err;
667
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000668 mv88e6xxx_reg_lock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700669 err = chip->info->ops->port_set_link(chip, port, link);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000670 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700671
672 if (err)
673 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
674}
675
676static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
677 unsigned int mode,
678 phy_interface_t interface)
679{
680 if (mode == MLO_AN_FIXED)
681 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
682}
683
684static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
685 unsigned int mode, phy_interface_t interface,
686 struct phy_device *phydev)
687{
688 if (mode == MLO_AN_FIXED)
689 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
690}
691
Andrew Lunna605a0f2016-11-21 23:26:58 +0100692static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000693{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100694 if (!chip->info->ops->stats_snapshot)
695 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000696
Andrew Lunna605a0f2016-11-21 23:26:58 +0100697 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000698}
699
Andrew Lunne413e7e2015-04-02 04:06:38 +0200700static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100701 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
702 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
703 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
704 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
705 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
706 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
707 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
708 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
709 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
710 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
711 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
712 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
713 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
714 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
715 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
716 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
717 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
718 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
719 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
720 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
721 { "single", 4, 0x14, STATS_TYPE_BANK0, },
722 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
723 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
724 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
725 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
726 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
727 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
728 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
729 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
730 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
731 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
732 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
733 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
734 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
735 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
736 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
737 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
738 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
739 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
740 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
741 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
742 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
743 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
744 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
745 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
746 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
747 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
748 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
749 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
750 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
751 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
752 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
753 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
754 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
755 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
756 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
757 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
758 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
759 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200760};
761
Vivien Didelotfad09c72016-06-21 12:28:20 -0400762static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100763 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100764 int port, u16 bank1_select,
765 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200766{
Andrew Lunn80c46272015-06-20 18:42:30 +0200767 u32 low;
768 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100769 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200770 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200771 u64 value;
772
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100773 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100774 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200775 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
776 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800777 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200778
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200779 low = reg;
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100780 if (s->size == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200781 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
782 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800783 return U64_MAX;
Rasmus Villemoes84b3fd12019-05-29 07:02:11 +0000784 low |= ((u32)reg) << 16;
Andrew Lunn80c46272015-06-20 18:42:30 +0200785 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100786 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100787 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100788 reg = bank1_select;
Andrew Lunndfafe442016-11-21 23:27:02 +0100789 /* fall through */
790 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100791 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100792 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100793 if (s->size == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100794 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Gustavo A. R. Silva9fc3e4d2017-05-11 22:11:29 -0500795 break;
796 default:
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800797 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200798 }
Andrew Lunn6e46e2d2019-02-28 18:14:03 +0100799 value = (((u64)high) << 32) | low;
Andrew Lunn80c46272015-06-20 18:42:30 +0200800 return value;
801}
802
Andrew Lunn436fe172018-03-01 02:02:29 +0100803static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
804 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100805{
806 struct mv88e6xxx_hw_stat *stat;
807 int i, j;
808
809 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
810 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100811 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100812 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
813 ETH_GSTRING_LEN);
814 j++;
815 }
816 }
Andrew Lunn436fe172018-03-01 02:02:29 +0100817
818 return j;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100819}
820
Andrew Lunn436fe172018-03-01 02:02:29 +0100821static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
822 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100823{
Andrew Lunn436fe172018-03-01 02:02:29 +0100824 return mv88e6xxx_stats_get_strings(chip, data,
825 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
Andrew Lunndfafe442016-11-21 23:27:02 +0100826}
827
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000828static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
829 uint8_t *data)
830{
831 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
832}
833
Andrew Lunn436fe172018-03-01 02:02:29 +0100834static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
835 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100836{
Andrew Lunn436fe172018-03-01 02:02:29 +0100837 return mv88e6xxx_stats_get_strings(chip, data,
838 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
Andrew Lunndfafe442016-11-21 23:27:02 +0100839}
840
Andrew Lunn65f60e42018-03-28 23:50:28 +0200841static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
842 "atu_member_violation",
843 "atu_miss_violation",
844 "atu_full_violation",
845 "vtu_member_violation",
846 "vtu_miss_violation",
847};
848
849static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
850{
851 unsigned int i;
852
853 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
854 strlcpy(data + i * ETH_GSTRING_LEN,
855 mv88e6xxx_atu_vtu_stats_strings[i],
856 ETH_GSTRING_LEN);
857}
858
Andrew Lunndfafe442016-11-21 23:27:02 +0100859static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
Florian Fainelli89f09042018-04-25 12:12:50 -0700860 u32 stringset, uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100861{
Vivien Didelot04bed142016-08-31 18:06:13 -0400862 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +0100863 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100864
Florian Fainelli89f09042018-04-25 12:12:50 -0700865 if (stringset != ETH_SS_STATS)
866 return;
867
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000868 mv88e6xxx_reg_lock(chip);
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100869
Andrew Lunndfafe442016-11-21 23:27:02 +0100870 if (chip->info->ops->stats_get_strings)
Andrew Lunn436fe172018-03-01 02:02:29 +0100871 count = chip->info->ops->stats_get_strings(chip, data);
872
873 if (chip->info->ops->serdes_get_strings) {
874 data += count * ETH_GSTRING_LEN;
Andrew Lunn65f60e42018-03-28 23:50:28 +0200875 count = chip->info->ops->serdes_get_strings(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +0100876 }
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100877
Andrew Lunn65f60e42018-03-28 23:50:28 +0200878 data += count * ETH_GSTRING_LEN;
879 mv88e6xxx_atu_vtu_get_strings(data);
880
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000881 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +0100882}
883
884static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
885 int types)
886{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100887 struct mv88e6xxx_hw_stat *stat;
888 int i, j;
889
890 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
891 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100892 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100893 j++;
894 }
895 return j;
896}
897
Andrew Lunndfafe442016-11-21 23:27:02 +0100898static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
899{
900 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
901 STATS_TYPE_PORT);
902}
903
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000904static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
905{
906 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
907}
908
Andrew Lunndfafe442016-11-21 23:27:02 +0100909static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
910{
911 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
912 STATS_TYPE_BANK1);
913}
914
Florian Fainelli89f09042018-04-25 12:12:50 -0700915static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
Andrew Lunndfafe442016-11-21 23:27:02 +0100916{
917 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +0100918 int serdes_count = 0;
919 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100920
Florian Fainelli89f09042018-04-25 12:12:50 -0700921 if (sset != ETH_SS_STATS)
922 return 0;
923
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000924 mv88e6xxx_reg_lock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +0100925 if (chip->info->ops->stats_get_sset_count)
Andrew Lunn436fe172018-03-01 02:02:29 +0100926 count = chip->info->ops->stats_get_sset_count(chip);
927 if (count < 0)
928 goto out;
929
930 if (chip->info->ops->serdes_get_sset_count)
931 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
932 port);
Andrew Lunn65f60e42018-03-28 23:50:28 +0200933 if (serdes_count < 0) {
Andrew Lunn436fe172018-03-01 02:02:29 +0100934 count = serdes_count;
Andrew Lunn65f60e42018-03-28 23:50:28 +0200935 goto out;
936 }
937 count += serdes_count;
938 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
939
Andrew Lunn436fe172018-03-01 02:02:29 +0100940out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000941 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +0100942
Andrew Lunn436fe172018-03-01 02:02:29 +0100943 return count;
Andrew Lunndfafe442016-11-21 23:27:02 +0100944}
945
Andrew Lunn436fe172018-03-01 02:02:29 +0100946static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
947 uint64_t *data, int types,
948 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +0100949{
950 struct mv88e6xxx_hw_stat *stat;
951 int i, j;
952
953 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
954 stat = &mv88e6xxx_hw_stats[i];
955 if (stat->type & types) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000956 mv88e6xxx_reg_lock(chip);
Andrew Lunne0d8b612016-11-21 23:27:04 +0100957 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
958 bank1_select,
959 histogram);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000960 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +0100961
Andrew Lunn052f9472016-11-21 23:27:03 +0100962 j++;
963 }
964 }
Andrew Lunn436fe172018-03-01 02:02:29 +0100965 return j;
Andrew Lunn052f9472016-11-21 23:27:03 +0100966}
967
Andrew Lunn436fe172018-03-01 02:02:29 +0100968static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
969 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +0100970{
971 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100972 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
Vivien Didelot57d1ef32017-06-15 12:14:05 -0400973 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +0100974}
975
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000976static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
977 uint64_t *data)
978{
979 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
980 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
981}
982
Andrew Lunn436fe172018-03-01 02:02:29 +0100983static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
984 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +0100985{
986 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100987 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -0400988 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
989 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunne0d8b612016-11-21 23:27:04 +0100990}
991
Andrew Lunn436fe172018-03-01 02:02:29 +0100992static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
993 uint64_t *data)
Andrew Lunne0d8b612016-11-21 23:27:04 +0100994{
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -0400997 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
998 0);
Andrew Lunn052f9472016-11-21 23:27:03 +0100999}
1000
Andrew Lunn65f60e42018-03-28 23:50:28 +02001001static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1002 uint64_t *data)
1003{
1004 *data++ = chip->ports[port].atu_member_violation;
1005 *data++ = chip->ports[port].atu_miss_violation;
1006 *data++ = chip->ports[port].atu_full_violation;
1007 *data++ = chip->ports[port].vtu_member_violation;
1008 *data++ = chip->ports[port].vtu_miss_violation;
1009}
1010
Andrew Lunn052f9472016-11-21 23:27:03 +01001011static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1012 uint64_t *data)
1013{
Andrew Lunn436fe172018-03-01 02:02:29 +01001014 int count = 0;
1015
Andrew Lunn052f9472016-11-21 23:27:03 +01001016 if (chip->info->ops->stats_get_stats)
Andrew Lunn436fe172018-03-01 02:02:29 +01001017 count = chip->info->ops->stats_get_stats(chip, port, data);
1018
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001019 mv88e6xxx_reg_lock(chip);
Andrew Lunn436fe172018-03-01 02:02:29 +01001020 if (chip->info->ops->serdes_get_stats) {
1021 data += count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001022 count = chip->info->ops->serdes_get_stats(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001023 }
Andrew Lunn65f60e42018-03-28 23:50:28 +02001024 data += count;
1025 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001026 mv88e6xxx_reg_unlock(chip);
Andrew Lunn052f9472016-11-21 23:27:03 +01001027}
1028
Vivien Didelotf81ec902016-05-09 13:22:58 -04001029static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1030 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001031{
Vivien Didelot04bed142016-08-31 18:06:13 -04001032 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001033 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001034
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001035 mv88e6xxx_reg_lock(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001036
Andrew Lunna605a0f2016-11-21 23:26:58 +01001037 ret = mv88e6xxx_stats_snapshot(chip, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001038 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001039
1040 if (ret < 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001041 return;
Andrew Lunn052f9472016-11-21 23:27:03 +01001042
1043 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001044
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001045}
Ben Hutchings98e67302011-11-25 14:36:19 +00001046
Vivien Didelotf81ec902016-05-09 13:22:58 -04001047static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001048{
1049 return 32 * sizeof(u16);
1050}
1051
Vivien Didelotf81ec902016-05-09 13:22:58 -04001052static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1053 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001054{
Vivien Didelot04bed142016-08-31 18:06:13 -04001055 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001056 int err;
1057 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001058 u16 *p = _p;
1059 int i;
1060
Vivien Didelota5f39322018-12-17 16:05:21 -05001061 regs->version = chip->info->prod_num;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001062
1063 memset(p, 0xff, 32 * sizeof(u16));
1064
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001065 mv88e6xxx_reg_lock(chip);
Vivien Didelot23062512016-05-09 13:22:45 -04001066
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001067 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001068
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001069 err = mv88e6xxx_port_read(chip, port, i, &reg);
1070 if (!err)
1071 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001072 }
Vivien Didelot23062512016-05-09 13:22:45 -04001073
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001074 mv88e6xxx_reg_unlock(chip);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001075}
1076
Vivien Didelot08f50062017-08-01 16:32:41 -04001077static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1078 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001079{
Vivien Didelot5480db62017-08-01 16:32:40 -04001080 /* Nothing to do on the port's MAC */
1081 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001082}
1083
Vivien Didelot08f50062017-08-01 16:32:41 -04001084static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1085 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001086{
Vivien Didelot5480db62017-08-01 16:32:40 -04001087 /* Nothing to do on the port's MAC */
1088 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001089}
1090
Vivien Didelote5887a22017-03-30 17:37:11 -04001091static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001092{
Vivien Didelote5887a22017-03-30 17:37:11 -04001093 struct dsa_switch *ds = NULL;
1094 struct net_device *br;
1095 u16 pvlan;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001096 int i;
1097
Vivien Didelote5887a22017-03-30 17:37:11 -04001098 if (dev < DSA_MAX_SWITCHES)
1099 ds = chip->ds->dst->ds[dev];
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001100
Vivien Didelote5887a22017-03-30 17:37:11 -04001101 /* Prevent frames from unknown switch or port */
1102 if (!ds || port >= ds->num_ports)
1103 return 0;
1104
1105 /* Frames from DSA links and CPU ports can egress any local port */
1106 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1107 return mv88e6xxx_port_mask(chip);
1108
1109 br = ds->ports[port].bridge_dev;
1110 pvlan = 0;
1111
1112 /* Frames from user ports can egress any local DSA links and CPU ports,
1113 * as well as any local member of their bridge group.
1114 */
1115 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1116 if (dsa_is_cpu_port(chip->ds, i) ||
1117 dsa_is_dsa_port(chip->ds, i) ||
Vivien Didelotc8652c82017-10-16 11:12:19 -04001118 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
Vivien Didelote5887a22017-03-30 17:37:11 -04001119 pvlan |= BIT(i);
1120
1121 return pvlan;
1122}
1123
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001124static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
Vivien Didelote5887a22017-03-30 17:37:11 -04001125{
1126 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001127
1128 /* prevent frames from going back out of the port they came in on */
1129 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001130
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001131 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001132}
1133
Vivien Didelotf81ec902016-05-09 13:22:58 -04001134static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1135 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001136{
Vivien Didelot04bed142016-08-31 18:06:13 -04001137 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot553eb542016-05-13 20:38:23 -04001138 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001139
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001140 mv88e6xxx_reg_lock(chip);
Vivien Didelotf894c292017-06-08 18:34:10 -04001141 err = mv88e6xxx_port_set_state(chip, port, state);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001142 mv88e6xxx_reg_unlock(chip);
Vivien Didelot553eb542016-05-13 20:38:23 -04001143
1144 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001145 dev_err(ds->dev, "p%d: failed to update state\n", port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001146}
1147
Vivien Didelot93e18d62018-05-11 17:16:35 -04001148static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1149{
1150 int err;
1151
1152 if (chip->info->ops->ieee_pri_map) {
1153 err = chip->info->ops->ieee_pri_map(chip);
1154 if (err)
1155 return err;
1156 }
1157
1158 if (chip->info->ops->ip_pri_map) {
1159 err = chip->info->ops->ip_pri_map(chip);
1160 if (err)
1161 return err;
1162 }
1163
1164 return 0;
1165}
1166
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001167static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1168{
1169 int target, port;
1170 int err;
1171
1172 if (!chip->info->global2_addr)
1173 return 0;
1174
1175 /* Initialize the routing port to the 32 possible target devices */
1176 for (target = 0; target < 32; target++) {
1177 port = 0x1f;
1178 if (target < DSA_MAX_SWITCHES)
1179 if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1180 port = chip->ds->rtable[target];
1181
1182 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1183 if (err)
1184 return err;
1185 }
1186
Vivien Didelot02317e62018-05-09 11:38:49 -04001187 if (chip->info->ops->set_cascade_port) {
1188 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1189 err = chip->info->ops->set_cascade_port(chip, port);
1190 if (err)
1191 return err;
1192 }
1193
Vivien Didelot23c98912018-05-09 11:38:50 -04001194 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1195 if (err)
1196 return err;
1197
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001198 return 0;
1199}
1200
Vivien Didelotb28f8722018-04-26 21:56:44 -04001201static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1202{
1203 /* Clear all trunk masks and mapping */
1204 if (chip->info->global2_addr)
1205 return mv88e6xxx_g2_trunk_clear(chip);
1206
1207 return 0;
1208}
1209
Vivien Didelot9e5baf92018-05-09 11:38:51 -04001210static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1211{
1212 if (chip->info->ops->rmu_disable)
1213 return chip->info->ops->rmu_disable(chip);
1214
1215 return 0;
1216}
1217
Vivien Didelot9e907d72017-07-17 13:03:43 -04001218static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1219{
1220 if (chip->info->ops->pot_clear)
1221 return chip->info->ops->pot_clear(chip);
1222
1223 return 0;
1224}
1225
Vivien Didelot51c901a2017-07-17 13:03:41 -04001226static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1227{
1228 if (chip->info->ops->mgmt_rsvd2cpu)
1229 return chip->info->ops->mgmt_rsvd2cpu(chip);
1230
1231 return 0;
1232}
1233
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001234static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1235{
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001236 int err;
1237
Vivien Didelotdaefc942017-03-11 16:12:54 -05001238 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1239 if (err)
1240 return err;
1241
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001242 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1243 if (err)
1244 return err;
1245
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001246 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1247}
1248
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04001249static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1250{
1251 int port;
1252 int err;
1253
1254 if (!chip->info->ops->irl_init_all)
1255 return 0;
1256
1257 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1258 /* Disable ingress rate limiting by resetting all per port
1259 * ingress rate limit resources to their initial state.
1260 */
1261 err = chip->info->ops->irl_init_all(chip, port);
1262 if (err)
1263 return err;
1264 }
1265
1266 return 0;
1267}
1268
Vivien Didelot04a69a12017-10-13 14:18:05 -04001269static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1270{
1271 if (chip->info->ops->set_switch_mac) {
1272 u8 addr[ETH_ALEN];
1273
1274 eth_random_addr(addr);
1275
1276 return chip->info->ops->set_switch_mac(chip, addr);
1277 }
1278
1279 return 0;
1280}
1281
Vivien Didelot17a15942017-03-30 17:37:09 -04001282static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1283{
1284 u16 pvlan = 0;
1285
1286 if (!mv88e6xxx_has_pvt(chip))
1287 return -EOPNOTSUPP;
1288
1289 /* Skip the local source device, which uses in-chip port VLAN */
1290 if (dev != chip->ds->index)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001291 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
Vivien Didelot17a15942017-03-30 17:37:09 -04001292
1293 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1294}
1295
Vivien Didelot81228992017-03-30 17:37:08 -04001296static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1297{
Vivien Didelot17a15942017-03-30 17:37:09 -04001298 int dev, port;
1299 int err;
1300
Vivien Didelot81228992017-03-30 17:37:08 -04001301 if (!mv88e6xxx_has_pvt(chip))
1302 return 0;
1303
1304 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1305 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1306 */
Vivien Didelot17a15942017-03-30 17:37:09 -04001307 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1308 if (err)
1309 return err;
1310
1311 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1312 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1313 err = mv88e6xxx_pvt_map(chip, dev, port);
1314 if (err)
1315 return err;
1316 }
1317 }
1318
1319 return 0;
Vivien Didelot81228992017-03-30 17:37:08 -04001320}
1321
Vivien Didelot749efcb2016-09-22 16:49:24 -04001322static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1323{
1324 struct mv88e6xxx_chip *chip = ds->priv;
1325 int err;
1326
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001327 mv88e6xxx_reg_lock(chip);
Vivien Didelote606ca32017-03-11 16:12:55 -05001328 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001329 mv88e6xxx_reg_unlock(chip);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001330
1331 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001332 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001333}
1334
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001335static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1336{
1337 if (!chip->info->max_vid)
1338 return 0;
1339
1340 return mv88e6xxx_g1_vtu_flush(chip);
1341}
1342
Vivien Didelotf1394b782017-05-01 14:05:22 -04001343static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1344 struct mv88e6xxx_vtu_entry *entry)
1345{
1346 if (!chip->info->ops->vtu_getnext)
1347 return -EOPNOTSUPP;
1348
1349 return chip->info->ops->vtu_getnext(chip, entry);
1350}
1351
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04001352static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1353 struct mv88e6xxx_vtu_entry *entry)
1354{
1355 if (!chip->info->ops->vtu_loadpurge)
1356 return -EOPNOTSUPP;
1357
1358 return chip->info->ops->vtu_loadpurge(chip, entry);
1359}
1360
Vivien Didelotd7f435f2017-03-11 16:12:56 -05001361static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001362{
1363 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001364 struct mv88e6xxx_vtu_entry vlan = {
1365 .vid = chip->info->max_vid,
1366 };
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001367 int i, err;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001368
1369 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1370
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001371 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001372 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotb4e48c52016-11-04 03:23:29 +01001373 err = mv88e6xxx_port_get_fid(chip, i, fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001374 if (err)
1375 return err;
1376
1377 set_bit(*fid, fid_bitmap);
1378 }
1379
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001380 /* Set every FID bit used by the VLAN entries */
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001381 do {
Vivien Didelotf1394b782017-05-01 14:05:22 -04001382 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001383 if (err)
1384 return err;
1385
1386 if (!vlan.valid)
1387 break;
1388
1389 set_bit(vlan.fid, fid_bitmap);
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001390 } while (vlan.vid < chip->info->max_vid);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001391
1392 /* The reset value 0x000 is used to indicate that multiple address
1393 * databases are not needed. Return the next positive available.
1394 */
1395 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001396 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001397 return -ENOSPC;
1398
1399 /* Clear the database */
Vivien Didelotdaefc942017-03-11 16:12:54 -05001400 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001401}
1402
Vivien Didelot567aa592017-05-01 14:05:25 -04001403static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1404 struct mv88e6xxx_vtu_entry *entry, bool new)
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001405{
1406 int err;
1407
1408 if (!vid)
Nikita Yushchenko62394702019-05-31 10:35:14 +03001409 return -EOPNOTSUPP;
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001410
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001411 entry->vid = vid - 1;
1412 entry->valid = false;
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001413
Vivien Didelotf1394b782017-05-01 14:05:22 -04001414 err = mv88e6xxx_vtu_getnext(chip, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001415 if (err)
1416 return err;
1417
Vivien Didelot567aa592017-05-01 14:05:25 -04001418 if (entry->vid == vid && entry->valid)
1419 return 0;
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001420
Vivien Didelot567aa592017-05-01 14:05:25 -04001421 if (new) {
1422 int i;
1423
1424 /* Initialize a fresh VLAN entry */
1425 memset(entry, 0, sizeof(*entry));
1426 entry->valid = true;
1427 entry->vid = vid;
1428
Vivien Didelot553a7682017-06-07 18:12:16 -04001429 /* Exclude all ports */
Vivien Didelot567aa592017-05-01 14:05:25 -04001430 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
Vivien Didelot553a7682017-06-07 18:12:16 -04001431 entry->member[i] =
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001432 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot567aa592017-05-01 14:05:25 -04001433
1434 return mv88e6xxx_atu_new(chip, &entry->fid);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001435 }
1436
Vivien Didelot567aa592017-05-01 14:05:25 -04001437 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1438 return -EOPNOTSUPP;
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001439}
1440
Vivien Didelotda9c3592016-02-12 12:09:40 -05001441static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1442 u16 vid_begin, u16 vid_end)
1443{
Vivien Didelot04bed142016-08-31 18:06:13 -04001444 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001445 struct mv88e6xxx_vtu_entry vlan = {
1446 .vid = vid_begin - 1,
1447 };
Vivien Didelotda9c3592016-02-12 12:09:40 -05001448 int i, err;
1449
Andrew Lunndb06ae412017-09-25 23:32:20 +02001450 /* DSA and CPU ports have to be members of multiple vlans */
1451 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1452 return 0;
1453
Vivien Didelotda9c3592016-02-12 12:09:40 -05001454 if (!vid_begin)
1455 return -EOPNOTSUPP;
1456
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001457 mv88e6xxx_reg_lock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001458
Vivien Didelotda9c3592016-02-12 12:09:40 -05001459 do {
Vivien Didelotf1394b782017-05-01 14:05:22 -04001460 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001461 if (err)
1462 goto unlock;
1463
1464 if (!vlan.valid)
1465 break;
1466
1467 if (vlan.vid > vid_end)
1468 break;
1469
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001470 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotda9c3592016-02-12 12:09:40 -05001471 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1472 continue;
1473
Andrew Lunncd886462017-11-09 22:29:53 +01001474 if (!ds->ports[i].slave)
Andrew Lunn66e28092016-12-11 21:07:19 +01001475 continue;
1476
Vivien Didelotbd00e052017-05-01 14:05:11 -04001477 if (vlan.member[i] ==
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001478 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001479 continue;
1480
Vivien Didelotc8652c82017-10-16 11:12:19 -04001481 if (dsa_to_port(ds, i)->bridge_dev ==
Vivien Didelotfae8a252017-01-27 15:29:42 -05001482 ds->ports[port].bridge_dev)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001483 break; /* same bridge, check next VLAN */
1484
Vivien Didelotc8652c82017-10-16 11:12:19 -04001485 if (!dsa_to_port(ds, i)->bridge_dev)
Andrew Lunn66e28092016-12-11 21:07:19 +01001486 continue;
1487
Andrew Lunn743fcc22017-11-09 22:29:54 +01001488 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1489 port, vlan.vid, i,
Vivien Didelotc8652c82017-10-16 11:12:19 -04001490 netdev_name(dsa_to_port(ds, i)->bridge_dev));
Vivien Didelotda9c3592016-02-12 12:09:40 -05001491 err = -EOPNOTSUPP;
1492 goto unlock;
1493 }
1494 } while (vlan.vid < vid_end);
1495
1496unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001497 mv88e6xxx_reg_unlock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001498
1499 return err;
1500}
1501
Vivien Didelotf81ec902016-05-09 13:22:58 -04001502static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1503 bool vlan_filtering)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001504{
Vivien Didelot04bed142016-08-31 18:06:13 -04001505 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot81c6edb2017-06-12 12:37:41 -04001506 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1507 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001508 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001509
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001510 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001511 return -EOPNOTSUPP;
1512
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001513 mv88e6xxx_reg_lock(chip);
Vivien Didelot385a0992016-11-04 03:23:31 +01001514 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001515 mv88e6xxx_reg_unlock(chip);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001516
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001517 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001518}
1519
Vivien Didelot57d32312016-06-20 13:13:58 -04001520static int
1521mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001522 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001523{
Vivien Didelot04bed142016-08-31 18:06:13 -04001524 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001525 int err;
1526
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001527 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001528 return -EOPNOTSUPP;
1529
Vivien Didelotda9c3592016-02-12 12:09:40 -05001530 /* If the requested port doesn't belong to the same bridge as the VLAN
1531 * members, do not support it (yet) and fallback to software VLAN.
1532 */
1533 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1534 vlan->vid_end);
1535 if (err)
1536 return err;
1537
Vivien Didelot76e398a2015-11-01 12:33:55 -05001538 /* We don't need any dynamic resource from the kernel (yet),
1539 * so skip the prepare phase.
1540 */
1541 return 0;
1542}
1543
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001544static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1545 const unsigned char *addr, u16 vid,
1546 u8 state)
1547{
1548 struct mv88e6xxx_vtu_entry vlan;
1549 struct mv88e6xxx_atu_entry entry;
1550 int err;
1551
1552 /* Null VLAN ID corresponds to the port private database */
1553 if (vid == 0)
1554 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1555 else
1556 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1557 if (err)
1558 return err;
1559
1560 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1561 ether_addr_copy(entry.mac, addr);
1562 eth_addr_dec(entry.mac);
1563
1564 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1565 if (err)
1566 return err;
1567
1568 /* Initialize a fresh ATU entry if it isn't found */
1569 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1570 !ether_addr_equal(entry.mac, addr)) {
1571 memset(&entry, 0, sizeof(entry));
1572 ether_addr_copy(entry.mac, addr);
1573 }
1574
1575 /* Purge the ATU entry only if no port is using it anymore */
1576 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1577 entry.portvec &= ~BIT(port);
1578 if (!entry.portvec)
1579 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1580 } else {
1581 entry.portvec |= BIT(port);
1582 entry.state = state;
1583 }
1584
1585 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1586}
1587
Andrew Lunn87fa8862017-11-09 22:29:56 +01001588static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1589 u16 vid)
1590{
1591 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1592 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1593
1594 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1595}
1596
1597static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1598{
1599 int port;
1600 int err;
1601
1602 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1603 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1604 if (err)
1605 return err;
1606 }
1607
1608 return 0;
1609}
1610
Vivien Didelotfad09c72016-06-21 12:28:20 -04001611static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
Vivien Didelotc91498e2017-06-07 18:12:13 -04001612 u16 vid, u8 member)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001613{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001614 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001615 int err;
1616
Vivien Didelot567aa592017-05-01 14:05:25 -04001617 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001618 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001619 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001620
Vivien Didelotc91498e2017-06-07 18:12:13 -04001621 vlan.member[port] = member;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001622
Andrew Lunn87fa8862017-11-09 22:29:56 +01001623 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1624 if (err)
1625 return err;
1626
1627 return mv88e6xxx_broadcast_setup(chip, vid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001628}
1629
Vivien Didelotf81ec902016-05-09 13:22:58 -04001630static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001631 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001632{
Vivien Didelot04bed142016-08-31 18:06:13 -04001633 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001634 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1635 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001636 u8 member;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001637 u16 vid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001638
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001639 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001640 return;
1641
Vivien Didelotc91498e2017-06-07 18:12:13 -04001642 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001643 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001644 else if (untagged)
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001645 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001646 else
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001647 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001648
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001649 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001650
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001651 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
Vivien Didelotc91498e2017-06-07 18:12:13 -04001652 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
Vivien Didelot774439e52017-06-08 18:34:08 -04001653 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1654 vid, untagged ? 'u' : 't');
Vivien Didelot76e398a2015-11-01 12:33:55 -05001655
Vivien Didelot77064f32016-11-04 03:23:30 +01001656 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
Vivien Didelot774439e52017-06-08 18:34:08 -04001657 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1658 vlan->vid_end);
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001659
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001660 mv88e6xxx_reg_unlock(chip);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001661}
1662
Vivien Didelotfad09c72016-06-21 12:28:20 -04001663static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001664 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001665{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001666 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001667 int i, err;
1668
Vivien Didelot567aa592017-05-01 14:05:25 -04001669 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001670 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001671 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001672
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001673 /* Tell switchdev if this VLAN is handled in software */
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001674 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05001675 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001676
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001677 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001678
1679 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04001680 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001681 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001682 if (vlan.member[i] !=
1683 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04001684 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001685 break;
1686 }
1687 }
1688
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04001689 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001690 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001691 return err;
1692
Vivien Didelote606ca32017-03-11 16:12:55 -05001693 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001694}
1695
Vivien Didelotf81ec902016-05-09 13:22:58 -04001696static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1697 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001698{
Vivien Didelot04bed142016-08-31 18:06:13 -04001699 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001700 u16 pvid, vid;
1701 int err = 0;
1702
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001703 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001704 return -EOPNOTSUPP;
1705
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001706 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001707
Vivien Didelot77064f32016-11-04 03:23:30 +01001708 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001709 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001710 goto unlock;
1711
Vivien Didelot76e398a2015-11-01 12:33:55 -05001712 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001713 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001714 if (err)
1715 goto unlock;
1716
1717 if (vid == pvid) {
Vivien Didelot77064f32016-11-04 03:23:30 +01001718 err = mv88e6xxx_port_set_pvid(chip, port, 0);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001719 if (err)
1720 goto unlock;
1721 }
1722 }
1723
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001724unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001725 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001726
1727 return err;
1728}
1729
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03001730static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1731 const unsigned char *addr, u16 vid)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07001732{
Vivien Didelot04bed142016-08-31 18:06:13 -04001733 struct mv88e6xxx_chip *chip = ds->priv;
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03001734 int err;
Vivien Didelot6630e232015-08-06 01:44:07 -04001735
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001736 mv88e6xxx_reg_lock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03001737 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1738 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001739 mv88e6xxx_reg_unlock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03001740
1741 return err;
David S. Millercdf09692015-08-11 12:00:37 -07001742}
1743
Vivien Didelotf81ec902016-05-09 13:22:58 -04001744static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
Arkadi Sharshevsky6c2c1dc2017-08-06 16:15:39 +03001745 const unsigned char *addr, u16 vid)
David S. Millercdf09692015-08-11 12:00:37 -07001746{
Vivien Didelot04bed142016-08-31 18:06:13 -04001747 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04001748 int err;
David S. Millercdf09692015-08-11 12:00:37 -07001749
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001750 mv88e6xxx_reg_lock(chip);
Arkadi Sharshevsky6c2c1dc2017-08-06 16:15:39 +03001751 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
Vivien Didelot27c0e602017-06-15 12:14:01 -04001752 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001753 mv88e6xxx_reg_unlock(chip);
David S. Millercdf09692015-08-11 12:00:37 -07001754
Vivien Didelot83dabd12016-08-31 11:50:04 -04001755 return err;
David S. Millercdf09692015-08-11 12:00:37 -07001756}
1757
Vivien Didelot83dabd12016-08-31 11:50:04 -04001758static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1759 u16 fid, u16 vid, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001760 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001761{
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001762 struct mv88e6xxx_atu_entry addr;
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001763 bool is_static;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001764 int err;
1765
Vivien Didelot27c0e602017-06-15 12:14:01 -04001766 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001767 eth_broadcast_addr(addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001768
1769 do {
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001770 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001771 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04001772 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001773
Vivien Didelot27c0e602017-06-15 12:14:01 -04001774 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001775 break;
1776
Vivien Didelot01bd96c2017-03-11 16:12:57 -05001777 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
Vivien Didelot83dabd12016-08-31 11:50:04 -04001778 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001779
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001780 if (!is_unicast_ether_addr(addr.mac))
1781 continue;
Vivien Didelot83dabd12016-08-31 11:50:04 -04001782
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001783 is_static = (addr.state ==
1784 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1785 err = cb(addr.mac, vid, is_static, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001786 if (err)
1787 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001788 } while (!is_broadcast_ether_addr(addr.mac));
1789
1790 return err;
1791}
1792
Vivien Didelot83dabd12016-08-31 11:50:04 -04001793static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001794 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot83dabd12016-08-31 11:50:04 -04001795{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001796 struct mv88e6xxx_vtu_entry vlan = {
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001797 .vid = chip->info->max_vid,
Vivien Didelot83dabd12016-08-31 11:50:04 -04001798 };
1799 u16 fid;
1800 int err;
1801
1802 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01001803 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001804 if (err)
1805 return err;
1806
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001807 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001808 if (err)
1809 return err;
1810
1811 /* Dump VLANs' Filtering Information Databases */
Vivien Didelot83dabd12016-08-31 11:50:04 -04001812 do {
Vivien Didelotf1394b782017-05-01 14:05:22 -04001813 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001814 if (err)
1815 return err;
1816
1817 if (!vlan.valid)
1818 break;
1819
1820 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001821 cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001822 if (err)
1823 return err;
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001824 } while (vlan.vid < chip->info->max_vid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001825
1826 return err;
1827}
1828
Vivien Didelotf81ec902016-05-09 13:22:58 -04001829static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03001830 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelotf33475b2015-10-22 09:34:41 -04001831{
Vivien Didelot04bed142016-08-31 18:06:13 -04001832 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotfcf15362019-06-12 12:42:47 -04001833 int err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04001834
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001835 mv88e6xxx_reg_lock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04001836 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001837 mv88e6xxx_reg_unlock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04001838
1839 return err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04001840}
1841
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001842static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1843 struct net_device *br)
1844{
Vivien Didelote96a6e02017-03-30 17:37:13 -04001845 struct dsa_switch *ds;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001846 int port;
Vivien Didelote96a6e02017-03-30 17:37:13 -04001847 int dev;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001848 int err;
1849
1850 /* Remap the Port VLAN of each local bridge group member */
1851 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1852 if (chip->ds->ports[port].bridge_dev == br) {
1853 err = mv88e6xxx_port_vlan_map(chip, port);
1854 if (err)
1855 return err;
1856 }
1857 }
1858
Vivien Didelote96a6e02017-03-30 17:37:13 -04001859 if (!mv88e6xxx_has_pvt(chip))
1860 return 0;
1861
1862 /* Remap the Port VLAN of each cross-chip bridge group member */
1863 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1864 ds = chip->ds->dst->ds[dev];
1865 if (!ds)
1866 break;
1867
1868 for (port = 0; port < ds->num_ports; ++port) {
1869 if (ds->ports[port].bridge_dev == br) {
1870 err = mv88e6xxx_pvt_map(chip, dev, port);
1871 if (err)
1872 return err;
1873 }
1874 }
1875 }
1876
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001877 return 0;
1878}
1879
Vivien Didelotf81ec902016-05-09 13:22:58 -04001880static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vivien Didelotfae8a252017-01-27 15:29:42 -05001881 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05001882{
Vivien Didelot04bed142016-08-31 18:06:13 -04001883 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001884 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05001885
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001886 mv88e6xxx_reg_lock(chip);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001887 err = mv88e6xxx_bridge_map(chip, br);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001888 mv88e6xxx_reg_unlock(chip);
Vivien Didelota6692752016-02-12 12:09:39 -05001889
Vivien Didelot466dfa02016-02-26 13:16:05 -05001890 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05001891}
1892
Vivien Didelotf123f2f2017-01-27 15:29:41 -05001893static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1894 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05001895{
Vivien Didelot04bed142016-08-31 18:06:13 -04001896 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot466dfa02016-02-26 13:16:05 -05001897
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001898 mv88e6xxx_reg_lock(chip);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001899 if (mv88e6xxx_bridge_map(chip, br) ||
1900 mv88e6xxx_port_vlan_map(chip, port))
1901 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001902 mv88e6xxx_reg_unlock(chip);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05001903}
1904
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001905static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1906 int port, struct net_device *br)
1907{
1908 struct mv88e6xxx_chip *chip = ds->priv;
1909 int err;
1910
1911 if (!mv88e6xxx_has_pvt(chip))
1912 return 0;
1913
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001914 mv88e6xxx_reg_lock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001915 err = mv88e6xxx_pvt_map(chip, dev, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001916 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001917
1918 return err;
1919}
1920
1921static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1922 int port, struct net_device *br)
1923{
1924 struct mv88e6xxx_chip *chip = ds->priv;
1925
1926 if (!mv88e6xxx_has_pvt(chip))
1927 return;
1928
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001929 mv88e6xxx_reg_lock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001930 if (mv88e6xxx_pvt_map(chip, dev, port))
1931 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001932 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001933}
1934
Vivien Didelot17e708b2016-12-05 17:30:27 -05001935static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1936{
1937 if (chip->info->ops->reset)
1938 return chip->info->ops->reset(chip);
1939
1940 return 0;
1941}
1942
Vivien Didelot309eca62016-12-05 17:30:26 -05001943static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1944{
1945 struct gpio_desc *gpiod = chip->reset;
1946
1947 /* If there is a GPIO connected to the reset pin, toggle it */
1948 if (gpiod) {
1949 gpiod_set_value_cansleep(gpiod, 1);
1950 usleep_range(10000, 20000);
1951 gpiod_set_value_cansleep(gpiod, 0);
1952 usleep_range(10000, 20000);
1953 }
1954}
1955
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05001956static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1957{
1958 int i, err;
1959
1960 /* Set all ports to the Disabled state */
1961 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotf894c292017-06-08 18:34:10 -04001962 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05001963 if (err)
1964 return err;
1965 }
1966
1967 /* Wait for transmit queues to drain,
1968 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1969 */
1970 usleep_range(2000, 4000);
1971
1972 return 0;
1973}
1974
Vivien Didelotfad09c72016-06-21 12:28:20 -04001975static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04001976{
Vivien Didelota935c052016-09-29 12:21:53 -04001977 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04001978
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05001979 err = mv88e6xxx_disable_ports(chip);
1980 if (err)
1981 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04001982
Vivien Didelot309eca62016-12-05 17:30:26 -05001983 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04001984
Vivien Didelot17e708b2016-12-05 17:30:27 -05001985 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04001986}
1987
Vivien Didelot43145572017-03-11 16:12:59 -05001988static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04001989 enum mv88e6xxx_frame_mode frame,
1990 enum mv88e6xxx_egress_mode egress, u16 etype)
Andrew Lunn56995cb2016-12-03 04:35:19 +01001991{
1992 int err;
1993
Vivien Didelot43145572017-03-11 16:12:59 -05001994 if (!chip->info->ops->port_set_frame_mode)
1995 return -EOPNOTSUPP;
1996
1997 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
Andrew Lunn56995cb2016-12-03 04:35:19 +01001998 if (err)
1999 return err;
2000
Vivien Didelot43145572017-03-11 16:12:59 -05002001 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2002 if (err)
2003 return err;
2004
2005 if (chip->info->ops->port_set_ether_type)
2006 return chip->info->ops->port_set_ether_type(chip, port, etype);
2007
2008 return 0;
2009}
2010
2011static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2012{
2013 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002014 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002015 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002016}
2017
2018static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2019{
2020 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002021 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002022 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002023}
2024
2025static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2026{
2027 return mv88e6xxx_set_port_mode(chip, port,
2028 MV88E6XXX_FRAME_MODE_ETHERTYPE,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002029 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2030 ETH_P_EDSA);
Vivien Didelot43145572017-03-11 16:12:59 -05002031}
2032
2033static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2034{
2035 if (dsa_is_dsa_port(chip->ds, port))
2036 return mv88e6xxx_set_port_mode_dsa(chip, port);
2037
Vivien Didelot2b3e9892017-10-26 11:22:54 -04002038 if (dsa_is_user_port(chip->ds, port))
Vivien Didelot43145572017-03-11 16:12:59 -05002039 return mv88e6xxx_set_port_mode_normal(chip, port);
2040
2041 /* Setup CPU port mode depending on its supported tag format */
2042 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2043 return mv88e6xxx_set_port_mode_dsa(chip, port);
2044
2045 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2046 return mv88e6xxx_set_port_mode_edsa(chip, port);
2047
2048 return -EINVAL;
2049}
2050
Vivien Didelotea698f42017-03-11 16:12:50 -05002051static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2052{
2053 bool message = dsa_is_dsa_port(chip->ds, port);
2054
2055 return mv88e6xxx_port_set_message_port(chip, port, message);
2056}
2057
Vivien Didelot601aeed2017-03-11 16:13:00 -05002058static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2059{
Vivien Didelot3ee50cb2017-12-05 15:34:09 -05002060 struct dsa_switch *ds = chip->ds;
David S. Miller407308f2019-06-15 13:35:29 -07002061 bool flood;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002062
David S. Miller407308f2019-06-15 13:35:29 -07002063 /* Upstream ports flood frames with unknown unicast or multicast DA */
2064 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2065 if (chip->info->ops->port_set_egress_floods)
2066 return chip->info->ops->port_set_egress_floods(chip, port,
2067 flood, flood);
Vivien Didelot601aeed2017-03-11 16:13:00 -05002068
David S. Miller407308f2019-06-15 13:35:29 -07002069 return 0;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002070}
2071
Andrew Lunn6d917822017-05-26 01:03:21 +02002072static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2073 bool on)
2074{
Vivien Didelot523a8902017-05-26 18:02:42 -04002075 if (chip->info->ops->serdes_power)
2076 return chip->info->ops->serdes_power(chip, port, on);
Andrew Lunn6d917822017-05-26 01:03:21 +02002077
Vivien Didelot523a8902017-05-26 18:02:42 -04002078 return 0;
Andrew Lunn6d917822017-05-26 01:03:21 +02002079}
2080
Vivien Didelotfa371c82017-12-05 15:34:10 -05002081static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2082{
2083 struct dsa_switch *ds = chip->ds;
2084 int upstream_port;
2085 int err;
2086
Vivien Didelot07073c72017-12-05 15:34:13 -05002087 upstream_port = dsa_upstream_port(ds, port);
Vivien Didelotfa371c82017-12-05 15:34:10 -05002088 if (chip->info->ops->port_set_upstream_port) {
2089 err = chip->info->ops->port_set_upstream_port(chip, port,
2090 upstream_port);
2091 if (err)
2092 return err;
2093 }
2094
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002095 if (port == upstream_port) {
2096 if (chip->info->ops->set_cpu_port) {
2097 err = chip->info->ops->set_cpu_port(chip,
2098 upstream_port);
2099 if (err)
2100 return err;
2101 }
2102
2103 if (chip->info->ops->set_egress_port) {
2104 err = chip->info->ops->set_egress_port(chip,
2105 upstream_port);
2106 if (err)
2107 return err;
2108 }
2109 }
2110
Vivien Didelotfa371c82017-12-05 15:34:10 -05002111 return 0;
2112}
2113
Vivien Didelotfad09c72016-06-21 12:28:20 -04002114static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002115{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002116 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002117 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002118 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002119
Andrew Lunn7b898462018-08-09 15:38:47 +02002120 chip->ports[port].chip = chip;
2121 chip->ports[port].port = port;
2122
Vivien Didelotd78343d2016-11-04 03:23:36 +01002123 /* MAC Forcing register: don't force link, speed, duplex or flow control
2124 * state to any particular values on physical ports, but force the CPU
2125 * port and all DSA ports to their maximum bandwidth and full duplex.
2126 */
2127 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2128 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2129 SPEED_MAX, DUPLEX_FULL,
Andrew Lunn54186b92018-08-09 15:38:37 +02002130 PAUSE_OFF,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002131 PHY_INTERFACE_MODE_NA);
2132 else
2133 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2134 SPEED_UNFORCED, DUPLEX_UNFORCED,
Andrew Lunn54186b92018-08-09 15:38:37 +02002135 PAUSE_ON,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002136 PHY_INTERFACE_MODE_NA);
2137 if (err)
2138 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002139
2140 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2141 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2142 * tunneling, determine priority by looking at 802.1p and IP
2143 * priority fields (IP prio has precedence), and set STP state
2144 * to Forwarding.
2145 *
2146 * If this is the CPU link, use DSA or EDSA tagging depending
2147 * on which tagging mode was configured.
2148 *
2149 * If this is a link to another switch, use DSA tagging mode.
2150 *
2151 * If this is the upstream port for this switch, enable
2152 * forwarding of unknown unicasts and multicasts.
2153 */
Vivien Didelota89b433be2017-06-12 12:37:37 -04002154 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2155 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2156 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2157 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002158 if (err)
2159 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002160
Vivien Didelot601aeed2017-03-11 16:13:00 -05002161 err = mv88e6xxx_setup_port_mode(chip, port);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002162 if (err)
2163 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002164
Vivien Didelot601aeed2017-03-11 16:13:00 -05002165 err = mv88e6xxx_setup_egress_floods(chip, port);
Vivien Didelot43145572017-03-11 16:12:59 -05002166 if (err)
2167 return err;
2168
Andrew Lunn04aca992017-05-26 01:03:24 +02002169 /* Enable the SERDES interface for DSA and CPU ports. Normal
2170 * ports SERDES are enabled when the port is enabled, thus
2171 * saving a bit of power.
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002172 */
Andrew Lunn04aca992017-05-26 01:03:24 +02002173 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2174 err = mv88e6xxx_serdes_power(chip, port, true);
2175 if (err)
2176 return err;
2177 }
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002178
Vivien Didelot8efdda42015-08-13 12:52:23 -04002179 /* Port Control 2: don't force a good FCS, set the maximum frame size to
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002180 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002181 * untagged frames on this port, do a destination address lookup on all
2182 * received packets as usual, disable ARP mirroring and don't send a
2183 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002184 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002185 err = mv88e6xxx_port_set_map_da(chip, port);
2186 if (err)
2187 return err;
2188
Vivien Didelotfa371c82017-12-05 15:34:10 -05002189 err = mv88e6xxx_setup_upstream_port(chip, port);
2190 if (err)
2191 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002192
Andrew Lunna23b2962017-02-04 20:15:28 +01002193 err = mv88e6xxx_port_set_8021q_mode(chip, port,
Vivien Didelot81c6edb2017-06-12 12:37:41 -04002194 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
Andrew Lunna23b2962017-02-04 20:15:28 +01002195 if (err)
2196 return err;
2197
Vivien Didelotcd782652017-06-08 18:34:13 -04002198 if (chip->info->ops->port_set_jumbo_size) {
2199 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
Andrew Lunn5f436662016-12-03 04:45:17 +01002200 if (err)
2201 return err;
2202 }
2203
Andrew Lunn54d792f2015-05-06 01:09:47 +02002204 /* Port Association Vector: when learning source addresses
2205 * of packets, add the address to the address database using
2206 * a port bitmap that has only the bit for this port set and
2207 * the other bits clear.
2208 */
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002209 reg = 1 << port;
Vivien Didelot996ecb82016-04-14 14:42:08 -04002210 /* Disable learning for CPU port */
2211 if (dsa_is_cpu_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002212 reg = 0;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002213
Vivien Didelot2a4614e2017-06-12 12:37:43 -04002214 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2215 reg);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002216 if (err)
2217 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002218
2219 /* Egress rate control 2: disable egress rate control. */
Vivien Didelot2cb8cb12017-06-12 12:37:42 -04002220 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2221 0x0000);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002222 if (err)
2223 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002224
Vivien Didelot08984322017-06-08 18:34:12 -04002225 if (chip->info->ops->port_pause_limit) {
2226 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002227 if (err)
2228 return err;
2229 }
2230
Vivien Didelotc8c94892017-03-11 16:13:01 -05002231 if (chip->info->ops->port_disable_learn_limit) {
2232 err = chip->info->ops->port_disable_learn_limit(chip, port);
2233 if (err)
2234 return err;
2235 }
2236
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002237 if (chip->info->ops->port_disable_pri_override) {
2238 err = chip->info->ops->port_disable_pri_override(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002239 if (err)
2240 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002241 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002242
Andrew Lunnef0a7312016-12-03 04:35:16 +01002243 if (chip->info->ops->port_tag_remap) {
2244 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002245 if (err)
2246 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002247 }
2248
Andrew Lunnef70b112016-12-03 04:45:18 +01002249 if (chip->info->ops->port_egress_rate_limiting) {
2250 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002251 if (err)
2252 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002253 }
2254
Vivien Didelotea698f42017-03-11 16:12:50 -05002255 err = mv88e6xxx_setup_message_port(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002256 if (err)
2257 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002258
Vivien Didelot207afda2016-04-14 14:42:09 -04002259 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002260 * database, and allow bidirectional communication between the
2261 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07002262 */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002263 err = mv88e6xxx_port_set_fid(chip, port, 0);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002264 if (err)
2265 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002266
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002267 err = mv88e6xxx_port_vlan_map(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002268 if (err)
2269 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002270
2271 /* Default VLAN ID and priority: don't set a default VLAN
2272 * ID, and set the default packet priority to zero.
2273 */
Vivien Didelotb7929fb2017-06-12 12:37:40 -04002274 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
Andrew Lunndbde9e62015-05-06 01:09:48 +02002275}
2276
Andrew Lunn04aca992017-05-26 01:03:24 +02002277static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2278 struct phy_device *phydev)
2279{
2280 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot523a8902017-05-26 18:02:42 -04002281 int err;
Andrew Lunn04aca992017-05-26 01:03:24 +02002282
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002283 mv88e6xxx_reg_lock(chip);
Andrew Lunnefd1ba62018-08-09 15:38:48 +02002284
Vivien Didelot523a8902017-05-26 18:02:42 -04002285 err = mv88e6xxx_serdes_power(chip, port, true);
Andrew Lunnefd1ba62018-08-09 15:38:48 +02002286
2287 if (!err && chip->info->ops->serdes_irq_setup)
2288 err = chip->info->ops->serdes_irq_setup(chip, port);
2289
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002290 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02002291
2292 return err;
2293}
2294
Andrew Lunn75104db2019-02-24 20:44:43 +01002295static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
Andrew Lunn04aca992017-05-26 01:03:24 +02002296{
2297 struct mv88e6xxx_chip *chip = ds->priv;
2298
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002299 mv88e6xxx_reg_lock(chip);
Andrew Lunnefd1ba62018-08-09 15:38:48 +02002300
Andrew Lunn4a0eb732019-05-01 00:08:30 +02002301 if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED))
2302 dev_err(chip->dev, "failed to disable port\n");
2303
Andrew Lunnefd1ba62018-08-09 15:38:48 +02002304 if (chip->info->ops->serdes_irq_free)
2305 chip->info->ops->serdes_irq_free(chip, port);
2306
Vivien Didelot523a8902017-05-26 18:02:42 -04002307 if (mv88e6xxx_serdes_power(chip, port, false))
2308 dev_err(chip->dev, "failed to power off SERDES\n");
Andrew Lunnefd1ba62018-08-09 15:38:48 +02002309
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002310 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02002311}
2312
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002313static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2314 unsigned int ageing_time)
2315{
Vivien Didelot04bed142016-08-31 18:06:13 -04002316 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002317 int err;
2318
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002319 mv88e6xxx_reg_lock(chip);
Vivien Didelot720c6342017-03-11 16:12:48 -05002320 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002321 mv88e6xxx_reg_unlock(chip);
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002322
2323 return err;
2324}
2325
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002326static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04002327{
2328 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04002329
Andrew Lunnde2273872016-11-21 23:27:01 +01002330 /* Initialize the statistics unit */
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002331 if (chip->info->ops->stats_set_histogram) {
2332 err = chip->info->ops->stats_set_histogram(chip);
2333 if (err)
2334 return err;
2335 }
Andrew Lunnde2273872016-11-21 23:27:01 +01002336
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002337 return mv88e6xxx_g1_stats_clear(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04002338}
2339
Andrew Lunnea890982019-01-09 00:24:03 +01002340/* The mv88e6390 has some hidden registers used for debug and
2341 * development. The errata also makes use of them.
2342 */
2343static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2344 int reg, u16 val)
2345{
2346 u16 ctrl;
2347 int err;
2348
2349 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2350 PORT_RESERVED_1A, val);
2351 if (err)
2352 return err;
2353
2354 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2355 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2356 reg;
2357
2358 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2359 PORT_RESERVED_1A, ctrl);
2360}
2361
2362static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2363{
2364 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2365 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2366}
2367
2368
2369static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2370 int reg, u16 *val)
2371{
2372 u16 ctrl;
2373 int err;
2374
2375 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2376 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2377 reg;
2378
2379 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2380 PORT_RESERVED_1A, ctrl);
2381 if (err)
2382 return err;
2383
2384 err = mv88e6390_hidden_wait(chip);
2385 if (err)
2386 return err;
2387
2388 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2389 PORT_RESERVED_1A, val);
2390}
2391
2392/* Check if the errata has already been applied. */
2393static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2394{
2395 int port;
2396 int err;
2397 u16 val;
2398
2399 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2400 err = mv88e6390_hidden_read(chip, port, 0, &val);
2401 if (err) {
2402 dev_err(chip->dev,
2403 "Error reading hidden register: %d\n", err);
2404 return false;
2405 }
2406 if (val != 0x01c0)
2407 return false;
2408 }
2409
2410 return true;
2411}
2412
2413/* The 6390 copper ports have an errata which require poking magic
2414 * values into undocumented hidden registers and then performing a
2415 * software reset.
2416 */
2417static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2418{
2419 int port;
2420 int err;
2421
2422 if (mv88e6390_setup_errata_applied(chip))
2423 return 0;
2424
2425 /* Set the ports into blocking mode */
2426 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2427 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2428 if (err)
2429 return err;
2430 }
2431
2432 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2433 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2434 if (err)
2435 return err;
2436 }
2437
2438 return mv88e6xxx_software_reset(chip);
2439}
2440
Vivien Didelotf81ec902016-05-09 13:22:58 -04002441static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07002442{
Vivien Didelot04bed142016-08-31 18:06:13 -04002443 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002444 u8 cmode;
Vivien Didelot552238b2016-05-09 13:22:49 -04002445 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002446 int i;
2447
Vivien Didelotfad09c72016-06-21 12:28:20 -04002448 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002449 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002450
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002451 mv88e6xxx_reg_lock(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002452
Andrew Lunnea890982019-01-09 00:24:03 +01002453 if (chip->info->ops->setup_errata) {
2454 err = chip->info->ops->setup_errata(chip);
2455 if (err)
2456 goto unlock;
2457 }
2458
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002459 /* Cache the cmode of each port. */
2460 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2461 if (chip->info->ops->port_get_cmode) {
2462 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2463 if (err)
Dan Carpentere29129f2018-08-14 12:09:05 +03002464 goto unlock;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002465
2466 chip->ports[i].cmode = cmode;
2467 }
2468 }
2469
Vivien Didelot97299342016-07-18 20:45:30 -04002470 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002471 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Andrew Lunn100a9b92019-05-01 00:08:31 +02002472 if (dsa_is_unused_port(ds, i)) {
2473 err = mv88e6xxx_port_set_state(chip, i,
2474 BR_STATE_DISABLED);
2475 if (err)
2476 goto unlock;
2477
2478 err = mv88e6xxx_serdes_power(chip, i, false);
2479 if (err)
2480 goto unlock;
2481
Vivien Didelot91dee142017-10-26 11:22:52 -04002482 continue;
Andrew Lunn100a9b92019-05-01 00:08:31 +02002483 }
Vivien Didelot91dee142017-10-26 11:22:52 -04002484
Vivien Didelot97299342016-07-18 20:45:30 -04002485 err = mv88e6xxx_setup_port(chip, i);
2486 if (err)
2487 goto unlock;
2488 }
2489
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04002490 err = mv88e6xxx_irl_setup(chip);
2491 if (err)
2492 goto unlock;
2493
Vivien Didelot04a69a12017-10-13 14:18:05 -04002494 err = mv88e6xxx_mac_setup(chip);
2495 if (err)
2496 goto unlock;
2497
Vivien Didelot1b17aed2017-05-26 18:03:05 -04002498 err = mv88e6xxx_phy_setup(chip);
2499 if (err)
2500 goto unlock;
2501
Vivien Didelotb486d7c2017-05-01 14:05:13 -04002502 err = mv88e6xxx_vtu_setup(chip);
2503 if (err)
2504 goto unlock;
2505
Vivien Didelot81228992017-03-30 17:37:08 -04002506 err = mv88e6xxx_pvt_setup(chip);
2507 if (err)
2508 goto unlock;
2509
Vivien Didelota2ac29d2017-03-11 16:12:49 -05002510 err = mv88e6xxx_atu_setup(chip);
2511 if (err)
2512 goto unlock;
2513
Andrew Lunn87fa8862017-11-09 22:29:56 +01002514 err = mv88e6xxx_broadcast_setup(chip, 0);
2515 if (err)
2516 goto unlock;
2517
Vivien Didelot9e907d72017-07-17 13:03:43 -04002518 err = mv88e6xxx_pot_setup(chip);
2519 if (err)
2520 goto unlock;
2521
Vivien Didelot9e5baf92018-05-09 11:38:51 -04002522 err = mv88e6xxx_rmu_setup(chip);
2523 if (err)
2524 goto unlock;
2525
Vivien Didelot51c901a2017-07-17 13:03:41 -04002526 err = mv88e6xxx_rsvd2cpu_setup(chip);
2527 if (err)
2528 goto unlock;
Andrew Lunn6e55f692016-12-03 04:45:16 +01002529
Vivien Didelotb28f8722018-04-26 21:56:44 -04002530 err = mv88e6xxx_trunk_setup(chip);
2531 if (err)
2532 goto unlock;
2533
Vivien Didelotc7f047b2018-04-26 21:56:45 -04002534 err = mv88e6xxx_devmap_setup(chip);
2535 if (err)
2536 goto unlock;
2537
Vivien Didelot93e18d62018-05-11 17:16:35 -04002538 err = mv88e6xxx_pri_setup(chip);
2539 if (err)
2540 goto unlock;
2541
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01002542 /* Setup PTP Hardware Clock and timestamping */
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01002543 if (chip->info->ptp_support) {
2544 err = mv88e6xxx_ptp_setup(chip);
2545 if (err)
2546 goto unlock;
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01002547
2548 err = mv88e6xxx_hwtstamp_setup(chip);
2549 if (err)
2550 goto unlock;
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01002551 }
2552
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002553 err = mv88e6xxx_stats_setup(chip);
2554 if (err)
2555 goto unlock;
2556
Vivien Didelot6b17e862015-08-13 12:52:18 -04002557unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002558 mv88e6xxx_reg_unlock(chip);
Andrew Lunndb687a52015-06-20 21:31:29 +02002559
Andrew Lunn48ace4e2016-04-14 23:47:12 +02002560 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002561}
2562
Vivien Didelote57e5e72016-08-15 17:19:00 -04002563static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002564{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002565 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2566 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002567 u16 val;
2568 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002569
Andrew Lunnee26a222017-01-24 14:53:48 +01002570 if (!chip->info->ops->phy_read)
2571 return -EOPNOTSUPP;
2572
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002573 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01002574 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002575 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04002576
Andrew Lunnda9f3302017-02-01 03:40:05 +01002577 if (reg == MII_PHYSID2) {
Andrew Lunnddc49ac2018-11-12 18:51:01 +01002578 /* Some internal PHYs don't have a model number. */
2579 if (chip->info->family != MV88E6XXX_FAMILY_6165)
2580 /* Then there is the 6165 family. It gets is
2581 * PHYs correct. But it can also have two
2582 * SERDES interfaces in the PHY address
2583 * space. And these don't have a model
2584 * number. But they are not PHYs, so we don't
2585 * want to give them something a PHY driver
2586 * will recognise.
2587 *
2588 * Use the mv88e6390 family model number
2589 * instead, for anything which really could be
2590 * a PHY,
2591 */
2592 if (!(val & 0x3f0))
2593 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
Andrew Lunnda9f3302017-02-01 03:40:05 +01002594 }
2595
Vivien Didelote57e5e72016-08-15 17:19:00 -04002596 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002597}
2598
Vivien Didelote57e5e72016-08-15 17:19:00 -04002599static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002600{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002601 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2602 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002603 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002604
Andrew Lunnee26a222017-01-24 14:53:48 +01002605 if (!chip->info->ops->phy_write)
2606 return -EOPNOTSUPP;
2607
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002608 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01002609 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002610 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04002611
2612 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002613}
2614
Vivien Didelotfad09c72016-06-21 12:28:20 -04002615static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01002616 struct device_node *np,
2617 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02002618{
2619 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002620 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02002621 struct mii_bus *bus;
2622 int err;
2623
Andrew Lunn2510bab2018-02-22 01:51:49 +01002624 if (external) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002625 mv88e6xxx_reg_lock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01002626 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002627 mv88e6xxx_reg_unlock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01002628
2629 if (err)
2630 return err;
2631 }
2632
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002633 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02002634 if (!bus)
2635 return -ENOMEM;
2636
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002637 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002638 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002639 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002640 INIT_LIST_HEAD(&mdio_bus->list);
2641 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002642
Andrew Lunnb516d452016-06-04 21:17:06 +02002643 if (np) {
2644 bus->name = np->full_name;
Rob Herringf7ce9102017-07-18 16:43:19 -05002645 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
Andrew Lunnb516d452016-06-04 21:17:06 +02002646 } else {
2647 bus->name = "mv88e6xxx SMI";
2648 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2649 }
2650
2651 bus->read = mv88e6xxx_mdio_read;
2652 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002653 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02002654
Andrew Lunn6f882842018-03-17 20:32:05 +01002655 if (!external) {
2656 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2657 if (err)
2658 return err;
2659 }
2660
Florian Fainelli00e798c2018-05-15 16:56:19 -07002661 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02002662 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002663 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunn6f882842018-03-17 20:32:05 +01002664 mv88e6xxx_g2_irq_mdio_free(chip, bus);
Andrew Lunna3c53be52017-01-24 14:53:50 +01002665 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02002666 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01002667
2668 if (external)
2669 list_add_tail(&mdio_bus->list, &chip->mdios);
2670 else
2671 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02002672
2673 return 0;
Andrew Lunnb516d452016-06-04 21:17:06 +02002674}
2675
Andrew Lunna3c53be52017-01-24 14:53:50 +01002676static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2677 { .compatible = "marvell,mv88e6xxx-mdio-external",
2678 .data = (void *)true },
2679 { },
2680};
2681
Andrew Lunn3126aee2017-12-07 01:05:57 +01002682static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2683
2684{
2685 struct mv88e6xxx_mdio_bus *mdio_bus;
2686 struct mii_bus *bus;
2687
2688 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2689 bus = mdio_bus->bus;
2690
Andrew Lunn6f882842018-03-17 20:32:05 +01002691 if (!mdio_bus->external)
2692 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2693
Andrew Lunn3126aee2017-12-07 01:05:57 +01002694 mdiobus_unregister(bus);
2695 }
2696}
2697
Andrew Lunna3c53be52017-01-24 14:53:50 +01002698static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2699 struct device_node *np)
2700{
2701 const struct of_device_id *match;
2702 struct device_node *child;
2703 int err;
2704
2705 /* Always register one mdio bus for the internal/default mdio
2706 * bus. This maybe represented in the device tree, but is
2707 * optional.
2708 */
2709 child = of_get_child_by_name(np, "mdio");
2710 err = mv88e6xxx_mdio_register(chip, child, false);
2711 if (err)
2712 return err;
2713
2714 /* Walk the device tree, and see if there are any other nodes
2715 * which say they are compatible with the external mdio
2716 * bus.
2717 */
2718 for_each_available_child_of_node(np, child) {
2719 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2720 if (match) {
2721 err = mv88e6xxx_mdio_register(chip, child, true);
Andrew Lunn3126aee2017-12-07 01:05:57 +01002722 if (err) {
2723 mv88e6xxx_mdios_unregister(chip);
Nishka Dasgupta78e42042019-07-23 16:13:07 +05302724 of_node_put(child);
Andrew Lunna3c53be52017-01-24 14:53:50 +01002725 return err;
Andrew Lunn3126aee2017-12-07 01:05:57 +01002726 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01002727 }
2728 }
2729
2730 return 0;
2731}
2732
Vivien Didelot855b1932016-07-20 18:18:35 -04002733static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2734{
Vivien Didelot04bed142016-08-31 18:06:13 -04002735 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04002736
2737 return chip->eeprom_len;
2738}
2739
Vivien Didelot855b1932016-07-20 18:18:35 -04002740static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2741 struct ethtool_eeprom *eeprom, u8 *data)
2742{
Vivien Didelot04bed142016-08-31 18:06:13 -04002743 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04002744 int err;
2745
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002746 if (!chip->info->ops->get_eeprom)
2747 return -EOPNOTSUPP;
2748
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002749 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002750 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002751 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04002752
2753 if (err)
2754 return err;
2755
2756 eeprom->magic = 0xc3ec4951;
2757
2758 return 0;
2759}
2760
Vivien Didelot855b1932016-07-20 18:18:35 -04002761static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2762 struct ethtool_eeprom *eeprom, u8 *data)
2763{
Vivien Didelot04bed142016-08-31 18:06:13 -04002764 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04002765 int err;
2766
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002767 if (!chip->info->ops->set_eeprom)
2768 return -EOPNOTSUPP;
2769
Vivien Didelot855b1932016-07-20 18:18:35 -04002770 if (eeprom->magic != 0xc3ec4951)
2771 return -EINVAL;
2772
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002773 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002774 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002775 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04002776
2777 return err;
2778}
2779
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002780static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002781 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04002782 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2783 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04002784 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002785 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04002786 .phy_read = mv88e6185_phy_ppu_read,
2787 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002788 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002789 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002790 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002791 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002792 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002793 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002794 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01002795 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04002796 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002797 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002798 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02002799 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002800 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002801 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002802 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01002803 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2804 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002805 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04002806 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2807 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002808 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04002809 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04002810 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002811 .ppu_enable = mv88e6185_g1_ppu_enable,
2812 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002813 .reset = mv88e6185_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04002814 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04002815 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002816 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02002817 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002818};
2819
2820static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002821 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04002822 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2823 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002824 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04002825 .phy_read = mv88e6185_phy_ppu_read,
2826 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002827 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002828 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002829 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002830 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002831 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunna23b2962017-02-04 20:15:28 +01002832 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Russell King6c422e32018-08-09 15:38:39 +02002833 .port_link_state = mv88e6185_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002834 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002835 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002836 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01002837 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2838 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002839 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelot51c901a2017-07-17 13:03:41 -04002840 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002841 .ppu_enable = mv88e6185_g1_ppu_enable,
2842 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002843 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04002844 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002845 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02002846 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002847};
2848
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002849static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01002850 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04002851 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2852 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04002853 .irl_init_all = mv88e6352_g2_irl_init_all,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002854 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2855 .phy_read = mv88e6xxx_g2_smi_phy_read,
2856 .phy_write = mv88e6xxx_g2_smi_phy_write,
2857 .port_set_link = mv88e6xxx_port_set_link,
2858 .port_set_duplex = mv88e6xxx_port_set_duplex,
2859 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002860 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002861 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002862 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002863 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04002864 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01002865 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04002866 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002867 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002868 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02002869 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002870 .port_get_cmode = mv88e6185_port_get_cmode,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002871 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002872 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002873 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2874 .stats_get_strings = mv88e6095_stats_get_strings,
2875 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04002876 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2877 .set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01002878 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04002879 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04002880 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002881 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04002882 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04002883 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002884 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02002885 .phylink_validate = mv88e6185_phylink_validate,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002886};
2887
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002888static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002889 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04002890 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2891 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04002892 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002893 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02002894 .phy_read = mv88e6xxx_g2_smi_phy_read,
2895 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002896 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002897 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002898 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002899 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002900 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002901 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002902 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02002903 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002904 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunn0ac64c32017-06-02 23:22:46 +02002905 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002906 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01002907 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2908 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002909 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04002910 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2911 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002912 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04002913 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04002914 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002915 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04002916 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002917 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02002918 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002919};
2920
2921static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002922 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04002923 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2924 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002925 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04002926 .phy_read = mv88e6185_phy_ppu_read,
2927 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002928 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002929 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002930 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002931 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002932 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002933 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002934 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01002935 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Vivien Didelotcd782652017-06-08 18:34:13 -04002936 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01002937 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04002938 .port_pause_limit = mv88e6097_port_pause_limit,
Andrew Lunn54186b92018-08-09 15:38:37 +02002939 .port_set_pause = mv88e6185_port_set_pause,
Russell King6c422e32018-08-09 15:38:39 +02002940 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002941 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002942 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002943 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01002944 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2945 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002946 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04002947 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2948 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002949 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04002950 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002951 .ppu_enable = mv88e6185_g1_ppu_enable,
Vivien Didelot02317e62018-05-09 11:38:49 -04002952 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002953 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002954 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04002955 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002956 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02002957 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002958};
2959
Vivien Didelot990e27b2017-03-28 13:50:32 -04002960static const struct mv88e6xxx_ops mv88e6141_ops = {
2961 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04002962 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2963 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04002964 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002965 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2966 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2967 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2968 .phy_read = mv88e6xxx_g2_smi_phy_read,
2969 .phy_write = mv88e6xxx_g2_smi_phy_write,
2970 .port_set_link = mv88e6xxx_port_set_link,
2971 .port_set_duplex = mv88e6xxx_port_set_duplex,
2972 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Marek Behún26422342018-10-13 14:40:31 +02002973 .port_set_speed = mv88e6341_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01002974 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002975 .port_tag_remap = mv88e6095_port_tag_remap,
2976 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2977 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2978 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04002979 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04002981 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02002984 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002985 .port_get_cmode = mv88e6352_port_get_cmode,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002986 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002987 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002988 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2989 .stats_get_strings = mv88e6320_stats_get_strings,
2990 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04002991 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2992 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002993 .watchdog_ops = &mv88e6390_watchdog_ops,
2994 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04002995 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot990e27b2017-03-28 13:50:32 -04002996 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04002997 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002998 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunn6751e7c2018-07-31 19:19:50 +02002999 .serdes_power = mv88e6341_serdes_power,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003000 .gpio_ops = &mv88e6352_gpio_ops,
Marek Behúne3af71a2019-02-25 12:39:55 +01003001 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003002};
3003
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003004static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003005 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003006 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3007 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003008 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003009 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003010 .phy_read = mv88e6xxx_g2_smi_phy_read,
3011 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003012 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003013 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003014 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003015 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003016 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003017 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003018 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003019 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003020 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003021 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003022 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003023 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003024 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003025 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunna6da21b2019-03-01 23:43:39 +01003026 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003027 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003028 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3029 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003030 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003031 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3032 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003033 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003034 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003035 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003036 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003037 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003038 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003039 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003040 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003041 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003042};
3043
3044static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003045 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003046 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3047 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003048 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003049 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003050 .phy_read = mv88e6165_phy_read,
3051 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003052 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003053 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003054 .port_set_speed = mv88e6185_port_set_speed,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003057 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003058 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003059 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003060 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003061 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3062 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003063 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003064 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3065 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003066 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003067 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003068 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003069 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003070 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003071 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003072 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003073 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003074 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003075};
3076
3077static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003078 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003079 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3080 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003081 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003082 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003083 .phy_read = mv88e6xxx_g2_smi_phy_read,
3084 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003085 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003086 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003087 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003088 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003089 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003090 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003091 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003092 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003093 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003094 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003095 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003096 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003097 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003098 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003099 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003100 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003101 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003102 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3103 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003104 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003105 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3106 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003107 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003108 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003109 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003110 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003111 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003112 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003113 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003114};
3115
3116static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003117 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003118 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3119 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003120 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003121 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3122 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003123 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003124 .phy_read = mv88e6xxx_g2_smi_phy_read,
3125 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003126 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003127 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003128 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003129 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003130 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003131 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003132 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003133 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003134 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003135 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003136 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003137 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003138 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003139 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003140 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003141 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003142 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003143 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3144 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003145 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003146 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3147 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003148 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003149 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003150 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003151 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003152 .rmu_disable = mv88e6352_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003153 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003154 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunn6d917822017-05-26 01:03:21 +02003155 .serdes_power = mv88e6352_serdes_power,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003156 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003157 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003158};
3159
3160static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003161 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003162 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3163 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003164 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003165 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003166 .phy_read = mv88e6xxx_g2_smi_phy_read,
3167 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003168 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003169 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003170 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003171 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003172 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003173 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003174 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003175 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003176 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003177 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003178 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003179 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003180 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003181 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003182 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003183 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003184 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003185 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3186 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003187 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003188 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3189 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003190 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003191 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003192 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003193 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003194 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003195 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003196 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003197};
3198
3199static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003200 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003201 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3202 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003203 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003204 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3205 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003206 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003207 .phy_read = mv88e6xxx_g2_smi_phy_read,
3208 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003209 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003210 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003211 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003212 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003213 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003214 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003215 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003216 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003217 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003218 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003219 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003220 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003221 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003222 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003223 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003224 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003225 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003226 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3227 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003228 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003229 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3230 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003231 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003232 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003233 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003234 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003235 .rmu_disable = mv88e6352_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003236 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003237 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunn6d917822017-05-26 01:03:21 +02003238 .serdes_power = mv88e6352_serdes_power,
Andrew Lunn43821722018-09-02 18:13:15 +02003239 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3240 .serdes_irq_free = mv88e6352_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003241 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003242 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003243};
3244
3245static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003246 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003247 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3248 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003249 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003250 .phy_read = mv88e6185_phy_ppu_read,
3251 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003252 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003253 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003254 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003255 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003256 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunnef70b112016-12-03 04:45:18 +01003257 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01003258 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn54186b92018-08-09 15:38:37 +02003259 .port_set_pause = mv88e6185_port_set_pause,
Russell King6c422e32018-08-09 15:38:39 +02003260 .port_link_state = mv88e6185_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003261 .port_get_cmode = mv88e6185_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003262 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003263 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003264 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3265 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003266 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003267 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3268 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003269 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003270 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelot02317e62018-05-09 11:38:49 -04003271 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003272 .ppu_enable = mv88e6185_g1_ppu_enable,
3273 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003274 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003275 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003276 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003277 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003278};
3279
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003280static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003281 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003282 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003283 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003284 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3285 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003286 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3287 .phy_read = mv88e6xxx_g2_smi_phy_read,
3288 .phy_write = mv88e6xxx_g2_smi_phy_write,
3289 .port_set_link = mv88e6xxx_port_set_link,
3290 .port_set_duplex = mv88e6xxx_port_set_duplex,
3291 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3292 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003293 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003294 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003295 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003296 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003297 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04003298 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003299 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003300 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003301 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003302 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003303 .port_set_cmode = mv88e6390_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003304 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003305 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003306 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3307 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003308 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003309 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3310 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003311 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003312 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003313 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003314 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003315 .rmu_disable = mv88e6390_g1_rmu_disable,
Vivien Didelot931d1822017-05-01 14:05:27 -04003316 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3317 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003318 .serdes_power = mv88e6390_serdes_power,
Andrew Lunnefd1ba62018-08-09 15:38:48 +02003319 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3320 .serdes_irq_free = mv88e6390_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003321 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003322 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003323};
3324
3325static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003326 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003327 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003328 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003329 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3330 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003331 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3332 .phy_read = mv88e6xxx_g2_smi_phy_read,
3333 .phy_write = mv88e6xxx_g2_smi_phy_write,
3334 .port_set_link = mv88e6xxx_port_set_link,
3335 .port_set_duplex = mv88e6xxx_port_set_duplex,
3336 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3337 .port_set_speed = mv88e6390x_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003338 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003339 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003340 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003341 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003342 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04003343 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003344 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003345 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003346 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003347 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003348 .port_set_cmode = mv88e6390x_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003349 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003350 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003351 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3352 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003353 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003354 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3355 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003356 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003357 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003358 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003359 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003360 .rmu_disable = mv88e6390_g1_rmu_disable,
Vivien Didelot931d1822017-05-01 14:05:27 -04003361 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3362 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn07ffbd72018-08-09 15:38:41 +02003363 .serdes_power = mv88e6390x_serdes_power,
Andrew Lunn2defda12018-11-11 00:32:17 +01003364 .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3365 .serdes_irq_free = mv88e6390x_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003366 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003367 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003368};
3369
3370static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003371 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003372 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003373 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003374 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3375 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003376 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3377 .phy_read = mv88e6xxx_g2_smi_phy_read,
3378 .phy_write = mv88e6xxx_g2_smi_phy_write,
3379 .port_set_link = mv88e6xxx_port_set_link,
3380 .port_set_duplex = mv88e6xxx_port_set_duplex,
3381 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3382 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003383 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003384 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003385 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003386 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003387 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04003388 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003391 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003392 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003393 .port_set_cmode = mv88e6390_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003394 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003395 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003396 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3397 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003398 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003399 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3400 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003401 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003402 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003403 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003404 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003405 .rmu_disable = mv88e6390_g1_rmu_disable,
Vivien Didelot931d1822017-05-01 14:05:27 -04003406 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3407 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003408 .serdes_power = mv88e6390_serdes_power,
Andrew Lunnefd1ba62018-08-09 15:38:48 +02003409 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3410 .serdes_irq_free = mv88e6390_serdes_irq_free,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003411 .avb_ops = &mv88e6390_avb_ops,
3412 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003413 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003414};
3415
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003416static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003417 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003418 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3419 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003420 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003421 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3422 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003423 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003424 .phy_read = mv88e6xxx_g2_smi_phy_read,
3425 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003426 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003427 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003428 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003429 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003430 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003431 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003432 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003433 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003434 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003435 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003436 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003437 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003438 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003439 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003440 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003441 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003442 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003443 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3444 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003445 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003446 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3447 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003448 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003449 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003450 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003451 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003452 .rmu_disable = mv88e6352_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003453 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003454 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunn6d917822017-05-26 01:03:21 +02003455 .serdes_power = mv88e6352_serdes_power,
Andrew Lunn43821722018-09-02 18:13:15 +02003456 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3457 .serdes_irq_free = mv88e6352_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003458 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003459 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003460 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003461 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003462};
3463
Rasmus Villemoes1f718362019-06-04 07:34:32 +00003464static const struct mv88e6xxx_ops mv88e6250_ops = {
3465 /* MV88E6XXX_FAMILY_6250 */
3466 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3467 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3468 .irl_init_all = mv88e6352_g2_irl_init_all,
3469 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3470 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3471 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3472 .phy_read = mv88e6xxx_g2_smi_phy_read,
3473 .phy_write = mv88e6xxx_g2_smi_phy_write,
3474 .port_set_link = mv88e6xxx_port_set_link,
3475 .port_set_duplex = mv88e6xxx_port_set_duplex,
3476 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3477 .port_set_speed = mv88e6250_port_set_speed,
3478 .port_tag_remap = mv88e6095_port_tag_remap,
3479 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3480 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3481 .port_set_ether_type = mv88e6351_port_set_ether_type,
3482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3483 .port_pause_limit = mv88e6097_port_pause_limit,
3484 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3485 .port_link_state = mv88e6250_port_link_state,
3486 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3487 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3488 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
3489 .stats_get_strings = mv88e6250_stats_get_strings,
3490 .stats_get_stats = mv88e6250_stats_get_stats,
3491 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3492 .set_egress_port = mv88e6095_g1_set_egress_port,
3493 .watchdog_ops = &mv88e6250_watchdog_ops,
3494 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3495 .pot_clear = mv88e6xxx_g2_pot_clear,
3496 .reset = mv88e6250_g1_reset,
3497 .vtu_getnext = mv88e6250_g1_vtu_getnext,
3498 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
3499 .phylink_validate = mv88e6065_phylink_validate,
3500};
3501
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003502static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003503 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003504 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003505 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003506 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3507 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003508 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3509 .phy_read = mv88e6xxx_g2_smi_phy_read,
3510 .phy_write = mv88e6xxx_g2_smi_phy_write,
3511 .port_set_link = mv88e6xxx_port_set_link,
3512 .port_set_duplex = mv88e6xxx_port_set_duplex,
3513 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3514 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003515 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003516 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003517 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003518 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003519 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04003520 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003521 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003522 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003523 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003524 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003525 .port_set_cmode = mv88e6390_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003526 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003527 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003528 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3529 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003530 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003531 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3532 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003533 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003534 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003535 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003536 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003537 .rmu_disable = mv88e6390_g1_rmu_disable,
Vivien Didelot931d1822017-05-01 14:05:27 -04003538 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3539 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003540 .serdes_power = mv88e6390_serdes_power,
Andrew Lunnefd1ba62018-08-09 15:38:48 +02003541 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3542 .serdes_irq_free = mv88e6390_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003543 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003544 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003545 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003546 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003547};
3548
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003549static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003550 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003551 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3552 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003553 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003554 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3555 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003557 .phy_read = mv88e6xxx_g2_smi_phy_read,
3558 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003559 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003560 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003561 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003562 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003563 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003564 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003565 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003566 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003567 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003568 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003569 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003570 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003571 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003572 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003573 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003574 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003575 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3576 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003577 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003578 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3579 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01003580 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003581 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003582 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003583 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003584 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003585 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003586 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003587 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003588 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003589 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003590};
3591
3592static const struct mv88e6xxx_ops mv88e6321_ops = {
Vivien Didelotbd807202017-07-17 13:03:37 -04003593 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003594 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3595 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003596 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003597 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3598 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003599 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003600 .phy_read = mv88e6xxx_g2_smi_phy_read,
3601 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003602 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003603 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003604 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003605 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003606 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003607 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003608 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003609 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003610 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003611 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003612 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003613 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003614 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003615 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003616 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003617 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003618 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3619 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003620 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003621 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3622 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01003623 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003624 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003625 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003626 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003627 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003628 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003629 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003630 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003631};
3632
Vivien Didelot16e329a2017-03-28 13:50:33 -04003633static const struct mv88e6xxx_ops mv88e6341_ops = {
3634 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003635 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3636 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003637 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003638 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3639 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3640 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3641 .phy_read = mv88e6xxx_g2_smi_phy_read,
3642 .phy_write = mv88e6xxx_g2_smi_phy_write,
3643 .port_set_link = mv88e6xxx_port_set_link,
3644 .port_set_duplex = mv88e6xxx_port_set_duplex,
3645 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Marek Behún26422342018-10-13 14:40:31 +02003646 .port_set_speed = mv88e6341_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003647 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003648 .port_tag_remap = mv88e6095_port_tag_remap,
3649 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3650 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3651 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003652 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003653 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003654 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003655 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3656 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003657 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003658 .port_get_cmode = mv88e6352_port_get_cmode,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003659 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003660 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003661 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3662 .stats_get_strings = mv88e6320_stats_get_strings,
3663 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003664 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3665 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003666 .watchdog_ops = &mv88e6390_watchdog_ops,
3667 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003668 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003669 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003670 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003671 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunn6751e7c2018-07-31 19:19:50 +02003672 .serdes_power = mv88e6341_serdes_power,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003673 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003674 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003675 .ptp_ops = &mv88e6352_ptp_ops,
Marek Behúne3af71a2019-02-25 12:39:55 +01003676 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot16e329a2017-03-28 13:50:33 -04003677};
3678
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003679static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003680 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003681 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3682 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003683 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003684 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003685 .phy_read = mv88e6xxx_g2_smi_phy_read,
3686 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003687 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003688 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003689 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003690 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003691 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003692 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003693 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003694 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003695 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003697 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003698 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003699 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003700 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003701 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003702 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003703 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003704 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3705 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003706 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003707 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3708 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003709 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003710 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003711 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003712 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003713 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003714 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003715 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003716};
3717
3718static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003719 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003720 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3721 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003722 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003723 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003724 .phy_read = mv88e6xxx_g2_smi_phy_read,
3725 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003726 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003727 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003728 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003729 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003730 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003731 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003732 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003733 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003734 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003735 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003736 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003737 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003738 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003739 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003740 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003741 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003742 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003743 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3744 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003745 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003746 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3747 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003748 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003749 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003750 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003751 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003752 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003753 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003754 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003755 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003756 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003757};
3758
3759static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003760 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003761 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3762 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003763 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003764 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3765 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003766 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003767 .phy_read = mv88e6xxx_g2_smi_phy_read,
3768 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003769 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003770 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003771 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003772 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003773 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003774 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003775 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003776 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003777 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003778 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003779 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003780 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003781 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003782 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003783 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003784 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003785 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003786 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3787 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003788 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003789 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3790 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003791 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003792 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003793 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003794 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003795 .rmu_disable = mv88e6352_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003796 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003797 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunn6d917822017-05-26 01:03:21 +02003798 .serdes_power = mv88e6352_serdes_power,
Andrew Lunn43821722018-09-02 18:13:15 +02003799 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3800 .serdes_irq_free = mv88e6352_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003801 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003802 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003803 .ptp_ops = &mv88e6352_ptp_ops,
Andrew Lunncda9f4a2018-03-01 02:02:31 +01003804 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3805 .serdes_get_strings = mv88e6352_serdes_get_strings,
3806 .serdes_get_stats = mv88e6352_serdes_get_stats,
Russell King6c422e32018-08-09 15:38:39 +02003807 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003808};
3809
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003810static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003811 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003812 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003813 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003814 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3815 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003816 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3817 .phy_read = mv88e6xxx_g2_smi_phy_read,
3818 .phy_write = mv88e6xxx_g2_smi_phy_write,
3819 .port_set_link = mv88e6xxx_port_set_link,
3820 .port_set_duplex = mv88e6xxx_port_set_duplex,
3821 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3822 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003823 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003824 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003825 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003826 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003827 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003828 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003829 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003830 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003831 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003832 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003833 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003834 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003835 .port_set_cmode = mv88e6390_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003836 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003837 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003838 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3839 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003840 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003841 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3842 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003843 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003844 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003845 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003846 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003847 .rmu_disable = mv88e6390_g1_rmu_disable,
Vivien Didelot931d1822017-05-01 14:05:27 -04003848 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3849 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003850 .serdes_power = mv88e6390_serdes_power,
Andrew Lunnefd1ba62018-08-09 15:38:48 +02003851 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3852 .serdes_irq_free = mv88e6390_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003853 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003854 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003855 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003856 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003857};
3858
3859static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003860 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003861 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003862 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003863 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3864 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003865 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3866 .phy_read = mv88e6xxx_g2_smi_phy_read,
3867 .phy_write = mv88e6xxx_g2_smi_phy_write,
3868 .port_set_link = mv88e6xxx_port_set_link,
3869 .port_set_duplex = mv88e6xxx_port_set_duplex,
3870 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3871 .port_set_speed = mv88e6390x_port_set_speed,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003872 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003873 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003874 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003875 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003876 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003877 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003878 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003879 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003880 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003881 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Russell King6c422e32018-08-09 15:38:39 +02003882 .port_link_state = mv88e6352_port_link_state,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003883 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnb3dce4d2018-11-11 00:32:14 +01003884 .port_set_cmode = mv88e6390x_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003885 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003886 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003887 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3888 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003889 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003890 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3891 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003892 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003893 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003894 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003895 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003896 .rmu_disable = mv88e6390_g1_rmu_disable,
Vivien Didelot931d1822017-05-01 14:05:27 -04003897 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3898 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn07ffbd72018-08-09 15:38:41 +02003899 .serdes_power = mv88e6390x_serdes_power,
Andrew Lunn2defda12018-11-11 00:32:17 +01003900 .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3901 .serdes_irq_free = mv88e6390x_serdes_irq_free,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003902 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003903 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003904 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003905 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003906};
3907
Vivien Didelotf81ec902016-05-09 13:22:58 -04003908static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3909 [MV88E6085] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04003910 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003911 .family = MV88E6XXX_FAMILY_6097,
3912 .name = "Marvell 88E6085",
3913 .num_databases = 4096,
3914 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01003915 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003916 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003917 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02003918 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04003919 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04003920 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003921 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003922 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04003923 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05003924 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003925 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04003926 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003927 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003928 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003929 },
3930
3931 [MV88E6095] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04003932 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003933 .family = MV88E6XXX_FAMILY_6095,
3934 .name = "Marvell 88E6095/88E6095F",
3935 .num_databases = 256,
3936 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01003937 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003938 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003939 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02003940 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04003941 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04003942 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003943 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003944 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003945 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04003946 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003947 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003948 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003949 },
3950
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003951 [MV88E6097] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04003952 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003953 .family = MV88E6XXX_FAMILY_6097,
3954 .name = "Marvell 88E6097/88E6097F",
3955 .num_databases = 4096,
3956 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01003957 .num_internal_phys = 8,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003958 .max_vid = 4095,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003959 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02003960 .phy_base_addr = 0x0,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003961 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04003962 .global2_addr = 0x1c,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003963 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01003964 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04003965 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05003966 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003967 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04003968 .multi_chip = true,
Stefan Eichenberger2bfcfcd2016-12-05 14:12:42 +01003969 .tag_protocol = DSA_TAG_PROTO_EDSA,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003970 .ops = &mv88e6097_ops,
3971 },
3972
Vivien Didelotf81ec902016-05-09 13:22:58 -04003973 [MV88E6123] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04003974 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003975 .family = MV88E6XXX_FAMILY_6165,
3976 .name = "Marvell 88E6123",
3977 .num_databases = 4096,
3978 .num_ports = 3,
Andrew Lunnbc393152018-03-17 20:32:04 +01003979 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003980 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003981 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02003982 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04003983 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04003984 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003985 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003986 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04003987 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05003988 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003989 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04003990 .multi_chip = true,
Andrew Lunn5ebe31d2017-06-07 15:06:19 +02003991 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003992 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003993 },
3994
3995 [MV88E6131] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04003996 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003997 .family = MV88E6XXX_FAMILY_6185,
3998 .name = "Marvell 88E6131",
3999 .num_databases = 256,
4000 .num_ports = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004001 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004002 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004003 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004004 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004005 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004006 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004007 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004008 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05004009 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004010 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004011 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004012 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004013 },
4014
Vivien Didelot990e27b2017-03-28 13:50:32 -04004015 [MV88E6141] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004016 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004017 .family = MV88E6XXX_FAMILY_6341,
Uwe Kleine-König79a68b22018-03-20 10:44:40 +01004018 .name = "Marvell 88E6141",
Vivien Didelot990e27b2017-03-28 13:50:32 -04004019 .num_databases = 4096,
4020 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004021 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004022 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004023 .max_vid = 4095,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004024 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004025 .phy_base_addr = 0x10,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004026 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004027 .global2_addr = 0x1c,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004028 .age_time_coeff = 3750,
4029 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01004030 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004031 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04004032 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004033 .multi_chip = true,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004034 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004035 .ops = &mv88e6141_ops,
4036 },
4037
Vivien Didelotf81ec902016-05-09 13:22:58 -04004038 [MV88E6161] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004039 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004040 .family = MV88E6XXX_FAMILY_6165,
4041 .name = "Marvell 88E6161",
4042 .num_databases = 4096,
4043 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004044 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004045 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004046 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004047 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004048 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004049 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004050 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004051 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004052 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004053 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004054 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004055 .multi_chip = true,
Andrew Lunn5ebe31d2017-06-07 15:06:19 +02004056 .tag_protocol = DSA_TAG_PROTO_EDSA,
Andrew Lunndfa54342018-07-18 22:38:22 +02004057 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004058 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004059 },
4060
4061 [MV88E6165] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004062 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004063 .family = MV88E6XXX_FAMILY_6165,
4064 .name = "Marvell 88E6165",
4065 .num_databases = 4096,
4066 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004067 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004068 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004069 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004070 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004071 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004072 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004073 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004074 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004075 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004076 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004077 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004078 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004079 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunndfa54342018-07-18 22:38:22 +02004080 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004081 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004082 },
4083
4084 [MV88E6171] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004086 .family = MV88E6XXX_FAMILY_6351,
4087 .name = "Marvell 88E6171",
4088 .num_databases = 4096,
4089 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004090 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004091 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004092 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004093 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004094 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004095 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004096 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004097 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004098 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004099 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004100 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004101 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004102 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004103 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004104 },
4105
4106 [MV88E6172] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004107 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004108 .family = MV88E6XXX_FAMILY_6352,
4109 .name = "Marvell 88E6172",
4110 .num_databases = 4096,
4111 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004112 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004113 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004114 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004115 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004116 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004117 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004118 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004119 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004120 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004121 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004122 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004123 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004124 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004125 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004126 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004127 },
4128
4129 [MV88E6175] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004130 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004131 .family = MV88E6XXX_FAMILY_6351,
4132 .name = "Marvell 88E6175",
4133 .num_databases = 4096,
4134 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004135 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004136 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004137 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004138 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004139 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004140 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004141 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004142 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004143 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004144 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004145 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004146 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004147 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004148 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004149 },
4150
4151 [MV88E6176] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004152 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004153 .family = MV88E6XXX_FAMILY_6352,
4154 .name = "Marvell 88E6176",
4155 .num_databases = 4096,
4156 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004157 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004158 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004159 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004160 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004161 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004162 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004163 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004164 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004165 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004166 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004167 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004168 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004169 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004170 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004171 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004172 },
4173
4174 [MV88E6185] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004175 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004176 .family = MV88E6XXX_FAMILY_6185,
4177 .name = "Marvell 88E6185",
4178 .num_databases = 256,
4179 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01004180 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004181 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004182 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004183 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004184 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004185 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004186 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004187 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05004188 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004189 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004190 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004191 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004192 },
4193
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004194 [MV88E6190] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004195 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004196 .family = MV88E6XXX_FAMILY_6390,
4197 .name = "Marvell 88E6190",
4198 .num_databases = 4096,
4199 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004200 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004201 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004202 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004203 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004204 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004205 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004206 .global2_addr = 0x1c,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004207 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004208 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004209 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004210 .g2_irqs = 14,
Vivien Didelotf3645652017-03-30 17:37:07 -04004211 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004212 .multi_chip = true,
Vivien Didelote606ca32017-03-11 16:12:55 -05004213 .atu_move_port_mask = 0x1f,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004214 .ops = &mv88e6190_ops,
4215 },
4216
4217 [MV88E6190X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004219 .family = MV88E6XXX_FAMILY_6390,
4220 .name = "Marvell 88E6190X",
4221 .num_databases = 4096,
4222 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004223 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004224 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004225 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004226 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004227 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004228 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004229 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004230 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004231 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004232 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004233 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004234 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004235 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004236 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004237 .ops = &mv88e6190x_ops,
4238 },
4239
4240 [MV88E6191] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004241 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004242 .family = MV88E6XXX_FAMILY_6390,
4243 .name = "Marvell 88E6191",
4244 .num_databases = 4096,
4245 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004246 .num_internal_phys = 9,
Vivien Didelot931d1822017-05-01 14:05:27 -04004247 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004248 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004249 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004250 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004251 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004252 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004253 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004254 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004255 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004256 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004257 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004258 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004259 .ptp_support = true,
Vivien Didelot2cf4cefb2017-03-28 13:50:34 -04004260 .ops = &mv88e6191_ops,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004261 },
4262
Vivien Didelotf81ec902016-05-09 13:22:58 -04004263 [MV88E6240] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004265 .family = MV88E6XXX_FAMILY_6352,
4266 .name = "Marvell 88E6240",
4267 .num_databases = 4096,
4268 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004269 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004270 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004271 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004272 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004273 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004274 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004275 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004276 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004277 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004278 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004279 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004280 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004281 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004282 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004283 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004284 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004285 },
4286
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004287 [MV88E6250] = {
4288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4289 .family = MV88E6XXX_FAMILY_6250,
4290 .name = "Marvell 88E6250",
4291 .num_databases = 64,
4292 .num_ports = 7,
4293 .num_internal_phys = 5,
4294 .max_vid = 4095,
4295 .port_base_addr = 0x08,
4296 .phy_base_addr = 0x00,
4297 .global1_addr = 0x0f,
4298 .global2_addr = 0x07,
4299 .age_time_coeff = 15000,
4300 .g1_irqs = 9,
4301 .g2_irqs = 10,
4302 .atu_move_port_mask = 0xf,
4303 .dual_chip = true,
4304 .tag_protocol = DSA_TAG_PROTO_DSA,
4305 .ops = &mv88e6250_ops,
4306 },
4307
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004308 [MV88E6290] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004309 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004310 .family = MV88E6XXX_FAMILY_6390,
4311 .name = "Marvell 88E6290",
4312 .num_databases = 4096,
4313 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004314 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004315 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004316 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004317 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004318 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004319 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004320 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004321 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004322 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004323 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004324 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004325 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004326 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004327 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004328 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004329 .ops = &mv88e6290_ops,
4330 },
4331
Vivien Didelotf81ec902016-05-09 13:22:58 -04004332 [MV88E6320] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004333 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004334 .family = MV88E6XXX_FAMILY_6320,
4335 .name = "Marvell 88E6320",
4336 .num_databases = 4096,
4337 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004338 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004339 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004340 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004341 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004342 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004343 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004344 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004345 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004346 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004347 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004348 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004349 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004350 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004351 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004352 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004353 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004354 },
4355
4356 [MV88E6321] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004357 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004358 .family = MV88E6XXX_FAMILY_6320,
4359 .name = "Marvell 88E6321",
4360 .num_databases = 4096,
4361 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004362 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004363 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004364 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004365 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004366 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004367 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004368 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004369 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004370 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004371 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004372 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004373 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004374 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004375 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004376 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004377 },
4378
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004379 [MV88E6341] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004380 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004381 .family = MV88E6XXX_FAMILY_6341,
4382 .name = "Marvell 88E6341",
4383 .num_databases = 4096,
Andrew Lunnbc393152018-03-17 20:32:04 +01004384 .num_internal_phys = 5,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004385 .num_ports = 6,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004386 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004387 .max_vid = 4095,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004388 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004389 .phy_base_addr = 0x10,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004390 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004391 .global2_addr = 0x1c,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004392 .age_time_coeff = 3750,
Vivien Didelote606ca32017-03-11 16:12:55 -05004393 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01004394 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004395 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04004396 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004397 .multi_chip = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004398 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004399 .ptp_support = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004400 .ops = &mv88e6341_ops,
4401 },
4402
Vivien Didelotf81ec902016-05-09 13:22:58 -04004403 [MV88E6350] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004404 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004405 .family = MV88E6XXX_FAMILY_6351,
4406 .name = "Marvell 88E6350",
4407 .num_databases = 4096,
4408 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004409 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004410 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004411 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004412 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004413 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004414 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004415 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004416 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004417 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004418 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004419 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004420 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004421 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004422 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004423 },
4424
4425 [MV88E6351] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004426 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004427 .family = MV88E6XXX_FAMILY_6351,
4428 .name = "Marvell 88E6351",
4429 .num_databases = 4096,
4430 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004431 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004432 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004433 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004434 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004435 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004436 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004437 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004438 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004439 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004440 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004441 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004442 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004443 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004444 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004445 },
4446
4447 [MV88E6352] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004448 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004449 .family = MV88E6XXX_FAMILY_6352,
4450 .name = "Marvell 88E6352",
4451 .num_databases = 4096,
4452 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004453 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004454 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004455 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004456 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004457 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004458 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004459 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004460 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004461 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004462 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004463 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004464 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004465 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004466 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004467 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004468 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004469 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004470 [MV88E6390] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004471 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004472 .family = MV88E6XXX_FAMILY_6390,
4473 .name = "Marvell 88E6390",
4474 .num_databases = 4096,
4475 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004476 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004477 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004478 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004479 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004480 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004481 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004482 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004483 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004484 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004485 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004486 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004487 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004488 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004489 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004490 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004491 .ops = &mv88e6390_ops,
4492 },
4493 [MV88E6390X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004494 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004495 .family = MV88E6XXX_FAMILY_6390,
4496 .name = "Marvell 88E6390X",
4497 .num_databases = 4096,
4498 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004499 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004500 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004501 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004502 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004503 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004504 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004505 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004506 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004507 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004508 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004509 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004510 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004511 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004512 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004513 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004514 .ops = &mv88e6390x_ops,
4515 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04004516};
4517
Vivien Didelot5f7c0362016-06-20 13:14:04 -04004518static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04004519{
Vivien Didelota439c062016-04-17 13:23:58 -04004520 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04004521
Vivien Didelot5f7c0362016-06-20 13:14:04 -04004522 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4523 if (mv88e6xxx_table[i].prod_num == prod_num)
4524 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04004525
Vivien Didelotb9b37712015-10-30 19:39:48 -04004526 return NULL;
4527}
4528
Vivien Didelotfad09c72016-06-21 12:28:20 -04004529static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004530{
4531 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04004532 unsigned int prod_num, rev;
4533 u16 id;
4534 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004535
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004536 mv88e6xxx_reg_lock(chip);
Vivien Didelot107fcc12017-06-12 12:37:36 -04004537 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004538 mv88e6xxx_reg_unlock(chip);
Vivien Didelot8f6345b2016-07-20 18:18:36 -04004539 if (err)
4540 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004541
Vivien Didelot107fcc12017-06-12 12:37:36 -04004542 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4543 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004544
4545 info = mv88e6xxx_lookup_info(prod_num);
4546 if (!info)
4547 return -ENODEV;
4548
Vivien Didelotcaac8542016-06-20 13:14:09 -04004549 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04004550 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004551
Vivien Didelotca070c12016-09-02 14:45:34 -04004552 err = mv88e6xxx_g2_require(chip);
4553 if (err)
4554 return err;
4555
Vivien Didelotfad09c72016-06-21 12:28:20 -04004556 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4557 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004558
4559 return 0;
4560}
4561
Vivien Didelotfad09c72016-06-21 12:28:20 -04004562static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04004563{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004564 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04004565
Vivien Didelotfad09c72016-06-21 12:28:20 -04004566 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4567 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04004568 return NULL;
4569
Vivien Didelotfad09c72016-06-21 12:28:20 -04004570 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04004571
Vivien Didelotfad09c72016-06-21 12:28:20 -04004572 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01004573 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelot469d7292016-06-20 13:14:06 -04004574
Vivien Didelotfad09c72016-06-21 12:28:20 -04004575 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04004576}
4577
Florian Fainelli5ed4e3e2017-11-10 15:22:52 -08004578static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4579 int port)
Andrew Lunn7b314362016-08-22 16:01:01 +02004580{
Vivien Didelot04bed142016-08-31 18:06:13 -04004581 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02004582
Andrew Lunn443d5a12016-12-03 04:35:18 +01004583 return chip->info->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02004584}
4585
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004586static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
Vivien Didelot3709aad2017-11-30 11:23:58 -05004587 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004588{
4589 /* We don't need any dynamic resource from the kernel (yet),
4590 * so skip the prepare phase.
4591 */
4592
4593 return 0;
4594}
4595
4596static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
Vivien Didelot3709aad2017-11-30 11:23:58 -05004597 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004598{
Vivien Didelot04bed142016-08-31 18:06:13 -04004599 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004600
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004601 mv88e6xxx_reg_lock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004602 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
Vivien Didelot27c0e602017-06-15 12:14:01 -04004603 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
Vivien Didelot774439e52017-06-08 18:34:08 -04004604 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4605 port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004606 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004607}
4608
4609static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4610 const struct switchdev_obj_port_mdb *mdb)
4611{
Vivien Didelot04bed142016-08-31 18:06:13 -04004612 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004613 int err;
4614
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004615 mv88e6xxx_reg_lock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004616 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
Vivien Didelot27c0e602017-06-15 12:14:01 -04004617 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004618 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004619
4620 return err;
4621}
4622
Russell King4f859012019-02-20 15:35:05 -08004623static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
4624 bool unicast, bool multicast)
4625{
4626 struct mv88e6xxx_chip *chip = ds->priv;
4627 int err = -EOPNOTSUPP;
4628
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004629 mv88e6xxx_reg_lock(chip);
Russell King4f859012019-02-20 15:35:05 -08004630 if (chip->info->ops->port_set_egress_floods)
4631 err = chip->info->ops->port_set_egress_floods(chip, port,
4632 unicast,
4633 multicast);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004634 mv88e6xxx_reg_unlock(chip);
Russell King4f859012019-02-20 15:35:05 -08004635
4636 return err;
4637}
4638
Florian Fainellia82f67a2017-01-08 14:52:08 -08004639static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunn7b314362016-08-22 16:01:01 +02004640 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004641 .setup = mv88e6xxx_setup,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004642 .adjust_link = mv88e6xxx_adjust_link,
Russell Kingc9a23562018-05-10 13:17:35 -07004643 .phylink_validate = mv88e6xxx_validate,
4644 .phylink_mac_link_state = mv88e6xxx_link_state,
4645 .phylink_mac_config = mv88e6xxx_mac_config,
4646 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
4647 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004648 .get_strings = mv88e6xxx_get_strings,
4649 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4650 .get_sset_count = mv88e6xxx_get_sset_count,
Andrew Lunn04aca992017-05-26 01:03:24 +02004651 .port_enable = mv88e6xxx_port_enable,
4652 .port_disable = mv88e6xxx_port_disable,
Vivien Didelot08f50062017-08-01 16:32:41 -04004653 .get_mac_eee = mv88e6xxx_get_mac_eee,
4654 .set_mac_eee = mv88e6xxx_set_mac_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004655 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004656 .get_eeprom = mv88e6xxx_get_eeprom,
4657 .set_eeprom = mv88e6xxx_set_eeprom,
4658 .get_regs_len = mv88e6xxx_get_regs_len,
4659 .get_regs = mv88e6xxx_get_regs,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04004660 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004661 .port_bridge_join = mv88e6xxx_port_bridge_join,
4662 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
Russell King4f859012019-02-20 15:35:05 -08004663 .port_egress_floods = mv88e6xxx_port_egress_floods,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004664 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04004665 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004666 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4667 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4668 .port_vlan_add = mv88e6xxx_port_vlan_add,
4669 .port_vlan_del = mv88e6xxx_port_vlan_del,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004670 .port_fdb_add = mv88e6xxx_port_fdb_add,
4671 .port_fdb_del = mv88e6xxx_port_fdb_del,
4672 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004673 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4674 .port_mdb_add = mv88e6xxx_port_mdb_add,
4675 .port_mdb_del = mv88e6xxx_port_mdb_del,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04004676 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4677 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01004678 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4679 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4680 .port_txtstamp = mv88e6xxx_port_txtstamp,
4681 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4682 .get_ts_info = mv88e6xxx_get_ts_info,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004683};
4684
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004685static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004686{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004687 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004688 struct dsa_switch *ds;
4689
Vivien Didelot73b12042017-03-30 17:37:10 -04004690 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004691 if (!ds)
4692 return -ENOMEM;
4693
Vivien Didelotfad09c72016-06-21 12:28:20 -04004694 ds->priv = chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004695 ds->dev = dev;
Vivien Didelot9d490b42016-08-23 12:38:56 -04004696 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelot9ff74f22017-03-15 15:53:50 -04004697 ds->ageing_time_min = chip->info->age_time_coeff;
4698 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004699
4700 dev_set_drvdata(dev, ds);
4701
Vivien Didelot23c9ee42017-05-26 18:12:51 -04004702 return dsa_register_switch(ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004703}
4704
Vivien Didelotfad09c72016-06-21 12:28:20 -04004705static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004706{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004707 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004708}
4709
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004710static const void *pdata_device_get_match_data(struct device *dev)
4711{
4712 const struct of_device_id *matches = dev->driver->of_match_table;
4713 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4714
4715 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4716 matches++) {
4717 if (!strcmp(pdata->compatible, matches->compatible))
4718 return matches->data;
4719 }
4720 return NULL;
4721}
4722
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01004723/* There is no suspend to RAM support at DSA level yet, the switch configuration
4724 * would be lost after a power cycle so prevent it to be suspended.
4725 */
4726static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
4727{
4728 return -EOPNOTSUPP;
4729}
4730
4731static int __maybe_unused mv88e6xxx_resume(struct device *dev)
4732{
4733 return 0;
4734}
4735
4736static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
4737
Vivien Didelot57d32312016-06-20 13:13:58 -04004738static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004739{
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004740 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
David S. Miller7ddae242018-05-20 19:04:24 -04004741 const struct mv88e6xxx_info *compat_info = NULL;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004742 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004743 struct device_node *np = dev->of_node;
Vivien Didelotfad09c72016-06-21 12:28:20 -04004744 struct mv88e6xxx_chip *chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004745 int port;
Andrew Lunn52638f72016-05-10 23:27:22 +02004746 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004747
Andrew Lunn7bb8c992018-05-31 00:15:42 +02004748 if (!np && !pdata)
4749 return -EINVAL;
4750
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004751 if (np)
4752 compat_info = of_device_get_match_data(dev);
4753
4754 if (pdata) {
4755 compat_info = pdata_device_get_match_data(dev);
4756
4757 if (!pdata->netdev)
4758 return -EINVAL;
4759
4760 for (port = 0; port < DSA_MAX_PORTS; port++) {
4761 if (!(pdata->enabled_ports & (1 << port)))
4762 continue;
4763 if (strcmp(pdata->cd.port_names[port], "cpu"))
4764 continue;
4765 pdata->cd.netdev[port] = &pdata->netdev->dev;
4766 break;
4767 }
4768 }
4769
Vivien Didelotcaac8542016-06-20 13:14:09 -04004770 if (!compat_info)
4771 return -EINVAL;
4772
Vivien Didelotfad09c72016-06-21 12:28:20 -04004773 chip = mv88e6xxx_alloc_chip(dev);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004774 if (!chip) {
4775 err = -ENOMEM;
4776 goto out;
4777 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004778
Vivien Didelotfad09c72016-06-21 12:28:20 -04004779 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04004780
Vivien Didelotfad09c72016-06-21 12:28:20 -04004781 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04004782 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004783 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004784
Andrew Lunnb4308f02016-11-21 23:26:55 +01004785 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004786 if (IS_ERR(chip->reset)) {
4787 err = PTR_ERR(chip->reset);
4788 goto out;
4789 }
Baruch Siach7b75e492019-06-27 21:17:39 +03004790 if (chip->reset)
4791 usleep_range(1000, 2000);
Andrew Lunnb4308f02016-11-21 23:26:55 +01004792
Vivien Didelotfad09c72016-06-21 12:28:20 -04004793 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004794 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004795 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004796
Vivien Didelote57e5e72016-08-15 17:19:00 -04004797 mv88e6xxx_phy_init(chip);
4798
Andrew Lunn00baabe2018-05-19 22:31:35 +02004799 if (chip->info->ops->get_eeprom) {
4800 if (np)
4801 of_property_read_u32(np, "eeprom-length",
4802 &chip->eeprom_len);
4803 else
4804 chip->eeprom_len = pdata->eeprom_len;
4805 }
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004806
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004807 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004808 err = mv88e6xxx_switch_reset(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004809 mv88e6xxx_reg_unlock(chip);
Andrew Lunnb516d452016-06-04 21:17:06 +02004810 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02004811 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02004812
Andrew Lunna27415d2019-05-01 00:10:50 +02004813 if (np) {
4814 chip->irq = of_irq_get(np, 0);
4815 if (chip->irq == -EPROBE_DEFER) {
4816 err = chip->irq;
4817 goto out;
4818 }
Andrew Lunn83c0afa2016-06-04 21:17:07 +02004819 }
4820
Andrew Lunna27415d2019-05-01 00:10:50 +02004821 if (pdata)
4822 chip->irq = pdata->irq;
4823
Andrew Lunn294d7112018-02-22 22:58:32 +01004824 /* Has to be performed before the MDIO bus is created, because
Uwe Kleine-Königa7087672018-03-20 10:44:41 +01004825 * the PHYs will link their interrupts to these interrupt
Andrew Lunn294d7112018-02-22 22:58:32 +01004826 * controllers
4827 */
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004828 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01004829 if (chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02004830 err = mv88e6xxx_g1_irq_setup(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01004831 else
4832 err = mv88e6xxx_irq_poll_setup(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00004833 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004834
Andrew Lunn294d7112018-02-22 22:58:32 +01004835 if (err)
4836 goto out;
4837
4838 if (chip->info->g2_irqs > 0) {
4839 err = mv88e6xxx_g2_irq_setup(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004840 if (err)
Andrew Lunn294d7112018-02-22 22:58:32 +01004841 goto out_g1_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02004842 }
4843
Andrew Lunn294d7112018-02-22 22:58:32 +01004844 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4845 if (err)
4846 goto out_g2_irq;
4847
4848 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4849 if (err)
4850 goto out_g1_atu_prob_irq;
4851
Andrew Lunna3c53be52017-01-24 14:53:50 +01004852 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02004853 if (err)
Andrew Lunn62eb1162018-01-14 02:32:45 +01004854 goto out_g1_vtu_prob_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02004855
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004856 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004857 if (err)
4858 goto out_mdio;
4859
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004860 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02004861
4862out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01004863 mv88e6xxx_mdios_unregister(chip);
Andrew Lunn62eb1162018-01-14 02:32:45 +01004864out_g1_vtu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01004865 mv88e6xxx_g1_vtu_prob_irq_free(chip);
Andrew Lunn09776442018-01-14 02:32:44 +01004866out_g1_atu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01004867 mv88e6xxx_g1_atu_prob_irq_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004868out_g2_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01004869 if (chip->info->g2_irqs > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02004870 mv88e6xxx_g2_irq_free(chip);
4871out_g1_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01004872 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01004873 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01004874 else
4875 mv88e6xxx_irq_poll_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004876out:
Andrew Lunn877b7cb2018-05-19 22:31:34 +02004877 if (pdata)
4878 dev_put(pdata->netdev);
4879
Andrew Lunndc30c352016-10-16 19:56:49 +02004880 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004881}
4882
4883static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4884{
4885 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vivien Didelot04bed142016-08-31 18:06:13 -04004886 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004887
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01004888 if (chip->info->ptp_support) {
4889 mv88e6xxx_hwtstamp_free(chip);
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004890 mv88e6xxx_ptp_free(chip);
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01004891 }
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004892
Andrew Lunn930188c2016-08-22 16:01:03 +02004893 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04004894 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01004895 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004896
Andrew Lunn76f38f12018-03-17 20:21:09 +01004897 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4898 mv88e6xxx_g1_atu_prob_irq_free(chip);
4899
4900 if (chip->info->g2_irqs > 0)
4901 mv88e6xxx_g2_irq_free(chip);
4902
Andrew Lunn76f38f12018-03-17 20:21:09 +01004903 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01004904 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn76f38f12018-03-17 20:21:09 +01004905 else
4906 mv88e6xxx_irq_poll_free(chip);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004907}
4908
4909static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04004910 {
4911 .compatible = "marvell,mv88e6085",
4912 .data = &mv88e6xxx_table[MV88E6085],
4913 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004914 {
4915 .compatible = "marvell,mv88e6190",
4916 .data = &mv88e6xxx_table[MV88E6190],
4917 },
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004918 {
4919 .compatible = "marvell,mv88e6250",
4920 .data = &mv88e6xxx_table[MV88E6250],
4921 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004922 { /* sentinel */ },
4923};
4924
4925MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4926
4927static struct mdio_driver mv88e6xxx_driver = {
4928 .probe = mv88e6xxx_probe,
4929 .remove = mv88e6xxx_remove,
4930 .mdiodrv.driver = {
4931 .name = "mv88e6085",
4932 .of_match_table = mv88e6xxx_of_match,
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01004933 .pm = &mv88e6xxx_pm_ops,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004934 },
4935};
4936
Andrew Lunn7324d502019-04-27 19:19:10 +02004937mdio_module_driver(mv88e6xxx_driver);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00004938
4939MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4940MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4941MODULE_LICENSE("GPL");