blob: 03dc886ed3d6be1747d5cef7616f2eb3074a5492 [file] [log] [blame]
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04002 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00004 * Copyright (c) 2008 Marvell Semiconductor
5 *
Vivien Didelotb8fee952015-08-13 12:52:19 -04006 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02009 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
Barry Grussling19b2f972013-01-08 16:05:54 +000017#include <linux/delay.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070018#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020019#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070020#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020021#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000024#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000025#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020026#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000027#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040028#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020029#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020030#include <linux/of_mdio.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000031#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010032#include <linux/gpio/consumer.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000033#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000034#include <net/dsa.h>
Vivien Didelot1f36faf2015-10-08 11:35:13 -040035#include <net/switchdev.h>
Vivien Didelotec561272016-09-02 14:45:33 -040036
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000037#include "mv88e6xxx.h"
Vivien Didelota935c052016-09-29 12:21:53 -040038#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040039#include "global2.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010040#include "port.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000041
Vivien Didelotfad09c72016-06-21 12:28:20 -040042static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040043{
Vivien Didelotfad09c72016-06-21 12:28:20 -040044 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040046 dump_stack();
47 }
48}
49
Vivien Didelot914b32f2016-06-20 13:14:11 -040050/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000060 */
Vivien Didelot914b32f2016-06-20 13:14:11 -040061
Vivien Didelotfad09c72016-06-21 12:28:20 -040062static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040063 int addr, int reg, u16 *val)
64{
Vivien Didelotfad09c72016-06-21 12:28:20 -040065 if (!chip->smi_ops)
Vivien Didelot914b32f2016-06-20 13:14:11 -040066 return -EOPNOTSUPP;
67
Vivien Didelotfad09c72016-06-21 12:28:20 -040068 return chip->smi_ops->read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040069}
70
Vivien Didelotfad09c72016-06-21 12:28:20 -040071static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040072 int addr, int reg, u16 val)
73{
Vivien Didelotfad09c72016-06-21 12:28:20 -040074 if (!chip->smi_ops)
Vivien Didelot914b32f2016-06-20 13:14:11 -040075 return -EOPNOTSUPP;
76
Vivien Didelotfad09c72016-06-21 12:28:20 -040077 return chip->smi_ops->write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040078}
79
Vivien Didelotfad09c72016-06-21 12:28:20 -040080static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040081 int addr, int reg, u16 *val)
82{
83 int ret;
84
Vivien Didelotfad09c72016-06-21 12:28:20 -040085 ret = mdiobus_read_nested(chip->bus, addr, reg);
Vivien Didelot914b32f2016-06-20 13:14:11 -040086 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
Vivien Didelotfad09c72016-06-21 12:28:20 -040094static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040095 int addr, int reg, u16 val)
96{
97 int ret;
98
Vivien Didelotfad09c72016-06-21 12:28:20 -040099 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
Vivien Didelotc08026a2016-09-29 12:21:59 -0400106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
Vivien Didelot914b32f2016-06-20 13:14:11 -0400107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
Vivien Didelotfad09c72016-06-21 12:28:20 -0400111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000118 if (ret < 0)
119 return ret;
120
Andrew Lunncca8b132015-04-02 04:06:39 +0200121 if ((ret & SMI_CMD_BUSY) == 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
Vivien Didelotfad09c72016-06-21 12:28:20 -0400128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400129 int addr, int reg, u16 *val)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000130{
131 int ret;
132
Barry Grussling3675c8d2013-01-08 16:05:53 +0000133 /* Wait for the bus to become free. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000135 if (ret < 0)
136 return ret;
137
Barry Grussling3675c8d2013-01-08 16:05:53 +0000138 /* Transmit the read command. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
Neil Armstrong6e899e62015-10-22 10:37:53 +0200140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000141 if (ret < 0)
142 return ret;
143
Barry Grussling3675c8d2013-01-08 16:05:53 +0000144 /* Wait for the read command to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000146 if (ret < 0)
147 return ret;
148
Barry Grussling3675c8d2013-01-08 16:05:53 +0000149 /* Read the data. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000151 if (ret < 0)
152 return ret;
153
Vivien Didelot914b32f2016-06-20 13:14:11 -0400154 *val = ret & 0xffff;
155
156 return 0;
157}
158
Vivien Didelotfad09c72016-06-21 12:28:20 -0400159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400160 int addr, int reg, u16 val)
161{
162 int ret;
163
164 /* Wait for the bus to become free. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400166 if (ret < 0)
167 return ret;
168
169 /* Transmit the data to write. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400171 if (ret < 0)
172 return ret;
173
174 /* Transmit the write command. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
177 if (ret < 0)
178 return ret;
179
180 /* Wait for the write command to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
Vivien Didelotc08026a2016-09-29 12:21:59 -0400188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
Vivien Didelot914b32f2016-06-20 13:14:11 -0400189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
Vivien Didelotec561272016-09-02 14:45:33 -0400193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -0400194{
195 int err;
196
Vivien Didelotfad09c72016-06-21 12:28:20 -0400197 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400198
Vivien Didelotfad09c72016-06-21 12:28:20 -0400199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400200 if (err)
201 return err;
202
Vivien Didelotfad09c72016-06-21 12:28:20 -0400203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -0400204 addr, reg, *val);
205
206 return 0;
207}
208
Vivien Didelotec561272016-09-02 14:45:33 -0400209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -0400210{
211 int err;
212
Vivien Didelotfad09c72016-06-21 12:28:20 -0400213 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400214
Vivien Didelotfad09c72016-06-21 12:28:20 -0400215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400216 if (err)
217 return err;
218
Vivien Didelotfad09c72016-06-21 12:28:20 -0400219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -0400220 addr, reg, val);
221
222 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000223}
224
Andrew Lunnee26a222017-01-24 14:53:48 +0100225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
Andrew Lunnefb3e742017-01-24 14:53:47 +0100228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
Andrew Lunnee26a222017-01-24 14:53:48 +0100232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
Andrew Lunnefb3e742017-01-24 14:53:47 +0100235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
Andrew Lunna3c53be52017-01-24 14:53:50 +0100239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
Vivien Didelote57e5e72016-08-15 17:19:00 -0400251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
Andrew Lunna3c53be52017-01-24 14:53:50 +0100255 struct mii_bus *bus;
Vivien Didelote57e5e72016-08-15 17:19:00 -0400256
Andrew Lunna3c53be52017-01-24 14:53:50 +0100257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
Vivien Didelote57e5e72016-08-15 17:19:00 -0400259 return -EOPNOTSUPP;
260
Andrew Lunna3c53be52017-01-24 14:53:50 +0100261 if (!chip->info->ops->phy_read)
Andrew Lunnee26a222017-01-24 14:53:48 +0100262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
Vivien Didelote57e5e72016-08-15 17:19:00 -0400265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
Andrew Lunna3c53be52017-01-24 14:53:50 +0100271 struct mii_bus *bus;
Vivien Didelote57e5e72016-08-15 17:19:00 -0400272
Andrew Lunna3c53be52017-01-24 14:53:50 +0100273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
Vivien Didelote57e5e72016-08-15 17:19:00 -0400275 return -EOPNOTSUPP;
276
Andrew Lunna3c53be52017-01-24 14:53:50 +0100277 if (!chip->info->ops->phy_write)
Andrew Lunnee26a222017-01-24 14:53:48 +0100278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
Vivien Didelote57e5e72016-08-15 17:19:00 -0400281}
282
Vivien Didelot09cb7df2016-08-15 17:19:01 -0400283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
Andrew Lunndc30c352016-10-16 19:56:49 +0200351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200459
Andreas Färber5edef2f2016-11-27 23:26:28 +0100460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200462 irq_dispose_mapping(virq);
463 }
464
Andrew Lunna3db3d32016-11-20 20:14:14 +0100465 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100470 int err, irq, virq;
471 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200487 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100488 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200489
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200491
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200493 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100494 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100499 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100506 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200507
508 return 0;
509
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200521
522 return err;
523}
524
Vivien Didelotec561272016-09-02 14:45:33 -0400525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
Vivien Didelot2d79af62016-08-15 17:18:57 -0400526{
Andrew Lunn6441e6692016-08-19 00:01:55 +0200527 int i;
Vivien Didelot2d79af62016-08-15 17:18:57 -0400528
Andrew Lunn6441e6692016-08-19 00:01:55 +0200529 for (i = 0; i < 16; i++) {
Vivien Didelot2d79af62016-08-15 17:18:57 -0400530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
Andrew Lunn30853552016-08-19 00:01:57 +0200543 dev_err(chip->dev, "Timeout while waiting for switch\n");
Vivien Didelot2d79af62016-08-15 17:18:57 -0400544 return -ETIMEDOUT;
545}
546
Vivien Didelotf22ab642016-07-18 20:45:31 -0400547/* Indirect write to single pointer-data register with an Update bit */
Vivien Didelotec561272016-09-02 14:45:33 -0400548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
Vivien Didelotf22ab642016-07-18 20:45:31 -0400549{
550 u16 val;
Andrew Lunn0f02b4f2016-08-19 00:01:56 +0200551 int err;
Vivien Didelotf22ab642016-07-18 20:45:31 -0400552
553 /* Wait until the previous operation is completed */
Andrew Lunn0f02b4f2016-08-19 00:01:56 +0200554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
Vivien Didelotf22ab642016-07-18 20:45:31 -0400557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
Vivien Didelota935c052016-09-29 12:21:53 -0400564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000565{
Vivien Didelota199d8b2016-12-05 17:30:28 -0500566 if (!chip->info->ops->ppu_disable)
567 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000568
Vivien Didelota199d8b2016-12-05 17:30:28 -0500569 return chip->info->ops->ppu_disable(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000570}
571
Vivien Didelotfad09c72016-06-21 12:28:20 -0400572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000573{
Vivien Didelota199d8b2016-12-05 17:30:28 -0500574 if (!chip->info->ops->ppu_enable)
575 return 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000576
Vivien Didelota199d8b2016-12-05 17:30:28 -0500577 return chip->info->ops->ppu_enable(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400582 struct mv88e6xxx_chip *chip;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000583
Vivien Didelotfad09c72016-06-21 12:28:20 -0400584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
Vivien Didelot762eb672016-06-04 21:16:54 +0200585
Vivien Didelotfad09c72016-06-21 12:28:20 -0400586 mutex_lock(&chip->reg_lock);
Vivien Didelot762eb672016-06-04 21:16:54 +0200587
Vivien Didelotfad09c72016-06-21 12:28:20 -0400588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000592 }
Vivien Didelot762eb672016-06-04 21:16:54 +0200593
Vivien Didelotfad09c72016-06-21 12:28:20 -0400594 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400599 struct mv88e6xxx_chip *chip = (void *)_ps;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000600
Vivien Didelotfad09c72016-06-21 12:28:20 -0400601 schedule_work(&chip->ppu_work);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000602}
603
Vivien Didelotfad09c72016-06-21 12:28:20 -0400604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000605{
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000606 int ret;
607
Vivien Didelotfad09c72016-06-21 12:28:20 -0400608 mutex_lock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000609
Barry Grussling3675c8d2013-01-08 16:05:53 +0000610 /* If the PHY polling unit is enabled, disable it so that
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
Barry Grussling85686582013-01-08 16:05:56 +0000617 if (ret < 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400618 mutex_unlock(&chip->ppu_mutex);
Barry Grussling85686582013-01-08 16:05:56 +0000619 return ret;
620 }
Vivien Didelotfad09c72016-06-21 12:28:20 -0400621 chip->ppu_disabled = 1;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000622 } else {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400623 del_timer(&chip->ppu_timer);
Barry Grussling85686582013-01-08 16:05:56 +0000624 ret = 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000625 }
626
627 return ret;
628}
629
Vivien Didelotfad09c72016-06-21 12:28:20 -0400630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000631{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000632 /* Schedule a timer to re-enable the PHY polling unit. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000635}
636
Vivien Didelotfad09c72016-06-21 12:28:20 -0400637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000638{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
Wei Yongjun68497a82016-10-22 14:28:00 +0000641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000643}
644
Andrew Lunn930188c2016-08-22 16:01:03 +0200645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
Andrew Lunnee26a222017-01-24 14:53:48 +0100650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000653{
Vivien Didelote57e5e72016-08-15 17:19:00 -0400654 int err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000655
Vivien Didelote57e5e72016-08-15 17:19:00 -0400656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
Vivien Didelotfad09c72016-06-21 12:28:20 -0400659 mv88e6xxx_ppu_access_put(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000660 }
661
Vivien Didelote57e5e72016-08-15 17:19:00 -0400662 return err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000663}
664
Andrew Lunnee26a222017-01-24 14:53:48 +0100665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000668{
Vivien Didelote57e5e72016-08-15 17:19:00 -0400669 int err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000670
Vivien Didelote57e5e72016-08-15 17:19:00 -0400671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
Vivien Didelotfad09c72016-06-21 12:28:20 -0400674 mv88e6xxx_ppu_access_put(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000675 }
676
Vivien Didelote57e5e72016-08-15 17:19:00 -0400677 return err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000678}
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000679
Vivien Didelotfad09c72016-06-21 12:28:20 -0400680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200681{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400682 return chip->info->family == MV88E6XXX_FAMILY_6097;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200683}
684
Vivien Didelotfad09c72016-06-21 12:28:20 -0400685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200686{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400687 return chip->info->family == MV88E6XXX_FAMILY_6165;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200688}
689
Vivien Didelotfad09c72016-06-21 12:28:20 -0400690static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -0700691{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400692 return chip->info->family == MV88E6XXX_FAMILY_6320;
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -0700693}
694
Gregory CLEMENTa75961d2017-01-30 20:29:34 +0100695static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
696{
697 return chip->info->family == MV88E6XXX_FAMILY_6341;
698}
699
Vivien Didelotfad09c72016-06-21 12:28:20 -0400700static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200701{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400702 return chip->info->family == MV88E6XXX_FAMILY_6351;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200703}
704
Vivien Didelotfad09c72016-06-21 12:28:20 -0400705static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
Andrew Lunnf3a8b6b2015-04-02 04:06:40 +0200706{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400707 return chip->info->family == MV88E6XXX_FAMILY_6352;
Andrew Lunnf3a8b6b2015-04-02 04:06:40 +0200708}
709
Vivien Didelotd78343d2016-11-04 03:23:36 +0100710static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
711 int link, int speed, int duplex,
712 phy_interface_t mode)
713{
714 int err;
715
716 if (!chip->info->ops->port_set_link)
717 return 0;
718
719 /* Port's MAC control must not be changed unless the link is down */
720 err = chip->info->ops->port_set_link(chip, port, 0);
721 if (err)
722 return err;
723
724 if (chip->info->ops->port_set_speed) {
725 err = chip->info->ops->port_set_speed(chip, port, speed);
726 if (err && err != -EOPNOTSUPP)
727 goto restore_link;
728 }
729
730 if (chip->info->ops->port_set_duplex) {
731 err = chip->info->ops->port_set_duplex(chip, port, duplex);
732 if (err && err != -EOPNOTSUPP)
733 goto restore_link;
734 }
735
736 if (chip->info->ops->port_set_rgmii_delay) {
737 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
738 if (err && err != -EOPNOTSUPP)
739 goto restore_link;
740 }
741
Andrew Lunnf39908d2017-02-04 20:02:50 +0100742 if (chip->info->ops->port_set_cmode) {
743 err = chip->info->ops->port_set_cmode(chip, port, mode);
744 if (err && err != -EOPNOTSUPP)
745 goto restore_link;
746 }
747
Vivien Didelotd78343d2016-11-04 03:23:36 +0100748 err = 0;
749restore_link:
750 if (chip->info->ops->port_set_link(chip, port, link))
751 netdev_err(chip->ds->ports[port].netdev,
752 "failed to restore MAC's link\n");
753
754 return err;
755}
756
Andrew Lunndea87022015-08-31 15:56:47 +0200757/* We expect the switch to perform auto negotiation if there is a real
758 * phy. However, in the case of a fixed link phy, we force the port
759 * settings from the fixed link settings.
760 */
Vivien Didelotf81ec902016-05-09 13:22:58 -0400761static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
762 struct phy_device *phydev)
Andrew Lunndea87022015-08-31 15:56:47 +0200763{
Vivien Didelot04bed142016-08-31 18:06:13 -0400764 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200765 int err;
Andrew Lunndea87022015-08-31 15:56:47 +0200766
767 if (!phy_is_pseudo_fixed_link(phydev))
768 return;
769
Vivien Didelotfad09c72016-06-21 12:28:20 -0400770 mutex_lock(&chip->reg_lock);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100771 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
772 phydev->duplex, phydev->interface);
Vivien Didelotfad09c72016-06-21 12:28:20 -0400773 mutex_unlock(&chip->reg_lock);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100774
775 if (err && err != -EOPNOTSUPP)
776 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
Andrew Lunndea87022015-08-31 15:56:47 +0200777}
778
Andrew Lunna605a0f2016-11-21 23:26:58 +0100779static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000780{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100781 if (!chip->info->ops->stats_snapshot)
782 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000783
Andrew Lunna605a0f2016-11-21 23:26:58 +0100784 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000785}
786
Andrew Lunne413e7e2015-04-02 04:06:38 +0200787static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100788 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
789 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
790 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
791 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
792 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
793 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
794 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
795 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
796 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
797 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
798 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
799 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
800 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
801 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
802 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
803 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
804 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
805 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
806 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
807 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
808 { "single", 4, 0x14, STATS_TYPE_BANK0, },
809 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
810 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
811 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
812 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
813 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
814 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
815 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
816 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
817 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
818 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
819 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
820 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
821 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
822 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
823 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
824 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
826 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
828 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
829 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
830 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
831 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
832 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
833 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
834 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
835 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
836 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
837 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
838 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
839 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
840 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
841 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
842 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
843 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
844 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
845 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
846 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200847};
848
Vivien Didelotfad09c72016-06-21 12:28:20 -0400849static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100850 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100851 int port, u16 bank1_select,
852 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200853{
Andrew Lunn80c46272015-06-20 18:42:30 +0200854 u32 low;
855 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100856 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200857 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200858 u64 value;
859
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100860 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100861 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200862 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
863 if (err)
Andrew Lunn80c46272015-06-20 18:42:30 +0200864 return UINT64_MAX;
865
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200866 low = reg;
Andrew Lunn80c46272015-06-20 18:42:30 +0200867 if (s->sizeof_stat == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200868 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
869 if (err)
Andrew Lunn80c46272015-06-20 18:42:30 +0200870 return UINT64_MAX;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200871 high = reg;
Andrew Lunn80c46272015-06-20 18:42:30 +0200872 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100873 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100874 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100875 reg = bank1_select;
Andrew Lunndfafe442016-11-21 23:27:02 +0100876 /* fall through */
877 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100878 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100879 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunn80c46272015-06-20 18:42:30 +0200880 if (s->sizeof_stat == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100881 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Andrew Lunn80c46272015-06-20 18:42:30 +0200882 }
883 value = (((u64)high) << 16) | low;
884 return value;
885}
886
Andrew Lunndfafe442016-11-21 23:27:02 +0100887static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
888 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100889{
890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
892
893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100895 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100896 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
897 ETH_GSTRING_LEN);
898 j++;
899 }
900 }
901}
902
Andrew Lunndfafe442016-11-21 23:27:02 +0100903static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
904 uint8_t *data)
905{
906 mv88e6xxx_stats_get_strings(chip, data,
907 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
908}
909
910static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
911 uint8_t *data)
912{
913 mv88e6xxx_stats_get_strings(chip, data,
914 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
915}
916
917static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
918 uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100919{
Vivien Didelot04bed142016-08-31 18:06:13 -0400920 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunndfafe442016-11-21 23:27:02 +0100921
922 if (chip->info->ops->stats_get_strings)
923 chip->info->ops->stats_get_strings(chip, data);
924}
925
926static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
927 int types)
928{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100929 struct mv88e6xxx_hw_stat *stat;
930 int i, j;
931
932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
933 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100934 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100935 j++;
936 }
937 return j;
938}
939
Andrew Lunndfafe442016-11-21 23:27:02 +0100940static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
941{
942 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
943 STATS_TYPE_PORT);
944}
945
946static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
947{
948 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
949 STATS_TYPE_BANK1);
950}
951
952static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
953{
954 struct mv88e6xxx_chip *chip = ds->priv;
955
956 if (chip->info->ops->stats_get_sset_count)
957 return chip->info->ops->stats_get_sset_count(chip);
958
959 return 0;
960}
961
Andrew Lunn052f9472016-11-21 23:27:03 +0100962static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100963 uint64_t *data, int types,
964 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +0100965{
966 struct mv88e6xxx_hw_stat *stat;
967 int i, j;
968
969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
970 stat = &mv88e6xxx_hw_stats[i];
971 if (stat->type & types) {
Andrew Lunne0d8b612016-11-21 23:27:04 +0100972 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
973 bank1_select,
974 histogram);
Andrew Lunn052f9472016-11-21 23:27:03 +0100975 j++;
976 }
977 }
978}
979
980static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
981 uint64_t *data)
982{
983 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100984 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
985 0, GLOBAL_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +0100986}
987
988static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
989 uint64_t *data)
990{
991 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100992 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
993 GLOBAL_STATS_OP_BANK_1_BIT_9,
994 GLOBAL_STATS_OP_HIST_RX_TX);
995}
996
997static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
998 uint64_t *data)
999{
1000 return mv88e6xxx_stats_get_stats(chip, port, data,
1001 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1002 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
Andrew Lunn052f9472016-11-21 23:27:03 +01001003}
1004
1005static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1006 uint64_t *data)
1007{
1008 if (chip->info->ops->stats_get_stats)
1009 chip->info->ops->stats_get_stats(chip, port, data);
1010}
1011
Vivien Didelotf81ec902016-05-09 13:22:58 -04001012static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1013 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001014{
Vivien Didelot04bed142016-08-31 18:06:13 -04001015 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001016 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001017
Vivien Didelotfad09c72016-06-21 12:28:20 -04001018 mutex_lock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001019
Andrew Lunna605a0f2016-11-21 23:26:58 +01001020 ret = mv88e6xxx_stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001021 if (ret < 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001022 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001023 return;
1024 }
Andrew Lunn052f9472016-11-21 23:27:03 +01001025
1026 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001027
Vivien Didelotfad09c72016-06-21 12:28:20 -04001028 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001029}
Ben Hutchings98e67302011-11-25 14:36:19 +00001030
Andrew Lunnde2273872016-11-21 23:27:01 +01001031static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1032{
1033 if (chip->info->ops->stats_set_histogram)
1034 return chip->info->ops->stats_set_histogram(chip);
1035
1036 return 0;
1037}
1038
Vivien Didelotf81ec902016-05-09 13:22:58 -04001039static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001040{
1041 return 32 * sizeof(u16);
1042}
1043
Vivien Didelotf81ec902016-05-09 13:22:58 -04001044static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1045 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001046{
Vivien Didelot04bed142016-08-31 18:06:13 -04001047 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001048 int err;
1049 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001050 u16 *p = _p;
1051 int i;
1052
1053 regs->version = 0;
1054
1055 memset(p, 0xff, 32 * sizeof(u16));
1056
Vivien Didelotfad09c72016-06-21 12:28:20 -04001057 mutex_lock(&chip->reg_lock);
Vivien Didelot23062512016-05-09 13:22:45 -04001058
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001059 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001060
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001061 err = mv88e6xxx_port_read(chip, port, i, &reg);
1062 if (!err)
1063 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001064 }
Vivien Didelot23062512016-05-09 13:22:45 -04001065
Vivien Didelotfad09c72016-06-21 12:28:20 -04001066 mutex_unlock(&chip->reg_lock);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001067}
1068
Vivien Didelotfad09c72016-06-21 12:28:20 -04001069static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001070{
Vivien Didelota935c052016-09-29 12:21:53 -04001071 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001072}
1073
Vivien Didelotf81ec902016-05-09 13:22:58 -04001074static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1075 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001076{
Vivien Didelot04bed142016-08-31 18:06:13 -04001077 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot9c938292016-08-15 17:19:02 -04001078 u16 reg;
1079 int err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001080
Vivien Didelotfad09c72016-06-21 12:28:20 -04001081 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
Vivien Didelotaadbdb82016-05-09 13:22:44 -04001082 return -EOPNOTSUPP;
1083
Vivien Didelotfad09c72016-06-21 12:28:20 -04001084 mutex_lock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001085
Vivien Didelot9c938292016-08-15 17:19:02 -04001086 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1087 if (err)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001088 goto out;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001089
1090 e->eee_enabled = !!(reg & 0x0200);
1091 e->tx_lpi_enabled = !!(reg & 0x0100);
1092
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001093 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
Vivien Didelot9c938292016-08-15 17:19:02 -04001094 if (err)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001095 goto out;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001096
Andrew Lunncca8b132015-04-02 04:06:39 +02001097 e->eee_active = !!(reg & PORT_STATUS_EEE);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001098out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001099 mutex_unlock(&chip->reg_lock);
Vivien Didelot9c938292016-08-15 17:19:02 -04001100
1101 return err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001102}
1103
Vivien Didelotf81ec902016-05-09 13:22:58 -04001104static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1105 struct phy_device *phydev, struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001106{
Vivien Didelot04bed142016-08-31 18:06:13 -04001107 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot9c938292016-08-15 17:19:02 -04001108 u16 reg;
1109 int err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001110
Vivien Didelotfad09c72016-06-21 12:28:20 -04001111 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
Vivien Didelotaadbdb82016-05-09 13:22:44 -04001112 return -EOPNOTSUPP;
1113
Vivien Didelotfad09c72016-06-21 12:28:20 -04001114 mutex_lock(&chip->reg_lock);
Guenter Roeck11b3b452015-03-06 22:23:51 -08001115
Vivien Didelot9c938292016-08-15 17:19:02 -04001116 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1117 if (err)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001118 goto out;
1119
Vivien Didelot9c938292016-08-15 17:19:02 -04001120 reg &= ~0x0300;
Andrew Lunn2f40c692015-04-02 04:06:37 +02001121 if (e->eee_enabled)
1122 reg |= 0x0200;
1123 if (e->tx_lpi_enabled)
1124 reg |= 0x0100;
1125
Vivien Didelot9c938292016-08-15 17:19:02 -04001126 err = mv88e6xxx_phy_write(chip, port, 16, reg);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001127out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001128 mutex_unlock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001129
Vivien Didelot9c938292016-08-15 17:19:02 -04001130 return err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001131}
1132
Vivien Didelotfad09c72016-06-21 12:28:20 -04001133static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001134{
Vivien Didelota935c052016-09-29 12:21:53 -04001135 u16 val;
1136 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001137
Vivien Didelot6dc10bb2016-09-29 12:21:55 -04001138 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
Vivien Didelota935c052016-09-29 12:21:53 -04001139 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1140 if (err)
1141 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001142 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001143 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
Vivien Didelota935c052016-09-29 12:21:53 -04001144 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1145 if (err)
1146 return err;
Vivien Didelot11ea8092016-03-31 16:53:44 -04001147
Vivien Didelota935c052016-09-29 12:21:53 -04001148 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1149 (val & 0xfff) | ((fid << 8) & 0xf000));
1150 if (err)
1151 return err;
Vivien Didelot11ea8092016-03-31 16:53:44 -04001152
1153 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1154 cmd |= fid & 0xf;
Vivien Didelotb426e5f2016-03-31 16:53:42 -04001155 }
1156
Vivien Didelota935c052016-09-29 12:21:53 -04001157 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1158 if (err)
1159 return err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001160
Vivien Didelotfad09c72016-06-21 12:28:20 -04001161 return _mv88e6xxx_atu_wait(chip);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001162}
1163
Vivien Didelotfad09c72016-06-21 12:28:20 -04001164static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelot37705b72015-09-04 14:34:11 -04001165 struct mv88e6xxx_atu_entry *entry)
1166{
1167 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1168
1169 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1170 unsigned int mask, shift;
1171
1172 if (entry->trunk) {
1173 data |= GLOBAL_ATU_DATA_TRUNK;
1174 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1175 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1176 } else {
1177 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1178 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1179 }
1180
1181 data |= (entry->portv_trunkid << shift) & mask;
1182 }
1183
Vivien Didelota935c052016-09-29 12:21:53 -04001184 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
Vivien Didelot37705b72015-09-04 14:34:11 -04001185}
1186
Vivien Didelotfad09c72016-06-21 12:28:20 -04001187static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001188 struct mv88e6xxx_atu_entry *entry,
1189 bool static_too)
1190{
1191 int op;
1192 int err;
1193
Vivien Didelotfad09c72016-06-21 12:28:20 -04001194 err = _mv88e6xxx_atu_wait(chip);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001195 if (err)
1196 return err;
1197
Vivien Didelotfad09c72016-06-21 12:28:20 -04001198 err = _mv88e6xxx_atu_data_write(chip, entry);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001199 if (err)
1200 return err;
1201
1202 if (entry->fid) {
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001203 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1204 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1205 } else {
1206 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1207 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1208 }
1209
Vivien Didelotfad09c72016-06-21 12:28:20 -04001210 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001211}
1212
Vivien Didelotfad09c72016-06-21 12:28:20 -04001213static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001214 u16 fid, bool static_too)
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001215{
1216 struct mv88e6xxx_atu_entry entry = {
1217 .fid = fid,
1218 .state = 0, /* EntryState bits must be 0 */
1219 };
1220
Vivien Didelotfad09c72016-06-21 12:28:20 -04001221 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001222}
1223
Vivien Didelotfad09c72016-06-21 12:28:20 -04001224static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
Andrew Lunn158bc062016-04-28 21:24:06 -04001225 int from_port, int to_port, bool static_too)
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001226{
1227 struct mv88e6xxx_atu_entry entry = {
1228 .trunk = false,
1229 .fid = fid,
1230 };
1231
1232 /* EntryState bits must be 0xF */
1233 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1234
1235 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1236 entry.portv_trunkid = (to_port & 0x0f) << 4;
1237 entry.portv_trunkid |= from_port & 0x0f;
1238
Vivien Didelotfad09c72016-06-21 12:28:20 -04001239 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001240}
1241
Vivien Didelotfad09c72016-06-21 12:28:20 -04001242static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
Andrew Lunn158bc062016-04-28 21:24:06 -04001243 int port, bool static_too)
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001244{
1245 /* Destination port 0xF means remove the entries */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001246 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001247}
1248
Vivien Didelotfad09c72016-06-21 12:28:20 -04001249static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001250{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001251 struct dsa_switch *ds = chip->ds;
Vivien Didelotfae8a252017-01-27 15:29:42 -05001252 struct net_device *bridge = ds->ports[port].bridge_dev;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001253 u16 output_ports = 0;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001254 int i;
1255
1256 /* allow CPU port or DSA link(s) to send frames to every port */
1257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001258 output_ports = ~0;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001259 } else {
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001260 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001261 /* allow sending frames to every group member */
Vivien Didelotfae8a252017-01-27 15:29:42 -05001262 if (bridge && ds->ports[i].bridge_dev == bridge)
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001263 output_ports |= BIT(i);
1264
1265 /* allow sending frames to CPU port and DSA link(s) */
1266 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1267 output_ports |= BIT(i);
1268 }
1269 }
1270
1271 /* prevent frames from going back out of the port they came in on */
1272 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001273
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001274 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001275}
1276
Vivien Didelotf81ec902016-05-09 13:22:58 -04001277static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1278 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001279{
Vivien Didelot04bed142016-08-31 18:06:13 -04001280 struct mv88e6xxx_chip *chip = ds->priv;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001281 int stp_state;
Vivien Didelot553eb542016-05-13 20:38:23 -04001282 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001283
1284 switch (state) {
1285 case BR_STATE_DISABLED:
Andrew Lunncca8b132015-04-02 04:06:39 +02001286 stp_state = PORT_CONTROL_STATE_DISABLED;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001287 break;
1288 case BR_STATE_BLOCKING:
1289 case BR_STATE_LISTENING:
Andrew Lunncca8b132015-04-02 04:06:39 +02001290 stp_state = PORT_CONTROL_STATE_BLOCKING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001291 break;
1292 case BR_STATE_LEARNING:
Andrew Lunncca8b132015-04-02 04:06:39 +02001293 stp_state = PORT_CONTROL_STATE_LEARNING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001294 break;
1295 case BR_STATE_FORWARDING:
1296 default:
Andrew Lunncca8b132015-04-02 04:06:39 +02001297 stp_state = PORT_CONTROL_STATE_FORWARDING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001298 break;
1299 }
1300
Vivien Didelotfad09c72016-06-21 12:28:20 -04001301 mutex_lock(&chip->reg_lock);
Vivien Didelote28def332016-11-04 03:23:27 +01001302 err = mv88e6xxx_port_set_state(chip, port, stp_state);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001303 mutex_unlock(&chip->reg_lock);
Vivien Didelot553eb542016-05-13 20:38:23 -04001304
1305 if (err)
Vivien Didelote28def332016-11-04 03:23:27 +01001306 netdev_err(ds->ports[port].netdev, "failed to update state\n");
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001307}
1308
Vivien Didelot749efcb2016-09-22 16:49:24 -04001309static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1310{
1311 struct mv88e6xxx_chip *chip = ds->priv;
1312 int err;
1313
1314 mutex_lock(&chip->reg_lock);
1315 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1316 mutex_unlock(&chip->reg_lock);
1317
1318 if (err)
1319 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1320}
1321
Vivien Didelotfad09c72016-06-21 12:28:20 -04001322static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
Vivien Didelot6b17e862015-08-13 12:52:18 -04001323{
Vivien Didelota935c052016-09-29 12:21:53 -04001324 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001325}
1326
Vivien Didelotfad09c72016-06-21 12:28:20 -04001327static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
Vivien Didelot6b17e862015-08-13 12:52:18 -04001328{
Vivien Didelota935c052016-09-29 12:21:53 -04001329 int err;
Vivien Didelot6b17e862015-08-13 12:52:18 -04001330
Vivien Didelota935c052016-09-29 12:21:53 -04001331 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1332 if (err)
1333 return err;
Vivien Didelot6b17e862015-08-13 12:52:18 -04001334
Vivien Didelotfad09c72016-06-21 12:28:20 -04001335 return _mv88e6xxx_vtu_wait(chip);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001336}
1337
Vivien Didelotfad09c72016-06-21 12:28:20 -04001338static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
Vivien Didelot6b17e862015-08-13 12:52:18 -04001339{
1340 int ret;
1341
Vivien Didelotfad09c72016-06-21 12:28:20 -04001342 ret = _mv88e6xxx_vtu_wait(chip);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001343 if (ret < 0)
1344 return ret;
1345
Vivien Didelotfad09c72016-06-21 12:28:20 -04001346 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001347}
1348
Vivien Didelotfad09c72016-06-21 12:28:20 -04001349static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001350 struct mv88e6xxx_vtu_entry *entry,
Vivien Didelotb8fee952015-08-13 12:52:19 -04001351 unsigned int nibble_offset)
1352{
Vivien Didelotb8fee952015-08-13 12:52:19 -04001353 u16 regs[3];
Vivien Didelota935c052016-09-29 12:21:53 -04001354 int i, err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001355
1356 for (i = 0; i < 3; ++i) {
Vivien Didelota935c052016-09-29 12:21:53 -04001357 u16 *reg = &regs[i];
Vivien Didelotb8fee952015-08-13 12:52:19 -04001358
Vivien Didelota935c052016-09-29 12:21:53 -04001359 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1360 if (err)
1361 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001362 }
1363
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001364 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotb8fee952015-08-13 12:52:19 -04001365 unsigned int shift = (i % 4) * 4 + nibble_offset;
1366 u16 reg = regs[i / 4];
1367
1368 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1369 }
1370
1371 return 0;
1372}
1373
Vivien Didelotfad09c72016-06-21 12:28:20 -04001374static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001375 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001376{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001377 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001378}
1379
Vivien Didelotfad09c72016-06-21 12:28:20 -04001380static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001381 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001382{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001383 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001384}
1385
Vivien Didelotfad09c72016-06-21 12:28:20 -04001386static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001387 struct mv88e6xxx_vtu_entry *entry,
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001388 unsigned int nibble_offset)
1389{
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001390 u16 regs[3] = { 0 };
Vivien Didelota935c052016-09-29 12:21:53 -04001391 int i, err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001392
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001393 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001394 unsigned int shift = (i % 4) * 4 + nibble_offset;
1395 u8 data = entry->data[i];
1396
1397 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1398 }
1399
1400 for (i = 0; i < 3; ++i) {
Vivien Didelota935c052016-09-29 12:21:53 -04001401 u16 reg = regs[i];
1402
1403 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1404 if (err)
1405 return err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001406 }
1407
1408 return 0;
1409}
1410
Vivien Didelotfad09c72016-06-21 12:28:20 -04001411static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001412 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001413{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001414 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001415}
1416
Vivien Didelotfad09c72016-06-21 12:28:20 -04001417static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001418 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001419{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001420 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001421}
1422
Vivien Didelotfad09c72016-06-21 12:28:20 -04001423static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001424{
Vivien Didelota935c052016-09-29 12:21:53 -04001425 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1426 vid & GLOBAL_VTU_VID_MASK);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001427}
1428
Vivien Didelotfad09c72016-06-21 12:28:20 -04001429static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001430 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelotb8fee952015-08-13 12:52:19 -04001431{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001432 struct mv88e6xxx_vtu_entry next = { 0 };
Vivien Didelota935c052016-09-29 12:21:53 -04001433 u16 val;
1434 int err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001435
Vivien Didelota935c052016-09-29 12:21:53 -04001436 err = _mv88e6xxx_vtu_wait(chip);
1437 if (err)
1438 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001439
Vivien Didelota935c052016-09-29 12:21:53 -04001440 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1441 if (err)
1442 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001443
Vivien Didelota935c052016-09-29 12:21:53 -04001444 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1445 if (err)
1446 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001447
Vivien Didelota935c052016-09-29 12:21:53 -04001448 next.vid = val & GLOBAL_VTU_VID_MASK;
1449 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
Vivien Didelotb8fee952015-08-13 12:52:19 -04001450
1451 if (next.valid) {
Vivien Didelota935c052016-09-29 12:21:53 -04001452 err = mv88e6xxx_vtu_data_read(chip, &next);
1453 if (err)
1454 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001455
Vivien Didelot6dc10bb2016-09-29 12:21:55 -04001456 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
Vivien Didelota935c052016-09-29 12:21:53 -04001457 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1458 if (err)
1459 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001460
Vivien Didelota935c052016-09-29 12:21:53 -04001461 next.fid = val & GLOBAL_VTU_FID_MASK;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001462 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001463 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1464 * VTU DBNum[3:0] are located in VTU Operation 3:0
1465 */
Vivien Didelota935c052016-09-29 12:21:53 -04001466 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1467 if (err)
1468 return err;
Vivien Didelot11ea8092016-03-31 16:53:44 -04001469
Vivien Didelota935c052016-09-29 12:21:53 -04001470 next.fid = (val & 0xf00) >> 4;
1471 next.fid |= val & 0xf;
Vivien Didelot2e7bd5e2016-03-31 16:53:41 -04001472 }
Vivien Didelotb8fee952015-08-13 12:52:19 -04001473
Vivien Didelotfad09c72016-06-21 12:28:20 -04001474 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
Vivien Didelota935c052016-09-29 12:21:53 -04001475 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1476 if (err)
1477 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001478
Vivien Didelota935c052016-09-29 12:21:53 -04001479 next.sid = val & GLOBAL_VTU_SID_MASK;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001480 }
1481 }
1482
1483 *entry = next;
1484 return 0;
1485}
1486
Vivien Didelotf81ec902016-05-09 13:22:58 -04001487static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1488 struct switchdev_obj_port_vlan *vlan,
1489 int (*cb)(struct switchdev_obj *obj))
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001490{
Vivien Didelot04bed142016-08-31 18:06:13 -04001491 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001492 struct mv88e6xxx_vtu_entry next;
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001493 u16 pvid;
1494 int err;
1495
Vivien Didelotfad09c72016-06-21 12:28:20 -04001496 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001497 return -EOPNOTSUPP;
1498
Vivien Didelotfad09c72016-06-21 12:28:20 -04001499 mutex_lock(&chip->reg_lock);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001500
Vivien Didelot77064f32016-11-04 03:23:30 +01001501 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001502 if (err)
1503 goto unlock;
1504
Vivien Didelotfad09c72016-06-21 12:28:20 -04001505 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001506 if (err)
1507 goto unlock;
1508
1509 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001510 err = _mv88e6xxx_vtu_getnext(chip, &next);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001511 if (err)
1512 break;
1513
1514 if (!next.valid)
1515 break;
1516
1517 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1518 continue;
1519
1520 /* reinit and dump this VLAN obj */
Vivien Didelot57d32312016-06-20 13:13:58 -04001521 vlan->vid_begin = next.vid;
1522 vlan->vid_end = next.vid;
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001523 vlan->flags = 0;
1524
1525 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1526 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1527
1528 if (next.vid == pvid)
1529 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1530
1531 err = cb(&vlan->obj);
1532 if (err)
1533 break;
1534 } while (next.vid < GLOBAL_VTU_VID_MASK);
1535
1536unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001537 mutex_unlock(&chip->reg_lock);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001538
1539 return err;
1540}
1541
Vivien Didelotfad09c72016-06-21 12:28:20 -04001542static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001543 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001544{
Vivien Didelot11ea8092016-03-31 16:53:44 -04001545 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001546 u16 reg = 0;
Vivien Didelota935c052016-09-29 12:21:53 -04001547 int err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001548
Vivien Didelota935c052016-09-29 12:21:53 -04001549 err = _mv88e6xxx_vtu_wait(chip);
1550 if (err)
1551 return err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001552
1553 if (!entry->valid)
1554 goto loadpurge;
1555
1556 /* Write port member tags */
Vivien Didelota935c052016-09-29 12:21:53 -04001557 err = mv88e6xxx_vtu_data_write(chip, entry);
1558 if (err)
1559 return err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001560
Vivien Didelotfad09c72016-06-21 12:28:20 -04001561 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001562 reg = entry->sid & GLOBAL_VTU_SID_MASK;
Vivien Didelota935c052016-09-29 12:21:53 -04001563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1564 if (err)
1565 return err;
Vivien Didelotb426e5f2016-03-31 16:53:42 -04001566 }
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001567
Vivien Didelot6dc10bb2016-09-29 12:21:55 -04001568 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001569 reg = entry->fid & GLOBAL_VTU_FID_MASK;
Vivien Didelota935c052016-09-29 12:21:53 -04001570 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1571 if (err)
1572 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001573 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001574 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1575 * VTU DBNum[3:0] are located in VTU Operation 3:0
1576 */
1577 op |= (entry->fid & 0xf0) << 8;
1578 op |= entry->fid & 0xf;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001579 }
1580
1581 reg = GLOBAL_VTU_VID_VALID;
1582loadpurge:
1583 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
Vivien Didelota935c052016-09-29 12:21:53 -04001584 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1585 if (err)
1586 return err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001587
Vivien Didelotfad09c72016-06-21 12:28:20 -04001588 return _mv88e6xxx_vtu_cmd(chip, op);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001589}
1590
Vivien Didelotfad09c72016-06-21 12:28:20 -04001591static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001592 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001593{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001594 struct mv88e6xxx_vtu_entry next = { 0 };
Vivien Didelota935c052016-09-29 12:21:53 -04001595 u16 val;
1596 int err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001597
Vivien Didelota935c052016-09-29 12:21:53 -04001598 err = _mv88e6xxx_vtu_wait(chip);
1599 if (err)
1600 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001601
Vivien Didelota935c052016-09-29 12:21:53 -04001602 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1603 sid & GLOBAL_VTU_SID_MASK);
1604 if (err)
1605 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001606
Vivien Didelota935c052016-09-29 12:21:53 -04001607 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1608 if (err)
1609 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001610
Vivien Didelota935c052016-09-29 12:21:53 -04001611 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1612 if (err)
1613 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001614
Vivien Didelota935c052016-09-29 12:21:53 -04001615 next.sid = val & GLOBAL_VTU_SID_MASK;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001616
Vivien Didelota935c052016-09-29 12:21:53 -04001617 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1618 if (err)
1619 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001620
Vivien Didelota935c052016-09-29 12:21:53 -04001621 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001622
1623 if (next.valid) {
Vivien Didelota935c052016-09-29 12:21:53 -04001624 err = mv88e6xxx_stu_data_read(chip, &next);
1625 if (err)
1626 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001627 }
1628
1629 *entry = next;
1630 return 0;
1631}
1632
Vivien Didelotfad09c72016-06-21 12:28:20 -04001633static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001634 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001635{
1636 u16 reg = 0;
Vivien Didelota935c052016-09-29 12:21:53 -04001637 int err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001638
Vivien Didelota935c052016-09-29 12:21:53 -04001639 err = _mv88e6xxx_vtu_wait(chip);
1640 if (err)
1641 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001642
1643 if (!entry->valid)
1644 goto loadpurge;
1645
1646 /* Write port states */
Vivien Didelota935c052016-09-29 12:21:53 -04001647 err = mv88e6xxx_stu_data_write(chip, entry);
1648 if (err)
1649 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001650
1651 reg = GLOBAL_VTU_VID_VALID;
1652loadpurge:
Vivien Didelota935c052016-09-29 12:21:53 -04001653 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1654 if (err)
1655 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001656
1657 reg = entry->sid & GLOBAL_VTU_SID_MASK;
Vivien Didelota935c052016-09-29 12:21:53 -04001658 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1659 if (err)
1660 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001661
Vivien Didelotfad09c72016-06-21 12:28:20 -04001662 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001663}
1664
Vivien Didelotfad09c72016-06-21 12:28:20 -04001665static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001666{
1667 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001668 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001669 int i, err;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001670
1671 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1672
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001673 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001674 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotb4e48c52016-11-04 03:23:29 +01001675 err = mv88e6xxx_port_get_fid(chip, i, fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001676 if (err)
1677 return err;
1678
1679 set_bit(*fid, fid_bitmap);
1680 }
1681
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001682 /* Set every FID bit used by the VLAN entries */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001683 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001684 if (err)
1685 return err;
1686
1687 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001688 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001689 if (err)
1690 return err;
1691
1692 if (!vlan.valid)
1693 break;
1694
1695 set_bit(vlan.fid, fid_bitmap);
1696 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1697
1698 /* The reset value 0x000 is used to indicate that multiple address
1699 * databases are not needed. Return the next positive available.
1700 */
1701 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001702 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001703 return -ENOSPC;
1704
1705 /* Clear the database */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001706 return _mv88e6xxx_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001707}
1708
Vivien Didelotfad09c72016-06-21 12:28:20 -04001709static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001710 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001711{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001712 struct dsa_switch *ds = chip->ds;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001713 struct mv88e6xxx_vtu_entry vlan = {
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001714 .valid = true,
1715 .vid = vid,
1716 };
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001717 int i, err;
1718
Vivien Didelotfad09c72016-06-21 12:28:20 -04001719 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001720 if (err)
1721 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001722
Vivien Didelot3d131f02015-11-03 10:52:52 -05001723 /* exclude all ports except the CPU and DSA ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001724 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
Vivien Didelot3d131f02015-11-03 10:52:52 -05001725 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1726 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1727 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001728
Vivien Didelotfad09c72016-06-21 12:28:20 -04001729 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01001730 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1731 mv88e6xxx_6341_family(chip)) {
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001732 struct mv88e6xxx_vtu_entry vstp;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001733
1734 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1735 * implemented, only one STU entry is needed to cover all VTU
1736 * entries. Thus, validate the SID 0.
1737 */
1738 vlan.sid = 0;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001739 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001740 if (err)
1741 return err;
1742
1743 if (vstp.sid != vlan.sid || !vstp.valid) {
1744 memset(&vstp, 0, sizeof(vstp));
1745 vstp.valid = true;
1746 vstp.sid = vlan.sid;
1747
Vivien Didelotfad09c72016-06-21 12:28:20 -04001748 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001749 if (err)
1750 return err;
1751 }
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001752 }
1753
1754 *entry = vlan;
1755 return 0;
1756}
1757
Vivien Didelotfad09c72016-06-21 12:28:20 -04001758static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001759 struct mv88e6xxx_vtu_entry *entry, bool creat)
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001760{
1761 int err;
1762
1763 if (!vid)
1764 return -EINVAL;
1765
Vivien Didelotfad09c72016-06-21 12:28:20 -04001766 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001767 if (err)
1768 return err;
1769
Vivien Didelotfad09c72016-06-21 12:28:20 -04001770 err = _mv88e6xxx_vtu_getnext(chip, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001771 if (err)
1772 return err;
1773
1774 if (entry->vid != vid || !entry->valid) {
1775 if (!creat)
1776 return -EOPNOTSUPP;
1777 /* -ENOENT would've been more appropriate, but switchdev expects
1778 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1779 */
1780
Vivien Didelotfad09c72016-06-21 12:28:20 -04001781 err = _mv88e6xxx_vtu_new(chip, vid, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001782 }
1783
1784 return err;
1785}
1786
Vivien Didelotda9c3592016-02-12 12:09:40 -05001787static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1788 u16 vid_begin, u16 vid_end)
1789{
Vivien Didelot04bed142016-08-31 18:06:13 -04001790 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001791 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001792 int i, err;
1793
1794 if (!vid_begin)
1795 return -EOPNOTSUPP;
1796
Vivien Didelotfad09c72016-06-21 12:28:20 -04001797 mutex_lock(&chip->reg_lock);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001798
Vivien Didelotfad09c72016-06-21 12:28:20 -04001799 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001800 if (err)
1801 goto unlock;
1802
1803 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001804 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001805 if (err)
1806 goto unlock;
1807
1808 if (!vlan.valid)
1809 break;
1810
1811 if (vlan.vid > vid_end)
1812 break;
1813
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001814 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotda9c3592016-02-12 12:09:40 -05001815 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1816 continue;
1817
Andrew Lunn66e28092016-12-11 21:07:19 +01001818 if (!ds->ports[port].netdev)
1819 continue;
1820
Vivien Didelotda9c3592016-02-12 12:09:40 -05001821 if (vlan.data[i] ==
1822 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1823 continue;
1824
Vivien Didelotfae8a252017-01-27 15:29:42 -05001825 if (ds->ports[i].bridge_dev ==
1826 ds->ports[port].bridge_dev)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001827 break; /* same bridge, check next VLAN */
1828
Vivien Didelotfae8a252017-01-27 15:29:42 -05001829 if (!ds->ports[i].bridge_dev)
Andrew Lunn66e28092016-12-11 21:07:19 +01001830 continue;
1831
Andrew Lunnc8b09802016-06-04 21:16:57 +02001832 netdev_warn(ds->ports[port].netdev,
Vivien Didelotda9c3592016-02-12 12:09:40 -05001833 "hardware VLAN %d already used by %s\n",
1834 vlan.vid,
Vivien Didelotfae8a252017-01-27 15:29:42 -05001835 netdev_name(ds->ports[i].bridge_dev));
Vivien Didelotda9c3592016-02-12 12:09:40 -05001836 err = -EOPNOTSUPP;
1837 goto unlock;
1838 }
1839 } while (vlan.vid < vid_end);
1840
1841unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001842 mutex_unlock(&chip->reg_lock);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001843
1844 return err;
1845}
1846
Vivien Didelotf81ec902016-05-09 13:22:58 -04001847static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1848 bool vlan_filtering)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001849{
Vivien Didelot04bed142016-08-31 18:06:13 -04001850 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot385a0992016-11-04 03:23:31 +01001851 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
Vivien Didelot214cdb92016-02-26 13:16:08 -05001852 PORT_CONTROL_2_8021Q_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001853 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001854
Vivien Didelotfad09c72016-06-21 12:28:20 -04001855 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001856 return -EOPNOTSUPP;
1857
Vivien Didelotfad09c72016-06-21 12:28:20 -04001858 mutex_lock(&chip->reg_lock);
Vivien Didelot385a0992016-11-04 03:23:31 +01001859 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001860 mutex_unlock(&chip->reg_lock);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001861
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001862 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001863}
1864
Vivien Didelot57d32312016-06-20 13:13:58 -04001865static int
1866mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1867 const struct switchdev_obj_port_vlan *vlan,
1868 struct switchdev_trans *trans)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001869{
Vivien Didelot04bed142016-08-31 18:06:13 -04001870 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001871 int err;
1872
Vivien Didelotfad09c72016-06-21 12:28:20 -04001873 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001874 return -EOPNOTSUPP;
1875
Vivien Didelotda9c3592016-02-12 12:09:40 -05001876 /* If the requested port doesn't belong to the same bridge as the VLAN
1877 * members, do not support it (yet) and fallback to software VLAN.
1878 */
1879 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1880 vlan->vid_end);
1881 if (err)
1882 return err;
1883
Vivien Didelot76e398a2015-11-01 12:33:55 -05001884 /* We don't need any dynamic resource from the kernel (yet),
1885 * so skip the prepare phase.
1886 */
1887 return 0;
1888}
1889
Vivien Didelotfad09c72016-06-21 12:28:20 -04001890static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
Andrew Lunn158bc062016-04-28 21:24:06 -04001891 u16 vid, bool untagged)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001892{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001893 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001894 int err;
1895
Vivien Didelotfad09c72016-06-21 12:28:20 -04001896 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001897 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001898 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001899
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001900 vlan.data[port] = untagged ?
1901 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1902 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1903
Vivien Didelotfad09c72016-06-21 12:28:20 -04001904 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001905}
1906
Vivien Didelotf81ec902016-05-09 13:22:58 -04001907static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1908 const struct switchdev_obj_port_vlan *vlan,
1909 struct switchdev_trans *trans)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001910{
Vivien Didelot04bed142016-08-31 18:06:13 -04001911 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001912 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1913 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1914 u16 vid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001915
Vivien Didelotfad09c72016-06-21 12:28:20 -04001916 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001917 return;
1918
Vivien Didelotfad09c72016-06-21 12:28:20 -04001919 mutex_lock(&chip->reg_lock);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001920
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001921 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
Vivien Didelotfad09c72016-06-21 12:28:20 -04001922 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
Andrew Lunnc8b09802016-06-04 21:16:57 +02001923 netdev_err(ds->ports[port].netdev,
1924 "failed to add VLAN %d%c\n",
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001925 vid, untagged ? 'u' : 't');
Vivien Didelot76e398a2015-11-01 12:33:55 -05001926
Vivien Didelot77064f32016-11-04 03:23:30 +01001927 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
Andrew Lunnc8b09802016-06-04 21:16:57 +02001928 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001929 vlan->vid_end);
1930
Vivien Didelotfad09c72016-06-21 12:28:20 -04001931 mutex_unlock(&chip->reg_lock);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001932}
1933
Vivien Didelotfad09c72016-06-21 12:28:20 -04001934static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001935 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001936{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001937 struct dsa_switch *ds = chip->ds;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001938 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001939 int i, err;
1940
Vivien Didelotfad09c72016-06-21 12:28:20 -04001941 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001942 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001943 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001944
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001945 /* Tell switchdev if this VLAN is handled in software */
1946 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05001947 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001948
1949 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1950
1951 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04001952 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001953 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot3d131f02015-11-03 10:52:52 -05001954 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001955 continue;
1956
1957 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04001958 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001959 break;
1960 }
1961 }
1962
Vivien Didelotfad09c72016-06-21 12:28:20 -04001963 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001964 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001965 return err;
1966
Vivien Didelotfad09c72016-06-21 12:28:20 -04001967 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001968}
1969
Vivien Didelotf81ec902016-05-09 13:22:58 -04001970static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1971 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001972{
Vivien Didelot04bed142016-08-31 18:06:13 -04001973 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001974 u16 pvid, vid;
1975 int err = 0;
1976
Vivien Didelotfad09c72016-06-21 12:28:20 -04001977 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001978 return -EOPNOTSUPP;
1979
Vivien Didelotfad09c72016-06-21 12:28:20 -04001980 mutex_lock(&chip->reg_lock);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001981
Vivien Didelot77064f32016-11-04 03:23:30 +01001982 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001983 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001984 goto unlock;
1985
Vivien Didelot76e398a2015-11-01 12:33:55 -05001986 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001987 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001988 if (err)
1989 goto unlock;
1990
1991 if (vid == pvid) {
Vivien Didelot77064f32016-11-04 03:23:30 +01001992 err = mv88e6xxx_port_set_pvid(chip, port, 0);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001993 if (err)
1994 goto unlock;
1995 }
1996 }
1997
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001998unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001999 mutex_unlock(&chip->reg_lock);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002000
2001 return err;
2002}
2003
Vivien Didelotfad09c72016-06-21 12:28:20 -04002004static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
Vivien Didelotc5723ac2015-08-10 09:09:48 -04002005 const unsigned char *addr)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002006{
Vivien Didelota935c052016-09-29 12:21:53 -04002007 int i, err;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002008
2009 for (i = 0; i < 3; i++) {
Vivien Didelota935c052016-09-29 12:21:53 -04002010 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2011 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2012 if (err)
2013 return err;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002014 }
2015
2016 return 0;
2017}
2018
Vivien Didelotfad09c72016-06-21 12:28:20 -04002019static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04002020 unsigned char *addr)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002021{
Vivien Didelota935c052016-09-29 12:21:53 -04002022 u16 val;
2023 int i, err;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002024
2025 for (i = 0; i < 3; i++) {
Vivien Didelota935c052016-09-29 12:21:53 -04002026 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2027 if (err)
2028 return err;
2029
2030 addr[i * 2] = val >> 8;
2031 addr[i * 2 + 1] = val & 0xff;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002032 }
2033
2034 return 0;
2035}
2036
Vivien Didelotfad09c72016-06-21 12:28:20 -04002037static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
Vivien Didelotfd231c82015-08-10 09:09:50 -04002038 struct mv88e6xxx_atu_entry *entry)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002039{
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002040 int ret;
2041
Vivien Didelotfad09c72016-06-21 12:28:20 -04002042 ret = _mv88e6xxx_atu_wait(chip);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002043 if (ret < 0)
2044 return ret;
2045
Vivien Didelotfad09c72016-06-21 12:28:20 -04002046 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002047 if (ret < 0)
2048 return ret;
2049
Vivien Didelotfad09c72016-06-21 12:28:20 -04002050 ret = _mv88e6xxx_atu_data_write(chip, entry);
Vivien Didelotfd231c82015-08-10 09:09:50 -04002051 if (ret < 0)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002052 return ret;
2053
Vivien Didelotfad09c72016-06-21 12:28:20 -04002054 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
Vivien Didelotfd231c82015-08-10 09:09:50 -04002055}
David S. Millercdf09692015-08-11 12:00:37 -07002056
Vivien Didelot88472932016-09-19 19:56:11 -04002057static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2058 struct mv88e6xxx_atu_entry *entry);
2059
2060static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2061 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2062{
2063 struct mv88e6xxx_atu_entry next;
2064 int err;
2065
Andrew Lunn59527582017-01-04 19:56:24 +01002066 memcpy(next.mac, addr, ETH_ALEN);
2067 eth_addr_dec(next.mac);
Vivien Didelot88472932016-09-19 19:56:11 -04002068
2069 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2070 if (err)
2071 return err;
2072
2073 do {
2074 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2075 if (err)
2076 return err;
2077
2078 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2079 break;
2080
2081 if (ether_addr_equal(next.mac, addr)) {
2082 *entry = next;
2083 return 0;
2084 }
Andrew Lunn59527582017-01-04 19:56:24 +01002085 } while (ether_addr_greater(addr, next.mac));
Vivien Didelot88472932016-09-19 19:56:11 -04002086
2087 memset(entry, 0, sizeof(*entry));
2088 entry->fid = fid;
2089 ether_addr_copy(entry->mac, addr);
2090
2091 return 0;
2092}
2093
Vivien Didelot83dabd12016-08-31 11:50:04 -04002094static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2095 const unsigned char *addr, u16 vid,
2096 u8 state)
Vivien Didelotfd231c82015-08-10 09:09:50 -04002097{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002098 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot88472932016-09-19 19:56:11 -04002099 struct mv88e6xxx_atu_entry entry;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05002100 int err;
Vivien Didelotfd231c82015-08-10 09:09:50 -04002101
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002102 /* Null VLAN ID corresponds to the port private database */
2103 if (vid == 0)
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002104 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002105 else
Vivien Didelotfad09c72016-06-21 12:28:20 -04002106 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05002107 if (err)
2108 return err;
2109
Vivien Didelot88472932016-09-19 19:56:11 -04002110 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2111 if (err)
2112 return err;
2113
2114 /* Purge the ATU entry only if no port is using it anymore */
2115 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2116 entry.portv_trunkid &= ~BIT(port);
2117 if (!entry.portv_trunkid)
2118 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2119 } else {
2120 entry.portv_trunkid |= BIT(port);
2121 entry.state = state;
Vivien Didelotfd231c82015-08-10 09:09:50 -04002122 }
2123
Vivien Didelotfad09c72016-06-21 12:28:20 -04002124 return _mv88e6xxx_atu_load(chip, &entry);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002125}
2126
Vivien Didelotf81ec902016-05-09 13:22:58 -04002127static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2128 const struct switchdev_obj_port_fdb *fdb,
2129 struct switchdev_trans *trans)
Vivien Didelot146a3202015-10-08 11:35:12 -04002130{
2131 /* We don't need any dynamic resource from the kernel (yet),
2132 * so skip the prepare phase.
2133 */
2134 return 0;
2135}
2136
Vivien Didelotf81ec902016-05-09 13:22:58 -04002137static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2138 const struct switchdev_obj_port_fdb *fdb,
2139 struct switchdev_trans *trans)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002140{
Vivien Didelot04bed142016-08-31 18:06:13 -04002141 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot6630e232015-08-06 01:44:07 -04002142
Vivien Didelotfad09c72016-06-21 12:28:20 -04002143 mutex_lock(&chip->reg_lock);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002144 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2145 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2146 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
Vivien Didelotfad09c72016-06-21 12:28:20 -04002147 mutex_unlock(&chip->reg_lock);
David S. Millercdf09692015-08-11 12:00:37 -07002148}
2149
Vivien Didelotf81ec902016-05-09 13:22:58 -04002150static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2151 const struct switchdev_obj_port_fdb *fdb)
David S. Millercdf09692015-08-11 12:00:37 -07002152{
Vivien Didelot04bed142016-08-31 18:06:13 -04002153 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002154 int err;
David S. Millercdf09692015-08-11 12:00:37 -07002155
Vivien Didelotfad09c72016-06-21 12:28:20 -04002156 mutex_lock(&chip->reg_lock);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002157 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2158 GLOBAL_ATU_DATA_STATE_UNUSED);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002159 mutex_unlock(&chip->reg_lock);
David S. Millercdf09692015-08-11 12:00:37 -07002160
Vivien Didelot83dabd12016-08-31 11:50:04 -04002161 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002162}
2163
Vivien Didelotfad09c72016-06-21 12:28:20 -04002164static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
Vivien Didelot1d194042015-08-10 09:09:51 -04002165 struct mv88e6xxx_atu_entry *entry)
David S. Millercdf09692015-08-11 12:00:37 -07002166{
Vivien Didelot1d194042015-08-10 09:09:51 -04002167 struct mv88e6xxx_atu_entry next = { 0 };
Vivien Didelota935c052016-09-29 12:21:53 -04002168 u16 val;
2169 int err;
Vivien Didelot1d194042015-08-10 09:09:51 -04002170
2171 next.fid = fid;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002172
Vivien Didelota935c052016-09-29 12:21:53 -04002173 err = _mv88e6xxx_atu_wait(chip);
2174 if (err)
2175 return err;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002176
Vivien Didelota935c052016-09-29 12:21:53 -04002177 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2178 if (err)
2179 return err;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002180
Vivien Didelota935c052016-09-29 12:21:53 -04002181 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2182 if (err)
2183 return err;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002184
Vivien Didelota935c052016-09-29 12:21:53 -04002185 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2186 if (err)
2187 return err;
Vivien Didelot1d194042015-08-10 09:09:51 -04002188
Vivien Didelota935c052016-09-29 12:21:53 -04002189 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
Vivien Didelot1d194042015-08-10 09:09:51 -04002190 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2191 unsigned int mask, shift;
2192
Vivien Didelota935c052016-09-29 12:21:53 -04002193 if (val & GLOBAL_ATU_DATA_TRUNK) {
Vivien Didelot1d194042015-08-10 09:09:51 -04002194 next.trunk = true;
2195 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2196 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2197 } else {
2198 next.trunk = false;
2199 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2200 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2201 }
2202
Vivien Didelota935c052016-09-29 12:21:53 -04002203 next.portv_trunkid = (val & mask) >> shift;
Vivien Didelot1d194042015-08-10 09:09:51 -04002204 }
2205
2206 *entry = next;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002207 return 0;
2208}
2209
Vivien Didelot83dabd12016-08-31 11:50:04 -04002210static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2211 u16 fid, u16 vid, int port,
2212 struct switchdev_obj *obj,
2213 int (*cb)(struct switchdev_obj *obj))
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002214{
2215 struct mv88e6xxx_atu_entry addr = {
2216 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2217 };
2218 int err;
2219
Vivien Didelotfad09c72016-06-21 12:28:20 -04002220 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002221 if (err)
2222 return err;
2223
2224 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002225 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002226 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002227 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002228
2229 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2230 break;
2231
Vivien Didelot83dabd12016-08-31 11:50:04 -04002232 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2233 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002234
Vivien Didelot83dabd12016-08-31 11:50:04 -04002235 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2236 struct switchdev_obj_port_fdb *fdb;
2237
2238 if (!is_unicast_ether_addr(addr.mac))
2239 continue;
2240
2241 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002242 fdb->vid = vid;
2243 ether_addr_copy(fdb->addr, addr.mac);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002244 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2245 fdb->ndm_state = NUD_NOARP;
2246 else
2247 fdb->ndm_state = NUD_REACHABLE;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04002248 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2249 struct switchdev_obj_port_mdb *mdb;
2250
2251 if (!is_multicast_ether_addr(addr.mac))
2252 continue;
2253
2254 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2255 mdb->vid = vid;
2256 ether_addr_copy(mdb->addr, addr.mac);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002257 } else {
2258 return -EOPNOTSUPP;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002259 }
Vivien Didelot83dabd12016-08-31 11:50:04 -04002260
2261 err = cb(obj);
2262 if (err)
2263 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002264 } while (!is_broadcast_ether_addr(addr.mac));
2265
2266 return err;
2267}
2268
Vivien Didelot83dabd12016-08-31 11:50:04 -04002269static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2270 struct switchdev_obj *obj,
2271 int (*cb)(struct switchdev_obj *obj))
2272{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002273 struct mv88e6xxx_vtu_entry vlan = {
Vivien Didelot83dabd12016-08-31 11:50:04 -04002274 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2275 };
2276 u16 fid;
2277 int err;
2278
2279 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002280 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002281 if (err)
2282 return err;
2283
2284 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2285 if (err)
2286 return err;
2287
2288 /* Dump VLANs' Filtering Information Databases */
2289 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2290 if (err)
2291 return err;
2292
2293 do {
2294 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2295 if (err)
2296 return err;
2297
2298 if (!vlan.valid)
2299 break;
2300
2301 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2302 obj, cb);
2303 if (err)
2304 return err;
2305 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2306
2307 return err;
2308}
2309
Vivien Didelotf81ec902016-05-09 13:22:58 -04002310static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2311 struct switchdev_obj_port_fdb *fdb,
2312 int (*cb)(struct switchdev_obj *obj))
Vivien Didelotf33475b2015-10-22 09:34:41 -04002313{
Vivien Didelot04bed142016-08-31 18:06:13 -04002314 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002315 int err;
2316
Vivien Didelotfad09c72016-06-21 12:28:20 -04002317 mutex_lock(&chip->reg_lock);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002318 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002319 mutex_unlock(&chip->reg_lock);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002320
2321 return err;
2322}
2323
Vivien Didelotf81ec902016-05-09 13:22:58 -04002324static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vivien Didelotfae8a252017-01-27 15:29:42 -05002325 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002326{
Vivien Didelot04bed142016-08-31 18:06:13 -04002327 struct mv88e6xxx_chip *chip = ds->priv;
Colin Ian King1d9619d2016-04-25 23:11:22 +01002328 int i, err = 0;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002329
Vivien Didelotfad09c72016-06-21 12:28:20 -04002330 mutex_lock(&chip->reg_lock);
Vivien Didelot466dfa02016-02-26 13:16:05 -05002331
Vivien Didelotfae8a252017-01-27 15:29:42 -05002332 /* Remap each port's VLANTable */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002333 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotfae8a252017-01-27 15:29:42 -05002334 if (ds->ports[i].bridge_dev == br) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002335 err = _mv88e6xxx_port_based_vlan_map(chip, i);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002336 if (err)
2337 break;
2338 }
2339 }
2340
Vivien Didelotfad09c72016-06-21 12:28:20 -04002341 mutex_unlock(&chip->reg_lock);
Vivien Didelota6692752016-02-12 12:09:39 -05002342
Vivien Didelot466dfa02016-02-26 13:16:05 -05002343 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002344}
2345
Vivien Didelotf123f2f2017-01-27 15:29:41 -05002346static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2347 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002348{
Vivien Didelot04bed142016-08-31 18:06:13 -04002349 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot16bfa702016-03-13 16:21:33 -04002350 int i;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002351
Vivien Didelotfad09c72016-06-21 12:28:20 -04002352 mutex_lock(&chip->reg_lock);
Vivien Didelot466dfa02016-02-26 13:16:05 -05002353
Vivien Didelotfae8a252017-01-27 15:29:42 -05002354 /* Remap each port's VLANTable */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002355 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
Vivien Didelotfae8a252017-01-27 15:29:42 -05002356 if (i == port || ds->ports[i].bridge_dev == br)
Vivien Didelotfad09c72016-06-21 12:28:20 -04002357 if (_mv88e6xxx_port_based_vlan_map(chip, i))
Andrew Lunnc8b09802016-06-04 21:16:57 +02002358 netdev_warn(ds->ports[i].netdev,
2359 "failed to remap\n");
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002360
Vivien Didelotfad09c72016-06-21 12:28:20 -04002361 mutex_unlock(&chip->reg_lock);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05002362}
2363
Vivien Didelot17e708b2016-12-05 17:30:27 -05002364static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2365{
2366 if (chip->info->ops->reset)
2367 return chip->info->ops->reset(chip);
2368
2369 return 0;
2370}
2371
Vivien Didelot309eca62016-12-05 17:30:26 -05002372static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2373{
2374 struct gpio_desc *gpiod = chip->reset;
2375
2376 /* If there is a GPIO connected to the reset pin, toggle it */
2377 if (gpiod) {
2378 gpiod_set_value_cansleep(gpiod, 1);
2379 usleep_range(10000, 20000);
2380 gpiod_set_value_cansleep(gpiod, 0);
2381 usleep_range(10000, 20000);
2382 }
2383}
2384
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002385static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2386{
2387 int i, err;
2388
2389 /* Set all ports to the Disabled state */
2390 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2391 err = mv88e6xxx_port_set_state(chip, i,
2392 PORT_CONTROL_STATE_DISABLED);
2393 if (err)
2394 return err;
2395 }
2396
2397 /* Wait for transmit queues to drain,
2398 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2399 */
2400 usleep_range(2000, 4000);
2401
2402 return 0;
2403}
2404
Vivien Didelotfad09c72016-06-21 12:28:20 -04002405static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002406{
Vivien Didelota935c052016-09-29 12:21:53 -04002407 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002408
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002409 err = mv88e6xxx_disable_ports(chip);
2410 if (err)
2411 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002412
Vivien Didelot309eca62016-12-05 17:30:26 -05002413 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002414
Vivien Didelot17e708b2016-12-05 17:30:27 -05002415 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002416}
2417
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002418static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002419{
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002420 u16 val;
2421 int err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002422
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002423 /* Clear Power Down bit */
2424 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2425 if (err)
2426 return err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002427
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002428 if (val & BMCR_PDOWN) {
2429 val &= ~BMCR_PDOWN;
2430 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002431 }
2432
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002433 return err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002434}
2435
Andrew Lunn56995cb2016-12-03 04:35:19 +01002436static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2437 int upstream_port)
2438{
2439 int err;
2440
2441 err = chip->info->ops->port_set_frame_mode(
2442 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2443 if (err)
2444 return err;
2445
2446 return chip->info->ops->port_set_egress_unknowns(
2447 chip, port, port == upstream_port);
2448}
2449
2450static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2451{
2452 int err;
2453
2454 switch (chip->info->tag_protocol) {
2455 case DSA_TAG_PROTO_EDSA:
2456 err = chip->info->ops->port_set_frame_mode(
2457 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2458 if (err)
2459 return err;
2460
2461 err = mv88e6xxx_port_set_egress_mode(
2462 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2463 if (err)
2464 return err;
2465
2466 if (chip->info->ops->port_set_ether_type)
2467 err = chip->info->ops->port_set_ether_type(
2468 chip, port, ETH_P_EDSA);
2469 break;
2470
2471 case DSA_TAG_PROTO_DSA:
2472 err = chip->info->ops->port_set_frame_mode(
2473 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2474 if (err)
2475 return err;
2476
2477 err = mv88e6xxx_port_set_egress_mode(
2478 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2479 break;
2480 default:
2481 err = -EINVAL;
2482 }
2483
2484 if (err)
2485 return err;
2486
2487 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2488}
2489
2490static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2491{
2492 int err;
2493
2494 err = chip->info->ops->port_set_frame_mode(
2495 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2496 if (err)
2497 return err;
2498
2499 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2500}
2501
Vivien Didelotfad09c72016-06-21 12:28:20 -04002502static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002503{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002504 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002505 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002506 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002507
Vivien Didelotd78343d2016-11-04 03:23:36 +01002508 /* MAC Forcing register: don't force link, speed, duplex or flow control
2509 * state to any particular values on physical ports, but force the CPU
2510 * port and all DSA ports to their maximum bandwidth and full duplex.
2511 */
2512 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2513 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2514 SPEED_MAX, DUPLEX_FULL,
2515 PHY_INTERFACE_MODE_NA);
2516 else
2517 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2518 SPEED_UNFORCED, DUPLEX_UNFORCED,
2519 PHY_INTERFACE_MODE_NA);
2520 if (err)
2521 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002522
2523 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2524 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2525 * tunneling, determine priority by looking at 802.1p and IP
2526 * priority fields (IP prio has precedence), and set STP state
2527 * to Forwarding.
2528 *
2529 * If this is the CPU link, use DSA or EDSA tagging depending
2530 * on which tagging mode was configured.
2531 *
2532 * If this is a link to another switch, use DSA tagging mode.
2533 *
2534 * If this is the upstream port for this switch, enable
2535 * forwarding of unknown unicasts and multicasts.
2536 */
Andrew Lunn56995cb2016-12-03 04:35:19 +01002537 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
Andrew Lunn54d792f2015-05-06 01:09:47 +02002538 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2539 PORT_CONTROL_STATE_FORWARDING;
Andrew Lunn56995cb2016-12-03 04:35:19 +01002540 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2541 if (err)
2542 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002543
Andrew Lunn56995cb2016-12-03 04:35:19 +01002544 if (dsa_is_cpu_port(ds, port)) {
2545 err = mv88e6xxx_setup_port_cpu(chip, port);
2546 } else if (dsa_is_dsa_port(ds, port)) {
2547 err = mv88e6xxx_setup_port_dsa(chip, port,
2548 dsa_upstream_port(ds));
2549 } else {
2550 err = mv88e6xxx_setup_port_normal(chip, port);
Andrew Lunn54d792f2015-05-06 01:09:47 +02002551 }
Andrew Lunn56995cb2016-12-03 04:35:19 +01002552 if (err)
2553 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002554
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002555 /* If this port is connected to a SerDes, make sure the SerDes is not
2556 * powered down.
2557 */
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002558 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002559 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2560 if (err)
2561 return err;
2562 reg &= PORT_STATUS_CMODE_MASK;
2563 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2564 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2565 (reg == PORT_STATUS_CMODE_SGMII)) {
2566 err = mv88e6xxx_serdes_power_on(chip);
2567 if (err < 0)
2568 return err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002569 }
2570 }
2571
Vivien Didelot8efdda42015-08-13 12:52:23 -04002572 /* Port Control 2: don't force a good FCS, set the maximum frame size to
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002573 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002574 * untagged frames on this port, do a destination address lookup on all
2575 * received packets as usual, disable ARP mirroring and don't send a
2576 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002577 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002578 err = mv88e6xxx_port_set_map_da(chip, port);
2579 if (err)
2580 return err;
2581
Andrew Lunn54d792f2015-05-06 01:09:47 +02002582 reg = 0;
Andrew Lunna23b2962017-02-04 20:15:28 +01002583 if (chip->info->ops->port_set_upstream_port) {
2584 err = chip->info->ops->port_set_upstream_port(
2585 chip, port, dsa_upstream_port(ds));
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002586 if (err)
2587 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002588 }
2589
Andrew Lunna23b2962017-02-04 20:15:28 +01002590 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2591 PORT_CONTROL_2_8021Q_DISABLED);
2592 if (err)
2593 return err;
2594
Andrew Lunn5f436662016-12-03 04:45:17 +01002595 if (chip->info->ops->port_jumbo_config) {
2596 err = chip->info->ops->port_jumbo_config(chip, port);
2597 if (err)
2598 return err;
2599 }
2600
Andrew Lunn54d792f2015-05-06 01:09:47 +02002601 /* Port Association Vector: when learning source addresses
2602 * of packets, add the address to the address database using
2603 * a port bitmap that has only the bit for this port set and
2604 * the other bits clear.
2605 */
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002606 reg = 1 << port;
Vivien Didelot996ecb82016-04-14 14:42:08 -04002607 /* Disable learning for CPU port */
2608 if (dsa_is_cpu_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002609 reg = 0;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002610
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002611 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2612 if (err)
2613 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002614
2615 /* Egress rate control 2: disable egress rate control. */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002616 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2617 if (err)
2618 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002619
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002620 if (chip->info->ops->port_pause_config) {
2621 err = chip->info->ops->port_pause_config(chip, port);
2622 if (err)
2623 return err;
2624 }
2625
Vivien Didelotfad09c72016-06-21 12:28:20 -04002626 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2627 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01002628 mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
Andrew Lunn54d792f2015-05-06 01:09:47 +02002629 /* Port ATU control: disable limiting the number of
2630 * address database entries that this port is allowed
2631 * to use.
2632 */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002633 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2634 0x0000);
Andrew Lunn54d792f2015-05-06 01:09:47 +02002635 /* Priority Override: disable DA, SA and VTU priority
2636 * override.
2637 */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002638 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2639 0x0000);
2640 if (err)
2641 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002642 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002643
Andrew Lunnef0a7312016-12-03 04:35:16 +01002644 if (chip->info->ops->port_tag_remap) {
2645 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002646 if (err)
2647 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002648 }
2649
Andrew Lunnef70b112016-12-03 04:45:18 +01002650 if (chip->info->ops->port_egress_rate_limiting) {
2651 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002652 if (err)
2653 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002654 }
2655
Guenter Roeck366f0a02015-03-26 18:36:30 -07002656 /* Port Control 1: disable trunking, disable sending
2657 * learning messages to this port.
Guenter Roeckd827e882015-03-26 18:36:29 -07002658 */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002659 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2660 if (err)
2661 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002662
Vivien Didelot207afda2016-04-14 14:42:09 -04002663 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002664 * database, and allow bidirectional communication between the
2665 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07002666 */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002667 err = mv88e6xxx_port_set_fid(chip, port, 0);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002668 if (err)
2669 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002670
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002671 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2672 if (err)
2673 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002674
2675 /* Default VLAN ID and priority: don't set a default VLAN
2676 * ID, and set the default packet priority to zero.
2677 */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002678 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
Andrew Lunndbde9e62015-05-06 01:09:48 +02002679}
2680
Wei Yongjunaa0938c2016-10-18 15:53:37 +00002681static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002682{
2683 int err;
2684
Vivien Didelota935c052016-09-29 12:21:53 -04002685 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002686 if (err)
2687 return err;
2688
Vivien Didelota935c052016-09-29 12:21:53 -04002689 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002690 if (err)
2691 return err;
2692
Vivien Didelota935c052016-09-29 12:21:53 -04002693 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2694 if (err)
2695 return err;
2696
2697 return 0;
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002698}
2699
Vivien Didelotacddbd22016-07-18 20:45:39 -04002700static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2701 unsigned int msecs)
2702{
2703 const unsigned int coeff = chip->info->age_time_coeff;
2704 const unsigned int min = 0x01 * coeff;
2705 const unsigned int max = 0xff * coeff;
2706 u8 age_time;
2707 u16 val;
2708 int err;
2709
2710 if (msecs < min || msecs > max)
2711 return -ERANGE;
2712
2713 /* Round to nearest multiple of coeff */
2714 age_time = (msecs + coeff / 2) / coeff;
2715
Vivien Didelota935c052016-09-29 12:21:53 -04002716 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
Vivien Didelotacddbd22016-07-18 20:45:39 -04002717 if (err)
2718 return err;
2719
2720 /* AgeTime is 11:4 bits */
2721 val &= ~0xff0;
2722 val |= age_time << 4;
2723
Vivien Didelota935c052016-09-29 12:21:53 -04002724 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
Vivien Didelotacddbd22016-07-18 20:45:39 -04002725}
2726
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002727static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2728 unsigned int ageing_time)
2729{
Vivien Didelot04bed142016-08-31 18:06:13 -04002730 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002731 int err;
2732
2733 mutex_lock(&chip->reg_lock);
2734 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2735 mutex_unlock(&chip->reg_lock);
2736
2737 return err;
2738}
2739
Vivien Didelot97299342016-07-18 20:45:30 -04002740static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04002741{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002742 struct dsa_switch *ds = chip->ds;
Vivien Didelotb0745e872016-05-09 13:22:53 -04002743 u32 upstream_port = dsa_upstream_port(ds);
Vivien Didelot08a01262016-05-09 13:22:50 -04002744 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04002745
Vivien Didelot119477b2016-05-09 13:22:51 -04002746 /* Enable the PHY Polling Unit if present, don't discard any packets,
2747 * and mask all interrupt sources.
2748 */
Vivien Didelota199d8b2016-12-05 17:30:28 -05002749 err = mv88e6xxx_ppu_enable(chip);
Vivien Didelot119477b2016-05-09 13:22:51 -04002750 if (err)
2751 return err;
2752
Andrew Lunn33641992016-12-03 04:35:17 +01002753 if (chip->info->ops->g1_set_cpu_port) {
2754 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2755 if (err)
2756 return err;
2757 }
2758
2759 if (chip->info->ops->g1_set_egress_port) {
2760 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2761 if (err)
2762 return err;
2763 }
Vivien Didelotb0745e872016-05-09 13:22:53 -04002764
Vivien Didelot50484ff2016-05-09 13:22:54 -04002765 /* Disable remote management, and set the switch's DSA device number. */
Vivien Didelota935c052016-09-29 12:21:53 -04002766 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2767 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2768 (ds->index & 0x1f));
Vivien Didelot50484ff2016-05-09 13:22:54 -04002769 if (err)
2770 return err;
2771
Vivien Didelotacddbd22016-07-18 20:45:39 -04002772 /* Clear all the VTU and STU entries */
2773 err = _mv88e6xxx_vtu_stu_flush(chip);
2774 if (err < 0)
2775 return err;
2776
Vivien Didelot08a01262016-05-09 13:22:50 -04002777 /* Set the default address aging time to 5 minutes, and
2778 * enable address learn messages to be sent to all message
2779 * ports.
2780 */
Vivien Didelota935c052016-09-29 12:21:53 -04002781 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2782 GLOBAL_ATU_CONTROL_LEARN2ALL);
Vivien Didelot08a01262016-05-09 13:22:50 -04002783 if (err)
2784 return err;
2785
Vivien Didelotacddbd22016-07-18 20:45:39 -04002786 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2787 if (err)
Vivien Didelot97299342016-07-18 20:45:30 -04002788 return err;
2789
2790 /* Clear all ATU entries */
2791 err = _mv88e6xxx_atu_flush(chip, 0, true);
2792 if (err)
2793 return err;
2794
Vivien Didelot08a01262016-05-09 13:22:50 -04002795 /* Configure the IP ToS mapping registers. */
Vivien Didelota935c052016-09-29 12:21:53 -04002796 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
Vivien Didelot08a01262016-05-09 13:22:50 -04002797 if (err)
2798 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002799 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
Vivien Didelot08a01262016-05-09 13:22:50 -04002800 if (err)
2801 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002802 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
Vivien Didelot08a01262016-05-09 13:22:50 -04002803 if (err)
2804 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002805 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
Vivien Didelot08a01262016-05-09 13:22:50 -04002806 if (err)
2807 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002808 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
Vivien Didelot08a01262016-05-09 13:22:50 -04002809 if (err)
2810 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002811 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
Vivien Didelot08a01262016-05-09 13:22:50 -04002812 if (err)
2813 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002814 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
Vivien Didelot08a01262016-05-09 13:22:50 -04002815 if (err)
2816 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002817 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
Vivien Didelot08a01262016-05-09 13:22:50 -04002818 if (err)
2819 return err;
2820
2821 /* Configure the IEEE 802.1p priority mapping register. */
Vivien Didelota935c052016-09-29 12:21:53 -04002822 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
Vivien Didelot08a01262016-05-09 13:22:50 -04002823 if (err)
2824 return err;
2825
Andrew Lunnde2273872016-11-21 23:27:01 +01002826 /* Initialize the statistics unit */
2827 err = mv88e6xxx_stats_set_histogram(chip);
2828 if (err)
2829 return err;
2830
Vivien Didelot97299342016-07-18 20:45:30 -04002831 /* Clear the statistics counters for all ports */
Vivien Didelota935c052016-09-29 12:21:53 -04002832 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2833 GLOBAL_STATS_OP_FLUSH_ALL);
Vivien Didelot97299342016-07-18 20:45:30 -04002834 if (err)
2835 return err;
2836
2837 /* Wait for the flush to complete. */
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +01002838 err = mv88e6xxx_g1_stats_wait(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04002839 if (err)
2840 return err;
2841
2842 return 0;
2843}
2844
Vivien Didelotf81ec902016-05-09 13:22:58 -04002845static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07002846{
Vivien Didelot04bed142016-08-31 18:06:13 -04002847 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot552238b2016-05-09 13:22:49 -04002848 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002849 int i;
2850
Vivien Didelotfad09c72016-06-21 12:28:20 -04002851 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002852 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002853
Vivien Didelotfad09c72016-06-21 12:28:20 -04002854 mutex_lock(&chip->reg_lock);
Vivien Didelot552238b2016-05-09 13:22:49 -04002855
Vivien Didelot97299342016-07-18 20:45:30 -04002856 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002857 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelot97299342016-07-18 20:45:30 -04002858 err = mv88e6xxx_setup_port(chip, i);
2859 if (err)
2860 goto unlock;
2861 }
2862
2863 /* Setup Switch Global 1 Registers */
2864 err = mv88e6xxx_g1_setup(chip);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002865 if (err)
2866 goto unlock;
2867
Vivien Didelot97299342016-07-18 20:45:30 -04002868 /* Setup Switch Global 2 Registers */
2869 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2870 err = mv88e6xxx_g2_setup(chip);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002871 if (err)
2872 goto unlock;
2873 }
Andrew Lunn54d792f2015-05-06 01:09:47 +02002874
Andrew Lunn6e55f692016-12-03 04:45:16 +01002875 /* Some generations have the configuration of sending reserved
2876 * management frames to the CPU in global2, others in
2877 * global1. Hence it does not fit the two setup functions
2878 * above.
2879 */
2880 if (chip->info->ops->mgmt_rsvd2cpu) {
2881 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2882 if (err)
2883 goto unlock;
2884 }
2885
Vivien Didelot6b17e862015-08-13 12:52:18 -04002886unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002887 mutex_unlock(&chip->reg_lock);
Andrew Lunndb687a52015-06-20 21:31:29 +02002888
Andrew Lunn48ace4e2016-04-14 23:47:12 +02002889 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002890}
2891
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002892static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2893{
Vivien Didelot04bed142016-08-31 18:06:13 -04002894 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002895 int err;
2896
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002897 if (!chip->info->ops->set_switch_mac)
2898 return -EOPNOTSUPP;
2899
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002900 mutex_lock(&chip->reg_lock);
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002901 err = chip->info->ops->set_switch_mac(chip, addr);
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002902 mutex_unlock(&chip->reg_lock);
2903
2904 return err;
2905}
2906
Vivien Didelote57e5e72016-08-15 17:19:00 -04002907static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002908{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002909 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2910 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002911 u16 val;
2912 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002913
Andrew Lunnee26a222017-01-24 14:53:48 +01002914 if (!chip->info->ops->phy_read)
2915 return -EOPNOTSUPP;
2916
Vivien Didelotfad09c72016-06-21 12:28:20 -04002917 mutex_lock(&chip->reg_lock);
Andrew Lunnee26a222017-01-24 14:53:48 +01002918 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002919 mutex_unlock(&chip->reg_lock);
Vivien Didelote57e5e72016-08-15 17:19:00 -04002920
Andrew Lunnda9f3302017-02-01 03:40:05 +01002921 if (reg == MII_PHYSID2) {
2922 /* Some internal PHYS don't have a model number. Use
2923 * the mv88e6390 family model number instead.
2924 */
2925 if (!(val & 0x3f0))
2926 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2927 }
2928
Vivien Didelote57e5e72016-08-15 17:19:00 -04002929 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002930}
2931
Vivien Didelote57e5e72016-08-15 17:19:00 -04002932static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002933{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002934 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2935 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002936 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002937
Andrew Lunnee26a222017-01-24 14:53:48 +01002938 if (!chip->info->ops->phy_write)
2939 return -EOPNOTSUPP;
2940
Vivien Didelotfad09c72016-06-21 12:28:20 -04002941 mutex_lock(&chip->reg_lock);
Andrew Lunnee26a222017-01-24 14:53:48 +01002942 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002943 mutex_unlock(&chip->reg_lock);
Vivien Didelote57e5e72016-08-15 17:19:00 -04002944
2945 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002946}
2947
Vivien Didelotfad09c72016-06-21 12:28:20 -04002948static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01002949 struct device_node *np,
2950 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02002951{
2952 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002953 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02002954 struct mii_bus *bus;
2955 int err;
2956
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002957 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02002958 if (!bus)
2959 return -ENOMEM;
2960
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002961 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002962 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002963 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002964 INIT_LIST_HEAD(&mdio_bus->list);
2965 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002966
Andrew Lunnb516d452016-06-04 21:17:06 +02002967 if (np) {
2968 bus->name = np->full_name;
2969 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2970 } else {
2971 bus->name = "mv88e6xxx SMI";
2972 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2973 }
2974
2975 bus->read = mv88e6xxx_mdio_read;
2976 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002977 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02002978
Andrew Lunna3c53be52017-01-24 14:53:50 +01002979 if (np)
2980 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02002981 else
2982 err = mdiobus_register(bus);
2983 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002984 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunna3c53be52017-01-24 14:53:50 +01002985 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02002986 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01002987
2988 if (external)
2989 list_add_tail(&mdio_bus->list, &chip->mdios);
2990 else
2991 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02002992
2993 return 0;
Andrew Lunnb516d452016-06-04 21:17:06 +02002994}
2995
Andrew Lunna3c53be52017-01-24 14:53:50 +01002996static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2997 { .compatible = "marvell,mv88e6xxx-mdio-external",
2998 .data = (void *)true },
2999 { },
3000};
3001
3002static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3003 struct device_node *np)
3004{
3005 const struct of_device_id *match;
3006 struct device_node *child;
3007 int err;
3008
3009 /* Always register one mdio bus for the internal/default mdio
3010 * bus. This maybe represented in the device tree, but is
3011 * optional.
3012 */
3013 child = of_get_child_by_name(np, "mdio");
3014 err = mv88e6xxx_mdio_register(chip, child, false);
3015 if (err)
3016 return err;
3017
3018 /* Walk the device tree, and see if there are any other nodes
3019 * which say they are compatible with the external mdio
3020 * bus.
3021 */
3022 for_each_available_child_of_node(np, child) {
3023 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3024 if (match) {
3025 err = mv88e6xxx_mdio_register(chip, child, true);
3026 if (err)
3027 return err;
3028 }
3029 }
3030
3031 return 0;
3032}
3033
3034static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
Andrew Lunnb516d452016-06-04 21:17:06 +02003035
3036{
Andrew Lunna3c53be52017-01-24 14:53:50 +01003037 struct mv88e6xxx_mdio_bus *mdio_bus;
3038 struct mii_bus *bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003039
Andrew Lunna3c53be52017-01-24 14:53:50 +01003040 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3041 bus = mdio_bus->bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003042
Andrew Lunna3c53be52017-01-24 14:53:50 +01003043 mdiobus_unregister(bus);
3044 }
Andrew Lunnb516d452016-06-04 21:17:06 +02003045}
3046
Vivien Didelot855b1932016-07-20 18:18:35 -04003047static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3048{
Vivien Didelot04bed142016-08-31 18:06:13 -04003049 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003050
3051 return chip->eeprom_len;
3052}
3053
Vivien Didelot855b1932016-07-20 18:18:35 -04003054static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3055 struct ethtool_eeprom *eeprom, u8 *data)
3056{
Vivien Didelot04bed142016-08-31 18:06:13 -04003057 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003058 int err;
3059
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003060 if (!chip->info->ops->get_eeprom)
3061 return -EOPNOTSUPP;
3062
Vivien Didelot855b1932016-07-20 18:18:35 -04003063 mutex_lock(&chip->reg_lock);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003064 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Vivien Didelot855b1932016-07-20 18:18:35 -04003065 mutex_unlock(&chip->reg_lock);
3066
3067 if (err)
3068 return err;
3069
3070 eeprom->magic = 0xc3ec4951;
3071
3072 return 0;
3073}
3074
Vivien Didelot855b1932016-07-20 18:18:35 -04003075static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3076 struct ethtool_eeprom *eeprom, u8 *data)
3077{
Vivien Didelot04bed142016-08-31 18:06:13 -04003078 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003079 int err;
3080
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003081 if (!chip->info->ops->set_eeprom)
3082 return -EOPNOTSUPP;
3083
Vivien Didelot855b1932016-07-20 18:18:35 -04003084 if (eeprom->magic != 0xc3ec4951)
3085 return -EINVAL;
3086
3087 mutex_lock(&chip->reg_lock);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003088 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Vivien Didelot855b1932016-07-20 18:18:35 -04003089 mutex_unlock(&chip->reg_lock);
3090
3091 return err;
3092}
3093
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003094static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003095 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003096 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003097 .phy_read = mv88e6xxx_phy_ppu_read,
3098 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003099 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003100 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003101 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003102 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003103 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3104 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3105 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003106 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003107 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003108 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003109 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3110 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003111 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003112 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3113 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003114 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003115 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003116 .ppu_enable = mv88e6185_g1_ppu_enable,
3117 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003118 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003119};
3120
3121static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003122 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003123 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003124 .phy_read = mv88e6xxx_phy_ppu_read,
3125 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003126 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003127 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003128 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003129 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Andrew Lunna23b2962017-02-04 20:15:28 +01003130 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
3131 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003132 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003133 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3134 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003135 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003136 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003137 .ppu_enable = mv88e6185_g1_ppu_enable,
3138 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003139 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003140};
3141
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003142static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01003143 /* MV88E6XXX_FAMILY_6097 */
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3145 .phy_read = mv88e6xxx_g2_smi_phy_read,
3146 .phy_write = mv88e6xxx_g2_smi_phy_write,
3147 .port_set_link = mv88e6xxx_port_set_link,
3148 .port_set_duplex = mv88e6xxx_port_set_duplex,
3149 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003150 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003151 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3152 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3153 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003154 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003155 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003156 .port_pause_config = mv88e6097_port_pause_config,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003157 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3158 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3159 .stats_get_strings = mv88e6095_stats_get_strings,
3160 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003161 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3162 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01003163 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003164 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003165 .reset = mv88e6352_g1_reset,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003166};
3167
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003168static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003169 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003170 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003171 .phy_read = mv88e6165_phy_read,
3172 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003173 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003174 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003175 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003176 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3177 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003178 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003179 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3180 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003181 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003182 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3183 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003184 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003185 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003186 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003187};
3188
3189static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003190 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003191 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003192 .phy_read = mv88e6xxx_phy_ppu_read,
3193 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003194 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003195 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003196 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003197 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003198 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Andrew Lunna23b2962017-02-04 20:15:28 +01003199 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003200 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01003201 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn5f436662016-12-03 04:45:17 +01003202 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003203 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003204 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003205 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003206 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3207 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003208 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003209 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3210 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003211 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003212 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003213 .ppu_enable = mv88e6185_g1_ppu_enable,
3214 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003215 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003216};
3217
3218static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003219 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003221 .phy_read = mv88e6165_phy_read,
3222 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003223 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003224 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003225 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003226 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003227 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3228 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3229 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003230 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003231 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003232 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003234 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3235 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003236 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003237 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3238 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003239 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003240 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003241 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003242};
3243
3244static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003245 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003247 .phy_read = mv88e6165_phy_read,
3248 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003249 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003250 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003251 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003252 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003253 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3254 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003255 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003256 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3257 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003258 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003259 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003260 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003261};
3262
3263static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003264 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003266 .phy_read = mv88e6xxx_g2_smi_phy_read,
3267 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003268 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003269 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003270 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003271 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003272 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003273 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3274 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3275 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003276 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003277 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003278 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003279 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003280 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3281 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003282 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003283 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3284 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003285 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003286 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003287 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003288};
3289
3290static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003291 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003292 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3293 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003295 .phy_read = mv88e6xxx_g2_smi_phy_read,
3296 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003297 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003298 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003299 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003300 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003301 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003302 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3303 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3304 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003305 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003306 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003307 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003308 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003309 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3310 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003311 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003312 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3313 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003314 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003315 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003316 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003317};
3318
3319static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003320 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003322 .phy_read = mv88e6xxx_g2_smi_phy_read,
3323 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003324 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003325 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003326 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003327 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003328 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003329 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3330 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3331 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003332 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003333 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003334 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003335 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003336 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3337 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003338 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003339 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3340 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003341 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003342 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003343 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003344};
3345
3346static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003347 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003348 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3349 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003350 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003351 .phy_read = mv88e6xxx_g2_smi_phy_read,
3352 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003353 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003354 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003355 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003356 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003357 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003358 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3359 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3360 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003361 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003362 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003363 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003364 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003365 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3366 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003367 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003368 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3369 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003370 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003371 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003372 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003373};
3374
3375static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003376 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003377 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003378 .phy_read = mv88e6xxx_phy_ppu_read,
3379 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003380 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003381 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003382 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003383 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Andrew Lunna23b2962017-02-04 20:15:28 +01003384 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
Andrew Lunnef70b112016-12-03 04:45:18 +01003385 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01003386 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003387 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003388 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3389 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003390 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003391 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3392 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003393 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003394 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003395 .ppu_enable = mv88e6185_g1_ppu_enable,
3396 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003397 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003398};
3399
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003400static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003401 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003402 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3403 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3405 .phy_read = mv88e6xxx_g2_smi_phy_read,
3406 .phy_write = mv88e6xxx_g2_smi_phy_write,
3407 .port_set_link = mv88e6xxx_port_set_link,
3408 .port_set_duplex = mv88e6xxx_port_set_duplex,
3409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3410 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003411 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003412 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3413 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3414 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003415 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunn79523472016-11-21 23:27:00 +01003416 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003417 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003418 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3419 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003420 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003421 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3422 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003423 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003424 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003425 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003426};
3427
3428static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003429 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003430 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3431 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003432 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3433 .phy_read = mv88e6xxx_g2_smi_phy_read,
3434 .phy_write = mv88e6xxx_g2_smi_phy_write,
3435 .port_set_link = mv88e6xxx_port_set_link,
3436 .port_set_duplex = mv88e6xxx_port_set_duplex,
3437 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3438 .port_set_speed = mv88e6390x_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003439 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003440 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3441 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3442 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003443 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunn79523472016-11-21 23:27:00 +01003444 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003445 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003446 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3447 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003448 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003449 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3450 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003451 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003452 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003453 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003454};
3455
3456static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003457 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003458 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3459 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003460 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3461 .phy_read = mv88e6xxx_g2_smi_phy_read,
3462 .phy_write = mv88e6xxx_g2_smi_phy_write,
3463 .port_set_link = mv88e6xxx_port_set_link,
3464 .port_set_duplex = mv88e6xxx_port_set_duplex,
3465 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3466 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003467 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003468 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3469 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3470 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003471 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunn79523472016-11-21 23:27:00 +01003472 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003473 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003474 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3475 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003476 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003477 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3478 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003479 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003480 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003481 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003482};
3483
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003484static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003485 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003486 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3487 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003489 .phy_read = mv88e6xxx_g2_smi_phy_read,
3490 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003491 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003492 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003493 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003494 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003495 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003496 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3497 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3498 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003499 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003500 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003501 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003502 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003503 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3504 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003505 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003506 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3507 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003508 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003509 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003510 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003511};
3512
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003513static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003514 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003515 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3516 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003517 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3518 .phy_read = mv88e6xxx_g2_smi_phy_read,
3519 .phy_write = mv88e6xxx_g2_smi_phy_write,
3520 .port_set_link = mv88e6xxx_port_set_link,
3521 .port_set_duplex = mv88e6xxx_port_set_duplex,
3522 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3523 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003524 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003525 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3526 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3527 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003528 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunnf39908d2017-02-04 20:02:50 +01003529 .port_set_cmode = mv88e6390x_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003530 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003531 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003532 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3533 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003534 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003535 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3536 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003537 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003538 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003539 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003540};
3541
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003542static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003543 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003544 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3545 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003546 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003547 .phy_read = mv88e6xxx_g2_smi_phy_read,
3548 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003549 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003550 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003551 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003552 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003553 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3554 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3555 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003556 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003557 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003558 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003559 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003560 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3561 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003562 .stats_get_stats = mv88e6320_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003563 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3564 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003565 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003566 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003567};
3568
3569static const struct mv88e6xxx_ops mv88e6321_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003570 /* MV88E6XXX_FAMILY_6321 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003571 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3572 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003573 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003574 .phy_read = mv88e6xxx_g2_smi_phy_read,
3575 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003576 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003577 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003578 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003579 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003580 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3581 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3582 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003583 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003584 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003585 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003586 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003587 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3588 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003589 .stats_get_stats = mv88e6320_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003590 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3591 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003592 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003593};
3594
3595static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003596 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003597 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003598 .phy_read = mv88e6xxx_g2_smi_phy_read,
3599 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003600 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003601 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003602 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003603 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003604 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003605 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3606 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3607 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003608 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003609 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003610 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003611 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003612 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3613 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003614 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003615 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3616 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003617 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003618 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003619 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003620};
3621
3622static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003623 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003624 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003625 .phy_read = mv88e6xxx_g2_smi_phy_read,
3626 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003627 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003628 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003629 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003630 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003631 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003632 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3633 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3634 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003635 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003636 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003637 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003638 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003639 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3640 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003641 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003642 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3643 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003644 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003645 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003646 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003647};
3648
3649static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003650 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003651 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3652 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003653 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003654 .phy_read = mv88e6xxx_g2_smi_phy_read,
3655 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003656 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003657 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003658 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003659 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003660 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003661 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3662 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3663 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003664 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003665 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003666 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003667 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003668 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3669 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003670 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003671 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3672 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003673 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003674 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003675 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003676};
3677
Gregory CLEMENT15587272017-01-30 20:29:35 +01003678static const struct mv88e6xxx_ops mv88e6141_ops = {
3679 /* MV88E6XXX_FAMILY_6341 */
3680 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3681 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3682 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3683 .phy_read = mv88e6xxx_g2_smi_phy_read,
3684 .phy_write = mv88e6xxx_g2_smi_phy_write,
3685 .port_set_link = mv88e6xxx_port_set_link,
3686 .port_set_duplex = mv88e6xxx_port_set_duplex,
3687 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3688 .port_set_speed = mv88e6390_port_set_speed,
3689 .port_tag_remap = mv88e6095_port_tag_remap,
3690 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3691 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3692 .port_set_ether_type = mv88e6351_port_set_ether_type,
3693 .port_jumbo_config = mv88e6165_port_jumbo_config,
3694 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3695 .port_pause_config = mv88e6097_port_pause_config,
3696 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3697 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3698 .stats_get_strings = mv88e6320_stats_get_strings,
3699 .stats_get_stats = mv88e6390_stats_get_stats,
3700 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3701 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003702 .watchdog_ops = &mv88e6390_watchdog_ops,
Gregory CLEMENT15587272017-01-30 20:29:35 +01003703 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3704 .reset = mv88e6352_g1_reset,
3705};
3706
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01003707static const struct mv88e6xxx_ops mv88e6341_ops = {
3708 /* MV88E6XXX_FAMILY_6341 */
3709 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3710 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3712 .phy_read = mv88e6xxx_g2_smi_phy_read,
3713 .phy_write = mv88e6xxx_g2_smi_phy_write,
3714 .port_set_link = mv88e6xxx_port_set_link,
3715 .port_set_duplex = mv88e6xxx_port_set_duplex,
3716 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3717 .port_set_speed = mv88e6390_port_set_speed,
3718 .port_tag_remap = mv88e6095_port_tag_remap,
3719 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3720 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3721 .port_set_ether_type = mv88e6351_port_set_ether_type,
3722 .port_jumbo_config = mv88e6165_port_jumbo_config,
3723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3724 .port_pause_config = mv88e6097_port_pause_config,
3725 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3726 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3727 .stats_get_strings = mv88e6320_stats_get_strings,
3728 .stats_get_stats = mv88e6390_stats_get_stats,
3729 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3730 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003731 .watchdog_ops = &mv88e6390_watchdog_ops,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01003732 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3733 .reset = mv88e6352_g1_reset,
3734};
3735
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003736static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003737 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003738 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3739 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003740 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3741 .phy_read = mv88e6xxx_g2_smi_phy_read,
3742 .phy_write = mv88e6xxx_g2_smi_phy_write,
3743 .port_set_link = mv88e6xxx_port_set_link,
3744 .port_set_duplex = mv88e6xxx_port_set_duplex,
3745 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3746 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003747 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003748 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3749 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3750 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003751 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003752 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003753 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunnf39908d2017-02-04 20:02:50 +01003754 .port_set_cmode = mv88e6390x_port_set_cmode,
Andrew Lunn79523472016-11-21 23:27:00 +01003755 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003756 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003757 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3758 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003759 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003760 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3761 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003762 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003763 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003764 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003765};
3766
3767static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003768 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003769 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3770 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3772 .phy_read = mv88e6xxx_g2_smi_phy_read,
3773 .phy_write = mv88e6xxx_g2_smi_phy_write,
3774 .port_set_link = mv88e6xxx_port_set_link,
3775 .port_set_duplex = mv88e6xxx_port_set_duplex,
3776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3777 .port_set_speed = mv88e6390x_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003778 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003779 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3780 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3781 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003782 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003783 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003784 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunn79523472016-11-21 23:27:00 +01003785 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003786 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003787 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3788 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003789 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003790 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3791 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003792 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003793 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003794 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003795};
3796
3797static const struct mv88e6xxx_ops mv88e6391_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003798 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003799 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3800 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003801 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3802 .phy_read = mv88e6xxx_g2_smi_phy_read,
3803 .phy_write = mv88e6xxx_g2_smi_phy_write,
3804 .port_set_link = mv88e6xxx_port_set_link,
3805 .port_set_duplex = mv88e6xxx_port_set_duplex,
3806 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3807 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003808 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003809 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3810 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3811 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003812 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunn79523472016-11-21 23:27:00 +01003813 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003814 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003815 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3816 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003817 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003818 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3819 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003820 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003821 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003822 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003823};
3824
Andrew Lunn56995cb2016-12-03 04:35:19 +01003825static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3826 const struct mv88e6xxx_ops *ops)
3827{
3828 if (!ops->port_set_frame_mode) {
3829 dev_err(chip->dev, "Missing port_set_frame_mode");
3830 return -EINVAL;
3831 }
3832
3833 if (!ops->port_set_egress_unknowns) {
3834 dev_err(chip->dev, "Missing port_set_egress_mode");
3835 return -EINVAL;
3836 }
3837
3838 return 0;
3839}
3840
Vivien Didelotf81ec902016-05-09 13:22:58 -04003841static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3842 [MV88E6085] = {
3843 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3844 .family = MV88E6XXX_FAMILY_6097,
3845 .name = "Marvell 88E6085",
3846 .num_databases = 4096,
3847 .num_ports = 10,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003848 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003849 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003850 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003851 .g1_irqs = 8,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003852 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003853 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003854 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003855 },
3856
3857 [MV88E6095] = {
3858 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3859 .family = MV88E6XXX_FAMILY_6095,
3860 .name = "Marvell 88E6095/88E6095F",
3861 .num_databases = 256,
3862 .num_ports = 11,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003863 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003864 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003865 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003866 .g1_irqs = 8,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003867 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003868 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003869 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003870 },
3871
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003872 [MV88E6097] = {
3873 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3874 .family = MV88E6XXX_FAMILY_6097,
3875 .name = "Marvell 88E6097/88E6097F",
3876 .num_databases = 4096,
3877 .num_ports = 11,
3878 .port_base_addr = 0x10,
3879 .global1_addr = 0x1b,
3880 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01003881 .g1_irqs = 8,
Stefan Eichenberger2bfcfcd2016-12-05 14:12:42 +01003882 .tag_protocol = DSA_TAG_PROTO_EDSA,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003883 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3884 .ops = &mv88e6097_ops,
3885 },
3886
Vivien Didelotf81ec902016-05-09 13:22:58 -04003887 [MV88E6123] = {
3888 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3889 .family = MV88E6XXX_FAMILY_6165,
3890 .name = "Marvell 88E6123",
3891 .num_databases = 4096,
3892 .num_ports = 3,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003893 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003894 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003895 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003896 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003897 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003898 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003899 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003900 },
3901
3902 [MV88E6131] = {
3903 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3904 .family = MV88E6XXX_FAMILY_6185,
3905 .name = "Marvell 88E6131",
3906 .num_databases = 256,
3907 .num_ports = 8,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003908 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003909 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003910 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003911 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003912 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003913 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003914 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003915 },
3916
3917 [MV88E6161] = {
3918 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3919 .family = MV88E6XXX_FAMILY_6165,
3920 .name = "Marvell 88E6161",
3921 .num_databases = 4096,
3922 .num_ports = 6,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003923 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003924 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003925 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003926 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003927 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003928 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003929 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003930 },
3931
3932 [MV88E6165] = {
3933 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3934 .family = MV88E6XXX_FAMILY_6165,
3935 .name = "Marvell 88E6165",
3936 .num_databases = 4096,
3937 .num_ports = 6,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003938 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003939 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003940 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003941 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003942 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003943 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003944 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003945 },
3946
3947 [MV88E6171] = {
3948 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3949 .family = MV88E6XXX_FAMILY_6351,
3950 .name = "Marvell 88E6171",
3951 .num_databases = 4096,
3952 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003953 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003954 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003955 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003956 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003957 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003958 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003959 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003960 },
3961
3962 [MV88E6172] = {
3963 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3964 .family = MV88E6XXX_FAMILY_6352,
3965 .name = "Marvell 88E6172",
3966 .num_databases = 4096,
3967 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003968 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003969 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003970 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003971 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003972 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003973 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003974 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003975 },
3976
3977 [MV88E6175] = {
3978 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3979 .family = MV88E6XXX_FAMILY_6351,
3980 .name = "Marvell 88E6175",
3981 .num_databases = 4096,
3982 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003983 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003984 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003985 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003986 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003987 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003988 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003989 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003990 },
3991
3992 [MV88E6176] = {
3993 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3994 .family = MV88E6XXX_FAMILY_6352,
3995 .name = "Marvell 88E6176",
3996 .num_databases = 4096,
3997 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003998 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003999 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004000 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004001 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004002 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004003 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004004 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004005 },
4006
4007 [MV88E6185] = {
4008 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
4009 .family = MV88E6XXX_FAMILY_6185,
4010 .name = "Marvell 88E6185",
4011 .num_databases = 256,
4012 .num_ports = 10,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004013 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004014 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004015 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004016 .g1_irqs = 8,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004017 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004018 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004019 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004020 },
4021
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004022 [MV88E6190] = {
4023 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
4024 .family = MV88E6XXX_FAMILY_6390,
4025 .name = "Marvell 88E6190",
4026 .num_databases = 4096,
4027 .num_ports = 11, /* 10 + Z80 */
4028 .port_base_addr = 0x0,
4029 .global1_addr = 0x1b,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004030 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004031 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004032 .g1_irqs = 9,
4033 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4034 .ops = &mv88e6190_ops,
4035 },
4036
4037 [MV88E6190X] = {
4038 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4039 .family = MV88E6XXX_FAMILY_6390,
4040 .name = "Marvell 88E6190X",
4041 .num_databases = 4096,
4042 .num_ports = 11, /* 10 + Z80 */
4043 .port_base_addr = 0x0,
4044 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004045 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004046 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004047 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004048 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4049 .ops = &mv88e6190x_ops,
4050 },
4051
4052 [MV88E6191] = {
4053 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4054 .family = MV88E6XXX_FAMILY_6390,
4055 .name = "Marvell 88E6191",
4056 .num_databases = 4096,
4057 .num_ports = 11, /* 10 + Z80 */
4058 .port_base_addr = 0x0,
4059 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004060 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004061 .g1_irqs = 9,
4062 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004063 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4064 .ops = &mv88e6391_ops,
4065 },
4066
Vivien Didelotf81ec902016-05-09 13:22:58 -04004067 [MV88E6240] = {
4068 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4069 .family = MV88E6XXX_FAMILY_6352,
4070 .name = "Marvell 88E6240",
4071 .num_databases = 4096,
4072 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004073 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004074 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004075 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004076 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004077 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004078 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004079 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004080 },
4081
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004082 [MV88E6290] = {
4083 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4084 .family = MV88E6XXX_FAMILY_6390,
4085 .name = "Marvell 88E6290",
4086 .num_databases = 4096,
4087 .num_ports = 11, /* 10 + Z80 */
4088 .port_base_addr = 0x0,
4089 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004090 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004091 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004092 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004093 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4094 .ops = &mv88e6290_ops,
4095 },
4096
Vivien Didelotf81ec902016-05-09 13:22:58 -04004097 [MV88E6320] = {
4098 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4099 .family = MV88E6XXX_FAMILY_6320,
4100 .name = "Marvell 88E6320",
4101 .num_databases = 4096,
4102 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004103 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004104 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004105 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004106 .g1_irqs = 8,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004107 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004108 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004109 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004110 },
4111
4112 [MV88E6321] = {
4113 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4114 .family = MV88E6XXX_FAMILY_6320,
4115 .name = "Marvell 88E6321",
4116 .num_databases = 4096,
4117 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004118 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004119 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004120 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004121 .g1_irqs = 8,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004122 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004123 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004124 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004125 },
4126
Gregory CLEMENT15587272017-01-30 20:29:35 +01004127 [MV88E6141] = {
4128 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
4129 .family = MV88E6XXX_FAMILY_6341,
4130 .name = "Marvell 88E6341",
4131 .num_databases = 4096,
4132 .num_ports = 6,
4133 .port_base_addr = 0x10,
4134 .global1_addr = 0x1b,
4135 .age_time_coeff = 3750,
4136 .tag_protocol = DSA_TAG_PROTO_EDSA,
4137 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4138 .ops = &mv88e6141_ops,
4139 },
4140
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004141 [MV88E6341] = {
4142 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
4143 .family = MV88E6XXX_FAMILY_6341,
4144 .name = "Marvell 88E6341",
4145 .num_databases = 4096,
4146 .num_ports = 6,
4147 .port_base_addr = 0x10,
4148 .global1_addr = 0x1b,
4149 .age_time_coeff = 3750,
4150 .tag_protocol = DSA_TAG_PROTO_EDSA,
4151 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4152 .ops = &mv88e6341_ops,
4153 },
4154
Vivien Didelotf81ec902016-05-09 13:22:58 -04004155 [MV88E6350] = {
4156 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4157 .family = MV88E6XXX_FAMILY_6351,
4158 .name = "Marvell 88E6350",
4159 .num_databases = 4096,
4160 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004161 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004162 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004163 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004164 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004165 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004166 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004167 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004168 },
4169
4170 [MV88E6351] = {
4171 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4172 .family = MV88E6XXX_FAMILY_6351,
4173 .name = "Marvell 88E6351",
4174 .num_databases = 4096,
4175 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004176 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004177 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004178 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004179 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004180 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004181 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004182 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004183 },
4184
4185 [MV88E6352] = {
4186 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4187 .family = MV88E6XXX_FAMILY_6352,
4188 .name = "Marvell 88E6352",
4189 .num_databases = 4096,
4190 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004191 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04004192 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004193 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004194 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004195 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004196 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004197 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004198 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004199 [MV88E6390] = {
4200 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4201 .family = MV88E6XXX_FAMILY_6390,
4202 .name = "Marvell 88E6390",
4203 .num_databases = 4096,
4204 .num_ports = 11, /* 10 + Z80 */
4205 .port_base_addr = 0x0,
4206 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004207 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004208 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004209 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004210 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4211 .ops = &mv88e6390_ops,
4212 },
4213 [MV88E6390X] = {
4214 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4215 .family = MV88E6XXX_FAMILY_6390,
4216 .name = "Marvell 88E6390X",
4217 .num_databases = 4096,
4218 .num_ports = 11, /* 10 + Z80 */
4219 .port_base_addr = 0x0,
4220 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004221 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004222 .g1_irqs = 9,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004223 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004224 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4225 .ops = &mv88e6390x_ops,
4226 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04004227};
4228
Vivien Didelot5f7c0362016-06-20 13:14:04 -04004229static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04004230{
Vivien Didelota439c062016-04-17 13:23:58 -04004231 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04004232
Vivien Didelot5f7c0362016-06-20 13:14:04 -04004233 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4234 if (mv88e6xxx_table[i].prod_num == prod_num)
4235 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04004236
Vivien Didelotb9b37712015-10-30 19:39:48 -04004237 return NULL;
4238}
4239
Vivien Didelotfad09c72016-06-21 12:28:20 -04004240static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004241{
4242 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04004243 unsigned int prod_num, rev;
4244 u16 id;
4245 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004246
Vivien Didelot8f6345b2016-07-20 18:18:36 -04004247 mutex_lock(&chip->reg_lock);
4248 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4249 mutex_unlock(&chip->reg_lock);
4250 if (err)
4251 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004252
4253 prod_num = (id & 0xfff0) >> 4;
4254 rev = id & 0x000f;
4255
4256 info = mv88e6xxx_lookup_info(prod_num);
4257 if (!info)
4258 return -ENODEV;
4259
Vivien Didelotcaac8542016-06-20 13:14:09 -04004260 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04004261 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004262
Vivien Didelotca070c12016-09-02 14:45:34 -04004263 err = mv88e6xxx_g2_require(chip);
4264 if (err)
4265 return err;
4266
Vivien Didelotfad09c72016-06-21 12:28:20 -04004267 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4268 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004269
4270 return 0;
4271}
4272
Vivien Didelotfad09c72016-06-21 12:28:20 -04004273static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04004274{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004275 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04004276
Vivien Didelotfad09c72016-06-21 12:28:20 -04004277 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4278 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04004279 return NULL;
4280
Vivien Didelotfad09c72016-06-21 12:28:20 -04004281 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04004282
Vivien Didelotfad09c72016-06-21 12:28:20 -04004283 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01004284 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelot469d7292016-06-20 13:14:06 -04004285
Vivien Didelotfad09c72016-06-21 12:28:20 -04004286 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04004287}
4288
Vivien Didelote57e5e72016-08-15 17:19:00 -04004289static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4290{
Vivien Didelota199d8b2016-12-05 17:30:28 -05004291 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
Vivien Didelote57e5e72016-08-15 17:19:00 -04004292 mv88e6xxx_ppu_state_init(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04004293}
4294
Andrew Lunn930188c2016-08-22 16:01:03 +02004295static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4296{
Vivien Didelota199d8b2016-12-05 17:30:28 -05004297 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
Andrew Lunn930188c2016-08-22 16:01:03 +02004298 mv88e6xxx_ppu_state_destroy(chip);
Andrew Lunn930188c2016-08-22 16:01:03 +02004299}
4300
Vivien Didelotfad09c72016-06-21 12:28:20 -04004301static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04004302 struct mii_bus *bus, int sw_addr)
4303{
Vivien Didelot914b32f2016-06-20 13:14:11 -04004304 if (sw_addr == 0)
Vivien Didelotfad09c72016-06-21 12:28:20 -04004305 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
Vivien Didelota0ffff22016-08-15 17:18:58 -04004306 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
Vivien Didelotfad09c72016-06-21 12:28:20 -04004307 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
Vivien Didelot914b32f2016-06-20 13:14:11 -04004308 else
4309 return -EINVAL;
4310
Vivien Didelotfad09c72016-06-21 12:28:20 -04004311 chip->bus = bus;
4312 chip->sw_addr = sw_addr;
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04004313
4314 return 0;
4315}
4316
Andrew Lunn7b314362016-08-22 16:01:01 +02004317static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4318{
Vivien Didelot04bed142016-08-31 18:06:13 -04004319 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02004320
Andrew Lunn443d5a12016-12-03 04:35:18 +01004321 return chip->info->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02004322}
4323
Andrew Lunnfcdce7d2016-05-10 23:27:20 +02004324static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4325 struct device *host_dev, int sw_addr,
4326 void **priv)
Andrew Lunna77d43f2016-04-13 02:40:42 +02004327{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004328 struct mv88e6xxx_chip *chip;
Vivien Didelota439c062016-04-17 13:23:58 -04004329 struct mii_bus *bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02004330 int err;
Andrew Lunna77d43f2016-04-13 02:40:42 +02004331
Vivien Didelota439c062016-04-17 13:23:58 -04004332 bus = dsa_host_dev_to_mii_bus(host_dev);
Andrew Lunnc1569132016-04-13 02:40:45 +02004333 if (!bus)
4334 return NULL;
4335
Vivien Didelotfad09c72016-06-21 12:28:20 -04004336 chip = mv88e6xxx_alloc_chip(dsa_dev);
4337 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04004338 return NULL;
4339
Vivien Didelotcaac8542016-06-20 13:14:09 -04004340 /* Legacy SMI probing will only support chips similar to 88E6085 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04004341 chip->info = &mv88e6xxx_table[MV88E6085];
Vivien Didelotcaac8542016-06-20 13:14:09 -04004342
Vivien Didelotfad09c72016-06-21 12:28:20 -04004343 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04004344 if (err)
4345 goto free;
4346
Vivien Didelotfad09c72016-06-21 12:28:20 -04004347 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004348 if (err)
Vivien Didelot469d7292016-06-20 13:14:06 -04004349 goto free;
Vivien Didelota439c062016-04-17 13:23:58 -04004350
Andrew Lunndc30c352016-10-16 19:56:49 +02004351 mutex_lock(&chip->reg_lock);
4352 err = mv88e6xxx_switch_reset(chip);
4353 mutex_unlock(&chip->reg_lock);
4354 if (err)
4355 goto free;
4356
Vivien Didelote57e5e72016-08-15 17:19:00 -04004357 mv88e6xxx_phy_init(chip);
4358
Andrew Lunna3c53be52017-01-24 14:53:50 +01004359 err = mv88e6xxx_mdios_register(chip, NULL);
Andrew Lunnb516d452016-06-04 21:17:06 +02004360 if (err)
Vivien Didelot469d7292016-06-20 13:14:06 -04004361 goto free;
Andrew Lunnb516d452016-06-04 21:17:06 +02004362
Vivien Didelotfad09c72016-06-21 12:28:20 -04004363 *priv = chip;
Vivien Didelota439c062016-04-17 13:23:58 -04004364
Vivien Didelotfad09c72016-06-21 12:28:20 -04004365 return chip->info->name;
Vivien Didelot469d7292016-06-20 13:14:06 -04004366free:
Vivien Didelotfad09c72016-06-21 12:28:20 -04004367 devm_kfree(dsa_dev, chip);
Vivien Didelot469d7292016-06-20 13:14:06 -04004368
4369 return NULL;
Andrew Lunna77d43f2016-04-13 02:40:42 +02004370}
4371
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004372static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4373 const struct switchdev_obj_port_mdb *mdb,
4374 struct switchdev_trans *trans)
4375{
4376 /* We don't need any dynamic resource from the kernel (yet),
4377 * so skip the prepare phase.
4378 */
4379
4380 return 0;
4381}
4382
4383static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4384 const struct switchdev_obj_port_mdb *mdb,
4385 struct switchdev_trans *trans)
4386{
Vivien Didelot04bed142016-08-31 18:06:13 -04004387 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004388
4389 mutex_lock(&chip->reg_lock);
4390 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4391 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4392 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4393 mutex_unlock(&chip->reg_lock);
4394}
4395
4396static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4397 const struct switchdev_obj_port_mdb *mdb)
4398{
Vivien Didelot04bed142016-08-31 18:06:13 -04004399 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004400 int err;
4401
4402 mutex_lock(&chip->reg_lock);
4403 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4404 GLOBAL_ATU_DATA_STATE_UNUSED);
4405 mutex_unlock(&chip->reg_lock);
4406
4407 return err;
4408}
4409
4410static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4411 struct switchdev_obj_port_mdb *mdb,
4412 int (*cb)(struct switchdev_obj *obj))
4413{
Vivien Didelot04bed142016-08-31 18:06:13 -04004414 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004415 int err;
4416
4417 mutex_lock(&chip->reg_lock);
4418 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4419 mutex_unlock(&chip->reg_lock);
4420
4421 return err;
4422}
4423
Florian Fainellia82f67a2017-01-08 14:52:08 -08004424static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunnfcdce7d2016-05-10 23:27:20 +02004425 .probe = mv88e6xxx_drv_probe,
Andrew Lunn7b314362016-08-22 16:01:01 +02004426 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004427 .setup = mv88e6xxx_setup,
4428 .set_addr = mv88e6xxx_set_addr,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004429 .adjust_link = mv88e6xxx_adjust_link,
4430 .get_strings = mv88e6xxx_get_strings,
4431 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4432 .get_sset_count = mv88e6xxx_get_sset_count,
4433 .set_eee = mv88e6xxx_set_eee,
4434 .get_eee = mv88e6xxx_get_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004435 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004436 .get_eeprom = mv88e6xxx_get_eeprom,
4437 .set_eeprom = mv88e6xxx_set_eeprom,
4438 .get_regs_len = mv88e6xxx_get_regs_len,
4439 .get_regs = mv88e6xxx_get_regs,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04004440 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004441 .port_bridge_join = mv88e6xxx_port_bridge_join,
4442 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4443 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04004444 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004445 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4446 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4447 .port_vlan_add = mv88e6xxx_port_vlan_add,
4448 .port_vlan_del = mv88e6xxx_port_vlan_del,
4449 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4450 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4451 .port_fdb_add = mv88e6xxx_port_fdb_add,
4452 .port_fdb_del = mv88e6xxx_port_fdb_del,
4453 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004454 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4455 .port_mdb_add = mv88e6xxx_port_mdb_add,
4456 .port_mdb_del = mv88e6xxx_port_mdb_del,
4457 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004458};
4459
Florian Fainelliab3d4082017-01-08 14:52:07 -08004460static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4461 .ops = &mv88e6xxx_switch_ops,
4462};
4463
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004464static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004465{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004466 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004467 struct dsa_switch *ds;
4468
Vivien Didelota0c02162017-01-27 15:29:36 -05004469 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004470 if (!ds)
4471 return -ENOMEM;
4472
Vivien Didelotfad09c72016-06-21 12:28:20 -04004473 ds->priv = chip;
Vivien Didelot9d490b42016-08-23 12:38:56 -04004474 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004475
4476 dev_set_drvdata(dev, ds);
4477
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004478 return dsa_register_switch(ds, dev);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004479}
4480
Vivien Didelotfad09c72016-06-21 12:28:20 -04004481static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004482{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004483 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004484}
4485
Vivien Didelot57d32312016-06-20 13:13:58 -04004486static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004487{
4488 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004489 struct device_node *np = dev->of_node;
Vivien Didelotcaac8542016-06-20 13:14:09 -04004490 const struct mv88e6xxx_info *compat_info;
Vivien Didelotfad09c72016-06-21 12:28:20 -04004491 struct mv88e6xxx_chip *chip;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004492 u32 eeprom_len;
Andrew Lunn52638f72016-05-10 23:27:22 +02004493 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004494
Vivien Didelotcaac8542016-06-20 13:14:09 -04004495 compat_info = of_device_get_match_data(dev);
4496 if (!compat_info)
4497 return -EINVAL;
4498
Vivien Didelotfad09c72016-06-21 12:28:20 -04004499 chip = mv88e6xxx_alloc_chip(dev);
4500 if (!chip)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004501 return -ENOMEM;
4502
Vivien Didelotfad09c72016-06-21 12:28:20 -04004503 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04004504
Andrew Lunn56995cb2016-12-03 04:35:19 +01004505 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4506 if (err)
4507 return err;
4508
Vivien Didelotfad09c72016-06-21 12:28:20 -04004509 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04004510 if (err)
4511 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004512
Andrew Lunnb4308f02016-11-21 23:26:55 +01004513 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4514 if (IS_ERR(chip->reset))
4515 return PTR_ERR(chip->reset);
4516
Vivien Didelotfad09c72016-06-21 12:28:20 -04004517 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004518 if (err)
4519 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004520
Vivien Didelote57e5e72016-08-15 17:19:00 -04004521 mv88e6xxx_phy_init(chip);
4522
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004523 if (chip->info->ops->get_eeprom &&
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004524 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
Vivien Didelotfad09c72016-06-21 12:28:20 -04004525 chip->eeprom_len = eeprom_len;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004526
Andrew Lunndc30c352016-10-16 19:56:49 +02004527 mutex_lock(&chip->reg_lock);
4528 err = mv88e6xxx_switch_reset(chip);
4529 mutex_unlock(&chip->reg_lock);
Andrew Lunnb516d452016-06-04 21:17:06 +02004530 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02004531 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02004532
Andrew Lunndc30c352016-10-16 19:56:49 +02004533 chip->irq = of_irq_get(np, 0);
4534 if (chip->irq == -EPROBE_DEFER) {
4535 err = chip->irq;
4536 goto out;
Andrew Lunn83c0afa2016-06-04 21:17:07 +02004537 }
4538
Andrew Lunndc30c352016-10-16 19:56:49 +02004539 if (chip->irq > 0) {
4540 /* Has to be performed before the MDIO bus is created,
4541 * because the PHYs will link there interrupts to these
4542 * interrupt controllers
4543 */
4544 mutex_lock(&chip->reg_lock);
4545 err = mv88e6xxx_g1_irq_setup(chip);
4546 mutex_unlock(&chip->reg_lock);
4547
4548 if (err)
4549 goto out;
4550
4551 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4552 err = mv88e6xxx_g2_irq_setup(chip);
4553 if (err)
4554 goto out_g1_irq;
4555 }
4556 }
4557
Andrew Lunna3c53be52017-01-24 14:53:50 +01004558 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02004559 if (err)
4560 goto out_g2_irq;
4561
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004562 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004563 if (err)
4564 goto out_mdio;
4565
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004566 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02004567
4568out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01004569 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004570out_g2_irq:
Andrew Lunn467126442016-11-20 20:14:15 +01004571 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02004572 mv88e6xxx_g2_irq_free(chip);
4573out_g1_irq:
Andrew Lunn61f7c3f2016-11-20 20:14:19 +01004574 if (chip->irq > 0) {
4575 mutex_lock(&chip->reg_lock);
Andrew Lunn467126442016-11-20 20:14:15 +01004576 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn61f7c3f2016-11-20 20:14:19 +01004577 mutex_unlock(&chip->reg_lock);
4578 }
Andrew Lunndc30c352016-10-16 19:56:49 +02004579out:
4580 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004581}
4582
4583static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4584{
4585 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vivien Didelot04bed142016-08-31 18:06:13 -04004586 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004587
Andrew Lunn930188c2016-08-22 16:01:03 +02004588 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04004589 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01004590 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004591
Andrew Lunn467126442016-11-20 20:14:15 +01004592 if (chip->irq > 0) {
4593 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4594 mv88e6xxx_g2_irq_free(chip);
4595 mv88e6xxx_g1_irq_free(chip);
4596 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004597}
4598
4599static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04004600 {
4601 .compatible = "marvell,mv88e6085",
4602 .data = &mv88e6xxx_table[MV88E6085],
4603 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004604 {
4605 .compatible = "marvell,mv88e6190",
4606 .data = &mv88e6xxx_table[MV88E6190],
4607 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004608 { /* sentinel */ },
4609};
4610
4611MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4612
4613static struct mdio_driver mv88e6xxx_driver = {
4614 .probe = mv88e6xxx_probe,
4615 .remove = mv88e6xxx_remove,
4616 .mdiodrv.driver = {
4617 .name = "mv88e6085",
4618 .of_match_table = mv88e6xxx_of_match,
4619 },
4620};
4621
Ben Hutchings98e67302011-11-25 14:36:19 +00004622static int __init mv88e6xxx_init(void)
4623{
Florian Fainelliab3d4082017-01-08 14:52:07 -08004624 register_switch_driver(&mv88e6xxx_switch_drv);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004625 return mdio_driver_register(&mv88e6xxx_driver);
Ben Hutchings98e67302011-11-25 14:36:19 +00004626}
4627module_init(mv88e6xxx_init);
4628
4629static void __exit mv88e6xxx_cleanup(void)
4630{
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004631 mdio_driver_unregister(&mv88e6xxx_driver);
Florian Fainelliab3d4082017-01-08 14:52:07 -08004632 unregister_switch_driver(&mv88e6xxx_switch_drv);
Ben Hutchings98e67302011-11-25 14:36:19 +00004633}
4634module_exit(mv88e6xxx_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00004635
4636MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4637MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4638MODULE_LICENSE("GPL");