blob: c49abfb83cf2aa6703caa89f74dc4ab79e4b07ff [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00002/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04003 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00005 * Copyright (c) 2008 Marvell Semiconductor
6 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02007 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
Vivien Didelot4333d612017-03-28 15:10:36 -04009 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 */
12
Vivien Didelot19fb7f62019-08-09 18:47:55 -040013#include <linux/bitfield.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000014#include <linux/delay.h>
Vladimir Oltean5bded822021-10-07 19:47:11 +030015#include <linux/dsa/mv88e6xxx.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070016#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020017#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070018#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020019#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000022#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000023#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020024#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000025#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040026#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020027#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020028#include <linux/of_mdio.h>
Andrew Lunn877b7cb2018-05-19 22:31:34 +020029#include <linux/platform_data/mv88e6xxx.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000030#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010031#include <linux/gpio/consumer.h>
Russell Kingc9a23562018-05-10 13:17:35 -070032#include <linux/phylink.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000033#include <net/dsa.h>
Vivien Didelotec561272016-09-02 14:45:33 -040034
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -040035#include "chip.h"
Andrew Lunn9dd43aa2020-09-18 21:11:05 +020036#include "devlink.h"
Vivien Didelota935c052016-09-29 12:21:53 -040037#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040038#include "global2.h"
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +010039#include "hwtstamp.h"
Andrew Lunn10fa5bf2017-05-26 01:03:20 +020040#include "phy.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010041#include "port.h"
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +010042#include "ptp.h"
Andrew Lunn6d917822017-05-26 01:03:21 +020043#include "serdes.h"
Vivien Didelote7ba0fa2019-05-03 19:28:22 -040044#include "smi.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000045
Vivien Didelotfad09c72016-06-21 12:28:20 -040046static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040047{
Vivien Didelotfad09c72016-06-21 12:28:20 -040048 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040050 dump_stack();
51 }
52}
53
Vivien Didelotec561272016-09-02 14:45:33 -040054int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040055{
56 int err;
57
Vivien Didelotfad09c72016-06-21 12:28:20 -040058 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040059
Vivien Didelotfad09c72016-06-21 12:28:20 -040060 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040061 if (err)
62 return err;
63
Vivien Didelotfad09c72016-06-21 12:28:20 -040064 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040065 addr, reg, *val);
66
67 return 0;
68}
69
Vivien Didelotec561272016-09-02 14:45:33 -040070int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040071{
72 int err;
73
Vivien Didelotfad09c72016-06-21 12:28:20 -040074 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040075
Vivien Didelotfad09c72016-06-21 12:28:20 -040076 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040077 if (err)
78 return err;
79
Vivien Didelotfad09c72016-06-21 12:28:20 -040080 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040081 addr, reg, val);
82
83 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000084}
85
Vivien Didelot683f2242019-08-09 18:47:54 -040086int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88{
89 u16 data;
90 int err;
91 int i;
92
93 /* There's no bus specific operation to wait for a mask */
94 for (i = 0; i < 16; i++) {
95 err = mv88e6xxx_read(chip, addr, reg, &data);
96 if (err)
97 return err;
98
99 if ((data & mask) == val)
100 return 0;
101
102 usleep_range(1000, 2000);
103 }
104
105 dev_err(chip->dev, "Timeout while waiting for switch\n");
106 return -ETIMEDOUT;
107}
108
Vivien Didelot19fb7f62019-08-09 18:47:55 -0400109int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
110 int bit, int val)
111{
112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
113 val ? BIT(bit) : 0x0000);
114}
115
Andrew Lunn10fa5bf2017-05-26 01:03:20 +0200116struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
Andrew Lunna3c53be52017-01-24 14:53:50 +0100117{
118 struct mv88e6xxx_mdio_bus *mdio_bus;
119
120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
121 list);
122 if (!mdio_bus)
123 return NULL;
124
125 return mdio_bus->bus;
126}
127
Andrew Lunndc30c352016-10-16 19:56:49 +0200128static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
129{
130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
131 unsigned int n = d->hwirq;
132
133 chip->g1_irq.masked |= (1 << n);
134}
135
136static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
137{
138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
139 unsigned int n = d->hwirq;
140
141 chip->g1_irq.masked &= ~(1 << n);
142}
143
Andrew Lunn294d7112018-02-22 22:58:32 +0100144static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200145{
Andrew Lunndc30c352016-10-16 19:56:49 +0200146 unsigned int nhandled = 0;
147 unsigned int sub_irq;
148 unsigned int n;
149 u16 reg;
John David Anglin7c0db242019-02-11 13:40:21 -0500150 u16 ctl1;
Andrew Lunndc30c352016-10-16 19:56:49 +0200151 int err;
152
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000153 mv88e6xxx_reg_lock(chip);
Vivien Didelot82466922017-06-15 12:13:59 -0400154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000155 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200156
157 if (err)
158 goto out;
159
John David Anglin7c0db242019-02-11 13:40:21 -0500160 do {
161 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
162 if (reg & (1 << n)) {
163 sub_irq = irq_find_mapping(chip->g1_irq.domain,
164 n);
165 handle_nested_irq(sub_irq);
166 ++nhandled;
167 }
Andrew Lunndc30c352016-10-16 19:56:49 +0200168 }
John David Anglin7c0db242019-02-11 13:40:21 -0500169
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000170 mv88e6xxx_reg_lock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
172 if (err)
173 goto unlock;
174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
175unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000176 mv88e6xxx_reg_unlock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500177 if (err)
178 goto out;
179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
180 } while (reg & ctl1);
181
Andrew Lunndc30c352016-10-16 19:56:49 +0200182out:
183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
184}
185
Andrew Lunn294d7112018-02-22 22:58:32 +0100186static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
187{
188 struct mv88e6xxx_chip *chip = dev_id;
189
190 return mv88e6xxx_g1_irq_thread_work(chip);
191}
192
Andrew Lunndc30c352016-10-16 19:56:49 +0200193static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
194{
195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
196
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000197 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200198}
199
200static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
201{
202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
204 u16 reg;
205 int err;
206
Vivien Didelotd77f4322017-06-15 12:14:03 -0400207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200208 if (err)
209 goto out;
210
211 reg &= ~mask;
212 reg |= (~chip->g1_irq.masked & mask);
213
Vivien Didelotd77f4322017-06-15 12:14:03 -0400214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200215 if (err)
216 goto out;
217
218out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000219 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200220}
221
Bhumika Goyal6eb15e22017-08-19 16:25:52 +0530222static const struct irq_chip mv88e6xxx_g1_irq_chip = {
Andrew Lunndc30c352016-10-16 19:56:49 +0200223 .name = "mv88e6xxx-g1",
224 .irq_mask = mv88e6xxx_g1_irq_mask,
225 .irq_unmask = mv88e6xxx_g1_irq_unmask,
226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
228};
229
230static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
231 unsigned int irq,
232 irq_hw_number_t hwirq)
233{
234 struct mv88e6xxx_chip *chip = d->host_data;
235
236 irq_set_chip_data(irq, d->host_data);
237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
238 irq_set_noprobe(irq);
239
240 return 0;
241}
242
243static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
244 .map = mv88e6xxx_g1_irq_domain_map,
245 .xlate = irq_domain_xlate_twocell,
246};
247
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200248/* To be called with reg_lock held */
Andrew Lunn294d7112018-02-22 22:58:32 +0100249static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200250{
251 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100252 u16 mask;
253
Vivien Didelotd77f4322017-06-15 12:14:03 -0400254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3460a572016-11-20 20:14:16 +0100257
Andreas Färber5edef2f2016-11-27 23:26:28 +0100258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100259 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200260 irq_dispose_mapping(virq);
261 }
262
Andrew Lunna3db3d32016-11-20 20:14:14 +0100263 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200264}
265
Andrew Lunn294d7112018-02-22 22:58:32 +0100266static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
267{
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200268 /*
269 * free_irq must be called without reg_lock taken because the irq
270 * handler takes this lock, too.
271 */
Andrew Lunn294d7112018-02-22 22:58:32 +0100272 free_irq(chip->irq, chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200273
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000274 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200275 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000276 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100277}
278
279static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200280{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100281 int err, irq, virq;
282 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200283
284 chip->g1_irq.nirqs = chip->info->g1_irqs;
285 chip->g1_irq.domain = irq_domain_add_simple(
286 NULL, chip->g1_irq.nirqs, 0,
287 &mv88e6xxx_g1_irq_domain_ops, chip);
288 if (!chip->g1_irq.domain)
289 return -ENOMEM;
290
291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
292 irq_create_mapping(chip->g1_irq.domain, irq);
293
294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
295 chip->g1_irq.masked = ~0;
296
Vivien Didelotd77f4322017-06-15 12:14:03 -0400297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200298 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100299 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200300
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200302
Vivien Didelotd77f4322017-06-15 12:14:03 -0400303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200304 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100305 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200306
307 /* Reading the interrupt status clears (most of) them */
Vivien Didelot82466922017-06-15 12:13:59 -0400308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200309 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100310 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200311
Andrew Lunndc30c352016-10-16 19:56:49 +0200312 return 0;
313
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100314out_disable:
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100317
318out_mapping:
319 for (irq = 0; irq < 16; irq++) {
320 virq = irq_find_mapping(chip->g1_irq.domain, irq);
321 irq_dispose_mapping(virq);
322 }
323
324 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200325
326 return err;
327}
328
Andrew Lunn294d7112018-02-22 22:58:32 +0100329static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
330{
Andrew Lunnf6d97582019-02-23 17:43:56 +0100331 static struct lock_class_key lock_key;
332 static struct lock_class_key request_key;
Andrew Lunn294d7112018-02-22 22:58:32 +0100333 int err;
334
335 err = mv88e6xxx_g1_irq_setup_common(chip);
336 if (err)
337 return err;
338
Andrew Lunnf6d97582019-02-23 17:43:56 +0100339 /* These lock classes tells lockdep that global 1 irqs are in
340 * a different category than their parent GPIO, so it won't
341 * report false recursion.
342 */
343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
344
Andrew Lunn30953832020-01-06 17:13:48 +0100345 snprintf(chip->irq_name, sizeof(chip->irq_name),
346 "mv88e6xxx-%s", dev_name(chip->dev));
347
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000348 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100349 err = request_threaded_irq(chip->irq, NULL,
350 mv88e6xxx_g1_irq_thread_fn,
Marek Behún03403762018-08-30 02:13:50 +0200351 IRQF_ONESHOT | IRQF_SHARED,
Andrew Lunn30953832020-01-06 17:13:48 +0100352 chip->irq_name, chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000353 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100354 if (err)
355 mv88e6xxx_g1_irq_free_common(chip);
356
357 return err;
358}
359
360static void mv88e6xxx_irq_poll(struct kthread_work *work)
361{
362 struct mv88e6xxx_chip *chip = container_of(work,
363 struct mv88e6xxx_chip,
364 irq_poll_work.work);
365 mv88e6xxx_g1_irq_thread_work(chip);
366
367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
368 msecs_to_jiffies(100));
369}
370
371static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
372{
373 int err;
374
375 err = mv88e6xxx_g1_irq_setup_common(chip);
376 if (err)
377 return err;
378
379 kthread_init_delayed_work(&chip->irq_poll_work,
380 mv88e6xxx_irq_poll);
381
Florian Fainelli3f8b8692019-02-21 20:09:27 -0800382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
Andrew Lunn294d7112018-02-22 22:58:32 +0100383 if (IS_ERR(chip->kworker))
384 return PTR_ERR(chip->kworker);
385
386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
387 msecs_to_jiffies(100));
388
389 return 0;
390}
391
392static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
393{
394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
395 kthread_destroy_worker(chip->kworker);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200396
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000397 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200398 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000399 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100400}
401
Russell King64d47d52020-03-14 10:15:38 +0000402static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
403 int port, phy_interface_t interface)
404{
405 int err;
406
407 if (chip->info->ops->port_set_rgmii_delay) {
408 err = chip->info->ops->port_set_rgmii_delay(chip, port,
409 interface);
410 if (err && err != -EOPNOTSUPP)
411 return err;
412 }
413
414 if (chip->info->ops->port_set_cmode) {
415 err = chip->info->ops->port_set_cmode(chip, port,
416 interface);
417 if (err && err != -EOPNOTSUPP)
418 return err;
419 }
420
421 return 0;
422}
423
Russell Kinga5a68582020-03-14 10:15:43 +0000424static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
425 int link, int speed, int duplex, int pause,
426 phy_interface_t mode)
Vivien Didelotd78343d2016-11-04 03:23:36 +0100427{
428 int err;
429
430 if (!chip->info->ops->port_set_link)
431 return 0;
432
433 /* Port's MAC control must not be changed unless the link is down */
Hubert Feurstein43c8e0a2019-07-30 12:11:42 +0200434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100435 if (err)
436 return err;
437
Russell Kingf365c6f2020-03-14 10:15:53 +0000438 if (chip->info->ops->port_set_speed_duplex) {
439 err = chip->info->ops->port_set_speed_duplex(chip, port,
440 speed, duplex);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100441 if (err && err != -EOPNOTSUPP)
442 goto restore_link;
443 }
444
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
446 mode = chip->info->ops->port_max_speed_mode(port);
447
Andrew Lunn54186b92018-08-09 15:38:37 +0200448 if (chip->info->ops->port_set_pause) {
449 err = chip->info->ops->port_set_pause(chip, port, pause);
450 if (err)
451 goto restore_link;
452 }
453
Russell King64d47d52020-03-14 10:15:38 +0000454 err = mv88e6xxx_port_config_interface(chip, port, mode);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100455restore_link:
456 if (chip->info->ops->port_set_link(chip, port, link))
Vivien Didelot774439e52017-06-08 18:34:08 -0400457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100458
459 return err;
460}
461
Marek Vasutd700ec42018-09-12 00:15:24 +0200462static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
463{
464 struct mv88e6xxx_chip *chip = ds->priv;
465
466 return port < chip->info->num_internal_phys;
467}
468
Russell King5d5b2312020-03-14 10:16:03 +0000469static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
470{
471 u16 reg;
472 int err;
473
474 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
475 if (err) {
476 dev_err(chip->dev,
477 "p%d: %s: failed to read port status\n",
478 port, __func__);
479 return err;
480 }
481
482 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
483}
484
Russell Kinga5a68582020-03-14 10:15:43 +0000485static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
486 struct phylink_link_state *state)
487{
488 struct mv88e6xxx_chip *chip = ds->priv;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100489 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000490 int err;
491
492 mv88e6xxx_reg_lock(chip);
493 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100494 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
Russell Kinga5a68582020-03-14 10:15:43 +0000495 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
496 state);
497 else
498 err = -EOPNOTSUPP;
499 mv88e6xxx_reg_unlock(chip);
500
501 return err;
502}
503
504static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
505 unsigned int mode,
506 phy_interface_t interface,
507 const unsigned long *advertise)
508{
509 const struct mv88e6xxx_ops *ops = chip->info->ops;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100510 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000511
512 if (ops->serdes_pcs_config) {
513 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100514 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000515 return ops->serdes_pcs_config(chip, port, lane, mode,
516 interface, advertise);
517 }
518
519 return 0;
520}
521
522static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
523{
524 struct mv88e6xxx_chip *chip = ds->priv;
525 const struct mv88e6xxx_ops *ops;
526 int err = 0;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100527 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000528
529 ops = chip->info->ops;
530
531 if (ops->serdes_pcs_an_restart) {
532 mv88e6xxx_reg_lock(chip);
533 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100534 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000535 err = ops->serdes_pcs_an_restart(chip, port, lane);
536 mv88e6xxx_reg_unlock(chip);
537
538 if (err)
539 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
540 }
541}
542
543static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
544 unsigned int mode,
545 int speed, int duplex)
546{
547 const struct mv88e6xxx_ops *ops = chip->info->ops;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100548 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000549
550 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
551 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100552 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000553 return ops->serdes_pcs_link_up(chip, port, lane,
554 speed, duplex);
555 }
556
557 return 0;
558}
559
Russell King6c422e32018-08-09 15:38:39 +0200560static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
561 unsigned long *mask,
562 struct phylink_link_state *state)
563{
564 if (!phy_interface_mode_is_8023z(state->interface)) {
565 /* 10M and 100M are only supported in non-802.3z mode */
566 phylink_set(mask, 10baseT_Half);
567 phylink_set(mask, 10baseT_Full);
568 phylink_set(mask, 100baseT_Half);
569 phylink_set(mask, 100baseT_Full);
570 }
571}
572
573static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
574 unsigned long *mask,
575 struct phylink_link_state *state)
576{
577 /* FIXME: if the port is in 1000Base-X mode, then it only supports
578 * 1000M FD speeds. In this case, CMODE will indicate 5.
579 */
580 phylink_set(mask, 1000baseT_Full);
581 phylink_set(mask, 1000baseX_Full);
582
583 mv88e6065_phylink_validate(chip, port, mask, state);
584}
585
Marek Behúne3af71a2019-02-25 12:39:55 +0100586static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
587 unsigned long *mask,
588 struct phylink_link_state *state)
589{
590 if (port >= 5)
591 phylink_set(mask, 2500baseX_Full);
592
593 /* No ethtool bits for 200Mbps */
594 phylink_set(mask, 1000baseT_Full);
595 phylink_set(mask, 1000baseX_Full);
596
597 mv88e6065_phylink_validate(chip, port, mask, state);
598}
599
Russell King6c422e32018-08-09 15:38:39 +0200600static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
601 unsigned long *mask,
602 struct phylink_link_state *state)
603{
604 /* No ethtool bits for 200Mbps */
605 phylink_set(mask, 1000baseT_Full);
606 phylink_set(mask, 1000baseX_Full);
607
608 mv88e6065_phylink_validate(chip, port, mask, state);
609}
610
611static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
612 unsigned long *mask,
613 struct phylink_link_state *state)
614{
Andrew Lunnec260162019-02-08 22:25:44 +0100615 if (port >= 9) {
Russell King6c422e32018-08-09 15:38:39 +0200616 phylink_set(mask, 2500baseX_Full);
Andrew Lunnec260162019-02-08 22:25:44 +0100617 phylink_set(mask, 2500baseT_Full);
618 }
Russell King6c422e32018-08-09 15:38:39 +0200619
620 /* No ethtool bits for 200Mbps */
621 phylink_set(mask, 1000baseT_Full);
622 phylink_set(mask, 1000baseX_Full);
623
624 mv88e6065_phylink_validate(chip, port, mask, state);
625}
626
627static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
628 unsigned long *mask,
629 struct phylink_link_state *state)
630{
631 if (port >= 9) {
632 phylink_set(mask, 10000baseT_Full);
633 phylink_set(mask, 10000baseKR_Full);
634 }
635
636 mv88e6390_phylink_validate(chip, port, mask, state);
637}
638
Pavana Sharmade776d02021-03-17 14:46:42 +0100639static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
640 unsigned long *mask,
641 struct phylink_link_state *state)
642{
Marek Behúndc2fc9f2021-11-04 18:17:47 +0100643 bool is_6191x =
644 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
645
646 if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
Pavana Sharmade776d02021-03-17 14:46:42 +0100647 phylink_set(mask, 10000baseT_Full);
648 phylink_set(mask, 10000baseKR_Full);
649 phylink_set(mask, 10000baseCR_Full);
650 phylink_set(mask, 10000baseSR_Full);
651 phylink_set(mask, 10000baseLR_Full);
652 phylink_set(mask, 10000baseLRM_Full);
653 phylink_set(mask, 10000baseER_Full);
654 phylink_set(mask, 5000baseT_Full);
655 phylink_set(mask, 2500baseX_Full);
656 phylink_set(mask, 2500baseT_Full);
657 }
658
659 phylink_set(mask, 1000baseT_Full);
660 phylink_set(mask, 1000baseX_Full);
661
662 mv88e6065_phylink_validate(chip, port, mask, state);
663}
664
Russell Kingc9a23562018-05-10 13:17:35 -0700665static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
666 unsigned long *supported,
667 struct phylink_link_state *state)
668{
Russell King6c422e32018-08-09 15:38:39 +0200669 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
670 struct mv88e6xxx_chip *chip = ds->priv;
671
672 /* Allow all the expected bits */
673 phylink_set(mask, Autoneg);
674 phylink_set(mask, Pause);
675 phylink_set_port_modes(mask);
676
677 if (chip->info->ops->phylink_validate)
678 chip->info->ops->phylink_validate(chip, port, mask, state);
679
Sean Anderson49730562021-10-22 18:41:04 -0400680 linkmode_and(supported, supported, mask);
681 linkmode_and(state->advertising, state->advertising, mask);
Russell King6c422e32018-08-09 15:38:39 +0200682
683 /* We can only operate at 2500BaseX or 1000BaseX. If requested
684 * to advertise both, only report advertising at 2500BaseX.
685 */
686 phylink_helper_basex_speed(state);
Russell Kingc9a23562018-05-10 13:17:35 -0700687}
688
Russell Kingc9a23562018-05-10 13:17:35 -0700689static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
690 unsigned int mode,
691 const struct phylink_link_state *state)
692{
693 struct mv88e6xxx_chip *chip = ds->priv;
Russell Kingfad58192020-07-19 12:00:35 +0100694 struct mv88e6xxx_port *p;
Russell King64d47d52020-03-14 10:15:38 +0000695 int err;
Russell Kingc9a23562018-05-10 13:17:35 -0700696
Russell Kingfad58192020-07-19 12:00:35 +0100697 p = &chip->ports[port];
698
Russell King64d47d52020-03-14 10:15:38 +0000699 /* FIXME: is this the correct test? If we're in fixed mode on an
700 * internal port, why should we process this any different from
701 * PHY mode? On the other hand, the port may be automedia between
702 * an internal PHY and the serdes...
703 */
Marek Vasutd700ec42018-09-12 00:15:24 +0200704 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
Russell Kingc9a23562018-05-10 13:17:35 -0700705 return;
706
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000707 mv88e6xxx_reg_lock(chip);
Russell Kingfad58192020-07-19 12:00:35 +0100708 /* In inband mode, the link may come up at any time while the link
709 * is not forced down. Force the link down while we reconfigure the
710 * interface mode.
Russell King64d47d52020-03-14 10:15:38 +0000711 */
Russell Kingfad58192020-07-19 12:00:35 +0100712 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
713 chip->info->ops->port_set_link)
714 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
715
Russell King64d47d52020-03-14 10:15:38 +0000716 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
Russell Kinga5a68582020-03-14 10:15:43 +0000717 if (err && err != -EOPNOTSUPP)
718 goto err_unlock;
719
720 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
721 state->advertising);
722 /* FIXME: we should restart negotiation if something changed - which
723 * is something we get if we convert to using phylinks PCS operations.
724 */
725 if (err > 0)
726 err = 0;
727
Russell Kingfad58192020-07-19 12:00:35 +0100728 /* Undo the forced down state above after completing configuration
729 * irrespective of its state on entry, which allows the link to come up.
730 */
731 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
732 chip->info->ops->port_set_link)
733 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
734
735 p->interface = state->interface;
736
Russell Kinga5a68582020-03-14 10:15:43 +0000737err_unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000738 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700739
740 if (err && err != -EOPNOTSUPP)
Russell King64d47d52020-03-14 10:15:38 +0000741 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700742}
743
Russell Kingc9a23562018-05-10 13:17:35 -0700744static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
745 unsigned int mode,
746 phy_interface_t interface)
747{
Russell King30c4a5b2020-02-26 10:23:51 +0000748 struct mv88e6xxx_chip *chip = ds->priv;
749 const struct mv88e6xxx_ops *ops;
750 int err = 0;
751
752 ops = chip->info->ops;
753
Russell King5d5b2312020-03-14 10:16:03 +0000754 mv88e6xxx_reg_lock(chip);
Maarten Zanders4a3e0ae2021-10-11 16:27:20 +0200755 /* Internal PHYs propagate their configuration directly to the MAC.
756 * External PHYs depend on whether the PPU is enabled for this port.
757 */
758 if (((!mv88e6xxx_phy_is_internal(ds, port) &&
759 !mv88e6xxx_port_ppu_updates(chip, port)) ||
Chris Packham4efe76622020-11-24 17:34:37 +1300760 mode == MLO_AN_FIXED) && ops->port_sync_link)
761 err = ops->port_sync_link(chip, port, mode, false);
Russell King5d5b2312020-03-14 10:16:03 +0000762 mv88e6xxx_reg_unlock(chip);
Russell King30c4a5b2020-02-26 10:23:51 +0000763
Russell King5d5b2312020-03-14 10:16:03 +0000764 if (err)
765 dev_err(chip->dev,
766 "p%d: failed to force MAC link down\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700767}
768
769static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
770 unsigned int mode, phy_interface_t interface,
Russell King5b502a72020-02-26 10:23:46 +0000771 struct phy_device *phydev,
772 int speed, int duplex,
773 bool tx_pause, bool rx_pause)
Russell Kingc9a23562018-05-10 13:17:35 -0700774{
Russell King30c4a5b2020-02-26 10:23:51 +0000775 struct mv88e6xxx_chip *chip = ds->priv;
776 const struct mv88e6xxx_ops *ops;
777 int err = 0;
778
779 ops = chip->info->ops;
780
Russell King5d5b2312020-03-14 10:16:03 +0000781 mv88e6xxx_reg_lock(chip);
Maarten Zanders4a3e0ae2021-10-11 16:27:20 +0200782 /* Internal PHYs propagate their configuration directly to the MAC.
783 * External PHYs depend on whether the PPU is enabled for this port.
784 */
785 if ((!mv88e6xxx_phy_is_internal(ds, port) &&
786 !mv88e6xxx_port_ppu_updates(chip, port)) ||
787 mode == MLO_AN_FIXED) {
Russell King30c4a5b2020-02-26 10:23:51 +0000788 /* FIXME: for an automedia port, should we force the link
789 * down here - what if the link comes up due to "other" media
790 * while we're bringing the port up, how is the exclusivity
Russell Kinga5a68582020-03-14 10:15:43 +0000791 * handled in the Marvell hardware? E.g. port 2 on 88E6390
Russell King30c4a5b2020-02-26 10:23:51 +0000792 * shared between internal PHY and Serdes.
793 */
Russell Kinga5a68582020-03-14 10:15:43 +0000794 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
795 duplex);
796 if (err)
797 goto error;
798
Russell Kingf365c6f2020-03-14 10:15:53 +0000799 if (ops->port_set_speed_duplex) {
800 err = ops->port_set_speed_duplex(chip, port,
801 speed, duplex);
Russell King30c4a5b2020-02-26 10:23:51 +0000802 if (err && err != -EOPNOTSUPP)
803 goto error;
804 }
805
Chris Packham4efe76622020-11-24 17:34:37 +1300806 if (ops->port_sync_link)
807 err = ops->port_sync_link(chip, port, mode, true);
Russell King30c4a5b2020-02-26 10:23:51 +0000808 }
Russell King5d5b2312020-03-14 10:16:03 +0000809error:
810 mv88e6xxx_reg_unlock(chip);
811
812 if (err && err != -EOPNOTSUPP)
813 dev_err(ds->dev,
814 "p%d: failed to configure MAC link up\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700815}
816
Andrew Lunna605a0f2016-11-21 23:26:58 +0100817static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000818{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100819 if (!chip->info->ops->stats_snapshot)
820 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000821
Andrew Lunna605a0f2016-11-21 23:26:58 +0100822 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000823}
824
Andrew Lunne413e7e2015-04-02 04:06:38 +0200825static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100826 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
827 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
828 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
829 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
830 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
831 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
832 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
833 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
834 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
835 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
836 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
837 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
838 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
839 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
840 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
841 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
842 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
843 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
844 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
845 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
846 { "single", 4, 0x14, STATS_TYPE_BANK0, },
847 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
848 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
849 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
850 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
851 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
852 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
853 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
854 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
855 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
856 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
857 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
858 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
859 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
860 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
861 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
862 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
863 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
864 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
865 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
866 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
867 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
868 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
869 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
870 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
871 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
872 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
873 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
874 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
875 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
876 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
877 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
878 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
879 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
880 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
881 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
882 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
883 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
884 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200885};
886
Vivien Didelotfad09c72016-06-21 12:28:20 -0400887static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100888 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100889 int port, u16 bank1_select,
890 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200891{
Andrew Lunn80c46272015-06-20 18:42:30 +0200892 u32 low;
893 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100894 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200895 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200896 u64 value;
897
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100898 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100899 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200900 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
901 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800902 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200903
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200904 low = reg;
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100905 if (s->size == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200906 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
907 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800908 return U64_MAX;
Rasmus Villemoes84b3fd12019-05-29 07:02:11 +0000909 low |= ((u32)reg) << 16;
Andrew Lunn80c46272015-06-20 18:42:30 +0200910 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100911 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100912 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100913 reg = bank1_select;
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -0500914 fallthrough;
Andrew Lunndfafe442016-11-21 23:27:02 +0100915 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100916 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100917 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100918 if (s->size == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100919 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Gustavo A. R. Silva9fc3e4d2017-05-11 22:11:29 -0500920 break;
921 default:
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800922 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200923 }
Andrew Lunn6e46e2d2019-02-28 18:14:03 +0100924 value = (((u64)high) << 32) | low;
Andrew Lunn80c46272015-06-20 18:42:30 +0200925 return value;
926}
927
Andrew Lunn436fe172018-03-01 02:02:29 +0100928static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
929 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100930{
931 struct mv88e6xxx_hw_stat *stat;
932 int i, j;
933
934 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
935 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100936 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100937 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
938 ETH_GSTRING_LEN);
939 j++;
940 }
941 }
Andrew Lunn436fe172018-03-01 02:02:29 +0100942
943 return j;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100944}
945
Andrew Lunn436fe172018-03-01 02:02:29 +0100946static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
947 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100948{
Andrew Lunn436fe172018-03-01 02:02:29 +0100949 return mv88e6xxx_stats_get_strings(chip, data,
950 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
Andrew Lunndfafe442016-11-21 23:27:02 +0100951}
952
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000953static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
954 uint8_t *data)
955{
956 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
957}
958
Andrew Lunn436fe172018-03-01 02:02:29 +0100959static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
960 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100961{
Andrew Lunn436fe172018-03-01 02:02:29 +0100962 return mv88e6xxx_stats_get_strings(chip, data,
963 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
Andrew Lunndfafe442016-11-21 23:27:02 +0100964}
965
Andrew Lunn65f60e42018-03-28 23:50:28 +0200966static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
967 "atu_member_violation",
968 "atu_miss_violation",
969 "atu_full_violation",
970 "vtu_member_violation",
971 "vtu_miss_violation",
972};
973
974static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
975{
976 unsigned int i;
977
978 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
979 strlcpy(data + i * ETH_GSTRING_LEN,
980 mv88e6xxx_atu_vtu_stats_strings[i],
981 ETH_GSTRING_LEN);
982}
983
Andrew Lunndfafe442016-11-21 23:27:02 +0100984static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
Florian Fainelli89f09042018-04-25 12:12:50 -0700985 u32 stringset, uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100986{
Vivien Didelot04bed142016-08-31 18:06:13 -0400987 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +0100988 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100989
Florian Fainelli89f09042018-04-25 12:12:50 -0700990 if (stringset != ETH_SS_STATS)
991 return;
992
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000993 mv88e6xxx_reg_lock(chip);
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100994
Andrew Lunndfafe442016-11-21 23:27:02 +0100995 if (chip->info->ops->stats_get_strings)
Andrew Lunn436fe172018-03-01 02:02:29 +0100996 count = chip->info->ops->stats_get_strings(chip, data);
997
998 if (chip->info->ops->serdes_get_strings) {
999 data += count * ETH_GSTRING_LEN;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001000 count = chip->info->ops->serdes_get_strings(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001001 }
Andrew Lunnc6c8cd52018-03-01 02:02:28 +01001002
Andrew Lunn65f60e42018-03-28 23:50:28 +02001003 data += count * ETH_GSTRING_LEN;
1004 mv88e6xxx_atu_vtu_get_strings(data);
1005
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001006 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001007}
1008
1009static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1010 int types)
1011{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +01001012 struct mv88e6xxx_hw_stat *stat;
1013 int i, j;
1014
1015 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1016 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +01001017 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +01001018 j++;
1019 }
1020 return j;
1021}
1022
Andrew Lunndfafe442016-11-21 23:27:02 +01001023static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1024{
1025 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1026 STATS_TYPE_PORT);
1027}
1028
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001029static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1030{
1031 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1032}
1033
Andrew Lunndfafe442016-11-21 23:27:02 +01001034static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1035{
1036 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1037 STATS_TYPE_BANK1);
1038}
1039
Florian Fainelli89f09042018-04-25 12:12:50 -07001040static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
Andrew Lunndfafe442016-11-21 23:27:02 +01001041{
1042 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +01001043 int serdes_count = 0;
1044 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +01001045
Florian Fainelli89f09042018-04-25 12:12:50 -07001046 if (sset != ETH_SS_STATS)
1047 return 0;
1048
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001049 mv88e6xxx_reg_lock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001050 if (chip->info->ops->stats_get_sset_count)
Andrew Lunn436fe172018-03-01 02:02:29 +01001051 count = chip->info->ops->stats_get_sset_count(chip);
1052 if (count < 0)
1053 goto out;
1054
1055 if (chip->info->ops->serdes_get_sset_count)
1056 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1057 port);
Andrew Lunn65f60e42018-03-28 23:50:28 +02001058 if (serdes_count < 0) {
Andrew Lunn436fe172018-03-01 02:02:29 +01001059 count = serdes_count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001060 goto out;
1061 }
1062 count += serdes_count;
1063 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1064
Andrew Lunn436fe172018-03-01 02:02:29 +01001065out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001066 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001067
Andrew Lunn436fe172018-03-01 02:02:29 +01001068 return count;
Andrew Lunndfafe442016-11-21 23:27:02 +01001069}
1070
Andrew Lunn436fe172018-03-01 02:02:29 +01001071static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1072 uint64_t *data, int types,
1073 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +01001074{
1075 struct mv88e6xxx_hw_stat *stat;
1076 int i, j;
1077
1078 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1079 stat = &mv88e6xxx_hw_stats[i];
1080 if (stat->type & types) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001081 mv88e6xxx_reg_lock(chip);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001082 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1083 bank1_select,
1084 histogram);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001085 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001086
Andrew Lunn052f9472016-11-21 23:27:03 +01001087 j++;
1088 }
1089 }
Andrew Lunn436fe172018-03-01 02:02:29 +01001090 return j;
Andrew Lunn052f9472016-11-21 23:27:03 +01001091}
1092
Andrew Lunn436fe172018-03-01 02:02:29 +01001093static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1094 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001095{
1096 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001097 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001098 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +01001099}
1100
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001101static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1102 uint64_t *data)
1103{
1104 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1105 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1106}
1107
Andrew Lunn436fe172018-03-01 02:02:29 +01001108static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1109 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001110{
1111 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001112 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001113 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1114 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001115}
1116
Andrew Lunn436fe172018-03-01 02:02:29 +01001117static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1118 uint64_t *data)
Andrew Lunne0d8b612016-11-21 23:27:04 +01001119{
1120 return mv88e6xxx_stats_get_stats(chip, port, data,
1121 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001122 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1123 0);
Andrew Lunn052f9472016-11-21 23:27:03 +01001124}
1125
Andrew Lunn65f60e42018-03-28 23:50:28 +02001126static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1127 uint64_t *data)
1128{
1129 *data++ = chip->ports[port].atu_member_violation;
1130 *data++ = chip->ports[port].atu_miss_violation;
1131 *data++ = chip->ports[port].atu_full_violation;
1132 *data++ = chip->ports[port].vtu_member_violation;
1133 *data++ = chip->ports[port].vtu_miss_violation;
1134}
1135
Andrew Lunn052f9472016-11-21 23:27:03 +01001136static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1137 uint64_t *data)
1138{
Andrew Lunn436fe172018-03-01 02:02:29 +01001139 int count = 0;
1140
Andrew Lunn052f9472016-11-21 23:27:03 +01001141 if (chip->info->ops->stats_get_stats)
Andrew Lunn436fe172018-03-01 02:02:29 +01001142 count = chip->info->ops->stats_get_stats(chip, port, data);
1143
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001144 mv88e6xxx_reg_lock(chip);
Andrew Lunn436fe172018-03-01 02:02:29 +01001145 if (chip->info->ops->serdes_get_stats) {
1146 data += count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001147 count = chip->info->ops->serdes_get_stats(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001148 }
Andrew Lunn65f60e42018-03-28 23:50:28 +02001149 data += count;
1150 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001151 mv88e6xxx_reg_unlock(chip);
Andrew Lunn052f9472016-11-21 23:27:03 +01001152}
1153
Vivien Didelotf81ec902016-05-09 13:22:58 -04001154static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1155 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001156{
Vivien Didelot04bed142016-08-31 18:06:13 -04001157 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001158 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001159
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001160 mv88e6xxx_reg_lock(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001161
Andrew Lunna605a0f2016-11-21 23:26:58 +01001162 ret = mv88e6xxx_stats_snapshot(chip, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001163 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001164
1165 if (ret < 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001166 return;
Andrew Lunn052f9472016-11-21 23:27:03 +01001167
1168 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001169
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001170}
Ben Hutchings98e67302011-11-25 14:36:19 +00001171
Vivien Didelotf81ec902016-05-09 13:22:58 -04001172static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001173{
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001174 struct mv88e6xxx_chip *chip = ds->priv;
1175 int len;
1176
1177 len = 32 * sizeof(u16);
1178 if (chip->info->ops->serdes_get_regs_len)
1179 len += chip->info->ops->serdes_get_regs_len(chip, port);
1180
1181 return len;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001182}
1183
Vivien Didelotf81ec902016-05-09 13:22:58 -04001184static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1185 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001186{
Vivien Didelot04bed142016-08-31 18:06:13 -04001187 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001188 int err;
1189 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001190 u16 *p = _p;
1191 int i;
1192
Vivien Didelota5f39322018-12-17 16:05:21 -05001193 regs->version = chip->info->prod_num;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001194
1195 memset(p, 0xff, 32 * sizeof(u16));
1196
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001197 mv88e6xxx_reg_lock(chip);
Vivien Didelot23062512016-05-09 13:22:45 -04001198
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001199 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001200
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001201 err = mv88e6xxx_port_read(chip, port, i, &reg);
1202 if (!err)
1203 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001204 }
Vivien Didelot23062512016-05-09 13:22:45 -04001205
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001206 if (chip->info->ops->serdes_get_regs)
1207 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1208
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001209 mv88e6xxx_reg_unlock(chip);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001210}
1211
Vivien Didelot08f50062017-08-01 16:32:41 -04001212static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1213 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001214{
Vivien Didelot5480db62017-08-01 16:32:40 -04001215 /* Nothing to do on the port's MAC */
1216 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001217}
1218
Vivien Didelot08f50062017-08-01 16:32:41 -04001219static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1220 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001221{
Vivien Didelot5480db62017-08-01 16:32:40 -04001222 /* Nothing to do on the port's MAC */
1223 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001224}
1225
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001226/* Mask of the local ports allowed to receive frames from a given fabric port */
Vivien Didelote5887a22017-03-30 17:37:11 -04001227static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001228{
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001229 struct dsa_switch *ds = chip->ds;
1230 struct dsa_switch_tree *dst = ds->dst;
Vladimir Oltean65144062021-12-06 18:57:51 +02001231 struct dsa_port *dp, *other_dp;
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001232 bool found = false;
Vivien Didelote5887a22017-03-30 17:37:11 -04001233 u16 pvlan;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001234
Vladimir Olteance5df682021-07-22 18:55:41 +03001235 /* dev is a physical switch */
1236 if (dev <= dst->last_switch) {
1237 list_for_each_entry(dp, &dst->ports, list) {
1238 if (dp->ds->index == dev && dp->index == port) {
1239 /* dp might be a DSA link or a user port, so it
Vladimir Oltean65144062021-12-06 18:57:51 +02001240 * might or might not have a bridge.
1241 * Use the "found" variable for both cases.
Vladimir Olteance5df682021-07-22 18:55:41 +03001242 */
Vladimir Olteance5df682021-07-22 18:55:41 +03001243 found = true;
1244 break;
1245 }
1246 }
1247 /* dev is a virtual bridge */
1248 } else {
1249 list_for_each_entry(dp, &dst->ports, list) {
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001250 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1251
1252 if (!bridge_num)
Vladimir Olteance5df682021-07-22 18:55:41 +03001253 continue;
1254
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001255 if (bridge_num + dst->last_switch != dev)
Vladimir Olteance5df682021-07-22 18:55:41 +03001256 continue;
1257
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001258 found = true;
1259 break;
1260 }
1261 }
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001262
Vladimir Olteance5df682021-07-22 18:55:41 +03001263 /* Prevent frames from unknown switch or virtual bridge */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001264 if (!found)
Vivien Didelote5887a22017-03-30 17:37:11 -04001265 return 0;
1266
1267 /* Frames from DSA links and CPU ports can egress any local port */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001268 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
Vivien Didelote5887a22017-03-30 17:37:11 -04001269 return mv88e6xxx_port_mask(chip);
1270
Vivien Didelote5887a22017-03-30 17:37:11 -04001271 pvlan = 0;
1272
1273 /* Frames from user ports can egress any local DSA links and CPU ports,
1274 * as well as any local member of their bridge group.
1275 */
Vladimir Oltean65144062021-12-06 18:57:51 +02001276 dsa_switch_for_each_port(other_dp, ds)
1277 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1278 other_dp->type == DSA_PORT_TYPE_DSA ||
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001279 dsa_port_bridge_same(dp, other_dp))
Vladimir Oltean65144062021-12-06 18:57:51 +02001280 pvlan |= BIT(other_dp->index);
Vivien Didelote5887a22017-03-30 17:37:11 -04001281
1282 return pvlan;
1283}
1284
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001285static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
Vivien Didelote5887a22017-03-30 17:37:11 -04001286{
1287 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001288
1289 /* prevent frames from going back out of the port they came in on */
1290 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001291
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001292 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001293}
1294
Vivien Didelotf81ec902016-05-09 13:22:58 -04001295static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1296 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001297{
Vivien Didelot04bed142016-08-31 18:06:13 -04001298 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot553eb542016-05-13 20:38:23 -04001299 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001300
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001301 mv88e6xxx_reg_lock(chip);
Vivien Didelotf894c292017-06-08 18:34:10 -04001302 err = mv88e6xxx_port_set_state(chip, port, state);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001303 mv88e6xxx_reg_unlock(chip);
Vivien Didelot553eb542016-05-13 20:38:23 -04001304
1305 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001306 dev_err(ds->dev, "p%d: failed to update state\n", port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001307}
1308
Vivien Didelot93e18d62018-05-11 17:16:35 -04001309static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1310{
1311 int err;
1312
1313 if (chip->info->ops->ieee_pri_map) {
1314 err = chip->info->ops->ieee_pri_map(chip);
1315 if (err)
1316 return err;
1317 }
1318
1319 if (chip->info->ops->ip_pri_map) {
1320 err = chip->info->ops->ip_pri_map(chip);
1321 if (err)
1322 return err;
1323 }
1324
1325 return 0;
1326}
1327
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001328static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1329{
Vivien Didelotc5f51762019-10-30 22:09:13 -04001330 struct dsa_switch *ds = chip->ds;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001331 int target, port;
1332 int err;
1333
1334 if (!chip->info->global2_addr)
1335 return 0;
1336
1337 /* Initialize the routing port to the 32 possible target devices */
1338 for (target = 0; target < 32; target++) {
Vivien Didelotc5f51762019-10-30 22:09:13 -04001339 port = dsa_routing_port(ds, target);
1340 if (port == ds->num_ports)
1341 port = 0x1f;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001342
1343 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1344 if (err)
1345 return err;
1346 }
1347
Vivien Didelot02317e62018-05-09 11:38:49 -04001348 if (chip->info->ops->set_cascade_port) {
1349 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1350 err = chip->info->ops->set_cascade_port(chip, port);
1351 if (err)
1352 return err;
1353 }
1354
Vivien Didelot23c98912018-05-09 11:38:50 -04001355 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1356 if (err)
1357 return err;
1358
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001359 return 0;
1360}
1361
Vivien Didelotb28f8722018-04-26 21:56:44 -04001362static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1363{
1364 /* Clear all trunk masks and mapping */
1365 if (chip->info->global2_addr)
1366 return mv88e6xxx_g2_trunk_clear(chip);
1367
1368 return 0;
1369}
1370
Vivien Didelot9e5baf92018-05-09 11:38:51 -04001371static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1372{
1373 if (chip->info->ops->rmu_disable)
1374 return chip->info->ops->rmu_disable(chip);
1375
1376 return 0;
1377}
1378
Vivien Didelot9e907d72017-07-17 13:03:43 -04001379static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1380{
1381 if (chip->info->ops->pot_clear)
1382 return chip->info->ops->pot_clear(chip);
1383
1384 return 0;
1385}
1386
Vivien Didelot51c901a2017-07-17 13:03:41 -04001387static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1388{
1389 if (chip->info->ops->mgmt_rsvd2cpu)
1390 return chip->info->ops->mgmt_rsvd2cpu(chip);
1391
1392 return 0;
1393}
1394
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001395static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1396{
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001397 int err;
1398
Vivien Didelotdaefc942017-03-11 16:12:54 -05001399 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1400 if (err)
1401 return err;
1402
Rasmus Villemoes49506a92020-12-10 12:06:44 +01001403 /* The chips that have a "learn2all" bit in Global1, ATU
1404 * Control are precisely those whose port registers have a
1405 * Message Port bit in Port Control 1 and hence implement
1406 * ->port_setup_message_port.
1407 */
1408 if (chip->info->ops->port_setup_message_port) {
1409 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1410 if (err)
1411 return err;
1412 }
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001413
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001414 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1415}
1416
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04001417static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1418{
1419 int port;
1420 int err;
1421
1422 if (!chip->info->ops->irl_init_all)
1423 return 0;
1424
1425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1426 /* Disable ingress rate limiting by resetting all per port
1427 * ingress rate limit resources to their initial state.
1428 */
1429 err = chip->info->ops->irl_init_all(chip, port);
1430 if (err)
1431 return err;
1432 }
1433
1434 return 0;
1435}
1436
Vivien Didelot04a69a12017-10-13 14:18:05 -04001437static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1438{
1439 if (chip->info->ops->set_switch_mac) {
1440 u8 addr[ETH_ALEN];
1441
1442 eth_random_addr(addr);
1443
1444 return chip->info->ops->set_switch_mac(chip, addr);
1445 }
1446
1447 return 0;
1448}
1449
Vivien Didelot17a15942017-03-30 17:37:09 -04001450static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1451{
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001452 struct dsa_switch_tree *dst = chip->ds->dst;
1453 struct dsa_switch *ds;
1454 struct dsa_port *dp;
Vivien Didelot17a15942017-03-30 17:37:09 -04001455 u16 pvlan = 0;
1456
1457 if (!mv88e6xxx_has_pvt(chip))
Vivien Didelotd14939b2019-10-21 16:51:25 -04001458 return 0;
Vivien Didelot17a15942017-03-30 17:37:09 -04001459
1460 /* Skip the local source device, which uses in-chip port VLAN */
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001461 if (dev != chip->ds->index) {
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001462 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
Vivien Didelot17a15942017-03-30 17:37:09 -04001463
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001464 ds = dsa_switch_find(dst->index, dev);
1465 dp = ds ? dsa_to_port(ds, port) : NULL;
1466 if (dp && dp->lag_dev) {
1467 /* As the PVT is used to limit flooding of
1468 * FORWARD frames, which use the LAG ID as the
1469 * source port, we must translate dev/port to
1470 * the special "LAG device" in the PVT, using
1471 * the LAG ID as the port number.
1472 */
Tobias Waldekranz78e70db2021-04-21 14:04:52 +02001473 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001474 port = dsa_lag_id(dst, dp->lag_dev);
1475 }
1476 }
1477
Vivien Didelot17a15942017-03-30 17:37:09 -04001478 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1479}
1480
Vivien Didelot81228992017-03-30 17:37:08 -04001481static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1482{
Vivien Didelot17a15942017-03-30 17:37:09 -04001483 int dev, port;
1484 int err;
1485
Vivien Didelot81228992017-03-30 17:37:08 -04001486 if (!mv88e6xxx_has_pvt(chip))
1487 return 0;
1488
1489 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1490 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1491 */
Vivien Didelot17a15942017-03-30 17:37:09 -04001492 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1493 if (err)
1494 return err;
1495
1496 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1497 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1498 err = mv88e6xxx_pvt_map(chip, dev, port);
1499 if (err)
1500 return err;
1501 }
1502 }
1503
1504 return 0;
Vivien Didelot81228992017-03-30 17:37:08 -04001505}
1506
Vivien Didelot749efcb2016-09-22 16:49:24 -04001507static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1508{
1509 struct mv88e6xxx_chip *chip = ds->priv;
1510 int err;
1511
Tobias Waldekranzffcec3f2021-03-18 20:25:34 +01001512 if (dsa_to_port(ds, port)->lag_dev)
1513 /* Hardware is incapable of fast-aging a LAG through a
1514 * regular ATU move operation. Until we have something
1515 * more fancy in place this is a no-op.
1516 */
1517 return;
1518
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001519 mv88e6xxx_reg_lock(chip);
Vivien Didelote606ca32017-03-11 16:12:55 -05001520 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001521 mv88e6xxx_reg_unlock(chip);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001522
1523 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001524 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001525}
1526
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001527static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1528{
Tobias Waldekranze545f862020-11-10 19:57:20 +01001529 if (!mv88e6xxx_max_vid(chip))
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001530 return 0;
1531
1532 return mv88e6xxx_g1_vtu_flush(chip);
1533}
1534
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001535static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1536 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelotf1394b782017-05-01 14:05:22 -04001537{
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001538 int err;
1539
Vivien Didelotf1394b782017-05-01 14:05:22 -04001540 if (!chip->info->ops->vtu_getnext)
1541 return -EOPNOTSUPP;
1542
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001543 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1544 entry->valid = false;
1545
1546 err = chip->info->ops->vtu_getnext(chip, entry);
1547
1548 if (entry->vid != vid)
1549 entry->valid = false;
1550
1551 return err;
Vivien Didelotf1394b782017-05-01 14:05:22 -04001552}
1553
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001554static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1555 int (*cb)(struct mv88e6xxx_chip *chip,
1556 const struct mv88e6xxx_vtu_entry *entry,
1557 void *priv),
1558 void *priv)
1559{
1560 struct mv88e6xxx_vtu_entry entry = {
1561 .vid = mv88e6xxx_max_vid(chip),
1562 .valid = false,
1563 };
1564 int err;
1565
1566 if (!chip->info->ops->vtu_getnext)
1567 return -EOPNOTSUPP;
1568
1569 do {
1570 err = chip->info->ops->vtu_getnext(chip, &entry);
1571 if (err)
1572 return err;
1573
1574 if (!entry.valid)
1575 break;
1576
1577 err = cb(chip, &entry, priv);
1578 if (err)
1579 return err;
1580 } while (entry.vid < mv88e6xxx_max_vid(chip));
1581
1582 return 0;
1583}
1584
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04001585static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1586 struct mv88e6xxx_vtu_entry *entry)
1587{
1588 if (!chip->info->ops->vtu_loadpurge)
1589 return -EOPNOTSUPP;
1590
1591 return chip->info->ops->vtu_loadpurge(chip, entry);
1592}
1593
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001594static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1595 const struct mv88e6xxx_vtu_entry *entry,
1596 void *_fid_bitmap)
1597{
1598 unsigned long *fid_bitmap = _fid_bitmap;
1599
1600 set_bit(entry->fid, fid_bitmap);
1601 return 0;
1602}
1603
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001604int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001605{
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001606 int i, err;
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001607 u16 fid;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001608
1609 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1610
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001611 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001612 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001613 err = mv88e6xxx_port_get_fid(chip, i, &fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001614 if (err)
1615 return err;
1616
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001617 set_bit(fid, fid_bitmap);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001618 }
1619
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001620 /* Set every FID bit used by the VLAN entries */
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001621 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001622}
1623
1624static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1625{
1626 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1627 int err;
1628
1629 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1630 if (err)
1631 return err;
1632
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001633 /* The reset value 0x000 is used to indicate that multiple address
1634 * databases are not needed. Return the next positive available.
1635 */
1636 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001637 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001638 return -ENOSPC;
1639
1640 /* Clear the database */
Vivien Didelotdaefc942017-03-11 16:12:54 -05001641 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001642}
1643
Vivien Didelotda9c3592016-02-12 12:09:40 -05001644static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001645 u16 vid)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001646{
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001647 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
Vivien Didelot04bed142016-08-31 18:06:13 -04001648 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot425d2d32019-08-01 14:36:34 -04001649 struct mv88e6xxx_vtu_entry vlan;
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001650 int err;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001651
Andrew Lunndb06ae412017-09-25 23:32:20 +02001652 /* DSA and CPU ports have to be members of multiple vlans */
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001653 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
Andrew Lunndb06ae412017-09-25 23:32:20 +02001654 return 0;
1655
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001656 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001657 if (err)
1658 return err;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001659
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001660 if (!vlan.valid)
1661 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001662
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001663 dsa_switch_for_each_user_port(other_dp, ds) {
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001664 struct net_device *other_br;
1665
Vladimir Oltean0493fa72021-12-06 18:57:50 +02001666 if (vlan.member[other_dp->index] ==
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001667 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1668 continue;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001669
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001670 if (dsa_port_bridge_same(dp, other_dp))
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001671 break; /* same bridge, check next VLAN */
Vivien Didelotda9c3592016-02-12 12:09:40 -05001672
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001673 other_br = dsa_port_bridge_dev_get(other_dp);
1674 if (!other_br)
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001675 continue;
Andrew Lunn66e28092016-12-11 21:07:19 +01001676
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001677 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001678 port, vlan.vid, other_dp->index, netdev_name(other_br));
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001679 return -EOPNOTSUPP;
1680 }
Vivien Didelotda9c3592016-02-12 12:09:40 -05001681
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001682 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001683}
1684
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001685static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
1686{
1687 struct dsa_port *dp = dsa_to_port(chip->ds, port);
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001688 struct net_device *br = dsa_port_bridge_dev_get(dp);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001689 struct mv88e6xxx_port *p = &chip->ports[port];
Vladimir Oltean5bded822021-10-07 19:47:11 +03001690 u16 pvid = MV88E6XXX_VID_STANDALONE;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001691 bool drop_untagged = false;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001692 int err;
1693
Vladimir Oltean41fb0cf2021-12-06 18:57:53 +02001694 if (br) {
1695 if (br_vlan_enabled(br)) {
Vladimir Oltean5bded822021-10-07 19:47:11 +03001696 pvid = p->bridge_pvid.vid;
1697 drop_untagged = !p->bridge_pvid.valid;
1698 } else {
1699 pvid = MV88E6XXX_VID_BRIDGED;
1700 }
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001701 }
1702
1703 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
1704 if (err)
1705 return err;
1706
1707 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
1708}
1709
Vivien Didelotf81ec902016-05-09 13:22:58 -04001710static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
Vladimir Oltean89153ed2021-02-13 22:43:19 +02001711 bool vlan_filtering,
1712 struct netlink_ext_ack *extack)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001713{
Vivien Didelot04bed142016-08-31 18:06:13 -04001714 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot81c6edb2017-06-12 12:37:41 -04001715 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1716 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001717 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001718
Vladimir Olteanbae33f22021-01-09 02:01:50 +02001719 if (!mv88e6xxx_max_vid(chip))
1720 return -EOPNOTSUPP;
Vivien Didelot54d77b52016-05-09 13:22:47 -04001721
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001722 mv88e6xxx_reg_lock(chip);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001723
Vivien Didelot385a0992016-11-04 03:23:31 +01001724 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03001725 if (err)
1726 goto unlock;
1727
1728 err = mv88e6xxx_port_commit_pvid(chip, port);
1729 if (err)
1730 goto unlock;
1731
1732unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001733 mv88e6xxx_reg_unlock(chip);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001734
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001735 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001736}
1737
Vivien Didelot57d32312016-06-20 13:13:58 -04001738static int
1739mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001740 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001741{
Vivien Didelot04bed142016-08-31 18:06:13 -04001742 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001743 int err;
1744
Tobias Waldekranze545f862020-11-10 19:57:20 +01001745 if (!mv88e6xxx_max_vid(chip))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001746 return -EOPNOTSUPP;
1747
Vivien Didelotda9c3592016-02-12 12:09:40 -05001748 /* If the requested port doesn't belong to the same bridge as the VLAN
1749 * members, do not support it (yet) and fallback to software VLAN.
1750 */
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001751 mv88e6xxx_reg_lock(chip);
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001752 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001753 mv88e6xxx_reg_unlock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001754
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001755 return err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001756}
1757
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001758static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1759 const unsigned char *addr, u16 vid,
1760 u8 state)
1761{
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001762 struct mv88e6xxx_atu_entry entry;
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001763 struct mv88e6xxx_vtu_entry vlan;
1764 u16 fid;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001765 int err;
1766
Vladimir Oltean5bded822021-10-07 19:47:11 +03001767 /* Ports have two private address databases: one for when the port is
1768 * standalone and one for when the port is under a bridge and the
1769 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
1770 * address database to remain 100% empty, so we never load an ATU entry
1771 * into a standalone port's database. Therefore, translate the null
1772 * VLAN ID into the port's database used for VLAN-unaware bridging.
1773 */
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001774 if (vid == 0) {
Vladimir Oltean5bded822021-10-07 19:47:11 +03001775 fid = MV88E6XXX_FID_BRIDGED;
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001776 } else {
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001777 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001778 if (err)
1779 return err;
1780
1781 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001782 if (!vlan.valid)
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001783 return -EOPNOTSUPP;
1784
1785 fid = vlan.fid;
1786 }
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001787
Vivien Didelotd8291a92019-09-07 16:00:47 -04001788 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001789 ether_addr_copy(entry.mac, addr);
1790 eth_addr_dec(entry.mac);
1791
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001792 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001793 if (err)
1794 return err;
1795
1796 /* Initialize a fresh ATU entry if it isn't found */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001797 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001798 memset(&entry, 0, sizeof(entry));
1799 ether_addr_copy(entry.mac, addr);
1800 }
1801
1802 /* Purge the ATU entry only if no port is using it anymore */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001803 if (!state) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001804 entry.portvec &= ~BIT(port);
1805 if (!entry.portvec)
Vivien Didelotd8291a92019-09-07 16:00:47 -04001806 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001807 } else {
DENG Qingfangf72f2fb2021-01-30 21:43:34 +08001808 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1809 entry.portvec = BIT(port);
1810 else
1811 entry.portvec |= BIT(port);
1812
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001813 entry.state = state;
1814 }
1815
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001816 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001817}
1818
Vivien Didelotda7dc872019-09-07 16:00:49 -04001819static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1820 const struct mv88e6xxx_policy *policy)
1821{
1822 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1823 enum mv88e6xxx_policy_action action = policy->action;
1824 const u8 *addr = policy->addr;
1825 u16 vid = policy->vid;
1826 u8 state;
1827 int err;
1828 int id;
1829
1830 if (!chip->info->ops->port_set_policy)
1831 return -EOPNOTSUPP;
1832
1833 switch (mapping) {
1834 case MV88E6XXX_POLICY_MAPPING_DA:
1835 case MV88E6XXX_POLICY_MAPPING_SA:
1836 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1837 state = 0; /* Dissociate the port and address */
1838 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1839 is_multicast_ether_addr(addr))
1840 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1841 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1842 is_unicast_ether_addr(addr))
1843 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1844 else
1845 return -EOPNOTSUPP;
1846
1847 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1848 state);
1849 if (err)
1850 return err;
1851 break;
1852 default:
1853 return -EOPNOTSUPP;
1854 }
1855
1856 /* Skip the port's policy clearing if the mapping is still in use */
1857 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1858 idr_for_each_entry(&chip->policies, policy, id)
1859 if (policy->port == port &&
1860 policy->mapping == mapping &&
1861 policy->action != action)
1862 return 0;
1863
1864 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1865}
1866
1867static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1868 struct ethtool_rx_flow_spec *fs)
1869{
1870 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1871 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1872 enum mv88e6xxx_policy_mapping mapping;
1873 enum mv88e6xxx_policy_action action;
1874 struct mv88e6xxx_policy *policy;
1875 u16 vid = 0;
1876 u8 *addr;
1877 int err;
1878 int id;
1879
1880 if (fs->location != RX_CLS_LOC_ANY)
1881 return -EINVAL;
1882
1883 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1884 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1885 else
1886 return -EOPNOTSUPP;
1887
1888 switch (fs->flow_type & ~FLOW_EXT) {
1889 case ETHER_FLOW:
1890 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1891 is_zero_ether_addr(mac_mask->h_source)) {
1892 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1893 addr = mac_entry->h_dest;
1894 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1895 !is_zero_ether_addr(mac_mask->h_source)) {
1896 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1897 addr = mac_entry->h_source;
1898 } else {
1899 /* Cannot support DA and SA mapping in the same rule */
1900 return -EOPNOTSUPP;
1901 }
1902 break;
1903 default:
1904 return -EOPNOTSUPP;
1905 }
1906
1907 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
Andrew Lunn04844282020-07-05 21:38:08 +02001908 if (fs->m_ext.vlan_tci != htons(0xffff))
Vivien Didelotda7dc872019-09-07 16:00:49 -04001909 return -EOPNOTSUPP;
1910 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1911 }
1912
1913 idr_for_each_entry(&chip->policies, policy, id) {
1914 if (policy->port == port && policy->mapping == mapping &&
1915 policy->action == action && policy->vid == vid &&
1916 ether_addr_equal(policy->addr, addr))
1917 return -EEXIST;
1918 }
1919
1920 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1921 if (!policy)
1922 return -ENOMEM;
1923
1924 fs->location = 0;
1925 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1926 GFP_KERNEL);
1927 if (err) {
1928 devm_kfree(chip->dev, policy);
1929 return err;
1930 }
1931
1932 memcpy(&policy->fs, fs, sizeof(*fs));
1933 ether_addr_copy(policy->addr, addr);
1934 policy->mapping = mapping;
1935 policy->action = action;
1936 policy->port = port;
1937 policy->vid = vid;
1938
1939 err = mv88e6xxx_policy_apply(chip, port, policy);
1940 if (err) {
1941 idr_remove(&chip->policies, fs->location);
1942 devm_kfree(chip->dev, policy);
1943 return err;
1944 }
1945
1946 return 0;
1947}
1948
1949static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1950 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1951{
1952 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1953 struct mv88e6xxx_chip *chip = ds->priv;
1954 struct mv88e6xxx_policy *policy;
1955 int err;
1956 int id;
1957
1958 mv88e6xxx_reg_lock(chip);
1959
1960 switch (rxnfc->cmd) {
1961 case ETHTOOL_GRXCLSRLCNT:
1962 rxnfc->data = 0;
1963 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1964 rxnfc->rule_cnt = 0;
1965 idr_for_each_entry(&chip->policies, policy, id)
1966 if (policy->port == port)
1967 rxnfc->rule_cnt++;
1968 err = 0;
1969 break;
1970 case ETHTOOL_GRXCLSRULE:
1971 err = -ENOENT;
1972 policy = idr_find(&chip->policies, fs->location);
1973 if (policy) {
1974 memcpy(fs, &policy->fs, sizeof(*fs));
1975 err = 0;
1976 }
1977 break;
1978 case ETHTOOL_GRXCLSRLALL:
1979 rxnfc->data = 0;
1980 rxnfc->rule_cnt = 0;
1981 idr_for_each_entry(&chip->policies, policy, id)
1982 if (policy->port == port)
1983 rule_locs[rxnfc->rule_cnt++] = id;
1984 err = 0;
1985 break;
1986 default:
1987 err = -EOPNOTSUPP;
1988 break;
1989 }
1990
1991 mv88e6xxx_reg_unlock(chip);
1992
1993 return err;
1994}
1995
1996static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1997 struct ethtool_rxnfc *rxnfc)
1998{
1999 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2000 struct mv88e6xxx_chip *chip = ds->priv;
2001 struct mv88e6xxx_policy *policy;
2002 int err;
2003
2004 mv88e6xxx_reg_lock(chip);
2005
2006 switch (rxnfc->cmd) {
2007 case ETHTOOL_SRXCLSRLINS:
2008 err = mv88e6xxx_policy_insert(chip, port, fs);
2009 break;
2010 case ETHTOOL_SRXCLSRLDEL:
2011 err = -ENOENT;
2012 policy = idr_remove(&chip->policies, fs->location);
2013 if (policy) {
2014 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2015 err = mv88e6xxx_policy_apply(chip, port, policy);
2016 devm_kfree(chip->dev, policy);
2017 }
2018 break;
2019 default:
2020 err = -EOPNOTSUPP;
2021 break;
2022 }
2023
2024 mv88e6xxx_reg_unlock(chip);
2025
2026 return err;
2027}
2028
Andrew Lunn87fa8862017-11-09 22:29:56 +01002029static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2030 u16 vid)
2031{
Andrew Lunn87fa8862017-11-09 22:29:56 +01002032 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
Tobias Waldekranz0806dd462021-03-18 20:25:37 +01002033 u8 broadcast[ETH_ALEN];
2034
2035 eth_broadcast_addr(broadcast);
Andrew Lunn87fa8862017-11-09 22:29:56 +01002036
2037 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2038}
2039
2040static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2041{
2042 int port;
2043 int err;
2044
2045 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01002046 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2047 struct net_device *brport;
2048
2049 if (dsa_is_unused_port(chip->ds, port))
2050 continue;
2051
2052 brport = dsa_port_to_bridge_port(dp);
2053 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2054 /* Skip bridged user ports where broadcast
2055 * flooding is disabled.
2056 */
2057 continue;
2058
Andrew Lunn87fa8862017-11-09 22:29:56 +01002059 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2060 if (err)
2061 return err;
2062 }
2063
2064 return 0;
2065}
2066
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01002067struct mv88e6xxx_port_broadcast_sync_ctx {
2068 int port;
2069 bool flood;
2070};
2071
2072static int
2073mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2074 const struct mv88e6xxx_vtu_entry *vlan,
2075 void *_ctx)
2076{
2077 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2078 u8 broadcast[ETH_ALEN];
2079 u8 state;
2080
2081 if (ctx->flood)
2082 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2083 else
2084 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2085
2086 eth_broadcast_addr(broadcast);
2087
2088 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2089 vlan->vid, state);
2090}
2091
2092static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2093 bool flood)
2094{
2095 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2096 .port = port,
2097 .flood = flood,
2098 };
2099 struct mv88e6xxx_vtu_entry vid0 = {
2100 .vid = 0,
2101 };
2102 int err;
2103
2104 /* Update the port's private database... */
2105 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2106 if (err)
2107 return err;
2108
2109 /* ...and the database for all VLANs. */
2110 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2111 &ctx);
2112}
2113
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002114static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
Russell King933b4422020-02-26 17:14:26 +00002115 u16 vid, u8 member, bool warn)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002116{
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002117 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002118 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002119 int i, err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002120
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002121 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002122 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002123 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002124
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002125 if (!vlan.valid) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002126 memset(&vlan, 0, sizeof(vlan));
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002127
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002128 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2129 if (err)
2130 return err;
Andrew Lunn87fa8862017-11-09 22:29:56 +01002131
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002132 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2133 if (i == port)
2134 vlan.member[i] = member;
2135 else
2136 vlan.member[i] = non_member;
2137
2138 vlan.vid = vid;
2139 vlan.valid = true;
2140
2141 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2142 if (err)
2143 return err;
2144
2145 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2146 if (err)
2147 return err;
2148 } else if (vlan.member[port] != member) {
2149 vlan.member[port] = member;
2150
2151 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2152 if (err)
2153 return err;
Russell King933b4422020-02-26 17:14:26 +00002154 } else if (warn) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002155 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2156 port, vid);
2157 }
2158
2159 return 0;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002160}
2161
Vladimir Oltean1958d582021-01-09 02:01:53 +02002162static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
Vladimir Oltean31046a52021-02-13 22:43:18 +02002163 const struct switchdev_obj_port_vlan *vlan,
2164 struct netlink_ext_ack *extack)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002165{
Vivien Didelot04bed142016-08-31 18:06:13 -04002166 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002167 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2168 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002169 struct mv88e6xxx_port *p = &chip->ports[port];
Russell King933b4422020-02-26 17:14:26 +00002170 bool warn;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002171 u8 member;
Vladimir Oltean1958d582021-01-09 02:01:53 +02002172 int err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002173
Eldar Gasanovb8b79c42021-06-21 11:54:38 +03002174 if (!vlan->vid)
2175 return 0;
2176
Vladimir Oltean1958d582021-01-09 02:01:53 +02002177 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2178 if (err)
2179 return err;
Vivien Didelot54d77b52016-05-09 13:22:47 -04002180
Vivien Didelotc91498e2017-06-07 18:12:13 -04002181 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002182 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002183 else if (untagged)
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002184 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002185 else
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002186 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002187
Russell King933b4422020-02-26 17:14:26 +00002188 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2189 * and then the CPU port. Do not warn for duplicates for the CPU port.
2190 */
2191 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2192
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002193 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002194
Vladimir Oltean1958d582021-01-09 02:01:53 +02002195 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2196 if (err) {
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002197 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2198 vlan->vid, untagged ? 'u' : 't');
Vladimir Oltean1958d582021-01-09 02:01:53 +02002199 goto out;
2200 }
Vivien Didelot76e398a2015-11-01 12:33:55 -05002201
Vladimir Oltean1958d582021-01-09 02:01:53 +02002202 if (pvid) {
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002203 p->bridge_pvid.vid = vlan->vid;
2204 p->bridge_pvid.valid = true;
2205
2206 err = mv88e6xxx_port_commit_pvid(chip, port);
2207 if (err)
Vladimir Oltean1958d582021-01-09 02:01:53 +02002208 goto out;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002209 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2210 /* The old pvid was reinstalled as a non-pvid VLAN */
2211 p->bridge_pvid.valid = false;
2212
2213 err = mv88e6xxx_port_commit_pvid(chip, port);
2214 if (err)
2215 goto out;
Vladimir Oltean1958d582021-01-09 02:01:53 +02002216 }
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002217
Vladimir Oltean1958d582021-01-09 02:01:53 +02002218out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002219 mv88e6xxx_reg_unlock(chip);
Vladimir Oltean1958d582021-01-09 02:01:53 +02002220
2221 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002222}
2223
Vivien Didelot521098922019-08-01 14:36:36 -04002224static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2225 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002226{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002227 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002228 int i, err;
2229
Vivien Didelot521098922019-08-01 14:36:36 -04002230 if (!vid)
Vladimir Olteanc92c7412021-07-22 16:05:51 +03002231 return 0;
Vivien Didelot521098922019-08-01 14:36:36 -04002232
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002233 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002234 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002235 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002236
Vivien Didelot521098922019-08-01 14:36:36 -04002237 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2238 * tell switchdev that this VLAN is likely handled in software.
2239 */
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002240 if (!vlan.valid ||
Vivien Didelot521098922019-08-01 14:36:36 -04002241 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05002242 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002243
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002244 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002245
2246 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002247 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002248 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002249 if (vlan.member[i] !=
2250 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002251 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002252 break;
2253 }
2254 }
2255
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002256 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002257 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002258 return err;
2259
Vivien Didelote606ca32017-03-11 16:12:55 -05002260 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002261}
2262
Vivien Didelotf81ec902016-05-09 13:22:58 -04002263static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2264 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002265{
Vivien Didelot04bed142016-08-31 18:06:13 -04002266 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002267 struct mv88e6xxx_port *p = &chip->ports[port];
Vivien Didelot76e398a2015-11-01 12:33:55 -05002268 int err = 0;
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002269 u16 pvid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002270
Tobias Waldekranze545f862020-11-10 19:57:20 +01002271 if (!mv88e6xxx_max_vid(chip))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002272 return -EOPNOTSUPP;
2273
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002274 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002275
Vivien Didelot77064f32016-11-04 03:23:30 +01002276 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002277 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002278 goto unlock;
2279
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002280 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2281 if (err)
2282 goto unlock;
2283
2284 if (vlan->vid == pvid) {
Vladimir Oltean8b6836d2021-10-07 19:47:10 +03002285 p->bridge_pvid.valid = false;
2286
2287 err = mv88e6xxx_port_commit_pvid(chip, port);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002288 if (err)
2289 goto unlock;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002290 }
2291
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002292unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002293 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002294
2295 return err;
2296}
2297
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002298static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2299 const unsigned char *addr, u16 vid)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002300{
Vivien Didelot04bed142016-08-31 18:06:13 -04002301 struct mv88e6xxx_chip *chip = ds->priv;
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002302 int err;
Vivien Didelot6630e232015-08-06 01:44:07 -04002303
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002304 mv88e6xxx_reg_lock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002305 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2306 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002307 mv88e6xxx_reg_unlock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002308
2309 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002310}
2311
Vivien Didelotf81ec902016-05-09 13:22:58 -04002312static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
Arkadi Sharshevsky6c2c1dc2017-08-06 16:15:39 +03002313 const unsigned char *addr, u16 vid)
David S. Millercdf09692015-08-11 12:00:37 -07002314{
Vivien Didelot04bed142016-08-31 18:06:13 -04002315 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002316 int err;
David S. Millercdf09692015-08-11 12:00:37 -07002317
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002318 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04002319 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002320 mv88e6xxx_reg_unlock(chip);
David S. Millercdf09692015-08-11 12:00:37 -07002321
Vivien Didelot83dabd12016-08-31 11:50:04 -04002322 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002323}
2324
Vivien Didelot83dabd12016-08-31 11:50:04 -04002325static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2326 u16 fid, u16 vid, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002327 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002328{
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002329 struct mv88e6xxx_atu_entry addr;
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002330 bool is_static;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002331 int err;
2332
Vivien Didelotd8291a92019-09-07 16:00:47 -04002333 addr.state = 0;
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002334 eth_broadcast_addr(addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002335
2336 do {
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002337 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002338 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002339 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002340
Vivien Didelotd8291a92019-09-07 16:00:47 -04002341 if (!addr.state)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002342 break;
2343
Vivien Didelot01bd96c2017-03-11 16:12:57 -05002344 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002345 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002346
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002347 if (!is_unicast_ether_addr(addr.mac))
2348 continue;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002349
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002350 is_static = (addr.state ==
2351 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2352 err = cb(addr.mac, vid, is_static, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002353 if (err)
2354 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002355 } while (!is_broadcast_ether_addr(addr.mac));
2356
2357 return err;
2358}
2359
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002360struct mv88e6xxx_port_db_dump_vlan_ctx {
2361 int port;
2362 dsa_fdb_dump_cb_t *cb;
2363 void *data;
2364};
2365
2366static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2367 const struct mv88e6xxx_vtu_entry *entry,
2368 void *_data)
2369{
2370 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2371
2372 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2373 ctx->port, ctx->cb, ctx->data);
2374}
2375
Vivien Didelot83dabd12016-08-31 11:50:04 -04002376static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002377 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002378{
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002379 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2380 .port = port,
2381 .cb = cb,
2382 .data = data,
2383 };
Vivien Didelot83dabd12016-08-31 11:50:04 -04002384 u16 fid;
2385 int err;
2386
2387 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002388 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002389 if (err)
2390 return err;
2391
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002392 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002393 if (err)
2394 return err;
2395
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002396 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002397}
2398
Vivien Didelotf81ec902016-05-09 13:22:58 -04002399static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002400 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelotf33475b2015-10-22 09:34:41 -04002401{
Vivien Didelot04bed142016-08-31 18:06:13 -04002402 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotfcf15362019-06-12 12:42:47 -04002403 int err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002404
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002405 mv88e6xxx_reg_lock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002406 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002407 mv88e6xxx_reg_unlock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002408
2409 return err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002410}
2411
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002412static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002413 struct dsa_bridge bridge)
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002414{
Vivien Didelotef2025e2019-10-21 16:51:27 -04002415 struct dsa_switch *ds = chip->ds;
2416 struct dsa_switch_tree *dst = ds->dst;
2417 struct dsa_port *dp;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002418 int err;
2419
Vivien Didelotef2025e2019-10-21 16:51:27 -04002420 list_for_each_entry(dp, &dst->ports, list) {
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002421 if (dsa_port_offloads_bridge(dp, &bridge)) {
Vivien Didelotef2025e2019-10-21 16:51:27 -04002422 if (dp->ds == ds) {
2423 /* This is a local bridge group member,
2424 * remap its Port VLAN Map.
2425 */
2426 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2427 if (err)
2428 return err;
2429 } else {
2430 /* This is an external bridge group member,
2431 * remap its cross-chip Port VLAN Table entry.
2432 */
2433 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2434 dp->index);
Vivien Didelote96a6e02017-03-30 17:37:13 -04002435 if (err)
2436 return err;
2437 }
2438 }
2439 }
2440
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002441 return 0;
2442}
2443
Vivien Didelotf81ec902016-05-09 13:22:58 -04002444static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vladimir Olteanb0799222021-12-06 18:57:57 +02002445 struct dsa_bridge bridge,
2446 bool *tx_fwd_offload)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002447{
Vivien Didelot04bed142016-08-31 18:06:13 -04002448 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002449 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002450
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002451 mv88e6xxx_reg_lock(chip);
Vladimir Oltean5bded822021-10-07 19:47:11 +03002452
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002453 err = mv88e6xxx_bridge_map(chip, bridge);
Vladimir Oltean5bded822021-10-07 19:47:11 +03002454 if (err)
2455 goto unlock;
2456
2457 err = mv88e6xxx_port_commit_pvid(chip, port);
2458 if (err)
2459 goto unlock;
2460
2461unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002462 mv88e6xxx_reg_unlock(chip);
Vivien Didelota6692752016-02-12 12:09:39 -05002463
Vivien Didelot466dfa02016-02-26 13:16:05 -05002464 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002465}
2466
Vivien Didelotf123f2f2017-01-27 15:29:41 -05002467static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002468 struct dsa_bridge bridge)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002469{
Vivien Didelot04bed142016-08-31 18:06:13 -04002470 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Oltean5bded822021-10-07 19:47:11 +03002471 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002472
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002473 mv88e6xxx_reg_lock(chip);
Vladimir Oltean5bded822021-10-07 19:47:11 +03002474
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002475 if (mv88e6xxx_bridge_map(chip, bridge) ||
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002476 mv88e6xxx_port_vlan_map(chip, port))
2477 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
Vladimir Oltean5bded822021-10-07 19:47:11 +03002478
2479 err = mv88e6xxx_port_commit_pvid(chip, port);
2480 if (err)
2481 dev_err(ds->dev,
2482 "port %d failed to restore standalone pvid: %pe\n",
2483 port, ERR_PTR(err));
2484
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002485 mv88e6xxx_reg_unlock(chip);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05002486}
2487
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002488static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2489 int tree_index, int sw_index,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002490 int port, struct dsa_bridge bridge)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002491{
2492 struct mv88e6xxx_chip *chip = ds->priv;
2493 int err;
2494
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002495 if (tree_index != ds->dst->index)
2496 return 0;
2497
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002498 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002499 err = mv88e6xxx_pvt_map(chip, sw_index, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002500 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002501
2502 return err;
2503}
2504
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002505static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2506 int tree_index, int sw_index,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002507 int port, struct dsa_bridge bridge)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002508{
2509 struct mv88e6xxx_chip *chip = ds->priv;
2510
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002511 if (tree_index != ds->dst->index)
2512 return;
2513
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002514 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002515 if (mv88e6xxx_pvt_map(chip, sw_index, port))
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002516 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002517 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002518}
2519
Vladimir Olteance5df682021-07-22 18:55:41 +03002520/* Treat the software bridge as a virtual single-port switch behind the
2521 * CPU and map in the PVT. First dst->last_switch elements are taken by
2522 * physical switches, so start from beyond that range.
2523 */
2524static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
Vladimir Oltean3f9bb032021-12-06 18:57:47 +02002525 unsigned int bridge_num)
Vladimir Olteance5df682021-07-22 18:55:41 +03002526{
Vladimir Oltean3f9bb032021-12-06 18:57:47 +02002527 u8 dev = bridge_num + ds->dst->last_switch;
Vladimir Olteance5df682021-07-22 18:55:41 +03002528 struct mv88e6xxx_chip *chip = ds->priv;
2529 int err;
2530
2531 mv88e6xxx_reg_lock(chip);
2532 err = mv88e6xxx_pvt_map(chip, dev, 0);
2533 mv88e6xxx_reg_unlock(chip);
2534
2535 return err;
2536}
2537
2538static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002539 struct dsa_bridge bridge)
Vladimir Olteance5df682021-07-22 18:55:41 +03002540{
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002541 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
Vladimir Olteance5df682021-07-22 18:55:41 +03002542}
2543
2544static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port,
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002545 struct dsa_bridge bridge)
Vladimir Olteance5df682021-07-22 18:55:41 +03002546{
2547 int err;
2548
Vladimir Olteand3eed0e2021-12-06 18:57:56 +02002549 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
Vladimir Olteance5df682021-07-22 18:55:41 +03002550 if (err) {
2551 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n",
2552 ERR_PTR(err));
2553 }
2554}
2555
Vivien Didelot17e708b2016-12-05 17:30:27 -05002556static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2557{
2558 if (chip->info->ops->reset)
2559 return chip->info->ops->reset(chip);
2560
2561 return 0;
2562}
2563
Vivien Didelot309eca62016-12-05 17:30:26 -05002564static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2565{
2566 struct gpio_desc *gpiod = chip->reset;
2567
2568 /* If there is a GPIO connected to the reset pin, toggle it */
2569 if (gpiod) {
2570 gpiod_set_value_cansleep(gpiod, 1);
2571 usleep_range(10000, 20000);
2572 gpiod_set_value_cansleep(gpiod, 0);
2573 usleep_range(10000, 20000);
Andrew Lunna3dcb3e2020-11-16 08:43:01 -08002574
2575 mv88e6xxx_g1_wait_eeprom_done(chip);
Vivien Didelot309eca62016-12-05 17:30:26 -05002576 }
2577}
2578
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002579static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2580{
2581 int i, err;
2582
2583 /* Set all ports to the Disabled state */
2584 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotf894c292017-06-08 18:34:10 -04002585 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002586 if (err)
2587 return err;
2588 }
2589
2590 /* Wait for transmit queues to drain,
2591 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2592 */
2593 usleep_range(2000, 4000);
2594
2595 return 0;
2596}
2597
Vivien Didelotfad09c72016-06-21 12:28:20 -04002598static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002599{
Vivien Didelota935c052016-09-29 12:21:53 -04002600 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002601
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002602 err = mv88e6xxx_disable_ports(chip);
2603 if (err)
2604 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002605
Vivien Didelot309eca62016-12-05 17:30:26 -05002606 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002607
Vivien Didelot17e708b2016-12-05 17:30:27 -05002608 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002609}
2610
Vivien Didelot43145572017-03-11 16:12:59 -05002611static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002612 enum mv88e6xxx_frame_mode frame,
2613 enum mv88e6xxx_egress_mode egress, u16 etype)
Andrew Lunn56995cb2016-12-03 04:35:19 +01002614{
2615 int err;
2616
Vivien Didelot43145572017-03-11 16:12:59 -05002617 if (!chip->info->ops->port_set_frame_mode)
2618 return -EOPNOTSUPP;
2619
2620 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002621 if (err)
2622 return err;
2623
Vivien Didelot43145572017-03-11 16:12:59 -05002624 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2625 if (err)
2626 return err;
2627
2628 if (chip->info->ops->port_set_ether_type)
2629 return chip->info->ops->port_set_ether_type(chip, port, etype);
2630
2631 return 0;
2632}
2633
2634static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2635{
2636 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002637 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002638 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002639}
2640
2641static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2642{
2643 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002644 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002645 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002646}
2647
2648static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2649{
2650 return mv88e6xxx_set_port_mode(chip, port,
2651 MV88E6XXX_FRAME_MODE_ETHERTYPE,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002652 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2653 ETH_P_EDSA);
Vivien Didelot43145572017-03-11 16:12:59 -05002654}
2655
2656static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2657{
2658 if (dsa_is_dsa_port(chip->ds, port))
2659 return mv88e6xxx_set_port_mode_dsa(chip, port);
2660
Vivien Didelot2b3e9892017-10-26 11:22:54 -04002661 if (dsa_is_user_port(chip->ds, port))
Vivien Didelot43145572017-03-11 16:12:59 -05002662 return mv88e6xxx_set_port_mode_normal(chip, port);
2663
2664 /* Setup CPU port mode depending on its supported tag format */
Tobias Waldekranz670bb802021-04-20 20:53:07 +02002665 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
Vivien Didelot43145572017-03-11 16:12:59 -05002666 return mv88e6xxx_set_port_mode_dsa(chip, port);
2667
Tobias Waldekranz670bb802021-04-20 20:53:07 +02002668 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
Vivien Didelot43145572017-03-11 16:12:59 -05002669 return mv88e6xxx_set_port_mode_edsa(chip, port);
2670
2671 return -EINVAL;
2672}
2673
Vivien Didelotea698f42017-03-11 16:12:50 -05002674static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2675{
2676 bool message = dsa_is_dsa_port(chip->ds, port);
2677
2678 return mv88e6xxx_port_set_message_port(chip, port, message);
2679}
2680
Vivien Didelot601aeed2017-03-11 16:13:00 -05002681static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2682{
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002683 int err;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002684
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002685 if (chip->info->ops->port_set_ucast_flood) {
Tobias Waldekranz7b9f16f2021-03-18 20:25:38 +01002686 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002687 if (err)
2688 return err;
2689 }
2690 if (chip->info->ops->port_set_mcast_flood) {
Tobias Waldekranz7b9f16f2021-03-18 20:25:38 +01002691 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002692 if (err)
2693 return err;
2694 }
Vivien Didelot601aeed2017-03-11 16:13:00 -05002695
David S. Miller407308f2019-06-15 13:35:29 -07002696 return 0;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002697}
2698
Vivien Didelot45de77f2019-08-31 16:18:36 -04002699static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2700{
2701 struct mv88e6xxx_port *mvp = dev_id;
2702 struct mv88e6xxx_chip *chip = mvp->chip;
2703 irqreturn_t ret = IRQ_NONE;
2704 int port = mvp->port;
Pavana Sharma193c5b22021-03-17 14:46:40 +01002705 int lane;
Vivien Didelot45de77f2019-08-31 16:18:36 -04002706
2707 mv88e6xxx_reg_lock(chip);
2708 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +01002709 if (lane >= 0)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002710 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2711 mv88e6xxx_reg_unlock(chip);
2712
2713 return ret;
2714}
2715
2716static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
Pavana Sharma193c5b22021-03-17 14:46:40 +01002717 int lane)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002718{
2719 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2720 unsigned int irq;
2721 int err;
2722
2723 /* Nothing to request if this SERDES port has no IRQ */
2724 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2725 if (!irq)
2726 return 0;
2727
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002728 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2729 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2730
Vivien Didelot45de77f2019-08-31 16:18:36 -04002731 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2732 mv88e6xxx_reg_unlock(chip);
2733 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002734 IRQF_ONESHOT, dev_id->serdes_irq_name,
2735 dev_id);
Vivien Didelot45de77f2019-08-31 16:18:36 -04002736 mv88e6xxx_reg_lock(chip);
2737 if (err)
2738 return err;
2739
2740 dev_id->serdes_irq = irq;
2741
2742 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2743}
2744
2745static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
Pavana Sharma193c5b22021-03-17 14:46:40 +01002746 int lane)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002747{
2748 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2749 unsigned int irq = dev_id->serdes_irq;
2750 int err;
2751
2752 /* Nothing to free if no IRQ has been requested */
2753 if (!irq)
2754 return 0;
2755
2756 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2757
2758 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2759 mv88e6xxx_reg_unlock(chip);
2760 free_irq(irq, dev_id);
2761 mv88e6xxx_reg_lock(chip);
2762
2763 dev_id->serdes_irq = 0;
2764
2765 return err;
2766}
2767
Andrew Lunn6d917822017-05-26 01:03:21 +02002768static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2769 bool on)
2770{
Pavana Sharma193c5b22021-03-17 14:46:40 +01002771 int lane;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002772 int err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002773
Vivien Didelotdc272f62019-08-31 16:18:33 -04002774 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +01002775 if (lane < 0)
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002776 return 0;
2777
2778 if (on) {
Vivien Didelotdc272f62019-08-31 16:18:33 -04002779 err = mv88e6xxx_serdes_power_up(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002780 if (err)
2781 return err;
2782
Vivien Didelot45de77f2019-08-31 16:18:36 -04002783 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002784 } else {
Vivien Didelot45de77f2019-08-31 16:18:36 -04002785 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2786 if (err)
2787 return err;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002788
Vivien Didelotdc272f62019-08-31 16:18:33 -04002789 err = mv88e6xxx_serdes_power_down(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002790 }
2791
2792 return err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002793}
2794
Marek Behún2fda45f2021-03-17 14:46:41 +01002795static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2796 enum mv88e6xxx_egress_direction direction,
2797 int port)
2798{
2799 int err;
2800
2801 if (!chip->info->ops->set_egress_port)
2802 return -EOPNOTSUPP;
2803
2804 err = chip->info->ops->set_egress_port(chip, direction, port);
2805 if (err)
2806 return err;
2807
2808 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2809 chip->ingress_dest_port = port;
2810 else
2811 chip->egress_dest_port = port;
2812
2813 return 0;
2814}
2815
Vivien Didelotfa371c82017-12-05 15:34:10 -05002816static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2817{
2818 struct dsa_switch *ds = chip->ds;
2819 int upstream_port;
2820 int err;
2821
Vivien Didelot07073c72017-12-05 15:34:13 -05002822 upstream_port = dsa_upstream_port(ds, port);
Vivien Didelotfa371c82017-12-05 15:34:10 -05002823 if (chip->info->ops->port_set_upstream_port) {
2824 err = chip->info->ops->port_set_upstream_port(chip, port,
2825 upstream_port);
2826 if (err)
2827 return err;
2828 }
2829
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002830 if (port == upstream_port) {
2831 if (chip->info->ops->set_cpu_port) {
2832 err = chip->info->ops->set_cpu_port(chip,
2833 upstream_port);
2834 if (err)
2835 return err;
2836 }
2837
Marek Behún2fda45f2021-03-17 14:46:41 +01002838 err = mv88e6xxx_set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002839 MV88E6XXX_EGRESS_DIR_INGRESS,
2840 upstream_port);
Marek Behún2fda45f2021-03-17 14:46:41 +01002841 if (err && err != -EOPNOTSUPP)
2842 return err;
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002843
Marek Behún2fda45f2021-03-17 14:46:41 +01002844 err = mv88e6xxx_set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002845 MV88E6XXX_EGRESS_DIR_EGRESS,
2846 upstream_port);
Marek Behún2fda45f2021-03-17 14:46:41 +01002847 if (err && err != -EOPNOTSUPP)
2848 return err;
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002849 }
2850
Vivien Didelotfa371c82017-12-05 15:34:10 -05002851 return 0;
2852}
2853
Vivien Didelotfad09c72016-06-21 12:28:20 -04002854static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002855{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002856 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002857 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002858 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002859
Andrew Lunn7b898462018-08-09 15:38:47 +02002860 chip->ports[port].chip = chip;
2861 chip->ports[port].port = port;
2862
Vivien Didelotd78343d2016-11-04 03:23:36 +01002863 /* MAC Forcing register: don't force link, speed, duplex or flow control
2864 * state to any particular values on physical ports, but force the CPU
2865 * port and all DSA ports to their maximum bandwidth and full duplex.
2866 */
2867 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2868 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2869 SPEED_MAX, DUPLEX_FULL,
Andrew Lunn54186b92018-08-09 15:38:37 +02002870 PAUSE_OFF,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002871 PHY_INTERFACE_MODE_NA);
2872 else
2873 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2874 SPEED_UNFORCED, DUPLEX_UNFORCED,
Andrew Lunn54186b92018-08-09 15:38:37 +02002875 PAUSE_ON,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002876 PHY_INTERFACE_MODE_NA);
2877 if (err)
2878 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002879
2880 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2881 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2882 * tunneling, determine priority by looking at 802.1p and IP
2883 * priority fields (IP prio has precedence), and set STP state
2884 * to Forwarding.
2885 *
2886 * If this is the CPU link, use DSA or EDSA tagging depending
2887 * on which tagging mode was configured.
2888 *
2889 * If this is a link to another switch, use DSA tagging mode.
2890 *
2891 * If this is the upstream port for this switch, enable
2892 * forwarding of unknown unicasts and multicasts.
2893 */
Vivien Didelota89b433be2017-06-12 12:37:37 -04002894 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2895 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2896 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2897 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002898 if (err)
2899 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002900
Vivien Didelot601aeed2017-03-11 16:13:00 -05002901 err = mv88e6xxx_setup_port_mode(chip, port);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002902 if (err)
2903 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002904
Vivien Didelot601aeed2017-03-11 16:13:00 -05002905 err = mv88e6xxx_setup_egress_floods(chip, port);
Vivien Didelot43145572017-03-11 16:12:59 -05002906 if (err)
2907 return err;
2908
Andrew Lunnb92ce2f2021-09-26 19:41:25 +02002909 /* Port Control 2: don't force a good FCS, set the MTU size to
2910 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002911 * untagged frames on this port, do a destination address lookup on all
2912 * received packets as usual, disable ARP mirroring and don't send a
2913 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002914 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002915 err = mv88e6xxx_port_set_map_da(chip, port);
2916 if (err)
2917 return err;
2918
Vivien Didelotfa371c82017-12-05 15:34:10 -05002919 err = mv88e6xxx_setup_upstream_port(chip, port);
2920 if (err)
2921 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002922
Andrew Lunna23b2962017-02-04 20:15:28 +01002923 err = mv88e6xxx_port_set_8021q_mode(chip, port,
Vivien Didelot81c6edb2017-06-12 12:37:41 -04002924 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
Andrew Lunna23b2962017-02-04 20:15:28 +01002925 if (err)
2926 return err;
2927
Vladimir Oltean5bded822021-10-07 19:47:11 +03002928 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
2929 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
2930 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
2931 * as the private PVID on ports under a VLAN-unaware bridge.
2932 * Shared (DSA and CPU) ports must also be members of it, to translate
2933 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
2934 * relying on their port default FID.
2935 */
2936 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
2937 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED,
2938 false);
2939 if (err)
2940 return err;
2941
Vivien Didelotcd782652017-06-08 18:34:13 -04002942 if (chip->info->ops->port_set_jumbo_size) {
Andrew Lunnb92ce2f2021-09-26 19:41:25 +02002943 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
Andrew Lunn5f436662016-12-03 04:45:17 +01002944 if (err)
2945 return err;
2946 }
2947
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002948 /* Port Association Vector: disable automatic address learning
2949 * on all user ports since they start out in standalone
2950 * mode. When joining a bridge, learning will be configured to
2951 * match the bridge port settings. Enable learning on all
2952 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2953 * learning process.
2954 *
2955 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2956 * and RefreshLocked. I.e. setup standard automatic learning.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002957 */
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002958 if (dsa_is_user_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002959 reg = 0;
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002960 else
2961 reg = 1 << port;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002962
Vivien Didelot2a4614e2017-06-12 12:37:43 -04002963 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2964 reg);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002965 if (err)
2966 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002967
2968 /* Egress rate control 2: disable egress rate control. */
Vivien Didelot2cb8cb12017-06-12 12:37:42 -04002969 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2970 0x0000);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002971 if (err)
2972 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002973
Vivien Didelot08984322017-06-08 18:34:12 -04002974 if (chip->info->ops->port_pause_limit) {
2975 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002976 if (err)
2977 return err;
2978 }
2979
Vivien Didelotc8c94892017-03-11 16:13:01 -05002980 if (chip->info->ops->port_disable_learn_limit) {
2981 err = chip->info->ops->port_disable_learn_limit(chip, port);
2982 if (err)
2983 return err;
2984 }
2985
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002986 if (chip->info->ops->port_disable_pri_override) {
2987 err = chip->info->ops->port_disable_pri_override(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002988 if (err)
2989 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002990 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002991
Andrew Lunnef0a7312016-12-03 04:35:16 +01002992 if (chip->info->ops->port_tag_remap) {
2993 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002994 if (err)
2995 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002996 }
2997
Andrew Lunnef70b112016-12-03 04:45:18 +01002998 if (chip->info->ops->port_egress_rate_limiting) {
2999 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02003000 if (err)
3001 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003002 }
3003
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003004 if (chip->info->ops->port_setup_message_port) {
3005 err = chip->info->ops->port_setup_message_port(chip, port);
3006 if (err)
3007 return err;
3008 }
Guenter Roeckd827e882015-03-26 18:36:29 -07003009
Vivien Didelot207afda2016-04-14 14:42:09 -04003010 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05003011 * database, and allow bidirectional communication between the
3012 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07003013 */
Vladimir Oltean5bded822021-10-07 19:47:11 +03003014 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02003015 if (err)
3016 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05003017
Vivien Didelot240ea3e2017-03-30 17:37:12 -04003018 err = mv88e6xxx_port_vlan_map(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02003019 if (err)
3020 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07003021
3022 /* Default VLAN ID and priority: don't set a default VLAN
3023 * ID, and set the default packet priority to zero.
3024 */
Vivien Didelotb7929fb2017-06-12 12:37:40 -04003025 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
Andrew Lunndbde9e62015-05-06 01:09:48 +02003026}
3027
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003028static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3029{
3030 struct mv88e6xxx_chip *chip = ds->priv;
3031
3032 if (chip->info->ops->port_set_jumbo_size)
Andrew Lunnb9c587f2021-09-26 19:41:26 +02003033 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
Chris Packham1baf0fa2020-07-24 11:21:22 +12003034 else if (chip->info->ops->set_max_frame_size)
Andrew Lunnb9c587f2021-09-26 19:41:26 +02003035 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3036 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003037}
3038
3039static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3040{
3041 struct mv88e6xxx_chip *chip = ds->priv;
3042 int ret = 0;
3043
Andrew Lunnb9c587f2021-09-26 19:41:26 +02003044 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3045 new_mtu += EDSA_HLEN;
3046
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003047 mv88e6xxx_reg_lock(chip);
3048 if (chip->info->ops->port_set_jumbo_size)
3049 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
Chris Packham1baf0fa2020-07-24 11:21:22 +12003050 else if (chip->info->ops->set_max_frame_size)
3051 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
Andrew Lunn2a550ae2020-07-11 22:32:05 +02003052 else
3053 if (new_mtu > 1522)
3054 ret = -EINVAL;
3055 mv88e6xxx_reg_unlock(chip);
3056
3057 return ret;
3058}
3059
Andrew Lunn04aca992017-05-26 01:03:24 +02003060static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3061 struct phy_device *phydev)
3062{
3063 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot523a8902017-05-26 18:02:42 -04003064 int err;
Andrew Lunn04aca992017-05-26 01:03:24 +02003065
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003066 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04003067 err = mv88e6xxx_serdes_power(chip, port, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003068 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02003069
3070 return err;
3071}
3072
Andrew Lunn75104db2019-02-24 20:44:43 +01003073static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
Andrew Lunn04aca992017-05-26 01:03:24 +02003074{
3075 struct mv88e6xxx_chip *chip = ds->priv;
3076
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003077 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04003078 if (mv88e6xxx_serdes_power(chip, port, false))
3079 dev_err(chip->dev, "failed to power off SERDES\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003080 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02003081}
3082
Vivien Didelot2cfcd962016-07-18 20:45:40 -04003083static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3084 unsigned int ageing_time)
3085{
Vivien Didelot04bed142016-08-31 18:06:13 -04003086 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04003087 int err;
3088
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003089 mv88e6xxx_reg_lock(chip);
Vivien Didelot720c6342017-03-11 16:12:48 -05003090 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003091 mv88e6xxx_reg_unlock(chip);
Vivien Didelot2cfcd962016-07-18 20:45:40 -04003092
3093 return err;
3094}
3095
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003096static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04003097{
3098 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04003099
Andrew Lunnde2273872016-11-21 23:27:01 +01003100 /* Initialize the statistics unit */
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003101 if (chip->info->ops->stats_set_histogram) {
3102 err = chip->info->ops->stats_set_histogram(chip);
3103 if (err)
3104 return err;
3105 }
Andrew Lunnde2273872016-11-21 23:27:01 +01003106
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003107 return mv88e6xxx_g1_stats_clear(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04003108}
3109
Andrew Lunnea890982019-01-09 00:24:03 +01003110/* Check if the errata has already been applied. */
3111static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3112{
3113 int port;
3114 int err;
3115 u16 val;
3116
3117 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02003118 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
Andrew Lunnea890982019-01-09 00:24:03 +01003119 if (err) {
3120 dev_err(chip->dev,
3121 "Error reading hidden register: %d\n", err);
3122 return false;
3123 }
3124 if (val != 0x01c0)
3125 return false;
3126 }
3127
3128 return true;
3129}
3130
3131/* The 6390 copper ports have an errata which require poking magic
3132 * values into undocumented hidden registers and then performing a
3133 * software reset.
3134 */
3135static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3136{
3137 int port;
3138 int err;
3139
3140 if (mv88e6390_setup_errata_applied(chip))
3141 return 0;
3142
3143 /* Set the ports into blocking mode */
3144 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3145 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3146 if (err)
3147 return err;
3148 }
3149
3150 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02003151 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
Andrew Lunnea890982019-01-09 00:24:03 +01003152 if (err)
3153 return err;
3154 }
3155
3156 return mv88e6xxx_software_reset(chip);
3157}
3158
Andrew Lunn23e8b472019-10-25 01:03:52 +02003159static void mv88e6xxx_teardown(struct dsa_switch *ds)
3160{
3161 mv88e6xxx_teardown_devlink_params(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003162 dsa_devlink_resources_unregister(ds);
Vladimir Olteanfd292c12021-09-17 17:29:16 +03003163 mv88e6xxx_teardown_devlink_regions_global(ds);
Andrew Lunn23e8b472019-10-25 01:03:52 +02003164}
3165
Vivien Didelotf81ec902016-05-09 13:22:58 -04003166static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07003167{
Vivien Didelot04bed142016-08-31 18:06:13 -04003168 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003169 u8 cmode;
Vivien Didelot552238b2016-05-09 13:22:49 -04003170 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04003171 int i;
3172
Vivien Didelotfad09c72016-06-21 12:28:20 -04003173 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003174 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04003175
Vladimir Olteance5df682021-07-22 18:55:41 +03003176 /* Since virtual bridges are mapped in the PVT, the number we support
3177 * depends on the physical switch topology. We need to let DSA figure
3178 * that out and therefore we cannot set this at dsa_register_switch()
3179 * time.
3180 */
3181 if (mv88e6xxx_has_pvt(chip))
Vladimir Oltean947c8742021-12-06 18:57:48 +02003182 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3183 ds->dst->last_switch - 1;
Vladimir Olteance5df682021-07-22 18:55:41 +03003184
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003185 mv88e6xxx_reg_lock(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04003186
Andrew Lunnea890982019-01-09 00:24:03 +01003187 if (chip->info->ops->setup_errata) {
3188 err = chip->info->ops->setup_errata(chip);
3189 if (err)
3190 goto unlock;
3191 }
3192
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003193 /* Cache the cmode of each port. */
3194 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3195 if (chip->info->ops->port_get_cmode) {
3196 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3197 if (err)
Dan Carpentere29129f2018-08-14 12:09:05 +03003198 goto unlock;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003199
3200 chip->ports[i].cmode = cmode;
3201 }
3202 }
3203
Vladimir Oltean5bded822021-10-07 19:47:11 +03003204 err = mv88e6xxx_vtu_setup(chip);
3205 if (err)
3206 goto unlock;
3207
Vivien Didelot97299342016-07-18 20:45:30 -04003208 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04003209 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotb759f522019-08-19 16:00:52 -04003210 if (dsa_is_unused_port(ds, i))
3211 continue;
3212
Hubert Feursteinc8574862019-07-31 10:23:48 +02003213 /* Prevent the use of an invalid port. */
Vivien Didelotb759f522019-08-19 16:00:52 -04003214 if (mv88e6xxx_is_invalid_port(chip, i)) {
Hubert Feursteinc8574862019-07-31 10:23:48 +02003215 dev_err(chip->dev, "port %d is invalid\n", i);
3216 err = -EINVAL;
3217 goto unlock;
3218 }
3219
Vivien Didelot97299342016-07-18 20:45:30 -04003220 err = mv88e6xxx_setup_port(chip, i);
3221 if (err)
3222 goto unlock;
3223 }
3224
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003225 err = mv88e6xxx_irl_setup(chip);
3226 if (err)
3227 goto unlock;
3228
Vivien Didelot04a69a12017-10-13 14:18:05 -04003229 err = mv88e6xxx_mac_setup(chip);
3230 if (err)
3231 goto unlock;
3232
Vivien Didelot1b17aed2017-05-26 18:03:05 -04003233 err = mv88e6xxx_phy_setup(chip);
3234 if (err)
3235 goto unlock;
3236
Vivien Didelot81228992017-03-30 17:37:08 -04003237 err = mv88e6xxx_pvt_setup(chip);
3238 if (err)
3239 goto unlock;
3240
Vivien Didelota2ac29d2017-03-11 16:12:49 -05003241 err = mv88e6xxx_atu_setup(chip);
3242 if (err)
3243 goto unlock;
3244
Andrew Lunn87fa8862017-11-09 22:29:56 +01003245 err = mv88e6xxx_broadcast_setup(chip, 0);
3246 if (err)
3247 goto unlock;
3248
Vivien Didelot9e907d72017-07-17 13:03:43 -04003249 err = mv88e6xxx_pot_setup(chip);
3250 if (err)
3251 goto unlock;
3252
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003253 err = mv88e6xxx_rmu_setup(chip);
3254 if (err)
3255 goto unlock;
3256
Vivien Didelot51c901a2017-07-17 13:03:41 -04003257 err = mv88e6xxx_rsvd2cpu_setup(chip);
3258 if (err)
3259 goto unlock;
Andrew Lunn6e55f692016-12-03 04:45:16 +01003260
Vivien Didelotb28f8722018-04-26 21:56:44 -04003261 err = mv88e6xxx_trunk_setup(chip);
3262 if (err)
3263 goto unlock;
3264
Vivien Didelotc7f047b2018-04-26 21:56:45 -04003265 err = mv88e6xxx_devmap_setup(chip);
3266 if (err)
3267 goto unlock;
3268
Vivien Didelot93e18d62018-05-11 17:16:35 -04003269 err = mv88e6xxx_pri_setup(chip);
3270 if (err)
3271 goto unlock;
3272
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01003273 /* Setup PTP Hardware Clock and timestamping */
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01003274 if (chip->info->ptp_support) {
3275 err = mv88e6xxx_ptp_setup(chip);
3276 if (err)
3277 goto unlock;
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01003278
3279 err = mv88e6xxx_hwtstamp_setup(chip);
3280 if (err)
3281 goto unlock;
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01003282 }
3283
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003284 err = mv88e6xxx_stats_setup(chip);
3285 if (err)
3286 goto unlock;
3287
Vivien Didelot6b17e862015-08-13 12:52:18 -04003288unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003289 mv88e6xxx_reg_unlock(chip);
Andrew Lunndb687a52015-06-20 21:31:29 +02003290
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003291 if (err)
3292 return err;
3293
3294 /* Have to be called without holding the register lock, since
3295 * they take the devlink lock, and we later take the locks in
3296 * the reverse order when getting/setting parameters or
3297 * resource occupancy.
Andrew Lunn23e8b472019-10-25 01:03:52 +02003298 */
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003299 err = mv88e6xxx_setup_devlink_resources(ds);
3300 if (err)
3301 return err;
3302
3303 err = mv88e6xxx_setup_devlink_params(ds);
3304 if (err)
Andrew Lunnbfb25542020-09-18 21:11:07 +02003305 goto out_resources;
3306
Vladimir Olteanfd292c12021-09-17 17:29:16 +03003307 err = mv88e6xxx_setup_devlink_regions_global(ds);
Andrew Lunnbfb25542020-09-18 21:11:07 +02003308 if (err)
3309 goto out_params;
3310
3311 return 0;
3312
3313out_params:
3314 mv88e6xxx_teardown_devlink_params(ds);
3315out_resources:
3316 dsa_devlink_resources_unregister(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003317
3318 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003319}
3320
Vladimir Olteanfd292c12021-09-17 17:29:16 +03003321static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3322{
3323 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3324}
3325
3326static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3327{
3328 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3329}
3330
Pali Rohár1fe976d2021-04-12 18:57:39 +02003331/* prod_id for switch families which do not have a PHY model number */
3332static const u16 family_prod_id_table[] = {
3333 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3334 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Marek Behúnc5d015b2021-04-20 09:54:02 +02003335 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
Pali Rohár1fe976d2021-04-12 18:57:39 +02003336};
3337
Vivien Didelote57e5e72016-08-15 17:19:00 -04003338static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003339{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003340 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3341 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Pali Rohár1fe976d2021-04-12 18:57:39 +02003342 u16 prod_id;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003343 u16 val;
3344 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003345
Andrew Lunnee26a222017-01-24 14:53:48 +01003346 if (!chip->info->ops->phy_read)
3347 return -EOPNOTSUPP;
3348
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003349 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003350 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003351 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003352
Pali Rohár1fe976d2021-04-12 18:57:39 +02003353 /* Some internal PHYs don't have a model number. */
3354 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3355 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3356 prod_id = family_prod_id_table[chip->info->family];
3357 if (prod_id)
3358 val |= prod_id >> 4;
Andrew Lunnda9f3302017-02-01 03:40:05 +01003359 }
3360
Vivien Didelote57e5e72016-08-15 17:19:00 -04003361 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003362}
3363
Vivien Didelote57e5e72016-08-15 17:19:00 -04003364static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003365{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003366 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3367 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003368 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003369
Andrew Lunnee26a222017-01-24 14:53:48 +01003370 if (!chip->info->ops->phy_write)
3371 return -EOPNOTSUPP;
3372
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003373 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003374 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003375 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003376
3377 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003378}
3379
Vivien Didelotfad09c72016-06-21 12:28:20 -04003380static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01003381 struct device_node *np,
3382 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02003383{
3384 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003385 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003386 struct mii_bus *bus;
3387 int err;
3388
Andrew Lunn2510bab2018-02-22 01:51:49 +01003389 if (external) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003390 mv88e6xxx_reg_lock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003391 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003392 mv88e6xxx_reg_unlock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003393
3394 if (err)
3395 return err;
3396 }
3397
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003398 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02003399 if (!bus)
3400 return -ENOMEM;
3401
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003402 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003403 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003404 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003405 INIT_LIST_HEAD(&mdio_bus->list);
3406 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003407
Andrew Lunnb516d452016-06-04 21:17:06 +02003408 if (np) {
3409 bus->name = np->full_name;
Rob Herringf7ce9102017-07-18 16:43:19 -05003410 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003411 } else {
3412 bus->name = "mv88e6xxx SMI";
3413 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3414 }
3415
3416 bus->read = mv88e6xxx_mdio_read;
3417 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003418 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02003419
Andrew Lunn6f882842018-03-17 20:32:05 +01003420 if (!external) {
3421 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3422 if (err)
3423 return err;
3424 }
3425
Florian Fainelli00e798c2018-05-15 16:56:19 -07003426 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003427 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003428 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunn6f882842018-03-17 20:32:05 +01003429 mv88e6xxx_g2_irq_mdio_free(chip, bus);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003430 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02003431 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003432
3433 if (external)
3434 list_add_tail(&mdio_bus->list, &chip->mdios);
3435 else
3436 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02003437
3438 return 0;
Andrew Lunnb516d452016-06-04 21:17:06 +02003439}
3440
Andrew Lunn3126aee2017-12-07 01:05:57 +01003441static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3442
3443{
3444 struct mv88e6xxx_mdio_bus *mdio_bus;
3445 struct mii_bus *bus;
3446
3447 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3448 bus = mdio_bus->bus;
3449
Andrew Lunn6f882842018-03-17 20:32:05 +01003450 if (!mdio_bus->external)
3451 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3452
Andrew Lunn3126aee2017-12-07 01:05:57 +01003453 mdiobus_unregister(bus);
3454 }
3455}
3456
Andrew Lunna3c53be52017-01-24 14:53:50 +01003457static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3458 struct device_node *np)
3459{
Andrew Lunna3c53be52017-01-24 14:53:50 +01003460 struct device_node *child;
3461 int err;
3462
3463 /* Always register one mdio bus for the internal/default mdio
3464 * bus. This maybe represented in the device tree, but is
3465 * optional.
3466 */
3467 child = of_get_child_by_name(np, "mdio");
3468 err = mv88e6xxx_mdio_register(chip, child, false);
3469 if (err)
3470 return err;
3471
3472 /* Walk the device tree, and see if there are any other nodes
3473 * which say they are compatible with the external mdio
3474 * bus.
3475 */
3476 for_each_available_child_of_node(np, child) {
Andrew Lunnceb96fa2020-09-01 04:32:57 +02003477 if (of_device_is_compatible(
3478 child, "marvell,mv88e6xxx-mdio-external")) {
Andrew Lunna3c53be52017-01-24 14:53:50 +01003479 err = mv88e6xxx_mdio_register(chip, child, true);
Andrew Lunn3126aee2017-12-07 01:05:57 +01003480 if (err) {
3481 mv88e6xxx_mdios_unregister(chip);
Nishka Dasgupta78e42042019-07-23 16:13:07 +05303482 of_node_put(child);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003483 return err;
Andrew Lunn3126aee2017-12-07 01:05:57 +01003484 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003485 }
3486 }
3487
3488 return 0;
3489}
3490
Vivien Didelot855b1932016-07-20 18:18:35 -04003491static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3492{
Vivien Didelot04bed142016-08-31 18:06:13 -04003493 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003494
3495 return chip->eeprom_len;
3496}
3497
Vivien Didelot855b1932016-07-20 18:18:35 -04003498static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3499 struct ethtool_eeprom *eeprom, u8 *data)
3500{
Vivien Didelot04bed142016-08-31 18:06:13 -04003501 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003502 int err;
3503
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003504 if (!chip->info->ops->get_eeprom)
3505 return -EOPNOTSUPP;
3506
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003507 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003508 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003509 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003510
3511 if (err)
3512 return err;
3513
3514 eeprom->magic = 0xc3ec4951;
3515
3516 return 0;
3517}
3518
Vivien Didelot855b1932016-07-20 18:18:35 -04003519static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3520 struct ethtool_eeprom *eeprom, u8 *data)
3521{
Vivien Didelot04bed142016-08-31 18:06:13 -04003522 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003523 int err;
3524
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003525 if (!chip->info->ops->set_eeprom)
3526 return -EOPNOTSUPP;
3527
Vivien Didelot855b1932016-07-20 18:18:35 -04003528 if (eeprom->magic != 0xc3ec4951)
3529 return -EINVAL;
3530
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003531 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003532 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003533 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003534
3535 return err;
3536}
3537
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003538static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003539 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003540 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3541 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003542 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003543 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003544 .phy_read = mv88e6185_phy_ppu_read,
3545 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003546 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003547 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003548 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003549 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003550 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003551 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3552 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003553 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003554 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003555 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003556 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003557 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003558 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003559 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003560 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003561 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003562 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3563 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003564 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003565 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3566 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003567 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003568 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003569 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003570 .ppu_enable = mv88e6185_g1_ppu_enable,
3571 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003572 .reset = mv88e6185_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003573 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003574 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003575 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003576 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003577 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003578};
3579
3580static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003581 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003582 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3583 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003584 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003585 .phy_read = mv88e6185_phy_ppu_read,
3586 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003587 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003588 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003589 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003590 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003591 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3592 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunna23b2962017-02-04 20:15:28 +01003593 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003594 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003595 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003596 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003597 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003598 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3599 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003600 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003601 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003602 .serdes_power = mv88e6185_serdes_power,
3603 .serdes_get_lane = mv88e6185_serdes_get_lane,
3604 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003605 .ppu_enable = mv88e6185_g1_ppu_enable,
3606 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003607 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003608 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003609 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003610 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003611 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003612};
3613
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003614static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01003615 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003616 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3617 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003618 .irl_init_all = mv88e6352_g2_irl_init_all,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003619 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3620 .phy_read = mv88e6xxx_g2_smi_phy_read,
3621 .phy_write = mv88e6xxx_g2_smi_phy_write,
3622 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003623 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003624 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003625 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003626 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003627 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3628 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003629 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003630 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003631 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003632 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003633 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003634 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003635 .port_setup_message_port = mv88e6xxx_setup_message_port,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003636 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003637 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003638 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3639 .stats_get_strings = mv88e6095_stats_get_strings,
3640 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003641 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3642 .set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01003643 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003644 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003645 .serdes_power = mv88e6185_serdes_power,
3646 .serdes_get_lane = mv88e6185_serdes_get_lane,
3647 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Chris Packham5c19bc82020-11-24 17:34:39 +13003648 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3649 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3650 .serdes_irq_status = mv88e6097_serdes_irq_status,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003651 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003652 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003653 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003654 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003655 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003656 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003657 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003658};
3659
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003660static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003661 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003662 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3663 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003664 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003665 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003666 .phy_read = mv88e6xxx_g2_smi_phy_read,
3667 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003668 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003669 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003670 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003671 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003672 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3673 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003674 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003675 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003676 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003677 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn0ac64c32017-06-02 23:22:46 +02003678 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003679 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003680 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3681 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003682 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003683 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3684 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003685 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003686 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003687 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003688 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003689 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3690 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003691 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003693 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003694 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003695};
3696
3697static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003698 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003699 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3700 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003701 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003702 .phy_read = mv88e6185_phy_ppu_read,
3703 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003704 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003705 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003706 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003707 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003708 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003709 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3710 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003711 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01003712 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Vivien Didelotcd782652017-06-08 18:34:13 -04003713 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003714 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003715 .port_pause_limit = mv88e6097_port_pause_limit,
Andrew Lunn54186b92018-08-09 15:38:37 +02003716 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003717 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003718 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003719 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003720 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003721 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3722 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003723 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003724 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3725 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003726 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003727 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003728 .ppu_enable = mv88e6185_g1_ppu_enable,
Vivien Didelot02317e62018-05-09 11:38:49 -04003729 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003730 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003731 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003732 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003733 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003734 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003735};
3736
Vivien Didelot990e27b2017-03-28 13:50:32 -04003737static const struct mv88e6xxx_ops mv88e6141_ops = {
3738 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003739 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3740 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003741 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003742 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3743 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3744 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3745 .phy_read = mv88e6xxx_g2_smi_phy_read,
3746 .phy_write = mv88e6xxx_g2_smi_phy_write,
3747 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003748 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003749 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003750 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003751 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003752 .port_tag_remap = mv88e6095_port_tag_remap,
Marek Behún7da467d2021-07-01 00:22:26 +02003753 .port_set_policy = mv88e6352_port_set_policy,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003754 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003755 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3756 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003757 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003758 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003759 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003760 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003761 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3762 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003763 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02003764 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003765 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003766 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Marek Behún11527f32021-07-01 00:22:27 +02003767 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003768 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3769 .stats_get_strings = mv88e6320_stats_get_strings,
3770 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003771 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3772 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003773 .watchdog_ops = &mv88e6390_watchdog_ops,
3774 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003775 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003776 .reset = mv88e6352_g1_reset,
Marek Behún37094882021-07-01 00:22:28 +02003777 .rmu_disable = mv88e6390_g1_rmu_disable,
Marek Behúnc07fff32021-07-01 00:22:29 +02003778 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3779 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003780 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003781 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02003782 .serdes_power = mv88e6390_serdes_power,
3783 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003784 /* Check status register pause & lpa register */
3785 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3786 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3787 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3788 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003789 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003790 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003791 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003792 .gpio_ops = &mv88e6352_gpio_ops,
Marek Behúna03b98d2021-07-01 00:22:30 +02003793 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3794 .serdes_get_strings = mv88e6390_serdes_get_strings,
3795 .serdes_get_stats = mv88e6390_serdes_get_stats,
Marek Behún953b0dc2021-07-01 00:22:31 +02003796 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3797 .serdes_get_regs = mv88e6390_serdes_get_regs,
Marek Behúne3af71a2019-02-25 12:39:55 +01003798 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003799};
3800
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003801static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003802 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003803 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3804 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003805 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003806 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003807 .phy_read = mv88e6xxx_g2_smi_phy_read,
3808 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003809 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003810 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003811 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003812 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003813 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003814 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3815 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003816 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003817 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003818 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003819 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003820 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003821 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003822 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna6da21b2019-03-01 23:43:39 +01003823 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003824 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003825 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3826 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003827 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003828 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3829 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003830 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003831 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003832 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003833 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003834 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3835 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003836 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003837 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003838 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003839 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003840 .phylink_validate = mv88e6185_phylink_validate,
Andrew Lunnfe230362021-09-26 19:41:24 +02003841 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003842};
3843
3844static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003845 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003846 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3847 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003848 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003849 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003850 .phy_read = mv88e6165_phy_read,
3851 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003852 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003853 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003854 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003857 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003858 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003859 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003860 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003861 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3862 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003863 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003864 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3865 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003866 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003867 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003868 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003869 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003870 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3871 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003872 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003873 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003874 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003875 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003876 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003877};
3878
3879static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003880 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003881 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3882 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003883 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003884 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003885 .phy_read = mv88e6xxx_g2_smi_phy_read,
3886 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003887 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003888 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003889 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003890 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003891 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003892 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003893 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3894 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003895 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003896 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003897 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003898 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003901 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003902 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003903 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003904 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003905 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3906 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003907 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003908 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3909 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003910 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003911 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003912 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003913 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003914 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3915 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003916 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003917 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003918 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003919};
3920
3921static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003922 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003923 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3924 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003925 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003926 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3927 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003928 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003929 .phy_read = mv88e6xxx_g2_smi_phy_read,
3930 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003931 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003932 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003933 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003934 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003935 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003936 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003937 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003938 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3939 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003940 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003941 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003942 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003943 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003944 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003945 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003946 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003947 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003948 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003949 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003950 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3951 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003952 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003953 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3954 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003955 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003956 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003957 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003958 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003959 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003960 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3961 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003962 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003963 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003964 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003965 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3966 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3967 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3968 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003969 .serdes_power = mv88e6352_serdes_power,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003970 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3971 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003972 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003973 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003974};
3975
3976static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003977 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003978 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3979 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003980 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003981 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003982 .phy_read = mv88e6xxx_g2_smi_phy_read,
3983 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003984 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003985 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003986 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003987 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003988 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003989 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003990 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3991 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003992 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003993 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003994 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003995 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003996 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003997 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003998 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003999 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004000 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004001 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004002 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4003 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004004 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004005 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4006 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004007 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004008 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004009 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004010 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004011 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4012 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004013 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004014 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004015 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004016};
4017
4018static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004019 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004020 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4021 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004022 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004023 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4024 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004025 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004026 .phy_read = mv88e6xxx_g2_smi_phy_read,
4027 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004028 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004029 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004030 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004031 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004032 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004033 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004034 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004035 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4036 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004037 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004038 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004039 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004040 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004041 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004042 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004043 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004044 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004045 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004046 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004047 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4048 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004049 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004050 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4051 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004052 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004053 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004054 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004055 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004056 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004057 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4058 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004059 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004060 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004061 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004062 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4063 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4064 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4065 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004066 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004067 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004068 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004069 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004070 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4071 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004072 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004073 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004074};
4075
4076static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004077 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004078 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4079 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004080 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04004081 .phy_read = mv88e6185_phy_ppu_read,
4082 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004083 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004084 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004085 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004086 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004087 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4088 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunnef70b112016-12-03 04:45:18 +01004089 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01004090 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn54186b92018-08-09 15:38:37 +02004091 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004092 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004093 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004094 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004095 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004096 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4097 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004098 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004099 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4100 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004101 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004102 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13004103 .serdes_power = mv88e6185_serdes_power,
4104 .serdes_get_lane = mv88e6185_serdes_get_lane,
4105 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Vivien Didelot02317e62018-05-09 11:38:49 -04004106 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05004107 .ppu_enable = mv88e6185_g1_ppu_enable,
4108 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004109 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004110 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004111 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004112 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12004113 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004114};
4115
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004116static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004117 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004118 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004119 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004120 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4121 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004122 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4123 .phy_read = mv88e6xxx_g2_smi_phy_read,
4124 .phy_write = mv88e6xxx_g2_smi_phy_write,
4125 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004126 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004127 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004128 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004129 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004130 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004131 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004132 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004133 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4134 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004135 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12004136 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04004137 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004140 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004141 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004142 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004143 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004144 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004145 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4146 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004147 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004148 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4149 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004150 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004151 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004152 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004153 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004154 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004155 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4156 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004157 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4158 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004159 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004160 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004161 /* Check status register pause & lpa register */
4162 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4163 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4164 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4165 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004166 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004167 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004168 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004169 .serdes_get_strings = mv88e6390_serdes_get_strings,
4170 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004171 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4172 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004173 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004174 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004175};
4176
4177static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004178 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004179 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004180 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004181 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4182 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004183 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4184 .phy_read = mv88e6xxx_g2_smi_phy_read,
4185 .phy_write = mv88e6xxx_g2_smi_phy_write,
4186 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004187 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004188 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004189 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004190 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004191 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004192 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004193 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004194 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4195 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004196 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12004197 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04004198 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004199 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004200 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004201 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004202 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004203 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004204 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004205 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004206 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4207 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004208 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004209 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4210 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004211 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004212 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004213 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004214 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004215 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004216 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4217 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004218 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4219 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004220 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004221 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004222 /* Check status register pause & lpa register */
4223 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4224 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4225 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4226 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004227 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004228 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004229 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004230 .serdes_get_strings = mv88e6390_serdes_get_strings,
4231 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004232 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4233 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004234 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004235 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004236};
4237
4238static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004239 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004240 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004241 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004242 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4243 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004244 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4245 .phy_read = mv88e6xxx_g2_smi_phy_read,
4246 .phy_write = mv88e6xxx_g2_smi_phy_write,
4247 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004248 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004249 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004250 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004251 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004252 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004253 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004254 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4255 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004256 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004257 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004258 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004259 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004260 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004261 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004262 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004263 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004264 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004265 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4266 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004267 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004268 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4269 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004270 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004271 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004272 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004273 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004274 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004275 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4276 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004277 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4278 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004279 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004280 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004281 /* Check status register pause & lpa register */
4282 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4283 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4284 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4285 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004286 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004287 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004288 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004289 .serdes_get_strings = mv88e6390_serdes_get_strings,
4290 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004291 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4292 .serdes_get_regs = mv88e6390_serdes_get_regs,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004293 .avb_ops = &mv88e6390_avb_ops,
4294 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004295 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004296};
4297
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004298static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004299 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004300 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4301 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004302 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004303 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4304 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004305 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004306 .phy_read = mv88e6xxx_g2_smi_phy_read,
4307 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004308 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004309 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004310 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004311 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004312 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004313 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004314 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004315 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4316 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004317 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004318 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004319 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004320 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004321 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004322 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004323 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004324 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004325 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004326 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004327 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4328 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004329 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004330 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4331 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004332 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004333 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004334 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004335 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004336 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004337 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4338 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004339 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004340 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004341 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004342 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4343 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4344 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4345 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004346 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004347 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004348 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004349 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004350 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4351 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004352 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004353 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004354 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004355 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004356};
4357
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004358static const struct mv88e6xxx_ops mv88e6250_ops = {
4359 /* MV88E6XXX_FAMILY_6250 */
4360 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4361 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4362 .irl_init_all = mv88e6352_g2_irl_init_all,
4363 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4364 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4365 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4366 .phy_read = mv88e6xxx_g2_smi_phy_read,
4367 .phy_write = mv88e6xxx_g2_smi_phy_write,
4368 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004369 .port_sync_link = mv88e6xxx_port_sync_link,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004370 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004371 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004372 .port_tag_remap = mv88e6095_port_tag_remap,
4373 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004376 .port_set_ether_type = mv88e6351_port_set_ether_type,
4377 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4378 .port_pause_limit = mv88e6097_port_pause_limit,
4379 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004380 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4381 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4382 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4383 .stats_get_strings = mv88e6250_stats_get_strings,
4384 .stats_get_stats = mv88e6250_stats_get_stats,
4385 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4386 .set_egress_port = mv88e6095_g1_set_egress_port,
4387 .watchdog_ops = &mv88e6250_watchdog_ops,
4388 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4389 .pot_clear = mv88e6xxx_g2_pot_clear,
4390 .reset = mv88e6250_g1_reset,
Rasmus Villemoes67c9ed12021-01-25 16:04:48 +01004391 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Rasmus Villemoesb28f3f32021-01-25 16:04:49 +01004392 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Hubert Feurstein71509612019-07-31 10:23:51 +02004393 .avb_ops = &mv88e6352_avb_ops,
4394 .ptp_ops = &mv88e6250_ptp_ops,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004395 .phylink_validate = mv88e6065_phylink_validate,
4396};
4397
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004398static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004399 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004400 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004401 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004402 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4403 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4405 .phy_read = mv88e6xxx_g2_smi_phy_read,
4406 .phy_write = mv88e6xxx_g2_smi_phy_write,
4407 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004408 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004410 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004411 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004412 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004413 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004414 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004415 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4416 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004417 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004418 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004419 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004420 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004421 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004422 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004423 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004424 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004425 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004426 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4427 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004428 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004429 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4430 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004431 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004432 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004433 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004434 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004435 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004436 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4437 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004438 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4439 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004440 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004441 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004442 /* Check status register pause & lpa register */
4443 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4444 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4445 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4446 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004447 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004448 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004449 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004450 .serdes_get_strings = mv88e6390_serdes_get_strings,
4451 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004452 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4453 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004454 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004455 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004456 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004457 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004458};
4459
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004460static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004461 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004462 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4463 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004464 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004465 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4466 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004468 .phy_read = mv88e6xxx_g2_smi_phy_read,
4469 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004470 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004471 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004472 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004473 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004474 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004475 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4476 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004477 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004478 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004479 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004480 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004481 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004482 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004483 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004484 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004485 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004486 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004487 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4488 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004489 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004490 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4491 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004492 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004493 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004494 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004495 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004496 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004497 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004498 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004499 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004500 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004501 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004502};
4503
4504static const struct mv88e6xxx_ops mv88e6321_ops = {
Vivien Didelotbd807202017-07-17 13:03:37 -04004505 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004506 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4507 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004508 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004509 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4510 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004511 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004512 .phy_read = mv88e6xxx_g2_smi_phy_read,
4513 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004514 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004515 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004516 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004517 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004518 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004519 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4520 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004521 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004522 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004523 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004524 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004525 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004526 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004527 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004528 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004529 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004530 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004531 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4532 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004533 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004534 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4535 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004536 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004537 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004538 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004539 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004540 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004541 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004542 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004543 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004544};
4545
Vivien Didelot16e329a2017-03-28 13:50:33 -04004546static const struct mv88e6xxx_ops mv88e6341_ops = {
4547 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004548 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4549 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004550 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004551 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4552 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4553 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4554 .phy_read = mv88e6xxx_g2_smi_phy_read,
4555 .phy_write = mv88e6xxx_g2_smi_phy_write,
4556 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004557 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004558 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004559 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004560 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004561 .port_tag_remap = mv88e6095_port_tag_remap,
Marek Behún7da467d2021-07-01 00:22:26 +02004562 .port_set_policy = mv88e6352_port_set_policy,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004563 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004564 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4565 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004566 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004567 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004568 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004569 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004570 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4571 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004572 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02004573 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004574 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004575 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Marek Behún11527f32021-07-01 00:22:27 +02004576 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004577 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4578 .stats_get_strings = mv88e6320_stats_get_strings,
4579 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004580 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4581 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004582 .watchdog_ops = &mv88e6390_watchdog_ops,
4583 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004584 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004585 .reset = mv88e6352_g1_reset,
Marek Behún37094882021-07-01 00:22:28 +02004586 .rmu_disable = mv88e6390_g1_rmu_disable,
Marek Behúnc07fff32021-07-01 00:22:29 +02004587 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4588 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004589 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004591 .serdes_power = mv88e6390_serdes_power,
4592 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004593 /* Check status register pause & lpa register */
4594 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4595 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4596 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4597 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004598 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004599 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004600 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004601 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004602 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004603 .ptp_ops = &mv88e6352_ptp_ops,
Marek Behúna03b98d2021-07-01 00:22:30 +02004604 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4605 .serdes_get_strings = mv88e6390_serdes_get_strings,
4606 .serdes_get_stats = mv88e6390_serdes_get_stats,
Marek Behún953b0dc2021-07-01 00:22:31 +02004607 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4608 .serdes_get_regs = mv88e6390_serdes_get_regs,
Marek Behúne3af71a2019-02-25 12:39:55 +01004609 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004610};
4611
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004612static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004613 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004614 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4615 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004616 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004618 .phy_read = mv88e6xxx_g2_smi_phy_read,
4619 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004620 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004621 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004622 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004623 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004624 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004625 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004626 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4627 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004628 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004629 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004630 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004631 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004632 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004633 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004634 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004635 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004636 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004637 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004638 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4639 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004640 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004641 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4642 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004643 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004644 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004645 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004646 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004647 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4648 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004649 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004650 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004651 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004652};
4653
4654static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004655 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004656 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4657 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004658 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004659 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004660 .phy_read = mv88e6xxx_g2_smi_phy_read,
4661 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004662 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004663 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004664 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004665 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004666 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004667 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004668 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4669 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004670 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004671 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004672 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004673 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004674 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004675 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004676 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004677 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004678 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004679 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004680 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4681 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004682 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004683 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4684 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004685 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004686 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004687 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004688 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004689 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4690 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004691 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004693 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004694 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004695 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004696};
4697
4698static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004699 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004700 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4701 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004702 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004703 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4704 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004705 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004706 .phy_read = mv88e6xxx_g2_smi_phy_read,
4707 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004708 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004709 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004710 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004711 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004712 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004713 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004714 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004715 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4716 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004717 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004718 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004719 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004720 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004721 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004722 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004723 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004724 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004725 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004726 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004727 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4728 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004729 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004730 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4731 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004732 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004733 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004734 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004735 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004736 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004737 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4738 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004739 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004740 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004741 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004742 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4743 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4744 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4745 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004746 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004747 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004748 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004749 .serdes_irq_status = mv88e6352_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004750 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004751 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004752 .ptp_ops = &mv88e6352_ptp_ops,
Andrew Lunncda9f4a2018-03-01 02:02:31 +01004753 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4754 .serdes_get_strings = mv88e6352_serdes_get_strings,
4755 .serdes_get_stats = mv88e6352_serdes_get_stats,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004756 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4757 .serdes_get_regs = mv88e6352_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004758 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004759};
4760
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004761static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004762 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004763 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004764 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004765 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4766 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004767 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4768 .phy_read = mv88e6xxx_g2_smi_phy_read,
4769 .phy_write = mv88e6xxx_g2_smi_phy_write,
4770 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004771 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004772 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004773 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004774 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004775 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004776 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004777 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004778 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4779 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004780 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004781 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004782 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004783 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004784 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004785 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004786 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004787 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004788 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004789 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004790 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004791 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4792 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004793 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004794 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4795 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004796 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004797 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004798 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004799 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004800 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004801 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4802 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004803 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4804 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004805 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004806 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004807 /* Check status register pause & lpa register */
4808 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4809 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4810 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4811 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004812 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004813 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004814 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004815 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004816 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004817 .ptp_ops = &mv88e6352_ptp_ops,
Nikita Yushchenko0df95282019-12-25 08:22:38 +03004818 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4819 .serdes_get_strings = mv88e6390_serdes_get_strings,
4820 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004821 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4822 .serdes_get_regs = mv88e6390_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004823 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004824};
4825
4826static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004827 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004828 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004829 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004830 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4831 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004832 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4833 .phy_read = mv88e6xxx_g2_smi_phy_read,
4834 .phy_write = mv88e6xxx_g2_smi_phy_write,
4835 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004836 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004837 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004838 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004839 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004840 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004841 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004842 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004843 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4844 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004845 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004846 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004847 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004848 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004849 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004850 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004851 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnb3dce4d2018-11-11 00:32:14 +01004852 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004853 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004854 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004855 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004856 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4857 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004858 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004859 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4860 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004861 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004862 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004863 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004864 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004865 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004866 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4867 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004868 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4869 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004870 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004871 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004872 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4873 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4874 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4875 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004876 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004877 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004878 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004879 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4880 .serdes_get_strings = mv88e6390_serdes_get_strings,
4881 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004882 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4883 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004884 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004885 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004886 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004887 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004888};
4889
Pavana Sharmade776d02021-03-17 14:46:42 +01004890static const struct mv88e6xxx_ops mv88e6393x_ops = {
4891 /* MV88E6XXX_FAMILY_6393 */
4892 .setup_errata = mv88e6393x_serdes_setup_errata,
4893 .irl_init_all = mv88e6390_g2_irl_init_all,
4894 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4895 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4896 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4897 .phy_read = mv88e6xxx_g2_smi_phy_read,
4898 .phy_write = mv88e6xxx_g2_smi_phy_write,
4899 .port_set_link = mv88e6xxx_port_set_link,
4900 .port_sync_link = mv88e6xxx_port_sync_link,
4901 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4902 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4903 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4904 .port_tag_remap = mv88e6390_port_tag_remap,
Marek Behún6584b262021-03-17 14:46:43 +01004905 .port_set_policy = mv88e6393x_port_set_policy,
Pavana Sharmade776d02021-03-17 14:46:42 +01004906 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4907 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4908 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4909 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4910 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4911 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4912 .port_pause_limit = mv88e6390_port_pause_limit,
4913 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4914 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4915 .port_get_cmode = mv88e6352_port_get_cmode,
4916 .port_set_cmode = mv88e6393x_port_set_cmode,
4917 .port_setup_message_port = mv88e6xxx_setup_message_port,
4918 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4919 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4920 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4921 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4922 .stats_get_strings = mv88e6320_stats_get_strings,
4923 .stats_get_stats = mv88e6390_stats_get_stats,
4924 /* .set_cpu_port is missing because this family does not support a global
4925 * CPU port, only per port CPU port which is set via
4926 * .port_set_upstream_port method.
4927 */
4928 .set_egress_port = mv88e6393x_set_egress_port,
4929 .watchdog_ops = &mv88e6390_watchdog_ops,
4930 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4931 .pot_clear = mv88e6xxx_g2_pot_clear,
4932 .reset = mv88e6352_g1_reset,
4933 .rmu_disable = mv88e6390_g1_rmu_disable,
4934 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4935 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4936 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4937 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4938 .serdes_power = mv88e6393x_serdes_power,
4939 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4940 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4941 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4942 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4943 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4944 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4945 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4946 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4947 /* TODO: serdes stats */
4948 .gpio_ops = &mv88e6352_gpio_ops,
4949 .avb_ops = &mv88e6390_avb_ops,
4950 .ptp_ops = &mv88e6352_ptp_ops,
4951 .phylink_validate = mv88e6393x_phylink_validate,
4952};
4953
Vivien Didelotf81ec902016-05-09 13:22:58 -04004954static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4955 [MV88E6085] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004956 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004957 .family = MV88E6XXX_FAMILY_6097,
4958 .name = "Marvell 88E6085",
4959 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004960 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004961 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01004962 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004963 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004964 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004965 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004966 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004967 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004968 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004969 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004970 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004971 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004972 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004973 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004974 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004975 },
4976
4977 [MV88E6095] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004978 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004979 .family = MV88E6XXX_FAMILY_6095,
4980 .name = "Marvell 88E6095/88E6095F",
4981 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004982 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004983 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01004984 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004985 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004986 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004987 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004988 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004989 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004990 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004991 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05004992 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004993 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004994 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004995 },
4996
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004997 [MV88E6097] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004999 .family = MV88E6XXX_FAMILY_6097,
5000 .name = "Marvell 88E6097/88E6097F",
5001 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005002 .num_macs = 8192,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005003 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01005004 .num_internal_phys = 8,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005005 .max_vid = 4095,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005006 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005007 .phy_base_addr = 0x0,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005008 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005009 .global2_addr = 0x1c,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005010 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01005011 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005012 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005013 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005014 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005015 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005016 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01005017 .ops = &mv88e6097_ops,
5018 },
5019
Vivien Didelotf81ec902016-05-09 13:22:58 -04005020 [MV88E6123] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005022 .family = MV88E6XXX_FAMILY_6165,
5023 .name = "Marvell 88E6123",
5024 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005025 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005026 .num_ports = 3,
Andrew Lunnbc393152018-03-17 20:32:04 +01005027 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005028 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005029 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005030 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005031 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005032 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005033 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005034 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005035 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005036 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005037 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005038 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005039 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005040 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005041 },
5042
5043 [MV88E6131] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005044 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005045 .family = MV88E6XXX_FAMILY_6185,
5046 .name = "Marvell 88E6131",
5047 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005048 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005049 .num_ports = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005050 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005051 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005052 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005053 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005054 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005055 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005056 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005057 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05005058 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005059 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005060 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005061 },
5062
Vivien Didelot990e27b2017-03-28 13:50:32 -04005063 [MV88E6141] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005064 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005065 .family = MV88E6XXX_FAMILY_6341,
Uwe Kleine-König79a68b22018-03-20 10:44:40 +01005066 .name = "Marvell 88E6141",
Vivien Didelot990e27b2017-03-28 13:50:32 -04005067 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005068 .num_macs = 2048,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005069 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01005070 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005071 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005072 .max_vid = 4095,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005073 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005074 .phy_base_addr = 0x10,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005075 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005076 .global2_addr = 0x1c,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005077 .age_time_coeff = 3750,
5078 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01005079 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005080 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04005081 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005082 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005083 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelot990e27b2017-03-28 13:50:32 -04005084 .ops = &mv88e6141_ops,
5085 },
5086
Vivien Didelotf81ec902016-05-09 13:22:58 -04005087 [MV88E6161] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005088 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005089 .family = MV88E6XXX_FAMILY_6165,
5090 .name = "Marvell 88E6161",
5091 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005092 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005093 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01005094 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005095 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005096 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005097 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005098 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005099 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005100 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005101 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005102 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005103 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005104 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005105 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005106 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Andrew Lunndfa54342018-07-18 22:38:22 +02005107 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005108 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005109 },
5110
5111 [MV88E6165] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005113 .family = MV88E6XXX_FAMILY_6165,
5114 .name = "Marvell 88E6165",
5115 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005116 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005117 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01005118 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005119 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005120 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005121 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005122 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005123 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005124 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005125 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005126 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005127 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005128 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005129 .multi_chip = true,
Andrew Lunndfa54342018-07-18 22:38:22 +02005130 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005131 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005132 },
5133
5134 [MV88E6171] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005136 .family = MV88E6XXX_FAMILY_6351,
5137 .name = "Marvell 88E6171",
5138 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005139 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005140 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005141 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005142 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005143 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005144 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005145 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005146 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005147 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005148 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005149 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005150 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005151 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005152 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005153 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005154 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005155 },
5156
5157 [MV88E6172] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005158 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005159 .family = MV88E6XXX_FAMILY_6352,
5160 .name = "Marvell 88E6172",
5161 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005162 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005163 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005164 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005165 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005166 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005167 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005168 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005169 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005170 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005171 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005172 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005173 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005174 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005175 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005176 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005177 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005178 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005179 },
5180
5181 [MV88E6175] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005182 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005183 .family = MV88E6XXX_FAMILY_6351,
5184 .name = "Marvell 88E6175",
5185 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005186 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005187 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005188 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005189 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005190 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005191 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005192 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005193 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005194 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005195 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005196 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005197 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005198 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005199 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005200 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005201 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005202 },
5203
5204 [MV88E6176] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005205 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005206 .family = MV88E6XXX_FAMILY_6352,
5207 .name = "Marvell 88E6176",
5208 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005209 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005210 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005211 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005212 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005213 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005214 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005215 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005216 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005217 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005218 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005219 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005220 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005221 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005222 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005223 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005224 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005225 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005226 },
5227
5228 [MV88E6185] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005230 .family = MV88E6XXX_FAMILY_6185,
5231 .name = "Marvell 88E6185",
5232 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005233 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005234 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01005235 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005236 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005237 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005238 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005239 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005240 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005241 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005242 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05005243 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005244 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005245 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005246 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005247 },
5248
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005249 [MV88E6190] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005250 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005251 .family = MV88E6XXX_FAMILY_6390,
5252 .name = "Marvell 88E6190",
5253 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005254 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005255 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005256 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005257 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005258 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005259 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005260 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005261 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005262 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005263 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005264 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005265 .g2_irqs = 14,
Vivien Didelotf3645652017-03-30 17:37:07 -04005266 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005267 .multi_chip = true,
Vivien Didelote606ca32017-03-11 16:12:55 -05005268 .atu_move_port_mask = 0x1f,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005269 .ops = &mv88e6190_ops,
5270 },
5271
5272 [MV88E6190X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005273 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005274 .family = MV88E6XXX_FAMILY_6390,
5275 .name = "Marvell 88E6190X",
5276 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005277 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005278 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005279 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005280 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005281 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005282 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005283 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005284 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005285 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005286 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005287 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005288 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005289 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005290 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005291 .multi_chip = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005292 .ops = &mv88e6190x_ops,
5293 },
5294
5295 [MV88E6191] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005296 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005297 .family = MV88E6XXX_FAMILY_6390,
5298 .name = "Marvell 88E6191",
5299 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005300 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005301 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005302 .num_internal_phys = 9,
Vivien Didelot931d1822017-05-01 14:05:27 -04005303 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005304 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005305 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005306 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005307 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005308 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005309 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005310 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005311 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005312 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005313 .multi_chip = true,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005314 .ptp_support = true,
Vivien Didelot2cf4cefb2017-03-28 13:50:34 -04005315 .ops = &mv88e6191_ops,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005316 },
5317
Pavana Sharmade776d02021-03-17 14:46:42 +01005318 [MV88E6191X] = {
5319 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5320 .family = MV88E6XXX_FAMILY_6393,
5321 .name = "Marvell 88E6191X",
5322 .num_databases = 4096,
5323 .num_ports = 11, /* 10 + Z80 */
5324 .num_internal_phys = 9,
5325 .max_vid = 8191,
5326 .port_base_addr = 0x0,
5327 .phy_base_addr = 0x0,
5328 .global1_addr = 0x1b,
5329 .global2_addr = 0x1c,
5330 .age_time_coeff = 3750,
5331 .g1_irqs = 10,
5332 .g2_irqs = 14,
5333 .atu_move_port_mask = 0x1f,
5334 .pvt = true,
5335 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005336 .ptp_support = true,
5337 .ops = &mv88e6393x_ops,
5338 },
5339
5340 [MV88E6193X] = {
5341 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5342 .family = MV88E6XXX_FAMILY_6393,
5343 .name = "Marvell 88E6193X",
5344 .num_databases = 4096,
5345 .num_ports = 11, /* 10 + Z80 */
5346 .num_internal_phys = 9,
5347 .max_vid = 8191,
5348 .port_base_addr = 0x0,
5349 .phy_base_addr = 0x0,
5350 .global1_addr = 0x1b,
5351 .global2_addr = 0x1c,
5352 .age_time_coeff = 3750,
5353 .g1_irqs = 10,
5354 .g2_irqs = 14,
5355 .atu_move_port_mask = 0x1f,
5356 .pvt = true,
5357 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005358 .ptp_support = true,
5359 .ops = &mv88e6393x_ops,
5360 },
5361
Hubert Feurstein49022642019-07-31 10:23:46 +02005362 [MV88E6220] = {
5363 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5364 .family = MV88E6XXX_FAMILY_6250,
5365 .name = "Marvell 88E6220",
5366 .num_databases = 64,
5367
5368 /* Ports 2-4 are not routed to pins
5369 * => usable ports 0, 1, 5, 6
5370 */
5371 .num_ports = 7,
5372 .num_internal_phys = 2,
Hubert Feursteinc8574862019-07-31 10:23:48 +02005373 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
Hubert Feurstein49022642019-07-31 10:23:46 +02005374 .max_vid = 4095,
5375 .port_base_addr = 0x08,
5376 .phy_base_addr = 0x00,
5377 .global1_addr = 0x0f,
5378 .global2_addr = 0x07,
5379 .age_time_coeff = 15000,
5380 .g1_irqs = 9,
5381 .g2_irqs = 10,
5382 .atu_move_port_mask = 0xf,
5383 .dual_chip = true,
Hubert Feurstein71509612019-07-31 10:23:51 +02005384 .ptp_support = true,
Hubert Feurstein49022642019-07-31 10:23:46 +02005385 .ops = &mv88e6250_ops,
5386 },
5387
Vivien Didelotf81ec902016-05-09 13:22:58 -04005388 [MV88E6240] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005389 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005390 .family = MV88E6XXX_FAMILY_6352,
5391 .name = "Marvell 88E6240",
5392 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005393 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005394 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005395 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005396 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005397 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005398 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005399 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005400 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005401 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005402 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005403 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005404 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005405 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005406 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005407 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005408 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005409 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005410 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005411 },
5412
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005413 [MV88E6250] = {
5414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5415 .family = MV88E6XXX_FAMILY_6250,
5416 .name = "Marvell 88E6250",
5417 .num_databases = 64,
5418 .num_ports = 7,
5419 .num_internal_phys = 5,
5420 .max_vid = 4095,
5421 .port_base_addr = 0x08,
5422 .phy_base_addr = 0x00,
5423 .global1_addr = 0x0f,
5424 .global2_addr = 0x07,
5425 .age_time_coeff = 15000,
5426 .g1_irqs = 9,
5427 .g2_irqs = 10,
5428 .atu_move_port_mask = 0xf,
5429 .dual_chip = true,
Hubert Feurstein71509612019-07-31 10:23:51 +02005430 .ptp_support = true,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005431 .ops = &mv88e6250_ops,
5432 },
5433
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005434 [MV88E6290] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005435 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005436 .family = MV88E6XXX_FAMILY_6390,
5437 .name = "Marvell 88E6290",
5438 .num_databases = 4096,
5439 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005440 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005441 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005442 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005443 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005444 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005445 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005446 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005447 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005448 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005449 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005450 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005451 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005452 .multi_chip = true,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005453 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005454 .ops = &mv88e6290_ops,
5455 },
5456
Vivien Didelotf81ec902016-05-09 13:22:58 -04005457 [MV88E6320] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005458 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005459 .family = MV88E6XXX_FAMILY_6320,
5460 .name = "Marvell 88E6320",
5461 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005462 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005463 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005464 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005465 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005466 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005467 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005468 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005469 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005470 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005471 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005472 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005473 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005474 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005475 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005476 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005477 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005478 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005479 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005480 },
5481
5482 [MV88E6321] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005483 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005484 .family = MV88E6XXX_FAMILY_6320,
5485 .name = "Marvell 88E6321",
5486 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005487 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005488 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005489 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005490 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005491 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005492 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005493 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005494 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005495 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005496 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005497 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005498 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005499 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005500 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005501 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005502 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005503 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005504 },
5505
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005506 [MV88E6341] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005507 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005508 .family = MV88E6XXX_FAMILY_6341,
5509 .name = "Marvell 88E6341",
5510 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005511 .num_macs = 2048,
Andrew Lunnbc393152018-03-17 20:32:04 +01005512 .num_internal_phys = 5,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005513 .num_ports = 6,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005514 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005515 .max_vid = 4095,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005516 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005517 .phy_base_addr = 0x10,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005518 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005519 .global2_addr = 0x1c,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005520 .age_time_coeff = 3750,
Vivien Didelote606ca32017-03-11 16:12:55 -05005521 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01005522 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005523 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04005524 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005525 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005526 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005527 .ptp_support = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005528 .ops = &mv88e6341_ops,
5529 },
5530
Vivien Didelotf81ec902016-05-09 13:22:58 -04005531 [MV88E6350] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005532 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005533 .family = MV88E6XXX_FAMILY_6351,
5534 .name = "Marvell 88E6350",
5535 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005536 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005537 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005538 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005539 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005540 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005541 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005542 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005543 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005544 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005545 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005546 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005547 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005548 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005549 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005550 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005551 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005552 },
5553
5554 [MV88E6351] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005555 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005556 .family = MV88E6XXX_FAMILY_6351,
5557 .name = "Marvell 88E6351",
5558 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005559 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005560 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005561 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005562 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005563 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005564 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005565 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005566 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005567 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005568 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005569 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005570 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005571 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005572 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005573 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005574 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005575 },
5576
5577 [MV88E6352] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005578 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005579 .family = MV88E6XXX_FAMILY_6352,
5580 .name = "Marvell 88E6352",
5581 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005582 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005583 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005584 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005585 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005586 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005587 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005588 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005589 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005590 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005591 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005592 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005593 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005594 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005595 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005596 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005597 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005598 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005599 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005600 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005601 [MV88E6390] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005602 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005603 .family = MV88E6XXX_FAMILY_6390,
5604 .name = "Marvell 88E6390",
5605 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005606 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005607 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005608 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005609 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005610 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005611 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005612 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005613 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005614 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005615 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005616 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005617 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005618 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005619 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005620 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005621 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005622 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005623 .ops = &mv88e6390_ops,
5624 },
5625 [MV88E6390X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005626 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005627 .family = MV88E6XXX_FAMILY_6390,
5628 .name = "Marvell 88E6390X",
5629 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005630 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005631 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005632 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005633 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005634 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005635 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005636 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005637 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005638 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005639 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005640 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005641 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005642 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005643 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005644 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005645 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005646 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005647 .ops = &mv88e6390x_ops,
5648 },
Pavana Sharmade776d02021-03-17 14:46:42 +01005649
5650 [MV88E6393X] = {
5651 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5652 .family = MV88E6XXX_FAMILY_6393,
5653 .name = "Marvell 88E6393X",
5654 .num_databases = 4096,
5655 .num_ports = 11, /* 10 + Z80 */
5656 .num_internal_phys = 9,
5657 .max_vid = 8191,
5658 .port_base_addr = 0x0,
5659 .phy_base_addr = 0x0,
5660 .global1_addr = 0x1b,
5661 .global2_addr = 0x1c,
5662 .age_time_coeff = 3750,
5663 .g1_irqs = 10,
5664 .g2_irqs = 14,
5665 .atu_move_port_mask = 0x1f,
5666 .pvt = true,
5667 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005668 .ptp_support = true,
5669 .ops = &mv88e6393x_ops,
5670 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04005671};
5672
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005673static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04005674{
Vivien Didelota439c062016-04-17 13:23:58 -04005675 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04005676
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005677 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5678 if (mv88e6xxx_table[i].prod_num == prod_num)
5679 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04005680
Vivien Didelotb9b37712015-10-30 19:39:48 -04005681 return NULL;
5682}
5683
Vivien Didelotfad09c72016-06-21 12:28:20 -04005684static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005685{
5686 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005687 unsigned int prod_num, rev;
5688 u16 id;
5689 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005690
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005691 mv88e6xxx_reg_lock(chip);
Vivien Didelot107fcc12017-06-12 12:37:36 -04005692 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005693 mv88e6xxx_reg_unlock(chip);
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005694 if (err)
5695 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005696
Vivien Didelot107fcc12017-06-12 12:37:36 -04005697 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5698 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005699
5700 info = mv88e6xxx_lookup_info(prod_num);
5701 if (!info)
5702 return -ENODEV;
5703
Vivien Didelotcaac8542016-06-20 13:14:09 -04005704 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04005705 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005706
Vivien Didelotfad09c72016-06-21 12:28:20 -04005707 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5708 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005709
5710 return 0;
5711}
5712
Vivien Didelotfad09c72016-06-21 12:28:20 -04005713static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04005714{
Vivien Didelotfad09c72016-06-21 12:28:20 -04005715 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005716
Vivien Didelotfad09c72016-06-21 12:28:20 -04005717 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5718 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04005719 return NULL;
5720
Vivien Didelotfad09c72016-06-21 12:28:20 -04005721 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04005722
Vivien Didelotfad09c72016-06-21 12:28:20 -04005723 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01005724 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelotda7dc872019-09-07 16:00:49 -04005725 idr_init(&chip->policies);
Vivien Didelot469d7292016-06-20 13:14:06 -04005726
Vivien Didelotfad09c72016-06-21 12:28:20 -04005727 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005728}
5729
Florian Fainelli5ed4e3e2017-11-10 15:22:52 -08005730static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
Florian Fainelli4d776482020-01-07 21:06:05 -08005731 int port,
5732 enum dsa_tag_protocol m)
Andrew Lunn7b314362016-08-22 16:01:01 +02005733{
Vivien Didelot04bed142016-08-31 18:06:13 -04005734 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02005735
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005736 return chip->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02005737}
5738
Tobias Waldekranz9a99bef2021-04-20 20:53:08 +02005739static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5740 enum dsa_tag_protocol proto)
5741{
5742 struct mv88e6xxx_chip *chip = ds->priv;
5743 enum dsa_tag_protocol old_protocol;
5744 int err;
5745
5746 switch (proto) {
5747 case DSA_TAG_PROTO_EDSA:
5748 switch (chip->info->edsa_support) {
5749 case MV88E6XXX_EDSA_UNSUPPORTED:
5750 return -EPROTONOSUPPORT;
5751 case MV88E6XXX_EDSA_UNDOCUMENTED:
5752 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5753 fallthrough;
5754 case MV88E6XXX_EDSA_SUPPORTED:
5755 break;
5756 }
5757 break;
5758 case DSA_TAG_PROTO_DSA:
5759 break;
5760 default:
5761 return -EPROTONOSUPPORT;
5762 }
5763
5764 old_protocol = chip->tag_protocol;
5765 chip->tag_protocol = proto;
5766
5767 mv88e6xxx_reg_lock(chip);
5768 err = mv88e6xxx_setup_port_mode(chip, port);
5769 mv88e6xxx_reg_unlock(chip);
5770
5771 if (err)
5772 chip->tag_protocol = old_protocol;
5773
5774 return err;
5775}
5776
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005777static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5778 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005779{
Vivien Didelot04bed142016-08-31 18:06:13 -04005780 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005781 int err;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005782
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005783 mv88e6xxx_reg_lock(chip);
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005784 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5785 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005786 mv88e6xxx_reg_unlock(chip);
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005787
5788 return err;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005789}
5790
5791static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5792 const struct switchdev_obj_port_mdb *mdb)
5793{
Vivien Didelot04bed142016-08-31 18:06:13 -04005794 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005795 int err;
5796
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005797 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04005798 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005799 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005800
5801 return err;
5802}
5803
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005804static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5805 struct dsa_mall_mirror_tc_entry *mirror,
5806 bool ingress)
5807{
5808 enum mv88e6xxx_egress_direction direction = ingress ?
5809 MV88E6XXX_EGRESS_DIR_INGRESS :
5810 MV88E6XXX_EGRESS_DIR_EGRESS;
5811 struct mv88e6xxx_chip *chip = ds->priv;
5812 bool other_mirrors = false;
5813 int i;
5814 int err;
5815
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005816 mutex_lock(&chip->reg_lock);
5817 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5818 mirror->to_local_port) {
5819 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5820 other_mirrors |= ingress ?
5821 chip->ports[i].mirror_ingress :
5822 chip->ports[i].mirror_egress;
5823
5824 /* Can't change egress port when other mirror is active */
5825 if (other_mirrors) {
5826 err = -EBUSY;
5827 goto out;
5828 }
5829
Marek Behún2fda45f2021-03-17 14:46:41 +01005830 err = mv88e6xxx_set_egress_port(chip, direction,
5831 mirror->to_local_port);
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005832 if (err)
5833 goto out;
5834 }
5835
5836 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5837out:
5838 mutex_unlock(&chip->reg_lock);
5839
5840 return err;
5841}
5842
5843static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5844 struct dsa_mall_mirror_tc_entry *mirror)
5845{
5846 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5847 MV88E6XXX_EGRESS_DIR_INGRESS :
5848 MV88E6XXX_EGRESS_DIR_EGRESS;
5849 struct mv88e6xxx_chip *chip = ds->priv;
5850 bool other_mirrors = false;
5851 int i;
5852
5853 mutex_lock(&chip->reg_lock);
5854 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5855 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5856
5857 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5858 other_mirrors |= mirror->ingress ?
5859 chip->ports[i].mirror_ingress :
5860 chip->ports[i].mirror_egress;
5861
5862 /* Reset egress port when no other mirror is active */
5863 if (!other_mirrors) {
Marek Behún2fda45f2021-03-17 14:46:41 +01005864 if (mv88e6xxx_set_egress_port(chip, direction,
5865 dsa_upstream_port(ds, port)))
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005866 dev_err(ds->dev, "failed to set egress port\n");
5867 }
5868
5869 mutex_unlock(&chip->reg_lock);
5870}
5871
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005872static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5873 struct switchdev_brport_flags flags,
5874 struct netlink_ext_ack *extack)
5875{
5876 struct mv88e6xxx_chip *chip = ds->priv;
5877 const struct mv88e6xxx_ops *ops;
5878
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01005879 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5880 BR_BCAST_FLOOD))
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005881 return -EINVAL;
5882
5883 ops = chip->info->ops;
5884
5885 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5886 return -EINVAL;
5887
5888 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5889 return -EINVAL;
5890
5891 return 0;
5892}
5893
5894static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5895 struct switchdev_brport_flags flags,
5896 struct netlink_ext_ack *extack)
Russell King4f859012019-02-20 15:35:05 -08005897{
5898 struct mv88e6xxx_chip *chip = ds->priv;
5899 int err = -EOPNOTSUPP;
5900
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005901 mv88e6xxx_reg_lock(chip);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005902
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005903 if (flags.mask & BR_LEARNING) {
5904 bool learning = !!(flags.val & BR_LEARNING);
5905 u16 pav = learning ? (1 << port) : 0;
5906
5907 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5908 if (err)
5909 goto out;
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005910 }
5911
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005912 if (flags.mask & BR_FLOOD) {
5913 bool unicast = !!(flags.val & BR_FLOOD);
5914
5915 err = chip->info->ops->port_set_ucast_flood(chip, port,
5916 unicast);
5917 if (err)
5918 goto out;
5919 }
5920
5921 if (flags.mask & BR_MCAST_FLOOD) {
5922 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5923
5924 err = chip->info->ops->port_set_mcast_flood(chip, port,
5925 multicast);
5926 if (err)
5927 goto out;
5928 }
5929
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01005930 if (flags.mask & BR_BCAST_FLOOD) {
5931 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5932
5933 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5934 if (err)
5935 goto out;
5936 }
5937
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005938out:
5939 mv88e6xxx_reg_unlock(chip);
5940
5941 return err;
5942}
5943
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005944static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5945 struct net_device *lag,
5946 struct netdev_lag_upper_info *info)
5947{
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01005948 struct mv88e6xxx_chip *chip = ds->priv;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005949 struct dsa_port *dp;
5950 int id, members = 0;
5951
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01005952 if (!mv88e6xxx_has_lag(chip))
5953 return false;
5954
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005955 id = dsa_lag_id(ds->dst, lag);
5956 if (id < 0 || id >= ds->num_lag_ids)
5957 return false;
5958
5959 dsa_lag_foreach_port(dp, ds->dst, lag)
5960 /* Includes the port joining the LAG */
5961 members++;
5962
5963 if (members > 8)
5964 return false;
5965
5966 /* We could potentially relax this to include active
5967 * backup in the future.
5968 */
5969 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5970 return false;
5971
5972 /* Ideally we would also validate that the hash type matches
5973 * the hardware. Alas, this is always set to unknown on team
5974 * interfaces.
5975 */
5976 return true;
5977}
5978
5979static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5980{
5981 struct mv88e6xxx_chip *chip = ds->priv;
5982 struct dsa_port *dp;
5983 u16 map = 0;
5984 int id;
5985
5986 id = dsa_lag_id(ds->dst, lag);
5987
5988 /* Build the map of all ports to distribute flows destined for
5989 * this LAG. This can be either a local user port, or a DSA
5990 * port if the LAG port is on a remote chip.
5991 */
5992 dsa_lag_foreach_port(dp, ds->dst, lag)
5993 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5994
5995 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5996}
5997
5998static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5999 /* Row number corresponds to the number of active members in a
6000 * LAG. Each column states which of the eight hash buckets are
6001 * mapped to the column:th port in the LAG.
6002 *
6003 * Example: In a LAG with three active ports, the second port
6004 * ([2][1]) would be selected for traffic mapped to buckets
6005 * 3,4,5 (0x38).
6006 */
6007 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6008 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6009 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6010 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6011 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6012 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6013 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6014 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6015};
6016
6017static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6018 int num_tx, int nth)
6019{
6020 u8 active = 0;
6021 int i;
6022
6023 num_tx = num_tx <= 8 ? num_tx : 8;
6024 if (nth < num_tx)
6025 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6026
6027 for (i = 0; i < 8; i++) {
6028 if (BIT(i) & active)
6029 mask[i] |= BIT(port);
6030 }
6031}
6032
6033static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6034{
6035 struct mv88e6xxx_chip *chip = ds->priv;
6036 unsigned int id, num_tx;
6037 struct net_device *lag;
6038 struct dsa_port *dp;
6039 int i, err, nth;
6040 u16 mask[8];
6041 u16 ivec;
6042
6043 /* Assume no port is a member of any LAG. */
6044 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6045
6046 /* Disable all masks for ports that _are_ members of a LAG. */
6047 list_for_each_entry(dp, &ds->dst->ports, list) {
6048 if (!dp->lag_dev || dp->ds != ds)
6049 continue;
6050
6051 ivec &= ~BIT(dp->index);
6052 }
6053
6054 for (i = 0; i < 8; i++)
6055 mask[i] = ivec;
6056
6057 /* Enable the correct subset of masks for all LAG ports that
6058 * are in the Tx set.
6059 */
6060 dsa_lags_foreach_id(id, ds->dst) {
6061 lag = dsa_lag_dev(ds->dst, id);
6062 if (!lag)
6063 continue;
6064
6065 num_tx = 0;
6066 dsa_lag_foreach_port(dp, ds->dst, lag) {
6067 if (dp->lag_tx_enabled)
6068 num_tx++;
6069 }
6070
6071 if (!num_tx)
6072 continue;
6073
6074 nth = 0;
6075 dsa_lag_foreach_port(dp, ds->dst, lag) {
6076 if (!dp->lag_tx_enabled)
6077 continue;
6078
6079 if (dp->ds == ds)
6080 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6081 num_tx, nth);
6082
6083 nth++;
6084 }
6085 }
6086
6087 for (i = 0; i < 8; i++) {
6088 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6089 if (err)
6090 return err;
6091 }
6092
6093 return 0;
6094}
6095
6096static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6097 struct net_device *lag)
6098{
6099 int err;
6100
6101 err = mv88e6xxx_lag_sync_masks(ds);
6102
6103 if (!err)
6104 err = mv88e6xxx_lag_sync_map(ds, lag);
6105
6106 return err;
6107}
6108
6109static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6110{
6111 struct mv88e6xxx_chip *chip = ds->priv;
6112 int err;
6113
6114 mv88e6xxx_reg_lock(chip);
6115 err = mv88e6xxx_lag_sync_masks(ds);
6116 mv88e6xxx_reg_unlock(chip);
6117 return err;
6118}
6119
6120static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6121 struct net_device *lag,
6122 struct netdev_lag_upper_info *info)
6123{
6124 struct mv88e6xxx_chip *chip = ds->priv;
6125 int err, id;
6126
6127 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6128 return -EOPNOTSUPP;
6129
6130 id = dsa_lag_id(ds->dst, lag);
6131
6132 mv88e6xxx_reg_lock(chip);
6133
6134 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6135 if (err)
6136 goto err_unlock;
6137
6138 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6139 if (err)
6140 goto err_clear_trunk;
6141
6142 mv88e6xxx_reg_unlock(chip);
6143 return 0;
6144
6145err_clear_trunk:
6146 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6147err_unlock:
6148 mv88e6xxx_reg_unlock(chip);
6149 return err;
6150}
6151
6152static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6153 struct net_device *lag)
6154{
6155 struct mv88e6xxx_chip *chip = ds->priv;
6156 int err_sync, err_trunk;
6157
6158 mv88e6xxx_reg_lock(chip);
6159 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6160 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6161 mv88e6xxx_reg_unlock(chip);
6162 return err_sync ? : err_trunk;
6163}
6164
6165static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6166 int port)
6167{
6168 struct mv88e6xxx_chip *chip = ds->priv;
6169 int err;
6170
6171 mv88e6xxx_reg_lock(chip);
6172 err = mv88e6xxx_lag_sync_masks(ds);
6173 mv88e6xxx_reg_unlock(chip);
6174 return err;
6175}
6176
6177static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6178 int port, struct net_device *lag,
6179 struct netdev_lag_upper_info *info)
6180{
6181 struct mv88e6xxx_chip *chip = ds->priv;
6182 int err;
6183
6184 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6185 return -EOPNOTSUPP;
6186
6187 mv88e6xxx_reg_lock(chip);
6188
6189 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6190 if (err)
6191 goto unlock;
6192
6193 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6194
6195unlock:
6196 mv88e6xxx_reg_unlock(chip);
6197 return err;
6198}
6199
6200static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6201 int port, struct net_device *lag)
6202{
6203 struct mv88e6xxx_chip *chip = ds->priv;
6204 int err_sync, err_pvt;
6205
6206 mv88e6xxx_reg_lock(chip);
6207 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6208 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6209 mv88e6xxx_reg_unlock(chip);
6210 return err_sync ? : err_pvt;
6211}
6212
Florian Fainellia82f67a2017-01-08 14:52:08 -08006213static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunn7b314362016-08-22 16:01:01 +02006214 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Tobias Waldekranz9a99bef2021-04-20 20:53:08 +02006215 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006216 .setup = mv88e6xxx_setup,
Andrew Lunn23e8b472019-10-25 01:03:52 +02006217 .teardown = mv88e6xxx_teardown,
Vladimir Olteanfd292c12021-09-17 17:29:16 +03006218 .port_setup = mv88e6xxx_port_setup,
6219 .port_teardown = mv88e6xxx_port_teardown,
Russell Kingc9a23562018-05-10 13:17:35 -07006220 .phylink_validate = mv88e6xxx_validate,
Russell Kinga5a68582020-03-14 10:15:43 +00006221 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
Russell Kingc9a23562018-05-10 13:17:35 -07006222 .phylink_mac_config = mv88e6xxx_mac_config,
Russell Kinga5a68582020-03-14 10:15:43 +00006223 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
Russell Kingc9a23562018-05-10 13:17:35 -07006224 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6225 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006226 .get_strings = mv88e6xxx_get_strings,
6227 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6228 .get_sset_count = mv88e6xxx_get_sset_count,
Andrew Lunn04aca992017-05-26 01:03:24 +02006229 .port_enable = mv88e6xxx_port_enable,
6230 .port_disable = mv88e6xxx_port_disable,
Andrew Lunn2a550ae2020-07-11 22:32:05 +02006231 .port_max_mtu = mv88e6xxx_get_max_mtu,
6232 .port_change_mtu = mv88e6xxx_change_mtu,
Vivien Didelot08f50062017-08-01 16:32:41 -04006233 .get_mac_eee = mv88e6xxx_get_mac_eee,
6234 .set_mac_eee = mv88e6xxx_set_mac_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006235 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006236 .get_eeprom = mv88e6xxx_get_eeprom,
6237 .set_eeprom = mv88e6xxx_set_eeprom,
6238 .get_regs_len = mv88e6xxx_get_regs_len,
6239 .get_regs = mv88e6xxx_get_regs,
Vivien Didelotda7dc872019-09-07 16:00:49 -04006240 .get_rxnfc = mv88e6xxx_get_rxnfc,
6241 .set_rxnfc = mv88e6xxx_set_rxnfc,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04006242 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006243 .port_bridge_join = mv88e6xxx_port_bridge_join,
6244 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02006245 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6246 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006247 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04006248 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006249 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006250 .port_vlan_add = mv88e6xxx_port_vlan_add,
6251 .port_vlan_del = mv88e6xxx_port_vlan_del,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006252 .port_fdb_add = mv88e6xxx_port_fdb_add,
6253 .port_fdb_del = mv88e6xxx_port_fdb_del,
6254 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04006255 .port_mdb_add = mv88e6xxx_port_mdb_add,
6256 .port_mdb_del = mv88e6xxx_port_mdb_del,
Iwan R Timmerf0942e02019-11-07 22:11:14 +01006257 .port_mirror_add = mv88e6xxx_port_mirror_add,
6258 .port_mirror_del = mv88e6xxx_port_mirror_del,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04006259 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6260 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006261 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6262 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6263 .port_txtstamp = mv88e6xxx_port_txtstamp,
6264 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6265 .get_ts_info = mv88e6xxx_get_ts_info,
Andrew Lunn23e8b472019-10-25 01:03:52 +02006266 .devlink_param_get = mv88e6xxx_devlink_param_get,
6267 .devlink_param_set = mv88e6xxx_devlink_param_set,
Andrew Lunn93157302020-09-18 21:11:09 +02006268 .devlink_info_get = mv88e6xxx_devlink_info_get,
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006269 .port_lag_change = mv88e6xxx_port_lag_change,
6270 .port_lag_join = mv88e6xxx_port_lag_join,
6271 .port_lag_leave = mv88e6xxx_port_lag_leave,
6272 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6273 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6274 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
Vladimir Olteance5df682021-07-22 18:55:41 +03006275 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload,
6276 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006277};
6278
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08006279static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006280{
Vivien Didelotfad09c72016-06-21 12:28:20 -04006281 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006282 struct dsa_switch *ds;
6283
Vivien Didelot7e99e342019-10-21 16:51:30 -04006284 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006285 if (!ds)
6286 return -ENOMEM;
6287
Vivien Didelot7e99e342019-10-21 16:51:30 -04006288 ds->dev = dev;
6289 ds->num_ports = mv88e6xxx_num_ports(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04006290 ds->priv = chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006291 ds->dev = dev;
Vivien Didelot9d490b42016-08-23 12:38:56 -04006292 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelot9ff74f22017-03-15 15:53:50 -04006293 ds->ageing_time_min = chip->info->age_time_coeff;
6294 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006295
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006296 /* Some chips support up to 32, but that requires enabling the
6297 * 5-bit port mode, which we do not support. 640k^W16 ought to
6298 * be enough for anyone.
6299 */
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01006300 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006301
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006302 dev_set_drvdata(dev, ds);
6303
Vivien Didelot23c9ee42017-05-26 18:12:51 -04006304 return dsa_register_switch(ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006305}
6306
Vivien Didelotfad09c72016-06-21 12:28:20 -04006307static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006308{
Vivien Didelotfad09c72016-06-21 12:28:20 -04006309 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006310}
6311
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006312static const void *pdata_device_get_match_data(struct device *dev)
6313{
6314 const struct of_device_id *matches = dev->driver->of_match_table;
6315 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6316
6317 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6318 matches++) {
6319 if (!strcmp(pdata->compatible, matches->compatible))
6320 return matches->data;
6321 }
6322 return NULL;
6323}
6324
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01006325/* There is no suspend to RAM support at DSA level yet, the switch configuration
6326 * would be lost after a power cycle so prevent it to be suspended.
6327 */
6328static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6329{
6330 return -EOPNOTSUPP;
6331}
6332
6333static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6334{
6335 return 0;
6336}
6337
6338static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6339
Vivien Didelot57d32312016-06-20 13:13:58 -04006340static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006341{
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006342 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
David S. Miller7ddae242018-05-20 19:04:24 -04006343 const struct mv88e6xxx_info *compat_info = NULL;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006344 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006345 struct device_node *np = dev->of_node;
Vivien Didelotfad09c72016-06-21 12:28:20 -04006346 struct mv88e6xxx_chip *chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006347 int port;
Andrew Lunn52638f72016-05-10 23:27:22 +02006348 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006349
Andrew Lunn7bb8c992018-05-31 00:15:42 +02006350 if (!np && !pdata)
6351 return -EINVAL;
6352
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006353 if (np)
6354 compat_info = of_device_get_match_data(dev);
6355
6356 if (pdata) {
6357 compat_info = pdata_device_get_match_data(dev);
6358
6359 if (!pdata->netdev)
6360 return -EINVAL;
6361
6362 for (port = 0; port < DSA_MAX_PORTS; port++) {
6363 if (!(pdata->enabled_ports & (1 << port)))
6364 continue;
6365 if (strcmp(pdata->cd.port_names[port], "cpu"))
6366 continue;
6367 pdata->cd.netdev[port] = &pdata->netdev->dev;
6368 break;
6369 }
6370 }
6371
Vivien Didelotcaac8542016-06-20 13:14:09 -04006372 if (!compat_info)
6373 return -EINVAL;
6374
Vivien Didelotfad09c72016-06-21 12:28:20 -04006375 chip = mv88e6xxx_alloc_chip(dev);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006376 if (!chip) {
6377 err = -ENOMEM;
6378 goto out;
6379 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006380
Vivien Didelotfad09c72016-06-21 12:28:20 -04006381 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04006382
Vivien Didelotfad09c72016-06-21 12:28:20 -04006383 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04006384 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006385 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006386
Andrew Lunnb4308f02016-11-21 23:26:55 +01006387 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006388 if (IS_ERR(chip->reset)) {
6389 err = PTR_ERR(chip->reset);
6390 goto out;
6391 }
Baruch Siach7b75e492019-06-27 21:17:39 +03006392 if (chip->reset)
6393 usleep_range(1000, 2000);
Andrew Lunnb4308f02016-11-21 23:26:55 +01006394
Vivien Didelotfad09c72016-06-21 12:28:20 -04006395 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04006396 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006397 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006398
Tobias Waldekranz670bb802021-04-20 20:53:07 +02006399 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6400 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6401 else
6402 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6403
Vivien Didelote57e5e72016-08-15 17:19:00 -04006404 mv88e6xxx_phy_init(chip);
6405
Andrew Lunn00baabe2018-05-19 22:31:35 +02006406 if (chip->info->ops->get_eeprom) {
6407 if (np)
6408 of_property_read_u32(np, "eeprom-length",
6409 &chip->eeprom_len);
6410 else
6411 chip->eeprom_len = pdata->eeprom_len;
6412 }
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006413
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006414 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006415 err = mv88e6xxx_switch_reset(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006416 mv88e6xxx_reg_unlock(chip);
Andrew Lunnb516d452016-06-04 21:17:06 +02006417 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02006418 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02006419
Andrew Lunna27415d2019-05-01 00:10:50 +02006420 if (np) {
6421 chip->irq = of_irq_get(np, 0);
6422 if (chip->irq == -EPROBE_DEFER) {
6423 err = chip->irq;
6424 goto out;
6425 }
Andrew Lunn83c0afa2016-06-04 21:17:07 +02006426 }
6427
Andrew Lunna27415d2019-05-01 00:10:50 +02006428 if (pdata)
6429 chip->irq = pdata->irq;
6430
Andrew Lunn294d7112018-02-22 22:58:32 +01006431 /* Has to be performed before the MDIO bus is created, because
Uwe Kleine-Königa7087672018-03-20 10:44:41 +01006432 * the PHYs will link their interrupts to these interrupt
Andrew Lunn294d7112018-02-22 22:58:32 +01006433 * controllers
6434 */
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006435 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006436 if (chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02006437 err = mv88e6xxx_g1_irq_setup(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006438 else
6439 err = mv88e6xxx_irq_poll_setup(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006440 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006441
Andrew Lunn294d7112018-02-22 22:58:32 +01006442 if (err)
6443 goto out;
6444
6445 if (chip->info->g2_irqs > 0) {
6446 err = mv88e6xxx_g2_irq_setup(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006447 if (err)
Andrew Lunn294d7112018-02-22 22:58:32 +01006448 goto out_g1_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02006449 }
6450
Andrew Lunn294d7112018-02-22 22:58:32 +01006451 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6452 if (err)
6453 goto out_g2_irq;
6454
6455 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6456 if (err)
6457 goto out_g1_atu_prob_irq;
6458
Andrew Lunna3c53be52017-01-24 14:53:50 +01006459 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02006460 if (err)
Andrew Lunn62eb1162018-01-14 02:32:45 +01006461 goto out_g1_vtu_prob_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02006462
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08006463 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006464 if (err)
6465 goto out_mdio;
6466
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006467 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02006468
6469out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01006470 mv88e6xxx_mdios_unregister(chip);
Andrew Lunn62eb1162018-01-14 02:32:45 +01006471out_g1_vtu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006472 mv88e6xxx_g1_vtu_prob_irq_free(chip);
Andrew Lunn09776442018-01-14 02:32:44 +01006473out_g1_atu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006474 mv88e6xxx_g1_atu_prob_irq_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006475out_g2_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006476 if (chip->info->g2_irqs > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02006477 mv88e6xxx_g2_irq_free(chip);
6478out_g1_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006479 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01006480 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006481 else
6482 mv88e6xxx_irq_poll_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006483out:
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006484 if (pdata)
6485 dev_put(pdata->netdev);
6486
Andrew Lunndc30c352016-10-16 19:56:49 +02006487 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006488}
6489
6490static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6491{
6492 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vladimir Oltean0650bf52021-09-17 16:34:33 +03006493 struct mv88e6xxx_chip *chip;
6494
6495 if (!ds)
6496 return;
6497
6498 chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006499
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006500 if (chip->info->ptp_support) {
6501 mv88e6xxx_hwtstamp_free(chip);
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01006502 mv88e6xxx_ptp_free(chip);
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006503 }
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01006504
Andrew Lunn930188c2016-08-22 16:01:03 +02006505 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04006506 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01006507 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006508
Andrew Lunn76f38f12018-03-17 20:21:09 +01006509 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6510 mv88e6xxx_g1_atu_prob_irq_free(chip);
6511
6512 if (chip->info->g2_irqs > 0)
6513 mv88e6xxx_g2_irq_free(chip);
6514
Andrew Lunn76f38f12018-03-17 20:21:09 +01006515 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01006516 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn76f38f12018-03-17 20:21:09 +01006517 else
6518 mv88e6xxx_irq_poll_free(chip);
Vladimir Oltean0650bf52021-09-17 16:34:33 +03006519
6520 dev_set_drvdata(&mdiodev->dev, NULL);
6521}
6522
6523static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
6524{
6525 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6526
6527 if (!ds)
6528 return;
6529
6530 dsa_switch_shutdown(ds);
6531
6532 dev_set_drvdata(&mdiodev->dev, NULL);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006533}
6534
6535static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04006536 {
6537 .compatible = "marvell,mv88e6085",
6538 .data = &mv88e6xxx_table[MV88E6085],
6539 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01006540 {
6541 .compatible = "marvell,mv88e6190",
6542 .data = &mv88e6xxx_table[MV88E6190],
6543 },
Rasmus Villemoes1f718362019-06-04 07:34:32 +00006544 {
6545 .compatible = "marvell,mv88e6250",
6546 .data = &mv88e6xxx_table[MV88E6250],
6547 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006548 { /* sentinel */ },
6549};
6550
6551MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6552
6553static struct mdio_driver mv88e6xxx_driver = {
6554 .probe = mv88e6xxx_probe,
6555 .remove = mv88e6xxx_remove,
Vladimir Oltean0650bf52021-09-17 16:34:33 +03006556 .shutdown = mv88e6xxx_shutdown,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006557 .mdiodrv.driver = {
6558 .name = "mv88e6085",
6559 .of_match_table = mv88e6xxx_of_match,
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01006560 .pm = &mv88e6xxx_pm_ops,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006561 },
6562};
6563
Andrew Lunn7324d502019-04-27 19:19:10 +02006564mdio_module_driver(mv88e6xxx_driver);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00006565
6566MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6567MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6568MODULE_LICENSE("GPL");