Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 2 | /* |
Vivien Didelot | 0d3cd4b | 2016-06-21 12:28:19 -0400 | [diff] [blame] | 3 | * Marvell 88e6xxx Ethernet switch single-chip support |
| 4 | * |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 5 | * Copyright (c) 2008 Marvell Semiconductor |
| 6 | * |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 7 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
| 8 | * |
Vivien Didelot | 4333d61 | 2017-03-28 15:10:36 -0400 | [diff] [blame] | 9 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
| 10 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
Vivien Didelot | 19fb7f6 | 2019-08-09 18:47:55 -0400 | [diff] [blame] | 13 | #include <linux/bitfield.h> |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 14 | #include <linux/delay.h> |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 15 | #include <linux/etherdevice.h> |
Andrew Lunn | dea8702 | 2015-08-31 15:56:47 +0200 | [diff] [blame] | 16 | #include <linux/ethtool.h> |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 17 | #include <linux/if_bridge.h> |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/irq.h> |
| 20 | #include <linux/irqdomain.h> |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 21 | #include <linux/jiffies.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 22 | #include <linux/list.h> |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 23 | #include <linux/mdio.h> |
Paul Gortmaker | 2bbba27 | 2012-01-24 10:41:40 +0000 | [diff] [blame] | 24 | #include <linux/module.h> |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 25 | #include <linux/of_device.h> |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 26 | #include <linux/of_irq.h> |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 27 | #include <linux/of_mdio.h> |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 28 | #include <linux/platform_data/mv88e6xxx.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 29 | #include <linux/netdevice.h> |
Andrew Lunn | c8c1b39a | 2015-11-20 03:56:24 +0100 | [diff] [blame] | 30 | #include <linux/gpio/consumer.h> |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 31 | #include <linux/phylink.h> |
Ben Hutchings | c8f0b86 | 2011-11-27 17:06:08 +0000 | [diff] [blame] | 32 | #include <net/dsa.h> |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 33 | |
Vivien Didelot | 4d5f2ba7 | 2017-06-02 17:06:15 -0400 | [diff] [blame] | 34 | #include "chip.h" |
Andrew Lunn | 9dd43aa | 2020-09-18 21:11:05 +0200 | [diff] [blame] | 35 | #include "devlink.h" |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 36 | #include "global1.h" |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 37 | #include "global2.h" |
Brandon Streiff | c6fe0ad | 2018-02-14 01:07:50 +0100 | [diff] [blame] | 38 | #include "hwtstamp.h" |
Andrew Lunn | 10fa5bf | 2017-05-26 01:03:20 +0200 | [diff] [blame] | 39 | #include "phy.h" |
Vivien Didelot | 18abed2 | 2016-11-04 03:23:26 +0100 | [diff] [blame] | 40 | #include "port.h" |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 41 | #include "ptp.h" |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 42 | #include "serdes.h" |
Vivien Didelot | e7ba0fa | 2019-05-03 19:28:22 -0400 | [diff] [blame] | 43 | #include "smi.h" |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 44 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 45 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 46 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 47 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
| 48 | dev_err(chip->dev, "Switch registers lock not held!\n"); |
Vivien Didelot | 3996a4f | 2015-10-30 18:56:45 -0400 | [diff] [blame] | 49 | dump_stack(); |
| 50 | } |
| 51 | } |
| 52 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 53 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 54 | { |
| 55 | int err; |
| 56 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 57 | assert_reg_lock(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 58 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 59 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 60 | if (err) |
| 61 | return err; |
| 62 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 63 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 64 | addr, reg, *val); |
| 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 69 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 70 | { |
| 71 | int err; |
| 72 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 73 | assert_reg_lock(chip); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 74 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 75 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 76 | if (err) |
| 77 | return err; |
| 78 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 79 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 80 | addr, reg, val); |
| 81 | |
| 82 | return 0; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Vivien Didelot | 683f224 | 2019-08-09 18:47:54 -0400 | [diff] [blame] | 85 | int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, |
| 86 | u16 mask, u16 val) |
| 87 | { |
| 88 | u16 data; |
| 89 | int err; |
| 90 | int i; |
| 91 | |
| 92 | /* There's no bus specific operation to wait for a mask */ |
| 93 | for (i = 0; i < 16; i++) { |
| 94 | err = mv88e6xxx_read(chip, addr, reg, &data); |
| 95 | if (err) |
| 96 | return err; |
| 97 | |
| 98 | if ((data & mask) == val) |
| 99 | return 0; |
| 100 | |
| 101 | usleep_range(1000, 2000); |
| 102 | } |
| 103 | |
| 104 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
| 105 | return -ETIMEDOUT; |
| 106 | } |
| 107 | |
Vivien Didelot | 19fb7f6 | 2019-08-09 18:47:55 -0400 | [diff] [blame] | 108 | int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, |
| 109 | int bit, int val) |
| 110 | { |
| 111 | return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), |
| 112 | val ? BIT(bit) : 0x0000); |
| 113 | } |
| 114 | |
Andrew Lunn | 10fa5bf | 2017-05-26 01:03:20 +0200 | [diff] [blame] | 115 | struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 116 | { |
| 117 | struct mv88e6xxx_mdio_bus *mdio_bus; |
| 118 | |
| 119 | mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, |
| 120 | list); |
| 121 | if (!mdio_bus) |
| 122 | return NULL; |
| 123 | |
| 124 | return mdio_bus->bus; |
| 125 | } |
| 126 | |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 127 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
| 128 | { |
| 129 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
| 130 | unsigned int n = d->hwirq; |
| 131 | |
| 132 | chip->g1_irq.masked |= (1 << n); |
| 133 | } |
| 134 | |
| 135 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) |
| 136 | { |
| 137 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
| 138 | unsigned int n = d->hwirq; |
| 139 | |
| 140 | chip->g1_irq.masked &= ~(1 << n); |
| 141 | } |
| 142 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 143 | static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 144 | { |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 145 | unsigned int nhandled = 0; |
| 146 | unsigned int sub_irq; |
| 147 | unsigned int n; |
| 148 | u16 reg; |
John David Anglin | 7c0db24 | 2019-02-11 13:40:21 -0500 | [diff] [blame] | 149 | u16 ctl1; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 150 | int err; |
| 151 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 152 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 8246692 | 2017-06-15 12:13:59 -0400 | [diff] [blame] | 153 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 154 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 155 | |
| 156 | if (err) |
| 157 | goto out; |
| 158 | |
John David Anglin | 7c0db24 | 2019-02-11 13:40:21 -0500 | [diff] [blame] | 159 | do { |
| 160 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { |
| 161 | if (reg & (1 << n)) { |
| 162 | sub_irq = irq_find_mapping(chip->g1_irq.domain, |
| 163 | n); |
| 164 | handle_nested_irq(sub_irq); |
| 165 | ++nhandled; |
| 166 | } |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 167 | } |
John David Anglin | 7c0db24 | 2019-02-11 13:40:21 -0500 | [diff] [blame] | 168 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 169 | mv88e6xxx_reg_lock(chip); |
John David Anglin | 7c0db24 | 2019-02-11 13:40:21 -0500 | [diff] [blame] | 170 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); |
| 171 | if (err) |
| 172 | goto unlock; |
| 173 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
| 174 | unlock: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 175 | mv88e6xxx_reg_unlock(chip); |
John David Anglin | 7c0db24 | 2019-02-11 13:40:21 -0500 | [diff] [blame] | 176 | if (err) |
| 177 | goto out; |
| 178 | ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); |
| 179 | } while (reg & ctl1); |
| 180 | |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 181 | out: |
| 182 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); |
| 183 | } |
| 184 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 185 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) |
| 186 | { |
| 187 | struct mv88e6xxx_chip *chip = dev_id; |
| 188 | |
| 189 | return mv88e6xxx_g1_irq_thread_work(chip); |
| 190 | } |
| 191 | |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 192 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) |
| 193 | { |
| 194 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
| 195 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 196 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) |
| 200 | { |
| 201 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
| 202 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); |
| 203 | u16 reg; |
| 204 | int err; |
| 205 | |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 206 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 207 | if (err) |
| 208 | goto out; |
| 209 | |
| 210 | reg &= ~mask; |
| 211 | reg |= (~chip->g1_irq.masked & mask); |
| 212 | |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 213 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 214 | if (err) |
| 215 | goto out; |
| 216 | |
| 217 | out: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 218 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 219 | } |
| 220 | |
Bhumika Goyal | 6eb15e2 | 2017-08-19 16:25:52 +0530 | [diff] [blame] | 221 | static const struct irq_chip mv88e6xxx_g1_irq_chip = { |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 222 | .name = "mv88e6xxx-g1", |
| 223 | .irq_mask = mv88e6xxx_g1_irq_mask, |
| 224 | .irq_unmask = mv88e6xxx_g1_irq_unmask, |
| 225 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, |
| 226 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, |
| 227 | }; |
| 228 | |
| 229 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, |
| 230 | unsigned int irq, |
| 231 | irq_hw_number_t hwirq) |
| 232 | { |
| 233 | struct mv88e6xxx_chip *chip = d->host_data; |
| 234 | |
| 235 | irq_set_chip_data(irq, d->host_data); |
| 236 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); |
| 237 | irq_set_noprobe(irq); |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { |
| 243 | .map = mv88e6xxx_g1_irq_domain_map, |
| 244 | .xlate = irq_domain_xlate_twocell, |
| 245 | }; |
| 246 | |
Uwe Kleine-König | 3d82475 | 2018-07-20 11:53:15 +0200 | [diff] [blame] | 247 | /* To be called with reg_lock held */ |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 248 | static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 249 | { |
| 250 | int irq, virq; |
Andrew Lunn | 3460a57 | 2016-11-20 20:14:16 +0100 | [diff] [blame] | 251 | u16 mask; |
| 252 | |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 253 | mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); |
Andrew Lunn | 3d5fdba | 2017-12-07 01:05:56 +0100 | [diff] [blame] | 254 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 255 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
Andrew Lunn | 3460a57 | 2016-11-20 20:14:16 +0100 | [diff] [blame] | 256 | |
Andreas Färber | 5edef2f | 2016-11-27 23:26:28 +0100 | [diff] [blame] | 257 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { |
Andrew Lunn | a3db3d3 | 2016-11-20 20:14:14 +0100 | [diff] [blame] | 258 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 259 | irq_dispose_mapping(virq); |
| 260 | } |
| 261 | |
Andrew Lunn | a3db3d3 | 2016-11-20 20:14:14 +0100 | [diff] [blame] | 262 | irq_domain_remove(chip->g1_irq.domain); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 263 | } |
| 264 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 265 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) |
| 266 | { |
Uwe Kleine-König | 3d82475 | 2018-07-20 11:53:15 +0200 | [diff] [blame] | 267 | /* |
| 268 | * free_irq must be called without reg_lock taken because the irq |
| 269 | * handler takes this lock, too. |
| 270 | */ |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 271 | free_irq(chip->irq, chip); |
Uwe Kleine-König | 3d82475 | 2018-07-20 11:53:15 +0200 | [diff] [blame] | 272 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 273 | mv88e6xxx_reg_lock(chip); |
Uwe Kleine-König | 3d82475 | 2018-07-20 11:53:15 +0200 | [diff] [blame] | 274 | mv88e6xxx_g1_irq_free_common(chip); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 275 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 279 | { |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 280 | int err, irq, virq; |
| 281 | u16 reg, mask; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 282 | |
| 283 | chip->g1_irq.nirqs = chip->info->g1_irqs; |
| 284 | chip->g1_irq.domain = irq_domain_add_simple( |
| 285 | NULL, chip->g1_irq.nirqs, 0, |
| 286 | &mv88e6xxx_g1_irq_domain_ops, chip); |
| 287 | if (!chip->g1_irq.domain) |
| 288 | return -ENOMEM; |
| 289 | |
| 290 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) |
| 291 | irq_create_mapping(chip->g1_irq.domain, irq); |
| 292 | |
| 293 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; |
| 294 | chip->g1_irq.masked = ~0; |
| 295 | |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 296 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 297 | if (err) |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 298 | goto out_mapping; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 299 | |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 300 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 301 | |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 302 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 303 | if (err) |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 304 | goto out_disable; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 305 | |
| 306 | /* Reading the interrupt status clears (most of) them */ |
Vivien Didelot | 8246692 | 2017-06-15 12:13:59 -0400 | [diff] [blame] | 307 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 308 | if (err) |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 309 | goto out_disable; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 310 | |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 311 | return 0; |
| 312 | |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 313 | out_disable: |
Andrew Lunn | 3d5fdba | 2017-12-07 01:05:56 +0100 | [diff] [blame] | 314 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
Vivien Didelot | d77f432 | 2017-06-15 12:14:03 -0400 | [diff] [blame] | 315 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
Andrew Lunn | 3dd0ef0 | 2016-11-20 20:14:17 +0100 | [diff] [blame] | 316 | |
| 317 | out_mapping: |
| 318 | for (irq = 0; irq < 16; irq++) { |
| 319 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
| 320 | irq_dispose_mapping(virq); |
| 321 | } |
| 322 | |
| 323 | irq_domain_remove(chip->g1_irq.domain); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 324 | |
| 325 | return err; |
| 326 | } |
| 327 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 328 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) |
| 329 | { |
Andrew Lunn | f6d9758 | 2019-02-23 17:43:56 +0100 | [diff] [blame] | 330 | static struct lock_class_key lock_key; |
| 331 | static struct lock_class_key request_key; |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 332 | int err; |
| 333 | |
| 334 | err = mv88e6xxx_g1_irq_setup_common(chip); |
| 335 | if (err) |
| 336 | return err; |
| 337 | |
Andrew Lunn | f6d9758 | 2019-02-23 17:43:56 +0100 | [diff] [blame] | 338 | /* These lock classes tells lockdep that global 1 irqs are in |
| 339 | * a different category than their parent GPIO, so it won't |
| 340 | * report false recursion. |
| 341 | */ |
| 342 | irq_set_lockdep_class(chip->irq, &lock_key, &request_key); |
| 343 | |
Andrew Lunn | 3095383 | 2020-01-06 17:13:48 +0100 | [diff] [blame] | 344 | snprintf(chip->irq_name, sizeof(chip->irq_name), |
| 345 | "mv88e6xxx-%s", dev_name(chip->dev)); |
| 346 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 347 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 348 | err = request_threaded_irq(chip->irq, NULL, |
| 349 | mv88e6xxx_g1_irq_thread_fn, |
Marek Behún | 0340376 | 2018-08-30 02:13:50 +0200 | [diff] [blame] | 350 | IRQF_ONESHOT | IRQF_SHARED, |
Andrew Lunn | 3095383 | 2020-01-06 17:13:48 +0100 | [diff] [blame] | 351 | chip->irq_name, chip); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 352 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 353 | if (err) |
| 354 | mv88e6xxx_g1_irq_free_common(chip); |
| 355 | |
| 356 | return err; |
| 357 | } |
| 358 | |
| 359 | static void mv88e6xxx_irq_poll(struct kthread_work *work) |
| 360 | { |
| 361 | struct mv88e6xxx_chip *chip = container_of(work, |
| 362 | struct mv88e6xxx_chip, |
| 363 | irq_poll_work.work); |
| 364 | mv88e6xxx_g1_irq_thread_work(chip); |
| 365 | |
| 366 | kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, |
| 367 | msecs_to_jiffies(100)); |
| 368 | } |
| 369 | |
| 370 | static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) |
| 371 | { |
| 372 | int err; |
| 373 | |
| 374 | err = mv88e6xxx_g1_irq_setup_common(chip); |
| 375 | if (err) |
| 376 | return err; |
| 377 | |
| 378 | kthread_init_delayed_work(&chip->irq_poll_work, |
| 379 | mv88e6xxx_irq_poll); |
| 380 | |
Florian Fainelli | 3f8b869 | 2019-02-21 20:09:27 -0800 | [diff] [blame] | 381 | chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 382 | if (IS_ERR(chip->kworker)) |
| 383 | return PTR_ERR(chip->kworker); |
| 384 | |
| 385 | kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, |
| 386 | msecs_to_jiffies(100)); |
| 387 | |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) |
| 392 | { |
| 393 | kthread_cancel_delayed_work_sync(&chip->irq_poll_work); |
| 394 | kthread_destroy_worker(chip->kworker); |
Uwe Kleine-König | 3d82475 | 2018-07-20 11:53:15 +0200 | [diff] [blame] | 395 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 396 | mv88e6xxx_reg_lock(chip); |
Uwe Kleine-König | 3d82475 | 2018-07-20 11:53:15 +0200 | [diff] [blame] | 397 | mv88e6xxx_g1_irq_free_common(chip); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 398 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 399 | } |
| 400 | |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 401 | static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, |
| 402 | int port, phy_interface_t interface) |
| 403 | { |
| 404 | int err; |
| 405 | |
| 406 | if (chip->info->ops->port_set_rgmii_delay) { |
| 407 | err = chip->info->ops->port_set_rgmii_delay(chip, port, |
| 408 | interface); |
| 409 | if (err && err != -EOPNOTSUPP) |
| 410 | return err; |
| 411 | } |
| 412 | |
| 413 | if (chip->info->ops->port_set_cmode) { |
| 414 | err = chip->info->ops->port_set_cmode(chip, port, |
| 415 | interface); |
| 416 | if (err && err != -EOPNOTSUPP) |
| 417 | return err; |
| 418 | } |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 423 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
| 424 | int link, int speed, int duplex, int pause, |
| 425 | phy_interface_t mode) |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 426 | { |
| 427 | int err; |
| 428 | |
| 429 | if (!chip->info->ops->port_set_link) |
| 430 | return 0; |
| 431 | |
| 432 | /* Port's MAC control must not be changed unless the link is down */ |
Hubert Feurstein | 43c8e0a | 2019-07-30 12:11:42 +0200 | [diff] [blame] | 433 | err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 434 | if (err) |
| 435 | return err; |
| 436 | |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 437 | if (chip->info->ops->port_set_speed_duplex) { |
| 438 | err = chip->info->ops->port_set_speed_duplex(chip, port, |
| 439 | speed, duplex); |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 440 | if (err && err != -EOPNOTSUPP) |
| 441 | goto restore_link; |
| 442 | } |
| 443 | |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 444 | if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) |
| 445 | mode = chip->info->ops->port_max_speed_mode(port); |
| 446 | |
Andrew Lunn | 54186b9 | 2018-08-09 15:38:37 +0200 | [diff] [blame] | 447 | if (chip->info->ops->port_set_pause) { |
| 448 | err = chip->info->ops->port_set_pause(chip, port, pause); |
| 449 | if (err) |
| 450 | goto restore_link; |
| 451 | } |
| 452 | |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 453 | err = mv88e6xxx_port_config_interface(chip, port, mode); |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 454 | restore_link: |
| 455 | if (chip->info->ops->port_set_link(chip, port, link)) |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 456 | dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 457 | |
| 458 | return err; |
| 459 | } |
| 460 | |
Marek Vasut | d700ec4 | 2018-09-12 00:15:24 +0200 | [diff] [blame] | 461 | static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) |
| 462 | { |
| 463 | struct mv88e6xxx_chip *chip = ds->priv; |
| 464 | |
| 465 | return port < chip->info->num_internal_phys; |
| 466 | } |
| 467 | |
Russell King | 5d5b231 | 2020-03-14 10:16:03 +0000 | [diff] [blame] | 468 | static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) |
| 469 | { |
| 470 | u16 reg; |
| 471 | int err; |
| 472 | |
| 473 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); |
| 474 | if (err) { |
| 475 | dev_err(chip->dev, |
| 476 | "p%d: %s: failed to read port status\n", |
| 477 | port, __func__); |
| 478 | return err; |
| 479 | } |
| 480 | |
| 481 | return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); |
| 482 | } |
| 483 | |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 484 | static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, |
| 485 | struct phylink_link_state *state) |
| 486 | { |
| 487 | struct mv88e6xxx_chip *chip = ds->priv; |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 488 | int lane; |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 489 | int err; |
| 490 | |
| 491 | mv88e6xxx_reg_lock(chip); |
| 492 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 493 | if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 494 | err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, |
| 495 | state); |
| 496 | else |
| 497 | err = -EOPNOTSUPP; |
| 498 | mv88e6xxx_reg_unlock(chip); |
| 499 | |
| 500 | return err; |
| 501 | } |
| 502 | |
| 503 | static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, |
| 504 | unsigned int mode, |
| 505 | phy_interface_t interface, |
| 506 | const unsigned long *advertise) |
| 507 | { |
| 508 | const struct mv88e6xxx_ops *ops = chip->info->ops; |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 509 | int lane; |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 510 | |
| 511 | if (ops->serdes_pcs_config) { |
| 512 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 513 | if (lane >= 0) |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 514 | return ops->serdes_pcs_config(chip, port, lane, mode, |
| 515 | interface, advertise); |
| 516 | } |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) |
| 522 | { |
| 523 | struct mv88e6xxx_chip *chip = ds->priv; |
| 524 | const struct mv88e6xxx_ops *ops; |
| 525 | int err = 0; |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 526 | int lane; |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 527 | |
| 528 | ops = chip->info->ops; |
| 529 | |
| 530 | if (ops->serdes_pcs_an_restart) { |
| 531 | mv88e6xxx_reg_lock(chip); |
| 532 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 533 | if (lane >= 0) |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 534 | err = ops->serdes_pcs_an_restart(chip, port, lane); |
| 535 | mv88e6xxx_reg_unlock(chip); |
| 536 | |
| 537 | if (err) |
| 538 | dev_err(ds->dev, "p%d: failed to restart AN\n", port); |
| 539 | } |
| 540 | } |
| 541 | |
| 542 | static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, |
| 543 | unsigned int mode, |
| 544 | int speed, int duplex) |
| 545 | { |
| 546 | const struct mv88e6xxx_ops *ops = chip->info->ops; |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 547 | int lane; |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 548 | |
| 549 | if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { |
| 550 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 551 | if (lane >= 0) |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 552 | return ops->serdes_pcs_link_up(chip, port, lane, |
| 553 | speed, duplex); |
| 554 | } |
| 555 | |
| 556 | return 0; |
| 557 | } |
| 558 | |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 559 | static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 560 | unsigned long *mask, |
| 561 | struct phylink_link_state *state) |
| 562 | { |
| 563 | if (!phy_interface_mode_is_8023z(state->interface)) { |
| 564 | /* 10M and 100M are only supported in non-802.3z mode */ |
| 565 | phylink_set(mask, 10baseT_Half); |
| 566 | phylink_set(mask, 10baseT_Full); |
| 567 | phylink_set(mask, 100baseT_Half); |
| 568 | phylink_set(mask, 100baseT_Full); |
| 569 | } |
| 570 | } |
| 571 | |
| 572 | static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 573 | unsigned long *mask, |
| 574 | struct phylink_link_state *state) |
| 575 | { |
| 576 | /* FIXME: if the port is in 1000Base-X mode, then it only supports |
| 577 | * 1000M FD speeds. In this case, CMODE will indicate 5. |
| 578 | */ |
| 579 | phylink_set(mask, 1000baseT_Full); |
| 580 | phylink_set(mask, 1000baseX_Full); |
| 581 | |
| 582 | mv88e6065_phylink_validate(chip, port, mask, state); |
| 583 | } |
| 584 | |
Marek Behún | e3af71a | 2019-02-25 12:39:55 +0100 | [diff] [blame] | 585 | static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 586 | unsigned long *mask, |
| 587 | struct phylink_link_state *state) |
| 588 | { |
| 589 | if (port >= 5) |
| 590 | phylink_set(mask, 2500baseX_Full); |
| 591 | |
| 592 | /* No ethtool bits for 200Mbps */ |
| 593 | phylink_set(mask, 1000baseT_Full); |
| 594 | phylink_set(mask, 1000baseX_Full); |
| 595 | |
| 596 | mv88e6065_phylink_validate(chip, port, mask, state); |
| 597 | } |
| 598 | |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 599 | static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 600 | unsigned long *mask, |
| 601 | struct phylink_link_state *state) |
| 602 | { |
| 603 | /* No ethtool bits for 200Mbps */ |
| 604 | phylink_set(mask, 1000baseT_Full); |
| 605 | phylink_set(mask, 1000baseX_Full); |
| 606 | |
| 607 | mv88e6065_phylink_validate(chip, port, mask, state); |
| 608 | } |
| 609 | |
| 610 | static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 611 | unsigned long *mask, |
| 612 | struct phylink_link_state *state) |
| 613 | { |
Andrew Lunn | ec26016 | 2019-02-08 22:25:44 +0100 | [diff] [blame] | 614 | if (port >= 9) { |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 615 | phylink_set(mask, 2500baseX_Full); |
Andrew Lunn | ec26016 | 2019-02-08 22:25:44 +0100 | [diff] [blame] | 616 | phylink_set(mask, 2500baseT_Full); |
| 617 | } |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 618 | |
| 619 | /* No ethtool bits for 200Mbps */ |
| 620 | phylink_set(mask, 1000baseT_Full); |
| 621 | phylink_set(mask, 1000baseX_Full); |
| 622 | |
| 623 | mv88e6065_phylink_validate(chip, port, mask, state); |
| 624 | } |
| 625 | |
| 626 | static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 627 | unsigned long *mask, |
| 628 | struct phylink_link_state *state) |
| 629 | { |
| 630 | if (port >= 9) { |
| 631 | phylink_set(mask, 10000baseT_Full); |
| 632 | phylink_set(mask, 10000baseKR_Full); |
| 633 | } |
| 634 | |
| 635 | mv88e6390_phylink_validate(chip, port, mask, state); |
| 636 | } |
| 637 | |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 638 | static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
| 639 | unsigned long *mask, |
| 640 | struct phylink_link_state *state) |
| 641 | { |
| 642 | if (port == 0 || port == 9 || port == 10) { |
| 643 | phylink_set(mask, 10000baseT_Full); |
| 644 | phylink_set(mask, 10000baseKR_Full); |
| 645 | phylink_set(mask, 10000baseCR_Full); |
| 646 | phylink_set(mask, 10000baseSR_Full); |
| 647 | phylink_set(mask, 10000baseLR_Full); |
| 648 | phylink_set(mask, 10000baseLRM_Full); |
| 649 | phylink_set(mask, 10000baseER_Full); |
| 650 | phylink_set(mask, 5000baseT_Full); |
| 651 | phylink_set(mask, 2500baseX_Full); |
| 652 | phylink_set(mask, 2500baseT_Full); |
| 653 | } |
| 654 | |
| 655 | phylink_set(mask, 1000baseT_Full); |
| 656 | phylink_set(mask, 1000baseX_Full); |
| 657 | |
| 658 | mv88e6065_phylink_validate(chip, port, mask, state); |
| 659 | } |
| 660 | |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 661 | static void mv88e6xxx_validate(struct dsa_switch *ds, int port, |
| 662 | unsigned long *supported, |
| 663 | struct phylink_link_state *state) |
| 664 | { |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 665 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
| 666 | struct mv88e6xxx_chip *chip = ds->priv; |
| 667 | |
| 668 | /* Allow all the expected bits */ |
| 669 | phylink_set(mask, Autoneg); |
| 670 | phylink_set(mask, Pause); |
| 671 | phylink_set_port_modes(mask); |
| 672 | |
| 673 | if (chip->info->ops->phylink_validate) |
| 674 | chip->info->ops->phylink_validate(chip, port, mask, state); |
| 675 | |
| 676 | bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); |
| 677 | bitmap_and(state->advertising, state->advertising, mask, |
| 678 | __ETHTOOL_LINK_MODE_MASK_NBITS); |
| 679 | |
| 680 | /* We can only operate at 2500BaseX or 1000BaseX. If requested |
| 681 | * to advertise both, only report advertising at 2500BaseX. |
| 682 | */ |
| 683 | phylink_helper_basex_speed(state); |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 684 | } |
| 685 | |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 686 | static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, |
| 687 | unsigned int mode, |
| 688 | const struct phylink_link_state *state) |
| 689 | { |
| 690 | struct mv88e6xxx_chip *chip = ds->priv; |
Russell King | fad5819 | 2020-07-19 12:00:35 +0100 | [diff] [blame] | 691 | struct mv88e6xxx_port *p; |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 692 | int err; |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 693 | |
Russell King | fad5819 | 2020-07-19 12:00:35 +0100 | [diff] [blame] | 694 | p = &chip->ports[port]; |
| 695 | |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 696 | /* FIXME: is this the correct test? If we're in fixed mode on an |
| 697 | * internal port, why should we process this any different from |
| 698 | * PHY mode? On the other hand, the port may be automedia between |
| 699 | * an internal PHY and the serdes... |
| 700 | */ |
Marek Vasut | d700ec4 | 2018-09-12 00:15:24 +0200 | [diff] [blame] | 701 | if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 702 | return; |
| 703 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 704 | mv88e6xxx_reg_lock(chip); |
Russell King | fad5819 | 2020-07-19 12:00:35 +0100 | [diff] [blame] | 705 | /* In inband mode, the link may come up at any time while the link |
| 706 | * is not forced down. Force the link down while we reconfigure the |
| 707 | * interface mode. |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 708 | */ |
Russell King | fad5819 | 2020-07-19 12:00:35 +0100 | [diff] [blame] | 709 | if (mode == MLO_AN_INBAND && p->interface != state->interface && |
| 710 | chip->info->ops->port_set_link) |
| 711 | chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); |
| 712 | |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 713 | err = mv88e6xxx_port_config_interface(chip, port, state->interface); |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 714 | if (err && err != -EOPNOTSUPP) |
| 715 | goto err_unlock; |
| 716 | |
| 717 | err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, |
| 718 | state->advertising); |
| 719 | /* FIXME: we should restart negotiation if something changed - which |
| 720 | * is something we get if we convert to using phylinks PCS operations. |
| 721 | */ |
| 722 | if (err > 0) |
| 723 | err = 0; |
| 724 | |
Russell King | fad5819 | 2020-07-19 12:00:35 +0100 | [diff] [blame] | 725 | /* Undo the forced down state above after completing configuration |
| 726 | * irrespective of its state on entry, which allows the link to come up. |
| 727 | */ |
| 728 | if (mode == MLO_AN_INBAND && p->interface != state->interface && |
| 729 | chip->info->ops->port_set_link) |
| 730 | chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); |
| 731 | |
| 732 | p->interface = state->interface; |
| 733 | |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 734 | err_unlock: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 735 | mv88e6xxx_reg_unlock(chip); |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 736 | |
| 737 | if (err && err != -EOPNOTSUPP) |
Russell King | 64d47d5 | 2020-03-14 10:15:38 +0000 | [diff] [blame] | 738 | dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 739 | } |
| 740 | |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 741 | static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, |
| 742 | unsigned int mode, |
| 743 | phy_interface_t interface) |
| 744 | { |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 745 | struct mv88e6xxx_chip *chip = ds->priv; |
| 746 | const struct mv88e6xxx_ops *ops; |
| 747 | int err = 0; |
| 748 | |
| 749 | ops = chip->info->ops; |
| 750 | |
Russell King | 5d5b231 | 2020-03-14 10:16:03 +0000 | [diff] [blame] | 751 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | 34b5e6a | 2020-04-14 02:34:38 +0200 | [diff] [blame] | 752 | if ((!mv88e6xxx_port_ppu_updates(chip, port) || |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 753 | mode == MLO_AN_FIXED) && ops->port_sync_link) |
| 754 | err = ops->port_sync_link(chip, port, mode, false); |
Russell King | 5d5b231 | 2020-03-14 10:16:03 +0000 | [diff] [blame] | 755 | mv88e6xxx_reg_unlock(chip); |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 756 | |
Russell King | 5d5b231 | 2020-03-14 10:16:03 +0000 | [diff] [blame] | 757 | if (err) |
| 758 | dev_err(chip->dev, |
| 759 | "p%d: failed to force MAC link down\n", port); |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, |
| 763 | unsigned int mode, phy_interface_t interface, |
Russell King | 5b502a7 | 2020-02-26 10:23:46 +0000 | [diff] [blame] | 764 | struct phy_device *phydev, |
| 765 | int speed, int duplex, |
| 766 | bool tx_pause, bool rx_pause) |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 767 | { |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 768 | struct mv88e6xxx_chip *chip = ds->priv; |
| 769 | const struct mv88e6xxx_ops *ops; |
| 770 | int err = 0; |
| 771 | |
| 772 | ops = chip->info->ops; |
| 773 | |
Russell King | 5d5b231 | 2020-03-14 10:16:03 +0000 | [diff] [blame] | 774 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | 34b5e6a | 2020-04-14 02:34:38 +0200 | [diff] [blame] | 775 | if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 776 | /* FIXME: for an automedia port, should we force the link |
| 777 | * down here - what if the link comes up due to "other" media |
| 778 | * while we're bringing the port up, how is the exclusivity |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 779 | * handled in the Marvell hardware? E.g. port 2 on 88E6390 |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 780 | * shared between internal PHY and Serdes. |
| 781 | */ |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 782 | err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, |
| 783 | duplex); |
| 784 | if (err) |
| 785 | goto error; |
| 786 | |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 787 | if (ops->port_set_speed_duplex) { |
| 788 | err = ops->port_set_speed_duplex(chip, port, |
| 789 | speed, duplex); |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 790 | if (err && err != -EOPNOTSUPP) |
| 791 | goto error; |
| 792 | } |
| 793 | |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 794 | if (ops->port_sync_link) |
| 795 | err = ops->port_sync_link(chip, port, mode, true); |
Russell King | 30c4a5b | 2020-02-26 10:23:51 +0000 | [diff] [blame] | 796 | } |
Russell King | 5d5b231 | 2020-03-14 10:16:03 +0000 | [diff] [blame] | 797 | error: |
| 798 | mv88e6xxx_reg_unlock(chip); |
| 799 | |
| 800 | if (err && err != -EOPNOTSUPP) |
| 801 | dev_err(ds->dev, |
| 802 | "p%d: failed to configure MAC link up\n", port); |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 803 | } |
| 804 | |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 805 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 806 | { |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 807 | if (!chip->info->ops->stats_snapshot) |
| 808 | return -EOPNOTSUPP; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 809 | |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 810 | return chip->info->ops->stats_snapshot(chip, port); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 811 | } |
| 812 | |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 813 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 814 | { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, |
| 815 | { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, |
| 816 | { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, |
| 817 | { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, |
| 818 | { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, |
| 819 | { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, |
| 820 | { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, |
| 821 | { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, |
| 822 | { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, |
| 823 | { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, |
| 824 | { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, |
| 825 | { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, |
| 826 | { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, |
| 827 | { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, |
| 828 | { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, |
| 829 | { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, |
| 830 | { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, |
| 831 | { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, |
| 832 | { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, |
| 833 | { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, |
| 834 | { "single", 4, 0x14, STATS_TYPE_BANK0, }, |
| 835 | { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, |
| 836 | { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, |
| 837 | { "late", 4, 0x1f, STATS_TYPE_BANK0, }, |
| 838 | { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, |
| 839 | { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, |
| 840 | { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, |
| 841 | { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, |
| 842 | { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, |
| 843 | { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, |
| 844 | { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, |
| 845 | { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, |
| 846 | { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, |
| 847 | { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, |
| 848 | { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, |
| 849 | { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, |
| 850 | { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, |
| 851 | { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, |
| 852 | { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, |
| 853 | { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, |
| 854 | { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, |
| 855 | { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, |
| 856 | { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, |
| 857 | { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, |
| 858 | { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, |
| 859 | { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, |
| 860 | { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, |
| 861 | { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, |
| 862 | { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, |
| 863 | { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, |
| 864 | { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, |
| 865 | { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, |
| 866 | { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, |
| 867 | { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, |
| 868 | { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, |
| 869 | { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, |
| 870 | { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, |
| 871 | { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, |
| 872 | { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, |
Andrew Lunn | e413e7e | 2015-04-02 04:06:38 +0200 | [diff] [blame] | 873 | }; |
| 874 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 875 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 876 | struct mv88e6xxx_hw_stat *s, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 877 | int port, u16 bank1_select, |
| 878 | u16 histogram) |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 879 | { |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 880 | u32 low; |
| 881 | u32 high = 0; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 882 | u16 reg = 0; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 883 | int err; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 884 | u64 value; |
| 885 | |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 886 | switch (s->type) { |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 887 | case STATS_TYPE_PORT: |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 888 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
| 889 | if (err) |
Jisheng Zhang | 6c3442f | 2018-04-27 16:18:58 +0800 | [diff] [blame] | 890 | return U64_MAX; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 891 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 892 | low = reg; |
Andrew Lunn | cda9f4a | 2018-03-01 02:02:31 +0100 | [diff] [blame] | 893 | if (s->size == 4) { |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 894 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
| 895 | if (err) |
Jisheng Zhang | 6c3442f | 2018-04-27 16:18:58 +0800 | [diff] [blame] | 896 | return U64_MAX; |
Rasmus Villemoes | 84b3fd1 | 2019-05-29 07:02:11 +0000 | [diff] [blame] | 897 | low |= ((u32)reg) << 16; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 898 | } |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 899 | break; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 900 | case STATS_TYPE_BANK1: |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 901 | reg = bank1_select; |
Gustavo A. R. Silva | df561f66 | 2020-08-23 17:36:59 -0500 | [diff] [blame] | 902 | fallthrough; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 903 | case STATS_TYPE_BANK0: |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 904 | reg |= s->reg | histogram; |
Andrew Lunn | 7f9ef3a | 2016-11-21 23:27:05 +0100 | [diff] [blame] | 905 | mv88e6xxx_g1_stats_read(chip, reg, &low); |
Andrew Lunn | cda9f4a | 2018-03-01 02:02:31 +0100 | [diff] [blame] | 906 | if (s->size == 8) |
Andrew Lunn | 7f9ef3a | 2016-11-21 23:27:05 +0100 | [diff] [blame] | 907 | mv88e6xxx_g1_stats_read(chip, reg + 1, &high); |
Gustavo A. R. Silva | 9fc3e4d | 2017-05-11 22:11:29 -0500 | [diff] [blame] | 908 | break; |
| 909 | default: |
Jisheng Zhang | 6c3442f | 2018-04-27 16:18:58 +0800 | [diff] [blame] | 910 | return U64_MAX; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 911 | } |
Andrew Lunn | 6e46e2d | 2019-02-28 18:14:03 +0100 | [diff] [blame] | 912 | value = (((u64)high) << 32) | low; |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 913 | return value; |
| 914 | } |
| 915 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 916 | static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, |
| 917 | uint8_t *data, int types) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 918 | { |
| 919 | struct mv88e6xxx_hw_stat *stat; |
| 920 | int i, j; |
| 921 | |
| 922 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 923 | stat = &mv88e6xxx_hw_stats[i]; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 924 | if (stat->type & types) { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 925 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
| 926 | ETH_GSTRING_LEN); |
| 927 | j++; |
| 928 | } |
| 929 | } |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 930 | |
| 931 | return j; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 932 | } |
| 933 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 934 | static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, |
| 935 | uint8_t *data) |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 936 | { |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 937 | return mv88e6xxx_stats_get_strings(chip, data, |
| 938 | STATS_TYPE_BANK0 | STATS_TYPE_PORT); |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 939 | } |
| 940 | |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 941 | static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, |
| 942 | uint8_t *data) |
| 943 | { |
| 944 | return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); |
| 945 | } |
| 946 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 947 | static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, |
| 948 | uint8_t *data) |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 949 | { |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 950 | return mv88e6xxx_stats_get_strings(chip, data, |
| 951 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1); |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 952 | } |
| 953 | |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 954 | static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { |
| 955 | "atu_member_violation", |
| 956 | "atu_miss_violation", |
| 957 | "atu_full_violation", |
| 958 | "vtu_member_violation", |
| 959 | "vtu_miss_violation", |
| 960 | }; |
| 961 | |
| 962 | static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) |
| 963 | { |
| 964 | unsigned int i; |
| 965 | |
| 966 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) |
| 967 | strlcpy(data + i * ETH_GSTRING_LEN, |
| 968 | mv88e6xxx_atu_vtu_stats_strings[i], |
| 969 | ETH_GSTRING_LEN); |
| 970 | } |
| 971 | |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 972 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
Florian Fainelli | 89f0904 | 2018-04-25 12:12:50 -0700 | [diff] [blame] | 973 | u32 stringset, uint8_t *data) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 974 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 975 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 976 | int count = 0; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 977 | |
Florian Fainelli | 89f0904 | 2018-04-25 12:12:50 -0700 | [diff] [blame] | 978 | if (stringset != ETH_SS_STATS) |
| 979 | return; |
| 980 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 981 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | c6c8cd5 | 2018-03-01 02:02:28 +0100 | [diff] [blame] | 982 | |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 983 | if (chip->info->ops->stats_get_strings) |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 984 | count = chip->info->ops->stats_get_strings(chip, data); |
| 985 | |
| 986 | if (chip->info->ops->serdes_get_strings) { |
| 987 | data += count * ETH_GSTRING_LEN; |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 988 | count = chip->info->ops->serdes_get_strings(chip, port, data); |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 989 | } |
Andrew Lunn | c6c8cd5 | 2018-03-01 02:02:28 +0100 | [diff] [blame] | 990 | |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 991 | data += count * ETH_GSTRING_LEN; |
| 992 | mv88e6xxx_atu_vtu_get_strings(data); |
| 993 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 994 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 995 | } |
| 996 | |
| 997 | static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, |
| 998 | int types) |
| 999 | { |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 1000 | struct mv88e6xxx_hw_stat *stat; |
| 1001 | int i, j; |
| 1002 | |
| 1003 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 1004 | stat = &mv88e6xxx_hw_stats[i]; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1005 | if (stat->type & types) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 1006 | j++; |
| 1007 | } |
| 1008 | return j; |
| 1009 | } |
| 1010 | |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1011 | static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
| 1012 | { |
| 1013 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | |
| 1014 | STATS_TYPE_PORT); |
| 1015 | } |
| 1016 | |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 1017 | static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
| 1018 | { |
| 1019 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); |
| 1020 | } |
| 1021 | |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1022 | static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
| 1023 | { |
| 1024 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | |
| 1025 | STATS_TYPE_BANK1); |
| 1026 | } |
| 1027 | |
Florian Fainelli | 89f0904 | 2018-04-25 12:12:50 -0700 | [diff] [blame] | 1028 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1029 | { |
| 1030 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1031 | int serdes_count = 0; |
| 1032 | int count = 0; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1033 | |
Florian Fainelli | 89f0904 | 2018-04-25 12:12:50 -0700 | [diff] [blame] | 1034 | if (sset != ETH_SS_STATS) |
| 1035 | return 0; |
| 1036 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1037 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1038 | if (chip->info->ops->stats_get_sset_count) |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1039 | count = chip->info->ops->stats_get_sset_count(chip); |
| 1040 | if (count < 0) |
| 1041 | goto out; |
| 1042 | |
| 1043 | if (chip->info->ops->serdes_get_sset_count) |
| 1044 | serdes_count = chip->info->ops->serdes_get_sset_count(chip, |
| 1045 | port); |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 1046 | if (serdes_count < 0) { |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1047 | count = serdes_count; |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 1048 | goto out; |
| 1049 | } |
| 1050 | count += serdes_count; |
| 1051 | count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); |
| 1052 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1053 | out: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1054 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1055 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1056 | return count; |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 1057 | } |
| 1058 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1059 | static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1060 | uint64_t *data, int types, |
| 1061 | u16 bank1_select, u16 histogram) |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1062 | { |
| 1063 | struct mv88e6xxx_hw_stat *stat; |
| 1064 | int i, j; |
| 1065 | |
| 1066 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
| 1067 | stat = &mv88e6xxx_hw_stats[i]; |
| 1068 | if (stat->type & types) { |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1069 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 1070 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, |
| 1071 | bank1_select, |
| 1072 | histogram); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1073 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 377cda1 | 2018-02-15 14:38:34 +0100 | [diff] [blame] | 1074 | |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1075 | j++; |
| 1076 | } |
| 1077 | } |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1078 | return j; |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1079 | } |
| 1080 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1081 | static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1082 | uint64_t *data) |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1083 | { |
| 1084 | return mv88e6xxx_stats_get_stats(chip, port, data, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 1085 | STATS_TYPE_BANK0 | STATS_TYPE_PORT, |
Vivien Didelot | 57d1ef3 | 2017-06-15 12:14:05 -0400 | [diff] [blame] | 1086 | 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1087 | } |
| 1088 | |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 1089 | static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1090 | uint64_t *data) |
| 1091 | { |
| 1092 | return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, |
| 1093 | 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); |
| 1094 | } |
| 1095 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1096 | static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1097 | uint64_t *data) |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1098 | { |
| 1099 | return mv88e6xxx_stats_get_stats(chip, port, data, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 1100 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, |
Vivien Didelot | 57d1ef3 | 2017-06-15 12:14:05 -0400 | [diff] [blame] | 1101 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, |
| 1102 | MV88E6XXX_G1_STATS_OP_HIST_RX_TX); |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 1103 | } |
| 1104 | |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1105 | static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1106 | uint64_t *data) |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 1107 | { |
| 1108 | return mv88e6xxx_stats_get_stats(chip, port, data, |
| 1109 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, |
Vivien Didelot | 57d1ef3 | 2017-06-15 12:14:05 -0400 | [diff] [blame] | 1110 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, |
| 1111 | 0); |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1112 | } |
| 1113 | |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 1114 | static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1115 | uint64_t *data) |
| 1116 | { |
| 1117 | *data++ = chip->ports[port].atu_member_violation; |
| 1118 | *data++ = chip->ports[port].atu_miss_violation; |
| 1119 | *data++ = chip->ports[port].atu_full_violation; |
| 1120 | *data++ = chip->ports[port].vtu_member_violation; |
| 1121 | *data++ = chip->ports[port].vtu_miss_violation; |
| 1122 | } |
| 1123 | |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1124 | static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, |
| 1125 | uint64_t *data) |
| 1126 | { |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1127 | int count = 0; |
| 1128 | |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1129 | if (chip->info->ops->stats_get_stats) |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1130 | count = chip->info->ops->stats_get_stats(chip, port, data); |
| 1131 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1132 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1133 | if (chip->info->ops->serdes_get_stats) { |
| 1134 | data += count; |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 1135 | count = chip->info->ops->serdes_get_stats(chip, port, data); |
Andrew Lunn | 436fe17 | 2018-03-01 02:02:29 +0100 | [diff] [blame] | 1136 | } |
Andrew Lunn | 65f60e4 | 2018-03-28 23:50:28 +0200 | [diff] [blame] | 1137 | data += count; |
| 1138 | mv88e6xxx_atu_vtu_get_stats(chip, port, data); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1139 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1140 | } |
| 1141 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1142 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
| 1143 | uint64_t *data) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1144 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1145 | struct mv88e6xxx_chip *chip = ds->priv; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1146 | int ret; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1147 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1148 | mv88e6xxx_reg_lock(chip); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1149 | |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 1150 | ret = mv88e6xxx_stats_snapshot(chip, port); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1151 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 377cda1 | 2018-02-15 14:38:34 +0100 | [diff] [blame] | 1152 | |
| 1153 | if (ret < 0) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1154 | return; |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 1155 | |
| 1156 | mv88e6xxx_get_stats(chip, port, data); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1157 | |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1158 | } |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 1159 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1160 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1161 | { |
Andrew Lunn | 0d30bbd | 2020-02-16 18:54:13 +0100 | [diff] [blame] | 1162 | struct mv88e6xxx_chip *chip = ds->priv; |
| 1163 | int len; |
| 1164 | |
| 1165 | len = 32 * sizeof(u16); |
| 1166 | if (chip->info->ops->serdes_get_regs_len) |
| 1167 | len += chip->info->ops->serdes_get_regs_len(chip, port); |
| 1168 | |
| 1169 | return len; |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1170 | } |
| 1171 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1172 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
| 1173 | struct ethtool_regs *regs, void *_p) |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1174 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1175 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 1176 | int err; |
| 1177 | u16 reg; |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1178 | u16 *p = _p; |
| 1179 | int i; |
| 1180 | |
Vivien Didelot | a5f3932 | 2018-12-17 16:05:21 -0500 | [diff] [blame] | 1181 | regs->version = chip->info->prod_num; |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1182 | |
| 1183 | memset(p, 0xff, 32 * sizeof(u16)); |
| 1184 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1185 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 2306251 | 2016-05-09 13:22:45 -0400 | [diff] [blame] | 1186 | |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1187 | for (i = 0; i < 32; i++) { |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1188 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 1189 | err = mv88e6xxx_port_read(chip, port, i, ®); |
| 1190 | if (!err) |
| 1191 | p[i] = reg; |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1192 | } |
Vivien Didelot | 2306251 | 2016-05-09 13:22:45 -0400 | [diff] [blame] | 1193 | |
Andrew Lunn | 0d30bbd | 2020-02-16 18:54:13 +0100 | [diff] [blame] | 1194 | if (chip->info->ops->serdes_get_regs) |
| 1195 | chip->info->ops->serdes_get_regs(chip, port, &p[i]); |
| 1196 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1197 | mv88e6xxx_reg_unlock(chip); |
Guenter Roeck | a1ab91f | 2014-10-29 10:45:05 -0700 | [diff] [blame] | 1198 | } |
| 1199 | |
Vivien Didelot | 08f5006 | 2017-08-01 16:32:41 -0400 | [diff] [blame] | 1200 | static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, |
| 1201 | struct ethtool_eee *e) |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 1202 | { |
Vivien Didelot | 5480db6 | 2017-08-01 16:32:40 -0400 | [diff] [blame] | 1203 | /* Nothing to do on the port's MAC */ |
| 1204 | return 0; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 1205 | } |
| 1206 | |
Vivien Didelot | 08f5006 | 2017-08-01 16:32:41 -0400 | [diff] [blame] | 1207 | static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, |
| 1208 | struct ethtool_eee *e) |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 1209 | { |
Vivien Didelot | 5480db6 | 2017-08-01 16:32:40 -0400 | [diff] [blame] | 1210 | /* Nothing to do on the port's MAC */ |
| 1211 | return 0; |
Guenter Roeck | 11b3b45 | 2015-03-06 22:23:51 -0800 | [diff] [blame] | 1212 | } |
| 1213 | |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1214 | /* Mask of the local ports allowed to receive frames from a given fabric port */ |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1215 | static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1216 | { |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1217 | struct dsa_switch *ds = chip->ds; |
| 1218 | struct dsa_switch_tree *dst = ds->dst; |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1219 | struct net_device *br; |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1220 | struct dsa_port *dp; |
| 1221 | bool found = false; |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1222 | u16 pvlan; |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1223 | |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1224 | list_for_each_entry(dp, &dst->ports, list) { |
| 1225 | if (dp->ds->index == dev && dp->index == port) { |
| 1226 | found = true; |
| 1227 | break; |
| 1228 | } |
| 1229 | } |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1230 | |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1231 | /* Prevent frames from unknown switch or port */ |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1232 | if (!found) |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1233 | return 0; |
| 1234 | |
| 1235 | /* Frames from DSA links and CPU ports can egress any local port */ |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1236 | if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1237 | return mv88e6xxx_port_mask(chip); |
| 1238 | |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1239 | br = dp->bridge_dev; |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1240 | pvlan = 0; |
| 1241 | |
| 1242 | /* Frames from user ports can egress any local DSA links and CPU ports, |
| 1243 | * as well as any local member of their bridge group. |
| 1244 | */ |
Vivien Didelot | 9dc8b13 | 2019-10-21 16:51:26 -0400 | [diff] [blame] | 1245 | list_for_each_entry(dp, &dst->ports, list) |
| 1246 | if (dp->ds == ds && |
| 1247 | (dp->type == DSA_PORT_TYPE_CPU || |
| 1248 | dp->type == DSA_PORT_TYPE_DSA || |
| 1249 | (br && dp->bridge_dev == br))) |
| 1250 | pvlan |= BIT(dp->index); |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1251 | |
| 1252 | return pvlan; |
| 1253 | } |
| 1254 | |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 1255 | static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) |
Vivien Didelot | e5887a2 | 2017-03-30 17:37:11 -0400 | [diff] [blame] | 1256 | { |
| 1257 | u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 1258 | |
| 1259 | /* prevent frames from going back out of the port they came in on */ |
| 1260 | output_ports &= ~BIT(port); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1261 | |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 1262 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1263 | } |
| 1264 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1265 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
| 1266 | u8 state) |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1267 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1268 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1269 | int err; |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1270 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1271 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 1272 | err = mv88e6xxx_port_set_state(chip, port, state); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1273 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 553eb54 | 2016-05-13 20:38:23 -0400 | [diff] [blame] | 1274 | |
| 1275 | if (err) |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 1276 | dev_err(ds->dev, "p%d: failed to update state\n", port); |
Guenter Roeck | facd95b | 2015-03-26 18:36:35 -0700 | [diff] [blame] | 1277 | } |
| 1278 | |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 1279 | static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) |
| 1280 | { |
| 1281 | int err; |
| 1282 | |
| 1283 | if (chip->info->ops->ieee_pri_map) { |
| 1284 | err = chip->info->ops->ieee_pri_map(chip); |
| 1285 | if (err) |
| 1286 | return err; |
| 1287 | } |
| 1288 | |
| 1289 | if (chip->info->ops->ip_pri_map) { |
| 1290 | err = chip->info->ops->ip_pri_map(chip); |
| 1291 | if (err) |
| 1292 | return err; |
| 1293 | } |
| 1294 | |
| 1295 | return 0; |
| 1296 | } |
| 1297 | |
Vivien Didelot | c7f047b | 2018-04-26 21:56:45 -0400 | [diff] [blame] | 1298 | static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) |
| 1299 | { |
Vivien Didelot | c5f5176 | 2019-10-30 22:09:13 -0400 | [diff] [blame] | 1300 | struct dsa_switch *ds = chip->ds; |
Vivien Didelot | c7f047b | 2018-04-26 21:56:45 -0400 | [diff] [blame] | 1301 | int target, port; |
| 1302 | int err; |
| 1303 | |
| 1304 | if (!chip->info->global2_addr) |
| 1305 | return 0; |
| 1306 | |
| 1307 | /* Initialize the routing port to the 32 possible target devices */ |
| 1308 | for (target = 0; target < 32; target++) { |
Vivien Didelot | c5f5176 | 2019-10-30 22:09:13 -0400 | [diff] [blame] | 1309 | port = dsa_routing_port(ds, target); |
| 1310 | if (port == ds->num_ports) |
| 1311 | port = 0x1f; |
Vivien Didelot | c7f047b | 2018-04-26 21:56:45 -0400 | [diff] [blame] | 1312 | |
| 1313 | err = mv88e6xxx_g2_device_mapping_write(chip, target, port); |
| 1314 | if (err) |
| 1315 | return err; |
| 1316 | } |
| 1317 | |
Vivien Didelot | 02317e6 | 2018-05-09 11:38:49 -0400 | [diff] [blame] | 1318 | if (chip->info->ops->set_cascade_port) { |
| 1319 | port = MV88E6XXX_CASCADE_PORT_MULTIPLE; |
| 1320 | err = chip->info->ops->set_cascade_port(chip, port); |
| 1321 | if (err) |
| 1322 | return err; |
| 1323 | } |
| 1324 | |
Vivien Didelot | 23c9891 | 2018-05-09 11:38:50 -0400 | [diff] [blame] | 1325 | err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); |
| 1326 | if (err) |
| 1327 | return err; |
| 1328 | |
Vivien Didelot | c7f047b | 2018-04-26 21:56:45 -0400 | [diff] [blame] | 1329 | return 0; |
| 1330 | } |
| 1331 | |
Vivien Didelot | b28f872 | 2018-04-26 21:56:44 -0400 | [diff] [blame] | 1332 | static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) |
| 1333 | { |
| 1334 | /* Clear all trunk masks and mapping */ |
| 1335 | if (chip->info->global2_addr) |
| 1336 | return mv88e6xxx_g2_trunk_clear(chip); |
| 1337 | |
| 1338 | return 0; |
| 1339 | } |
| 1340 | |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 1341 | static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) |
| 1342 | { |
| 1343 | if (chip->info->ops->rmu_disable) |
| 1344 | return chip->info->ops->rmu_disable(chip); |
| 1345 | |
| 1346 | return 0; |
| 1347 | } |
| 1348 | |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 1349 | static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) |
| 1350 | { |
| 1351 | if (chip->info->ops->pot_clear) |
| 1352 | return chip->info->ops->pot_clear(chip); |
| 1353 | |
| 1354 | return 0; |
| 1355 | } |
| 1356 | |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 1357 | static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) |
| 1358 | { |
| 1359 | if (chip->info->ops->mgmt_rsvd2cpu) |
| 1360 | return chip->info->ops->mgmt_rsvd2cpu(chip); |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
Vivien Didelot | a2ac29d | 2017-03-11 16:12:49 -0500 | [diff] [blame] | 1365 | static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) |
| 1366 | { |
Vivien Didelot | c3a7d4a | 2017-03-11 16:12:51 -0500 | [diff] [blame] | 1367 | int err; |
| 1368 | |
Vivien Didelot | daefc94 | 2017-03-11 16:12:54 -0500 | [diff] [blame] | 1369 | err = mv88e6xxx_g1_atu_flush(chip, 0, true); |
| 1370 | if (err) |
| 1371 | return err; |
| 1372 | |
Rasmus Villemoes | 49506a9 | 2020-12-10 12:06:44 +0100 | [diff] [blame] | 1373 | /* The chips that have a "learn2all" bit in Global1, ATU |
| 1374 | * Control are precisely those whose port registers have a |
| 1375 | * Message Port bit in Port Control 1 and hence implement |
| 1376 | * ->port_setup_message_port. |
| 1377 | */ |
| 1378 | if (chip->info->ops->port_setup_message_port) { |
| 1379 | err = mv88e6xxx_g1_atu_set_learn2all(chip, true); |
| 1380 | if (err) |
| 1381 | return err; |
| 1382 | } |
Vivien Didelot | c3a7d4a | 2017-03-11 16:12:51 -0500 | [diff] [blame] | 1383 | |
Vivien Didelot | a2ac29d | 2017-03-11 16:12:49 -0500 | [diff] [blame] | 1384 | return mv88e6xxx_g1_atu_set_age_time(chip, 300000); |
| 1385 | } |
| 1386 | |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 1387 | static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) |
| 1388 | { |
| 1389 | int port; |
| 1390 | int err; |
| 1391 | |
| 1392 | if (!chip->info->ops->irl_init_all) |
| 1393 | return 0; |
| 1394 | |
| 1395 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
| 1396 | /* Disable ingress rate limiting by resetting all per port |
| 1397 | * ingress rate limit resources to their initial state. |
| 1398 | */ |
| 1399 | err = chip->info->ops->irl_init_all(chip, port); |
| 1400 | if (err) |
| 1401 | return err; |
| 1402 | } |
| 1403 | |
| 1404 | return 0; |
| 1405 | } |
| 1406 | |
Vivien Didelot | 04a69a1 | 2017-10-13 14:18:05 -0400 | [diff] [blame] | 1407 | static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) |
| 1408 | { |
| 1409 | if (chip->info->ops->set_switch_mac) { |
| 1410 | u8 addr[ETH_ALEN]; |
| 1411 | |
| 1412 | eth_random_addr(addr); |
| 1413 | |
| 1414 | return chip->info->ops->set_switch_mac(chip, addr); |
| 1415 | } |
| 1416 | |
| 1417 | return 0; |
| 1418 | } |
| 1419 | |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1420 | static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) |
| 1421 | { |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 1422 | struct dsa_switch_tree *dst = chip->ds->dst; |
| 1423 | struct dsa_switch *ds; |
| 1424 | struct dsa_port *dp; |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1425 | u16 pvlan = 0; |
| 1426 | |
| 1427 | if (!mv88e6xxx_has_pvt(chip)) |
Vivien Didelot | d14939b | 2019-10-21 16:51:25 -0400 | [diff] [blame] | 1428 | return 0; |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1429 | |
| 1430 | /* Skip the local source device, which uses in-chip port VLAN */ |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 1431 | if (dev != chip->ds->index) { |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 1432 | pvlan = mv88e6xxx_port_vlan(chip, dev, port); |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1433 | |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 1434 | ds = dsa_switch_find(dst->index, dev); |
| 1435 | dp = ds ? dsa_to_port(ds, port) : NULL; |
| 1436 | if (dp && dp->lag_dev) { |
| 1437 | /* As the PVT is used to limit flooding of |
| 1438 | * FORWARD frames, which use the LAG ID as the |
| 1439 | * source port, we must translate dev/port to |
| 1440 | * the special "LAG device" in the PVT, using |
| 1441 | * the LAG ID as the port number. |
| 1442 | */ |
Tobias Waldekranz | 78e70db | 2021-04-21 14:04:52 +0200 | [diff] [blame] | 1443 | dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 1444 | port = dsa_lag_id(dst, dp->lag_dev); |
| 1445 | } |
| 1446 | } |
| 1447 | |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1448 | return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); |
| 1449 | } |
| 1450 | |
Vivien Didelot | 8122899 | 2017-03-30 17:37:08 -0400 | [diff] [blame] | 1451 | static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) |
| 1452 | { |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1453 | int dev, port; |
| 1454 | int err; |
| 1455 | |
Vivien Didelot | 8122899 | 2017-03-30 17:37:08 -0400 | [diff] [blame] | 1456 | if (!mv88e6xxx_has_pvt(chip)) |
| 1457 | return 0; |
| 1458 | |
| 1459 | /* Clear 5 Bit Port for usage with Marvell Link Street devices: |
| 1460 | * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. |
| 1461 | */ |
Vivien Didelot | 17a1594 | 2017-03-30 17:37:09 -0400 | [diff] [blame] | 1462 | err = mv88e6xxx_g2_misc_4_bit_port(chip); |
| 1463 | if (err) |
| 1464 | return err; |
| 1465 | |
| 1466 | for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { |
| 1467 | for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { |
| 1468 | err = mv88e6xxx_pvt_map(chip, dev, port); |
| 1469 | if (err) |
| 1470 | return err; |
| 1471 | } |
| 1472 | } |
| 1473 | |
| 1474 | return 0; |
Vivien Didelot | 8122899 | 2017-03-30 17:37:08 -0400 | [diff] [blame] | 1475 | } |
| 1476 | |
Vivien Didelot | 749efcb | 2016-09-22 16:49:24 -0400 | [diff] [blame] | 1477 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
| 1478 | { |
| 1479 | struct mv88e6xxx_chip *chip = ds->priv; |
| 1480 | int err; |
| 1481 | |
Tobias Waldekranz | ffcec3f | 2021-03-18 20:25:34 +0100 | [diff] [blame] | 1482 | if (dsa_to_port(ds, port)->lag_dev) |
| 1483 | /* Hardware is incapable of fast-aging a LAG through a |
| 1484 | * regular ATU move operation. Until we have something |
| 1485 | * more fancy in place this is a no-op. |
| 1486 | */ |
| 1487 | return; |
| 1488 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1489 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 1490 | err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1491 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 749efcb | 2016-09-22 16:49:24 -0400 | [diff] [blame] | 1492 | |
| 1493 | if (err) |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 1494 | dev_err(ds->dev, "p%d: failed to flush ATU\n", port); |
Vivien Didelot | 749efcb | 2016-09-22 16:49:24 -0400 | [diff] [blame] | 1495 | } |
| 1496 | |
Vivien Didelot | b486d7c | 2017-05-01 14:05:13 -0400 | [diff] [blame] | 1497 | static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) |
| 1498 | { |
Tobias Waldekranz | e545f86 | 2020-11-10 19:57:20 +0100 | [diff] [blame] | 1499 | if (!mv88e6xxx_max_vid(chip)) |
Vivien Didelot | b486d7c | 2017-05-01 14:05:13 -0400 | [diff] [blame] | 1500 | return 0; |
| 1501 | |
| 1502 | return mv88e6xxx_g1_vtu_flush(chip); |
| 1503 | } |
| 1504 | |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 1505 | static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
| 1506 | struct mv88e6xxx_vtu_entry *entry) |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 1507 | { |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 1508 | int err; |
| 1509 | |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 1510 | if (!chip->info->ops->vtu_getnext) |
| 1511 | return -EOPNOTSUPP; |
| 1512 | |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 1513 | entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); |
| 1514 | entry->valid = false; |
| 1515 | |
| 1516 | err = chip->info->ops->vtu_getnext(chip, entry); |
| 1517 | |
| 1518 | if (entry->vid != vid) |
| 1519 | entry->valid = false; |
| 1520 | |
| 1521 | return err; |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 1522 | } |
| 1523 | |
Tobias Waldekranz | d89ef4b | 2021-03-18 20:25:35 +0100 | [diff] [blame] | 1524 | static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, |
| 1525 | int (*cb)(struct mv88e6xxx_chip *chip, |
| 1526 | const struct mv88e6xxx_vtu_entry *entry, |
| 1527 | void *priv), |
| 1528 | void *priv) |
| 1529 | { |
| 1530 | struct mv88e6xxx_vtu_entry entry = { |
| 1531 | .vid = mv88e6xxx_max_vid(chip), |
| 1532 | .valid = false, |
| 1533 | }; |
| 1534 | int err; |
| 1535 | |
| 1536 | if (!chip->info->ops->vtu_getnext) |
| 1537 | return -EOPNOTSUPP; |
| 1538 | |
| 1539 | do { |
| 1540 | err = chip->info->ops->vtu_getnext(chip, &entry); |
| 1541 | if (err) |
| 1542 | return err; |
| 1543 | |
| 1544 | if (!entry.valid) |
| 1545 | break; |
| 1546 | |
| 1547 | err = cb(chip, &entry, priv); |
| 1548 | if (err) |
| 1549 | return err; |
| 1550 | } while (entry.vid < mv88e6xxx_max_vid(chip)); |
| 1551 | |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 1555 | static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
| 1556 | struct mv88e6xxx_vtu_entry *entry) |
| 1557 | { |
| 1558 | if (!chip->info->ops->vtu_loadpurge) |
| 1559 | return -EOPNOTSUPP; |
| 1560 | |
| 1561 | return chip->info->ops->vtu_loadpurge(chip, entry); |
| 1562 | } |
| 1563 | |
Tobias Waldekranz | d89ef4b | 2021-03-18 20:25:35 +0100 | [diff] [blame] | 1564 | static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, |
| 1565 | const struct mv88e6xxx_vtu_entry *entry, |
| 1566 | void *_fid_bitmap) |
| 1567 | { |
| 1568 | unsigned long *fid_bitmap = _fid_bitmap; |
| 1569 | |
| 1570 | set_bit(entry->fid, fid_bitmap); |
| 1571 | return 0; |
| 1572 | } |
| 1573 | |
Andrew Lunn | 90b6dbd | 2020-09-18 21:11:06 +0200 | [diff] [blame] | 1574 | int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1575 | { |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1576 | int i, err; |
Andrew Lunn | 90b6dbd | 2020-09-18 21:11:06 +0200 | [diff] [blame] | 1577 | u16 fid; |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1578 | |
| 1579 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); |
| 1580 | |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1581 | /* Set every FID bit used by the (un)bridged ports */ |
Vivien Didelot | 370b4ff | 2016-09-29 12:21:57 -0400 | [diff] [blame] | 1582 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
Andrew Lunn | 90b6dbd | 2020-09-18 21:11:06 +0200 | [diff] [blame] | 1583 | err = mv88e6xxx_port_get_fid(chip, i, &fid); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1584 | if (err) |
| 1585 | return err; |
| 1586 | |
Andrew Lunn | 90b6dbd | 2020-09-18 21:11:06 +0200 | [diff] [blame] | 1587 | set_bit(fid, fid_bitmap); |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 1588 | } |
| 1589 | |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1590 | /* Set every FID bit used by the VLAN entries */ |
Tobias Waldekranz | d89ef4b | 2021-03-18 20:25:35 +0100 | [diff] [blame] | 1591 | return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); |
Andrew Lunn | 90b6dbd | 2020-09-18 21:11:06 +0200 | [diff] [blame] | 1592 | } |
| 1593 | |
| 1594 | static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) |
| 1595 | { |
| 1596 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); |
| 1597 | int err; |
| 1598 | |
| 1599 | err = mv88e6xxx_fid_map(chip, fid_bitmap); |
| 1600 | if (err) |
| 1601 | return err; |
| 1602 | |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1603 | /* The reset value 0x000 is used to indicate that multiple address |
| 1604 | * databases are not needed. Return the next positive available. |
| 1605 | */ |
| 1606 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 1607 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1608 | return -ENOSPC; |
| 1609 | |
| 1610 | /* Clear the database */ |
Vivien Didelot | daefc94 | 2017-03-11 16:12:54 -0500 | [diff] [blame] | 1611 | return mv88e6xxx_g1_atu_flush(chip, *fid, true); |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 1612 | } |
| 1613 | |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1614 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1615 | u16 vid) |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1616 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1617 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 425d2d3 | 2019-08-01 14:36:34 -0400 | [diff] [blame] | 1618 | struct mv88e6xxx_vtu_entry vlan; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1619 | int i, err; |
| 1620 | |
Andrew Lunn | db06ae41 | 2017-09-25 23:32:20 +0200 | [diff] [blame] | 1621 | /* DSA and CPU ports have to be members of multiple vlans */ |
| 1622 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) |
| 1623 | return 0; |
| 1624 | |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 1625 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1626 | if (err) |
| 1627 | return err; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1628 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1629 | if (!vlan.valid) |
| 1630 | return 0; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1631 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1632 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
| 1633 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
| 1634 | continue; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1635 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1636 | if (!dsa_to_port(ds, i)->slave) |
| 1637 | continue; |
Andrew Lunn | 66e2809 | 2016-12-11 21:07:19 +0100 | [diff] [blame] | 1638 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1639 | if (vlan.member[i] == |
| 1640 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
| 1641 | continue; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1642 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1643 | if (dsa_to_port(ds, i)->bridge_dev == |
| 1644 | dsa_to_port(ds, port)->bridge_dev) |
| 1645 | break; /* same bridge, check next VLAN */ |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1646 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1647 | if (!dsa_to_port(ds, i)->bridge_dev) |
| 1648 | continue; |
Andrew Lunn | 66e2809 | 2016-12-11 21:07:19 +0100 | [diff] [blame] | 1649 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1650 | dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", |
| 1651 | port, vlan.vid, i, |
| 1652 | netdev_name(dsa_to_port(ds, i)->bridge_dev)); |
| 1653 | return -EOPNOTSUPP; |
| 1654 | } |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1655 | |
Vivien Didelot | 7095a4c | 2019-08-01 14:36:33 -0400 | [diff] [blame] | 1656 | return 0; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1657 | } |
| 1658 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 1659 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
Vladimir Oltean | 89153ed | 2021-02-13 22:43:19 +0200 | [diff] [blame] | 1660 | bool vlan_filtering, |
| 1661 | struct netlink_ext_ack *extack) |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1662 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1663 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 1664 | u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : |
| 1665 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 1666 | int err; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1667 | |
Vladimir Oltean | bae33f2 | 2021-01-09 02:01:50 +0200 | [diff] [blame] | 1668 | if (!mv88e6xxx_max_vid(chip)) |
| 1669 | return -EOPNOTSUPP; |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1670 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1671 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 1672 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 1673 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1674 | |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 1675 | return err; |
Vivien Didelot | 214cdb9 | 2016-02-26 13:16:08 -0500 | [diff] [blame] | 1676 | } |
| 1677 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 1678 | static int |
| 1679 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
Vivien Didelot | 80e0236 | 2017-11-30 11:23:57 -0500 | [diff] [blame] | 1680 | const struct switchdev_obj_port_vlan *vlan) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 1681 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 1682 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1683 | int err; |
| 1684 | |
Tobias Waldekranz | e545f86 | 2020-11-10 19:57:20 +0100 | [diff] [blame] | 1685 | if (!mv88e6xxx_max_vid(chip)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 1686 | return -EOPNOTSUPP; |
| 1687 | |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1688 | /* If the requested port doesn't belong to the same bridge as the VLAN |
| 1689 | * members, do not support it (yet) and fallback to software VLAN. |
| 1690 | */ |
Vivien Didelot | 7095a4c | 2019-08-01 14:36:33 -0400 | [diff] [blame] | 1691 | mv88e6xxx_reg_lock(chip); |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 1692 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); |
Vivien Didelot | 7095a4c | 2019-08-01 14:36:33 -0400 | [diff] [blame] | 1693 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | da9c359 | 2016-02-12 12:09:40 -0500 | [diff] [blame] | 1694 | |
Vivien Didelot | 7095a4c | 2019-08-01 14:36:33 -0400 | [diff] [blame] | 1695 | return err; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 1696 | } |
| 1697 | |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1698 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
| 1699 | const unsigned char *addr, u16 vid, |
| 1700 | u8 state) |
| 1701 | { |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1702 | struct mv88e6xxx_atu_entry entry; |
Vivien Didelot | 5ef8d24 | 2019-08-01 14:36:35 -0400 | [diff] [blame] | 1703 | struct mv88e6xxx_vtu_entry vlan; |
| 1704 | u16 fid; |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1705 | int err; |
| 1706 | |
| 1707 | /* Null VLAN ID corresponds to the port private database */ |
Vivien Didelot | 5ef8d24 | 2019-08-01 14:36:35 -0400 | [diff] [blame] | 1708 | if (vid == 0) { |
| 1709 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
| 1710 | if (err) |
| 1711 | return err; |
| 1712 | } else { |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 1713 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
Vivien Didelot | 5ef8d24 | 2019-08-01 14:36:35 -0400 | [diff] [blame] | 1714 | if (err) |
| 1715 | return err; |
| 1716 | |
| 1717 | /* switchdev expects -EOPNOTSUPP to honor software VLANs */ |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 1718 | if (!vlan.valid) |
Vivien Didelot | 5ef8d24 | 2019-08-01 14:36:35 -0400 | [diff] [blame] | 1719 | return -EOPNOTSUPP; |
| 1720 | |
| 1721 | fid = vlan.fid; |
| 1722 | } |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1723 | |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 1724 | entry.state = 0; |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1725 | ether_addr_copy(entry.mac, addr); |
| 1726 | eth_addr_dec(entry.mac); |
| 1727 | |
Vivien Didelot | 5ef8d24 | 2019-08-01 14:36:35 -0400 | [diff] [blame] | 1728 | err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1729 | if (err) |
| 1730 | return err; |
| 1731 | |
| 1732 | /* Initialize a fresh ATU entry if it isn't found */ |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 1733 | if (!entry.state || !ether_addr_equal(entry.mac, addr)) { |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1734 | memset(&entry, 0, sizeof(entry)); |
| 1735 | ether_addr_copy(entry.mac, addr); |
| 1736 | } |
| 1737 | |
| 1738 | /* Purge the ATU entry only if no port is using it anymore */ |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 1739 | if (!state) { |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1740 | entry.portvec &= ~BIT(port); |
| 1741 | if (!entry.portvec) |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 1742 | entry.state = 0; |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1743 | } else { |
DENG Qingfang | f72f2fb | 2021-01-30 21:43:34 +0800 | [diff] [blame] | 1744 | if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) |
| 1745 | entry.portvec = BIT(port); |
| 1746 | else |
| 1747 | entry.portvec |= BIT(port); |
| 1748 | |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1749 | entry.state = state; |
| 1750 | } |
| 1751 | |
Vivien Didelot | 5ef8d24 | 2019-08-01 14:36:35 -0400 | [diff] [blame] | 1752 | return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); |
Andrew Lunn | a4c93ae | 2017-11-09 22:29:55 +0100 | [diff] [blame] | 1753 | } |
| 1754 | |
Vivien Didelot | da7dc87 | 2019-09-07 16:00:49 -0400 | [diff] [blame] | 1755 | static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, |
| 1756 | const struct mv88e6xxx_policy *policy) |
| 1757 | { |
| 1758 | enum mv88e6xxx_policy_mapping mapping = policy->mapping; |
| 1759 | enum mv88e6xxx_policy_action action = policy->action; |
| 1760 | const u8 *addr = policy->addr; |
| 1761 | u16 vid = policy->vid; |
| 1762 | u8 state; |
| 1763 | int err; |
| 1764 | int id; |
| 1765 | |
| 1766 | if (!chip->info->ops->port_set_policy) |
| 1767 | return -EOPNOTSUPP; |
| 1768 | |
| 1769 | switch (mapping) { |
| 1770 | case MV88E6XXX_POLICY_MAPPING_DA: |
| 1771 | case MV88E6XXX_POLICY_MAPPING_SA: |
| 1772 | if (action == MV88E6XXX_POLICY_ACTION_NORMAL) |
| 1773 | state = 0; /* Dissociate the port and address */ |
| 1774 | else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && |
| 1775 | is_multicast_ether_addr(addr)) |
| 1776 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; |
| 1777 | else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && |
| 1778 | is_unicast_ether_addr(addr)) |
| 1779 | state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; |
| 1780 | else |
| 1781 | return -EOPNOTSUPP; |
| 1782 | |
| 1783 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
| 1784 | state); |
| 1785 | if (err) |
| 1786 | return err; |
| 1787 | break; |
| 1788 | default: |
| 1789 | return -EOPNOTSUPP; |
| 1790 | } |
| 1791 | |
| 1792 | /* Skip the port's policy clearing if the mapping is still in use */ |
| 1793 | if (action == MV88E6XXX_POLICY_ACTION_NORMAL) |
| 1794 | idr_for_each_entry(&chip->policies, policy, id) |
| 1795 | if (policy->port == port && |
| 1796 | policy->mapping == mapping && |
| 1797 | policy->action != action) |
| 1798 | return 0; |
| 1799 | |
| 1800 | return chip->info->ops->port_set_policy(chip, port, mapping, action); |
| 1801 | } |
| 1802 | |
| 1803 | static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, |
| 1804 | struct ethtool_rx_flow_spec *fs) |
| 1805 | { |
| 1806 | struct ethhdr *mac_entry = &fs->h_u.ether_spec; |
| 1807 | struct ethhdr *mac_mask = &fs->m_u.ether_spec; |
| 1808 | enum mv88e6xxx_policy_mapping mapping; |
| 1809 | enum mv88e6xxx_policy_action action; |
| 1810 | struct mv88e6xxx_policy *policy; |
| 1811 | u16 vid = 0; |
| 1812 | u8 *addr; |
| 1813 | int err; |
| 1814 | int id; |
| 1815 | |
| 1816 | if (fs->location != RX_CLS_LOC_ANY) |
| 1817 | return -EINVAL; |
| 1818 | |
| 1819 | if (fs->ring_cookie == RX_CLS_FLOW_DISC) |
| 1820 | action = MV88E6XXX_POLICY_ACTION_DISCARD; |
| 1821 | else |
| 1822 | return -EOPNOTSUPP; |
| 1823 | |
| 1824 | switch (fs->flow_type & ~FLOW_EXT) { |
| 1825 | case ETHER_FLOW: |
| 1826 | if (!is_zero_ether_addr(mac_mask->h_dest) && |
| 1827 | is_zero_ether_addr(mac_mask->h_source)) { |
| 1828 | mapping = MV88E6XXX_POLICY_MAPPING_DA; |
| 1829 | addr = mac_entry->h_dest; |
| 1830 | } else if (is_zero_ether_addr(mac_mask->h_dest) && |
| 1831 | !is_zero_ether_addr(mac_mask->h_source)) { |
| 1832 | mapping = MV88E6XXX_POLICY_MAPPING_SA; |
| 1833 | addr = mac_entry->h_source; |
| 1834 | } else { |
| 1835 | /* Cannot support DA and SA mapping in the same rule */ |
| 1836 | return -EOPNOTSUPP; |
| 1837 | } |
| 1838 | break; |
| 1839 | default: |
| 1840 | return -EOPNOTSUPP; |
| 1841 | } |
| 1842 | |
| 1843 | if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { |
Andrew Lunn | 0484428 | 2020-07-05 21:38:08 +0200 | [diff] [blame] | 1844 | if (fs->m_ext.vlan_tci != htons(0xffff)) |
Vivien Didelot | da7dc87 | 2019-09-07 16:00:49 -0400 | [diff] [blame] | 1845 | return -EOPNOTSUPP; |
| 1846 | vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; |
| 1847 | } |
| 1848 | |
| 1849 | idr_for_each_entry(&chip->policies, policy, id) { |
| 1850 | if (policy->port == port && policy->mapping == mapping && |
| 1851 | policy->action == action && policy->vid == vid && |
| 1852 | ether_addr_equal(policy->addr, addr)) |
| 1853 | return -EEXIST; |
| 1854 | } |
| 1855 | |
| 1856 | policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); |
| 1857 | if (!policy) |
| 1858 | return -ENOMEM; |
| 1859 | |
| 1860 | fs->location = 0; |
| 1861 | err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, |
| 1862 | GFP_KERNEL); |
| 1863 | if (err) { |
| 1864 | devm_kfree(chip->dev, policy); |
| 1865 | return err; |
| 1866 | } |
| 1867 | |
| 1868 | memcpy(&policy->fs, fs, sizeof(*fs)); |
| 1869 | ether_addr_copy(policy->addr, addr); |
| 1870 | policy->mapping = mapping; |
| 1871 | policy->action = action; |
| 1872 | policy->port = port; |
| 1873 | policy->vid = vid; |
| 1874 | |
| 1875 | err = mv88e6xxx_policy_apply(chip, port, policy); |
| 1876 | if (err) { |
| 1877 | idr_remove(&chip->policies, fs->location); |
| 1878 | devm_kfree(chip->dev, policy); |
| 1879 | return err; |
| 1880 | } |
| 1881 | |
| 1882 | return 0; |
| 1883 | } |
| 1884 | |
| 1885 | static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, |
| 1886 | struct ethtool_rxnfc *rxnfc, u32 *rule_locs) |
| 1887 | { |
| 1888 | struct ethtool_rx_flow_spec *fs = &rxnfc->fs; |
| 1889 | struct mv88e6xxx_chip *chip = ds->priv; |
| 1890 | struct mv88e6xxx_policy *policy; |
| 1891 | int err; |
| 1892 | int id; |
| 1893 | |
| 1894 | mv88e6xxx_reg_lock(chip); |
| 1895 | |
| 1896 | switch (rxnfc->cmd) { |
| 1897 | case ETHTOOL_GRXCLSRLCNT: |
| 1898 | rxnfc->data = 0; |
| 1899 | rxnfc->data |= RX_CLS_LOC_SPECIAL; |
| 1900 | rxnfc->rule_cnt = 0; |
| 1901 | idr_for_each_entry(&chip->policies, policy, id) |
| 1902 | if (policy->port == port) |
| 1903 | rxnfc->rule_cnt++; |
| 1904 | err = 0; |
| 1905 | break; |
| 1906 | case ETHTOOL_GRXCLSRULE: |
| 1907 | err = -ENOENT; |
| 1908 | policy = idr_find(&chip->policies, fs->location); |
| 1909 | if (policy) { |
| 1910 | memcpy(fs, &policy->fs, sizeof(*fs)); |
| 1911 | err = 0; |
| 1912 | } |
| 1913 | break; |
| 1914 | case ETHTOOL_GRXCLSRLALL: |
| 1915 | rxnfc->data = 0; |
| 1916 | rxnfc->rule_cnt = 0; |
| 1917 | idr_for_each_entry(&chip->policies, policy, id) |
| 1918 | if (policy->port == port) |
| 1919 | rule_locs[rxnfc->rule_cnt++] = id; |
| 1920 | err = 0; |
| 1921 | break; |
| 1922 | default: |
| 1923 | err = -EOPNOTSUPP; |
| 1924 | break; |
| 1925 | } |
| 1926 | |
| 1927 | mv88e6xxx_reg_unlock(chip); |
| 1928 | |
| 1929 | return err; |
| 1930 | } |
| 1931 | |
| 1932 | static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, |
| 1933 | struct ethtool_rxnfc *rxnfc) |
| 1934 | { |
| 1935 | struct ethtool_rx_flow_spec *fs = &rxnfc->fs; |
| 1936 | struct mv88e6xxx_chip *chip = ds->priv; |
| 1937 | struct mv88e6xxx_policy *policy; |
| 1938 | int err; |
| 1939 | |
| 1940 | mv88e6xxx_reg_lock(chip); |
| 1941 | |
| 1942 | switch (rxnfc->cmd) { |
| 1943 | case ETHTOOL_SRXCLSRLINS: |
| 1944 | err = mv88e6xxx_policy_insert(chip, port, fs); |
| 1945 | break; |
| 1946 | case ETHTOOL_SRXCLSRLDEL: |
| 1947 | err = -ENOENT; |
| 1948 | policy = idr_remove(&chip->policies, fs->location); |
| 1949 | if (policy) { |
| 1950 | policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; |
| 1951 | err = mv88e6xxx_policy_apply(chip, port, policy); |
| 1952 | devm_kfree(chip->dev, policy); |
| 1953 | } |
| 1954 | break; |
| 1955 | default: |
| 1956 | err = -EOPNOTSUPP; |
| 1957 | break; |
| 1958 | } |
| 1959 | |
| 1960 | mv88e6xxx_reg_unlock(chip); |
| 1961 | |
| 1962 | return err; |
| 1963 | } |
| 1964 | |
Andrew Lunn | 87fa886 | 2017-11-09 22:29:56 +0100 | [diff] [blame] | 1965 | static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, |
| 1966 | u16 vid) |
| 1967 | { |
Andrew Lunn | 87fa886 | 2017-11-09 22:29:56 +0100 | [diff] [blame] | 1968 | u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; |
Tobias Waldekranz | 0806dd46 | 2021-03-18 20:25:37 +0100 | [diff] [blame] | 1969 | u8 broadcast[ETH_ALEN]; |
| 1970 | |
| 1971 | eth_broadcast_addr(broadcast); |
Andrew Lunn | 87fa886 | 2017-11-09 22:29:56 +0100 | [diff] [blame] | 1972 | |
| 1973 | return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); |
| 1974 | } |
| 1975 | |
| 1976 | static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) |
| 1977 | { |
| 1978 | int port; |
| 1979 | int err; |
| 1980 | |
| 1981 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
Tobias Waldekranz | 8d1d829 | 2021-03-18 20:25:40 +0100 | [diff] [blame] | 1982 | struct dsa_port *dp = dsa_to_port(chip->ds, port); |
| 1983 | struct net_device *brport; |
| 1984 | |
| 1985 | if (dsa_is_unused_port(chip->ds, port)) |
| 1986 | continue; |
| 1987 | |
| 1988 | brport = dsa_port_to_bridge_port(dp); |
| 1989 | if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) |
| 1990 | /* Skip bridged user ports where broadcast |
| 1991 | * flooding is disabled. |
| 1992 | */ |
| 1993 | continue; |
| 1994 | |
Andrew Lunn | 87fa886 | 2017-11-09 22:29:56 +0100 | [diff] [blame] | 1995 | err = mv88e6xxx_port_add_broadcast(chip, port, vid); |
| 1996 | if (err) |
| 1997 | return err; |
| 1998 | } |
| 1999 | |
| 2000 | return 0; |
| 2001 | } |
| 2002 | |
Tobias Waldekranz | 8d1d829 | 2021-03-18 20:25:40 +0100 | [diff] [blame] | 2003 | struct mv88e6xxx_port_broadcast_sync_ctx { |
| 2004 | int port; |
| 2005 | bool flood; |
| 2006 | }; |
| 2007 | |
| 2008 | static int |
| 2009 | mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, |
| 2010 | const struct mv88e6xxx_vtu_entry *vlan, |
| 2011 | void *_ctx) |
| 2012 | { |
| 2013 | struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; |
| 2014 | u8 broadcast[ETH_ALEN]; |
| 2015 | u8 state; |
| 2016 | |
| 2017 | if (ctx->flood) |
| 2018 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; |
| 2019 | else |
| 2020 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; |
| 2021 | |
| 2022 | eth_broadcast_addr(broadcast); |
| 2023 | |
| 2024 | return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, |
| 2025 | vlan->vid, state); |
| 2026 | } |
| 2027 | |
| 2028 | static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, |
| 2029 | bool flood) |
| 2030 | { |
| 2031 | struct mv88e6xxx_port_broadcast_sync_ctx ctx = { |
| 2032 | .port = port, |
| 2033 | .flood = flood, |
| 2034 | }; |
| 2035 | struct mv88e6xxx_vtu_entry vid0 = { |
| 2036 | .vid = 0, |
| 2037 | }; |
| 2038 | int err; |
| 2039 | |
| 2040 | /* Update the port's private database... */ |
| 2041 | err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); |
| 2042 | if (err) |
| 2043 | return err; |
| 2044 | |
| 2045 | /* ...and the database for all VLANs. */ |
| 2046 | return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, |
| 2047 | &ctx); |
| 2048 | } |
| 2049 | |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2050 | static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, |
Russell King | 933b442 | 2020-02-26 17:14:26 +0000 | [diff] [blame] | 2051 | u16 vid, u8 member, bool warn) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2052 | { |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2053 | const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
Vivien Didelot | b4e47c0 | 2016-09-29 12:21:58 -0400 | [diff] [blame] | 2054 | struct mv88e6xxx_vtu_entry vlan; |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2055 | int i, err; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 2056 | |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 2057 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 2058 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2059 | return err; |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 2060 | |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 2061 | if (!vlan.valid) { |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2062 | memset(&vlan, 0, sizeof(vlan)); |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 2063 | |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2064 | err = mv88e6xxx_atu_new(chip, &vlan.fid); |
| 2065 | if (err) |
| 2066 | return err; |
Andrew Lunn | 87fa886 | 2017-11-09 22:29:56 +0100 | [diff] [blame] | 2067 | |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2068 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
| 2069 | if (i == port) |
| 2070 | vlan.member[i] = member; |
| 2071 | else |
| 2072 | vlan.member[i] = non_member; |
| 2073 | |
| 2074 | vlan.vid = vid; |
| 2075 | vlan.valid = true; |
| 2076 | |
| 2077 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
| 2078 | if (err) |
| 2079 | return err; |
| 2080 | |
| 2081 | err = mv88e6xxx_broadcast_setup(chip, vlan.vid); |
| 2082 | if (err) |
| 2083 | return err; |
| 2084 | } else if (vlan.member[port] != member) { |
| 2085 | vlan.member[port] = member; |
| 2086 | |
| 2087 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
| 2088 | if (err) |
| 2089 | return err; |
Russell King | 933b442 | 2020-02-26 17:14:26 +0000 | [diff] [blame] | 2090 | } else if (warn) { |
Vivien Didelot | b1ac6fb | 2019-08-01 14:36:37 -0400 | [diff] [blame] | 2091 | dev_info(chip->dev, "p%d: already a member of VLAN %d\n", |
| 2092 | port, vid); |
| 2093 | } |
| 2094 | |
| 2095 | return 0; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2096 | } |
| 2097 | |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2098 | static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
Vladimir Oltean | 31046a5 | 2021-02-13 22:43:18 +0200 | [diff] [blame] | 2099 | const struct switchdev_obj_port_vlan *vlan, |
| 2100 | struct netlink_ext_ack *extack) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2101 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2102 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2103 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
| 2104 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; |
Russell King | 933b442 | 2020-02-26 17:14:26 +0000 | [diff] [blame] | 2105 | bool warn; |
Vivien Didelot | c91498e | 2017-06-07 18:12:13 -0400 | [diff] [blame] | 2106 | u8 member; |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2107 | int err; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2108 | |
Eldar Gasanov | b8b79c4 | 2021-06-21 11:54:38 +0300 | [diff] [blame] | 2109 | if (!vlan->vid) |
| 2110 | return 0; |
| 2111 | |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2112 | err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); |
| 2113 | if (err) |
| 2114 | return err; |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 2115 | |
Vivien Didelot | c91498e | 2017-06-07 18:12:13 -0400 | [diff] [blame] | 2116 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) |
Vivien Didelot | 7ec60d6e | 2017-06-15 12:14:02 -0400 | [diff] [blame] | 2117 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; |
Vivien Didelot | c91498e | 2017-06-07 18:12:13 -0400 | [diff] [blame] | 2118 | else if (untagged) |
Vivien Didelot | 7ec60d6e | 2017-06-15 12:14:02 -0400 | [diff] [blame] | 2119 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; |
Vivien Didelot | c91498e | 2017-06-07 18:12:13 -0400 | [diff] [blame] | 2120 | else |
Vivien Didelot | 7ec60d6e | 2017-06-15 12:14:02 -0400 | [diff] [blame] | 2121 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; |
Vivien Didelot | c91498e | 2017-06-07 18:12:13 -0400 | [diff] [blame] | 2122 | |
Russell King | 933b442 | 2020-02-26 17:14:26 +0000 | [diff] [blame] | 2123 | /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port |
| 2124 | * and then the CPU port. Do not warn for duplicates for the CPU port. |
| 2125 | */ |
| 2126 | warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); |
| 2127 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2128 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2129 | |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2130 | err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); |
| 2131 | if (err) { |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 2132 | dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, |
| 2133 | vlan->vid, untagged ? 'u' : 't'); |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2134 | goto out; |
| 2135 | } |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2136 | |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2137 | if (pvid) { |
| 2138 | err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid); |
| 2139 | if (err) { |
| 2140 | dev_err(ds->dev, "p%d: failed to set PVID %d\n", |
| 2141 | port, vlan->vid); |
| 2142 | goto out; |
| 2143 | } |
| 2144 | } |
| 2145 | out: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2146 | mv88e6xxx_reg_unlock(chip); |
Vladimir Oltean | 1958d58 | 2021-01-09 02:01:53 +0200 | [diff] [blame] | 2147 | |
| 2148 | return err; |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 2149 | } |
| 2150 | |
Vivien Didelot | 52109892 | 2019-08-01 14:36:36 -0400 | [diff] [blame] | 2151 | static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, |
| 2152 | int port, u16 vid) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2153 | { |
Vivien Didelot | b4e47c0 | 2016-09-29 12:21:58 -0400 | [diff] [blame] | 2154 | struct mv88e6xxx_vtu_entry vlan; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2155 | int i, err; |
| 2156 | |
Vivien Didelot | 52109892 | 2019-08-01 14:36:36 -0400 | [diff] [blame] | 2157 | if (!vid) |
| 2158 | return -EOPNOTSUPP; |
| 2159 | |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 2160 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 2161 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2162 | return err; |
Vivien Didelot | 36d04ba | 2015-10-22 09:34:39 -0400 | [diff] [blame] | 2163 | |
Vivien Didelot | 52109892 | 2019-08-01 14:36:36 -0400 | [diff] [blame] | 2164 | /* If the VLAN doesn't exist in hardware or the port isn't a member, |
| 2165 | * tell switchdev that this VLAN is likely handled in software. |
| 2166 | */ |
Tobias Waldekranz | 34065c5 | 2021-03-18 20:25:36 +0100 | [diff] [blame] | 2167 | if (!vlan.valid || |
Vivien Didelot | 52109892 | 2019-08-01 14:36:36 -0400 | [diff] [blame] | 2168 | vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
Vivien Didelot | 3c06f08 | 2016-02-05 14:04:39 -0500 | [diff] [blame] | 2169 | return -EOPNOTSUPP; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2170 | |
Vivien Didelot | 7ec60d6e | 2017-06-15 12:14:02 -0400 | [diff] [blame] | 2171 | vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2172 | |
| 2173 | /* keep the VLAN unless all ports are excluded */ |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 2174 | vlan.valid = false; |
Vivien Didelot | 370b4ff | 2016-09-29 12:21:57 -0400 | [diff] [blame] | 2175 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
Vivien Didelot | 7ec60d6e | 2017-06-15 12:14:02 -0400 | [diff] [blame] | 2176 | if (vlan.member[i] != |
| 2177 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { |
Vivien Didelot | f02bdff | 2015-10-11 18:08:36 -0400 | [diff] [blame] | 2178 | vlan.valid = true; |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2179 | break; |
| 2180 | } |
| 2181 | } |
| 2182 | |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 2183 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2184 | if (err) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2185 | return err; |
| 2186 | |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 2187 | return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2188 | } |
| 2189 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2190 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
| 2191 | const struct switchdev_obj_port_vlan *vlan) |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2192 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2193 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2194 | int err = 0; |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 2195 | u16 pvid; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2196 | |
Tobias Waldekranz | e545f86 | 2020-11-10 19:57:20 +0100 | [diff] [blame] | 2197 | if (!mv88e6xxx_max_vid(chip)) |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 2198 | return -EOPNOTSUPP; |
| 2199 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2200 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2201 | |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 2202 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2203 | if (err) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2204 | goto unlock; |
| 2205 | |
Vladimir Oltean | b7a9e0d | 2021-01-09 02:01:46 +0200 | [diff] [blame] | 2206 | err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); |
| 2207 | if (err) |
| 2208 | goto unlock; |
| 2209 | |
| 2210 | if (vlan->vid == pvid) { |
| 2211 | err = mv88e6xxx_port_set_pvid(chip, port, 0); |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2212 | if (err) |
| 2213 | goto unlock; |
Vivien Didelot | 76e398a | 2015-11-01 12:33:55 -0500 | [diff] [blame] | 2214 | } |
| 2215 | |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2216 | unlock: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2217 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 2218 | |
| 2219 | return err; |
| 2220 | } |
| 2221 | |
Arkadi Sharshevsky | 1b6dd55 | 2017-08-06 16:15:40 +0300 | [diff] [blame] | 2222 | static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
| 2223 | const unsigned char *addr, u16 vid) |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 2224 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2225 | struct mv88e6xxx_chip *chip = ds->priv; |
Arkadi Sharshevsky | 1b6dd55 | 2017-08-06 16:15:40 +0300 | [diff] [blame] | 2226 | int err; |
Vivien Didelot | 6630e23 | 2015-08-06 01:44:07 -0400 | [diff] [blame] | 2227 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2228 | mv88e6xxx_reg_lock(chip); |
Arkadi Sharshevsky | 1b6dd55 | 2017-08-06 16:15:40 +0300 | [diff] [blame] | 2229 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
| 2230 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2231 | mv88e6xxx_reg_unlock(chip); |
Arkadi Sharshevsky | 1b6dd55 | 2017-08-06 16:15:40 +0300 | [diff] [blame] | 2232 | |
| 2233 | return err; |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2234 | } |
| 2235 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2236 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
Arkadi Sharshevsky | 6c2c1dc | 2017-08-06 16:15:39 +0300 | [diff] [blame] | 2237 | const unsigned char *addr, u16 vid) |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2238 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2239 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2240 | int err; |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2241 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2242 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 2243 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2244 | mv88e6xxx_reg_unlock(chip); |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2245 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2246 | return err; |
David S. Miller | cdf0969 | 2015-08-11 12:00:37 -0700 | [diff] [blame] | 2247 | } |
| 2248 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2249 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
| 2250 | u16 fid, u16 vid, int port, |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2251 | dsa_fdb_dump_cb_t *cb, void *data) |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2252 | { |
Vivien Didelot | dabc1a9 | 2017-03-11 16:12:53 -0500 | [diff] [blame] | 2253 | struct mv88e6xxx_atu_entry addr; |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2254 | bool is_static; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2255 | int err; |
| 2256 | |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 2257 | addr.state = 0; |
Vivien Didelot | dabc1a9 | 2017-03-11 16:12:53 -0500 | [diff] [blame] | 2258 | eth_broadcast_addr(addr.mac); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2259 | |
| 2260 | do { |
Vivien Didelot | dabc1a9 | 2017-03-11 16:12:53 -0500 | [diff] [blame] | 2261 | err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2262 | if (err) |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2263 | return err; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2264 | |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 2265 | if (!addr.state) |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2266 | break; |
| 2267 | |
Vivien Didelot | 01bd96c | 2017-03-11 16:12:57 -0500 | [diff] [blame] | 2268 | if (addr.trunk || (addr.portvec & BIT(port)) == 0) |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2269 | continue; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2270 | |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2271 | if (!is_unicast_ether_addr(addr.mac)) |
| 2272 | continue; |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2273 | |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2274 | is_static = (addr.state == |
| 2275 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); |
| 2276 | err = cb(addr.mac, vid, is_static, data); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2277 | if (err) |
| 2278 | return err; |
Vivien Didelot | 74b6ba0 | 2016-02-26 13:16:02 -0500 | [diff] [blame] | 2279 | } while (!is_broadcast_ether_addr(addr.mac)); |
| 2280 | |
| 2281 | return err; |
| 2282 | } |
| 2283 | |
Tobias Waldekranz | d89ef4b | 2021-03-18 20:25:35 +0100 | [diff] [blame] | 2284 | struct mv88e6xxx_port_db_dump_vlan_ctx { |
| 2285 | int port; |
| 2286 | dsa_fdb_dump_cb_t *cb; |
| 2287 | void *data; |
| 2288 | }; |
| 2289 | |
| 2290 | static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, |
| 2291 | const struct mv88e6xxx_vtu_entry *entry, |
| 2292 | void *_data) |
| 2293 | { |
| 2294 | struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; |
| 2295 | |
| 2296 | return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, |
| 2297 | ctx->port, ctx->cb, ctx->data); |
| 2298 | } |
| 2299 | |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2300 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2301 | dsa_fdb_dump_cb_t *cb, void *data) |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2302 | { |
Tobias Waldekranz | d89ef4b | 2021-03-18 20:25:35 +0100 | [diff] [blame] | 2303 | struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { |
| 2304 | .port = port, |
| 2305 | .cb = cb, |
| 2306 | .data = data, |
| 2307 | }; |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2308 | u16 fid; |
| 2309 | int err; |
| 2310 | |
| 2311 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 2312 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2313 | if (err) |
| 2314 | return err; |
| 2315 | |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2316 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2317 | if (err) |
| 2318 | return err; |
| 2319 | |
Tobias Waldekranz | d89ef4b | 2021-03-18 20:25:35 +0100 | [diff] [blame] | 2320 | return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); |
Vivien Didelot | 83dabd1 | 2016-08-31 11:50:04 -0400 | [diff] [blame] | 2321 | } |
| 2322 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2323 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
Arkadi Sharshevsky | 2bedde1 | 2017-08-06 16:15:49 +0300 | [diff] [blame] | 2324 | dsa_fdb_dump_cb_t *cb, void *data) |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2325 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2326 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | fcf1536 | 2019-06-12 12:42:47 -0400 | [diff] [blame] | 2327 | int err; |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2328 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2329 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | fcf1536 | 2019-06-12 12:42:47 -0400 | [diff] [blame] | 2330 | err = mv88e6xxx_port_db_dump(chip, port, cb, data); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2331 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | fcf1536 | 2019-06-12 12:42:47 -0400 | [diff] [blame] | 2332 | |
| 2333 | return err; |
Vivien Didelot | f33475b | 2015-10-22 09:34:41 -0400 | [diff] [blame] | 2334 | } |
| 2335 | |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2336 | static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, |
| 2337 | struct net_device *br) |
| 2338 | { |
Vivien Didelot | ef2025e | 2019-10-21 16:51:27 -0400 | [diff] [blame] | 2339 | struct dsa_switch *ds = chip->ds; |
| 2340 | struct dsa_switch_tree *dst = ds->dst; |
| 2341 | struct dsa_port *dp; |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2342 | int err; |
| 2343 | |
Vivien Didelot | ef2025e | 2019-10-21 16:51:27 -0400 | [diff] [blame] | 2344 | list_for_each_entry(dp, &dst->ports, list) { |
| 2345 | if (dp->bridge_dev == br) { |
| 2346 | if (dp->ds == ds) { |
| 2347 | /* This is a local bridge group member, |
| 2348 | * remap its Port VLAN Map. |
| 2349 | */ |
| 2350 | err = mv88e6xxx_port_vlan_map(chip, dp->index); |
| 2351 | if (err) |
| 2352 | return err; |
| 2353 | } else { |
| 2354 | /* This is an external bridge group member, |
| 2355 | * remap its cross-chip Port VLAN Table entry. |
| 2356 | */ |
| 2357 | err = mv88e6xxx_pvt_map(chip, dp->ds->index, |
| 2358 | dp->index); |
Vivien Didelot | e96a6e0 | 2017-03-30 17:37:13 -0400 | [diff] [blame] | 2359 | if (err) |
| 2360 | return err; |
| 2361 | } |
| 2362 | } |
| 2363 | } |
| 2364 | |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2365 | return 0; |
| 2366 | } |
| 2367 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 2368 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
Vivien Didelot | fae8a25 | 2017-01-27 15:29:42 -0500 | [diff] [blame] | 2369 | struct net_device *br) |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2370 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2371 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2372 | int err; |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2373 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2374 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2375 | err = mv88e6xxx_bridge_map(chip, br); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2376 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | a669275 | 2016-02-12 12:09:39 -0500 | [diff] [blame] | 2377 | |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2378 | return err; |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2379 | } |
| 2380 | |
Vivien Didelot | f123f2f | 2017-01-27 15:29:41 -0500 | [diff] [blame] | 2381 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, |
| 2382 | struct net_device *br) |
Vivien Didelot | e79a8bc | 2015-11-04 17:23:40 -0500 | [diff] [blame] | 2383 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2384 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 466dfa0 | 2016-02-26 13:16:05 -0500 | [diff] [blame] | 2385 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2386 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2387 | if (mv88e6xxx_bridge_map(chip, br) || |
| 2388 | mv88e6xxx_port_vlan_map(chip, port)) |
| 2389 | dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2390 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 66d9cd0 | 2016-02-05 14:07:14 -0500 | [diff] [blame] | 2391 | } |
| 2392 | |
Vladimir Oltean | f66a6a6 | 2020-05-10 19:37:41 +0300 | [diff] [blame] | 2393 | static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, |
| 2394 | int tree_index, int sw_index, |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 2395 | int port, struct net_device *br) |
| 2396 | { |
| 2397 | struct mv88e6xxx_chip *chip = ds->priv; |
| 2398 | int err; |
| 2399 | |
Vladimir Oltean | f66a6a6 | 2020-05-10 19:37:41 +0300 | [diff] [blame] | 2400 | if (tree_index != ds->dst->index) |
| 2401 | return 0; |
| 2402 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2403 | mv88e6xxx_reg_lock(chip); |
Vladimir Oltean | f66a6a6 | 2020-05-10 19:37:41 +0300 | [diff] [blame] | 2404 | err = mv88e6xxx_pvt_map(chip, sw_index, port); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2405 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 2406 | |
| 2407 | return err; |
| 2408 | } |
| 2409 | |
Vladimir Oltean | f66a6a6 | 2020-05-10 19:37:41 +0300 | [diff] [blame] | 2410 | static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, |
| 2411 | int tree_index, int sw_index, |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 2412 | int port, struct net_device *br) |
| 2413 | { |
| 2414 | struct mv88e6xxx_chip *chip = ds->priv; |
| 2415 | |
Vladimir Oltean | f66a6a6 | 2020-05-10 19:37:41 +0300 | [diff] [blame] | 2416 | if (tree_index != ds->dst->index) |
| 2417 | return; |
| 2418 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2419 | mv88e6xxx_reg_lock(chip); |
Vladimir Oltean | f66a6a6 | 2020-05-10 19:37:41 +0300 | [diff] [blame] | 2420 | if (mv88e6xxx_pvt_map(chip, sw_index, port)) |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 2421 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2422 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 2423 | } |
| 2424 | |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 2425 | static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) |
| 2426 | { |
| 2427 | if (chip->info->ops->reset) |
| 2428 | return chip->info->ops->reset(chip); |
| 2429 | |
| 2430 | return 0; |
| 2431 | } |
| 2432 | |
Vivien Didelot | 309eca6 | 2016-12-05 17:30:26 -0500 | [diff] [blame] | 2433 | static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) |
| 2434 | { |
| 2435 | struct gpio_desc *gpiod = chip->reset; |
| 2436 | |
| 2437 | /* If there is a GPIO connected to the reset pin, toggle it */ |
| 2438 | if (gpiod) { |
| 2439 | gpiod_set_value_cansleep(gpiod, 1); |
| 2440 | usleep_range(10000, 20000); |
| 2441 | gpiod_set_value_cansleep(gpiod, 0); |
| 2442 | usleep_range(10000, 20000); |
Andrew Lunn | a3dcb3e | 2020-11-16 08:43:01 -0800 | [diff] [blame] | 2443 | |
| 2444 | mv88e6xxx_g1_wait_eeprom_done(chip); |
Vivien Didelot | 309eca6 | 2016-12-05 17:30:26 -0500 | [diff] [blame] | 2445 | } |
| 2446 | } |
| 2447 | |
Vivien Didelot | 4ac4b5a | 2016-12-05 17:30:25 -0500 | [diff] [blame] | 2448 | static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) |
| 2449 | { |
| 2450 | int i, err; |
| 2451 | |
| 2452 | /* Set all ports to the Disabled state */ |
| 2453 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 2454 | err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); |
Vivien Didelot | 4ac4b5a | 2016-12-05 17:30:25 -0500 | [diff] [blame] | 2455 | if (err) |
| 2456 | return err; |
| 2457 | } |
| 2458 | |
| 2459 | /* Wait for transmit queues to drain, |
| 2460 | * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. |
| 2461 | */ |
| 2462 | usleep_range(2000, 4000); |
| 2463 | |
| 2464 | return 0; |
| 2465 | } |
| 2466 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2467 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2468 | { |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 2469 | int err; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2470 | |
Vivien Didelot | 4ac4b5a | 2016-12-05 17:30:25 -0500 | [diff] [blame] | 2471 | err = mv88e6xxx_disable_ports(chip); |
| 2472 | if (err) |
| 2473 | return err; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2474 | |
Vivien Didelot | 309eca6 | 2016-12-05 17:30:26 -0500 | [diff] [blame] | 2475 | mv88e6xxx_hardware_reset(chip); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2476 | |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 2477 | return mv88e6xxx_software_reset(chip); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 2478 | } |
| 2479 | |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2480 | static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 2481 | enum mv88e6xxx_frame_mode frame, |
| 2482 | enum mv88e6xxx_egress_mode egress, u16 etype) |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 2483 | { |
| 2484 | int err; |
| 2485 | |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2486 | if (!chip->info->ops->port_set_frame_mode) |
| 2487 | return -EOPNOTSUPP; |
| 2488 | |
| 2489 | err = mv88e6xxx_port_set_egress_mode(chip, port, egress); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 2490 | if (err) |
| 2491 | return err; |
| 2492 | |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2493 | err = chip->info->ops->port_set_frame_mode(chip, port, frame); |
| 2494 | if (err) |
| 2495 | return err; |
| 2496 | |
| 2497 | if (chip->info->ops->port_set_ether_type) |
| 2498 | return chip->info->ops->port_set_ether_type(chip, port, etype); |
| 2499 | |
| 2500 | return 0; |
| 2501 | } |
| 2502 | |
| 2503 | static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) |
| 2504 | { |
| 2505 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 2506 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
Vivien Didelot | b810959 | 2017-06-12 12:37:45 -0400 | [diff] [blame] | 2507 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2508 | } |
| 2509 | |
| 2510 | static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) |
| 2511 | { |
| 2512 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 2513 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
Vivien Didelot | b810959 | 2017-06-12 12:37:45 -0400 | [diff] [blame] | 2514 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2515 | } |
| 2516 | |
| 2517 | static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) |
| 2518 | { |
| 2519 | return mv88e6xxx_set_port_mode(chip, port, |
| 2520 | MV88E6XXX_FRAME_MODE_ETHERTYPE, |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 2521 | MV88E6XXX_EGRESS_MODE_ETHERTYPE, |
| 2522 | ETH_P_EDSA); |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2523 | } |
| 2524 | |
| 2525 | static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) |
| 2526 | { |
| 2527 | if (dsa_is_dsa_port(chip->ds, port)) |
| 2528 | return mv88e6xxx_set_port_mode_dsa(chip, port); |
| 2529 | |
Vivien Didelot | 2b3e989 | 2017-10-26 11:22:54 -0400 | [diff] [blame] | 2530 | if (dsa_is_user_port(chip->ds, port)) |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2531 | return mv88e6xxx_set_port_mode_normal(chip, port); |
| 2532 | |
| 2533 | /* Setup CPU port mode depending on its supported tag format */ |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 2534 | if (chip->tag_protocol == DSA_TAG_PROTO_DSA) |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2535 | return mv88e6xxx_set_port_mode_dsa(chip, port); |
| 2536 | |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 2537 | if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2538 | return mv88e6xxx_set_port_mode_edsa(chip, port); |
| 2539 | |
| 2540 | return -EINVAL; |
| 2541 | } |
| 2542 | |
Vivien Didelot | ea698f4 | 2017-03-11 16:12:50 -0500 | [diff] [blame] | 2543 | static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) |
| 2544 | { |
| 2545 | bool message = dsa_is_dsa_port(chip->ds, port); |
| 2546 | |
| 2547 | return mv88e6xxx_port_set_message_port(chip, port, message); |
| 2548 | } |
| 2549 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 2550 | static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) |
| 2551 | { |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 2552 | int err; |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 2553 | |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 2554 | if (chip->info->ops->port_set_ucast_flood) { |
Tobias Waldekranz | 7b9f16f | 2021-03-18 20:25:38 +0100 | [diff] [blame] | 2555 | err = chip->info->ops->port_set_ucast_flood(chip, port, true); |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 2556 | if (err) |
| 2557 | return err; |
| 2558 | } |
| 2559 | if (chip->info->ops->port_set_mcast_flood) { |
Tobias Waldekranz | 7b9f16f | 2021-03-18 20:25:38 +0100 | [diff] [blame] | 2560 | err = chip->info->ops->port_set_mcast_flood(chip, port, true); |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 2561 | if (err) |
| 2562 | return err; |
| 2563 | } |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 2564 | |
David S. Miller | 407308f | 2019-06-15 13:35:29 -0700 | [diff] [blame] | 2565 | return 0; |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 2566 | } |
| 2567 | |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2568 | static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) |
| 2569 | { |
| 2570 | struct mv88e6xxx_port *mvp = dev_id; |
| 2571 | struct mv88e6xxx_chip *chip = mvp->chip; |
| 2572 | irqreturn_t ret = IRQ_NONE; |
| 2573 | int port = mvp->port; |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 2574 | int lane; |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2575 | |
| 2576 | mv88e6xxx_reg_lock(chip); |
| 2577 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 2578 | if (lane >= 0) |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2579 | ret = mv88e6xxx_serdes_irq_status(chip, port, lane); |
| 2580 | mv88e6xxx_reg_unlock(chip); |
| 2581 | |
| 2582 | return ret; |
| 2583 | } |
| 2584 | |
| 2585 | static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 2586 | int lane) |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2587 | { |
| 2588 | struct mv88e6xxx_port *dev_id = &chip->ports[port]; |
| 2589 | unsigned int irq; |
| 2590 | int err; |
| 2591 | |
| 2592 | /* Nothing to request if this SERDES port has no IRQ */ |
| 2593 | irq = mv88e6xxx_serdes_irq_mapping(chip, port); |
| 2594 | if (!irq) |
| 2595 | return 0; |
| 2596 | |
Andrew Lunn | e6f2f6b | 2020-01-06 17:13:49 +0100 | [diff] [blame] | 2597 | snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), |
| 2598 | "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); |
| 2599 | |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2600 | /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ |
| 2601 | mv88e6xxx_reg_unlock(chip); |
| 2602 | err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, |
Andrew Lunn | e6f2f6b | 2020-01-06 17:13:49 +0100 | [diff] [blame] | 2603 | IRQF_ONESHOT, dev_id->serdes_irq_name, |
| 2604 | dev_id); |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2605 | mv88e6xxx_reg_lock(chip); |
| 2606 | if (err) |
| 2607 | return err; |
| 2608 | |
| 2609 | dev_id->serdes_irq = irq; |
| 2610 | |
| 2611 | return mv88e6xxx_serdes_irq_enable(chip, port, lane); |
| 2612 | } |
| 2613 | |
| 2614 | static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 2615 | int lane) |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2616 | { |
| 2617 | struct mv88e6xxx_port *dev_id = &chip->ports[port]; |
| 2618 | unsigned int irq = dev_id->serdes_irq; |
| 2619 | int err; |
| 2620 | |
| 2621 | /* Nothing to free if no IRQ has been requested */ |
| 2622 | if (!irq) |
| 2623 | return 0; |
| 2624 | |
| 2625 | err = mv88e6xxx_serdes_irq_disable(chip, port, lane); |
| 2626 | |
| 2627 | /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ |
| 2628 | mv88e6xxx_reg_unlock(chip); |
| 2629 | free_irq(irq, dev_id); |
| 2630 | mv88e6xxx_reg_lock(chip); |
| 2631 | |
| 2632 | dev_id->serdes_irq = 0; |
| 2633 | |
| 2634 | return err; |
| 2635 | } |
| 2636 | |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 2637 | static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, |
| 2638 | bool on) |
| 2639 | { |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 2640 | int lane; |
Vivien Didelot | fc0bc01 | 2019-08-19 16:00:53 -0400 | [diff] [blame] | 2641 | int err; |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 2642 | |
Vivien Didelot | dc272f6 | 2019-08-31 16:18:33 -0400 | [diff] [blame] | 2643 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
Pavana Sharma | 193c5b2 | 2021-03-17 14:46:40 +0100 | [diff] [blame] | 2644 | if (lane < 0) |
Vivien Didelot | fc0bc01 | 2019-08-19 16:00:53 -0400 | [diff] [blame] | 2645 | return 0; |
| 2646 | |
| 2647 | if (on) { |
Vivien Didelot | dc272f6 | 2019-08-31 16:18:33 -0400 | [diff] [blame] | 2648 | err = mv88e6xxx_serdes_power_up(chip, port, lane); |
Vivien Didelot | fc0bc01 | 2019-08-19 16:00:53 -0400 | [diff] [blame] | 2649 | if (err) |
| 2650 | return err; |
| 2651 | |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2652 | err = mv88e6xxx_serdes_irq_request(chip, port, lane); |
Vivien Didelot | fc0bc01 | 2019-08-19 16:00:53 -0400 | [diff] [blame] | 2653 | } else { |
Vivien Didelot | 45de77f | 2019-08-31 16:18:36 -0400 | [diff] [blame] | 2654 | err = mv88e6xxx_serdes_irq_free(chip, port, lane); |
| 2655 | if (err) |
| 2656 | return err; |
Vivien Didelot | fc0bc01 | 2019-08-19 16:00:53 -0400 | [diff] [blame] | 2657 | |
Vivien Didelot | dc272f6 | 2019-08-31 16:18:33 -0400 | [diff] [blame] | 2658 | err = mv88e6xxx_serdes_power_down(chip, port, lane); |
Vivien Didelot | fc0bc01 | 2019-08-19 16:00:53 -0400 | [diff] [blame] | 2659 | } |
| 2660 | |
| 2661 | return err; |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 2662 | } |
| 2663 | |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 2664 | static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, |
| 2665 | enum mv88e6xxx_egress_direction direction, |
| 2666 | int port) |
| 2667 | { |
| 2668 | int err; |
| 2669 | |
| 2670 | if (!chip->info->ops->set_egress_port) |
| 2671 | return -EOPNOTSUPP; |
| 2672 | |
| 2673 | err = chip->info->ops->set_egress_port(chip, direction, port); |
| 2674 | if (err) |
| 2675 | return err; |
| 2676 | |
| 2677 | if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) |
| 2678 | chip->ingress_dest_port = port; |
| 2679 | else |
| 2680 | chip->egress_dest_port = port; |
| 2681 | |
| 2682 | return 0; |
| 2683 | } |
| 2684 | |
Vivien Didelot | fa371c8 | 2017-12-05 15:34:10 -0500 | [diff] [blame] | 2685 | static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) |
| 2686 | { |
| 2687 | struct dsa_switch *ds = chip->ds; |
| 2688 | int upstream_port; |
| 2689 | int err; |
| 2690 | |
Vivien Didelot | 07073c7 | 2017-12-05 15:34:13 -0500 | [diff] [blame] | 2691 | upstream_port = dsa_upstream_port(ds, port); |
Vivien Didelot | fa371c8 | 2017-12-05 15:34:10 -0500 | [diff] [blame] | 2692 | if (chip->info->ops->port_set_upstream_port) { |
| 2693 | err = chip->info->ops->port_set_upstream_port(chip, port, |
| 2694 | upstream_port); |
| 2695 | if (err) |
| 2696 | return err; |
| 2697 | } |
| 2698 | |
Vivien Didelot | 0ea54dd | 2017-12-05 15:34:11 -0500 | [diff] [blame] | 2699 | if (port == upstream_port) { |
| 2700 | if (chip->info->ops->set_cpu_port) { |
| 2701 | err = chip->info->ops->set_cpu_port(chip, |
| 2702 | upstream_port); |
| 2703 | if (err) |
| 2704 | return err; |
| 2705 | } |
| 2706 | |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 2707 | err = mv88e6xxx_set_egress_port(chip, |
Iwan R Timmer | 5c74c54 | 2019-11-07 22:11:13 +0100 | [diff] [blame] | 2708 | MV88E6XXX_EGRESS_DIR_INGRESS, |
| 2709 | upstream_port); |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 2710 | if (err && err != -EOPNOTSUPP) |
| 2711 | return err; |
Iwan R Timmer | 5c74c54 | 2019-11-07 22:11:13 +0100 | [diff] [blame] | 2712 | |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 2713 | err = mv88e6xxx_set_egress_port(chip, |
Iwan R Timmer | 5c74c54 | 2019-11-07 22:11:13 +0100 | [diff] [blame] | 2714 | MV88E6XXX_EGRESS_DIR_EGRESS, |
| 2715 | upstream_port); |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 2716 | if (err && err != -EOPNOTSUPP) |
| 2717 | return err; |
Vivien Didelot | 0ea54dd | 2017-12-05 15:34:11 -0500 | [diff] [blame] | 2718 | } |
| 2719 | |
Vivien Didelot | fa371c8 | 2017-12-05 15:34:10 -0500 | [diff] [blame] | 2720 | return 0; |
| 2721 | } |
| 2722 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2723 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2724 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 2725 | struct dsa_switch *ds = chip->ds; |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2726 | int err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2727 | u16 reg; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2728 | |
Andrew Lunn | 7b89846 | 2018-08-09 15:38:47 +0200 | [diff] [blame] | 2729 | chip->ports[port].chip = chip; |
| 2730 | chip->ports[port].port = port; |
| 2731 | |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 2732 | /* MAC Forcing register: don't force link, speed, duplex or flow control |
| 2733 | * state to any particular values on physical ports, but force the CPU |
| 2734 | * port and all DSA ports to their maximum bandwidth and full duplex. |
| 2735 | */ |
| 2736 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) |
| 2737 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, |
| 2738 | SPEED_MAX, DUPLEX_FULL, |
Andrew Lunn | 54186b9 | 2018-08-09 15:38:37 +0200 | [diff] [blame] | 2739 | PAUSE_OFF, |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 2740 | PHY_INTERFACE_MODE_NA); |
| 2741 | else |
| 2742 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, |
| 2743 | SPEED_UNFORCED, DUPLEX_UNFORCED, |
Andrew Lunn | 54186b9 | 2018-08-09 15:38:37 +0200 | [diff] [blame] | 2744 | PAUSE_ON, |
Vivien Didelot | d78343d | 2016-11-04 03:23:36 +0100 | [diff] [blame] | 2745 | PHY_INTERFACE_MODE_NA); |
| 2746 | if (err) |
| 2747 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2748 | |
| 2749 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
| 2750 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
| 2751 | * tunneling, determine priority by looking at 802.1p and IP |
| 2752 | * priority fields (IP prio has precedence), and set STP state |
| 2753 | * to Forwarding. |
| 2754 | * |
| 2755 | * If this is the CPU link, use DSA or EDSA tagging depending |
| 2756 | * on which tagging mode was configured. |
| 2757 | * |
| 2758 | * If this is a link to another switch, use DSA tagging mode. |
| 2759 | * |
| 2760 | * If this is the upstream port for this switch, enable |
| 2761 | * forwarding of unknown unicasts and multicasts. |
| 2762 | */ |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 2763 | reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | |
| 2764 | MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | |
| 2765 | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; |
| 2766 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 2767 | if (err) |
| 2768 | return err; |
Andrew Lunn | 6083ce7 | 2015-08-17 23:52:52 +0200 | [diff] [blame] | 2769 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 2770 | err = mv88e6xxx_setup_port_mode(chip, port); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 2771 | if (err) |
| 2772 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2773 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 2774 | err = mv88e6xxx_setup_egress_floods(chip, port); |
Vivien Didelot | 4314557 | 2017-03-11 16:12:59 -0500 | [diff] [blame] | 2775 | if (err) |
| 2776 | return err; |
| 2777 | |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2778 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
Vivien Didelot | 46fbe5e | 2016-02-26 13:16:07 -0500 | [diff] [blame] | 2779 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 2780 | * untagged frames on this port, do a destination address lookup on all |
| 2781 | * received packets as usual, disable ARP mirroring and don't send a |
| 2782 | * copy of all transmitted/received frames on this port to the CPU. |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2783 | */ |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 2784 | err = mv88e6xxx_port_set_map_da(chip, port); |
| 2785 | if (err) |
| 2786 | return err; |
| 2787 | |
Vivien Didelot | fa371c8 | 2017-12-05 15:34:10 -0500 | [diff] [blame] | 2788 | err = mv88e6xxx_setup_upstream_port(chip, port); |
| 2789 | if (err) |
| 2790 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2791 | |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 2792 | err = mv88e6xxx_port_set_8021q_mode(chip, port, |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 2793 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 2794 | if (err) |
| 2795 | return err; |
| 2796 | |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 2797 | if (chip->info->ops->port_set_jumbo_size) { |
| 2798 | err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); |
Andrew Lunn | 5f43666 | 2016-12-03 04:45:17 +0100 | [diff] [blame] | 2799 | if (err) |
| 2800 | return err; |
| 2801 | } |
| 2802 | |
Tobias Waldekranz | 041bd54 | 2021-03-18 20:25:39 +0100 | [diff] [blame] | 2803 | /* Port Association Vector: disable automatic address learning |
| 2804 | * on all user ports since they start out in standalone |
| 2805 | * mode. When joining a bridge, learning will be configured to |
| 2806 | * match the bridge port settings. Enable learning on all |
| 2807 | * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the |
| 2808 | * learning process. |
| 2809 | * |
| 2810 | * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, |
| 2811 | * and RefreshLocked. I.e. setup standard automatic learning. |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2812 | */ |
Tobias Waldekranz | 041bd54 | 2021-03-18 20:25:39 +0100 | [diff] [blame] | 2813 | if (dsa_is_user_port(ds, port)) |
Vivien Didelot | 65fa402 | 2016-04-14 14:42:07 -0400 | [diff] [blame] | 2814 | reg = 0; |
Tobias Waldekranz | 041bd54 | 2021-03-18 20:25:39 +0100 | [diff] [blame] | 2815 | else |
| 2816 | reg = 1 << port; |
Andrew Lunn | 4c7ea3c | 2015-11-03 10:52:36 -0500 | [diff] [blame] | 2817 | |
Vivien Didelot | 2a4614e | 2017-06-12 12:37:43 -0400 | [diff] [blame] | 2818 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, |
| 2819 | reg); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2820 | if (err) |
| 2821 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2822 | |
| 2823 | /* Egress rate control 2: disable egress rate control. */ |
Vivien Didelot | 2cb8cb1 | 2017-06-12 12:37:42 -0400 | [diff] [blame] | 2824 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, |
| 2825 | 0x0000); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2826 | if (err) |
| 2827 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2828 | |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 2829 | if (chip->info->ops->port_pause_limit) { |
| 2830 | err = chip->info->ops->port_pause_limit(chip, port, 0, 0); |
Andrew Lunn | b35d322a | 2016-12-03 04:45:19 +0100 | [diff] [blame] | 2831 | if (err) |
| 2832 | return err; |
| 2833 | } |
| 2834 | |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 2835 | if (chip->info->ops->port_disable_learn_limit) { |
| 2836 | err = chip->info->ops->port_disable_learn_limit(chip, port); |
| 2837 | if (err) |
| 2838 | return err; |
| 2839 | } |
| 2840 | |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 2841 | if (chip->info->ops->port_disable_pri_override) { |
| 2842 | err = chip->info->ops->port_disable_pri_override(chip, port); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2843 | if (err) |
| 2844 | return err; |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 2845 | } |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 2846 | |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 2847 | if (chip->info->ops->port_tag_remap) { |
| 2848 | err = chip->info->ops->port_tag_remap(chip, port); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2849 | if (err) |
| 2850 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2851 | } |
| 2852 | |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 2853 | if (chip->info->ops->port_egress_rate_limiting) { |
| 2854 | err = chip->info->ops->port_egress_rate_limiting(chip, port); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2855 | if (err) |
| 2856 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 2857 | } |
| 2858 | |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 2859 | if (chip->info->ops->port_setup_message_port) { |
| 2860 | err = chip->info->ops->port_setup_message_port(chip, port); |
| 2861 | if (err) |
| 2862 | return err; |
| 2863 | } |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2864 | |
Vivien Didelot | 207afda | 2016-04-14 14:42:09 -0400 | [diff] [blame] | 2865 | /* Port based VLAN map: give each port the same default address |
Vivien Didelot | b7666ef | 2016-02-26 13:16:06 -0500 | [diff] [blame] | 2866 | * database, and allow bidirectional communication between the |
| 2867 | * CPU and DSA port(s), and the other ports. |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2868 | */ |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 2869 | err = mv88e6xxx_port_set_fid(chip, port, 0); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2870 | if (err) |
| 2871 | return err; |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 2872 | |
Vivien Didelot | 240ea3e | 2017-03-30 17:37:12 -0400 | [diff] [blame] | 2873 | err = mv88e6xxx_port_vlan_map(chip, port); |
Andrew Lunn | 0e7b992 | 2016-09-21 01:40:31 +0200 | [diff] [blame] | 2874 | if (err) |
| 2875 | return err; |
Guenter Roeck | d827e88 | 2015-03-26 18:36:29 -0700 | [diff] [blame] | 2876 | |
| 2877 | /* Default VLAN ID and priority: don't set a default VLAN |
| 2878 | * ID, and set the default packet priority to zero. |
| 2879 | */ |
Vivien Didelot | b7929fb | 2017-06-12 12:37:40 -0400 | [diff] [blame] | 2880 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); |
Andrew Lunn | dbde9e6 | 2015-05-06 01:09:48 +0200 | [diff] [blame] | 2881 | } |
| 2882 | |
Andrew Lunn | 2a550ae | 2020-07-11 22:32:05 +0200 | [diff] [blame] | 2883 | static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) |
| 2884 | { |
| 2885 | struct mv88e6xxx_chip *chip = ds->priv; |
| 2886 | |
| 2887 | if (chip->info->ops->port_set_jumbo_size) |
| 2888 | return 10240; |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 2889 | else if (chip->info->ops->set_max_frame_size) |
| 2890 | return 1632; |
Andrew Lunn | 2a550ae | 2020-07-11 22:32:05 +0200 | [diff] [blame] | 2891 | return 1522; |
| 2892 | } |
| 2893 | |
| 2894 | static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) |
| 2895 | { |
| 2896 | struct mv88e6xxx_chip *chip = ds->priv; |
| 2897 | int ret = 0; |
| 2898 | |
| 2899 | mv88e6xxx_reg_lock(chip); |
| 2900 | if (chip->info->ops->port_set_jumbo_size) |
| 2901 | ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 2902 | else if (chip->info->ops->set_max_frame_size) |
| 2903 | ret = chip->info->ops->set_max_frame_size(chip, new_mtu); |
Andrew Lunn | 2a550ae | 2020-07-11 22:32:05 +0200 | [diff] [blame] | 2904 | else |
| 2905 | if (new_mtu > 1522) |
| 2906 | ret = -EINVAL; |
| 2907 | mv88e6xxx_reg_unlock(chip); |
| 2908 | |
| 2909 | return ret; |
| 2910 | } |
| 2911 | |
Andrew Lunn | 04aca99 | 2017-05-26 01:03:24 +0200 | [diff] [blame] | 2912 | static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, |
| 2913 | struct phy_device *phydev) |
| 2914 | { |
| 2915 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 523a890 | 2017-05-26 18:02:42 -0400 | [diff] [blame] | 2916 | int err; |
Andrew Lunn | 04aca99 | 2017-05-26 01:03:24 +0200 | [diff] [blame] | 2917 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2918 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 523a890 | 2017-05-26 18:02:42 -0400 | [diff] [blame] | 2919 | err = mv88e6xxx_serdes_power(chip, port, true); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2920 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 04aca99 | 2017-05-26 01:03:24 +0200 | [diff] [blame] | 2921 | |
| 2922 | return err; |
| 2923 | } |
| 2924 | |
Andrew Lunn | 75104db | 2019-02-24 20:44:43 +0100 | [diff] [blame] | 2925 | static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) |
Andrew Lunn | 04aca99 | 2017-05-26 01:03:24 +0200 | [diff] [blame] | 2926 | { |
| 2927 | struct mv88e6xxx_chip *chip = ds->priv; |
| 2928 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2929 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 523a890 | 2017-05-26 18:02:42 -0400 | [diff] [blame] | 2930 | if (mv88e6xxx_serdes_power(chip, port, false)) |
| 2931 | dev_err(chip->dev, "failed to power off SERDES\n"); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2932 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 04aca99 | 2017-05-26 01:03:24 +0200 | [diff] [blame] | 2933 | } |
| 2934 | |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 2935 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
| 2936 | unsigned int ageing_time) |
| 2937 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 2938 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 2939 | int err; |
| 2940 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2941 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 720c634 | 2017-03-11 16:12:48 -0500 | [diff] [blame] | 2942 | err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 2943 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 2944 | |
| 2945 | return err; |
| 2946 | } |
| 2947 | |
Vivien Didelot | 447b1bb | 2018-05-11 17:16:36 -0400 | [diff] [blame] | 2948 | static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2949 | { |
| 2950 | int err; |
Vivien Didelot | 08a0126 | 2016-05-09 13:22:50 -0400 | [diff] [blame] | 2951 | |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 2952 | /* Initialize the statistics unit */ |
Vivien Didelot | 447b1bb | 2018-05-11 17:16:36 -0400 | [diff] [blame] | 2953 | if (chip->info->ops->stats_set_histogram) { |
| 2954 | err = chip->info->ops->stats_set_histogram(chip); |
| 2955 | if (err) |
| 2956 | return err; |
| 2957 | } |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 2958 | |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 2959 | return mv88e6xxx_g1_stats_clear(chip); |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 2960 | } |
| 2961 | |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 2962 | /* Check if the errata has already been applied. */ |
| 2963 | static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) |
| 2964 | { |
| 2965 | int port; |
| 2966 | int err; |
| 2967 | u16 val; |
| 2968 | |
| 2969 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
Marek Behún | 6090701 | 2019-08-26 23:31:51 +0200 | [diff] [blame] | 2970 | err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 2971 | if (err) { |
| 2972 | dev_err(chip->dev, |
| 2973 | "Error reading hidden register: %d\n", err); |
| 2974 | return false; |
| 2975 | } |
| 2976 | if (val != 0x01c0) |
| 2977 | return false; |
| 2978 | } |
| 2979 | |
| 2980 | return true; |
| 2981 | } |
| 2982 | |
| 2983 | /* The 6390 copper ports have an errata which require poking magic |
| 2984 | * values into undocumented hidden registers and then performing a |
| 2985 | * software reset. |
| 2986 | */ |
| 2987 | static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) |
| 2988 | { |
| 2989 | int port; |
| 2990 | int err; |
| 2991 | |
| 2992 | if (mv88e6390_setup_errata_applied(chip)) |
| 2993 | return 0; |
| 2994 | |
| 2995 | /* Set the ports into blocking mode */ |
| 2996 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
| 2997 | err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); |
| 2998 | if (err) |
| 2999 | return err; |
| 3000 | } |
| 3001 | |
| 3002 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
Marek Behún | 6090701 | 2019-08-26 23:31:51 +0200 | [diff] [blame] | 3003 | err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 3004 | if (err) |
| 3005 | return err; |
| 3006 | } |
| 3007 | |
| 3008 | return mv88e6xxx_software_reset(chip); |
| 3009 | } |
| 3010 | |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3011 | static void mv88e6xxx_teardown(struct dsa_switch *ds) |
| 3012 | { |
| 3013 | mv88e6xxx_teardown_devlink_params(ds); |
Andrew Lunn | e0c69ca | 2019-11-05 01:13:01 +0100 | [diff] [blame] | 3014 | dsa_devlink_resources_unregister(ds); |
Andrew Lunn | bfb2554 | 2020-09-18 21:11:07 +0200 | [diff] [blame] | 3015 | mv88e6xxx_teardown_devlink_regions(ds); |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3016 | } |
| 3017 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 3018 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
Guenter Roeck | acdaffc | 2015-03-26 18:36:28 -0700 | [diff] [blame] | 3019 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3020 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3021 | u8 cmode; |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 3022 | int err; |
Vivien Didelot | a1a6a4d | 2016-05-09 13:22:56 -0400 | [diff] [blame] | 3023 | int i; |
| 3024 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3025 | chip->ds = ds; |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3026 | ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 3027 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3028 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 3029 | |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 3030 | if (chip->info->ops->setup_errata) { |
| 3031 | err = chip->info->ops->setup_errata(chip); |
| 3032 | if (err) |
| 3033 | goto unlock; |
| 3034 | } |
| 3035 | |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3036 | /* Cache the cmode of each port. */ |
| 3037 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
| 3038 | if (chip->info->ops->port_get_cmode) { |
| 3039 | err = chip->info->ops->port_get_cmode(chip, i, &cmode); |
| 3040 | if (err) |
Dan Carpenter | e29129f | 2018-08-14 12:09:05 +0300 | [diff] [blame] | 3041 | goto unlock; |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3042 | |
| 3043 | chip->ports[i].cmode = cmode; |
| 3044 | } |
| 3045 | } |
| 3046 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3047 | /* Setup Switch Port Registers */ |
Vivien Didelot | 370b4ff | 2016-09-29 12:21:57 -0400 | [diff] [blame] | 3048 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
Vivien Didelot | b759f52 | 2019-08-19 16:00:52 -0400 | [diff] [blame] | 3049 | if (dsa_is_unused_port(ds, i)) |
| 3050 | continue; |
| 3051 | |
Hubert Feurstein | c857486 | 2019-07-31 10:23:48 +0200 | [diff] [blame] | 3052 | /* Prevent the use of an invalid port. */ |
Vivien Didelot | b759f52 | 2019-08-19 16:00:52 -0400 | [diff] [blame] | 3053 | if (mv88e6xxx_is_invalid_port(chip, i)) { |
Hubert Feurstein | c857486 | 2019-07-31 10:23:48 +0200 | [diff] [blame] | 3054 | dev_err(chip->dev, "port %d is invalid\n", i); |
| 3055 | err = -EINVAL; |
| 3056 | goto unlock; |
| 3057 | } |
| 3058 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 3059 | err = mv88e6xxx_setup_port(chip, i); |
| 3060 | if (err) |
| 3061 | goto unlock; |
| 3062 | } |
| 3063 | |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3064 | err = mv88e6xxx_irl_setup(chip); |
| 3065 | if (err) |
| 3066 | goto unlock; |
| 3067 | |
Vivien Didelot | 04a69a1 | 2017-10-13 14:18:05 -0400 | [diff] [blame] | 3068 | err = mv88e6xxx_mac_setup(chip); |
| 3069 | if (err) |
| 3070 | goto unlock; |
| 3071 | |
Vivien Didelot | 1b17aed | 2017-05-26 18:03:05 -0400 | [diff] [blame] | 3072 | err = mv88e6xxx_phy_setup(chip); |
| 3073 | if (err) |
| 3074 | goto unlock; |
| 3075 | |
Vivien Didelot | b486d7c | 2017-05-01 14:05:13 -0400 | [diff] [blame] | 3076 | err = mv88e6xxx_vtu_setup(chip); |
| 3077 | if (err) |
| 3078 | goto unlock; |
| 3079 | |
Vivien Didelot | 8122899 | 2017-03-30 17:37:08 -0400 | [diff] [blame] | 3080 | err = mv88e6xxx_pvt_setup(chip); |
| 3081 | if (err) |
| 3082 | goto unlock; |
| 3083 | |
Vivien Didelot | a2ac29d | 2017-03-11 16:12:49 -0500 | [diff] [blame] | 3084 | err = mv88e6xxx_atu_setup(chip); |
| 3085 | if (err) |
| 3086 | goto unlock; |
| 3087 | |
Andrew Lunn | 87fa886 | 2017-11-09 22:29:56 +0100 | [diff] [blame] | 3088 | err = mv88e6xxx_broadcast_setup(chip, 0); |
| 3089 | if (err) |
| 3090 | goto unlock; |
| 3091 | |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3092 | err = mv88e6xxx_pot_setup(chip); |
| 3093 | if (err) |
| 3094 | goto unlock; |
| 3095 | |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 3096 | err = mv88e6xxx_rmu_setup(chip); |
| 3097 | if (err) |
| 3098 | goto unlock; |
| 3099 | |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3100 | err = mv88e6xxx_rsvd2cpu_setup(chip); |
| 3101 | if (err) |
| 3102 | goto unlock; |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 3103 | |
Vivien Didelot | b28f872 | 2018-04-26 21:56:44 -0400 | [diff] [blame] | 3104 | err = mv88e6xxx_trunk_setup(chip); |
| 3105 | if (err) |
| 3106 | goto unlock; |
| 3107 | |
Vivien Didelot | c7f047b | 2018-04-26 21:56:45 -0400 | [diff] [blame] | 3108 | err = mv88e6xxx_devmap_setup(chip); |
| 3109 | if (err) |
| 3110 | goto unlock; |
| 3111 | |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3112 | err = mv88e6xxx_pri_setup(chip); |
| 3113 | if (err) |
| 3114 | goto unlock; |
| 3115 | |
Brandon Streiff | c6fe0ad | 2018-02-14 01:07:50 +0100 | [diff] [blame] | 3116 | /* Setup PTP Hardware Clock and timestamping */ |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 3117 | if (chip->info->ptp_support) { |
| 3118 | err = mv88e6xxx_ptp_setup(chip); |
| 3119 | if (err) |
| 3120 | goto unlock; |
Brandon Streiff | c6fe0ad | 2018-02-14 01:07:50 +0100 | [diff] [blame] | 3121 | |
| 3122 | err = mv88e6xxx_hwtstamp_setup(chip); |
| 3123 | if (err) |
| 3124 | goto unlock; |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 3125 | } |
| 3126 | |
Vivien Didelot | 447b1bb | 2018-05-11 17:16:36 -0400 | [diff] [blame] | 3127 | err = mv88e6xxx_stats_setup(chip); |
| 3128 | if (err) |
| 3129 | goto unlock; |
| 3130 | |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 3131 | unlock: |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3132 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | db687a5 | 2015-06-20 21:31:29 +0200 | [diff] [blame] | 3133 | |
Andrew Lunn | e0c69ca | 2019-11-05 01:13:01 +0100 | [diff] [blame] | 3134 | if (err) |
| 3135 | return err; |
| 3136 | |
| 3137 | /* Have to be called without holding the register lock, since |
| 3138 | * they take the devlink lock, and we later take the locks in |
| 3139 | * the reverse order when getting/setting parameters or |
| 3140 | * resource occupancy. |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3141 | */ |
Andrew Lunn | e0c69ca | 2019-11-05 01:13:01 +0100 | [diff] [blame] | 3142 | err = mv88e6xxx_setup_devlink_resources(ds); |
| 3143 | if (err) |
| 3144 | return err; |
| 3145 | |
| 3146 | err = mv88e6xxx_setup_devlink_params(ds); |
| 3147 | if (err) |
Andrew Lunn | bfb2554 | 2020-09-18 21:11:07 +0200 | [diff] [blame] | 3148 | goto out_resources; |
| 3149 | |
| 3150 | err = mv88e6xxx_setup_devlink_regions(ds); |
| 3151 | if (err) |
| 3152 | goto out_params; |
| 3153 | |
| 3154 | return 0; |
| 3155 | |
| 3156 | out_params: |
| 3157 | mv88e6xxx_teardown_devlink_params(ds); |
| 3158 | out_resources: |
| 3159 | dsa_devlink_resources_unregister(ds); |
Andrew Lunn | e0c69ca | 2019-11-05 01:13:01 +0100 | [diff] [blame] | 3160 | |
| 3161 | return err; |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 3162 | } |
| 3163 | |
Pali Rohár | 1fe976d | 2021-04-12 18:57:39 +0200 | [diff] [blame] | 3164 | /* prod_id for switch families which do not have a PHY model number */ |
| 3165 | static const u16 family_prod_id_table[] = { |
| 3166 | [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
| 3167 | [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
Marek Behún | c5d015b | 2021-04-20 09:54:02 +0200 | [diff] [blame] | 3168 | [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, |
Pali Rohár | 1fe976d | 2021-04-12 18:57:39 +0200 | [diff] [blame] | 3169 | }; |
| 3170 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3171 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3172 | { |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3173 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
| 3174 | struct mv88e6xxx_chip *chip = mdio_bus->chip; |
Pali Rohár | 1fe976d | 2021-04-12 18:57:39 +0200 | [diff] [blame] | 3175 | u16 prod_id; |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3176 | u16 val; |
| 3177 | int err; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3178 | |
Andrew Lunn | ee26a22 | 2017-01-24 14:53:48 +0100 | [diff] [blame] | 3179 | if (!chip->info->ops->phy_read) |
| 3180 | return -EOPNOTSUPP; |
| 3181 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3182 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | ee26a22 | 2017-01-24 14:53:48 +0100 | [diff] [blame] | 3183 | err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3184 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3185 | |
Pali Rohár | 1fe976d | 2021-04-12 18:57:39 +0200 | [diff] [blame] | 3186 | /* Some internal PHYs don't have a model number. */ |
| 3187 | if (reg == MII_PHYSID2 && !(val & 0x3f0) && |
| 3188 | chip->info->family < ARRAY_SIZE(family_prod_id_table)) { |
| 3189 | prod_id = family_prod_id_table[chip->info->family]; |
| 3190 | if (prod_id) |
| 3191 | val |= prod_id >> 4; |
Andrew Lunn | da9f330 | 2017-02-01 03:40:05 +0100 | [diff] [blame] | 3192 | } |
| 3193 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3194 | return err ? err : val; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3195 | } |
| 3196 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3197 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3198 | { |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3199 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
| 3200 | struct mv88e6xxx_chip *chip = mdio_bus->chip; |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3201 | int err; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3202 | |
Andrew Lunn | ee26a22 | 2017-01-24 14:53:48 +0100 | [diff] [blame] | 3203 | if (!chip->info->ops->phy_write) |
| 3204 | return -EOPNOTSUPP; |
| 3205 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3206 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | ee26a22 | 2017-01-24 14:53:48 +0100 | [diff] [blame] | 3207 | err = chip->info->ops->phy_write(chip, bus, phy, reg, val); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3208 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 3209 | |
| 3210 | return err; |
Andrew Lunn | fd3a0ee | 2015-04-02 04:06:36 +0200 | [diff] [blame] | 3211 | } |
| 3212 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3213 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3214 | struct device_node *np, |
| 3215 | bool external) |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3216 | { |
| 3217 | static int index; |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3218 | struct mv88e6xxx_mdio_bus *mdio_bus; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3219 | struct mii_bus *bus; |
| 3220 | int err; |
| 3221 | |
Andrew Lunn | 2510bab | 2018-02-22 01:51:49 +0100 | [diff] [blame] | 3222 | if (external) { |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3223 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | 2510bab | 2018-02-22 01:51:49 +0100 | [diff] [blame] | 3224 | err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3225 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | 2510bab | 2018-02-22 01:51:49 +0100 | [diff] [blame] | 3226 | |
| 3227 | if (err) |
| 3228 | return err; |
| 3229 | } |
| 3230 | |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3231 | bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3232 | if (!bus) |
| 3233 | return -ENOMEM; |
| 3234 | |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3235 | mdio_bus = bus->priv; |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3236 | mdio_bus->bus = bus; |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3237 | mdio_bus->chip = chip; |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3238 | INIT_LIST_HEAD(&mdio_bus->list); |
| 3239 | mdio_bus->external = external; |
Andrew Lunn | 0dd12d5 | 2017-01-24 14:53:49 +0100 | [diff] [blame] | 3240 | |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3241 | if (np) { |
| 3242 | bus->name = np->full_name; |
Rob Herring | f7ce910 | 2017-07-18 16:43:19 -0500 | [diff] [blame] | 3243 | snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3244 | } else { |
| 3245 | bus->name = "mv88e6xxx SMI"; |
| 3246 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); |
| 3247 | } |
| 3248 | |
| 3249 | bus->read = mv88e6xxx_mdio_read; |
| 3250 | bus->write = mv88e6xxx_mdio_write; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3251 | bus->parent = chip->dev; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3252 | |
Andrew Lunn | 6f88284 | 2018-03-17 20:32:05 +0100 | [diff] [blame] | 3253 | if (!external) { |
| 3254 | err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); |
| 3255 | if (err) |
| 3256 | return err; |
| 3257 | } |
| 3258 | |
Florian Fainelli | 00e798c | 2018-05-15 16:56:19 -0700 | [diff] [blame] | 3259 | err = of_mdiobus_register(bus, np); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3260 | if (err) { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 3261 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
Andrew Lunn | 6f88284 | 2018-03-17 20:32:05 +0100 | [diff] [blame] | 3262 | mv88e6xxx_g2_irq_mdio_free(chip, bus); |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3263 | return err; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3264 | } |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3265 | |
| 3266 | if (external) |
| 3267 | list_add_tail(&mdio_bus->list, &chip->mdios); |
| 3268 | else |
| 3269 | list_add(&mdio_bus->list, &chip->mdios); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3270 | |
| 3271 | return 0; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 3272 | } |
| 3273 | |
Andrew Lunn | 3126aee | 2017-12-07 01:05:57 +0100 | [diff] [blame] | 3274 | static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) |
| 3275 | |
| 3276 | { |
| 3277 | struct mv88e6xxx_mdio_bus *mdio_bus; |
| 3278 | struct mii_bus *bus; |
| 3279 | |
| 3280 | list_for_each_entry(mdio_bus, &chip->mdios, list) { |
| 3281 | bus = mdio_bus->bus; |
| 3282 | |
Andrew Lunn | 6f88284 | 2018-03-17 20:32:05 +0100 | [diff] [blame] | 3283 | if (!mdio_bus->external) |
| 3284 | mv88e6xxx_g2_irq_mdio_free(chip, bus); |
| 3285 | |
Andrew Lunn | 3126aee | 2017-12-07 01:05:57 +0100 | [diff] [blame] | 3286 | mdiobus_unregister(bus); |
| 3287 | } |
| 3288 | } |
| 3289 | |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3290 | static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, |
| 3291 | struct device_node *np) |
| 3292 | { |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3293 | struct device_node *child; |
| 3294 | int err; |
| 3295 | |
| 3296 | /* Always register one mdio bus for the internal/default mdio |
| 3297 | * bus. This maybe represented in the device tree, but is |
| 3298 | * optional. |
| 3299 | */ |
| 3300 | child = of_get_child_by_name(np, "mdio"); |
| 3301 | err = mv88e6xxx_mdio_register(chip, child, false); |
| 3302 | if (err) |
| 3303 | return err; |
| 3304 | |
| 3305 | /* Walk the device tree, and see if there are any other nodes |
| 3306 | * which say they are compatible with the external mdio |
| 3307 | * bus. |
| 3308 | */ |
| 3309 | for_each_available_child_of_node(np, child) { |
Andrew Lunn | ceb96fa | 2020-09-01 04:32:57 +0200 | [diff] [blame] | 3310 | if (of_device_is_compatible( |
| 3311 | child, "marvell,mv88e6xxx-mdio-external")) { |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3312 | err = mv88e6xxx_mdio_register(chip, child, true); |
Andrew Lunn | 3126aee | 2017-12-07 01:05:57 +0100 | [diff] [blame] | 3313 | if (err) { |
| 3314 | mv88e6xxx_mdios_unregister(chip); |
Nishka Dasgupta | 78e4204 | 2019-07-23 16:13:07 +0530 | [diff] [blame] | 3315 | of_node_put(child); |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3316 | return err; |
Andrew Lunn | 3126aee | 2017-12-07 01:05:57 +0100 | [diff] [blame] | 3317 | } |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 3318 | } |
| 3319 | } |
| 3320 | |
| 3321 | return 0; |
| 3322 | } |
| 3323 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3324 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
| 3325 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3326 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3327 | |
| 3328 | return chip->eeprom_len; |
| 3329 | } |
| 3330 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3331 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
| 3332 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3333 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3334 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3335 | int err; |
| 3336 | |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 3337 | if (!chip->info->ops->get_eeprom) |
| 3338 | return -EOPNOTSUPP; |
| 3339 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3340 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 3341 | err = chip->info->ops->get_eeprom(chip, eeprom, data); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3342 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3343 | |
| 3344 | if (err) |
| 3345 | return err; |
| 3346 | |
| 3347 | eeprom->magic = 0xc3ec4951; |
| 3348 | |
| 3349 | return 0; |
| 3350 | } |
| 3351 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3352 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
| 3353 | struct ethtool_eeprom *eeprom, u8 *data) |
| 3354 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 3355 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3356 | int err; |
| 3357 | |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 3358 | if (!chip->info->ops->set_eeprom) |
| 3359 | return -EOPNOTSUPP; |
| 3360 | |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3361 | if (eeprom->magic != 0xc3ec4951) |
| 3362 | return -EINVAL; |
| 3363 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3364 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 3365 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 3366 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 3367 | |
| 3368 | return err; |
| 3369 | } |
| 3370 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3371 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3372 | /* MV88E6XXX_FAMILY_6097 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3373 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3374 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3375 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3376 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
Vivien Didelot | 7e20cfb | 2017-05-26 18:03:06 -0400 | [diff] [blame] | 3377 | .phy_read = mv88e6185_phy_ppu_read, |
| 3378 | .phy_write = mv88e6185_phy_ppu_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3379 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3380 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3381 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3382 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3383 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3384 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3385 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3386 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3387 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3388 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3389 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3390 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3391 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3392 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3393 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3394 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3395 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3396 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3397 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3398 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3399 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3400 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3401 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3402 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | a199d8b | 2016-12-05 17:30:28 -0500 | [diff] [blame] | 3403 | .ppu_enable = mv88e6185_g1_ppu_enable, |
| 3404 | .ppu_disable = mv88e6185_g1_ppu_disable, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3405 | .reset = mv88e6185_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 3406 | .rmu_disable = mv88e6085_g1_rmu_disable, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3407 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3408 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3409 | .phylink_validate = mv88e6185_phylink_validate, |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 3410 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3411 | }; |
| 3412 | |
| 3413 | static const struct mv88e6xxx_ops mv88e6095_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3414 | /* MV88E6XXX_FAMILY_6095 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3415 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3416 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3417 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
Vivien Didelot | 7e20cfb | 2017-05-26 18:03:06 -0400 | [diff] [blame] | 3418 | .phy_read = mv88e6185_phy_ppu_read, |
| 3419 | .phy_write = mv88e6185_phy_ppu_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3420 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3421 | .port_sync_link = mv88e6185_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3422 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3423 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3424 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
| 3425 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 3426 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3427 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3428 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3429 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3430 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3431 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3432 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3433 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3434 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
Chris Packham | f5be107 | 2020-11-24 17:34:38 +1300 | [diff] [blame] | 3435 | .serdes_power = mv88e6185_serdes_power, |
| 3436 | .serdes_get_lane = mv88e6185_serdes_get_lane, |
| 3437 | .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, |
Vivien Didelot | a199d8b | 2016-12-05 17:30:28 -0500 | [diff] [blame] | 3438 | .ppu_enable = mv88e6185_g1_ppu_enable, |
| 3439 | .ppu_disable = mv88e6185_g1_ppu_disable, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3440 | .reset = mv88e6185_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3441 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3442 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3443 | .phylink_validate = mv88e6185_phylink_validate, |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 3444 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3445 | }; |
| 3446 | |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 3447 | static const struct mv88e6xxx_ops mv88e6097_ops = { |
Stefan Eichenberger | 15da3cc | 2016-11-25 09:41:30 +0100 | [diff] [blame] | 3448 | /* MV88E6XXX_FAMILY_6097 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3449 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3450 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3451 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 3452 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 3453 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3454 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 3455 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3456 | .port_sync_link = mv88e6185_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3457 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3458 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3459 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3460 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3461 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3462 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3463 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3464 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3465 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3466 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3467 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3468 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 3469 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3470 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 3471 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3472 | .stats_get_strings = mv88e6095_stats_get_strings, |
| 3473 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3474 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3475 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Volodymyr Bendiuga | 91eaa47 | 2017-02-14 11:29:30 +0100 | [diff] [blame] | 3476 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3477 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Chris Packham | f5be107 | 2020-11-24 17:34:38 +1300 | [diff] [blame] | 3478 | .serdes_power = mv88e6185_serdes_power, |
| 3479 | .serdes_get_lane = mv88e6185_serdes_get_lane, |
| 3480 | .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, |
Chris Packham | 5c19bc8 | 2020-11-24 17:34:39 +1300 | [diff] [blame] | 3481 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
| 3482 | .serdes_irq_enable = mv88e6097_serdes_irq_enable, |
| 3483 | .serdes_irq_status = mv88e6097_serdes_irq_status, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3484 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3485 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 3486 | .rmu_disable = mv88e6085_g1_rmu_disable, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3487 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3488 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3489 | .phylink_validate = mv88e6185_phylink_validate, |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 3490 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 3491 | }; |
| 3492 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3493 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3494 | /* MV88E6XXX_FAMILY_6165 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3495 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3496 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3497 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3498 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Andrew Lunn | ec8378b | 2017-06-02 23:22:45 +0200 | [diff] [blame] | 3499 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3500 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3501 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3502 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3503 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3504 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3505 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3506 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3507 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3508 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3509 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3510 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 0ac64c3 | 2017-06-02 23:22:46 +0200 | [diff] [blame] | 3511 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3512 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3513 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3514 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3515 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3516 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3517 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3518 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3519 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3520 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3521 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3522 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3523 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3524 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3525 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3526 | .phylink_validate = mv88e6185_phylink_validate, |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 3527 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3528 | }; |
| 3529 | |
| 3530 | static const struct mv88e6xxx_ops mv88e6131_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3531 | /* MV88E6XXX_FAMILY_6185 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3532 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3533 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3534 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
Vivien Didelot | 7e20cfb | 2017-05-26 18:03:06 -0400 | [diff] [blame] | 3535 | .phy_read = mv88e6185_phy_ppu_read, |
| 3536 | .phy_write = mv88e6185_phy_ppu_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3537 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3538 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3539 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3540 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3541 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3542 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
| 3543 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3544 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 3545 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3546 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3547 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3548 | .port_pause_limit = mv88e6097_port_pause_limit, |
Andrew Lunn | 54186b9 | 2018-08-09 15:38:37 +0200 | [diff] [blame] | 3549 | .port_set_pause = mv88e6185_port_set_pause, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3550 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3551 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3552 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3553 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3554 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3555 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3556 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3557 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3558 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3559 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3560 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
Vivien Didelot | a199d8b | 2016-12-05 17:30:28 -0500 | [diff] [blame] | 3561 | .ppu_enable = mv88e6185_g1_ppu_enable, |
Vivien Didelot | 02317e6 | 2018-05-09 11:38:49 -0400 | [diff] [blame] | 3562 | .set_cascade_port = mv88e6185_g1_set_cascade_port, |
Vivien Didelot | a199d8b | 2016-12-05 17:30:28 -0500 | [diff] [blame] | 3563 | .ppu_disable = mv88e6185_g1_ppu_disable, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3564 | .reset = mv88e6185_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3565 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3566 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3567 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3568 | }; |
| 3569 | |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3570 | static const struct mv88e6xxx_ops mv88e6141_ops = { |
| 3571 | /* MV88E6XXX_FAMILY_6341 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3572 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3573 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3574 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3575 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 3576 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
| 3577 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 3578 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3579 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 3580 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3581 | .port_sync_link = mv88e6xxx_port_sync_link, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3582 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3583 | .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 3584 | .port_max_speed_mode = mv88e6341_port_max_speed_mode, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3585 | .port_tag_remap = mv88e6095_port_tag_remap, |
Marek Behún | 7da467d | 2021-07-01 00:22:26 +0200 | [diff] [blame^] | 3586 | .port_set_policy = mv88e6352_port_set_policy, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3587 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3588 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3589 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3590 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3591 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3592 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3593 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3594 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
| 3595 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3596 | .port_get_cmode = mv88e6352_port_get_cmode, |
Marek Behún | 7a3007d | 2019-08-26 23:31:55 +0200 | [diff] [blame] | 3597 | .port_set_cmode = mv88e6341_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3598 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3599 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3600 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3601 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 3602 | .stats_get_strings = mv88e6320_stats_get_strings, |
| 3603 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3604 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 3605 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3606 | .watchdog_ops = &mv88e6390_watchdog_ops, |
| 3607 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3608 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3609 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3610 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3611 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Marek Behún | d3cf7d8 | 2019-08-26 23:31:53 +0200 | [diff] [blame] | 3612 | .serdes_power = mv88e6390_serdes_power, |
| 3613 | .serdes_get_lane = mv88e6341_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 3614 | /* Check status register pause & lpa register */ |
| 3615 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 3616 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 3617 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 3618 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 3619 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 3620 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 3621 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 3622 | .gpio_ops = &mv88e6352_gpio_ops, |
Marek Behún | e3af71a | 2019-02-25 12:39:55 +0100 | [diff] [blame] | 3623 | .phylink_validate = mv88e6341_phylink_validate, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 3624 | }; |
| 3625 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3626 | static const struct mv88e6xxx_ops mv88e6161_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3627 | /* MV88E6XXX_FAMILY_6165 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3628 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3629 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3630 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3631 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Andrew Lunn | ec8378b | 2017-06-02 23:22:45 +0200 | [diff] [blame] | 3632 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3633 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3634 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3635 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3636 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3637 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3638 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3639 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3640 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3641 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3642 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3643 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3644 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3645 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3646 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3647 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3648 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a6da21b | 2019-03-01 23:43:39 +0100 | [diff] [blame] | 3649 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3650 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3651 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3652 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3653 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3654 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3655 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3656 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3657 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3658 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3659 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3660 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3661 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3662 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3663 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Andrew Lunn | a469a61 | 2018-07-18 22:38:21 +0200 | [diff] [blame] | 3664 | .avb_ops = &mv88e6165_avb_ops, |
Andrew Lunn | dfa5434 | 2018-07-18 22:38:22 +0200 | [diff] [blame] | 3665 | .ptp_ops = &mv88e6165_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3666 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3667 | }; |
| 3668 | |
| 3669 | static const struct mv88e6xxx_ops mv88e6165_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3670 | /* MV88E6XXX_FAMILY_6165 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3671 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3672 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3673 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3674 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Andrew Lunn | efb3e74 | 2017-01-24 14:53:47 +0100 | [diff] [blame] | 3675 | .phy_read = mv88e6165_phy_read, |
| 3676 | .phy_write = mv88e6165_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3677 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3678 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3679 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3680 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3681 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3682 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3683 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3684 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3685 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3686 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3687 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3688 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3689 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3690 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3691 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3692 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3693 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3694 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3695 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3696 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3697 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3698 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Andrew Lunn | a469a61 | 2018-07-18 22:38:21 +0200 | [diff] [blame] | 3699 | .avb_ops = &mv88e6165_avb_ops, |
Andrew Lunn | dfa5434 | 2018-07-18 22:38:22 +0200 | [diff] [blame] | 3700 | .ptp_ops = &mv88e6165_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3701 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3702 | }; |
| 3703 | |
| 3704 | static const struct mv88e6xxx_ops mv88e6171_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3705 | /* MV88E6XXX_FAMILY_6351 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3706 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3707 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3708 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3709 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3710 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3711 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3712 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3713 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 94d66ae | 2016-11-10 15:44:01 +0100 | [diff] [blame] | 3714 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3715 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3716 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3717 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3718 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3719 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3720 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3721 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3722 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3723 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3724 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3725 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3726 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3727 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3728 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3729 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3730 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3731 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3732 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3733 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3734 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3735 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3736 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3737 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3738 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3739 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3740 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3741 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3742 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3743 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3744 | }; |
| 3745 | |
| 3746 | static const struct mv88e6xxx_ops mv88e6172_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3747 | /* MV88E6XXX_FAMILY_6352 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3748 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3749 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3750 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 3751 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 3752 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3753 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3754 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3755 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3756 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3757 | .port_sync_link = mv88e6xxx_port_sync_link, |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 3758 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3759 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3760 | .port_tag_remap = mv88e6095_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 3761 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3762 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3763 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3764 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3765 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3766 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3767 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3768 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3769 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3770 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3771 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3772 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3773 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3774 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3775 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3776 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3777 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3778 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3779 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3780 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3781 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3782 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3783 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 3784 | .rmu_disable = mv88e6352_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3785 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3786 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3787 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3788 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Vivien Didelot | 9db4a72 | 2019-08-31 16:18:31 -0400 | [diff] [blame] | 3789 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 3790 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
| 3791 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, |
| 3792 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, |
| 3793 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 3794 | .serdes_power = mv88e6352_serdes_power, |
Andrew Lunn | d3f88a2 | 2020-02-16 18:54:14 +0100 | [diff] [blame] | 3795 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
| 3796 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 3797 | .gpio_ops = &mv88e6352_gpio_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3798 | .phylink_validate = mv88e6352_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3799 | }; |
| 3800 | |
| 3801 | static const struct mv88e6xxx_ops mv88e6175_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3802 | /* MV88E6XXX_FAMILY_6351 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3803 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3804 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3805 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3806 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3807 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3808 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3809 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3810 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 94d66ae | 2016-11-10 15:44:01 +0100 | [diff] [blame] | 3811 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3812 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3813 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3814 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3815 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3816 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3817 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3818 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3819 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3820 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3821 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3822 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3823 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3824 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3825 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3826 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3827 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3828 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3829 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3830 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3831 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3832 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3833 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3834 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3835 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3836 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3837 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3838 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3839 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3840 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3841 | }; |
| 3842 | |
| 3843 | static const struct mv88e6xxx_ops mv88e6176_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3844 | /* MV88E6XXX_FAMILY_6352 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3845 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3846 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3847 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 3848 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 3849 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3850 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3851 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3852 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3853 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3854 | .port_sync_link = mv88e6xxx_port_sync_link, |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 3855 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3856 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3857 | .port_tag_remap = mv88e6095_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 3858 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3859 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3860 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3861 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3862 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 3863 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3864 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3865 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3866 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3867 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3868 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3869 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3870 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3871 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3872 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3873 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3874 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3875 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3876 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3877 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3878 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3879 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3880 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 3881 | .rmu_disable = mv88e6352_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3882 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3883 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3884 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3885 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Vivien Didelot | 9db4a72 | 2019-08-31 16:18:31 -0400 | [diff] [blame] | 3886 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 3887 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
| 3888 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, |
| 3889 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, |
| 3890 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 3891 | .serdes_power = mv88e6352_serdes_power, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 3892 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 3893 | .serdes_irq_enable = mv88e6352_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 3894 | .serdes_irq_status = mv88e6352_serdes_irq_status, |
Andrew Lunn | d3f88a2 | 2020-02-16 18:54:14 +0100 | [diff] [blame] | 3895 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
| 3896 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 3897 | .gpio_ops = &mv88e6352_gpio_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3898 | .phylink_validate = mv88e6352_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3899 | }; |
| 3900 | |
| 3901 | static const struct mv88e6xxx_ops mv88e6185_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3902 | /* MV88E6XXX_FAMILY_6185 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 3903 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 3904 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 3905 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
Vivien Didelot | 7e20cfb | 2017-05-26 18:03:06 -0400 | [diff] [blame] | 3906 | .phy_read = mv88e6185_phy_ppu_read, |
| 3907 | .phy_write = mv88e6185_phy_ppu_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 3908 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3909 | .port_sync_link = mv88e6185_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3910 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3911 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3912 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
| 3913 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 3914 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 3915 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
Andrew Lunn | 54186b9 | 2018-08-09 15:38:37 +0200 | [diff] [blame] | 3916 | .port_set_pause = mv88e6185_port_set_pause, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3917 | .port_get_cmode = mv88e6185_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3918 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 3919 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 3920 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3921 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 3922 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 3923 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3924 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 3925 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 3926 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 3927 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
Chris Packham | f5be107 | 2020-11-24 17:34:38 +1300 | [diff] [blame] | 3928 | .serdes_power = mv88e6185_serdes_power, |
| 3929 | .serdes_get_lane = mv88e6185_serdes_get_lane, |
| 3930 | .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, |
Vivien Didelot | 02317e6 | 2018-05-09 11:38:49 -0400 | [diff] [blame] | 3931 | .set_cascade_port = mv88e6185_g1_set_cascade_port, |
Vivien Didelot | a199d8b | 2016-12-05 17:30:28 -0500 | [diff] [blame] | 3932 | .ppu_enable = mv88e6185_g1_ppu_enable, |
| 3933 | .ppu_disable = mv88e6185_g1_ppu_disable, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3934 | .reset = mv88e6185_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 3935 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 3936 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3937 | .phylink_validate = mv88e6185_phylink_validate, |
Chris Packham | 1baf0fa | 2020-07-24 11:21:22 +1200 | [diff] [blame] | 3938 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 3939 | }; |
| 3940 | |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 3941 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 3942 | /* MV88E6XXX_FAMILY_6390 */ |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 3943 | .setup_errata = mv88e6390_setup_errata, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 3944 | .irl_init_all = mv88e6390_g2_irl_init_all, |
Vivien Didelot | 98fc3c6 | 2017-01-12 18:07:16 -0500 | [diff] [blame] | 3945 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 3946 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 3947 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 3948 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 3949 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 3950 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 3951 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 3952 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 3953 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 3954 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 3955 | .port_tag_remap = mv88e6390_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 3956 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3957 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 3958 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 3959 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 3960 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Chris Packham | e8b34c6 | 2020-07-24 11:21:21 +1200 | [diff] [blame] | 3961 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 3962 | .port_pause_limit = mv88e6390_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 3963 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 3964 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 3965 | .port_get_cmode = mv88e6352_port_get_cmode, |
Andrew Lunn | fdc71ee | 2018-11-11 00:32:15 +0100 | [diff] [blame] | 3966 | .port_set_cmode = mv88e6390_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 3967 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 7952347 | 2016-11-21 23:27:00 +0100 | [diff] [blame] | 3968 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 3969 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 3970 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 3971 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 3972 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 3973 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 3974 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Andrew Lunn | 6130373 | 2017-02-09 00:03:43 +0100 | [diff] [blame] | 3975 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 3976 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 3977 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 3978 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 3979 | .rmu_disable = mv88e6390_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 3980 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 3981 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 3982 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 3983 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
Andrew Lunn | 6335e9f | 2017-05-26 01:03:23 +0200 | [diff] [blame] | 3984 | .serdes_power = mv88e6390_serdes_power, |
Marek Behún | 17deaf5 | 2019-08-26 23:31:52 +0200 | [diff] [blame] | 3985 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 3986 | /* Check status register pause & lpa register */ |
| 3987 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 3988 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 3989 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 3990 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 3991 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 3992 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 3993 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Andrew Lunn | 4262c38 | 2020-01-18 19:40:56 +0100 | [diff] [blame] | 3994 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
| 3995 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
Andrew Lunn | bf3504c | 2020-02-16 18:54:15 +0100 | [diff] [blame] | 3996 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
| 3997 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 3998 | .gpio_ops = &mv88e6352_gpio_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 3999 | .phylink_validate = mv88e6390_phylink_validate, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4000 | }; |
| 4001 | |
| 4002 | static const struct mv88e6xxx_ops mv88e6190x_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4003 | /* MV88E6XXX_FAMILY_6390 */ |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 4004 | .setup_errata = mv88e6390_setup_errata, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4005 | .irl_init_all = mv88e6390_g2_irl_init_all, |
Vivien Didelot | 98fc3c6 | 2017-01-12 18:07:16 -0500 | [diff] [blame] | 4006 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4007 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4008 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4009 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4010 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4011 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4012 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4013 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4014 | .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 4015 | .port_max_speed_mode = mv88e6390x_port_max_speed_mode, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4016 | .port_tag_remap = mv88e6390_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 4017 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4018 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4019 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4020 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4021 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Chris Packham | e8b34c6 | 2020-07-24 11:21:21 +1200 | [diff] [blame] | 4022 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4023 | .port_pause_limit = mv88e6390_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4024 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4025 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4026 | .port_get_cmode = mv88e6352_port_get_cmode, |
Andrew Lunn | fdc71ee | 2018-11-11 00:32:15 +0100 | [diff] [blame] | 4027 | .port_set_cmode = mv88e6390x_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4028 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 7952347 | 2016-11-21 23:27:00 +0100 | [diff] [blame] | 4029 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 4030 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4031 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4032 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 4033 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4034 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 4035 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Andrew Lunn | 6130373 | 2017-02-09 00:03:43 +0100 | [diff] [blame] | 4036 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 4037 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4038 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4039 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4040 | .rmu_disable = mv88e6390_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4041 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4042 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 4043 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 4044 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
Marek Behún | d3cf7d8 | 2019-08-26 23:31:53 +0200 | [diff] [blame] | 4045 | .serdes_power = mv88e6390_serdes_power, |
Marek Behún | 17deaf5 | 2019-08-26 23:31:52 +0200 | [diff] [blame] | 4046 | .serdes_get_lane = mv88e6390x_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4047 | /* Check status register pause & lpa register */ |
| 4048 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 4049 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4050 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4051 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4052 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4053 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4054 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Andrew Lunn | 4262c38 | 2020-01-18 19:40:56 +0100 | [diff] [blame] | 4055 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
| 4056 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
Andrew Lunn | bf3504c | 2020-02-16 18:54:15 +0100 | [diff] [blame] | 4057 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
| 4058 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4059 | .gpio_ops = &mv88e6352_gpio_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4060 | .phylink_validate = mv88e6390x_phylink_validate, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4061 | }; |
| 4062 | |
| 4063 | static const struct mv88e6xxx_ops mv88e6191_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4064 | /* MV88E6XXX_FAMILY_6390 */ |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 4065 | .setup_errata = mv88e6390_setup_errata, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4066 | .irl_init_all = mv88e6390_g2_irl_init_all, |
Vivien Didelot | 98fc3c6 | 2017-01-12 18:07:16 -0500 | [diff] [blame] | 4067 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4068 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4069 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4070 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4071 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4072 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4073 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4074 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4075 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 4076 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4077 | .port_tag_remap = mv88e6390_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4078 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4079 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4080 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4081 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4082 | .port_pause_limit = mv88e6390_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4083 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4084 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4085 | .port_get_cmode = mv88e6352_port_get_cmode, |
Andrew Lunn | fdc71ee | 2018-11-11 00:32:15 +0100 | [diff] [blame] | 4086 | .port_set_cmode = mv88e6390_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4087 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 7952347 | 2016-11-21 23:27:00 +0100 | [diff] [blame] | 4088 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 4089 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4090 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4091 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 4092 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4093 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 4094 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Andrew Lunn | 6130373 | 2017-02-09 00:03:43 +0100 | [diff] [blame] | 4095 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 4096 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4097 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4098 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4099 | .rmu_disable = mv88e6390_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4100 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4101 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 4102 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 4103 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
Andrew Lunn | 6335e9f | 2017-05-26 01:03:23 +0200 | [diff] [blame] | 4104 | .serdes_power = mv88e6390_serdes_power, |
Marek Behún | 17deaf5 | 2019-08-26 23:31:52 +0200 | [diff] [blame] | 4105 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4106 | /* Check status register pause & lpa register */ |
| 4107 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 4108 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4109 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4110 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4111 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4112 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4113 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Andrew Lunn | 4262c38 | 2020-01-18 19:40:56 +0100 | [diff] [blame] | 4114 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
| 4115 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
Andrew Lunn | bf3504c | 2020-02-16 18:54:15 +0100 | [diff] [blame] | 4116 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
| 4117 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4118 | .avb_ops = &mv88e6390_avb_ops, |
| 4119 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4120 | .phylink_validate = mv88e6390_phylink_validate, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4121 | }; |
| 4122 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4123 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4124 | /* MV88E6XXX_FAMILY_6352 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4125 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4126 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4127 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 4128 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 4129 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 4130 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4131 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4132 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 4133 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4134 | .port_sync_link = mv88e6xxx_port_sync_link, |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 4135 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4136 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4137 | .port_tag_remap = mv88e6095_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 4138 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4139 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4140 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4141 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4142 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4143 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4144 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4145 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4146 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4147 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4148 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4149 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 4150 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4151 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4152 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 4153 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 4154 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4155 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4156 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 4157 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 4158 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4159 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4160 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4161 | .rmu_disable = mv88e6352_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4162 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4163 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4164 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4165 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Vivien Didelot | 9db4a72 | 2019-08-31 16:18:31 -0400 | [diff] [blame] | 4166 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4167 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
| 4168 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, |
| 4169 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, |
| 4170 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 4171 | .serdes_power = mv88e6352_serdes_power, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4172 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4173 | .serdes_irq_enable = mv88e6352_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4174 | .serdes_irq_status = mv88e6352_serdes_irq_status, |
Andrew Lunn | d3f88a2 | 2020-02-16 18:54:14 +0100 | [diff] [blame] | 4175 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
| 4176 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4177 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4178 | .avb_ops = &mv88e6352_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4179 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4180 | .phylink_validate = mv88e6352_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4181 | }; |
| 4182 | |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 4183 | static const struct mv88e6xxx_ops mv88e6250_ops = { |
| 4184 | /* MV88E6XXX_FAMILY_6250 */ |
| 4185 | .ieee_pri_map = mv88e6250_g1_ieee_pri_map, |
| 4186 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
| 4187 | .irl_init_all = mv88e6352_g2_irl_init_all, |
| 4188 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 4189 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
| 4190 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4191 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4192 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4193 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4194 | .port_sync_link = mv88e6xxx_port_sync_link, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 4195 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4196 | .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 4197 | .port_tag_remap = mv88e6095_port_tag_remap, |
| 4198 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4199 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4200 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 4201 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
| 4202 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
| 4203 | .port_pause_limit = mv88e6097_port_pause_limit, |
| 4204 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 4205 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
| 4206 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
| 4207 | .stats_get_sset_count = mv88e6250_stats_get_sset_count, |
| 4208 | .stats_get_strings = mv88e6250_stats_get_strings, |
| 4209 | .stats_get_stats = mv88e6250_stats_get_stats, |
| 4210 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4211 | .set_egress_port = mv88e6095_g1_set_egress_port, |
| 4212 | .watchdog_ops = &mv88e6250_watchdog_ops, |
| 4213 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
| 4214 | .pot_clear = mv88e6xxx_g2_pot_clear, |
| 4215 | .reset = mv88e6250_g1_reset, |
Rasmus Villemoes | 67c9ed1 | 2021-01-25 16:04:48 +0100 | [diff] [blame] | 4216 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
Rasmus Villemoes | b28f3f3 | 2021-01-25 16:04:49 +0100 | [diff] [blame] | 4217 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
Hubert Feurstein | 7150961 | 2019-07-31 10:23:51 +0200 | [diff] [blame] | 4218 | .avb_ops = &mv88e6352_avb_ops, |
| 4219 | .ptp_ops = &mv88e6250_ptp_ops, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 4220 | .phylink_validate = mv88e6065_phylink_validate, |
| 4221 | }; |
| 4222 | |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4223 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4224 | /* MV88E6XXX_FAMILY_6390 */ |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 4225 | .setup_errata = mv88e6390_setup_errata, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4226 | .irl_init_all = mv88e6390_g2_irl_init_all, |
Vivien Didelot | 98fc3c6 | 2017-01-12 18:07:16 -0500 | [diff] [blame] | 4227 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4228 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4229 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4230 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4231 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4232 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4233 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4234 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4235 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 4236 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4237 | .port_tag_remap = mv88e6390_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 4238 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4239 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4240 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4241 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4242 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4243 | .port_pause_limit = mv88e6390_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4244 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4245 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4246 | .port_get_cmode = mv88e6352_port_get_cmode, |
Andrew Lunn | fdc71ee | 2018-11-11 00:32:15 +0100 | [diff] [blame] | 4247 | .port_set_cmode = mv88e6390_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4248 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 7952347 | 2016-11-21 23:27:00 +0100 | [diff] [blame] | 4249 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 4250 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4251 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4252 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 4253 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4254 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 4255 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Andrew Lunn | 6130373 | 2017-02-09 00:03:43 +0100 | [diff] [blame] | 4256 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 4257 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4258 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4259 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4260 | .rmu_disable = mv88e6390_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4261 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4262 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 4263 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 4264 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
Andrew Lunn | 6335e9f | 2017-05-26 01:03:23 +0200 | [diff] [blame] | 4265 | .serdes_power = mv88e6390_serdes_power, |
Marek Behún | 17deaf5 | 2019-08-26 23:31:52 +0200 | [diff] [blame] | 4266 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4267 | /* Check status register pause & lpa register */ |
| 4268 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 4269 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4270 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4271 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4272 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4273 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4274 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Andrew Lunn | 4262c38 | 2020-01-18 19:40:56 +0100 | [diff] [blame] | 4275 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
| 4276 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
Andrew Lunn | bf3504c | 2020-02-16 18:54:15 +0100 | [diff] [blame] | 4277 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
| 4278 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4279 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4280 | .avb_ops = &mv88e6390_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4281 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4282 | .phylink_validate = mv88e6390_phylink_validate, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4283 | }; |
| 4284 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4285 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4286 | /* MV88E6XXX_FAMILY_6320 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4287 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4288 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4289 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 4290 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 4291 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 4292 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4293 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4294 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 4295 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4296 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4297 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4298 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4299 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4300 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4301 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4302 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4303 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4304 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4305 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4306 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4307 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4308 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4309 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 4310 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4311 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4312 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4313 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 4314 | .stats_get_stats = mv88e6320_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4315 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4316 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | 9c7f37e | 2018-12-19 18:28:54 +0100 | [diff] [blame] | 4317 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 4318 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4319 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4320 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4321 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4322 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4323 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4324 | .avb_ops = &mv88e6352_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4325 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4326 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4327 | }; |
| 4328 | |
| 4329 | static const struct mv88e6xxx_ops mv88e6321_ops = { |
Vivien Didelot | bd80720 | 2017-07-17 13:03:37 -0400 | [diff] [blame] | 4330 | /* MV88E6XXX_FAMILY_6320 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4331 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4332 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4333 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 4334 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 4335 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 4336 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4337 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4338 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 4339 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4340 | .port_sync_link = mv88e6xxx_port_sync_link, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4341 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4342 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4343 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4344 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4345 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4346 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4347 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4348 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4349 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4350 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4351 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4352 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4353 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 4354 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4355 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4356 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4357 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 4358 | .stats_get_stats = mv88e6320_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4359 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4360 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | 9c7f37e | 2018-12-19 18:28:54 +0100 | [diff] [blame] | 4361 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4362 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4363 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4364 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4365 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4366 | .avb_ops = &mv88e6352_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4367 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4368 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4369 | }; |
| 4370 | |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4371 | static const struct mv88e6xxx_ops mv88e6341_ops = { |
| 4372 | /* MV88E6XXX_FAMILY_6341 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4373 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4374 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4375 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4376 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4377 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
| 4378 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4379 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4380 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4381 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4382 | .port_sync_link = mv88e6xxx_port_sync_link, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4383 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4384 | .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 4385 | .port_max_speed_mode = mv88e6341_port_max_speed_mode, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4386 | .port_tag_remap = mv88e6095_port_tag_remap, |
Marek Behún | 7da467d | 2021-07-01 00:22:26 +0200 | [diff] [blame^] | 4387 | .port_set_policy = mv88e6352_port_set_policy, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4388 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4389 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4390 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4391 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4392 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4393 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4394 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4395 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
| 4396 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4397 | .port_get_cmode = mv88e6352_port_get_cmode, |
Marek Behún | 7a3007d | 2019-08-26 23:31:55 +0200 | [diff] [blame] | 4398 | .port_set_cmode = mv88e6341_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4399 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4400 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4401 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4402 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4403 | .stats_get_strings = mv88e6320_stats_get_strings, |
| 4404 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4405 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 4406 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4407 | .watchdog_ops = &mv88e6390_watchdog_ops, |
| 4408 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4409 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4410 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4411 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4412 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Marek Behún | d3cf7d8 | 2019-08-26 23:31:53 +0200 | [diff] [blame] | 4413 | .serdes_power = mv88e6390_serdes_power, |
| 4414 | .serdes_get_lane = mv88e6341_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4415 | /* Check status register pause & lpa register */ |
| 4416 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 4417 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4418 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4419 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4420 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4421 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4422 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4423 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4424 | .avb_ops = &mv88e6390_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4425 | .ptp_ops = &mv88e6352_ptp_ops, |
Marek Behún | e3af71a | 2019-02-25 12:39:55 +0100 | [diff] [blame] | 4426 | .phylink_validate = mv88e6341_phylink_validate, |
Vivien Didelot | 16e329a | 2017-03-28 13:50:33 -0400 | [diff] [blame] | 4427 | }; |
| 4428 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4429 | static const struct mv88e6xxx_ops mv88e6350_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4430 | /* MV88E6XXX_FAMILY_6351 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4431 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4432 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4433 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 4434 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4435 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4436 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 4437 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4438 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 94d66ae | 2016-11-10 15:44:01 +0100 | [diff] [blame] | 4439 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4440 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4441 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4442 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4443 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4444 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4445 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4446 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4447 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4448 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4449 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4450 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4451 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4452 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 4453 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4454 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4455 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 4456 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 4457 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4458 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4459 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 4460 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 4461 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4462 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4463 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4464 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4465 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4466 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4467 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4468 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4469 | }; |
| 4470 | |
| 4471 | static const struct mv88e6xxx_ops mv88e6351_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4472 | /* MV88E6XXX_FAMILY_6351 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4473 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4474 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4475 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 4476 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4477 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4478 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 4479 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4480 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 94d66ae | 2016-11-10 15:44:01 +0100 | [diff] [blame] | 4481 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4482 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4483 | .port_tag_remap = mv88e6095_port_tag_remap, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4484 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4485 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4486 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4487 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4488 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4489 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4490 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4491 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4492 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4493 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4494 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 4495 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4496 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4497 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 4498 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 4499 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4500 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4501 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 4502 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 4503 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4504 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4505 | .reset = mv88e6352_g1_reset, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4506 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4507 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4508 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4509 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4510 | .avb_ops = &mv88e6352_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4511 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4512 | .phylink_validate = mv88e6185_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4513 | }; |
| 4514 | |
| 4515 | static const struct mv88e6xxx_ops mv88e6352_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4516 | /* MV88E6XXX_FAMILY_6352 */ |
Vivien Didelot | 93e18d6 | 2018-05-11 17:16:35 -0400 | [diff] [blame] | 4517 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
| 4518 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4519 | .irl_init_all = mv88e6352_g2_irl_init_all, |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 4520 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
| 4521 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 4522 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4523 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4524 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 4525 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4526 | .port_sync_link = mv88e6xxx_port_sync_link, |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 4527 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4528 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4529 | .port_tag_remap = mv88e6095_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 4530 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4531 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4532 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4533 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4534 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4535 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4536 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4537 | .port_pause_limit = mv88e6097_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4538 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4539 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4540 | .port_get_cmode = mv88e6352_port_get_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4541 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | a605a0f | 2016-11-21 23:26:58 +0100 | [diff] [blame] | 4542 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
Andrew Lunn | 40cff8f | 2017-11-10 00:36:41 +0100 | [diff] [blame] | 4543 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4544 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
| 4545 | .stats_get_strings = mv88e6095_stats_get_strings, |
Andrew Lunn | 052f947 | 2016-11-21 23:27:03 +0100 | [diff] [blame] | 4546 | .stats_get_stats = mv88e6095_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4547 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
| 4548 | .set_egress_port = mv88e6095_g1_set_egress_port, |
Andrew Lunn | fcd2516 | 2017-02-09 00:03:42 +0100 | [diff] [blame] | 4549 | .watchdog_ops = &mv88e6097_watchdog_ops, |
Vivien Didelot | 51c901a | 2017-07-17 13:03:41 -0400 | [diff] [blame] | 4550 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4551 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4552 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4553 | .rmu_disable = mv88e6352_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4554 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4555 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | f1394b78 | 2017-05-01 14:05:22 -0400 | [diff] [blame] | 4556 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
Vivien Didelot | 0ad5daf | 2017-05-01 14:05:23 -0400 | [diff] [blame] | 4557 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
Vivien Didelot | 9db4a72 | 2019-08-31 16:18:31 -0400 | [diff] [blame] | 4558 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4559 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
| 4560 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, |
| 4561 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, |
| 4562 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, |
Andrew Lunn | 6d91782 | 2017-05-26 01:03:21 +0200 | [diff] [blame] | 4563 | .serdes_power = mv88e6352_serdes_power, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4564 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4565 | .serdes_irq_enable = mv88e6352_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4566 | .serdes_irq_status = mv88e6352_serdes_irq_status, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4567 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4568 | .avb_ops = &mv88e6352_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4569 | .ptp_ops = &mv88e6352_ptp_ops, |
Andrew Lunn | cda9f4a | 2018-03-01 02:02:31 +0100 | [diff] [blame] | 4570 | .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, |
| 4571 | .serdes_get_strings = mv88e6352_serdes_get_strings, |
| 4572 | .serdes_get_stats = mv88e6352_serdes_get_stats, |
Andrew Lunn | d3f88a2 | 2020-02-16 18:54:14 +0100 | [diff] [blame] | 4573 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
| 4574 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4575 | .phylink_validate = mv88e6352_phylink_validate, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4576 | }; |
| 4577 | |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4578 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4579 | /* MV88E6XXX_FAMILY_6390 */ |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 4580 | .setup_errata = mv88e6390_setup_errata, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4581 | .irl_init_all = mv88e6390_g2_irl_init_all, |
Vivien Didelot | 98fc3c6 | 2017-01-12 18:07:16 -0500 | [diff] [blame] | 4582 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4583 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4584 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4585 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4586 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4587 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4588 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4589 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4590 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 4591 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4592 | .port_tag_remap = mv88e6390_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 4593 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4594 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4595 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4596 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4597 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4598 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4599 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4600 | .port_pause_limit = mv88e6390_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4601 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4602 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4603 | .port_get_cmode = mv88e6352_port_get_cmode, |
Andrew Lunn | fdc71ee | 2018-11-11 00:32:15 +0100 | [diff] [blame] | 4604 | .port_set_cmode = mv88e6390_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4605 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 7952347 | 2016-11-21 23:27:00 +0100 | [diff] [blame] | 4606 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 4607 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4608 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4609 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 4610 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4611 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 4612 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Andrew Lunn | 6130373 | 2017-02-09 00:03:43 +0100 | [diff] [blame] | 4613 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 4614 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4615 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4616 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4617 | .rmu_disable = mv88e6390_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4618 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4619 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 4620 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 4621 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
Andrew Lunn | 6335e9f | 2017-05-26 01:03:23 +0200 | [diff] [blame] | 4622 | .serdes_power = mv88e6390_serdes_power, |
Marek Behún | 17deaf5 | 2019-08-26 23:31:52 +0200 | [diff] [blame] | 4623 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4624 | /* Check status register pause & lpa register */ |
| 4625 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 4626 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4627 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4628 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4629 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4630 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4631 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4632 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4633 | .avb_ops = &mv88e6390_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4634 | .ptp_ops = &mv88e6352_ptp_ops, |
Nikita Yushchenko | 0df9528 | 2019-12-25 08:22:38 +0300 | [diff] [blame] | 4635 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
| 4636 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
| 4637 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
Andrew Lunn | bf3504c | 2020-02-16 18:54:15 +0100 | [diff] [blame] | 4638 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
| 4639 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4640 | .phylink_validate = mv88e6390_phylink_validate, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4641 | }; |
| 4642 | |
| 4643 | static const struct mv88e6xxx_ops mv88e6390x_ops = { |
Andrew Lunn | 4b325d8 | 2016-11-21 23:26:59 +0100 | [diff] [blame] | 4644 | /* MV88E6XXX_FAMILY_6390 */ |
Andrew Lunn | ea89098 | 2019-01-09 00:24:03 +0100 | [diff] [blame] | 4645 | .setup_errata = mv88e6390_setup_errata, |
Vivien Didelot | cd8da8b | 2017-06-19 10:55:36 -0400 | [diff] [blame] | 4646 | .irl_init_all = mv88e6390_g2_irl_init_all, |
Vivien Didelot | 98fc3c6 | 2017-01-12 18:07:16 -0500 | [diff] [blame] | 4647 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4648 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4649 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4650 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4651 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4652 | .port_set_link = mv88e6xxx_port_set_link, |
Chris Packham | 4efe7662 | 2020-11-24 17:34:37 +1300 | [diff] [blame] | 4653 | .port_sync_link = mv88e6xxx_port_sync_link, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4654 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
Russell King | f365c6f | 2020-03-14 10:15:53 +0000 | [diff] [blame] | 4655 | .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, |
Andrew Lunn | 7cbbee0 | 2019-03-08 01:21:27 +0100 | [diff] [blame] | 4656 | .port_max_speed_mode = mv88e6390x_port_max_speed_mode, |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 4657 | .port_tag_remap = mv88e6390_port_tag_remap, |
Vivien Didelot | f3a2cd3 | 2019-09-07 16:00:48 -0400 | [diff] [blame] | 4658 | .port_set_policy = mv88e6352_port_set_policy, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4659 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 4660 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4661 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 4662 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 4663 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 4664 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 4665 | .port_pause_limit = mv88e6390_port_pause_limit, |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 4666 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 4667 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
Andrew Lunn | 2d2e1dd | 2018-08-09 15:38:45 +0200 | [diff] [blame] | 4668 | .port_get_cmode = mv88e6352_port_get_cmode, |
Andrew Lunn | b3dce4d | 2018-11-11 00:32:14 +0100 | [diff] [blame] | 4669 | .port_set_cmode = mv88e6390x_port_set_cmode, |
Hubert Feurstein | 121b8fe | 2019-07-31 10:23:49 +0200 | [diff] [blame] | 4670 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
Andrew Lunn | 7952347 | 2016-11-21 23:27:00 +0100 | [diff] [blame] | 4671 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
Andrew Lunn | de227387 | 2016-11-21 23:27:01 +0100 | [diff] [blame] | 4672 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
Andrew Lunn | dfafe44 | 2016-11-21 23:27:02 +0100 | [diff] [blame] | 4673 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4674 | .stats_get_strings = mv88e6320_stats_get_strings, |
Andrew Lunn | e0d8b61 | 2016-11-21 23:27:04 +0100 | [diff] [blame] | 4675 | .stats_get_stats = mv88e6390_stats_get_stats, |
Vivien Didelot | fa8d117 | 2017-06-08 18:34:11 -0400 | [diff] [blame] | 4676 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
| 4677 | .set_egress_port = mv88e6390_g1_set_egress_port, |
Andrew Lunn | 6130373 | 2017-02-09 00:03:43 +0100 | [diff] [blame] | 4678 | .watchdog_ops = &mv88e6390_watchdog_ops, |
Andrew Lunn | 6e55f69 | 2016-12-03 04:45:16 +0100 | [diff] [blame] | 4679 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
Vivien Didelot | 9e907d7 | 2017-07-17 13:03:43 -0400 | [diff] [blame] | 4680 | .pot_clear = mv88e6xxx_g2_pot_clear, |
Vivien Didelot | 17e708b | 2016-12-05 17:30:27 -0500 | [diff] [blame] | 4681 | .reset = mv88e6352_g1_reset, |
Vivien Didelot | 9e5baf9 | 2018-05-09 11:38:51 -0400 | [diff] [blame] | 4682 | .rmu_disable = mv88e6390_g1_rmu_disable, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 4683 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4684 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 4685 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 4686 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
Marek Behún | d3cf7d8 | 2019-08-26 23:31:53 +0200 | [diff] [blame] | 4687 | .serdes_power = mv88e6390_serdes_power, |
Marek Behún | 17deaf5 | 2019-08-26 23:31:52 +0200 | [diff] [blame] | 4688 | .serdes_get_lane = mv88e6390x_serdes_get_lane, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 4689 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
| 4690 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4691 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4692 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
Vivien Didelot | 4241ef5 | 2019-08-31 16:18:29 -0400 | [diff] [blame] | 4693 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
Vivien Didelot | 61a46b4 | 2019-08-31 16:18:34 -0400 | [diff] [blame] | 4694 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
Vivien Didelot | 907b9b9 | 2019-08-31 16:18:35 -0400 | [diff] [blame] | 4695 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
Andrew Lunn | 4262c38 | 2020-01-18 19:40:56 +0100 | [diff] [blame] | 4696 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
| 4697 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
| 4698 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
Andrew Lunn | bf3504c | 2020-02-16 18:54:15 +0100 | [diff] [blame] | 4699 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
| 4700 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4701 | .gpio_ops = &mv88e6352_gpio_ops, |
Brandon Streiff | 0d632c3 | 2018-02-14 01:07:44 +0100 | [diff] [blame] | 4702 | .avb_ops = &mv88e6390_avb_ops, |
Andrew Lunn | 6d2ac8e | 2018-07-18 22:38:20 +0200 | [diff] [blame] | 4703 | .ptp_ops = &mv88e6352_ptp_ops, |
Russell King | 6c422e3 | 2018-08-09 15:38:39 +0200 | [diff] [blame] | 4704 | .phylink_validate = mv88e6390x_phylink_validate, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 4705 | }; |
| 4706 | |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 4707 | static const struct mv88e6xxx_ops mv88e6393x_ops = { |
| 4708 | /* MV88E6XXX_FAMILY_6393 */ |
| 4709 | .setup_errata = mv88e6393x_serdes_setup_errata, |
| 4710 | .irl_init_all = mv88e6390_g2_irl_init_all, |
| 4711 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
| 4712 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
| 4713 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
| 4714 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
| 4715 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
| 4716 | .port_set_link = mv88e6xxx_port_set_link, |
| 4717 | .port_sync_link = mv88e6xxx_port_sync_link, |
| 4718 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
| 4719 | .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, |
| 4720 | .port_max_speed_mode = mv88e6393x_port_max_speed_mode, |
| 4721 | .port_tag_remap = mv88e6390_port_tag_remap, |
Marek Behún | 6584b26 | 2021-03-17 14:46:43 +0100 | [diff] [blame] | 4722 | .port_set_policy = mv88e6393x_port_set_policy, |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 4723 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
| 4724 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
| 4725 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
| 4726 | .port_set_ether_type = mv88e6393x_port_set_ether_type, |
| 4727 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
| 4728 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
| 4729 | .port_pause_limit = mv88e6390_port_pause_limit, |
| 4730 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
| 4731 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
| 4732 | .port_get_cmode = mv88e6352_port_get_cmode, |
| 4733 | .port_set_cmode = mv88e6393x_port_set_cmode, |
| 4734 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
| 4735 | .port_set_upstream_port = mv88e6393x_port_set_upstream_port, |
| 4736 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
| 4737 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
| 4738 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
| 4739 | .stats_get_strings = mv88e6320_stats_get_strings, |
| 4740 | .stats_get_stats = mv88e6390_stats_get_stats, |
| 4741 | /* .set_cpu_port is missing because this family does not support a global |
| 4742 | * CPU port, only per port CPU port which is set via |
| 4743 | * .port_set_upstream_port method. |
| 4744 | */ |
| 4745 | .set_egress_port = mv88e6393x_set_egress_port, |
| 4746 | .watchdog_ops = &mv88e6390_watchdog_ops, |
| 4747 | .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, |
| 4748 | .pot_clear = mv88e6xxx_g2_pot_clear, |
| 4749 | .reset = mv88e6352_g1_reset, |
| 4750 | .rmu_disable = mv88e6390_g1_rmu_disable, |
| 4751 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
| 4752 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
| 4753 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
| 4754 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
| 4755 | .serdes_power = mv88e6393x_serdes_power, |
| 4756 | .serdes_get_lane = mv88e6393x_serdes_get_lane, |
| 4757 | .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, |
| 4758 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, |
| 4759 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, |
| 4760 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, |
| 4761 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
| 4762 | .serdes_irq_enable = mv88e6393x_serdes_irq_enable, |
| 4763 | .serdes_irq_status = mv88e6393x_serdes_irq_status, |
| 4764 | /* TODO: serdes stats */ |
| 4765 | .gpio_ops = &mv88e6352_gpio_ops, |
| 4766 | .avb_ops = &mv88e6390_avb_ops, |
| 4767 | .ptp_ops = &mv88e6352_ptp_ops, |
| 4768 | .phylink_validate = mv88e6393x_phylink_validate, |
| 4769 | }; |
| 4770 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4771 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
| 4772 | [MV88E6085] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4773 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4774 | .family = MV88E6XXX_FAMILY_6097, |
| 4775 | .name = "Marvell 88E6085", |
| 4776 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4777 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4778 | .num_ports = 10, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4779 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4780 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4781 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4782 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4783 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4784 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4785 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4786 | .g1_irqs = 8, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4787 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4788 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4789 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4790 | .multi_chip = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4791 | .ops = &mv88e6085_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4792 | }, |
| 4793 | |
| 4794 | [MV88E6095] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4795 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4796 | .family = MV88E6XXX_FAMILY_6095, |
| 4797 | .name = "Marvell 88E6095/88E6095F", |
| 4798 | .num_databases = 256, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4799 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4800 | .num_ports = 11, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4801 | .num_internal_phys = 0, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4802 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4803 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4804 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4805 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4806 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4807 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4808 | .g1_irqs = 8, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4809 | .atu_move_port_mask = 0xf, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4810 | .multi_chip = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4811 | .ops = &mv88e6095_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4812 | }, |
| 4813 | |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4814 | [MV88E6097] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4815 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4816 | .family = MV88E6XXX_FAMILY_6097, |
| 4817 | .name = "Marvell 88E6097/88E6097F", |
| 4818 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4819 | .num_macs = 8192, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4820 | .num_ports = 11, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4821 | .num_internal_phys = 8, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4822 | .max_vid = 4095, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4823 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4824 | .phy_base_addr = 0x0, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4825 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4826 | .global2_addr = 0x1c, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4827 | .age_time_coeff = 15000, |
Stefan Eichenberger | c534178 | 2016-11-25 09:41:29 +0100 | [diff] [blame] | 4828 | .g1_irqs = 8, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4829 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4830 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4831 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4832 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 4833 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Stefan Eichenberger | 7d381a0 | 2016-11-22 17:47:21 +0100 | [diff] [blame] | 4834 | .ops = &mv88e6097_ops, |
| 4835 | }, |
| 4836 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4837 | [MV88E6123] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4838 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4839 | .family = MV88E6XXX_FAMILY_6165, |
| 4840 | .name = "Marvell 88E6123", |
| 4841 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4842 | .num_macs = 1024, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4843 | .num_ports = 3, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4844 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4845 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4846 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4847 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4848 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4849 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4850 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4851 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4852 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4853 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4854 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4855 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 4856 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4857 | .ops = &mv88e6123_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4858 | }, |
| 4859 | |
| 4860 | [MV88E6131] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4861 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4862 | .family = MV88E6XXX_FAMILY_6185, |
| 4863 | .name = "Marvell 88E6131", |
| 4864 | .num_databases = 256, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4865 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4866 | .num_ports = 8, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4867 | .num_internal_phys = 0, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4868 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4869 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4870 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4871 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4872 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4873 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4874 | .g1_irqs = 9, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4875 | .atu_move_port_mask = 0xf, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4876 | .multi_chip = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4877 | .ops = &mv88e6131_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4878 | }, |
| 4879 | |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4880 | [MV88E6141] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4881 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4882 | .family = MV88E6XXX_FAMILY_6341, |
Uwe Kleine-König | 79a68b2 | 2018-03-20 10:44:40 +0100 | [diff] [blame] | 4883 | .name = "Marvell 88E6141", |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4884 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4885 | .num_macs = 2048, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4886 | .num_ports = 6, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4887 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4888 | .num_gpio = 11, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4889 | .max_vid = 4095, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4890 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4891 | .phy_base_addr = 0x10, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4892 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4893 | .global2_addr = 0x1c, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4894 | .age_time_coeff = 3750, |
| 4895 | .atu_move_port_mask = 0x1f, |
Andrew Lunn | adfccf1 | 2018-03-17 20:32:03 +0100 | [diff] [blame] | 4896 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4897 | .g2_irqs = 10, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4898 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4899 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 4900 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | 990e27b | 2017-03-28 13:50:32 -0400 | [diff] [blame] | 4901 | .ops = &mv88e6141_ops, |
| 4902 | }, |
| 4903 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4904 | [MV88E6161] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4905 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4906 | .family = MV88E6XXX_FAMILY_6165, |
| 4907 | .name = "Marvell 88E6161", |
| 4908 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4909 | .num_macs = 1024, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4910 | .num_ports = 6, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4911 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4912 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4913 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4914 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4915 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4916 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4917 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4918 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4919 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4920 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4921 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4922 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 4923 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Andrew Lunn | dfa5434 | 2018-07-18 22:38:22 +0200 | [diff] [blame] | 4924 | .ptp_support = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4925 | .ops = &mv88e6161_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4926 | }, |
| 4927 | |
| 4928 | [MV88E6165] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4929 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4930 | .family = MV88E6XXX_FAMILY_6165, |
| 4931 | .name = "Marvell 88E6165", |
| 4932 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4933 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4934 | .num_ports = 6, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4935 | .num_internal_phys = 0, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4936 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4937 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4938 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4939 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4940 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4941 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4942 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4943 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4944 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4945 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4946 | .multi_chip = true, |
Andrew Lunn | dfa5434 | 2018-07-18 22:38:22 +0200 | [diff] [blame] | 4947 | .ptp_support = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4948 | .ops = &mv88e6165_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4949 | }, |
| 4950 | |
| 4951 | [MV88E6171] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4952 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4953 | .family = MV88E6XXX_FAMILY_6351, |
| 4954 | .name = "Marvell 88E6171", |
| 4955 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4956 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4957 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4958 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4959 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4960 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4961 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4962 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4963 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4964 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4965 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4966 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4967 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4968 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4969 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 4970 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4971 | .ops = &mv88e6171_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4972 | }, |
| 4973 | |
| 4974 | [MV88E6172] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4975 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4976 | .family = MV88E6XXX_FAMILY_6352, |
| 4977 | .name = "Marvell 88E6172", |
| 4978 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 4979 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4980 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 4981 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 4982 | .num_gpio = 15, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 4983 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 4984 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 4985 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 4986 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 4987 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 4988 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 4989 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 4990 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 4991 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 4992 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 4993 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 4994 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 4995 | .ops = &mv88e6172_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 4996 | }, |
| 4997 | |
| 4998 | [MV88E6175] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 4999 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5000 | .family = MV88E6XXX_FAMILY_6351, |
| 5001 | .name = "Marvell 88E6175", |
| 5002 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5003 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5004 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5005 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5006 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5007 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5008 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5009 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5010 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5011 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5012 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5013 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5014 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5015 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5016 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5017 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5018 | .ops = &mv88e6175_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5019 | }, |
| 5020 | |
| 5021 | [MV88E6176] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5022 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5023 | .family = MV88E6XXX_FAMILY_6352, |
| 5024 | .name = "Marvell 88E6176", |
| 5025 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5026 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5027 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5028 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5029 | .num_gpio = 15, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5030 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5031 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5032 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5033 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5034 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5035 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5036 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5037 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5038 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5039 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5040 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5041 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5042 | .ops = &mv88e6176_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5043 | }, |
| 5044 | |
| 5045 | [MV88E6185] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5046 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5047 | .family = MV88E6XXX_FAMILY_6185, |
| 5048 | .name = "Marvell 88E6185", |
| 5049 | .num_databases = 256, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5050 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5051 | .num_ports = 10, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5052 | .num_internal_phys = 0, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5053 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5054 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5055 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5056 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5057 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5058 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5059 | .g1_irqs = 8, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5060 | .atu_move_port_mask = 0xf, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5061 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5062 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5063 | .ops = &mv88e6185_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5064 | }, |
| 5065 | |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5066 | [MV88E6190] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5067 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5068 | .family = MV88E6XXX_FAMILY_6390, |
| 5069 | .name = "Marvell 88E6190", |
| 5070 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5071 | .num_macs = 16384, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5072 | .num_ports = 11, /* 10 + Z80 */ |
Heiner Kallweit | 95150f2 | 2019-03-02 10:06:05 +0100 | [diff] [blame] | 5073 | .num_internal_phys = 9, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5074 | .num_gpio = 16, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 5075 | .max_vid = 8191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5076 | .port_base_addr = 0x0, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5077 | .phy_base_addr = 0x0, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5078 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5079 | .global2_addr = 0x1c, |
Andrew Lunn | b91e055 | 2017-02-02 00:46:15 +0100 | [diff] [blame] | 5080 | .age_time_coeff = 3750, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5081 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5082 | .g2_irqs = 14, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5083 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5084 | .multi_chip = true, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5085 | .atu_move_port_mask = 0x1f, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5086 | .ops = &mv88e6190_ops, |
| 5087 | }, |
| 5088 | |
| 5089 | [MV88E6190X] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5090 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5091 | .family = MV88E6XXX_FAMILY_6390, |
| 5092 | .name = "Marvell 88E6190X", |
| 5093 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5094 | .num_macs = 16384, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5095 | .num_ports = 11, /* 10 + Z80 */ |
Heiner Kallweit | 95150f2 | 2019-03-02 10:06:05 +0100 | [diff] [blame] | 5096 | .num_internal_phys = 9, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5097 | .num_gpio = 16, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 5098 | .max_vid = 8191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5099 | .port_base_addr = 0x0, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5100 | .phy_base_addr = 0x0, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5101 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5102 | .global2_addr = 0x1c, |
Andrew Lunn | b91e055 | 2017-02-02 00:46:15 +0100 | [diff] [blame] | 5103 | .age_time_coeff = 3750, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5104 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5105 | .g2_irqs = 14, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5106 | .atu_move_port_mask = 0x1f, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5107 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5108 | .multi_chip = true, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5109 | .ops = &mv88e6190x_ops, |
| 5110 | }, |
| 5111 | |
| 5112 | [MV88E6191] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5113 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5114 | .family = MV88E6XXX_FAMILY_6390, |
| 5115 | .name = "Marvell 88E6191", |
| 5116 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5117 | .num_macs = 16384, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5118 | .num_ports = 11, /* 10 + Z80 */ |
Heiner Kallweit | 95150f2 | 2019-03-02 10:06:05 +0100 | [diff] [blame] | 5119 | .num_internal_phys = 9, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 5120 | .max_vid = 8191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5121 | .port_base_addr = 0x0, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5122 | .phy_base_addr = 0x0, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5123 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5124 | .global2_addr = 0x1c, |
Andrew Lunn | b91e055 | 2017-02-02 00:46:15 +0100 | [diff] [blame] | 5125 | .age_time_coeff = 3750, |
Andrew Lunn | 443d5a1 | 2016-12-03 04:35:18 +0100 | [diff] [blame] | 5126 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5127 | .g2_irqs = 14, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5128 | .atu_move_port_mask = 0x1f, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5129 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5130 | .multi_chip = true, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5131 | .ptp_support = true, |
Vivien Didelot | 2cf4cefb | 2017-03-28 13:50:34 -0400 | [diff] [blame] | 5132 | .ops = &mv88e6191_ops, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5133 | }, |
| 5134 | |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 5135 | [MV88E6191X] = { |
| 5136 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, |
| 5137 | .family = MV88E6XXX_FAMILY_6393, |
| 5138 | .name = "Marvell 88E6191X", |
| 5139 | .num_databases = 4096, |
| 5140 | .num_ports = 11, /* 10 + Z80 */ |
| 5141 | .num_internal_phys = 9, |
| 5142 | .max_vid = 8191, |
| 5143 | .port_base_addr = 0x0, |
| 5144 | .phy_base_addr = 0x0, |
| 5145 | .global1_addr = 0x1b, |
| 5146 | .global2_addr = 0x1c, |
| 5147 | .age_time_coeff = 3750, |
| 5148 | .g1_irqs = 10, |
| 5149 | .g2_irqs = 14, |
| 5150 | .atu_move_port_mask = 0x1f, |
| 5151 | .pvt = true, |
| 5152 | .multi_chip = true, |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 5153 | .ptp_support = true, |
| 5154 | .ops = &mv88e6393x_ops, |
| 5155 | }, |
| 5156 | |
| 5157 | [MV88E6193X] = { |
| 5158 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, |
| 5159 | .family = MV88E6XXX_FAMILY_6393, |
| 5160 | .name = "Marvell 88E6193X", |
| 5161 | .num_databases = 4096, |
| 5162 | .num_ports = 11, /* 10 + Z80 */ |
| 5163 | .num_internal_phys = 9, |
| 5164 | .max_vid = 8191, |
| 5165 | .port_base_addr = 0x0, |
| 5166 | .phy_base_addr = 0x0, |
| 5167 | .global1_addr = 0x1b, |
| 5168 | .global2_addr = 0x1c, |
| 5169 | .age_time_coeff = 3750, |
| 5170 | .g1_irqs = 10, |
| 5171 | .g2_irqs = 14, |
| 5172 | .atu_move_port_mask = 0x1f, |
| 5173 | .pvt = true, |
| 5174 | .multi_chip = true, |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 5175 | .ptp_support = true, |
| 5176 | .ops = &mv88e6393x_ops, |
| 5177 | }, |
| 5178 | |
Hubert Feurstein | 4902264 | 2019-07-31 10:23:46 +0200 | [diff] [blame] | 5179 | [MV88E6220] = { |
| 5180 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, |
| 5181 | .family = MV88E6XXX_FAMILY_6250, |
| 5182 | .name = "Marvell 88E6220", |
| 5183 | .num_databases = 64, |
| 5184 | |
| 5185 | /* Ports 2-4 are not routed to pins |
| 5186 | * => usable ports 0, 1, 5, 6 |
| 5187 | */ |
| 5188 | .num_ports = 7, |
| 5189 | .num_internal_phys = 2, |
Hubert Feurstein | c857486 | 2019-07-31 10:23:48 +0200 | [diff] [blame] | 5190 | .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), |
Hubert Feurstein | 4902264 | 2019-07-31 10:23:46 +0200 | [diff] [blame] | 5191 | .max_vid = 4095, |
| 5192 | .port_base_addr = 0x08, |
| 5193 | .phy_base_addr = 0x00, |
| 5194 | .global1_addr = 0x0f, |
| 5195 | .global2_addr = 0x07, |
| 5196 | .age_time_coeff = 15000, |
| 5197 | .g1_irqs = 9, |
| 5198 | .g2_irqs = 10, |
| 5199 | .atu_move_port_mask = 0xf, |
| 5200 | .dual_chip = true, |
Hubert Feurstein | 7150961 | 2019-07-31 10:23:51 +0200 | [diff] [blame] | 5201 | .ptp_support = true, |
Hubert Feurstein | 4902264 | 2019-07-31 10:23:46 +0200 | [diff] [blame] | 5202 | .ops = &mv88e6250_ops, |
| 5203 | }, |
| 5204 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5205 | [MV88E6240] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5206 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5207 | .family = MV88E6XXX_FAMILY_6352, |
| 5208 | .name = "Marvell 88E6240", |
| 5209 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5210 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5211 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5212 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5213 | .num_gpio = 15, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5214 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5215 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5216 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5217 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5218 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5219 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5220 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5221 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5222 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5223 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5224 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5225 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5226 | .ptp_support = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5227 | .ops = &mv88e6240_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5228 | }, |
| 5229 | |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 5230 | [MV88E6250] = { |
| 5231 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, |
| 5232 | .family = MV88E6XXX_FAMILY_6250, |
| 5233 | .name = "Marvell 88E6250", |
| 5234 | .num_databases = 64, |
| 5235 | .num_ports = 7, |
| 5236 | .num_internal_phys = 5, |
| 5237 | .max_vid = 4095, |
| 5238 | .port_base_addr = 0x08, |
| 5239 | .phy_base_addr = 0x00, |
| 5240 | .global1_addr = 0x0f, |
| 5241 | .global2_addr = 0x07, |
| 5242 | .age_time_coeff = 15000, |
| 5243 | .g1_irqs = 9, |
| 5244 | .g2_irqs = 10, |
| 5245 | .atu_move_port_mask = 0xf, |
| 5246 | .dual_chip = true, |
Hubert Feurstein | 7150961 | 2019-07-31 10:23:51 +0200 | [diff] [blame] | 5247 | .ptp_support = true, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 5248 | .ops = &mv88e6250_ops, |
| 5249 | }, |
| 5250 | |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5251 | [MV88E6290] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5252 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5253 | .family = MV88E6XXX_FAMILY_6390, |
| 5254 | .name = "Marvell 88E6290", |
| 5255 | .num_databases = 4096, |
| 5256 | .num_ports = 11, /* 10 + Z80 */ |
Heiner Kallweit | 95150f2 | 2019-03-02 10:06:05 +0100 | [diff] [blame] | 5257 | .num_internal_phys = 9, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5258 | .num_gpio = 16, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 5259 | .max_vid = 8191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5260 | .port_base_addr = 0x0, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5261 | .phy_base_addr = 0x0, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5262 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5263 | .global2_addr = 0x1c, |
Andrew Lunn | b91e055 | 2017-02-02 00:46:15 +0100 | [diff] [blame] | 5264 | .age_time_coeff = 3750, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5265 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5266 | .g2_irqs = 14, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5267 | .atu_move_port_mask = 0x1f, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5268 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5269 | .multi_chip = true, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5270 | .ptp_support = true, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5271 | .ops = &mv88e6290_ops, |
| 5272 | }, |
| 5273 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5274 | [MV88E6320] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5275 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5276 | .family = MV88E6XXX_FAMILY_6320, |
| 5277 | .name = "Marvell 88E6320", |
| 5278 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5279 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5280 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5281 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5282 | .num_gpio = 15, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5283 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5284 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5285 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5286 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5287 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5288 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5289 | .g1_irqs = 8, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5290 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5291 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5292 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5293 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5294 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5295 | .ptp_support = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5296 | .ops = &mv88e6320_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5297 | }, |
| 5298 | |
| 5299 | [MV88E6321] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5300 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5301 | .family = MV88E6XXX_FAMILY_6320, |
| 5302 | .name = "Marvell 88E6321", |
| 5303 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5304 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5305 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5306 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5307 | .num_gpio = 15, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5308 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5309 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5310 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5311 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5312 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5313 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5314 | .g1_irqs = 8, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5315 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5316 | .atu_move_port_mask = 0xf, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5317 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5318 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5319 | .ptp_support = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5320 | .ops = &mv88e6321_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5321 | }, |
| 5322 | |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5323 | [MV88E6341] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5324 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5325 | .family = MV88E6XXX_FAMILY_6341, |
| 5326 | .name = "Marvell 88E6341", |
| 5327 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5328 | .num_macs = 2048, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5329 | .num_internal_phys = 5, |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5330 | .num_ports = 6, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5331 | .num_gpio = 11, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5332 | .max_vid = 4095, |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5333 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5334 | .phy_base_addr = 0x10, |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5335 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5336 | .global2_addr = 0x1c, |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5337 | .age_time_coeff = 3750, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5338 | .atu_move_port_mask = 0x1f, |
Andrew Lunn | adfccf1 | 2018-03-17 20:32:03 +0100 | [diff] [blame] | 5339 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5340 | .g2_irqs = 10, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5341 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5342 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5343 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5344 | .ptp_support = true, |
Gregory CLEMENT | a75961d | 2017-01-30 20:29:34 +0100 | [diff] [blame] | 5345 | .ops = &mv88e6341_ops, |
| 5346 | }, |
| 5347 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5348 | [MV88E6350] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5349 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5350 | .family = MV88E6XXX_FAMILY_6351, |
| 5351 | .name = "Marvell 88E6350", |
| 5352 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5353 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5354 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5355 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5356 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5357 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5358 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5359 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5360 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5361 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5362 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5363 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5364 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5365 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5366 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5367 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5368 | .ops = &mv88e6350_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5369 | }, |
| 5370 | |
| 5371 | [MV88E6351] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5372 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5373 | .family = MV88E6XXX_FAMILY_6351, |
| 5374 | .name = "Marvell 88E6351", |
| 5375 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5376 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5377 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5378 | .num_internal_phys = 5, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5379 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5380 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5381 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5382 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5383 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5384 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5385 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5386 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5387 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5388 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5389 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5390 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5391 | .ops = &mv88e6351_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5392 | }, |
| 5393 | |
| 5394 | [MV88E6352] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5395 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5396 | .family = MV88E6XXX_FAMILY_6352, |
| 5397 | .name = "Marvell 88E6352", |
| 5398 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5399 | .num_macs = 8192, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5400 | .num_ports = 7, |
Andrew Lunn | bc39315 | 2018-03-17 20:32:04 +0100 | [diff] [blame] | 5401 | .num_internal_phys = 5, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5402 | .num_gpio = 15, |
Vivien Didelot | 3cf3c84 | 2017-05-01 14:05:10 -0400 | [diff] [blame] | 5403 | .max_vid = 4095, |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 5404 | .port_base_addr = 0x10, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5405 | .phy_base_addr = 0x0, |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 5406 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5407 | .global2_addr = 0x1c, |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 5408 | .age_time_coeff = 15000, |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 5409 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5410 | .g2_irqs = 10, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5411 | .atu_move_port_mask = 0xf, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5412 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5413 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5414 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5415 | .ptp_support = true, |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 5416 | .ops = &mv88e6352_ops, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5417 | }, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5418 | [MV88E6390] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5419 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5420 | .family = MV88E6XXX_FAMILY_6390, |
| 5421 | .name = "Marvell 88E6390", |
| 5422 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5423 | .num_macs = 16384, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5424 | .num_ports = 11, /* 10 + Z80 */ |
Heiner Kallweit | 95150f2 | 2019-03-02 10:06:05 +0100 | [diff] [blame] | 5425 | .num_internal_phys = 9, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5426 | .num_gpio = 16, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 5427 | .max_vid = 8191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5428 | .port_base_addr = 0x0, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5429 | .phy_base_addr = 0x0, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5430 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5431 | .global2_addr = 0x1c, |
Andrew Lunn | b91e055 | 2017-02-02 00:46:15 +0100 | [diff] [blame] | 5432 | .age_time_coeff = 3750, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5433 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5434 | .g2_irqs = 14, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5435 | .atu_move_port_mask = 0x1f, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5436 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5437 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5438 | .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5439 | .ptp_support = true, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5440 | .ops = &mv88e6390_ops, |
| 5441 | }, |
| 5442 | [MV88E6390X] = { |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5443 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5444 | .family = MV88E6XXX_FAMILY_6390, |
| 5445 | .name = "Marvell 88E6390X", |
| 5446 | .num_databases = 4096, |
Andrew Lunn | d9ea562 | 2019-11-05 01:12:58 +0100 | [diff] [blame] | 5447 | .num_macs = 16384, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5448 | .num_ports = 11, /* 10 + Z80 */ |
Heiner Kallweit | 95150f2 | 2019-03-02 10:06:05 +0100 | [diff] [blame] | 5449 | .num_internal_phys = 9, |
Brandon Streiff | a73ccd6 | 2018-02-14 01:07:46 +0100 | [diff] [blame] | 5450 | .num_gpio = 16, |
Vivien Didelot | 931d182 | 2017-05-01 14:05:27 -0400 | [diff] [blame] | 5451 | .max_vid = 8191, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5452 | .port_base_addr = 0x0, |
Andrew Lunn | 9255bac | 2018-05-05 20:58:22 +0200 | [diff] [blame] | 5453 | .phy_base_addr = 0x0, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5454 | .global1_addr = 0x1b, |
Vivien Didelot | 9069c13 | 2017-07-17 13:03:44 -0400 | [diff] [blame] | 5455 | .global2_addr = 0x1c, |
Andrew Lunn | b91e055 | 2017-02-02 00:46:15 +0100 | [diff] [blame] | 5456 | .age_time_coeff = 3750, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5457 | .g1_irqs = 9, |
Vivien Didelot | d6c5e6a | 2017-07-17 13:03:40 -0400 | [diff] [blame] | 5458 | .g2_irqs = 14, |
Vivien Didelot | e606ca3 | 2017-03-11 16:12:55 -0500 | [diff] [blame] | 5459 | .atu_move_port_mask = 0x1f, |
Vivien Didelot | f364565 | 2017-03-30 17:37:07 -0400 | [diff] [blame] | 5460 | .pvt = true, |
Vivien Didelot | b3e05aa | 2017-07-17 13:03:46 -0400 | [diff] [blame] | 5461 | .multi_chip = true, |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5462 | .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 5463 | .ptp_support = true, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 5464 | .ops = &mv88e6390x_ops, |
| 5465 | }, |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 5466 | |
| 5467 | [MV88E6393X] = { |
| 5468 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, |
| 5469 | .family = MV88E6XXX_FAMILY_6393, |
| 5470 | .name = "Marvell 88E6393X", |
| 5471 | .num_databases = 4096, |
| 5472 | .num_ports = 11, /* 10 + Z80 */ |
| 5473 | .num_internal_phys = 9, |
| 5474 | .max_vid = 8191, |
| 5475 | .port_base_addr = 0x0, |
| 5476 | .phy_base_addr = 0x0, |
| 5477 | .global1_addr = 0x1b, |
| 5478 | .global2_addr = 0x1c, |
| 5479 | .age_time_coeff = 3750, |
| 5480 | .g1_irqs = 10, |
| 5481 | .g2_irqs = 14, |
| 5482 | .atu_move_port_mask = 0x1f, |
| 5483 | .pvt = true, |
| 5484 | .multi_chip = true, |
Pavana Sharma | de776d0 | 2021-03-17 14:46:42 +0100 | [diff] [blame] | 5485 | .ptp_support = true, |
| 5486 | .ops = &mv88e6393x_ops, |
| 5487 | }, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 5488 | }; |
| 5489 | |
Vivien Didelot | 5f7c036 | 2016-06-20 13:14:04 -0400 | [diff] [blame] | 5490 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 5491 | { |
Vivien Didelot | a439c06 | 2016-04-17 13:23:58 -0400 | [diff] [blame] | 5492 | int i; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 5493 | |
Vivien Didelot | 5f7c036 | 2016-06-20 13:14:04 -0400 | [diff] [blame] | 5494 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
| 5495 | if (mv88e6xxx_table[i].prod_num == prod_num) |
| 5496 | return &mv88e6xxx_table[i]; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 5497 | |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 5498 | return NULL; |
| 5499 | } |
| 5500 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5501 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 5502 | { |
| 5503 | const struct mv88e6xxx_info *info; |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 5504 | unsigned int prod_num, rev; |
| 5505 | u16 id; |
| 5506 | int err; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 5507 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5508 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5509 | err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5510 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 8f6345b | 2016-07-20 18:18:36 -0400 | [diff] [blame] | 5511 | if (err) |
| 5512 | return err; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 5513 | |
Vivien Didelot | 107fcc1 | 2017-06-12 12:37:36 -0400 | [diff] [blame] | 5514 | prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; |
| 5515 | rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 5516 | |
| 5517 | info = mv88e6xxx_lookup_info(prod_num); |
| 5518 | if (!info) |
| 5519 | return -ENODEV; |
| 5520 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 5521 | /* Update the compatible info with the probed one */ |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5522 | chip->info = info; |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 5523 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5524 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
| 5525 | chip->info->prod_num, chip->info->name, rev); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 5526 | |
| 5527 | return 0; |
| 5528 | } |
| 5529 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5530 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 5531 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5532 | struct mv88e6xxx_chip *chip; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 5533 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5534 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
| 5535 | if (!chip) |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 5536 | return NULL; |
| 5537 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5538 | chip->dev = dev; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 5539 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5540 | mutex_init(&chip->reg_lock); |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 5541 | INIT_LIST_HEAD(&chip->mdios); |
Vivien Didelot | da7dc87 | 2019-09-07 16:00:49 -0400 | [diff] [blame] | 5542 | idr_init(&chip->policies); |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 5543 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 5544 | return chip; |
Vivien Didelot | 469d729 | 2016-06-20 13:14:06 -0400 | [diff] [blame] | 5545 | } |
| 5546 | |
Florian Fainelli | 5ed4e3e | 2017-11-10 15:22:52 -0800 | [diff] [blame] | 5547 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, |
Florian Fainelli | 4d77648 | 2020-01-07 21:06:05 -0800 | [diff] [blame] | 5548 | int port, |
| 5549 | enum dsa_tag_protocol m) |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 5550 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 5551 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 5552 | |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 5553 | return chip->tag_protocol; |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 5554 | } |
| 5555 | |
Tobias Waldekranz | 9a99bef | 2021-04-20 20:53:08 +0200 | [diff] [blame] | 5556 | static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, |
| 5557 | enum dsa_tag_protocol proto) |
| 5558 | { |
| 5559 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5560 | enum dsa_tag_protocol old_protocol; |
| 5561 | int err; |
| 5562 | |
| 5563 | switch (proto) { |
| 5564 | case DSA_TAG_PROTO_EDSA: |
| 5565 | switch (chip->info->edsa_support) { |
| 5566 | case MV88E6XXX_EDSA_UNSUPPORTED: |
| 5567 | return -EPROTONOSUPPORT; |
| 5568 | case MV88E6XXX_EDSA_UNDOCUMENTED: |
| 5569 | dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); |
| 5570 | fallthrough; |
| 5571 | case MV88E6XXX_EDSA_SUPPORTED: |
| 5572 | break; |
| 5573 | } |
| 5574 | break; |
| 5575 | case DSA_TAG_PROTO_DSA: |
| 5576 | break; |
| 5577 | default: |
| 5578 | return -EPROTONOSUPPORT; |
| 5579 | } |
| 5580 | |
| 5581 | old_protocol = chip->tag_protocol; |
| 5582 | chip->tag_protocol = proto; |
| 5583 | |
| 5584 | mv88e6xxx_reg_lock(chip); |
| 5585 | err = mv88e6xxx_setup_port_mode(chip, port); |
| 5586 | mv88e6xxx_reg_unlock(chip); |
| 5587 | |
| 5588 | if (err) |
| 5589 | chip->tag_protocol = old_protocol; |
| 5590 | |
| 5591 | return err; |
| 5592 | } |
| 5593 | |
Vladimir Oltean | a52b2da | 2021-01-09 02:01:52 +0200 | [diff] [blame] | 5594 | static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, |
| 5595 | const struct switchdev_obj_port_mdb *mdb) |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 5596 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 5597 | struct mv88e6xxx_chip *chip = ds->priv; |
Vladimir Oltean | a52b2da | 2021-01-09 02:01:52 +0200 | [diff] [blame] | 5598 | int err; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 5599 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5600 | mv88e6xxx_reg_lock(chip); |
Vladimir Oltean | a52b2da | 2021-01-09 02:01:52 +0200 | [diff] [blame] | 5601 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, |
| 5602 | MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5603 | mv88e6xxx_reg_unlock(chip); |
Vladimir Oltean | a52b2da | 2021-01-09 02:01:52 +0200 | [diff] [blame] | 5604 | |
| 5605 | return err; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 5606 | } |
| 5607 | |
| 5608 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, |
| 5609 | const struct switchdev_obj_port_mdb *mdb) |
| 5610 | { |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 5611 | struct mv88e6xxx_chip *chip = ds->priv; |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 5612 | int err; |
| 5613 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5614 | mv88e6xxx_reg_lock(chip); |
Vivien Didelot | d8291a9 | 2019-09-07 16:00:47 -0400 | [diff] [blame] | 5615 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5616 | mv88e6xxx_reg_unlock(chip); |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 5617 | |
| 5618 | return err; |
| 5619 | } |
| 5620 | |
Iwan R Timmer | f0942e0 | 2019-11-07 22:11:14 +0100 | [diff] [blame] | 5621 | static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, |
| 5622 | struct dsa_mall_mirror_tc_entry *mirror, |
| 5623 | bool ingress) |
| 5624 | { |
| 5625 | enum mv88e6xxx_egress_direction direction = ingress ? |
| 5626 | MV88E6XXX_EGRESS_DIR_INGRESS : |
| 5627 | MV88E6XXX_EGRESS_DIR_EGRESS; |
| 5628 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5629 | bool other_mirrors = false; |
| 5630 | int i; |
| 5631 | int err; |
| 5632 | |
Iwan R Timmer | f0942e0 | 2019-11-07 22:11:14 +0100 | [diff] [blame] | 5633 | mutex_lock(&chip->reg_lock); |
| 5634 | if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != |
| 5635 | mirror->to_local_port) { |
| 5636 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) |
| 5637 | other_mirrors |= ingress ? |
| 5638 | chip->ports[i].mirror_ingress : |
| 5639 | chip->ports[i].mirror_egress; |
| 5640 | |
| 5641 | /* Can't change egress port when other mirror is active */ |
| 5642 | if (other_mirrors) { |
| 5643 | err = -EBUSY; |
| 5644 | goto out; |
| 5645 | } |
| 5646 | |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 5647 | err = mv88e6xxx_set_egress_port(chip, direction, |
| 5648 | mirror->to_local_port); |
Iwan R Timmer | f0942e0 | 2019-11-07 22:11:14 +0100 | [diff] [blame] | 5649 | if (err) |
| 5650 | goto out; |
| 5651 | } |
| 5652 | |
| 5653 | err = mv88e6xxx_port_set_mirror(chip, port, direction, true); |
| 5654 | out: |
| 5655 | mutex_unlock(&chip->reg_lock); |
| 5656 | |
| 5657 | return err; |
| 5658 | } |
| 5659 | |
| 5660 | static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, |
| 5661 | struct dsa_mall_mirror_tc_entry *mirror) |
| 5662 | { |
| 5663 | enum mv88e6xxx_egress_direction direction = mirror->ingress ? |
| 5664 | MV88E6XXX_EGRESS_DIR_INGRESS : |
| 5665 | MV88E6XXX_EGRESS_DIR_EGRESS; |
| 5666 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5667 | bool other_mirrors = false; |
| 5668 | int i; |
| 5669 | |
| 5670 | mutex_lock(&chip->reg_lock); |
| 5671 | if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) |
| 5672 | dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); |
| 5673 | |
| 5674 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) |
| 5675 | other_mirrors |= mirror->ingress ? |
| 5676 | chip->ports[i].mirror_ingress : |
| 5677 | chip->ports[i].mirror_egress; |
| 5678 | |
| 5679 | /* Reset egress port when no other mirror is active */ |
| 5680 | if (!other_mirrors) { |
Marek Behún | 2fda45f | 2021-03-17 14:46:41 +0100 | [diff] [blame] | 5681 | if (mv88e6xxx_set_egress_port(chip, direction, |
| 5682 | dsa_upstream_port(ds, port))) |
Iwan R Timmer | f0942e0 | 2019-11-07 22:11:14 +0100 | [diff] [blame] | 5683 | dev_err(ds->dev, "failed to set egress port\n"); |
| 5684 | } |
| 5685 | |
| 5686 | mutex_unlock(&chip->reg_lock); |
| 5687 | } |
| 5688 | |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 5689 | static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, |
| 5690 | struct switchdev_brport_flags flags, |
| 5691 | struct netlink_ext_ack *extack) |
| 5692 | { |
| 5693 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5694 | const struct mv88e6xxx_ops *ops; |
| 5695 | |
Tobias Waldekranz | 8d1d829 | 2021-03-18 20:25:40 +0100 | [diff] [blame] | 5696 | if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | |
| 5697 | BR_BCAST_FLOOD)) |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 5698 | return -EINVAL; |
| 5699 | |
| 5700 | ops = chip->info->ops; |
| 5701 | |
| 5702 | if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) |
| 5703 | return -EINVAL; |
| 5704 | |
| 5705 | if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) |
| 5706 | return -EINVAL; |
| 5707 | |
| 5708 | return 0; |
| 5709 | } |
| 5710 | |
| 5711 | static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, |
| 5712 | struct switchdev_brport_flags flags, |
| 5713 | struct netlink_ext_ack *extack) |
Russell King | 4f85901 | 2019-02-20 15:35:05 -0800 | [diff] [blame] | 5714 | { |
| 5715 | struct mv88e6xxx_chip *chip = ds->priv; |
Tobias Waldekranz | 041bd54 | 2021-03-18 20:25:39 +0100 | [diff] [blame] | 5716 | bool do_fast_age = false; |
Russell King | 4f85901 | 2019-02-20 15:35:05 -0800 | [diff] [blame] | 5717 | int err = -EOPNOTSUPP; |
| 5718 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5719 | mv88e6xxx_reg_lock(chip); |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 5720 | |
Tobias Waldekranz | 041bd54 | 2021-03-18 20:25:39 +0100 | [diff] [blame] | 5721 | if (flags.mask & BR_LEARNING) { |
| 5722 | bool learning = !!(flags.val & BR_LEARNING); |
| 5723 | u16 pav = learning ? (1 << port) : 0; |
| 5724 | |
| 5725 | err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); |
| 5726 | if (err) |
| 5727 | goto out; |
| 5728 | |
| 5729 | if (!learning) |
| 5730 | do_fast_age = true; |
| 5731 | } |
| 5732 | |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 5733 | if (flags.mask & BR_FLOOD) { |
| 5734 | bool unicast = !!(flags.val & BR_FLOOD); |
| 5735 | |
| 5736 | err = chip->info->ops->port_set_ucast_flood(chip, port, |
| 5737 | unicast); |
| 5738 | if (err) |
| 5739 | goto out; |
| 5740 | } |
| 5741 | |
| 5742 | if (flags.mask & BR_MCAST_FLOOD) { |
| 5743 | bool multicast = !!(flags.val & BR_MCAST_FLOOD); |
| 5744 | |
| 5745 | err = chip->info->ops->port_set_mcast_flood(chip, port, |
| 5746 | multicast); |
| 5747 | if (err) |
| 5748 | goto out; |
| 5749 | } |
| 5750 | |
Tobias Waldekranz | 8d1d829 | 2021-03-18 20:25:40 +0100 | [diff] [blame] | 5751 | if (flags.mask & BR_BCAST_FLOOD) { |
| 5752 | bool broadcast = !!(flags.val & BR_BCAST_FLOOD); |
| 5753 | |
| 5754 | err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); |
| 5755 | if (err) |
| 5756 | goto out; |
| 5757 | } |
| 5758 | |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 5759 | out: |
| 5760 | mv88e6xxx_reg_unlock(chip); |
| 5761 | |
Tobias Waldekranz | 041bd54 | 2021-03-18 20:25:39 +0100 | [diff] [blame] | 5762 | if (do_fast_age) |
| 5763 | mv88e6xxx_port_fast_age(ds, port); |
| 5764 | |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 5765 | return err; |
| 5766 | } |
| 5767 | |
| 5768 | static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port, |
| 5769 | bool mrouter, |
| 5770 | struct netlink_ext_ack *extack) |
| 5771 | { |
| 5772 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5773 | int err; |
| 5774 | |
| 5775 | if (!chip->info->ops->port_set_mcast_flood) |
| 5776 | return -EOPNOTSUPP; |
| 5777 | |
| 5778 | mv88e6xxx_reg_lock(chip); |
| 5779 | err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 5780 | mv88e6xxx_reg_unlock(chip); |
Russell King | 4f85901 | 2019-02-20 15:35:05 -0800 | [diff] [blame] | 5781 | |
| 5782 | return err; |
| 5783 | } |
| 5784 | |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 5785 | static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, |
| 5786 | struct net_device *lag, |
| 5787 | struct netdev_lag_upper_info *info) |
| 5788 | { |
Tobias Waldekranz | b80dc51 | 2021-01-15 13:52:59 +0100 | [diff] [blame] | 5789 | struct mv88e6xxx_chip *chip = ds->priv; |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 5790 | struct dsa_port *dp; |
| 5791 | int id, members = 0; |
| 5792 | |
Tobias Waldekranz | b80dc51 | 2021-01-15 13:52:59 +0100 | [diff] [blame] | 5793 | if (!mv88e6xxx_has_lag(chip)) |
| 5794 | return false; |
| 5795 | |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 5796 | id = dsa_lag_id(ds->dst, lag); |
| 5797 | if (id < 0 || id >= ds->num_lag_ids) |
| 5798 | return false; |
| 5799 | |
| 5800 | dsa_lag_foreach_port(dp, ds->dst, lag) |
| 5801 | /* Includes the port joining the LAG */ |
| 5802 | members++; |
| 5803 | |
| 5804 | if (members > 8) |
| 5805 | return false; |
| 5806 | |
| 5807 | /* We could potentially relax this to include active |
| 5808 | * backup in the future. |
| 5809 | */ |
| 5810 | if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) |
| 5811 | return false; |
| 5812 | |
| 5813 | /* Ideally we would also validate that the hash type matches |
| 5814 | * the hardware. Alas, this is always set to unknown on team |
| 5815 | * interfaces. |
| 5816 | */ |
| 5817 | return true; |
| 5818 | } |
| 5819 | |
| 5820 | static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) |
| 5821 | { |
| 5822 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5823 | struct dsa_port *dp; |
| 5824 | u16 map = 0; |
| 5825 | int id; |
| 5826 | |
| 5827 | id = dsa_lag_id(ds->dst, lag); |
| 5828 | |
| 5829 | /* Build the map of all ports to distribute flows destined for |
| 5830 | * this LAG. This can be either a local user port, or a DSA |
| 5831 | * port if the LAG port is on a remote chip. |
| 5832 | */ |
| 5833 | dsa_lag_foreach_port(dp, ds->dst, lag) |
| 5834 | map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); |
| 5835 | |
| 5836 | return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); |
| 5837 | } |
| 5838 | |
| 5839 | static const u8 mv88e6xxx_lag_mask_table[8][8] = { |
| 5840 | /* Row number corresponds to the number of active members in a |
| 5841 | * LAG. Each column states which of the eight hash buckets are |
| 5842 | * mapped to the column:th port in the LAG. |
| 5843 | * |
| 5844 | * Example: In a LAG with three active ports, the second port |
| 5845 | * ([2][1]) would be selected for traffic mapped to buckets |
| 5846 | * 3,4,5 (0x38). |
| 5847 | */ |
| 5848 | { 0xff, 0, 0, 0, 0, 0, 0, 0 }, |
| 5849 | { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, |
| 5850 | { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, |
| 5851 | { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, |
| 5852 | { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, |
| 5853 | { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, |
| 5854 | { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, |
| 5855 | { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, |
| 5856 | }; |
| 5857 | |
| 5858 | static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, |
| 5859 | int num_tx, int nth) |
| 5860 | { |
| 5861 | u8 active = 0; |
| 5862 | int i; |
| 5863 | |
| 5864 | num_tx = num_tx <= 8 ? num_tx : 8; |
| 5865 | if (nth < num_tx) |
| 5866 | active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; |
| 5867 | |
| 5868 | for (i = 0; i < 8; i++) { |
| 5869 | if (BIT(i) & active) |
| 5870 | mask[i] |= BIT(port); |
| 5871 | } |
| 5872 | } |
| 5873 | |
| 5874 | static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) |
| 5875 | { |
| 5876 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5877 | unsigned int id, num_tx; |
| 5878 | struct net_device *lag; |
| 5879 | struct dsa_port *dp; |
| 5880 | int i, err, nth; |
| 5881 | u16 mask[8]; |
| 5882 | u16 ivec; |
| 5883 | |
| 5884 | /* Assume no port is a member of any LAG. */ |
| 5885 | ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; |
| 5886 | |
| 5887 | /* Disable all masks for ports that _are_ members of a LAG. */ |
| 5888 | list_for_each_entry(dp, &ds->dst->ports, list) { |
| 5889 | if (!dp->lag_dev || dp->ds != ds) |
| 5890 | continue; |
| 5891 | |
| 5892 | ivec &= ~BIT(dp->index); |
| 5893 | } |
| 5894 | |
| 5895 | for (i = 0; i < 8; i++) |
| 5896 | mask[i] = ivec; |
| 5897 | |
| 5898 | /* Enable the correct subset of masks for all LAG ports that |
| 5899 | * are in the Tx set. |
| 5900 | */ |
| 5901 | dsa_lags_foreach_id(id, ds->dst) { |
| 5902 | lag = dsa_lag_dev(ds->dst, id); |
| 5903 | if (!lag) |
| 5904 | continue; |
| 5905 | |
| 5906 | num_tx = 0; |
| 5907 | dsa_lag_foreach_port(dp, ds->dst, lag) { |
| 5908 | if (dp->lag_tx_enabled) |
| 5909 | num_tx++; |
| 5910 | } |
| 5911 | |
| 5912 | if (!num_tx) |
| 5913 | continue; |
| 5914 | |
| 5915 | nth = 0; |
| 5916 | dsa_lag_foreach_port(dp, ds->dst, lag) { |
| 5917 | if (!dp->lag_tx_enabled) |
| 5918 | continue; |
| 5919 | |
| 5920 | if (dp->ds == ds) |
| 5921 | mv88e6xxx_lag_set_port_mask(mask, dp->index, |
| 5922 | num_tx, nth); |
| 5923 | |
| 5924 | nth++; |
| 5925 | } |
| 5926 | } |
| 5927 | |
| 5928 | for (i = 0; i < 8; i++) { |
| 5929 | err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); |
| 5930 | if (err) |
| 5931 | return err; |
| 5932 | } |
| 5933 | |
| 5934 | return 0; |
| 5935 | } |
| 5936 | |
| 5937 | static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, |
| 5938 | struct net_device *lag) |
| 5939 | { |
| 5940 | int err; |
| 5941 | |
| 5942 | err = mv88e6xxx_lag_sync_masks(ds); |
| 5943 | |
| 5944 | if (!err) |
| 5945 | err = mv88e6xxx_lag_sync_map(ds, lag); |
| 5946 | |
| 5947 | return err; |
| 5948 | } |
| 5949 | |
| 5950 | static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) |
| 5951 | { |
| 5952 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5953 | int err; |
| 5954 | |
| 5955 | mv88e6xxx_reg_lock(chip); |
| 5956 | err = mv88e6xxx_lag_sync_masks(ds); |
| 5957 | mv88e6xxx_reg_unlock(chip); |
| 5958 | return err; |
| 5959 | } |
| 5960 | |
| 5961 | static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, |
| 5962 | struct net_device *lag, |
| 5963 | struct netdev_lag_upper_info *info) |
| 5964 | { |
| 5965 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5966 | int err, id; |
| 5967 | |
| 5968 | if (!mv88e6xxx_lag_can_offload(ds, lag, info)) |
| 5969 | return -EOPNOTSUPP; |
| 5970 | |
| 5971 | id = dsa_lag_id(ds->dst, lag); |
| 5972 | |
| 5973 | mv88e6xxx_reg_lock(chip); |
| 5974 | |
| 5975 | err = mv88e6xxx_port_set_trunk(chip, port, true, id); |
| 5976 | if (err) |
| 5977 | goto err_unlock; |
| 5978 | |
| 5979 | err = mv88e6xxx_lag_sync_masks_map(ds, lag); |
| 5980 | if (err) |
| 5981 | goto err_clear_trunk; |
| 5982 | |
| 5983 | mv88e6xxx_reg_unlock(chip); |
| 5984 | return 0; |
| 5985 | |
| 5986 | err_clear_trunk: |
| 5987 | mv88e6xxx_port_set_trunk(chip, port, false, 0); |
| 5988 | err_unlock: |
| 5989 | mv88e6xxx_reg_unlock(chip); |
| 5990 | return err; |
| 5991 | } |
| 5992 | |
| 5993 | static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, |
| 5994 | struct net_device *lag) |
| 5995 | { |
| 5996 | struct mv88e6xxx_chip *chip = ds->priv; |
| 5997 | int err_sync, err_trunk; |
| 5998 | |
| 5999 | mv88e6xxx_reg_lock(chip); |
| 6000 | err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); |
| 6001 | err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); |
| 6002 | mv88e6xxx_reg_unlock(chip); |
| 6003 | return err_sync ? : err_trunk; |
| 6004 | } |
| 6005 | |
| 6006 | static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, |
| 6007 | int port) |
| 6008 | { |
| 6009 | struct mv88e6xxx_chip *chip = ds->priv; |
| 6010 | int err; |
| 6011 | |
| 6012 | mv88e6xxx_reg_lock(chip); |
| 6013 | err = mv88e6xxx_lag_sync_masks(ds); |
| 6014 | mv88e6xxx_reg_unlock(chip); |
| 6015 | return err; |
| 6016 | } |
| 6017 | |
| 6018 | static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, |
| 6019 | int port, struct net_device *lag, |
| 6020 | struct netdev_lag_upper_info *info) |
| 6021 | { |
| 6022 | struct mv88e6xxx_chip *chip = ds->priv; |
| 6023 | int err; |
| 6024 | |
| 6025 | if (!mv88e6xxx_lag_can_offload(ds, lag, info)) |
| 6026 | return -EOPNOTSUPP; |
| 6027 | |
| 6028 | mv88e6xxx_reg_lock(chip); |
| 6029 | |
| 6030 | err = mv88e6xxx_lag_sync_masks_map(ds, lag); |
| 6031 | if (err) |
| 6032 | goto unlock; |
| 6033 | |
| 6034 | err = mv88e6xxx_pvt_map(chip, sw_index, port); |
| 6035 | |
| 6036 | unlock: |
| 6037 | mv88e6xxx_reg_unlock(chip); |
| 6038 | return err; |
| 6039 | } |
| 6040 | |
| 6041 | static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, |
| 6042 | int port, struct net_device *lag) |
| 6043 | { |
| 6044 | struct mv88e6xxx_chip *chip = ds->priv; |
| 6045 | int err_sync, err_pvt; |
| 6046 | |
| 6047 | mv88e6xxx_reg_lock(chip); |
| 6048 | err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); |
| 6049 | err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); |
| 6050 | mv88e6xxx_reg_unlock(chip); |
| 6051 | return err_sync ? : err_pvt; |
| 6052 | } |
| 6053 | |
Florian Fainelli | a82f67a | 2017-01-08 14:52:08 -0800 | [diff] [blame] | 6054 | static const struct dsa_switch_ops mv88e6xxx_switch_ops = { |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 6055 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
Tobias Waldekranz | 9a99bef | 2021-04-20 20:53:08 +0200 | [diff] [blame] | 6056 | .change_tag_protocol = mv88e6xxx_change_tag_protocol, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6057 | .setup = mv88e6xxx_setup, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 6058 | .teardown = mv88e6xxx_teardown, |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 6059 | .phylink_validate = mv88e6xxx_validate, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 6060 | .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 6061 | .phylink_mac_config = mv88e6xxx_mac_config, |
Russell King | a5a6858 | 2020-03-14 10:15:43 +0000 | [diff] [blame] | 6062 | .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 6063 | .phylink_mac_link_down = mv88e6xxx_mac_link_down, |
| 6064 | .phylink_mac_link_up = mv88e6xxx_mac_link_up, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6065 | .get_strings = mv88e6xxx_get_strings, |
| 6066 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, |
| 6067 | .get_sset_count = mv88e6xxx_get_sset_count, |
Andrew Lunn | 04aca99 | 2017-05-26 01:03:24 +0200 | [diff] [blame] | 6068 | .port_enable = mv88e6xxx_port_enable, |
| 6069 | .port_disable = mv88e6xxx_port_disable, |
Andrew Lunn | 2a550ae | 2020-07-11 22:32:05 +0200 | [diff] [blame] | 6070 | .port_max_mtu = mv88e6xxx_get_max_mtu, |
| 6071 | .port_change_mtu = mv88e6xxx_change_mtu, |
Vivien Didelot | 08f5006 | 2017-08-01 16:32:41 -0400 | [diff] [blame] | 6072 | .get_mac_eee = mv88e6xxx_get_mac_eee, |
| 6073 | .set_mac_eee = mv88e6xxx_set_mac_eee, |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 6074 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6075 | .get_eeprom = mv88e6xxx_get_eeprom, |
| 6076 | .set_eeprom = mv88e6xxx_set_eeprom, |
| 6077 | .get_regs_len = mv88e6xxx_get_regs_len, |
| 6078 | .get_regs = mv88e6xxx_get_regs, |
Vivien Didelot | da7dc87 | 2019-09-07 16:00:49 -0400 | [diff] [blame] | 6079 | .get_rxnfc = mv88e6xxx_get_rxnfc, |
| 6080 | .set_rxnfc = mv88e6xxx_set_rxnfc, |
Vivien Didelot | 2cfcd96 | 2016-07-18 20:45:40 -0400 | [diff] [blame] | 6081 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6082 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
| 6083 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, |
Vladimir Oltean | a8b659e | 2021-02-12 17:15:56 +0200 | [diff] [blame] | 6084 | .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, |
| 6085 | .port_bridge_flags = mv88e6xxx_port_bridge_flags, |
| 6086 | .port_set_mrouter = mv88e6xxx_port_set_mrouter, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6087 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, |
Vivien Didelot | 749efcb | 2016-09-22 16:49:24 -0400 | [diff] [blame] | 6088 | .port_fast_age = mv88e6xxx_port_fast_age, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6089 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6090 | .port_vlan_add = mv88e6xxx_port_vlan_add, |
| 6091 | .port_vlan_del = mv88e6xxx_port_vlan_del, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6092 | .port_fdb_add = mv88e6xxx_port_fdb_add, |
| 6093 | .port_fdb_del = mv88e6xxx_port_fdb_del, |
| 6094 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, |
Vivien Didelot | 7df8fbd | 2016-08-31 11:50:05 -0400 | [diff] [blame] | 6095 | .port_mdb_add = mv88e6xxx_port_mdb_add, |
| 6096 | .port_mdb_del = mv88e6xxx_port_mdb_del, |
Iwan R Timmer | f0942e0 | 2019-11-07 22:11:14 +0100 | [diff] [blame] | 6097 | .port_mirror_add = mv88e6xxx_port_mirror_add, |
| 6098 | .port_mirror_del = mv88e6xxx_port_mirror_del, |
Vivien Didelot | aec5ac8 | 2017-03-30 17:37:15 -0400 | [diff] [blame] | 6099 | .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, |
| 6100 | .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, |
Brandon Streiff | c6fe0ad | 2018-02-14 01:07:50 +0100 | [diff] [blame] | 6101 | .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, |
| 6102 | .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, |
| 6103 | .port_txtstamp = mv88e6xxx_port_txtstamp, |
| 6104 | .port_rxtstamp = mv88e6xxx_port_rxtstamp, |
| 6105 | .get_ts_info = mv88e6xxx_get_ts_info, |
Andrew Lunn | 23e8b47 | 2019-10-25 01:03:52 +0200 | [diff] [blame] | 6106 | .devlink_param_get = mv88e6xxx_devlink_param_get, |
| 6107 | .devlink_param_set = mv88e6xxx_devlink_param_set, |
Andrew Lunn | 9315730 | 2020-09-18 21:11:09 +0200 | [diff] [blame] | 6108 | .devlink_info_get = mv88e6xxx_devlink_info_get, |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 6109 | .port_lag_change = mv88e6xxx_port_lag_change, |
| 6110 | .port_lag_join = mv88e6xxx_port_lag_join, |
| 6111 | .port_lag_leave = mv88e6xxx_port_lag_leave, |
| 6112 | .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, |
| 6113 | .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, |
| 6114 | .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 6115 | }; |
| 6116 | |
Florian Fainelli | 55ed0ce | 2017-01-26 10:45:51 -0800 | [diff] [blame] | 6117 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6118 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6119 | struct device *dev = chip->dev; |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6120 | struct dsa_switch *ds; |
| 6121 | |
Vivien Didelot | 7e99e34 | 2019-10-21 16:51:30 -0400 | [diff] [blame] | 6122 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6123 | if (!ds) |
| 6124 | return -ENOMEM; |
| 6125 | |
Vivien Didelot | 7e99e34 | 2019-10-21 16:51:30 -0400 | [diff] [blame] | 6126 | ds->dev = dev; |
| 6127 | ds->num_ports = mv88e6xxx_num_ports(chip); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6128 | ds->priv = chip; |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6129 | ds->dev = dev; |
Vivien Didelot | 9d490b4 | 2016-08-23 12:38:56 -0400 | [diff] [blame] | 6130 | ds->ops = &mv88e6xxx_switch_ops; |
Vivien Didelot | 9ff74f2 | 2017-03-15 15:53:50 -0400 | [diff] [blame] | 6131 | ds->ageing_time_min = chip->info->age_time_coeff; |
| 6132 | ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6133 | |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 6134 | /* Some chips support up to 32, but that requires enabling the |
| 6135 | * 5-bit port mode, which we do not support. 640k^W16 ought to |
| 6136 | * be enough for anyone. |
| 6137 | */ |
Tobias Waldekranz | b80dc51 | 2021-01-15 13:52:59 +0100 | [diff] [blame] | 6138 | ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; |
Tobias Waldekranz | 57e661a | 2021-01-13 09:42:54 +0100 | [diff] [blame] | 6139 | |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6140 | dev_set_drvdata(dev, ds); |
| 6141 | |
Vivien Didelot | 23c9ee4 | 2017-05-26 18:12:51 -0400 | [diff] [blame] | 6142 | return dsa_register_switch(ds); |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6143 | } |
| 6144 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6145 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6146 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6147 | dsa_unregister_switch(chip->ds); |
Vivien Didelot | b7e66a5 | 2016-06-20 13:14:02 -0400 | [diff] [blame] | 6148 | } |
| 6149 | |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6150 | static const void *pdata_device_get_match_data(struct device *dev) |
| 6151 | { |
| 6152 | const struct of_device_id *matches = dev->driver->of_match_table; |
| 6153 | const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; |
| 6154 | |
| 6155 | for (; matches->name[0] || matches->type[0] || matches->compatible[0]; |
| 6156 | matches++) { |
| 6157 | if (!strcmp(pdata->compatible, matches->compatible)) |
| 6158 | return matches->data; |
| 6159 | } |
| 6160 | return NULL; |
| 6161 | } |
| 6162 | |
Miquel Raynal | bcd3d9d | 2019-02-05 12:07:28 +0100 | [diff] [blame] | 6163 | /* There is no suspend to RAM support at DSA level yet, the switch configuration |
| 6164 | * would be lost after a power cycle so prevent it to be suspended. |
| 6165 | */ |
| 6166 | static int __maybe_unused mv88e6xxx_suspend(struct device *dev) |
| 6167 | { |
| 6168 | return -EOPNOTSUPP; |
| 6169 | } |
| 6170 | |
| 6171 | static int __maybe_unused mv88e6xxx_resume(struct device *dev) |
| 6172 | { |
| 6173 | return 0; |
| 6174 | } |
| 6175 | |
| 6176 | static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); |
| 6177 | |
Vivien Didelot | 57d3231 | 2016-06-20 13:13:58 -0400 | [diff] [blame] | 6178 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6179 | { |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6180 | struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; |
David S. Miller | 7ddae24 | 2018-05-20 19:04:24 -0400 | [diff] [blame] | 6181 | const struct mv88e6xxx_info *compat_info = NULL; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6182 | struct device *dev = &mdiodev->dev; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 6183 | struct device_node *np = dev->of_node; |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6184 | struct mv88e6xxx_chip *chip; |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6185 | int port; |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 6186 | int err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6187 | |
Andrew Lunn | 7bb8c99 | 2018-05-31 00:15:42 +0200 | [diff] [blame] | 6188 | if (!np && !pdata) |
| 6189 | return -EINVAL; |
| 6190 | |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6191 | if (np) |
| 6192 | compat_info = of_device_get_match_data(dev); |
| 6193 | |
| 6194 | if (pdata) { |
| 6195 | compat_info = pdata_device_get_match_data(dev); |
| 6196 | |
| 6197 | if (!pdata->netdev) |
| 6198 | return -EINVAL; |
| 6199 | |
| 6200 | for (port = 0; port < DSA_MAX_PORTS; port++) { |
| 6201 | if (!(pdata->enabled_ports & (1 << port))) |
| 6202 | continue; |
| 6203 | if (strcmp(pdata->cd.port_names[port], "cpu")) |
| 6204 | continue; |
| 6205 | pdata->cd.netdev[port] = &pdata->netdev->dev; |
| 6206 | break; |
| 6207 | } |
| 6208 | } |
| 6209 | |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 6210 | if (!compat_info) |
| 6211 | return -EINVAL; |
| 6212 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6213 | chip = mv88e6xxx_alloc_chip(dev); |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6214 | if (!chip) { |
| 6215 | err = -ENOMEM; |
| 6216 | goto out; |
| 6217 | } |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6218 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6219 | chip->info = compat_info; |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 6220 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6221 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
Vivien Didelot | 4a70c4a | 2016-06-20 13:14:07 -0400 | [diff] [blame] | 6222 | if (err) |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6223 | goto out; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6224 | |
Andrew Lunn | b4308f0 | 2016-11-21 23:26:55 +0100 | [diff] [blame] | 6225 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6226 | if (IS_ERR(chip->reset)) { |
| 6227 | err = PTR_ERR(chip->reset); |
| 6228 | goto out; |
| 6229 | } |
Baruch Siach | 7b75e49 | 2019-06-27 21:17:39 +0300 | [diff] [blame] | 6230 | if (chip->reset) |
| 6231 | usleep_range(1000, 2000); |
Andrew Lunn | b4308f0 | 2016-11-21 23:26:55 +0100 | [diff] [blame] | 6232 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6233 | err = mv88e6xxx_detect(chip); |
Vivien Didelot | bc46a3d | 2016-06-20 13:14:08 -0400 | [diff] [blame] | 6234 | if (err) |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6235 | goto out; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6236 | |
Tobias Waldekranz | 670bb80 | 2021-04-20 20:53:07 +0200 | [diff] [blame] | 6237 | if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) |
| 6238 | chip->tag_protocol = DSA_TAG_PROTO_EDSA; |
| 6239 | else |
| 6240 | chip->tag_protocol = DSA_TAG_PROTO_DSA; |
| 6241 | |
Vivien Didelot | e57e5e7 | 2016-08-15 17:19:00 -0400 | [diff] [blame] | 6242 | mv88e6xxx_phy_init(chip); |
| 6243 | |
Andrew Lunn | 00baabe | 2018-05-19 22:31:35 +0200 | [diff] [blame] | 6244 | if (chip->info->ops->get_eeprom) { |
| 6245 | if (np) |
| 6246 | of_property_read_u32(np, "eeprom-length", |
| 6247 | &chip->eeprom_len); |
| 6248 | else |
| 6249 | chip->eeprom_len = pdata->eeprom_len; |
| 6250 | } |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 6251 | |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 6252 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6253 | err = mv88e6xxx_switch_reset(chip); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 6254 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 6255 | if (err) |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6256 | goto out; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 6257 | |
Andrew Lunn | a27415d | 2019-05-01 00:10:50 +0200 | [diff] [blame] | 6258 | if (np) { |
| 6259 | chip->irq = of_irq_get(np, 0); |
| 6260 | if (chip->irq == -EPROBE_DEFER) { |
| 6261 | err = chip->irq; |
| 6262 | goto out; |
| 6263 | } |
Andrew Lunn | 83c0afa | 2016-06-04 21:17:07 +0200 | [diff] [blame] | 6264 | } |
| 6265 | |
Andrew Lunn | a27415d | 2019-05-01 00:10:50 +0200 | [diff] [blame] | 6266 | if (pdata) |
| 6267 | chip->irq = pdata->irq; |
| 6268 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6269 | /* Has to be performed before the MDIO bus is created, because |
Uwe Kleine-König | a708767 | 2018-03-20 10:44:41 +0100 | [diff] [blame] | 6270 | * the PHYs will link their interrupts to these interrupt |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6271 | * controllers |
| 6272 | */ |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 6273 | mv88e6xxx_reg_lock(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6274 | if (chip->irq > 0) |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6275 | err = mv88e6xxx_g1_irq_setup(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6276 | else |
| 6277 | err = mv88e6xxx_irq_poll_setup(chip); |
Rasmus Villemoes | c9acece | 2019-06-20 13:50:42 +0000 | [diff] [blame] | 6278 | mv88e6xxx_reg_unlock(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6279 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6280 | if (err) |
| 6281 | goto out; |
| 6282 | |
| 6283 | if (chip->info->g2_irqs > 0) { |
| 6284 | err = mv88e6xxx_g2_irq_setup(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6285 | if (err) |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6286 | goto out_g1_irq; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6287 | } |
| 6288 | |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6289 | err = mv88e6xxx_g1_atu_prob_irq_setup(chip); |
| 6290 | if (err) |
| 6291 | goto out_g2_irq; |
| 6292 | |
| 6293 | err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); |
| 6294 | if (err) |
| 6295 | goto out_g1_atu_prob_irq; |
| 6296 | |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 6297 | err = mv88e6xxx_mdios_register(chip, np); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6298 | if (err) |
Andrew Lunn | 62eb116 | 2018-01-14 02:32:45 +0100 | [diff] [blame] | 6299 | goto out_g1_vtu_prob_irq; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6300 | |
Florian Fainelli | 55ed0ce | 2017-01-26 10:45:51 -0800 | [diff] [blame] | 6301 | err = mv88e6xxx_register_switch(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6302 | if (err) |
| 6303 | goto out_mdio; |
| 6304 | |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6305 | return 0; |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6306 | |
| 6307 | out_mdio: |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 6308 | mv88e6xxx_mdios_unregister(chip); |
Andrew Lunn | 62eb116 | 2018-01-14 02:32:45 +0100 | [diff] [blame] | 6309 | out_g1_vtu_prob_irq: |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6310 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
Andrew Lunn | 0977644 | 2018-01-14 02:32:44 +0100 | [diff] [blame] | 6311 | out_g1_atu_prob_irq: |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6312 | mv88e6xxx_g1_atu_prob_irq_free(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6313 | out_g2_irq: |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6314 | if (chip->info->g2_irqs > 0) |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6315 | mv88e6xxx_g2_irq_free(chip); |
| 6316 | out_g1_irq: |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6317 | if (chip->irq > 0) |
Andrew Lunn | 46712644 | 2016-11-20 20:14:15 +0100 | [diff] [blame] | 6318 | mv88e6xxx_g1_irq_free(chip); |
Andrew Lunn | 294d711 | 2018-02-22 22:58:32 +0100 | [diff] [blame] | 6319 | else |
| 6320 | mv88e6xxx_irq_poll_free(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6321 | out: |
Andrew Lunn | 877b7cb | 2018-05-19 22:31:34 +0200 | [diff] [blame] | 6322 | if (pdata) |
| 6323 | dev_put(pdata->netdev); |
| 6324 | |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6325 | return err; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6326 | } |
| 6327 | |
| 6328 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) |
| 6329 | { |
| 6330 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); |
Vivien Didelot | 04bed14 | 2016-08-31 18:06:13 -0400 | [diff] [blame] | 6331 | struct mv88e6xxx_chip *chip = ds->priv; |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6332 | |
Brandon Streiff | c6fe0ad | 2018-02-14 01:07:50 +0100 | [diff] [blame] | 6333 | if (chip->info->ptp_support) { |
| 6334 | mv88e6xxx_hwtstamp_free(chip); |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 6335 | mv88e6xxx_ptp_free(chip); |
Brandon Streiff | c6fe0ad | 2018-02-14 01:07:50 +0100 | [diff] [blame] | 6336 | } |
Brandon Streiff | 2fa8d3a | 2018-02-14 01:07:45 +0100 | [diff] [blame] | 6337 | |
Andrew Lunn | 930188c | 2016-08-22 16:01:03 +0200 | [diff] [blame] | 6338 | mv88e6xxx_phy_destroy(chip); |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 6339 | mv88e6xxx_unregister_switch(chip); |
Andrew Lunn | a3c53be5 | 2017-01-24 14:53:50 +0100 | [diff] [blame] | 6340 | mv88e6xxx_mdios_unregister(chip); |
Andrew Lunn | dc30c35 | 2016-10-16 19:56:49 +0200 | [diff] [blame] | 6341 | |
Andrew Lunn | 76f38f1 | 2018-03-17 20:21:09 +0100 | [diff] [blame] | 6342 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
| 6343 | mv88e6xxx_g1_atu_prob_irq_free(chip); |
| 6344 | |
| 6345 | if (chip->info->g2_irqs > 0) |
| 6346 | mv88e6xxx_g2_irq_free(chip); |
| 6347 | |
Andrew Lunn | 76f38f1 | 2018-03-17 20:21:09 +0100 | [diff] [blame] | 6348 | if (chip->irq > 0) |
Andrew Lunn | 46712644 | 2016-11-20 20:14:15 +0100 | [diff] [blame] | 6349 | mv88e6xxx_g1_irq_free(chip); |
Andrew Lunn | 76f38f1 | 2018-03-17 20:21:09 +0100 | [diff] [blame] | 6350 | else |
| 6351 | mv88e6xxx_irq_poll_free(chip); |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6352 | } |
| 6353 | |
| 6354 | static const struct of_device_id mv88e6xxx_of_match[] = { |
Vivien Didelot | caac854 | 2016-06-20 13:14:09 -0400 | [diff] [blame] | 6355 | { |
| 6356 | .compatible = "marvell,mv88e6085", |
| 6357 | .data = &mv88e6xxx_table[MV88E6085], |
| 6358 | }, |
Andrew Lunn | 1a3b39e | 2016-11-21 23:26:57 +0100 | [diff] [blame] | 6359 | { |
| 6360 | .compatible = "marvell,mv88e6190", |
| 6361 | .data = &mv88e6xxx_table[MV88E6190], |
| 6362 | }, |
Rasmus Villemoes | 1f71836 | 2019-06-04 07:34:32 +0000 | [diff] [blame] | 6363 | { |
| 6364 | .compatible = "marvell,mv88e6250", |
| 6365 | .data = &mv88e6xxx_table[MV88E6250], |
| 6366 | }, |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6367 | { /* sentinel */ }, |
| 6368 | }; |
| 6369 | |
| 6370 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); |
| 6371 | |
| 6372 | static struct mdio_driver mv88e6xxx_driver = { |
| 6373 | .probe = mv88e6xxx_probe, |
| 6374 | .remove = mv88e6xxx_remove, |
| 6375 | .mdiodrv.driver = { |
| 6376 | .name = "mv88e6085", |
| 6377 | .of_match_table = mv88e6xxx_of_match, |
Miquel Raynal | bcd3d9d | 2019-02-05 12:07:28 +0100 | [diff] [blame] | 6378 | .pm = &mv88e6xxx_pm_ops, |
Andrew Lunn | 14c7b3c | 2016-05-10 23:27:21 +0200 | [diff] [blame] | 6379 | }, |
| 6380 | }; |
| 6381 | |
Andrew Lunn | 7324d50 | 2019-04-27 19:19:10 +0200 | [diff] [blame] | 6382 | mdio_module_driver(mv88e6xxx_driver); |
Ben Hutchings | 3d825ed | 2011-11-25 14:37:16 +0000 | [diff] [blame] | 6383 | |
| 6384 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); |
| 6385 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); |
| 6386 | MODULE_LICENSE("GPL"); |