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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00002/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04003 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00005 * Copyright (c) 2008 Marvell Semiconductor
6 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02007 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
Vivien Didelot4333d612017-03-28 15:10:36 -04009 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 */
12
Vivien Didelot19fb7f62019-08-09 18:47:55 -040013#include <linux/bitfield.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000014#include <linux/delay.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070015#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020016#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070017#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020018#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000021#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000022#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020023#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000024#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040025#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020026#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020027#include <linux/of_mdio.h>
Andrew Lunn877b7cb2018-05-19 22:31:34 +020028#include <linux/platform_data/mv88e6xxx.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000029#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010030#include <linux/gpio/consumer.h>
Russell Kingc9a23562018-05-10 13:17:35 -070031#include <linux/phylink.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000032#include <net/dsa.h>
Vivien Didelotec561272016-09-02 14:45:33 -040033
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -040034#include "chip.h"
Andrew Lunn9dd43aa2020-09-18 21:11:05 +020035#include "devlink.h"
Vivien Didelota935c052016-09-29 12:21:53 -040036#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040037#include "global2.h"
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +010038#include "hwtstamp.h"
Andrew Lunn10fa5bf2017-05-26 01:03:20 +020039#include "phy.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010040#include "port.h"
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +010041#include "ptp.h"
Andrew Lunn6d917822017-05-26 01:03:21 +020042#include "serdes.h"
Vivien Didelote7ba0fa2019-05-03 19:28:22 -040043#include "smi.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000044
Vivien Didelotfad09c72016-06-21 12:28:20 -040045static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040046{
Vivien Didelotfad09c72016-06-21 12:28:20 -040047 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040049 dump_stack();
50 }
51}
52
Vivien Didelotec561272016-09-02 14:45:33 -040053int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040054{
55 int err;
56
Vivien Didelotfad09c72016-06-21 12:28:20 -040057 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040058
Vivien Didelotfad09c72016-06-21 12:28:20 -040059 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040060 if (err)
61 return err;
62
Vivien Didelotfad09c72016-06-21 12:28:20 -040063 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040064 addr, reg, *val);
65
66 return 0;
67}
68
Vivien Didelotec561272016-09-02 14:45:33 -040069int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040070{
71 int err;
72
Vivien Didelotfad09c72016-06-21 12:28:20 -040073 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040074
Vivien Didelotfad09c72016-06-21 12:28:20 -040075 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040076 if (err)
77 return err;
78
Vivien Didelotfad09c72016-06-21 12:28:20 -040079 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040080 addr, reg, val);
81
82 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000083}
84
Vivien Didelot683f2242019-08-09 18:47:54 -040085int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87{
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106}
107
Vivien Didelot19fb7f62019-08-09 18:47:55 -0400108int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110{
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113}
114
Andrew Lunn10fa5bf2017-05-26 01:03:20 +0200115struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
Andrew Lunna3c53be52017-01-24 14:53:50 +0100116{
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125}
126
Andrew Lunndc30c352016-10-16 19:56:49 +0200127static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128{
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133}
134
135static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136{
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141}
142
Andrew Lunn294d7112018-02-22 22:58:32 +0100143static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200144{
Andrew Lunndc30c352016-10-16 19:56:49 +0200145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
John David Anglin7c0db242019-02-11 13:40:21 -0500149 u16 ctl1;
Andrew Lunndc30c352016-10-16 19:56:49 +0200150 int err;
151
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000152 mv88e6xxx_reg_lock(chip);
Vivien Didelot82466922017-06-15 12:13:59 -0400153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000154 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200155
156 if (err)
157 goto out;
158
John David Anglin7c0db242019-02-11 13:40:21 -0500159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
Andrew Lunndc30c352016-10-16 19:56:49 +0200167 }
John David Anglin7c0db242019-02-11 13:40:21 -0500168
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000169 mv88e6xxx_reg_lock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
174unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000175 mv88e6xxx_reg_unlock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
Andrew Lunndc30c352016-10-16 19:56:49 +0200181out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183}
184
Andrew Lunn294d7112018-02-22 22:58:32 +0100185static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186{
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190}
191
Andrew Lunndc30c352016-10-16 19:56:49 +0200192static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193{
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000196 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200197}
198
199static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200{
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
Vivien Didelotd77f4322017-06-15 12:14:03 -0400206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
Vivien Didelotd77f4322017-06-15 12:14:03 -0400213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200214 if (err)
215 goto out;
216
217out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000218 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200219}
220
Bhumika Goyal6eb15e22017-08-19 16:25:52 +0530221static const struct irq_chip mv88e6xxx_g1_irq_chip = {
Andrew Lunndc30c352016-10-16 19:56:49 +0200222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227};
228
229static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232{
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240}
241
242static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245};
246
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200247/* To be called with reg_lock held */
Andrew Lunn294d7112018-02-22 22:58:32 +0100248static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200249{
250 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100251 u16 mask;
252
Vivien Didelotd77f4322017-06-15 12:14:03 -0400253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3460a572016-11-20 20:14:16 +0100256
Andreas Färber5edef2f2016-11-27 23:26:28 +0100257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200259 irq_dispose_mapping(virq);
260 }
261
Andrew Lunna3db3d32016-11-20 20:14:14 +0100262 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200263}
264
Andrew Lunn294d7112018-02-22 22:58:32 +0100265static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266{
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
Andrew Lunn294d7112018-02-22 22:58:32 +0100271 free_irq(chip->irq, chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200272
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000273 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200274 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000275 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100276}
277
278static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200279{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100280 int err, irq, virq;
281 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
Vivien Didelotd77f4322017-06-15 12:14:03 -0400296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200297 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100298 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200299
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200301
Vivien Didelotd77f4322017-06-15 12:14:03 -0400302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200303 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100304 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200305
306 /* Reading the interrupt status clears (most of) them */
Vivien Didelot82466922017-06-15 12:13:59 -0400307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200308 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100309 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200310
Andrew Lunndc30c352016-10-16 19:56:49 +0200311 return 0;
312
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100313out_disable:
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100316
317out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200324
325 return err;
326}
327
Andrew Lunn294d7112018-02-22 22:58:32 +0100328static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329{
Andrew Lunnf6d97582019-02-23 17:43:56 +0100330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
Andrew Lunn294d7112018-02-22 22:58:32 +0100332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
Andrew Lunnf6d97582019-02-23 17:43:56 +0100338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
Andrew Lunn30953832020-01-06 17:13:48 +0100344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000347 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
Marek Behún03403762018-08-30 02:13:50 +0200350 IRQF_ONESHOT | IRQF_SHARED,
Andrew Lunn30953832020-01-06 17:13:48 +0100351 chip->irq_name, chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000352 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357}
358
359static void mv88e6xxx_irq_poll(struct kthread_work *work)
360{
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368}
369
370static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371{
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
Florian Fainelli3f8b8692019-02-21 20:09:27 -0800381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
Andrew Lunn294d7112018-02-22 22:58:32 +0100382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389}
390
391static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392{
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200395
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000396 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200397 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000398 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100399}
400
Russell King64d47d52020-03-14 10:15:38 +0000401static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403{
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421}
422
Russell Kinga5a68582020-03-14 10:15:43 +0000423static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
Vivien Didelotd78343d2016-11-04 03:23:36 +0100426{
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
Hubert Feurstein43c8e0a2019-07-30 12:11:42 +0200433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100434 if (err)
435 return err;
436
Russell Kingf365c6f2020-03-14 10:15:53 +0000437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
Andrew Lunn54186b92018-08-09 15:38:37 +0200447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
Russell King64d47d52020-03-14 10:15:38 +0000453 err = mv88e6xxx_port_config_interface(chip, port, mode);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100454restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
Vivien Didelot774439e52017-06-08 18:34:08 -0400456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100457
458 return err;
459}
460
Marek Vasutd700ec42018-09-12 00:15:24 +0200461static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462{
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466}
467
Russell King5d5b2312020-03-14 10:16:03 +0000468static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469{
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482}
483
Russell Kinga5a68582020-03-14 10:15:43 +0000484static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486{
487 struct mv88e6xxx_chip *chip = ds->priv;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100488 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
Russell Kinga5a68582020-03-14 10:15:43 +0000494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501}
502
503static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507{
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100509 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100513 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519}
520
521static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522{
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100526 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100533 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540}
541
542static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545{
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
Pavana Sharma193c5b22021-03-17 14:46:40 +0100547 int lane;
Russell Kinga5a68582020-03-14 10:15:43 +0000548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +0100551 if (lane >= 0)
Russell Kinga5a68582020-03-14 10:15:43 +0000552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557}
558
Russell King6c422e32018-08-09 15:38:39 +0200559static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562{
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570}
571
572static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575{
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583}
584
Marek Behúne3af71a2019-02-25 12:39:55 +0100585static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588{
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597}
598
Russell King6c422e32018-08-09 15:38:39 +0200599static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602{
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608}
609
610static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613{
Andrew Lunnec260162019-02-08 22:25:44 +0100614 if (port >= 9) {
Russell King6c422e32018-08-09 15:38:39 +0200615 phylink_set(mask, 2500baseX_Full);
Andrew Lunnec260162019-02-08 22:25:44 +0100616 phylink_set(mask, 2500baseT_Full);
617 }
Russell King6c422e32018-08-09 15:38:39 +0200618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624}
625
626static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629{
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636}
637
Pavana Sharmade776d02021-03-17 14:46:42 +0100638static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
639 unsigned long *mask,
640 struct phylink_link_state *state)
641{
642 if (port == 0 || port == 9 || port == 10) {
643 phylink_set(mask, 10000baseT_Full);
644 phylink_set(mask, 10000baseKR_Full);
645 phylink_set(mask, 10000baseCR_Full);
646 phylink_set(mask, 10000baseSR_Full);
647 phylink_set(mask, 10000baseLR_Full);
648 phylink_set(mask, 10000baseLRM_Full);
649 phylink_set(mask, 10000baseER_Full);
650 phylink_set(mask, 5000baseT_Full);
651 phylink_set(mask, 2500baseX_Full);
652 phylink_set(mask, 2500baseT_Full);
653 }
654
655 phylink_set(mask, 1000baseT_Full);
656 phylink_set(mask, 1000baseX_Full);
657
658 mv88e6065_phylink_validate(chip, port, mask, state);
659}
660
Russell Kingc9a23562018-05-10 13:17:35 -0700661static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
662 unsigned long *supported,
663 struct phylink_link_state *state)
664{
Russell King6c422e32018-08-09 15:38:39 +0200665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
666 struct mv88e6xxx_chip *chip = ds->priv;
667
668 /* Allow all the expected bits */
669 phylink_set(mask, Autoneg);
670 phylink_set(mask, Pause);
671 phylink_set_port_modes(mask);
672
673 if (chip->info->ops->phylink_validate)
674 chip->info->ops->phylink_validate(chip, port, mask, state);
675
676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
677 bitmap_and(state->advertising, state->advertising, mask,
678 __ETHTOOL_LINK_MODE_MASK_NBITS);
679
680 /* We can only operate at 2500BaseX or 1000BaseX. If requested
681 * to advertise both, only report advertising at 2500BaseX.
682 */
683 phylink_helper_basex_speed(state);
Russell Kingc9a23562018-05-10 13:17:35 -0700684}
685
Russell Kingc9a23562018-05-10 13:17:35 -0700686static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
687 unsigned int mode,
688 const struct phylink_link_state *state)
689{
690 struct mv88e6xxx_chip *chip = ds->priv;
Russell Kingfad58192020-07-19 12:00:35 +0100691 struct mv88e6xxx_port *p;
Russell King64d47d52020-03-14 10:15:38 +0000692 int err;
Russell Kingc9a23562018-05-10 13:17:35 -0700693
Russell Kingfad58192020-07-19 12:00:35 +0100694 p = &chip->ports[port];
695
Russell King64d47d52020-03-14 10:15:38 +0000696 /* FIXME: is this the correct test? If we're in fixed mode on an
697 * internal port, why should we process this any different from
698 * PHY mode? On the other hand, the port may be automedia between
699 * an internal PHY and the serdes...
700 */
Marek Vasutd700ec42018-09-12 00:15:24 +0200701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
Russell Kingc9a23562018-05-10 13:17:35 -0700702 return;
703
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000704 mv88e6xxx_reg_lock(chip);
Russell Kingfad58192020-07-19 12:00:35 +0100705 /* In inband mode, the link may come up at any time while the link
706 * is not forced down. Force the link down while we reconfigure the
707 * interface mode.
Russell King64d47d52020-03-14 10:15:38 +0000708 */
Russell Kingfad58192020-07-19 12:00:35 +0100709 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
710 chip->info->ops->port_set_link)
711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
712
Russell King64d47d52020-03-14 10:15:38 +0000713 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
Russell Kinga5a68582020-03-14 10:15:43 +0000714 if (err && err != -EOPNOTSUPP)
715 goto err_unlock;
716
717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
718 state->advertising);
719 /* FIXME: we should restart negotiation if something changed - which
720 * is something we get if we convert to using phylinks PCS operations.
721 */
722 if (err > 0)
723 err = 0;
724
Russell Kingfad58192020-07-19 12:00:35 +0100725 /* Undo the forced down state above after completing configuration
726 * irrespective of its state on entry, which allows the link to come up.
727 */
728 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
729 chip->info->ops->port_set_link)
730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
731
732 p->interface = state->interface;
733
Russell Kinga5a68582020-03-14 10:15:43 +0000734err_unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000735 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700736
737 if (err && err != -EOPNOTSUPP)
Russell King64d47d52020-03-14 10:15:38 +0000738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700739}
740
Russell Kingc9a23562018-05-10 13:17:35 -0700741static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
742 unsigned int mode,
743 phy_interface_t interface)
744{
Russell King30c4a5b2020-02-26 10:23:51 +0000745 struct mv88e6xxx_chip *chip = ds->priv;
746 const struct mv88e6xxx_ops *ops;
747 int err = 0;
748
749 ops = chip->info->ops;
750
Russell King5d5b2312020-03-14 10:16:03 +0000751 mv88e6xxx_reg_lock(chip);
Andrew Lunn34b5e6a2020-04-14 02:34:38 +0200752 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
Chris Packham4efe76622020-11-24 17:34:37 +1300753 mode == MLO_AN_FIXED) && ops->port_sync_link)
754 err = ops->port_sync_link(chip, port, mode, false);
Russell King5d5b2312020-03-14 10:16:03 +0000755 mv88e6xxx_reg_unlock(chip);
Russell King30c4a5b2020-02-26 10:23:51 +0000756
Russell King5d5b2312020-03-14 10:16:03 +0000757 if (err)
758 dev_err(chip->dev,
759 "p%d: failed to force MAC link down\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700760}
761
762static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
763 unsigned int mode, phy_interface_t interface,
Russell King5b502a72020-02-26 10:23:46 +0000764 struct phy_device *phydev,
765 int speed, int duplex,
766 bool tx_pause, bool rx_pause)
Russell Kingc9a23562018-05-10 13:17:35 -0700767{
Russell King30c4a5b2020-02-26 10:23:51 +0000768 struct mv88e6xxx_chip *chip = ds->priv;
769 const struct mv88e6xxx_ops *ops;
770 int err = 0;
771
772 ops = chip->info->ops;
773
Russell King5d5b2312020-03-14 10:16:03 +0000774 mv88e6xxx_reg_lock(chip);
Andrew Lunn34b5e6a2020-04-14 02:34:38 +0200775 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
Russell King30c4a5b2020-02-26 10:23:51 +0000776 /* FIXME: for an automedia port, should we force the link
777 * down here - what if the link comes up due to "other" media
778 * while we're bringing the port up, how is the exclusivity
Russell Kinga5a68582020-03-14 10:15:43 +0000779 * handled in the Marvell hardware? E.g. port 2 on 88E6390
Russell King30c4a5b2020-02-26 10:23:51 +0000780 * shared between internal PHY and Serdes.
781 */
Russell Kinga5a68582020-03-14 10:15:43 +0000782 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
783 duplex);
784 if (err)
785 goto error;
786
Russell Kingf365c6f2020-03-14 10:15:53 +0000787 if (ops->port_set_speed_duplex) {
788 err = ops->port_set_speed_duplex(chip, port,
789 speed, duplex);
Russell King30c4a5b2020-02-26 10:23:51 +0000790 if (err && err != -EOPNOTSUPP)
791 goto error;
792 }
793
Chris Packham4efe76622020-11-24 17:34:37 +1300794 if (ops->port_sync_link)
795 err = ops->port_sync_link(chip, port, mode, true);
Russell King30c4a5b2020-02-26 10:23:51 +0000796 }
Russell King5d5b2312020-03-14 10:16:03 +0000797error:
798 mv88e6xxx_reg_unlock(chip);
799
800 if (err && err != -EOPNOTSUPP)
801 dev_err(ds->dev,
802 "p%d: failed to configure MAC link up\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700803}
804
Andrew Lunna605a0f2016-11-21 23:26:58 +0100805static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000806{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100807 if (!chip->info->ops->stats_snapshot)
808 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000809
Andrew Lunna605a0f2016-11-21 23:26:58 +0100810 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000811}
812
Andrew Lunne413e7e2015-04-02 04:06:38 +0200813static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100814 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
815 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
816 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
817 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
818 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
819 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
820 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
821 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
822 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
823 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
824 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
825 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
826 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
827 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
828 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
829 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
830 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
831 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
832 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
833 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
834 { "single", 4, 0x14, STATS_TYPE_BANK0, },
835 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
836 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
837 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
838 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
839 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
840 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
841 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
842 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
843 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
844 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
845 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
846 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
847 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
848 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
849 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
850 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
851 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
852 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
853 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
854 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
855 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
856 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
857 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
858 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
859 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
860 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
861 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
862 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
863 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
864 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
865 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
866 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
867 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
868 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
869 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
870 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
871 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
872 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200873};
874
Vivien Didelotfad09c72016-06-21 12:28:20 -0400875static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100876 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100877 int port, u16 bank1_select,
878 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200879{
Andrew Lunn80c46272015-06-20 18:42:30 +0200880 u32 low;
881 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100882 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200883 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200884 u64 value;
885
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100886 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100887 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200888 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
889 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800890 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200891
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200892 low = reg;
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100893 if (s->size == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200894 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
895 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800896 return U64_MAX;
Rasmus Villemoes84b3fd12019-05-29 07:02:11 +0000897 low |= ((u32)reg) << 16;
Andrew Lunn80c46272015-06-20 18:42:30 +0200898 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100899 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100900 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100901 reg = bank1_select;
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -0500902 fallthrough;
Andrew Lunndfafe442016-11-21 23:27:02 +0100903 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100904 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100905 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100906 if (s->size == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100907 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Gustavo A. R. Silva9fc3e4d2017-05-11 22:11:29 -0500908 break;
909 default:
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800910 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200911 }
Andrew Lunn6e46e2d2019-02-28 18:14:03 +0100912 value = (((u64)high) << 32) | low;
Andrew Lunn80c46272015-06-20 18:42:30 +0200913 return value;
914}
915
Andrew Lunn436fe172018-03-01 02:02:29 +0100916static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
917 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100918{
919 struct mv88e6xxx_hw_stat *stat;
920 int i, j;
921
922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
923 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100924 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100925 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
926 ETH_GSTRING_LEN);
927 j++;
928 }
929 }
Andrew Lunn436fe172018-03-01 02:02:29 +0100930
931 return j;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100932}
933
Andrew Lunn436fe172018-03-01 02:02:29 +0100934static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
935 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100936{
Andrew Lunn436fe172018-03-01 02:02:29 +0100937 return mv88e6xxx_stats_get_strings(chip, data,
938 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
Andrew Lunndfafe442016-11-21 23:27:02 +0100939}
940
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000941static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
942 uint8_t *data)
943{
944 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
945}
946
Andrew Lunn436fe172018-03-01 02:02:29 +0100947static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
948 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100949{
Andrew Lunn436fe172018-03-01 02:02:29 +0100950 return mv88e6xxx_stats_get_strings(chip, data,
951 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
Andrew Lunndfafe442016-11-21 23:27:02 +0100952}
953
Andrew Lunn65f60e42018-03-28 23:50:28 +0200954static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
955 "atu_member_violation",
956 "atu_miss_violation",
957 "atu_full_violation",
958 "vtu_member_violation",
959 "vtu_miss_violation",
960};
961
962static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
963{
964 unsigned int i;
965
966 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
967 strlcpy(data + i * ETH_GSTRING_LEN,
968 mv88e6xxx_atu_vtu_stats_strings[i],
969 ETH_GSTRING_LEN);
970}
971
Andrew Lunndfafe442016-11-21 23:27:02 +0100972static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
Florian Fainelli89f09042018-04-25 12:12:50 -0700973 u32 stringset, uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100974{
Vivien Didelot04bed142016-08-31 18:06:13 -0400975 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +0100976 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100977
Florian Fainelli89f09042018-04-25 12:12:50 -0700978 if (stringset != ETH_SS_STATS)
979 return;
980
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000981 mv88e6xxx_reg_lock(chip);
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100982
Andrew Lunndfafe442016-11-21 23:27:02 +0100983 if (chip->info->ops->stats_get_strings)
Andrew Lunn436fe172018-03-01 02:02:29 +0100984 count = chip->info->ops->stats_get_strings(chip, data);
985
986 if (chip->info->ops->serdes_get_strings) {
987 data += count * ETH_GSTRING_LEN;
Andrew Lunn65f60e42018-03-28 23:50:28 +0200988 count = chip->info->ops->serdes_get_strings(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +0100989 }
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100990
Andrew Lunn65f60e42018-03-28 23:50:28 +0200991 data += count * ETH_GSTRING_LEN;
992 mv88e6xxx_atu_vtu_get_strings(data);
993
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000994 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +0100995}
996
997static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
998 int types)
999{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +01001000 struct mv88e6xxx_hw_stat *stat;
1001 int i, j;
1002
1003 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1004 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +01001005 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +01001006 j++;
1007 }
1008 return j;
1009}
1010
Andrew Lunndfafe442016-11-21 23:27:02 +01001011static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1012{
1013 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1014 STATS_TYPE_PORT);
1015}
1016
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001017static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1018{
1019 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1020}
1021
Andrew Lunndfafe442016-11-21 23:27:02 +01001022static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1023{
1024 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1025 STATS_TYPE_BANK1);
1026}
1027
Florian Fainelli89f09042018-04-25 12:12:50 -07001028static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
Andrew Lunndfafe442016-11-21 23:27:02 +01001029{
1030 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +01001031 int serdes_count = 0;
1032 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +01001033
Florian Fainelli89f09042018-04-25 12:12:50 -07001034 if (sset != ETH_SS_STATS)
1035 return 0;
1036
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001037 mv88e6xxx_reg_lock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001038 if (chip->info->ops->stats_get_sset_count)
Andrew Lunn436fe172018-03-01 02:02:29 +01001039 count = chip->info->ops->stats_get_sset_count(chip);
1040 if (count < 0)
1041 goto out;
1042
1043 if (chip->info->ops->serdes_get_sset_count)
1044 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1045 port);
Andrew Lunn65f60e42018-03-28 23:50:28 +02001046 if (serdes_count < 0) {
Andrew Lunn436fe172018-03-01 02:02:29 +01001047 count = serdes_count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001048 goto out;
1049 }
1050 count += serdes_count;
1051 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1052
Andrew Lunn436fe172018-03-01 02:02:29 +01001053out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001054 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001055
Andrew Lunn436fe172018-03-01 02:02:29 +01001056 return count;
Andrew Lunndfafe442016-11-21 23:27:02 +01001057}
1058
Andrew Lunn436fe172018-03-01 02:02:29 +01001059static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1060 uint64_t *data, int types,
1061 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +01001062{
1063 struct mv88e6xxx_hw_stat *stat;
1064 int i, j;
1065
1066 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1067 stat = &mv88e6xxx_hw_stats[i];
1068 if (stat->type & types) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001069 mv88e6xxx_reg_lock(chip);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001070 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1071 bank1_select,
1072 histogram);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001073 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001074
Andrew Lunn052f9472016-11-21 23:27:03 +01001075 j++;
1076 }
1077 }
Andrew Lunn436fe172018-03-01 02:02:29 +01001078 return j;
Andrew Lunn052f9472016-11-21 23:27:03 +01001079}
1080
Andrew Lunn436fe172018-03-01 02:02:29 +01001081static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1082 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001083{
1084 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001085 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001086 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +01001087}
1088
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001089static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1090 uint64_t *data)
1091{
1092 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1093 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1094}
1095
Andrew Lunn436fe172018-03-01 02:02:29 +01001096static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1097 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001098{
1099 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001100 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001101 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1102 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001103}
1104
Andrew Lunn436fe172018-03-01 02:02:29 +01001105static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1106 uint64_t *data)
Andrew Lunne0d8b612016-11-21 23:27:04 +01001107{
1108 return mv88e6xxx_stats_get_stats(chip, port, data,
1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1111 0);
Andrew Lunn052f9472016-11-21 23:27:03 +01001112}
1113
Andrew Lunn65f60e42018-03-28 23:50:28 +02001114static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1115 uint64_t *data)
1116{
1117 *data++ = chip->ports[port].atu_member_violation;
1118 *data++ = chip->ports[port].atu_miss_violation;
1119 *data++ = chip->ports[port].atu_full_violation;
1120 *data++ = chip->ports[port].vtu_member_violation;
1121 *data++ = chip->ports[port].vtu_miss_violation;
1122}
1123
Andrew Lunn052f9472016-11-21 23:27:03 +01001124static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1125 uint64_t *data)
1126{
Andrew Lunn436fe172018-03-01 02:02:29 +01001127 int count = 0;
1128
Andrew Lunn052f9472016-11-21 23:27:03 +01001129 if (chip->info->ops->stats_get_stats)
Andrew Lunn436fe172018-03-01 02:02:29 +01001130 count = chip->info->ops->stats_get_stats(chip, port, data);
1131
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001132 mv88e6xxx_reg_lock(chip);
Andrew Lunn436fe172018-03-01 02:02:29 +01001133 if (chip->info->ops->serdes_get_stats) {
1134 data += count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001135 count = chip->info->ops->serdes_get_stats(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001136 }
Andrew Lunn65f60e42018-03-28 23:50:28 +02001137 data += count;
1138 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001139 mv88e6xxx_reg_unlock(chip);
Andrew Lunn052f9472016-11-21 23:27:03 +01001140}
1141
Vivien Didelotf81ec902016-05-09 13:22:58 -04001142static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1143 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001144{
Vivien Didelot04bed142016-08-31 18:06:13 -04001145 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001146 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001147
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001148 mv88e6xxx_reg_lock(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001149
Andrew Lunna605a0f2016-11-21 23:26:58 +01001150 ret = mv88e6xxx_stats_snapshot(chip, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001151 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001152
1153 if (ret < 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001154 return;
Andrew Lunn052f9472016-11-21 23:27:03 +01001155
1156 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001157
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001158}
Ben Hutchings98e67302011-11-25 14:36:19 +00001159
Vivien Didelotf81ec902016-05-09 13:22:58 -04001160static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001161{
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001162 struct mv88e6xxx_chip *chip = ds->priv;
1163 int len;
1164
1165 len = 32 * sizeof(u16);
1166 if (chip->info->ops->serdes_get_regs_len)
1167 len += chip->info->ops->serdes_get_regs_len(chip, port);
1168
1169 return len;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001170}
1171
Vivien Didelotf81ec902016-05-09 13:22:58 -04001172static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1173 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001174{
Vivien Didelot04bed142016-08-31 18:06:13 -04001175 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001176 int err;
1177 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001178 u16 *p = _p;
1179 int i;
1180
Vivien Didelota5f39322018-12-17 16:05:21 -05001181 regs->version = chip->info->prod_num;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001182
1183 memset(p, 0xff, 32 * sizeof(u16));
1184
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001185 mv88e6xxx_reg_lock(chip);
Vivien Didelot23062512016-05-09 13:22:45 -04001186
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001187 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001188
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001189 err = mv88e6xxx_port_read(chip, port, i, &reg);
1190 if (!err)
1191 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001192 }
Vivien Didelot23062512016-05-09 13:22:45 -04001193
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001194 if (chip->info->ops->serdes_get_regs)
1195 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1196
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001197 mv88e6xxx_reg_unlock(chip);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001198}
1199
Vivien Didelot08f50062017-08-01 16:32:41 -04001200static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1201 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001202{
Vivien Didelot5480db62017-08-01 16:32:40 -04001203 /* Nothing to do on the port's MAC */
1204 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001205}
1206
Vivien Didelot08f50062017-08-01 16:32:41 -04001207static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1208 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001209{
Vivien Didelot5480db62017-08-01 16:32:40 -04001210 /* Nothing to do on the port's MAC */
1211 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001212}
1213
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001214/* Mask of the local ports allowed to receive frames from a given fabric port */
Vivien Didelote5887a22017-03-30 17:37:11 -04001215static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001216{
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001217 struct dsa_switch *ds = chip->ds;
1218 struct dsa_switch_tree *dst = ds->dst;
Vivien Didelote5887a22017-03-30 17:37:11 -04001219 struct net_device *br;
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001220 struct dsa_port *dp;
1221 bool found = false;
Vivien Didelote5887a22017-03-30 17:37:11 -04001222 u16 pvlan;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001223
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001224 list_for_each_entry(dp, &dst->ports, list) {
1225 if (dp->ds->index == dev && dp->index == port) {
1226 found = true;
1227 break;
1228 }
1229 }
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001230
Vivien Didelote5887a22017-03-30 17:37:11 -04001231 /* Prevent frames from unknown switch or port */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001232 if (!found)
Vivien Didelote5887a22017-03-30 17:37:11 -04001233 return 0;
1234
1235 /* Frames from DSA links and CPU ports can egress any local port */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001236 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
Vivien Didelote5887a22017-03-30 17:37:11 -04001237 return mv88e6xxx_port_mask(chip);
1238
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001239 br = dp->bridge_dev;
Vivien Didelote5887a22017-03-30 17:37:11 -04001240 pvlan = 0;
1241
1242 /* Frames from user ports can egress any local DSA links and CPU ports,
1243 * as well as any local member of their bridge group.
1244 */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001245 list_for_each_entry(dp, &dst->ports, list)
1246 if (dp->ds == ds &&
1247 (dp->type == DSA_PORT_TYPE_CPU ||
1248 dp->type == DSA_PORT_TYPE_DSA ||
1249 (br && dp->bridge_dev == br)))
1250 pvlan |= BIT(dp->index);
Vivien Didelote5887a22017-03-30 17:37:11 -04001251
1252 return pvlan;
1253}
1254
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001255static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
Vivien Didelote5887a22017-03-30 17:37:11 -04001256{
1257 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001258
1259 /* prevent frames from going back out of the port they came in on */
1260 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001261
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001262 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001263}
1264
Vivien Didelotf81ec902016-05-09 13:22:58 -04001265static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1266 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001267{
Vivien Didelot04bed142016-08-31 18:06:13 -04001268 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot553eb542016-05-13 20:38:23 -04001269 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001270
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001271 mv88e6xxx_reg_lock(chip);
Vivien Didelotf894c292017-06-08 18:34:10 -04001272 err = mv88e6xxx_port_set_state(chip, port, state);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001273 mv88e6xxx_reg_unlock(chip);
Vivien Didelot553eb542016-05-13 20:38:23 -04001274
1275 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001276 dev_err(ds->dev, "p%d: failed to update state\n", port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001277}
1278
Vivien Didelot93e18d62018-05-11 17:16:35 -04001279static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1280{
1281 int err;
1282
1283 if (chip->info->ops->ieee_pri_map) {
1284 err = chip->info->ops->ieee_pri_map(chip);
1285 if (err)
1286 return err;
1287 }
1288
1289 if (chip->info->ops->ip_pri_map) {
1290 err = chip->info->ops->ip_pri_map(chip);
1291 if (err)
1292 return err;
1293 }
1294
1295 return 0;
1296}
1297
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001298static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1299{
Vivien Didelotc5f51762019-10-30 22:09:13 -04001300 struct dsa_switch *ds = chip->ds;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001301 int target, port;
1302 int err;
1303
1304 if (!chip->info->global2_addr)
1305 return 0;
1306
1307 /* Initialize the routing port to the 32 possible target devices */
1308 for (target = 0; target < 32; target++) {
Vivien Didelotc5f51762019-10-30 22:09:13 -04001309 port = dsa_routing_port(ds, target);
1310 if (port == ds->num_ports)
1311 port = 0x1f;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001312
1313 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1314 if (err)
1315 return err;
1316 }
1317
Vivien Didelot02317e62018-05-09 11:38:49 -04001318 if (chip->info->ops->set_cascade_port) {
1319 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1320 err = chip->info->ops->set_cascade_port(chip, port);
1321 if (err)
1322 return err;
1323 }
1324
Vivien Didelot23c98912018-05-09 11:38:50 -04001325 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1326 if (err)
1327 return err;
1328
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001329 return 0;
1330}
1331
Vivien Didelotb28f8722018-04-26 21:56:44 -04001332static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1333{
1334 /* Clear all trunk masks and mapping */
1335 if (chip->info->global2_addr)
1336 return mv88e6xxx_g2_trunk_clear(chip);
1337
1338 return 0;
1339}
1340
Vivien Didelot9e5baf92018-05-09 11:38:51 -04001341static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1342{
1343 if (chip->info->ops->rmu_disable)
1344 return chip->info->ops->rmu_disable(chip);
1345
1346 return 0;
1347}
1348
Vivien Didelot9e907d72017-07-17 13:03:43 -04001349static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1350{
1351 if (chip->info->ops->pot_clear)
1352 return chip->info->ops->pot_clear(chip);
1353
1354 return 0;
1355}
1356
Vivien Didelot51c901a2017-07-17 13:03:41 -04001357static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1358{
1359 if (chip->info->ops->mgmt_rsvd2cpu)
1360 return chip->info->ops->mgmt_rsvd2cpu(chip);
1361
1362 return 0;
1363}
1364
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001365static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1366{
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001367 int err;
1368
Vivien Didelotdaefc942017-03-11 16:12:54 -05001369 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1370 if (err)
1371 return err;
1372
Rasmus Villemoes49506a92020-12-10 12:06:44 +01001373 /* The chips that have a "learn2all" bit in Global1, ATU
1374 * Control are precisely those whose port registers have a
1375 * Message Port bit in Port Control 1 and hence implement
1376 * ->port_setup_message_port.
1377 */
1378 if (chip->info->ops->port_setup_message_port) {
1379 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1380 if (err)
1381 return err;
1382 }
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001383
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001384 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1385}
1386
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04001387static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1388{
1389 int port;
1390 int err;
1391
1392 if (!chip->info->ops->irl_init_all)
1393 return 0;
1394
1395 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1396 /* Disable ingress rate limiting by resetting all per port
1397 * ingress rate limit resources to their initial state.
1398 */
1399 err = chip->info->ops->irl_init_all(chip, port);
1400 if (err)
1401 return err;
1402 }
1403
1404 return 0;
1405}
1406
Vivien Didelot04a69a12017-10-13 14:18:05 -04001407static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1408{
1409 if (chip->info->ops->set_switch_mac) {
1410 u8 addr[ETH_ALEN];
1411
1412 eth_random_addr(addr);
1413
1414 return chip->info->ops->set_switch_mac(chip, addr);
1415 }
1416
1417 return 0;
1418}
1419
Vivien Didelot17a15942017-03-30 17:37:09 -04001420static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1421{
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001422 struct dsa_switch_tree *dst = chip->ds->dst;
1423 struct dsa_switch *ds;
1424 struct dsa_port *dp;
Vivien Didelot17a15942017-03-30 17:37:09 -04001425 u16 pvlan = 0;
1426
1427 if (!mv88e6xxx_has_pvt(chip))
Vivien Didelotd14939b2019-10-21 16:51:25 -04001428 return 0;
Vivien Didelot17a15942017-03-30 17:37:09 -04001429
1430 /* Skip the local source device, which uses in-chip port VLAN */
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001431 if (dev != chip->ds->index) {
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001432 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
Vivien Didelot17a15942017-03-30 17:37:09 -04001433
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001434 ds = dsa_switch_find(dst->index, dev);
1435 dp = ds ? dsa_to_port(ds, port) : NULL;
1436 if (dp && dp->lag_dev) {
1437 /* As the PVT is used to limit flooding of
1438 * FORWARD frames, which use the LAG ID as the
1439 * source port, we must translate dev/port to
1440 * the special "LAG device" in the PVT, using
1441 * the LAG ID as the port number.
1442 */
Tobias Waldekranz78e70db2021-04-21 14:04:52 +02001443 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01001444 port = dsa_lag_id(dst, dp->lag_dev);
1445 }
1446 }
1447
Vivien Didelot17a15942017-03-30 17:37:09 -04001448 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1449}
1450
Vivien Didelot81228992017-03-30 17:37:08 -04001451static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1452{
Vivien Didelot17a15942017-03-30 17:37:09 -04001453 int dev, port;
1454 int err;
1455
Vivien Didelot81228992017-03-30 17:37:08 -04001456 if (!mv88e6xxx_has_pvt(chip))
1457 return 0;
1458
1459 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1460 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1461 */
Vivien Didelot17a15942017-03-30 17:37:09 -04001462 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1463 if (err)
1464 return err;
1465
1466 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1467 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1468 err = mv88e6xxx_pvt_map(chip, dev, port);
1469 if (err)
1470 return err;
1471 }
1472 }
1473
1474 return 0;
Vivien Didelot81228992017-03-30 17:37:08 -04001475}
1476
Vivien Didelot749efcb2016-09-22 16:49:24 -04001477static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1478{
1479 struct mv88e6xxx_chip *chip = ds->priv;
1480 int err;
1481
Tobias Waldekranzffcec3f2021-03-18 20:25:34 +01001482 if (dsa_to_port(ds, port)->lag_dev)
1483 /* Hardware is incapable of fast-aging a LAG through a
1484 * regular ATU move operation. Until we have something
1485 * more fancy in place this is a no-op.
1486 */
1487 return;
1488
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001489 mv88e6xxx_reg_lock(chip);
Vivien Didelote606ca32017-03-11 16:12:55 -05001490 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001491 mv88e6xxx_reg_unlock(chip);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001492
1493 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001494 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001495}
1496
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001497static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1498{
Tobias Waldekranze545f862020-11-10 19:57:20 +01001499 if (!mv88e6xxx_max_vid(chip))
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001500 return 0;
1501
1502 return mv88e6xxx_g1_vtu_flush(chip);
1503}
1504
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001505static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1506 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelotf1394b782017-05-01 14:05:22 -04001507{
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001508 int err;
1509
Vivien Didelotf1394b782017-05-01 14:05:22 -04001510 if (!chip->info->ops->vtu_getnext)
1511 return -EOPNOTSUPP;
1512
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001513 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1514 entry->valid = false;
1515
1516 err = chip->info->ops->vtu_getnext(chip, entry);
1517
1518 if (entry->vid != vid)
1519 entry->valid = false;
1520
1521 return err;
Vivien Didelotf1394b782017-05-01 14:05:22 -04001522}
1523
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001524static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1525 int (*cb)(struct mv88e6xxx_chip *chip,
1526 const struct mv88e6xxx_vtu_entry *entry,
1527 void *priv),
1528 void *priv)
1529{
1530 struct mv88e6xxx_vtu_entry entry = {
1531 .vid = mv88e6xxx_max_vid(chip),
1532 .valid = false,
1533 };
1534 int err;
1535
1536 if (!chip->info->ops->vtu_getnext)
1537 return -EOPNOTSUPP;
1538
1539 do {
1540 err = chip->info->ops->vtu_getnext(chip, &entry);
1541 if (err)
1542 return err;
1543
1544 if (!entry.valid)
1545 break;
1546
1547 err = cb(chip, &entry, priv);
1548 if (err)
1549 return err;
1550 } while (entry.vid < mv88e6xxx_max_vid(chip));
1551
1552 return 0;
1553}
1554
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04001555static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1556 struct mv88e6xxx_vtu_entry *entry)
1557{
1558 if (!chip->info->ops->vtu_loadpurge)
1559 return -EOPNOTSUPP;
1560
1561 return chip->info->ops->vtu_loadpurge(chip, entry);
1562}
1563
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001564static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1565 const struct mv88e6xxx_vtu_entry *entry,
1566 void *_fid_bitmap)
1567{
1568 unsigned long *fid_bitmap = _fid_bitmap;
1569
1570 set_bit(entry->fid, fid_bitmap);
1571 return 0;
1572}
1573
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001574int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001575{
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001576 int i, err;
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001577 u16 fid;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001578
1579 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1580
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001581 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001582 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001583 err = mv88e6xxx_port_get_fid(chip, i, &fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001584 if (err)
1585 return err;
1586
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001587 set_bit(fid, fid_bitmap);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001588 }
1589
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001590 /* Set every FID bit used by the VLAN entries */
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01001591 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001592}
1593
1594static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1595{
1596 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1597 int err;
1598
1599 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1600 if (err)
1601 return err;
1602
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001603 /* The reset value 0x000 is used to indicate that multiple address
1604 * databases are not needed. Return the next positive available.
1605 */
1606 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001607 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001608 return -ENOSPC;
1609
1610 /* Clear the database */
Vivien Didelotdaefc942017-03-11 16:12:54 -05001611 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001612}
1613
Vivien Didelotda9c3592016-02-12 12:09:40 -05001614static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001615 u16 vid)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001616{
Vivien Didelot04bed142016-08-31 18:06:13 -04001617 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot425d2d32019-08-01 14:36:34 -04001618 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001619 int i, err;
1620
Andrew Lunndb06ae412017-09-25 23:32:20 +02001621 /* DSA and CPU ports have to be members of multiple vlans */
1622 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1623 return 0;
1624
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001625 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001626 if (err)
1627 return err;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001628
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001629 if (!vlan.valid)
1630 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001631
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001632 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1633 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1634 continue;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001635
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001636 if (!dsa_to_port(ds, i)->slave)
1637 continue;
Andrew Lunn66e28092016-12-11 21:07:19 +01001638
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001639 if (vlan.member[i] ==
1640 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1641 continue;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001642
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001643 if (dsa_to_port(ds, i)->bridge_dev ==
1644 dsa_to_port(ds, port)->bridge_dev)
1645 break; /* same bridge, check next VLAN */
Vivien Didelotda9c3592016-02-12 12:09:40 -05001646
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001647 if (!dsa_to_port(ds, i)->bridge_dev)
1648 continue;
Andrew Lunn66e28092016-12-11 21:07:19 +01001649
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001650 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1651 port, vlan.vid, i,
1652 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1653 return -EOPNOTSUPP;
1654 }
Vivien Didelotda9c3592016-02-12 12:09:40 -05001655
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001656 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001657}
1658
Vivien Didelotf81ec902016-05-09 13:22:58 -04001659static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
Vladimir Oltean89153ed2021-02-13 22:43:19 +02001660 bool vlan_filtering,
1661 struct netlink_ext_ack *extack)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001662{
Vivien Didelot04bed142016-08-31 18:06:13 -04001663 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot81c6edb2017-06-12 12:37:41 -04001664 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1665 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001666 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001667
Vladimir Olteanbae33f22021-01-09 02:01:50 +02001668 if (!mv88e6xxx_max_vid(chip))
1669 return -EOPNOTSUPP;
Vivien Didelot54d77b52016-05-09 13:22:47 -04001670
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001671 mv88e6xxx_reg_lock(chip);
Vivien Didelot385a0992016-11-04 03:23:31 +01001672 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001673 mv88e6xxx_reg_unlock(chip);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001674
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001675 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001676}
1677
Vivien Didelot57d32312016-06-20 13:13:58 -04001678static int
1679mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001680 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001681{
Vivien Didelot04bed142016-08-31 18:06:13 -04001682 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001683 int err;
1684
Tobias Waldekranze545f862020-11-10 19:57:20 +01001685 if (!mv88e6xxx_max_vid(chip))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001686 return -EOPNOTSUPP;
1687
Vivien Didelotda9c3592016-02-12 12:09:40 -05001688 /* If the requested port doesn't belong to the same bridge as the VLAN
1689 * members, do not support it (yet) and fallback to software VLAN.
1690 */
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001691 mv88e6xxx_reg_lock(chip);
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02001692 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001693 mv88e6xxx_reg_unlock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001694
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001695 return err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001696}
1697
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001698static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1699 const unsigned char *addr, u16 vid,
1700 u8 state)
1701{
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001702 struct mv88e6xxx_atu_entry entry;
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001703 struct mv88e6xxx_vtu_entry vlan;
1704 u16 fid;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001705 int err;
1706
1707 /* Null VLAN ID corresponds to the port private database */
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001708 if (vid == 0) {
1709 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1710 if (err)
1711 return err;
1712 } else {
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001713 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001714 if (err)
1715 return err;
1716
1717 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
Tobias Waldekranz34065c52021-03-18 20:25:36 +01001718 if (!vlan.valid)
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001719 return -EOPNOTSUPP;
1720
1721 fid = vlan.fid;
1722 }
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001723
Vivien Didelotd8291a92019-09-07 16:00:47 -04001724 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001725 ether_addr_copy(entry.mac, addr);
1726 eth_addr_dec(entry.mac);
1727
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001728 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001729 if (err)
1730 return err;
1731
1732 /* Initialize a fresh ATU entry if it isn't found */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001733 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001734 memset(&entry, 0, sizeof(entry));
1735 ether_addr_copy(entry.mac, addr);
1736 }
1737
1738 /* Purge the ATU entry only if no port is using it anymore */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001739 if (!state) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001740 entry.portvec &= ~BIT(port);
1741 if (!entry.portvec)
Vivien Didelotd8291a92019-09-07 16:00:47 -04001742 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001743 } else {
DENG Qingfangf72f2fb2021-01-30 21:43:34 +08001744 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1745 entry.portvec = BIT(port);
1746 else
1747 entry.portvec |= BIT(port);
1748
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001749 entry.state = state;
1750 }
1751
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001752 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001753}
1754
Vivien Didelotda7dc872019-09-07 16:00:49 -04001755static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1756 const struct mv88e6xxx_policy *policy)
1757{
1758 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1759 enum mv88e6xxx_policy_action action = policy->action;
1760 const u8 *addr = policy->addr;
1761 u16 vid = policy->vid;
1762 u8 state;
1763 int err;
1764 int id;
1765
1766 if (!chip->info->ops->port_set_policy)
1767 return -EOPNOTSUPP;
1768
1769 switch (mapping) {
1770 case MV88E6XXX_POLICY_MAPPING_DA:
1771 case MV88E6XXX_POLICY_MAPPING_SA:
1772 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1773 state = 0; /* Dissociate the port and address */
1774 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1775 is_multicast_ether_addr(addr))
1776 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1777 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1778 is_unicast_ether_addr(addr))
1779 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1780 else
1781 return -EOPNOTSUPP;
1782
1783 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1784 state);
1785 if (err)
1786 return err;
1787 break;
1788 default:
1789 return -EOPNOTSUPP;
1790 }
1791
1792 /* Skip the port's policy clearing if the mapping is still in use */
1793 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1794 idr_for_each_entry(&chip->policies, policy, id)
1795 if (policy->port == port &&
1796 policy->mapping == mapping &&
1797 policy->action != action)
1798 return 0;
1799
1800 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1801}
1802
1803static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1804 struct ethtool_rx_flow_spec *fs)
1805{
1806 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1807 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1808 enum mv88e6xxx_policy_mapping mapping;
1809 enum mv88e6xxx_policy_action action;
1810 struct mv88e6xxx_policy *policy;
1811 u16 vid = 0;
1812 u8 *addr;
1813 int err;
1814 int id;
1815
1816 if (fs->location != RX_CLS_LOC_ANY)
1817 return -EINVAL;
1818
1819 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1820 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1821 else
1822 return -EOPNOTSUPP;
1823
1824 switch (fs->flow_type & ~FLOW_EXT) {
1825 case ETHER_FLOW:
1826 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1827 is_zero_ether_addr(mac_mask->h_source)) {
1828 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1829 addr = mac_entry->h_dest;
1830 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1831 !is_zero_ether_addr(mac_mask->h_source)) {
1832 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1833 addr = mac_entry->h_source;
1834 } else {
1835 /* Cannot support DA and SA mapping in the same rule */
1836 return -EOPNOTSUPP;
1837 }
1838 break;
1839 default:
1840 return -EOPNOTSUPP;
1841 }
1842
1843 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
Andrew Lunn04844282020-07-05 21:38:08 +02001844 if (fs->m_ext.vlan_tci != htons(0xffff))
Vivien Didelotda7dc872019-09-07 16:00:49 -04001845 return -EOPNOTSUPP;
1846 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1847 }
1848
1849 idr_for_each_entry(&chip->policies, policy, id) {
1850 if (policy->port == port && policy->mapping == mapping &&
1851 policy->action == action && policy->vid == vid &&
1852 ether_addr_equal(policy->addr, addr))
1853 return -EEXIST;
1854 }
1855
1856 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1857 if (!policy)
1858 return -ENOMEM;
1859
1860 fs->location = 0;
1861 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1862 GFP_KERNEL);
1863 if (err) {
1864 devm_kfree(chip->dev, policy);
1865 return err;
1866 }
1867
1868 memcpy(&policy->fs, fs, sizeof(*fs));
1869 ether_addr_copy(policy->addr, addr);
1870 policy->mapping = mapping;
1871 policy->action = action;
1872 policy->port = port;
1873 policy->vid = vid;
1874
1875 err = mv88e6xxx_policy_apply(chip, port, policy);
1876 if (err) {
1877 idr_remove(&chip->policies, fs->location);
1878 devm_kfree(chip->dev, policy);
1879 return err;
1880 }
1881
1882 return 0;
1883}
1884
1885static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1886 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1887{
1888 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1889 struct mv88e6xxx_chip *chip = ds->priv;
1890 struct mv88e6xxx_policy *policy;
1891 int err;
1892 int id;
1893
1894 mv88e6xxx_reg_lock(chip);
1895
1896 switch (rxnfc->cmd) {
1897 case ETHTOOL_GRXCLSRLCNT:
1898 rxnfc->data = 0;
1899 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1900 rxnfc->rule_cnt = 0;
1901 idr_for_each_entry(&chip->policies, policy, id)
1902 if (policy->port == port)
1903 rxnfc->rule_cnt++;
1904 err = 0;
1905 break;
1906 case ETHTOOL_GRXCLSRULE:
1907 err = -ENOENT;
1908 policy = idr_find(&chip->policies, fs->location);
1909 if (policy) {
1910 memcpy(fs, &policy->fs, sizeof(*fs));
1911 err = 0;
1912 }
1913 break;
1914 case ETHTOOL_GRXCLSRLALL:
1915 rxnfc->data = 0;
1916 rxnfc->rule_cnt = 0;
1917 idr_for_each_entry(&chip->policies, policy, id)
1918 if (policy->port == port)
1919 rule_locs[rxnfc->rule_cnt++] = id;
1920 err = 0;
1921 break;
1922 default:
1923 err = -EOPNOTSUPP;
1924 break;
1925 }
1926
1927 mv88e6xxx_reg_unlock(chip);
1928
1929 return err;
1930}
1931
1932static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1933 struct ethtool_rxnfc *rxnfc)
1934{
1935 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1936 struct mv88e6xxx_chip *chip = ds->priv;
1937 struct mv88e6xxx_policy *policy;
1938 int err;
1939
1940 mv88e6xxx_reg_lock(chip);
1941
1942 switch (rxnfc->cmd) {
1943 case ETHTOOL_SRXCLSRLINS:
1944 err = mv88e6xxx_policy_insert(chip, port, fs);
1945 break;
1946 case ETHTOOL_SRXCLSRLDEL:
1947 err = -ENOENT;
1948 policy = idr_remove(&chip->policies, fs->location);
1949 if (policy) {
1950 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1951 err = mv88e6xxx_policy_apply(chip, port, policy);
1952 devm_kfree(chip->dev, policy);
1953 }
1954 break;
1955 default:
1956 err = -EOPNOTSUPP;
1957 break;
1958 }
1959
1960 mv88e6xxx_reg_unlock(chip);
1961
1962 return err;
1963}
1964
Andrew Lunn87fa8862017-11-09 22:29:56 +01001965static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1966 u16 vid)
1967{
Andrew Lunn87fa8862017-11-09 22:29:56 +01001968 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
Tobias Waldekranz0806dd462021-03-18 20:25:37 +01001969 u8 broadcast[ETH_ALEN];
1970
1971 eth_broadcast_addr(broadcast);
Andrew Lunn87fa8862017-11-09 22:29:56 +01001972
1973 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1974}
1975
1976static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1977{
1978 int port;
1979 int err;
1980
1981 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01001982 struct dsa_port *dp = dsa_to_port(chip->ds, port);
1983 struct net_device *brport;
1984
1985 if (dsa_is_unused_port(chip->ds, port))
1986 continue;
1987
1988 brport = dsa_port_to_bridge_port(dp);
1989 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
1990 /* Skip bridged user ports where broadcast
1991 * flooding is disabled.
1992 */
1993 continue;
1994
Andrew Lunn87fa8862017-11-09 22:29:56 +01001995 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1996 if (err)
1997 return err;
1998 }
1999
2000 return 0;
2001}
2002
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01002003struct mv88e6xxx_port_broadcast_sync_ctx {
2004 int port;
2005 bool flood;
2006};
2007
2008static int
2009mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2010 const struct mv88e6xxx_vtu_entry *vlan,
2011 void *_ctx)
2012{
2013 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2014 u8 broadcast[ETH_ALEN];
2015 u8 state;
2016
2017 if (ctx->flood)
2018 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2019 else
2020 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2021
2022 eth_broadcast_addr(broadcast);
2023
2024 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2025 vlan->vid, state);
2026}
2027
2028static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2029 bool flood)
2030{
2031 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2032 .port = port,
2033 .flood = flood,
2034 };
2035 struct mv88e6xxx_vtu_entry vid0 = {
2036 .vid = 0,
2037 };
2038 int err;
2039
2040 /* Update the port's private database... */
2041 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2042 if (err)
2043 return err;
2044
2045 /* ...and the database for all VLANs. */
2046 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2047 &ctx);
2048}
2049
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002050static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
Russell King933b4422020-02-26 17:14:26 +00002051 u16 vid, u8 member, bool warn)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002052{
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002053 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002054 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002055 int i, err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002056
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002057 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002058 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002059 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002060
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002061 if (!vlan.valid) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002062 memset(&vlan, 0, sizeof(vlan));
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002063
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002064 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2065 if (err)
2066 return err;
Andrew Lunn87fa8862017-11-09 22:29:56 +01002067
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002068 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2069 if (i == port)
2070 vlan.member[i] = member;
2071 else
2072 vlan.member[i] = non_member;
2073
2074 vlan.vid = vid;
2075 vlan.valid = true;
2076
2077 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2078 if (err)
2079 return err;
2080
2081 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2082 if (err)
2083 return err;
2084 } else if (vlan.member[port] != member) {
2085 vlan.member[port] = member;
2086
2087 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2088 if (err)
2089 return err;
Russell King933b4422020-02-26 17:14:26 +00002090 } else if (warn) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04002091 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2092 port, vid);
2093 }
2094
2095 return 0;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002096}
2097
Vladimir Oltean1958d582021-01-09 02:01:53 +02002098static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
Vladimir Oltean31046a52021-02-13 22:43:18 +02002099 const struct switchdev_obj_port_vlan *vlan,
2100 struct netlink_ext_ack *extack)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002101{
Vivien Didelot04bed142016-08-31 18:06:13 -04002102 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002103 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2104 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
Russell King933b4422020-02-26 17:14:26 +00002105 bool warn;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002106 u8 member;
Vladimir Oltean1958d582021-01-09 02:01:53 +02002107 int err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002108
Eldar Gasanovb8b79c42021-06-21 11:54:38 +03002109 if (!vlan->vid)
2110 return 0;
2111
Vladimir Oltean1958d582021-01-09 02:01:53 +02002112 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2113 if (err)
2114 return err;
Vivien Didelot54d77b52016-05-09 13:22:47 -04002115
Vivien Didelotc91498e2017-06-07 18:12:13 -04002116 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002117 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002118 else if (untagged)
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002119 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002120 else
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002121 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04002122
Russell King933b4422020-02-26 17:14:26 +00002123 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2124 * and then the CPU port. Do not warn for duplicates for the CPU port.
2125 */
2126 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2127
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002128 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002129
Vladimir Oltean1958d582021-01-09 02:01:53 +02002130 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2131 if (err) {
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002132 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2133 vlan->vid, untagged ? 'u' : 't');
Vladimir Oltean1958d582021-01-09 02:01:53 +02002134 goto out;
2135 }
Vivien Didelot76e398a2015-11-01 12:33:55 -05002136
Vladimir Oltean1958d582021-01-09 02:01:53 +02002137 if (pvid) {
2138 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid);
2139 if (err) {
2140 dev_err(ds->dev, "p%d: failed to set PVID %d\n",
2141 port, vlan->vid);
2142 goto out;
2143 }
2144 }
2145out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002146 mv88e6xxx_reg_unlock(chip);
Vladimir Oltean1958d582021-01-09 02:01:53 +02002147
2148 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002149}
2150
Vivien Didelot521098922019-08-01 14:36:36 -04002151static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2152 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002153{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002154 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002155 int i, err;
2156
Vivien Didelot521098922019-08-01 14:36:36 -04002157 if (!vid)
2158 return -EOPNOTSUPP;
2159
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002160 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002161 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002162 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002163
Vivien Didelot521098922019-08-01 14:36:36 -04002164 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2165 * tell switchdev that this VLAN is likely handled in software.
2166 */
Tobias Waldekranz34065c52021-03-18 20:25:36 +01002167 if (!vlan.valid ||
Vivien Didelot521098922019-08-01 14:36:36 -04002168 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05002169 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002170
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002171 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002172
2173 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002174 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002175 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002176 if (vlan.member[i] !=
2177 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002178 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002179 break;
2180 }
2181 }
2182
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002183 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002184 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002185 return err;
2186
Vivien Didelote606ca32017-03-11 16:12:55 -05002187 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002188}
2189
Vivien Didelotf81ec902016-05-09 13:22:58 -04002190static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2191 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002192{
Vivien Didelot04bed142016-08-31 18:06:13 -04002193 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002194 int err = 0;
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002195 u16 pvid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002196
Tobias Waldekranze545f862020-11-10 19:57:20 +01002197 if (!mv88e6xxx_max_vid(chip))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002198 return -EOPNOTSUPP;
2199
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002200 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002201
Vivien Didelot77064f32016-11-04 03:23:30 +01002202 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002203 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002204 goto unlock;
2205
Vladimir Olteanb7a9e0d2021-01-09 02:01:46 +02002206 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2207 if (err)
2208 goto unlock;
2209
2210 if (vlan->vid == pvid) {
2211 err = mv88e6xxx_port_set_pvid(chip, port, 0);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002212 if (err)
2213 goto unlock;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002214 }
2215
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002216unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002217 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002218
2219 return err;
2220}
2221
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002222static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2223 const unsigned char *addr, u16 vid)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002224{
Vivien Didelot04bed142016-08-31 18:06:13 -04002225 struct mv88e6xxx_chip *chip = ds->priv;
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002226 int err;
Vivien Didelot6630e232015-08-06 01:44:07 -04002227
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002228 mv88e6xxx_reg_lock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002229 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2230 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002231 mv88e6xxx_reg_unlock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002232
2233 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002234}
2235
Vivien Didelotf81ec902016-05-09 13:22:58 -04002236static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
Arkadi Sharshevsky6c2c1dc2017-08-06 16:15:39 +03002237 const unsigned char *addr, u16 vid)
David S. Millercdf09692015-08-11 12:00:37 -07002238{
Vivien Didelot04bed142016-08-31 18:06:13 -04002239 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002240 int err;
David S. Millercdf09692015-08-11 12:00:37 -07002241
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002242 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04002243 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002244 mv88e6xxx_reg_unlock(chip);
David S. Millercdf09692015-08-11 12:00:37 -07002245
Vivien Didelot83dabd12016-08-31 11:50:04 -04002246 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002247}
2248
Vivien Didelot83dabd12016-08-31 11:50:04 -04002249static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2250 u16 fid, u16 vid, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002251 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002252{
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002253 struct mv88e6xxx_atu_entry addr;
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002254 bool is_static;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002255 int err;
2256
Vivien Didelotd8291a92019-09-07 16:00:47 -04002257 addr.state = 0;
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002258 eth_broadcast_addr(addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002259
2260 do {
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002261 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002262 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002263 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002264
Vivien Didelotd8291a92019-09-07 16:00:47 -04002265 if (!addr.state)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002266 break;
2267
Vivien Didelot01bd96c2017-03-11 16:12:57 -05002268 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002269 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002270
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002271 if (!is_unicast_ether_addr(addr.mac))
2272 continue;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002273
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002274 is_static = (addr.state ==
2275 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2276 err = cb(addr.mac, vid, is_static, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002277 if (err)
2278 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002279 } while (!is_broadcast_ether_addr(addr.mac));
2280
2281 return err;
2282}
2283
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002284struct mv88e6xxx_port_db_dump_vlan_ctx {
2285 int port;
2286 dsa_fdb_dump_cb_t *cb;
2287 void *data;
2288};
2289
2290static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2291 const struct mv88e6xxx_vtu_entry *entry,
2292 void *_data)
2293{
2294 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2295
2296 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2297 ctx->port, ctx->cb, ctx->data);
2298}
2299
Vivien Didelot83dabd12016-08-31 11:50:04 -04002300static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002301 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002302{
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002303 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2304 .port = port,
2305 .cb = cb,
2306 .data = data,
2307 };
Vivien Didelot83dabd12016-08-31 11:50:04 -04002308 u16 fid;
2309 int err;
2310
2311 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002312 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002313 if (err)
2314 return err;
2315
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002316 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002317 if (err)
2318 return err;
2319
Tobias Waldekranzd89ef4b2021-03-18 20:25:35 +01002320 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002321}
2322
Vivien Didelotf81ec902016-05-09 13:22:58 -04002323static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002324 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelotf33475b2015-10-22 09:34:41 -04002325{
Vivien Didelot04bed142016-08-31 18:06:13 -04002326 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotfcf15362019-06-12 12:42:47 -04002327 int err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002328
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002329 mv88e6xxx_reg_lock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002330 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002331 mv88e6xxx_reg_unlock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002332
2333 return err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002334}
2335
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002336static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2337 struct net_device *br)
2338{
Vivien Didelotef2025e2019-10-21 16:51:27 -04002339 struct dsa_switch *ds = chip->ds;
2340 struct dsa_switch_tree *dst = ds->dst;
2341 struct dsa_port *dp;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002342 int err;
2343
Vivien Didelotef2025e2019-10-21 16:51:27 -04002344 list_for_each_entry(dp, &dst->ports, list) {
2345 if (dp->bridge_dev == br) {
2346 if (dp->ds == ds) {
2347 /* This is a local bridge group member,
2348 * remap its Port VLAN Map.
2349 */
2350 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2351 if (err)
2352 return err;
2353 } else {
2354 /* This is an external bridge group member,
2355 * remap its cross-chip Port VLAN Table entry.
2356 */
2357 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2358 dp->index);
Vivien Didelote96a6e02017-03-30 17:37:13 -04002359 if (err)
2360 return err;
2361 }
2362 }
2363 }
2364
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002365 return 0;
2366}
2367
Vivien Didelotf81ec902016-05-09 13:22:58 -04002368static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vivien Didelotfae8a252017-01-27 15:29:42 -05002369 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002370{
Vivien Didelot04bed142016-08-31 18:06:13 -04002371 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002372 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002373
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002374 mv88e6xxx_reg_lock(chip);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002375 err = mv88e6xxx_bridge_map(chip, br);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002376 mv88e6xxx_reg_unlock(chip);
Vivien Didelota6692752016-02-12 12:09:39 -05002377
Vivien Didelot466dfa02016-02-26 13:16:05 -05002378 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002379}
2380
Vivien Didelotf123f2f2017-01-27 15:29:41 -05002381static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2382 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002383{
Vivien Didelot04bed142016-08-31 18:06:13 -04002384 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002385
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002386 mv88e6xxx_reg_lock(chip);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002387 if (mv88e6xxx_bridge_map(chip, br) ||
2388 mv88e6xxx_port_vlan_map(chip, port))
2389 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002390 mv88e6xxx_reg_unlock(chip);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05002391}
2392
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002393static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2394 int tree_index, int sw_index,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002395 int port, struct net_device *br)
2396{
2397 struct mv88e6xxx_chip *chip = ds->priv;
2398 int err;
2399
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002400 if (tree_index != ds->dst->index)
2401 return 0;
2402
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002403 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002404 err = mv88e6xxx_pvt_map(chip, sw_index, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002405 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002406
2407 return err;
2408}
2409
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002410static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2411 int tree_index, int sw_index,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002412 int port, struct net_device *br)
2413{
2414 struct mv88e6xxx_chip *chip = ds->priv;
2415
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002416 if (tree_index != ds->dst->index)
2417 return;
2418
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002419 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002420 if (mv88e6xxx_pvt_map(chip, sw_index, port))
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002421 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002422 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002423}
2424
Vivien Didelot17e708b2016-12-05 17:30:27 -05002425static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2426{
2427 if (chip->info->ops->reset)
2428 return chip->info->ops->reset(chip);
2429
2430 return 0;
2431}
2432
Vivien Didelot309eca62016-12-05 17:30:26 -05002433static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2434{
2435 struct gpio_desc *gpiod = chip->reset;
2436
2437 /* If there is a GPIO connected to the reset pin, toggle it */
2438 if (gpiod) {
2439 gpiod_set_value_cansleep(gpiod, 1);
2440 usleep_range(10000, 20000);
2441 gpiod_set_value_cansleep(gpiod, 0);
2442 usleep_range(10000, 20000);
Andrew Lunna3dcb3e2020-11-16 08:43:01 -08002443
2444 mv88e6xxx_g1_wait_eeprom_done(chip);
Vivien Didelot309eca62016-12-05 17:30:26 -05002445 }
2446}
2447
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002448static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2449{
2450 int i, err;
2451
2452 /* Set all ports to the Disabled state */
2453 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotf894c292017-06-08 18:34:10 -04002454 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002455 if (err)
2456 return err;
2457 }
2458
2459 /* Wait for transmit queues to drain,
2460 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2461 */
2462 usleep_range(2000, 4000);
2463
2464 return 0;
2465}
2466
Vivien Didelotfad09c72016-06-21 12:28:20 -04002467static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002468{
Vivien Didelota935c052016-09-29 12:21:53 -04002469 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002470
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002471 err = mv88e6xxx_disable_ports(chip);
2472 if (err)
2473 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002474
Vivien Didelot309eca62016-12-05 17:30:26 -05002475 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002476
Vivien Didelot17e708b2016-12-05 17:30:27 -05002477 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002478}
2479
Vivien Didelot43145572017-03-11 16:12:59 -05002480static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002481 enum mv88e6xxx_frame_mode frame,
2482 enum mv88e6xxx_egress_mode egress, u16 etype)
Andrew Lunn56995cb2016-12-03 04:35:19 +01002483{
2484 int err;
2485
Vivien Didelot43145572017-03-11 16:12:59 -05002486 if (!chip->info->ops->port_set_frame_mode)
2487 return -EOPNOTSUPP;
2488
2489 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002490 if (err)
2491 return err;
2492
Vivien Didelot43145572017-03-11 16:12:59 -05002493 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2494 if (err)
2495 return err;
2496
2497 if (chip->info->ops->port_set_ether_type)
2498 return chip->info->ops->port_set_ether_type(chip, port, etype);
2499
2500 return 0;
2501}
2502
2503static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2504{
2505 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002506 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002507 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002508}
2509
2510static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2511{
2512 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002513 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002514 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002515}
2516
2517static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2518{
2519 return mv88e6xxx_set_port_mode(chip, port,
2520 MV88E6XXX_FRAME_MODE_ETHERTYPE,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002521 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2522 ETH_P_EDSA);
Vivien Didelot43145572017-03-11 16:12:59 -05002523}
2524
2525static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2526{
2527 if (dsa_is_dsa_port(chip->ds, port))
2528 return mv88e6xxx_set_port_mode_dsa(chip, port);
2529
Vivien Didelot2b3e9892017-10-26 11:22:54 -04002530 if (dsa_is_user_port(chip->ds, port))
Vivien Didelot43145572017-03-11 16:12:59 -05002531 return mv88e6xxx_set_port_mode_normal(chip, port);
2532
2533 /* Setup CPU port mode depending on its supported tag format */
Tobias Waldekranz670bb802021-04-20 20:53:07 +02002534 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
Vivien Didelot43145572017-03-11 16:12:59 -05002535 return mv88e6xxx_set_port_mode_dsa(chip, port);
2536
Tobias Waldekranz670bb802021-04-20 20:53:07 +02002537 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
Vivien Didelot43145572017-03-11 16:12:59 -05002538 return mv88e6xxx_set_port_mode_edsa(chip, port);
2539
2540 return -EINVAL;
2541}
2542
Vivien Didelotea698f42017-03-11 16:12:50 -05002543static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2544{
2545 bool message = dsa_is_dsa_port(chip->ds, port);
2546
2547 return mv88e6xxx_port_set_message_port(chip, port, message);
2548}
2549
Vivien Didelot601aeed2017-03-11 16:13:00 -05002550static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2551{
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002552 int err;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002553
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002554 if (chip->info->ops->port_set_ucast_flood) {
Tobias Waldekranz7b9f16f2021-03-18 20:25:38 +01002555 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002556 if (err)
2557 return err;
2558 }
2559 if (chip->info->ops->port_set_mcast_flood) {
Tobias Waldekranz7b9f16f2021-03-18 20:25:38 +01002560 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02002561 if (err)
2562 return err;
2563 }
Vivien Didelot601aeed2017-03-11 16:13:00 -05002564
David S. Miller407308f2019-06-15 13:35:29 -07002565 return 0;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002566}
2567
Vivien Didelot45de77f2019-08-31 16:18:36 -04002568static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2569{
2570 struct mv88e6xxx_port *mvp = dev_id;
2571 struct mv88e6xxx_chip *chip = mvp->chip;
2572 irqreturn_t ret = IRQ_NONE;
2573 int port = mvp->port;
Pavana Sharma193c5b22021-03-17 14:46:40 +01002574 int lane;
Vivien Didelot45de77f2019-08-31 16:18:36 -04002575
2576 mv88e6xxx_reg_lock(chip);
2577 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +01002578 if (lane >= 0)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002579 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2580 mv88e6xxx_reg_unlock(chip);
2581
2582 return ret;
2583}
2584
2585static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
Pavana Sharma193c5b22021-03-17 14:46:40 +01002586 int lane)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002587{
2588 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2589 unsigned int irq;
2590 int err;
2591
2592 /* Nothing to request if this SERDES port has no IRQ */
2593 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2594 if (!irq)
2595 return 0;
2596
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002597 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2598 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2599
Vivien Didelot45de77f2019-08-31 16:18:36 -04002600 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2601 mv88e6xxx_reg_unlock(chip);
2602 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002603 IRQF_ONESHOT, dev_id->serdes_irq_name,
2604 dev_id);
Vivien Didelot45de77f2019-08-31 16:18:36 -04002605 mv88e6xxx_reg_lock(chip);
2606 if (err)
2607 return err;
2608
2609 dev_id->serdes_irq = irq;
2610
2611 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2612}
2613
2614static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
Pavana Sharma193c5b22021-03-17 14:46:40 +01002615 int lane)
Vivien Didelot45de77f2019-08-31 16:18:36 -04002616{
2617 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2618 unsigned int irq = dev_id->serdes_irq;
2619 int err;
2620
2621 /* Nothing to free if no IRQ has been requested */
2622 if (!irq)
2623 return 0;
2624
2625 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2626
2627 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2628 mv88e6xxx_reg_unlock(chip);
2629 free_irq(irq, dev_id);
2630 mv88e6xxx_reg_lock(chip);
2631
2632 dev_id->serdes_irq = 0;
2633
2634 return err;
2635}
2636
Andrew Lunn6d917822017-05-26 01:03:21 +02002637static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2638 bool on)
2639{
Pavana Sharma193c5b22021-03-17 14:46:40 +01002640 int lane;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002641 int err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002642
Vivien Didelotdc272f62019-08-31 16:18:33 -04002643 lane = mv88e6xxx_serdes_get_lane(chip, port);
Pavana Sharma193c5b22021-03-17 14:46:40 +01002644 if (lane < 0)
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002645 return 0;
2646
2647 if (on) {
Vivien Didelotdc272f62019-08-31 16:18:33 -04002648 err = mv88e6xxx_serdes_power_up(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002649 if (err)
2650 return err;
2651
Vivien Didelot45de77f2019-08-31 16:18:36 -04002652 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002653 } else {
Vivien Didelot45de77f2019-08-31 16:18:36 -04002654 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2655 if (err)
2656 return err;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002657
Vivien Didelotdc272f62019-08-31 16:18:33 -04002658 err = mv88e6xxx_serdes_power_down(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002659 }
2660
2661 return err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002662}
2663
Marek Behún2fda45f2021-03-17 14:46:41 +01002664static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2665 enum mv88e6xxx_egress_direction direction,
2666 int port)
2667{
2668 int err;
2669
2670 if (!chip->info->ops->set_egress_port)
2671 return -EOPNOTSUPP;
2672
2673 err = chip->info->ops->set_egress_port(chip, direction, port);
2674 if (err)
2675 return err;
2676
2677 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2678 chip->ingress_dest_port = port;
2679 else
2680 chip->egress_dest_port = port;
2681
2682 return 0;
2683}
2684
Vivien Didelotfa371c82017-12-05 15:34:10 -05002685static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2686{
2687 struct dsa_switch *ds = chip->ds;
2688 int upstream_port;
2689 int err;
2690
Vivien Didelot07073c72017-12-05 15:34:13 -05002691 upstream_port = dsa_upstream_port(ds, port);
Vivien Didelotfa371c82017-12-05 15:34:10 -05002692 if (chip->info->ops->port_set_upstream_port) {
2693 err = chip->info->ops->port_set_upstream_port(chip, port,
2694 upstream_port);
2695 if (err)
2696 return err;
2697 }
2698
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002699 if (port == upstream_port) {
2700 if (chip->info->ops->set_cpu_port) {
2701 err = chip->info->ops->set_cpu_port(chip,
2702 upstream_port);
2703 if (err)
2704 return err;
2705 }
2706
Marek Behún2fda45f2021-03-17 14:46:41 +01002707 err = mv88e6xxx_set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002708 MV88E6XXX_EGRESS_DIR_INGRESS,
2709 upstream_port);
Marek Behún2fda45f2021-03-17 14:46:41 +01002710 if (err && err != -EOPNOTSUPP)
2711 return err;
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002712
Marek Behún2fda45f2021-03-17 14:46:41 +01002713 err = mv88e6xxx_set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002714 MV88E6XXX_EGRESS_DIR_EGRESS,
2715 upstream_port);
Marek Behún2fda45f2021-03-17 14:46:41 +01002716 if (err && err != -EOPNOTSUPP)
2717 return err;
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002718 }
2719
Vivien Didelotfa371c82017-12-05 15:34:10 -05002720 return 0;
2721}
2722
Vivien Didelotfad09c72016-06-21 12:28:20 -04002723static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002724{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002725 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002726 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002727 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002728
Andrew Lunn7b898462018-08-09 15:38:47 +02002729 chip->ports[port].chip = chip;
2730 chip->ports[port].port = port;
2731
Vivien Didelotd78343d2016-11-04 03:23:36 +01002732 /* MAC Forcing register: don't force link, speed, duplex or flow control
2733 * state to any particular values on physical ports, but force the CPU
2734 * port and all DSA ports to their maximum bandwidth and full duplex.
2735 */
2736 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2737 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2738 SPEED_MAX, DUPLEX_FULL,
Andrew Lunn54186b92018-08-09 15:38:37 +02002739 PAUSE_OFF,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002740 PHY_INTERFACE_MODE_NA);
2741 else
2742 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2743 SPEED_UNFORCED, DUPLEX_UNFORCED,
Andrew Lunn54186b92018-08-09 15:38:37 +02002744 PAUSE_ON,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002745 PHY_INTERFACE_MODE_NA);
2746 if (err)
2747 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002748
2749 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2750 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2751 * tunneling, determine priority by looking at 802.1p and IP
2752 * priority fields (IP prio has precedence), and set STP state
2753 * to Forwarding.
2754 *
2755 * If this is the CPU link, use DSA or EDSA tagging depending
2756 * on which tagging mode was configured.
2757 *
2758 * If this is a link to another switch, use DSA tagging mode.
2759 *
2760 * If this is the upstream port for this switch, enable
2761 * forwarding of unknown unicasts and multicasts.
2762 */
Vivien Didelota89b433be2017-06-12 12:37:37 -04002763 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2764 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2765 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2766 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002767 if (err)
2768 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002769
Vivien Didelot601aeed2017-03-11 16:13:00 -05002770 err = mv88e6xxx_setup_port_mode(chip, port);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002771 if (err)
2772 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002773
Vivien Didelot601aeed2017-03-11 16:13:00 -05002774 err = mv88e6xxx_setup_egress_floods(chip, port);
Vivien Didelot43145572017-03-11 16:12:59 -05002775 if (err)
2776 return err;
2777
Vivien Didelot8efdda42015-08-13 12:52:23 -04002778 /* Port Control 2: don't force a good FCS, set the maximum frame size to
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002779 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002780 * untagged frames on this port, do a destination address lookup on all
2781 * received packets as usual, disable ARP mirroring and don't send a
2782 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002783 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002784 err = mv88e6xxx_port_set_map_da(chip, port);
2785 if (err)
2786 return err;
2787
Vivien Didelotfa371c82017-12-05 15:34:10 -05002788 err = mv88e6xxx_setup_upstream_port(chip, port);
2789 if (err)
2790 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002791
Andrew Lunna23b2962017-02-04 20:15:28 +01002792 err = mv88e6xxx_port_set_8021q_mode(chip, port,
Vivien Didelot81c6edb2017-06-12 12:37:41 -04002793 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
Andrew Lunna23b2962017-02-04 20:15:28 +01002794 if (err)
2795 return err;
2796
Vivien Didelotcd782652017-06-08 18:34:13 -04002797 if (chip->info->ops->port_set_jumbo_size) {
2798 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
Andrew Lunn5f436662016-12-03 04:45:17 +01002799 if (err)
2800 return err;
2801 }
2802
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002803 /* Port Association Vector: disable automatic address learning
2804 * on all user ports since they start out in standalone
2805 * mode. When joining a bridge, learning will be configured to
2806 * match the bridge port settings. Enable learning on all
2807 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2808 * learning process.
2809 *
2810 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2811 * and RefreshLocked. I.e. setup standard automatic learning.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002812 */
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002813 if (dsa_is_user_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002814 reg = 0;
Tobias Waldekranz041bd542021-03-18 20:25:39 +01002815 else
2816 reg = 1 << port;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002817
Vivien Didelot2a4614e2017-06-12 12:37:43 -04002818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2819 reg);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002820 if (err)
2821 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002822
2823 /* Egress rate control 2: disable egress rate control. */
Vivien Didelot2cb8cb12017-06-12 12:37:42 -04002824 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2825 0x0000);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002826 if (err)
2827 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002828
Vivien Didelot08984322017-06-08 18:34:12 -04002829 if (chip->info->ops->port_pause_limit) {
2830 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002831 if (err)
2832 return err;
2833 }
2834
Vivien Didelotc8c94892017-03-11 16:13:01 -05002835 if (chip->info->ops->port_disable_learn_limit) {
2836 err = chip->info->ops->port_disable_learn_limit(chip, port);
2837 if (err)
2838 return err;
2839 }
2840
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002841 if (chip->info->ops->port_disable_pri_override) {
2842 err = chip->info->ops->port_disable_pri_override(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002843 if (err)
2844 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002845 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002846
Andrew Lunnef0a7312016-12-03 04:35:16 +01002847 if (chip->info->ops->port_tag_remap) {
2848 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002849 if (err)
2850 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002851 }
2852
Andrew Lunnef70b112016-12-03 04:45:18 +01002853 if (chip->info->ops->port_egress_rate_limiting) {
2854 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002855 if (err)
2856 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002857 }
2858
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02002859 if (chip->info->ops->port_setup_message_port) {
2860 err = chip->info->ops->port_setup_message_port(chip, port);
2861 if (err)
2862 return err;
2863 }
Guenter Roeckd827e882015-03-26 18:36:29 -07002864
Vivien Didelot207afda2016-04-14 14:42:09 -04002865 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002866 * database, and allow bidirectional communication between the
2867 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07002868 */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002869 err = mv88e6xxx_port_set_fid(chip, port, 0);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002870 if (err)
2871 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002872
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002873 err = mv88e6xxx_port_vlan_map(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002874 if (err)
2875 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002876
2877 /* Default VLAN ID and priority: don't set a default VLAN
2878 * ID, and set the default packet priority to zero.
2879 */
Vivien Didelotb7929fb2017-06-12 12:37:40 -04002880 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
Andrew Lunndbde9e62015-05-06 01:09:48 +02002881}
2882
Andrew Lunn2a550ae2020-07-11 22:32:05 +02002883static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2884{
2885 struct mv88e6xxx_chip *chip = ds->priv;
2886
2887 if (chip->info->ops->port_set_jumbo_size)
2888 return 10240;
Chris Packham1baf0fa2020-07-24 11:21:22 +12002889 else if (chip->info->ops->set_max_frame_size)
2890 return 1632;
Andrew Lunn2a550ae2020-07-11 22:32:05 +02002891 return 1522;
2892}
2893
2894static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2895{
2896 struct mv88e6xxx_chip *chip = ds->priv;
2897 int ret = 0;
2898
2899 mv88e6xxx_reg_lock(chip);
2900 if (chip->info->ops->port_set_jumbo_size)
2901 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
Chris Packham1baf0fa2020-07-24 11:21:22 +12002902 else if (chip->info->ops->set_max_frame_size)
2903 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
Andrew Lunn2a550ae2020-07-11 22:32:05 +02002904 else
2905 if (new_mtu > 1522)
2906 ret = -EINVAL;
2907 mv88e6xxx_reg_unlock(chip);
2908
2909 return ret;
2910}
2911
Andrew Lunn04aca992017-05-26 01:03:24 +02002912static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2913 struct phy_device *phydev)
2914{
2915 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot523a8902017-05-26 18:02:42 -04002916 int err;
Andrew Lunn04aca992017-05-26 01:03:24 +02002917
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002918 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04002919 err = mv88e6xxx_serdes_power(chip, port, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002920 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02002921
2922 return err;
2923}
2924
Andrew Lunn75104db2019-02-24 20:44:43 +01002925static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
Andrew Lunn04aca992017-05-26 01:03:24 +02002926{
2927 struct mv88e6xxx_chip *chip = ds->priv;
2928
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002929 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04002930 if (mv88e6xxx_serdes_power(chip, port, false))
2931 dev_err(chip->dev, "failed to power off SERDES\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002932 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02002933}
2934
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002935static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2936 unsigned int ageing_time)
2937{
Vivien Didelot04bed142016-08-31 18:06:13 -04002938 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002939 int err;
2940
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002941 mv88e6xxx_reg_lock(chip);
Vivien Didelot720c6342017-03-11 16:12:48 -05002942 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002943 mv88e6xxx_reg_unlock(chip);
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002944
2945 return err;
2946}
2947
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002948static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04002949{
2950 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04002951
Andrew Lunnde2273872016-11-21 23:27:01 +01002952 /* Initialize the statistics unit */
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002953 if (chip->info->ops->stats_set_histogram) {
2954 err = chip->info->ops->stats_set_histogram(chip);
2955 if (err)
2956 return err;
2957 }
Andrew Lunnde2273872016-11-21 23:27:01 +01002958
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002959 return mv88e6xxx_g1_stats_clear(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04002960}
2961
Andrew Lunnea890982019-01-09 00:24:03 +01002962/* Check if the errata has already been applied. */
2963static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2964{
2965 int port;
2966 int err;
2967 u16 val;
2968
2969 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02002970 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
Andrew Lunnea890982019-01-09 00:24:03 +01002971 if (err) {
2972 dev_err(chip->dev,
2973 "Error reading hidden register: %d\n", err);
2974 return false;
2975 }
2976 if (val != 0x01c0)
2977 return false;
2978 }
2979
2980 return true;
2981}
2982
2983/* The 6390 copper ports have an errata which require poking magic
2984 * values into undocumented hidden registers and then performing a
2985 * software reset.
2986 */
2987static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2988{
2989 int port;
2990 int err;
2991
2992 if (mv88e6390_setup_errata_applied(chip))
2993 return 0;
2994
2995 /* Set the ports into blocking mode */
2996 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2997 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2998 if (err)
2999 return err;
3000 }
3001
3002 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02003003 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
Andrew Lunnea890982019-01-09 00:24:03 +01003004 if (err)
3005 return err;
3006 }
3007
3008 return mv88e6xxx_software_reset(chip);
3009}
3010
Andrew Lunn23e8b472019-10-25 01:03:52 +02003011static void mv88e6xxx_teardown(struct dsa_switch *ds)
3012{
3013 mv88e6xxx_teardown_devlink_params(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003014 dsa_devlink_resources_unregister(ds);
Andrew Lunnbfb25542020-09-18 21:11:07 +02003015 mv88e6xxx_teardown_devlink_regions(ds);
Andrew Lunn23e8b472019-10-25 01:03:52 +02003016}
3017
Vivien Didelotf81ec902016-05-09 13:22:58 -04003018static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07003019{
Vivien Didelot04bed142016-08-31 18:06:13 -04003020 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003021 u8 cmode;
Vivien Didelot552238b2016-05-09 13:22:49 -04003022 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04003023 int i;
3024
Vivien Didelotfad09c72016-06-21 12:28:20 -04003025 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003026 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04003027
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003028 mv88e6xxx_reg_lock(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04003029
Andrew Lunnea890982019-01-09 00:24:03 +01003030 if (chip->info->ops->setup_errata) {
3031 err = chip->info->ops->setup_errata(chip);
3032 if (err)
3033 goto unlock;
3034 }
3035
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003036 /* Cache the cmode of each port. */
3037 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3038 if (chip->info->ops->port_get_cmode) {
3039 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3040 if (err)
Dan Carpentere29129f2018-08-14 12:09:05 +03003041 goto unlock;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003042
3043 chip->ports[i].cmode = cmode;
3044 }
3045 }
3046
Vivien Didelot97299342016-07-18 20:45:30 -04003047 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04003048 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotb759f522019-08-19 16:00:52 -04003049 if (dsa_is_unused_port(ds, i))
3050 continue;
3051
Hubert Feursteinc8574862019-07-31 10:23:48 +02003052 /* Prevent the use of an invalid port. */
Vivien Didelotb759f522019-08-19 16:00:52 -04003053 if (mv88e6xxx_is_invalid_port(chip, i)) {
Hubert Feursteinc8574862019-07-31 10:23:48 +02003054 dev_err(chip->dev, "port %d is invalid\n", i);
3055 err = -EINVAL;
3056 goto unlock;
3057 }
3058
Vivien Didelot97299342016-07-18 20:45:30 -04003059 err = mv88e6xxx_setup_port(chip, i);
3060 if (err)
3061 goto unlock;
3062 }
3063
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003064 err = mv88e6xxx_irl_setup(chip);
3065 if (err)
3066 goto unlock;
3067
Vivien Didelot04a69a12017-10-13 14:18:05 -04003068 err = mv88e6xxx_mac_setup(chip);
3069 if (err)
3070 goto unlock;
3071
Vivien Didelot1b17aed2017-05-26 18:03:05 -04003072 err = mv88e6xxx_phy_setup(chip);
3073 if (err)
3074 goto unlock;
3075
Vivien Didelotb486d7c2017-05-01 14:05:13 -04003076 err = mv88e6xxx_vtu_setup(chip);
3077 if (err)
3078 goto unlock;
3079
Vivien Didelot81228992017-03-30 17:37:08 -04003080 err = mv88e6xxx_pvt_setup(chip);
3081 if (err)
3082 goto unlock;
3083
Vivien Didelota2ac29d2017-03-11 16:12:49 -05003084 err = mv88e6xxx_atu_setup(chip);
3085 if (err)
3086 goto unlock;
3087
Andrew Lunn87fa8862017-11-09 22:29:56 +01003088 err = mv88e6xxx_broadcast_setup(chip, 0);
3089 if (err)
3090 goto unlock;
3091
Vivien Didelot9e907d72017-07-17 13:03:43 -04003092 err = mv88e6xxx_pot_setup(chip);
3093 if (err)
3094 goto unlock;
3095
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003096 err = mv88e6xxx_rmu_setup(chip);
3097 if (err)
3098 goto unlock;
3099
Vivien Didelot51c901a2017-07-17 13:03:41 -04003100 err = mv88e6xxx_rsvd2cpu_setup(chip);
3101 if (err)
3102 goto unlock;
Andrew Lunn6e55f692016-12-03 04:45:16 +01003103
Vivien Didelotb28f8722018-04-26 21:56:44 -04003104 err = mv88e6xxx_trunk_setup(chip);
3105 if (err)
3106 goto unlock;
3107
Vivien Didelotc7f047b2018-04-26 21:56:45 -04003108 err = mv88e6xxx_devmap_setup(chip);
3109 if (err)
3110 goto unlock;
3111
Vivien Didelot93e18d62018-05-11 17:16:35 -04003112 err = mv88e6xxx_pri_setup(chip);
3113 if (err)
3114 goto unlock;
3115
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01003116 /* Setup PTP Hardware Clock and timestamping */
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01003117 if (chip->info->ptp_support) {
3118 err = mv88e6xxx_ptp_setup(chip);
3119 if (err)
3120 goto unlock;
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01003121
3122 err = mv88e6xxx_hwtstamp_setup(chip);
3123 if (err)
3124 goto unlock;
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01003125 }
3126
Vivien Didelot447b1bb2018-05-11 17:16:36 -04003127 err = mv88e6xxx_stats_setup(chip);
3128 if (err)
3129 goto unlock;
3130
Vivien Didelot6b17e862015-08-13 12:52:18 -04003131unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003132 mv88e6xxx_reg_unlock(chip);
Andrew Lunndb687a52015-06-20 21:31:29 +02003133
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003134 if (err)
3135 return err;
3136
3137 /* Have to be called without holding the register lock, since
3138 * they take the devlink lock, and we later take the locks in
3139 * the reverse order when getting/setting parameters or
3140 * resource occupancy.
Andrew Lunn23e8b472019-10-25 01:03:52 +02003141 */
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003142 err = mv88e6xxx_setup_devlink_resources(ds);
3143 if (err)
3144 return err;
3145
3146 err = mv88e6xxx_setup_devlink_params(ds);
3147 if (err)
Andrew Lunnbfb25542020-09-18 21:11:07 +02003148 goto out_resources;
3149
3150 err = mv88e6xxx_setup_devlink_regions(ds);
3151 if (err)
3152 goto out_params;
3153
3154 return 0;
3155
3156out_params:
3157 mv88e6xxx_teardown_devlink_params(ds);
3158out_resources:
3159 dsa_devlink_resources_unregister(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01003160
3161 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003162}
3163
Pali Rohár1fe976d2021-04-12 18:57:39 +02003164/* prod_id for switch families which do not have a PHY model number */
3165static const u16 family_prod_id_table[] = {
3166 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3167 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Marek Behúnc5d015b2021-04-20 09:54:02 +02003168 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
Pali Rohár1fe976d2021-04-12 18:57:39 +02003169};
3170
Vivien Didelote57e5e72016-08-15 17:19:00 -04003171static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003172{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003173 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3174 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Pali Rohár1fe976d2021-04-12 18:57:39 +02003175 u16 prod_id;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003176 u16 val;
3177 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003178
Andrew Lunnee26a222017-01-24 14:53:48 +01003179 if (!chip->info->ops->phy_read)
3180 return -EOPNOTSUPP;
3181
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003182 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003183 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003184 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003185
Pali Rohár1fe976d2021-04-12 18:57:39 +02003186 /* Some internal PHYs don't have a model number. */
3187 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3188 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3189 prod_id = family_prod_id_table[chip->info->family];
3190 if (prod_id)
3191 val |= prod_id >> 4;
Andrew Lunnda9f3302017-02-01 03:40:05 +01003192 }
3193
Vivien Didelote57e5e72016-08-15 17:19:00 -04003194 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003195}
3196
Vivien Didelote57e5e72016-08-15 17:19:00 -04003197static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003198{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003199 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3200 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003201 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003202
Andrew Lunnee26a222017-01-24 14:53:48 +01003203 if (!chip->info->ops->phy_write)
3204 return -EOPNOTSUPP;
3205
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003206 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003207 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003208 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003209
3210 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003211}
3212
Vivien Didelotfad09c72016-06-21 12:28:20 -04003213static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01003214 struct device_node *np,
3215 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02003216{
3217 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003218 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003219 struct mii_bus *bus;
3220 int err;
3221
Andrew Lunn2510bab2018-02-22 01:51:49 +01003222 if (external) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003223 mv88e6xxx_reg_lock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003224 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003225 mv88e6xxx_reg_unlock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003226
3227 if (err)
3228 return err;
3229 }
3230
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003231 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02003232 if (!bus)
3233 return -ENOMEM;
3234
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003235 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003236 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003237 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003238 INIT_LIST_HEAD(&mdio_bus->list);
3239 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003240
Andrew Lunnb516d452016-06-04 21:17:06 +02003241 if (np) {
3242 bus->name = np->full_name;
Rob Herringf7ce9102017-07-18 16:43:19 -05003243 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003244 } else {
3245 bus->name = "mv88e6xxx SMI";
3246 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3247 }
3248
3249 bus->read = mv88e6xxx_mdio_read;
3250 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003251 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02003252
Andrew Lunn6f882842018-03-17 20:32:05 +01003253 if (!external) {
3254 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3255 if (err)
3256 return err;
3257 }
3258
Florian Fainelli00e798c2018-05-15 16:56:19 -07003259 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003260 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003261 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunn6f882842018-03-17 20:32:05 +01003262 mv88e6xxx_g2_irq_mdio_free(chip, bus);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003263 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02003264 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003265
3266 if (external)
3267 list_add_tail(&mdio_bus->list, &chip->mdios);
3268 else
3269 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02003270
3271 return 0;
Andrew Lunnb516d452016-06-04 21:17:06 +02003272}
3273
Andrew Lunn3126aee2017-12-07 01:05:57 +01003274static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3275
3276{
3277 struct mv88e6xxx_mdio_bus *mdio_bus;
3278 struct mii_bus *bus;
3279
3280 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3281 bus = mdio_bus->bus;
3282
Andrew Lunn6f882842018-03-17 20:32:05 +01003283 if (!mdio_bus->external)
3284 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3285
Andrew Lunn3126aee2017-12-07 01:05:57 +01003286 mdiobus_unregister(bus);
3287 }
3288}
3289
Andrew Lunna3c53be52017-01-24 14:53:50 +01003290static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3291 struct device_node *np)
3292{
Andrew Lunna3c53be52017-01-24 14:53:50 +01003293 struct device_node *child;
3294 int err;
3295
3296 /* Always register one mdio bus for the internal/default mdio
3297 * bus. This maybe represented in the device tree, but is
3298 * optional.
3299 */
3300 child = of_get_child_by_name(np, "mdio");
3301 err = mv88e6xxx_mdio_register(chip, child, false);
3302 if (err)
3303 return err;
3304
3305 /* Walk the device tree, and see if there are any other nodes
3306 * which say they are compatible with the external mdio
3307 * bus.
3308 */
3309 for_each_available_child_of_node(np, child) {
Andrew Lunnceb96fa2020-09-01 04:32:57 +02003310 if (of_device_is_compatible(
3311 child, "marvell,mv88e6xxx-mdio-external")) {
Andrew Lunna3c53be52017-01-24 14:53:50 +01003312 err = mv88e6xxx_mdio_register(chip, child, true);
Andrew Lunn3126aee2017-12-07 01:05:57 +01003313 if (err) {
3314 mv88e6xxx_mdios_unregister(chip);
Nishka Dasgupta78e42042019-07-23 16:13:07 +05303315 of_node_put(child);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003316 return err;
Andrew Lunn3126aee2017-12-07 01:05:57 +01003317 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003318 }
3319 }
3320
3321 return 0;
3322}
3323
Vivien Didelot855b1932016-07-20 18:18:35 -04003324static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3325{
Vivien Didelot04bed142016-08-31 18:06:13 -04003326 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003327
3328 return chip->eeprom_len;
3329}
3330
Vivien Didelot855b1932016-07-20 18:18:35 -04003331static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3332 struct ethtool_eeprom *eeprom, u8 *data)
3333{
Vivien Didelot04bed142016-08-31 18:06:13 -04003334 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003335 int err;
3336
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003337 if (!chip->info->ops->get_eeprom)
3338 return -EOPNOTSUPP;
3339
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003340 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003341 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003342 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003343
3344 if (err)
3345 return err;
3346
3347 eeprom->magic = 0xc3ec4951;
3348
3349 return 0;
3350}
3351
Vivien Didelot855b1932016-07-20 18:18:35 -04003352static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3353 struct ethtool_eeprom *eeprom, u8 *data)
3354{
Vivien Didelot04bed142016-08-31 18:06:13 -04003355 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003356 int err;
3357
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003358 if (!chip->info->ops->set_eeprom)
3359 return -EOPNOTSUPP;
3360
Vivien Didelot855b1932016-07-20 18:18:35 -04003361 if (eeprom->magic != 0xc3ec4951)
3362 return -EINVAL;
3363
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003364 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003365 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003366 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003367
3368 return err;
3369}
3370
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003371static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003372 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3374 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003375 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003376 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003377 .phy_read = mv88e6185_phy_ppu_read,
3378 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003379 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003380 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003381 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003382 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003383 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003384 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3385 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003386 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003387 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003388 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003391 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003392 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003393 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003394 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003395 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3396 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003397 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003398 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3399 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003400 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003401 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003402 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003403 .ppu_enable = mv88e6185_g1_ppu_enable,
3404 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003405 .reset = mv88e6185_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003406 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003407 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003408 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003409 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003410 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003411};
3412
3413static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003414 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003415 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3416 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003417 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003418 .phy_read = mv88e6185_phy_ppu_read,
3419 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003420 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003421 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003422 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003423 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003424 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3425 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunna23b2962017-02-04 20:15:28 +01003426 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003427 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003428 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003429 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003431 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3432 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003433 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003434 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003435 .serdes_power = mv88e6185_serdes_power,
3436 .serdes_get_lane = mv88e6185_serdes_get_lane,
3437 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003438 .ppu_enable = mv88e6185_g1_ppu_enable,
3439 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003440 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003441 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003442 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003443 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003444 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003445};
3446
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003447static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01003448 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003449 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3450 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003451 .irl_init_all = mv88e6352_g2_irl_init_all,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003452 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3453 .phy_read = mv88e6xxx_g2_smi_phy_read,
3454 .phy_write = mv88e6xxx_g2_smi_phy_write,
3455 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003456 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003457 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003458 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003459 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003460 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3461 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003462 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003463 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003464 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003465 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003466 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003467 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003468 .port_setup_message_port = mv88e6xxx_setup_message_port,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003469 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003470 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003471 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3472 .stats_get_strings = mv88e6095_stats_get_strings,
3473 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003474 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3475 .set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01003476 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003477 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003478 .serdes_power = mv88e6185_serdes_power,
3479 .serdes_get_lane = mv88e6185_serdes_get_lane,
3480 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Chris Packham5c19bc82020-11-24 17:34:39 +13003481 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3482 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3483 .serdes_irq_status = mv88e6097_serdes_irq_status,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003484 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003485 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003486 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003487 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003489 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003490 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003491};
3492
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003493static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003494 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3496 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003497 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003499 .phy_read = mv88e6xxx_g2_smi_phy_read,
3500 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003501 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003502 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003503 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003504 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003505 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3506 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003507 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003508 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003509 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003510 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn0ac64c32017-06-02 23:22:46 +02003511 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003512 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003513 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3514 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003515 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003516 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3517 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003518 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003519 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003520 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003521 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003522 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3523 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003524 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003525 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003526 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003527 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003528};
3529
3530static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003531 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003532 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3533 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003534 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003535 .phy_read = mv88e6185_phy_ppu_read,
3536 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003537 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003538 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003539 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003540 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003542 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3543 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003544 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01003545 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Vivien Didelotcd782652017-06-08 18:34:13 -04003546 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003547 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003548 .port_pause_limit = mv88e6097_port_pause_limit,
Andrew Lunn54186b92018-08-09 15:38:37 +02003549 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003550 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003551 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003552 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003553 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003554 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3555 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003556 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003557 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3558 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003559 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003560 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003561 .ppu_enable = mv88e6185_g1_ppu_enable,
Vivien Didelot02317e62018-05-09 11:38:49 -04003562 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003563 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003564 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003565 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003566 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003567 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003568};
3569
Vivien Didelot990e27b2017-03-28 13:50:32 -04003570static const struct mv88e6xxx_ops mv88e6141_ops = {
3571 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003572 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3573 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003574 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003575 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3576 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3577 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3578 .phy_read = mv88e6xxx_g2_smi_phy_read,
3579 .phy_write = mv88e6xxx_g2_smi_phy_write,
3580 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003581 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003582 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003583 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003584 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003585 .port_tag_remap = mv88e6095_port_tag_remap,
Marek Behún7da467d2021-07-01 00:22:26 +02003586 .port_set_policy = mv88e6352_port_set_policy,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003587 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003588 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3589 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003590 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003591 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003592 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003593 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003594 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3595 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003596 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02003597 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003598 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003599 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003600 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003601 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3602 .stats_get_strings = mv88e6320_stats_get_strings,
3603 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003604 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3605 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003606 .watchdog_ops = &mv88e6390_watchdog_ops,
3607 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003608 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003609 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003610 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003611 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02003612 .serdes_power = mv88e6390_serdes_power,
3613 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003614 /* Check status register pause & lpa register */
3615 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3616 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3617 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3618 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003619 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003620 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003621 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003622 .gpio_ops = &mv88e6352_gpio_ops,
Marek Behúne3af71a2019-02-25 12:39:55 +01003623 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003624};
3625
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003626static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003627 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003628 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3629 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003630 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003631 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003632 .phy_read = mv88e6xxx_g2_smi_phy_read,
3633 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003634 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003635 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003636 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003637 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003638 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003639 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3640 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003641 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003642 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003643 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003644 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003645 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003646 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003647 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003648 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna6da21b2019-03-01 23:43:39 +01003649 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003650 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003651 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3652 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003653 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003654 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3655 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003656 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003657 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003658 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003659 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003660 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3661 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003662 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003663 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003664 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003665 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003666 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003667};
3668
3669static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003670 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003671 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3672 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003673 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003674 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003675 .phy_read = mv88e6165_phy_read,
3676 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003677 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003678 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003679 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003680 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003681 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003682 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003683 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003684 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003685 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003686 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3687 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003688 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003689 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3690 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003691 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003692 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003693 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003694 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003695 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3696 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003697 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003698 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003699 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003700 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003701 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003702};
3703
3704static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003705 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003706 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3707 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003708 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003709 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003710 .phy_read = mv88e6xxx_g2_smi_phy_read,
3711 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003712 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003713 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003714 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003715 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003716 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003717 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003718 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3719 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003720 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003721 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003722 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003723 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003724 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003725 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003726 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003727 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003728 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003729 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003730 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3731 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003732 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003733 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3734 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003735 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003736 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003737 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003738 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003739 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3740 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003741 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003742 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003743 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003744};
3745
3746static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003747 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003748 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3749 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003750 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003751 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3752 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003754 .phy_read = mv88e6xxx_g2_smi_phy_read,
3755 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003756 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003757 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003758 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003759 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003760 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003761 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003762 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003763 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3764 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003765 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003766 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003767 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003768 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003769 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003770 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003771 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003772 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003773 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003774 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003775 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3776 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003777 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003778 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3779 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003780 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003781 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003782 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003783 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003784 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003785 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3786 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003787 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003788 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003789 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003790 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3791 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3792 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3793 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003794 .serdes_power = mv88e6352_serdes_power,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003795 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3796 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003797 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003798 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003799};
3800
3801static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003802 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003803 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3804 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003805 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003806 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003807 .phy_read = mv88e6xxx_g2_smi_phy_read,
3808 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003809 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003810 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003811 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003812 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003813 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003814 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003815 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3816 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003817 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003818 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003819 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003820 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003821 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003822 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003823 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003824 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003825 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003826 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003827 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3828 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003829 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003830 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3831 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003832 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003833 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003834 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003835 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003836 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3837 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003838 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003839 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003840 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003841};
3842
3843static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003844 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003845 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3846 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003847 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003848 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3849 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003850 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003851 .phy_read = mv88e6xxx_g2_smi_phy_read,
3852 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003853 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003854 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003855 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003856 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003857 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003858 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003859 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003860 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3861 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003862 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003863 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003864 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003865 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003868 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003869 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003870 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003871 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003872 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3873 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003874 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003875 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3876 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003877 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003878 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003879 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003880 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003881 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003882 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3883 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003884 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003885 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003886 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003887 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3888 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3889 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3890 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003891 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003892 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003893 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003894 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003895 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3896 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003897 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003898 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003899};
3900
3901static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003902 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003903 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3904 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003905 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003906 .phy_read = mv88e6185_phy_ppu_read,
3907 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003908 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003909 .port_sync_link = mv88e6185_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003910 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003911 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003912 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3913 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
Andrew Lunnef70b112016-12-03 04:45:18 +01003914 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01003915 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn54186b92018-08-09 15:38:37 +02003916 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003917 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003918 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003919 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003920 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003921 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3922 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003923 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003924 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3925 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003926 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003927 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Chris Packhamf5be1072020-11-24 17:34:38 +13003928 .serdes_power = mv88e6185_serdes_power,
3929 .serdes_get_lane = mv88e6185_serdes_get_lane,
3930 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
Vivien Didelot02317e62018-05-09 11:38:49 -04003931 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003932 .ppu_enable = mv88e6185_g1_ppu_enable,
3933 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003934 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003935 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003936 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003937 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003938 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003939};
3940
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003941static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003942 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003943 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003944 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003945 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3946 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003947 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3948 .phy_read = mv88e6xxx_g2_smi_phy_read,
3949 .phy_write = mv88e6xxx_g2_smi_phy_write,
3950 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13003951 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003952 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003953 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003954 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003955 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003956 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003957 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02003958 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3959 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003960 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12003961 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04003962 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003963 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003964 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003965 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003966 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003967 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01003968 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003969 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003970 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3971 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003972 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003973 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3974 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003975 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003976 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003977 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003978 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003979 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003980 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3981 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04003982 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3983 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003984 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02003985 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003986 /* Check status register pause & lpa register */
3987 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3988 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3989 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3990 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003991 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003992 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003993 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01003994 .serdes_get_strings = mv88e6390_serdes_get_strings,
3995 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01003996 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3997 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003998 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003999 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004000};
4001
4002static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004003 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004004 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004005 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004006 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4007 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4009 .phy_read = mv88e6xxx_g2_smi_phy_read,
4010 .phy_write = mv88e6xxx_g2_smi_phy_write,
4011 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004012 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004013 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004014 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004015 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004016 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004017 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004018 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004019 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4020 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004021 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12004022 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04004023 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004024 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004025 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004026 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004027 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004028 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004029 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004030 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004031 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4032 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004033 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004034 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4035 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004036 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004037 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004038 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004039 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004040 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004041 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4042 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004043 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4044 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004045 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004046 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004047 /* Check status register pause & lpa register */
4048 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4049 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4050 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4051 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004052 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004053 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004054 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004055 .serdes_get_strings = mv88e6390_serdes_get_strings,
4056 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004057 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4058 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004059 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02004060 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004061};
4062
4063static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004064 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004065 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004066 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004067 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4068 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004069 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4070 .phy_read = mv88e6xxx_g2_smi_phy_read,
4071 .phy_write = mv88e6xxx_g2_smi_phy_write,
4072 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004073 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004074 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004075 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004076 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004077 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004078 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004079 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4080 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004081 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004082 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004085 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004086 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004087 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004088 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004089 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004090 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4091 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004092 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004093 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4094 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004095 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004096 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004097 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004098 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004099 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004100 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4101 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004102 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4103 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004104 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004105 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004106 /* Check status register pause & lpa register */
4107 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4108 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4109 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4110 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004111 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004112 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004113 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004114 .serdes_get_strings = mv88e6390_serdes_get_strings,
4115 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004116 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4117 .serdes_get_regs = mv88e6390_serdes_get_regs,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004118 .avb_ops = &mv88e6390_avb_ops,
4119 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004120 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004121};
4122
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004123static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004124 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004125 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4126 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004127 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004128 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4129 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004130 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004131 .phy_read = mv88e6xxx_g2_smi_phy_read,
4132 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004133 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004134 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004135 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004136 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004137 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004138 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004139 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004140 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4141 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004142 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004143 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004144 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004145 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004146 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004147 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004148 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004149 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004150 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004151 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004152 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4153 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004154 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004155 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4156 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004157 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004158 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004159 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004160 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004161 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004162 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4163 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004164 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004165 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004166 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004167 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4168 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4169 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4170 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004171 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004172 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004173 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004174 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004175 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4176 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004177 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004178 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004179 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004180 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004181};
4182
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004183static const struct mv88e6xxx_ops mv88e6250_ops = {
4184 /* MV88E6XXX_FAMILY_6250 */
4185 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4186 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4187 .irl_init_all = mv88e6352_g2_irl_init_all,
4188 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4189 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4190 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4191 .phy_read = mv88e6xxx_g2_smi_phy_read,
4192 .phy_write = mv88e6xxx_g2_smi_phy_write,
4193 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004194 .port_sync_link = mv88e6xxx_port_sync_link,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004195 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004196 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004197 .port_tag_remap = mv88e6095_port_tag_remap,
4198 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004199 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4200 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004201 .port_set_ether_type = mv88e6351_port_set_ether_type,
4202 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4203 .port_pause_limit = mv88e6097_port_pause_limit,
4204 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004205 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4206 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4207 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4208 .stats_get_strings = mv88e6250_stats_get_strings,
4209 .stats_get_stats = mv88e6250_stats_get_stats,
4210 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4211 .set_egress_port = mv88e6095_g1_set_egress_port,
4212 .watchdog_ops = &mv88e6250_watchdog_ops,
4213 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4214 .pot_clear = mv88e6xxx_g2_pot_clear,
4215 .reset = mv88e6250_g1_reset,
Rasmus Villemoes67c9ed12021-01-25 16:04:48 +01004216 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Rasmus Villemoesb28f3f32021-01-25 16:04:49 +01004217 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Hubert Feurstein71509612019-07-31 10:23:51 +02004218 .avb_ops = &mv88e6352_avb_ops,
4219 .ptp_ops = &mv88e6250_ptp_ops,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004220 .phylink_validate = mv88e6065_phylink_validate,
4221};
4222
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004223static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004224 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004225 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004226 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004227 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4228 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004229 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4230 .phy_read = mv88e6xxx_g2_smi_phy_read,
4231 .phy_write = mv88e6xxx_g2_smi_phy_write,
4232 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004233 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004234 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004235 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004236 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004237 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004238 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004239 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004240 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4241 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004242 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004243 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004244 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004245 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004246 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004247 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004248 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004249 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004250 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004251 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4252 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004253 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004254 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4255 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004256 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004257 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004258 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004259 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004260 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004261 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4262 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004263 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4264 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004265 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004266 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004267 /* Check status register pause & lpa register */
4268 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4269 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4270 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4271 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004272 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004273 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004274 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004275 .serdes_get_strings = mv88e6390_serdes_get_strings,
4276 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004277 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4278 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004279 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004280 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004281 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004282 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004283};
4284
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004285static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004286 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004287 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4288 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004289 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004290 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4291 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004292 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004293 .phy_read = mv88e6xxx_g2_smi_phy_read,
4294 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004295 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004296 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004297 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004298 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004299 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004300 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4301 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004302 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004303 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004304 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004305 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004306 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004307 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004308 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004309 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004310 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004311 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004312 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4313 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004314 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004315 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4316 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004317 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004318 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004319 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004320 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004321 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004322 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004323 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004324 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004325 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004326 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004327};
4328
4329static const struct mv88e6xxx_ops mv88e6321_ops = {
Vivien Didelotbd807202017-07-17 13:03:37 -04004330 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004331 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4332 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004333 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004334 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4335 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004336 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004337 .phy_read = mv88e6xxx_g2_smi_phy_read,
4338 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004339 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004340 .port_sync_link = mv88e6xxx_port_sync_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004341 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004342 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004343 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004344 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4345 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004346 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004347 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004348 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004349 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004350 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004351 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004352 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004353 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004354 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004355 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004356 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4357 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004358 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004359 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4360 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004361 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004362 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004363 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004364 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004365 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004366 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004367 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004368 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004369};
4370
Vivien Didelot16e329a2017-03-28 13:50:33 -04004371static const struct mv88e6xxx_ops mv88e6341_ops = {
4372 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4374 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004375 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004376 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4377 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4379 .phy_read = mv88e6xxx_g2_smi_phy_read,
4380 .phy_write = mv88e6xxx_g2_smi_phy_write,
4381 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004382 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004383 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004384 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004385 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004386 .port_tag_remap = mv88e6095_port_tag_remap,
Marek Behún7da467d2021-07-01 00:22:26 +02004387 .port_set_policy = mv88e6352_port_set_policy,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004388 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004389 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4390 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004391 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004392 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004393 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004394 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004395 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4396 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004397 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02004398 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004399 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004400 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004401 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004402 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4403 .stats_get_strings = mv88e6320_stats_get_strings,
4404 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004405 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4406 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004407 .watchdog_ops = &mv88e6390_watchdog_ops,
4408 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004409 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004410 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004411 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004412 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004413 .serdes_power = mv88e6390_serdes_power,
4414 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004415 /* Check status register pause & lpa register */
4416 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4417 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4418 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4419 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004420 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004421 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004422 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004423 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004424 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004425 .ptp_ops = &mv88e6352_ptp_ops,
Marek Behúne3af71a2019-02-25 12:39:55 +01004426 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004427};
4428
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004429static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004430 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004431 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4432 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004433 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004434 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004435 .phy_read = mv88e6xxx_g2_smi_phy_read,
4436 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004437 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004438 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004439 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004440 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004441 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004442 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004443 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4444 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004445 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004446 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004447 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004448 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004449 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004450 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004451 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004452 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004453 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004454 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004455 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4456 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004457 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004458 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4459 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004460 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004461 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004462 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004463 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004464 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4465 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004466 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004467 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004468 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004469};
4470
4471static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004472 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004473 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4474 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004475 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004476 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004477 .phy_read = mv88e6xxx_g2_smi_phy_read,
4478 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004479 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004480 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004481 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004482 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004483 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004484 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004485 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4486 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004487 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004488 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004489 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004490 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004491 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004492 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004493 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004494 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004495 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004496 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004497 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4498 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004499 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004500 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4501 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004502 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004503 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004504 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004505 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004506 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4507 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004508 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004509 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004510 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004511 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004512 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004513};
4514
4515static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004516 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004517 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4518 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004519 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004520 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4521 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004523 .phy_read = mv88e6xxx_g2_smi_phy_read,
4524 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004525 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004526 .port_sync_link = mv88e6xxx_port_sync_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004527 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004528 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004529 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004530 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004531 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004532 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4533 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004534 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004535 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004536 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004537 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004538 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004539 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004540 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004541 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004542 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004543 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004544 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4545 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004546 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004547 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4548 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004549 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004550 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004551 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004552 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004553 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004554 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4555 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004556 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004557 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004558 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004559 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4560 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4561 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4562 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004563 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004564 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004565 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004566 .serdes_irq_status = mv88e6352_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004567 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004568 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004569 .ptp_ops = &mv88e6352_ptp_ops,
Andrew Lunncda9f4a2018-03-01 02:02:31 +01004570 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4571 .serdes_get_strings = mv88e6352_serdes_get_strings,
4572 .serdes_get_stats = mv88e6352_serdes_get_stats,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004573 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4574 .serdes_get_regs = mv88e6352_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004575 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004576};
4577
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004578static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004579 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004580 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004581 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004582 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4583 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004584 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4585 .phy_read = mv88e6xxx_g2_smi_phy_read,
4586 .phy_write = mv88e6xxx_g2_smi_phy_write,
4587 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004588 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004589 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004590 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004591 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004592 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004593 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004594 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004595 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4596 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004597 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004598 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004599 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004600 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004601 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004602 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004603 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004604 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004605 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004606 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004607 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004608 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4609 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004610 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004611 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4612 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004613 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004614 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004615 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004616 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004617 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004618 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4619 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004620 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4621 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004622 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004623 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004624 /* Check status register pause & lpa register */
4625 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4626 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4627 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4628 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004629 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004630 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004631 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004632 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004633 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004634 .ptp_ops = &mv88e6352_ptp_ops,
Nikita Yushchenko0df95282019-12-25 08:22:38 +03004635 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4636 .serdes_get_strings = mv88e6390_serdes_get_strings,
4637 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004638 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4639 .serdes_get_regs = mv88e6390_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004640 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004641};
4642
4643static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004644 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004645 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004646 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004647 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4648 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004649 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4650 .phy_read = mv88e6xxx_g2_smi_phy_read,
4651 .phy_write = mv88e6xxx_g2_smi_phy_write,
4652 .port_set_link = mv88e6xxx_port_set_link,
Chris Packham4efe76622020-11-24 17:34:37 +13004653 .port_sync_link = mv88e6xxx_port_sync_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004654 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004655 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004656 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004657 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004658 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004659 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02004660 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4661 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004662 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004663 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004664 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004665 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004666 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004667 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004668 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnb3dce4d2018-11-11 00:32:14 +01004669 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004670 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004671 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004672 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004673 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4674 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004675 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004676 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4677 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004678 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004679 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004680 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004681 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004682 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004683 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4684 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004685 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4686 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004687 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004688 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004689 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4690 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4691 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4692 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004693 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004694 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004695 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004696 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4697 .serdes_get_strings = mv88e6390_serdes_get_strings,
4698 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004699 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4700 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004701 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004702 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004703 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004704 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004705};
4706
Pavana Sharmade776d02021-03-17 14:46:42 +01004707static const struct mv88e6xxx_ops mv88e6393x_ops = {
4708 /* MV88E6XXX_FAMILY_6393 */
4709 .setup_errata = mv88e6393x_serdes_setup_errata,
4710 .irl_init_all = mv88e6390_g2_irl_init_all,
4711 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4712 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4713 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4714 .phy_read = mv88e6xxx_g2_smi_phy_read,
4715 .phy_write = mv88e6xxx_g2_smi_phy_write,
4716 .port_set_link = mv88e6xxx_port_set_link,
4717 .port_sync_link = mv88e6xxx_port_sync_link,
4718 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4719 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4720 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4721 .port_tag_remap = mv88e6390_port_tag_remap,
Marek Behún6584b262021-03-17 14:46:43 +01004722 .port_set_policy = mv88e6393x_port_set_policy,
Pavana Sharmade776d02021-03-17 14:46:42 +01004723 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4724 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4725 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4726 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4727 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4728 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4729 .port_pause_limit = mv88e6390_port_pause_limit,
4730 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4731 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4732 .port_get_cmode = mv88e6352_port_get_cmode,
4733 .port_set_cmode = mv88e6393x_port_set_cmode,
4734 .port_setup_message_port = mv88e6xxx_setup_message_port,
4735 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4736 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4737 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4738 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4739 .stats_get_strings = mv88e6320_stats_get_strings,
4740 .stats_get_stats = mv88e6390_stats_get_stats,
4741 /* .set_cpu_port is missing because this family does not support a global
4742 * CPU port, only per port CPU port which is set via
4743 * .port_set_upstream_port method.
4744 */
4745 .set_egress_port = mv88e6393x_set_egress_port,
4746 .watchdog_ops = &mv88e6390_watchdog_ops,
4747 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4748 .pot_clear = mv88e6xxx_g2_pot_clear,
4749 .reset = mv88e6352_g1_reset,
4750 .rmu_disable = mv88e6390_g1_rmu_disable,
4751 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4752 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4753 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4754 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4755 .serdes_power = mv88e6393x_serdes_power,
4756 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4757 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4758 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4759 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4760 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4761 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4762 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4763 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4764 /* TODO: serdes stats */
4765 .gpio_ops = &mv88e6352_gpio_ops,
4766 .avb_ops = &mv88e6390_avb_ops,
4767 .ptp_ops = &mv88e6352_ptp_ops,
4768 .phylink_validate = mv88e6393x_phylink_validate,
4769};
4770
Vivien Didelotf81ec902016-05-09 13:22:58 -04004771static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4772 [MV88E6085] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004773 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004774 .family = MV88E6XXX_FAMILY_6097,
4775 .name = "Marvell 88E6085",
4776 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004777 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004778 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01004779 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004780 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004781 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004782 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004783 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004784 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004785 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004786 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004787 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004788 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004789 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004790 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004791 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004792 },
4793
4794 [MV88E6095] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004795 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004796 .family = MV88E6XXX_FAMILY_6095,
4797 .name = "Marvell 88E6095/88E6095F",
4798 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004799 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004800 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01004801 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004802 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004803 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004804 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004805 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004806 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004807 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004808 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05004809 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004810 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004811 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004812 },
4813
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004814 [MV88E6097] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004815 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004816 .family = MV88E6XXX_FAMILY_6097,
4817 .name = "Marvell 88E6097/88E6097F",
4818 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004819 .num_macs = 8192,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004820 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01004821 .num_internal_phys = 8,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004822 .max_vid = 4095,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004823 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004824 .phy_base_addr = 0x0,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004825 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004826 .global2_addr = 0x1c,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004827 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01004828 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004829 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004830 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004831 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004832 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02004833 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004834 .ops = &mv88e6097_ops,
4835 },
4836
Vivien Didelotf81ec902016-05-09 13:22:58 -04004837 [MV88E6123] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004838 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004839 .family = MV88E6XXX_FAMILY_6165,
4840 .name = "Marvell 88E6123",
4841 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004842 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004843 .num_ports = 3,
Andrew Lunnbc393152018-03-17 20:32:04 +01004844 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004845 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004846 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004847 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004848 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004849 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004850 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004851 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004852 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004853 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004854 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004855 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02004856 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004857 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004858 },
4859
4860 [MV88E6131] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004861 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004862 .family = MV88E6XXX_FAMILY_6185,
4863 .name = "Marvell 88E6131",
4864 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004865 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004866 .num_ports = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004867 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004868 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004869 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004870 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004871 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004872 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004873 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004874 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05004875 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004876 .multi_chip = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004877 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004878 },
4879
Vivien Didelot990e27b2017-03-28 13:50:32 -04004880 [MV88E6141] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004881 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004882 .family = MV88E6XXX_FAMILY_6341,
Uwe Kleine-König79a68b22018-03-20 10:44:40 +01004883 .name = "Marvell 88E6141",
Vivien Didelot990e27b2017-03-28 13:50:32 -04004884 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004885 .num_macs = 2048,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004886 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004887 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004888 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004889 .max_vid = 4095,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004890 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004891 .phy_base_addr = 0x10,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004892 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004893 .global2_addr = 0x1c,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004894 .age_time_coeff = 3750,
4895 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01004896 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004897 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04004898 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004899 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02004900 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004901 .ops = &mv88e6141_ops,
4902 },
4903
Vivien Didelotf81ec902016-05-09 13:22:58 -04004904 [MV88E6161] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004905 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004906 .family = MV88E6XXX_FAMILY_6165,
4907 .name = "Marvell 88E6161",
4908 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004909 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004910 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004911 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004912 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004913 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004914 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004915 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004916 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004917 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004918 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004919 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004920 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004921 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004922 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02004923 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Andrew Lunndfa54342018-07-18 22:38:22 +02004924 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004925 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004926 },
4927
4928 [MV88E6165] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004929 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004930 .family = MV88E6XXX_FAMILY_6165,
4931 .name = "Marvell 88E6165",
4932 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004933 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004934 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004935 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004936 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004937 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004938 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004939 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004940 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004941 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004942 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004943 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004944 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004945 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004946 .multi_chip = true,
Andrew Lunndfa54342018-07-18 22:38:22 +02004947 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004948 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004949 },
4950
4951 [MV88E6171] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004952 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004953 .family = MV88E6XXX_FAMILY_6351,
4954 .name = "Marvell 88E6171",
4955 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004956 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004957 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004958 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004959 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004960 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004961 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004962 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004963 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004964 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004965 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004966 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004967 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004968 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004969 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02004970 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004971 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004972 },
4973
4974 [MV88E6172] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004975 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004976 .family = MV88E6XXX_FAMILY_6352,
4977 .name = "Marvell 88E6172",
4978 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004979 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004980 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004981 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004982 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004983 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004984 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004985 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004986 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004987 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004988 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004989 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004990 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004991 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004992 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004993 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02004994 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004995 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004996 },
4997
4998 [MV88E6175] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004999 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005000 .family = MV88E6XXX_FAMILY_6351,
5001 .name = "Marvell 88E6175",
5002 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005003 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005004 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005005 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005006 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005007 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005008 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005009 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005010 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005011 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005012 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005013 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005014 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005015 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005016 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005017 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005018 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005019 },
5020
5021 [MV88E6176] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005022 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005023 .family = MV88E6XXX_FAMILY_6352,
5024 .name = "Marvell 88E6176",
5025 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005026 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005027 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005028 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005029 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005030 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005031 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005032 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005033 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005034 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005035 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005036 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005037 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005038 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005039 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005040 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005041 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005042 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005043 },
5044
5045 [MV88E6185] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005047 .family = MV88E6XXX_FAMILY_6185,
5048 .name = "Marvell 88E6185",
5049 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005050 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005051 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01005052 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005053 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005054 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005055 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005056 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005057 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005058 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005059 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05005060 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005061 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005062 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005063 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005064 },
5065
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005066 [MV88E6190] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005067 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005068 .family = MV88E6XXX_FAMILY_6390,
5069 .name = "Marvell 88E6190",
5070 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005071 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005072 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005073 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005074 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005075 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005076 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005077 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005078 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005079 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005080 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005081 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005082 .g2_irqs = 14,
Vivien Didelotf3645652017-03-30 17:37:07 -04005083 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005084 .multi_chip = true,
Vivien Didelote606ca32017-03-11 16:12:55 -05005085 .atu_move_port_mask = 0x1f,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005086 .ops = &mv88e6190_ops,
5087 },
5088
5089 [MV88E6190X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005090 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005091 .family = MV88E6XXX_FAMILY_6390,
5092 .name = "Marvell 88E6190X",
5093 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005094 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005095 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005096 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005097 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005098 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005099 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005100 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005101 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005102 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005103 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005104 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005105 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005106 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005107 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005108 .multi_chip = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005109 .ops = &mv88e6190x_ops,
5110 },
5111
5112 [MV88E6191] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005113 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005114 .family = MV88E6XXX_FAMILY_6390,
5115 .name = "Marvell 88E6191",
5116 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005117 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005118 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005119 .num_internal_phys = 9,
Vivien Didelot931d1822017-05-01 14:05:27 -04005120 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005121 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005122 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005123 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005124 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005125 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005126 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005127 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005128 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005129 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005130 .multi_chip = true,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005131 .ptp_support = true,
Vivien Didelot2cf4cefb2017-03-28 13:50:34 -04005132 .ops = &mv88e6191_ops,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005133 },
5134
Pavana Sharmade776d02021-03-17 14:46:42 +01005135 [MV88E6191X] = {
5136 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5137 .family = MV88E6XXX_FAMILY_6393,
5138 .name = "Marvell 88E6191X",
5139 .num_databases = 4096,
5140 .num_ports = 11, /* 10 + Z80 */
5141 .num_internal_phys = 9,
5142 .max_vid = 8191,
5143 .port_base_addr = 0x0,
5144 .phy_base_addr = 0x0,
5145 .global1_addr = 0x1b,
5146 .global2_addr = 0x1c,
5147 .age_time_coeff = 3750,
5148 .g1_irqs = 10,
5149 .g2_irqs = 14,
5150 .atu_move_port_mask = 0x1f,
5151 .pvt = true,
5152 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005153 .ptp_support = true,
5154 .ops = &mv88e6393x_ops,
5155 },
5156
5157 [MV88E6193X] = {
5158 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5159 .family = MV88E6XXX_FAMILY_6393,
5160 .name = "Marvell 88E6193X",
5161 .num_databases = 4096,
5162 .num_ports = 11, /* 10 + Z80 */
5163 .num_internal_phys = 9,
5164 .max_vid = 8191,
5165 .port_base_addr = 0x0,
5166 .phy_base_addr = 0x0,
5167 .global1_addr = 0x1b,
5168 .global2_addr = 0x1c,
5169 .age_time_coeff = 3750,
5170 .g1_irqs = 10,
5171 .g2_irqs = 14,
5172 .atu_move_port_mask = 0x1f,
5173 .pvt = true,
5174 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005175 .ptp_support = true,
5176 .ops = &mv88e6393x_ops,
5177 },
5178
Hubert Feurstein49022642019-07-31 10:23:46 +02005179 [MV88E6220] = {
5180 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5181 .family = MV88E6XXX_FAMILY_6250,
5182 .name = "Marvell 88E6220",
5183 .num_databases = 64,
5184
5185 /* Ports 2-4 are not routed to pins
5186 * => usable ports 0, 1, 5, 6
5187 */
5188 .num_ports = 7,
5189 .num_internal_phys = 2,
Hubert Feursteinc8574862019-07-31 10:23:48 +02005190 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
Hubert Feurstein49022642019-07-31 10:23:46 +02005191 .max_vid = 4095,
5192 .port_base_addr = 0x08,
5193 .phy_base_addr = 0x00,
5194 .global1_addr = 0x0f,
5195 .global2_addr = 0x07,
5196 .age_time_coeff = 15000,
5197 .g1_irqs = 9,
5198 .g2_irqs = 10,
5199 .atu_move_port_mask = 0xf,
5200 .dual_chip = true,
Hubert Feurstein71509612019-07-31 10:23:51 +02005201 .ptp_support = true,
Hubert Feurstein49022642019-07-31 10:23:46 +02005202 .ops = &mv88e6250_ops,
5203 },
5204
Vivien Didelotf81ec902016-05-09 13:22:58 -04005205 [MV88E6240] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005206 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005207 .family = MV88E6XXX_FAMILY_6352,
5208 .name = "Marvell 88E6240",
5209 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005210 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005211 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005212 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005213 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005214 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005215 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005216 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005217 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005218 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005219 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005220 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005221 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005222 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005223 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005224 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005225 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005226 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005227 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005228 },
5229
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005230 [MV88E6250] = {
5231 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5232 .family = MV88E6XXX_FAMILY_6250,
5233 .name = "Marvell 88E6250",
5234 .num_databases = 64,
5235 .num_ports = 7,
5236 .num_internal_phys = 5,
5237 .max_vid = 4095,
5238 .port_base_addr = 0x08,
5239 .phy_base_addr = 0x00,
5240 .global1_addr = 0x0f,
5241 .global2_addr = 0x07,
5242 .age_time_coeff = 15000,
5243 .g1_irqs = 9,
5244 .g2_irqs = 10,
5245 .atu_move_port_mask = 0xf,
5246 .dual_chip = true,
Hubert Feurstein71509612019-07-31 10:23:51 +02005247 .ptp_support = true,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005248 .ops = &mv88e6250_ops,
5249 },
5250
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005251 [MV88E6290] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005252 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005253 .family = MV88E6XXX_FAMILY_6390,
5254 .name = "Marvell 88E6290",
5255 .num_databases = 4096,
5256 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005257 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005258 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005259 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005260 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005261 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005262 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005263 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005264 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005265 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005266 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005267 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005268 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005269 .multi_chip = true,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005270 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005271 .ops = &mv88e6290_ops,
5272 },
5273
Vivien Didelotf81ec902016-05-09 13:22:58 -04005274 [MV88E6320] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005275 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005276 .family = MV88E6XXX_FAMILY_6320,
5277 .name = "Marvell 88E6320",
5278 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005279 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005280 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005281 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005282 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005283 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005284 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005285 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005286 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005287 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005288 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005289 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005290 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005291 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005292 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005293 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005294 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005295 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005296 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005297 },
5298
5299 [MV88E6321] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005300 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005301 .family = MV88E6XXX_FAMILY_6320,
5302 .name = "Marvell 88E6321",
5303 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005304 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005305 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005306 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005307 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005308 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005309 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005310 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005311 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005312 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005313 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005314 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01005315 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005316 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005317 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005318 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005319 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005320 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005321 },
5322
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005323 [MV88E6341] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005325 .family = MV88E6XXX_FAMILY_6341,
5326 .name = "Marvell 88E6341",
5327 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005328 .num_macs = 2048,
Andrew Lunnbc393152018-03-17 20:32:04 +01005329 .num_internal_phys = 5,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005330 .num_ports = 6,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005331 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005332 .max_vid = 4095,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005333 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005334 .phy_base_addr = 0x10,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005335 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005336 .global2_addr = 0x1c,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005337 .age_time_coeff = 3750,
Vivien Didelote606ca32017-03-11 16:12:55 -05005338 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01005339 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005340 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04005341 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005342 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005343 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005344 .ptp_support = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005345 .ops = &mv88e6341_ops,
5346 },
5347
Vivien Didelotf81ec902016-05-09 13:22:58 -04005348 [MV88E6350] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005349 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005350 .family = MV88E6XXX_FAMILY_6351,
5351 .name = "Marvell 88E6350",
5352 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005353 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005354 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005355 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005356 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005357 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005358 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005359 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005360 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005361 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005362 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005363 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005364 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005365 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005366 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005367 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005368 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005369 },
5370
5371 [MV88E6351] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005372 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005373 .family = MV88E6XXX_FAMILY_6351,
5374 .name = "Marvell 88E6351",
5375 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005376 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005377 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005378 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005379 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005380 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005381 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005382 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005383 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005384 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005385 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005386 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005387 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005388 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005389 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005390 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005391 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005392 },
5393
5394 [MV88E6352] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005395 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005396 .family = MV88E6XXX_FAMILY_6352,
5397 .name = "Marvell 88E6352",
5398 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005399 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005400 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005401 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005402 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005403 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005404 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005405 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005406 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005407 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005408 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005409 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005410 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005411 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005412 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005413 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005414 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005415 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005416 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005417 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005418 [MV88E6390] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005419 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005420 .family = MV88E6XXX_FAMILY_6390,
5421 .name = "Marvell 88E6390",
5422 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005423 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005424 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005425 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005426 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005427 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005428 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005429 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005430 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005431 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005432 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005433 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005434 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005435 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005436 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005437 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005438 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005439 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005440 .ops = &mv88e6390_ops,
5441 },
5442 [MV88E6390X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005443 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005444 .family = MV88E6XXX_FAMILY_6390,
5445 .name = "Marvell 88E6390X",
5446 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005447 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005448 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005449 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005450 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005451 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005452 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005453 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005454 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005455 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005456 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005457 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005458 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005459 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005460 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005461 .multi_chip = true,
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005462 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005463 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005464 .ops = &mv88e6390x_ops,
5465 },
Pavana Sharmade776d02021-03-17 14:46:42 +01005466
5467 [MV88E6393X] = {
5468 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5469 .family = MV88E6XXX_FAMILY_6393,
5470 .name = "Marvell 88E6393X",
5471 .num_databases = 4096,
5472 .num_ports = 11, /* 10 + Z80 */
5473 .num_internal_phys = 9,
5474 .max_vid = 8191,
5475 .port_base_addr = 0x0,
5476 .phy_base_addr = 0x0,
5477 .global1_addr = 0x1b,
5478 .global2_addr = 0x1c,
5479 .age_time_coeff = 3750,
5480 .g1_irqs = 10,
5481 .g2_irqs = 14,
5482 .atu_move_port_mask = 0x1f,
5483 .pvt = true,
5484 .multi_chip = true,
Pavana Sharmade776d02021-03-17 14:46:42 +01005485 .ptp_support = true,
5486 .ops = &mv88e6393x_ops,
5487 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04005488};
5489
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005490static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04005491{
Vivien Didelota439c062016-04-17 13:23:58 -04005492 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04005493
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005494 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5495 if (mv88e6xxx_table[i].prod_num == prod_num)
5496 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04005497
Vivien Didelotb9b37712015-10-30 19:39:48 -04005498 return NULL;
5499}
5500
Vivien Didelotfad09c72016-06-21 12:28:20 -04005501static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005502{
5503 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005504 unsigned int prod_num, rev;
5505 u16 id;
5506 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005507
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005508 mv88e6xxx_reg_lock(chip);
Vivien Didelot107fcc12017-06-12 12:37:36 -04005509 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005510 mv88e6xxx_reg_unlock(chip);
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005511 if (err)
5512 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005513
Vivien Didelot107fcc12017-06-12 12:37:36 -04005514 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5515 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005516
5517 info = mv88e6xxx_lookup_info(prod_num);
5518 if (!info)
5519 return -ENODEV;
5520
Vivien Didelotcaac8542016-06-20 13:14:09 -04005521 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04005522 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005523
Vivien Didelotfad09c72016-06-21 12:28:20 -04005524 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5525 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005526
5527 return 0;
5528}
5529
Vivien Didelotfad09c72016-06-21 12:28:20 -04005530static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04005531{
Vivien Didelotfad09c72016-06-21 12:28:20 -04005532 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005533
Vivien Didelotfad09c72016-06-21 12:28:20 -04005534 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5535 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04005536 return NULL;
5537
Vivien Didelotfad09c72016-06-21 12:28:20 -04005538 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04005539
Vivien Didelotfad09c72016-06-21 12:28:20 -04005540 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01005541 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelotda7dc872019-09-07 16:00:49 -04005542 idr_init(&chip->policies);
Vivien Didelot469d7292016-06-20 13:14:06 -04005543
Vivien Didelotfad09c72016-06-21 12:28:20 -04005544 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005545}
5546
Florian Fainelli5ed4e3e2017-11-10 15:22:52 -08005547static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
Florian Fainelli4d776482020-01-07 21:06:05 -08005548 int port,
5549 enum dsa_tag_protocol m)
Andrew Lunn7b314362016-08-22 16:01:01 +02005550{
Vivien Didelot04bed142016-08-31 18:06:13 -04005551 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02005552
Tobias Waldekranz670bb802021-04-20 20:53:07 +02005553 return chip->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02005554}
5555
Tobias Waldekranz9a99bef2021-04-20 20:53:08 +02005556static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5557 enum dsa_tag_protocol proto)
5558{
5559 struct mv88e6xxx_chip *chip = ds->priv;
5560 enum dsa_tag_protocol old_protocol;
5561 int err;
5562
5563 switch (proto) {
5564 case DSA_TAG_PROTO_EDSA:
5565 switch (chip->info->edsa_support) {
5566 case MV88E6XXX_EDSA_UNSUPPORTED:
5567 return -EPROTONOSUPPORT;
5568 case MV88E6XXX_EDSA_UNDOCUMENTED:
5569 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5570 fallthrough;
5571 case MV88E6XXX_EDSA_SUPPORTED:
5572 break;
5573 }
5574 break;
5575 case DSA_TAG_PROTO_DSA:
5576 break;
5577 default:
5578 return -EPROTONOSUPPORT;
5579 }
5580
5581 old_protocol = chip->tag_protocol;
5582 chip->tag_protocol = proto;
5583
5584 mv88e6xxx_reg_lock(chip);
5585 err = mv88e6xxx_setup_port_mode(chip, port);
5586 mv88e6xxx_reg_unlock(chip);
5587
5588 if (err)
5589 chip->tag_protocol = old_protocol;
5590
5591 return err;
5592}
5593
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005594static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5595 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005596{
Vivien Didelot04bed142016-08-31 18:06:13 -04005597 struct mv88e6xxx_chip *chip = ds->priv;
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005598 int err;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005599
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005600 mv88e6xxx_reg_lock(chip);
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005601 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5602 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005603 mv88e6xxx_reg_unlock(chip);
Vladimir Olteana52b2da2021-01-09 02:01:52 +02005604
5605 return err;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005606}
5607
5608static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5609 const struct switchdev_obj_port_mdb *mdb)
5610{
Vivien Didelot04bed142016-08-31 18:06:13 -04005611 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005612 int err;
5613
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005614 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04005615 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005616 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005617
5618 return err;
5619}
5620
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005621static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5622 struct dsa_mall_mirror_tc_entry *mirror,
5623 bool ingress)
5624{
5625 enum mv88e6xxx_egress_direction direction = ingress ?
5626 MV88E6XXX_EGRESS_DIR_INGRESS :
5627 MV88E6XXX_EGRESS_DIR_EGRESS;
5628 struct mv88e6xxx_chip *chip = ds->priv;
5629 bool other_mirrors = false;
5630 int i;
5631 int err;
5632
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005633 mutex_lock(&chip->reg_lock);
5634 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5635 mirror->to_local_port) {
5636 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5637 other_mirrors |= ingress ?
5638 chip->ports[i].mirror_ingress :
5639 chip->ports[i].mirror_egress;
5640
5641 /* Can't change egress port when other mirror is active */
5642 if (other_mirrors) {
5643 err = -EBUSY;
5644 goto out;
5645 }
5646
Marek Behún2fda45f2021-03-17 14:46:41 +01005647 err = mv88e6xxx_set_egress_port(chip, direction,
5648 mirror->to_local_port);
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005649 if (err)
5650 goto out;
5651 }
5652
5653 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5654out:
5655 mutex_unlock(&chip->reg_lock);
5656
5657 return err;
5658}
5659
5660static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5661 struct dsa_mall_mirror_tc_entry *mirror)
5662{
5663 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5664 MV88E6XXX_EGRESS_DIR_INGRESS :
5665 MV88E6XXX_EGRESS_DIR_EGRESS;
5666 struct mv88e6xxx_chip *chip = ds->priv;
5667 bool other_mirrors = false;
5668 int i;
5669
5670 mutex_lock(&chip->reg_lock);
5671 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5672 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5673
5674 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5675 other_mirrors |= mirror->ingress ?
5676 chip->ports[i].mirror_ingress :
5677 chip->ports[i].mirror_egress;
5678
5679 /* Reset egress port when no other mirror is active */
5680 if (!other_mirrors) {
Marek Behún2fda45f2021-03-17 14:46:41 +01005681 if (mv88e6xxx_set_egress_port(chip, direction,
5682 dsa_upstream_port(ds, port)))
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005683 dev_err(ds->dev, "failed to set egress port\n");
5684 }
5685
5686 mutex_unlock(&chip->reg_lock);
5687}
5688
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005689static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5690 struct switchdev_brport_flags flags,
5691 struct netlink_ext_ack *extack)
5692{
5693 struct mv88e6xxx_chip *chip = ds->priv;
5694 const struct mv88e6xxx_ops *ops;
5695
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01005696 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5697 BR_BCAST_FLOOD))
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005698 return -EINVAL;
5699
5700 ops = chip->info->ops;
5701
5702 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5703 return -EINVAL;
5704
5705 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5706 return -EINVAL;
5707
5708 return 0;
5709}
5710
5711static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5712 struct switchdev_brport_flags flags,
5713 struct netlink_ext_ack *extack)
Russell King4f859012019-02-20 15:35:05 -08005714{
5715 struct mv88e6xxx_chip *chip = ds->priv;
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005716 bool do_fast_age = false;
Russell King4f859012019-02-20 15:35:05 -08005717 int err = -EOPNOTSUPP;
5718
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005719 mv88e6xxx_reg_lock(chip);
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005720
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005721 if (flags.mask & BR_LEARNING) {
5722 bool learning = !!(flags.val & BR_LEARNING);
5723 u16 pav = learning ? (1 << port) : 0;
5724
5725 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5726 if (err)
5727 goto out;
5728
5729 if (!learning)
5730 do_fast_age = true;
5731 }
5732
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005733 if (flags.mask & BR_FLOOD) {
5734 bool unicast = !!(flags.val & BR_FLOOD);
5735
5736 err = chip->info->ops->port_set_ucast_flood(chip, port,
5737 unicast);
5738 if (err)
5739 goto out;
5740 }
5741
5742 if (flags.mask & BR_MCAST_FLOOD) {
5743 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5744
5745 err = chip->info->ops->port_set_mcast_flood(chip, port,
5746 multicast);
5747 if (err)
5748 goto out;
5749 }
5750
Tobias Waldekranz8d1d8292021-03-18 20:25:40 +01005751 if (flags.mask & BR_BCAST_FLOOD) {
5752 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5753
5754 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5755 if (err)
5756 goto out;
5757 }
5758
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005759out:
5760 mv88e6xxx_reg_unlock(chip);
5761
Tobias Waldekranz041bd542021-03-18 20:25:39 +01005762 if (do_fast_age)
5763 mv88e6xxx_port_fast_age(ds, port);
5764
Vladimir Olteana8b659e2021-02-12 17:15:56 +02005765 return err;
5766}
5767
5768static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port,
5769 bool mrouter,
5770 struct netlink_ext_ack *extack)
5771{
5772 struct mv88e6xxx_chip *chip = ds->priv;
5773 int err;
5774
5775 if (!chip->info->ops->port_set_mcast_flood)
5776 return -EOPNOTSUPP;
5777
5778 mv88e6xxx_reg_lock(chip);
5779 err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005780 mv88e6xxx_reg_unlock(chip);
Russell King4f859012019-02-20 15:35:05 -08005781
5782 return err;
5783}
5784
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005785static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5786 struct net_device *lag,
5787 struct netdev_lag_upper_info *info)
5788{
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01005789 struct mv88e6xxx_chip *chip = ds->priv;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005790 struct dsa_port *dp;
5791 int id, members = 0;
5792
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01005793 if (!mv88e6xxx_has_lag(chip))
5794 return false;
5795
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01005796 id = dsa_lag_id(ds->dst, lag);
5797 if (id < 0 || id >= ds->num_lag_ids)
5798 return false;
5799
5800 dsa_lag_foreach_port(dp, ds->dst, lag)
5801 /* Includes the port joining the LAG */
5802 members++;
5803
5804 if (members > 8)
5805 return false;
5806
5807 /* We could potentially relax this to include active
5808 * backup in the future.
5809 */
5810 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5811 return false;
5812
5813 /* Ideally we would also validate that the hash type matches
5814 * the hardware. Alas, this is always set to unknown on team
5815 * interfaces.
5816 */
5817 return true;
5818}
5819
5820static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5821{
5822 struct mv88e6xxx_chip *chip = ds->priv;
5823 struct dsa_port *dp;
5824 u16 map = 0;
5825 int id;
5826
5827 id = dsa_lag_id(ds->dst, lag);
5828
5829 /* Build the map of all ports to distribute flows destined for
5830 * this LAG. This can be either a local user port, or a DSA
5831 * port if the LAG port is on a remote chip.
5832 */
5833 dsa_lag_foreach_port(dp, ds->dst, lag)
5834 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5835
5836 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5837}
5838
5839static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5840 /* Row number corresponds to the number of active members in a
5841 * LAG. Each column states which of the eight hash buckets are
5842 * mapped to the column:th port in the LAG.
5843 *
5844 * Example: In a LAG with three active ports, the second port
5845 * ([2][1]) would be selected for traffic mapped to buckets
5846 * 3,4,5 (0x38).
5847 */
5848 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
5849 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
5850 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
5851 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
5852 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
5853 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
5854 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
5855 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5856};
5857
5858static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
5859 int num_tx, int nth)
5860{
5861 u8 active = 0;
5862 int i;
5863
5864 num_tx = num_tx <= 8 ? num_tx : 8;
5865 if (nth < num_tx)
5866 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
5867
5868 for (i = 0; i < 8; i++) {
5869 if (BIT(i) & active)
5870 mask[i] |= BIT(port);
5871 }
5872}
5873
5874static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
5875{
5876 struct mv88e6xxx_chip *chip = ds->priv;
5877 unsigned int id, num_tx;
5878 struct net_device *lag;
5879 struct dsa_port *dp;
5880 int i, err, nth;
5881 u16 mask[8];
5882 u16 ivec;
5883
5884 /* Assume no port is a member of any LAG. */
5885 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
5886
5887 /* Disable all masks for ports that _are_ members of a LAG. */
5888 list_for_each_entry(dp, &ds->dst->ports, list) {
5889 if (!dp->lag_dev || dp->ds != ds)
5890 continue;
5891
5892 ivec &= ~BIT(dp->index);
5893 }
5894
5895 for (i = 0; i < 8; i++)
5896 mask[i] = ivec;
5897
5898 /* Enable the correct subset of masks for all LAG ports that
5899 * are in the Tx set.
5900 */
5901 dsa_lags_foreach_id(id, ds->dst) {
5902 lag = dsa_lag_dev(ds->dst, id);
5903 if (!lag)
5904 continue;
5905
5906 num_tx = 0;
5907 dsa_lag_foreach_port(dp, ds->dst, lag) {
5908 if (dp->lag_tx_enabled)
5909 num_tx++;
5910 }
5911
5912 if (!num_tx)
5913 continue;
5914
5915 nth = 0;
5916 dsa_lag_foreach_port(dp, ds->dst, lag) {
5917 if (!dp->lag_tx_enabled)
5918 continue;
5919
5920 if (dp->ds == ds)
5921 mv88e6xxx_lag_set_port_mask(mask, dp->index,
5922 num_tx, nth);
5923
5924 nth++;
5925 }
5926 }
5927
5928 for (i = 0; i < 8; i++) {
5929 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
5930 if (err)
5931 return err;
5932 }
5933
5934 return 0;
5935}
5936
5937static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
5938 struct net_device *lag)
5939{
5940 int err;
5941
5942 err = mv88e6xxx_lag_sync_masks(ds);
5943
5944 if (!err)
5945 err = mv88e6xxx_lag_sync_map(ds, lag);
5946
5947 return err;
5948}
5949
5950static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
5951{
5952 struct mv88e6xxx_chip *chip = ds->priv;
5953 int err;
5954
5955 mv88e6xxx_reg_lock(chip);
5956 err = mv88e6xxx_lag_sync_masks(ds);
5957 mv88e6xxx_reg_unlock(chip);
5958 return err;
5959}
5960
5961static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
5962 struct net_device *lag,
5963 struct netdev_lag_upper_info *info)
5964{
5965 struct mv88e6xxx_chip *chip = ds->priv;
5966 int err, id;
5967
5968 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
5969 return -EOPNOTSUPP;
5970
5971 id = dsa_lag_id(ds->dst, lag);
5972
5973 mv88e6xxx_reg_lock(chip);
5974
5975 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
5976 if (err)
5977 goto err_unlock;
5978
5979 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
5980 if (err)
5981 goto err_clear_trunk;
5982
5983 mv88e6xxx_reg_unlock(chip);
5984 return 0;
5985
5986err_clear_trunk:
5987 mv88e6xxx_port_set_trunk(chip, port, false, 0);
5988err_unlock:
5989 mv88e6xxx_reg_unlock(chip);
5990 return err;
5991}
5992
5993static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
5994 struct net_device *lag)
5995{
5996 struct mv88e6xxx_chip *chip = ds->priv;
5997 int err_sync, err_trunk;
5998
5999 mv88e6xxx_reg_lock(chip);
6000 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6001 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6002 mv88e6xxx_reg_unlock(chip);
6003 return err_sync ? : err_trunk;
6004}
6005
6006static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6007 int port)
6008{
6009 struct mv88e6xxx_chip *chip = ds->priv;
6010 int err;
6011
6012 mv88e6xxx_reg_lock(chip);
6013 err = mv88e6xxx_lag_sync_masks(ds);
6014 mv88e6xxx_reg_unlock(chip);
6015 return err;
6016}
6017
6018static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6019 int port, struct net_device *lag,
6020 struct netdev_lag_upper_info *info)
6021{
6022 struct mv88e6xxx_chip *chip = ds->priv;
6023 int err;
6024
6025 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6026 return -EOPNOTSUPP;
6027
6028 mv88e6xxx_reg_lock(chip);
6029
6030 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6031 if (err)
6032 goto unlock;
6033
6034 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6035
6036unlock:
6037 mv88e6xxx_reg_unlock(chip);
6038 return err;
6039}
6040
6041static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6042 int port, struct net_device *lag)
6043{
6044 struct mv88e6xxx_chip *chip = ds->priv;
6045 int err_sync, err_pvt;
6046
6047 mv88e6xxx_reg_lock(chip);
6048 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6049 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6050 mv88e6xxx_reg_unlock(chip);
6051 return err_sync ? : err_pvt;
6052}
6053
Florian Fainellia82f67a2017-01-08 14:52:08 -08006054static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunn7b314362016-08-22 16:01:01 +02006055 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Tobias Waldekranz9a99bef2021-04-20 20:53:08 +02006056 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006057 .setup = mv88e6xxx_setup,
Andrew Lunn23e8b472019-10-25 01:03:52 +02006058 .teardown = mv88e6xxx_teardown,
Russell Kingc9a23562018-05-10 13:17:35 -07006059 .phylink_validate = mv88e6xxx_validate,
Russell Kinga5a68582020-03-14 10:15:43 +00006060 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
Russell Kingc9a23562018-05-10 13:17:35 -07006061 .phylink_mac_config = mv88e6xxx_mac_config,
Russell Kinga5a68582020-03-14 10:15:43 +00006062 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
Russell Kingc9a23562018-05-10 13:17:35 -07006063 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6064 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006065 .get_strings = mv88e6xxx_get_strings,
6066 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6067 .get_sset_count = mv88e6xxx_get_sset_count,
Andrew Lunn04aca992017-05-26 01:03:24 +02006068 .port_enable = mv88e6xxx_port_enable,
6069 .port_disable = mv88e6xxx_port_disable,
Andrew Lunn2a550ae2020-07-11 22:32:05 +02006070 .port_max_mtu = mv88e6xxx_get_max_mtu,
6071 .port_change_mtu = mv88e6xxx_change_mtu,
Vivien Didelot08f50062017-08-01 16:32:41 -04006072 .get_mac_eee = mv88e6xxx_get_mac_eee,
6073 .set_mac_eee = mv88e6xxx_set_mac_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006074 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006075 .get_eeprom = mv88e6xxx_get_eeprom,
6076 .set_eeprom = mv88e6xxx_set_eeprom,
6077 .get_regs_len = mv88e6xxx_get_regs_len,
6078 .get_regs = mv88e6xxx_get_regs,
Vivien Didelotda7dc872019-09-07 16:00:49 -04006079 .get_rxnfc = mv88e6xxx_get_rxnfc,
6080 .set_rxnfc = mv88e6xxx_set_rxnfc,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04006081 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006082 .port_bridge_join = mv88e6xxx_port_bridge_join,
6083 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
Vladimir Olteana8b659e2021-02-12 17:15:56 +02006084 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6085 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6086 .port_set_mrouter = mv88e6xxx_port_set_mrouter,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006087 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04006088 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006089 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006090 .port_vlan_add = mv88e6xxx_port_vlan_add,
6091 .port_vlan_del = mv88e6xxx_port_vlan_del,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006092 .port_fdb_add = mv88e6xxx_port_fdb_add,
6093 .port_fdb_del = mv88e6xxx_port_fdb_del,
6094 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04006095 .port_mdb_add = mv88e6xxx_port_mdb_add,
6096 .port_mdb_del = mv88e6xxx_port_mdb_del,
Iwan R Timmerf0942e02019-11-07 22:11:14 +01006097 .port_mirror_add = mv88e6xxx_port_mirror_add,
6098 .port_mirror_del = mv88e6xxx_port_mirror_del,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04006099 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6100 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006101 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6102 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6103 .port_txtstamp = mv88e6xxx_port_txtstamp,
6104 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6105 .get_ts_info = mv88e6xxx_get_ts_info,
Andrew Lunn23e8b472019-10-25 01:03:52 +02006106 .devlink_param_get = mv88e6xxx_devlink_param_get,
6107 .devlink_param_set = mv88e6xxx_devlink_param_set,
Andrew Lunn93157302020-09-18 21:11:09 +02006108 .devlink_info_get = mv88e6xxx_devlink_info_get,
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006109 .port_lag_change = mv88e6xxx_port_lag_change,
6110 .port_lag_join = mv88e6xxx_port_lag_join,
6111 .port_lag_leave = mv88e6xxx_port_lag_leave,
6112 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6113 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6114 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
Vivien Didelotf81ec902016-05-09 13:22:58 -04006115};
6116
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08006117static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006118{
Vivien Didelotfad09c72016-06-21 12:28:20 -04006119 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006120 struct dsa_switch *ds;
6121
Vivien Didelot7e99e342019-10-21 16:51:30 -04006122 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006123 if (!ds)
6124 return -ENOMEM;
6125
Vivien Didelot7e99e342019-10-21 16:51:30 -04006126 ds->dev = dev;
6127 ds->num_ports = mv88e6xxx_num_ports(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04006128 ds->priv = chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006129 ds->dev = dev;
Vivien Didelot9d490b42016-08-23 12:38:56 -04006130 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelot9ff74f22017-03-15 15:53:50 -04006131 ds->ageing_time_min = chip->info->age_time_coeff;
6132 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006133
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006134 /* Some chips support up to 32, but that requires enabling the
6135 * 5-bit port mode, which we do not support. 640k^W16 ought to
6136 * be enough for anyone.
6137 */
Tobias Waldekranzb80dc512021-01-15 13:52:59 +01006138 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
Tobias Waldekranz57e661a2021-01-13 09:42:54 +01006139
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006140 dev_set_drvdata(dev, ds);
6141
Vivien Didelot23c9ee42017-05-26 18:12:51 -04006142 return dsa_register_switch(ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006143}
6144
Vivien Didelotfad09c72016-06-21 12:28:20 -04006145static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006146{
Vivien Didelotfad09c72016-06-21 12:28:20 -04006147 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04006148}
6149
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006150static const void *pdata_device_get_match_data(struct device *dev)
6151{
6152 const struct of_device_id *matches = dev->driver->of_match_table;
6153 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6154
6155 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6156 matches++) {
6157 if (!strcmp(pdata->compatible, matches->compatible))
6158 return matches->data;
6159 }
6160 return NULL;
6161}
6162
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01006163/* There is no suspend to RAM support at DSA level yet, the switch configuration
6164 * would be lost after a power cycle so prevent it to be suspended.
6165 */
6166static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6167{
6168 return -EOPNOTSUPP;
6169}
6170
6171static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6172{
6173 return 0;
6174}
6175
6176static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6177
Vivien Didelot57d32312016-06-20 13:13:58 -04006178static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006179{
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006180 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
David S. Miller7ddae242018-05-20 19:04:24 -04006181 const struct mv88e6xxx_info *compat_info = NULL;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006182 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006183 struct device_node *np = dev->of_node;
Vivien Didelotfad09c72016-06-21 12:28:20 -04006184 struct mv88e6xxx_chip *chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006185 int port;
Andrew Lunn52638f72016-05-10 23:27:22 +02006186 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006187
Andrew Lunn7bb8c992018-05-31 00:15:42 +02006188 if (!np && !pdata)
6189 return -EINVAL;
6190
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006191 if (np)
6192 compat_info = of_device_get_match_data(dev);
6193
6194 if (pdata) {
6195 compat_info = pdata_device_get_match_data(dev);
6196
6197 if (!pdata->netdev)
6198 return -EINVAL;
6199
6200 for (port = 0; port < DSA_MAX_PORTS; port++) {
6201 if (!(pdata->enabled_ports & (1 << port)))
6202 continue;
6203 if (strcmp(pdata->cd.port_names[port], "cpu"))
6204 continue;
6205 pdata->cd.netdev[port] = &pdata->netdev->dev;
6206 break;
6207 }
6208 }
6209
Vivien Didelotcaac8542016-06-20 13:14:09 -04006210 if (!compat_info)
6211 return -EINVAL;
6212
Vivien Didelotfad09c72016-06-21 12:28:20 -04006213 chip = mv88e6xxx_alloc_chip(dev);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006214 if (!chip) {
6215 err = -ENOMEM;
6216 goto out;
6217 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006218
Vivien Didelotfad09c72016-06-21 12:28:20 -04006219 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04006220
Vivien Didelotfad09c72016-06-21 12:28:20 -04006221 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04006222 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006223 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006224
Andrew Lunnb4308f02016-11-21 23:26:55 +01006225 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006226 if (IS_ERR(chip->reset)) {
6227 err = PTR_ERR(chip->reset);
6228 goto out;
6229 }
Baruch Siach7b75e492019-06-27 21:17:39 +03006230 if (chip->reset)
6231 usleep_range(1000, 2000);
Andrew Lunnb4308f02016-11-21 23:26:55 +01006232
Vivien Didelotfad09c72016-06-21 12:28:20 -04006233 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04006234 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006235 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006236
Tobias Waldekranz670bb802021-04-20 20:53:07 +02006237 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6238 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6239 else
6240 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6241
Vivien Didelote57e5e72016-08-15 17:19:00 -04006242 mv88e6xxx_phy_init(chip);
6243
Andrew Lunn00baabe2018-05-19 22:31:35 +02006244 if (chip->info->ops->get_eeprom) {
6245 if (np)
6246 of_property_read_u32(np, "eeprom-length",
6247 &chip->eeprom_len);
6248 else
6249 chip->eeprom_len = pdata->eeprom_len;
6250 }
Andrew Lunnf8cd8752016-05-10 23:27:25 +02006251
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006252 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006253 err = mv88e6xxx_switch_reset(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006254 mv88e6xxx_reg_unlock(chip);
Andrew Lunnb516d452016-06-04 21:17:06 +02006255 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02006256 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02006257
Andrew Lunna27415d2019-05-01 00:10:50 +02006258 if (np) {
6259 chip->irq = of_irq_get(np, 0);
6260 if (chip->irq == -EPROBE_DEFER) {
6261 err = chip->irq;
6262 goto out;
6263 }
Andrew Lunn83c0afa2016-06-04 21:17:07 +02006264 }
6265
Andrew Lunna27415d2019-05-01 00:10:50 +02006266 if (pdata)
6267 chip->irq = pdata->irq;
6268
Andrew Lunn294d7112018-02-22 22:58:32 +01006269 /* Has to be performed before the MDIO bus is created, because
Uwe Kleine-Königa7087672018-03-20 10:44:41 +01006270 * the PHYs will link their interrupts to these interrupt
Andrew Lunn294d7112018-02-22 22:58:32 +01006271 * controllers
6272 */
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006273 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006274 if (chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02006275 err = mv88e6xxx_g1_irq_setup(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006276 else
6277 err = mv88e6xxx_irq_poll_setup(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00006278 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006279
Andrew Lunn294d7112018-02-22 22:58:32 +01006280 if (err)
6281 goto out;
6282
6283 if (chip->info->g2_irqs > 0) {
6284 err = mv88e6xxx_g2_irq_setup(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006285 if (err)
Andrew Lunn294d7112018-02-22 22:58:32 +01006286 goto out_g1_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02006287 }
6288
Andrew Lunn294d7112018-02-22 22:58:32 +01006289 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6290 if (err)
6291 goto out_g2_irq;
6292
6293 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6294 if (err)
6295 goto out_g1_atu_prob_irq;
6296
Andrew Lunna3c53be52017-01-24 14:53:50 +01006297 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02006298 if (err)
Andrew Lunn62eb1162018-01-14 02:32:45 +01006299 goto out_g1_vtu_prob_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02006300
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08006301 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006302 if (err)
6303 goto out_mdio;
6304
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006305 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02006306
6307out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01006308 mv88e6xxx_mdios_unregister(chip);
Andrew Lunn62eb1162018-01-14 02:32:45 +01006309out_g1_vtu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006310 mv88e6xxx_g1_vtu_prob_irq_free(chip);
Andrew Lunn09776442018-01-14 02:32:44 +01006311out_g1_atu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006312 mv88e6xxx_g1_atu_prob_irq_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006313out_g2_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006314 if (chip->info->g2_irqs > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02006315 mv88e6xxx_g2_irq_free(chip);
6316out_g1_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01006317 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01006318 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01006319 else
6320 mv88e6xxx_irq_poll_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006321out:
Andrew Lunn877b7cb2018-05-19 22:31:34 +02006322 if (pdata)
6323 dev_put(pdata->netdev);
6324
Andrew Lunndc30c352016-10-16 19:56:49 +02006325 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006326}
6327
6328static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6329{
6330 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vivien Didelot04bed142016-08-31 18:06:13 -04006331 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006332
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006333 if (chip->info->ptp_support) {
6334 mv88e6xxx_hwtstamp_free(chip);
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01006335 mv88e6xxx_ptp_free(chip);
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01006336 }
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01006337
Andrew Lunn930188c2016-08-22 16:01:03 +02006338 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04006339 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01006340 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02006341
Andrew Lunn76f38f12018-03-17 20:21:09 +01006342 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6343 mv88e6xxx_g1_atu_prob_irq_free(chip);
6344
6345 if (chip->info->g2_irqs > 0)
6346 mv88e6xxx_g2_irq_free(chip);
6347
Andrew Lunn76f38f12018-03-17 20:21:09 +01006348 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01006349 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn76f38f12018-03-17 20:21:09 +01006350 else
6351 mv88e6xxx_irq_poll_free(chip);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006352}
6353
6354static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04006355 {
6356 .compatible = "marvell,mv88e6085",
6357 .data = &mv88e6xxx_table[MV88E6085],
6358 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01006359 {
6360 .compatible = "marvell,mv88e6190",
6361 .data = &mv88e6xxx_table[MV88E6190],
6362 },
Rasmus Villemoes1f718362019-06-04 07:34:32 +00006363 {
6364 .compatible = "marvell,mv88e6250",
6365 .data = &mv88e6xxx_table[MV88E6250],
6366 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006367 { /* sentinel */ },
6368};
6369
6370MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6371
6372static struct mdio_driver mv88e6xxx_driver = {
6373 .probe = mv88e6xxx_probe,
6374 .remove = mv88e6xxx_remove,
6375 .mdiodrv.driver = {
6376 .name = "mv88e6085",
6377 .of_match_table = mv88e6xxx_of_match,
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01006378 .pm = &mv88e6xxx_pm_ops,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006379 },
6380};
6381
Andrew Lunn7324d502019-04-27 19:19:10 +02006382mdio_module_driver(mv88e6xxx_driver);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00006383
6384MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6385MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6386MODULE_LICENSE("GPL");