blob: bd297ae7cf9e79ec4e6339730259b972804380e4 [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00002/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04003 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00005 * Copyright (c) 2008 Marvell Semiconductor
6 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02007 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
Vivien Didelot4333d612017-03-28 15:10:36 -04009 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 */
12
Vivien Didelot19fb7f62019-08-09 18:47:55 -040013#include <linux/bitfield.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000014#include <linux/delay.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070015#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020016#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070017#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020018#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000021#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000022#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020023#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000024#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040025#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020026#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020027#include <linux/of_mdio.h>
Andrew Lunn877b7cb2018-05-19 22:31:34 +020028#include <linux/platform_data/mv88e6xxx.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000029#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010030#include <linux/gpio/consumer.h>
Russell Kingc9a23562018-05-10 13:17:35 -070031#include <linux/phylink.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000032#include <net/dsa.h>
Vivien Didelotec561272016-09-02 14:45:33 -040033
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -040034#include "chip.h"
Andrew Lunn9dd43aa2020-09-18 21:11:05 +020035#include "devlink.h"
Vivien Didelota935c052016-09-29 12:21:53 -040036#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040037#include "global2.h"
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +010038#include "hwtstamp.h"
Andrew Lunn10fa5bf2017-05-26 01:03:20 +020039#include "phy.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010040#include "port.h"
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +010041#include "ptp.h"
Andrew Lunn6d917822017-05-26 01:03:21 +020042#include "serdes.h"
Vivien Didelote7ba0fa2019-05-03 19:28:22 -040043#include "smi.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000044
Vivien Didelotfad09c72016-06-21 12:28:20 -040045static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040046{
Vivien Didelotfad09c72016-06-21 12:28:20 -040047 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040049 dump_stack();
50 }
51}
52
Vivien Didelotec561272016-09-02 14:45:33 -040053int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040054{
55 int err;
56
Vivien Didelotfad09c72016-06-21 12:28:20 -040057 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040058
Vivien Didelotfad09c72016-06-21 12:28:20 -040059 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040060 if (err)
61 return err;
62
Vivien Didelotfad09c72016-06-21 12:28:20 -040063 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040064 addr, reg, *val);
65
66 return 0;
67}
68
Vivien Didelotec561272016-09-02 14:45:33 -040069int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -040070{
71 int err;
72
Vivien Didelotfad09c72016-06-21 12:28:20 -040073 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -040074
Vivien Didelotfad09c72016-06-21 12:28:20 -040075 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040076 if (err)
77 return err;
78
Vivien Didelotfad09c72016-06-21 12:28:20 -040079 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -040080 addr, reg, val);
81
82 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000083}
84
Vivien Didelot683f2242019-08-09 18:47:54 -040085int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87{
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106}
107
Vivien Didelot19fb7f62019-08-09 18:47:55 -0400108int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110{
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113}
114
Andrew Lunn10fa5bf2017-05-26 01:03:20 +0200115struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
Andrew Lunna3c53be52017-01-24 14:53:50 +0100116{
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125}
126
Andrew Lunndc30c352016-10-16 19:56:49 +0200127static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128{
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133}
134
135static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136{
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141}
142
Andrew Lunn294d7112018-02-22 22:58:32 +0100143static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200144{
Andrew Lunndc30c352016-10-16 19:56:49 +0200145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
John David Anglin7c0db242019-02-11 13:40:21 -0500149 u16 ctl1;
Andrew Lunndc30c352016-10-16 19:56:49 +0200150 int err;
151
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000152 mv88e6xxx_reg_lock(chip);
Vivien Didelot82466922017-06-15 12:13:59 -0400153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000154 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200155
156 if (err)
157 goto out;
158
John David Anglin7c0db242019-02-11 13:40:21 -0500159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
Andrew Lunndc30c352016-10-16 19:56:49 +0200167 }
John David Anglin7c0db242019-02-11 13:40:21 -0500168
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000169 mv88e6xxx_reg_lock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
174unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000175 mv88e6xxx_reg_unlock(chip);
John David Anglin7c0db242019-02-11 13:40:21 -0500176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
Andrew Lunndc30c352016-10-16 19:56:49 +0200181out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183}
184
Andrew Lunn294d7112018-02-22 22:58:32 +0100185static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186{
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190}
191
Andrew Lunndc30c352016-10-16 19:56:49 +0200192static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193{
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000196 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200197}
198
199static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200{
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
Vivien Didelotd77f4322017-06-15 12:14:03 -0400206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
Vivien Didelotd77f4322017-06-15 12:14:03 -0400213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200214 if (err)
215 goto out;
216
217out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000218 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200219}
220
Bhumika Goyal6eb15e22017-08-19 16:25:52 +0530221static const struct irq_chip mv88e6xxx_g1_irq_chip = {
Andrew Lunndc30c352016-10-16 19:56:49 +0200222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227};
228
229static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232{
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240}
241
242static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245};
246
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200247/* To be called with reg_lock held */
Andrew Lunn294d7112018-02-22 22:58:32 +0100248static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200249{
250 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100251 u16 mask;
252
Vivien Didelotd77f4322017-06-15 12:14:03 -0400253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3460a572016-11-20 20:14:16 +0100256
Andreas Färber5edef2f2016-11-27 23:26:28 +0100257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200259 irq_dispose_mapping(virq);
260 }
261
Andrew Lunna3db3d32016-11-20 20:14:14 +0100262 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200263}
264
Andrew Lunn294d7112018-02-22 22:58:32 +0100265static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266{
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
Andrew Lunn294d7112018-02-22 22:58:32 +0100271 free_irq(chip->irq, chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200272
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000273 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200274 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000275 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100276}
277
278static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
Andrew Lunndc30c352016-10-16 19:56:49 +0200279{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100280 int err, irq, virq;
281 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
Vivien Didelotd77f4322017-06-15 12:14:03 -0400296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200297 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100298 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200299
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200301
Vivien Didelotd77f4322017-06-15 12:14:03 -0400302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200303 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100304 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200305
306 /* Reading the interrupt status clears (most of) them */
Vivien Didelot82466922017-06-15 12:13:59 -0400307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
Andrew Lunndc30c352016-10-16 19:56:49 +0200308 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100309 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200310
Andrew Lunndc30c352016-10-16 19:56:49 +0200311 return 0;
312
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100313out_disable:
Andrew Lunn3d5fdba2017-12-07 01:05:56 +0100314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Vivien Didelotd77f4322017-06-15 12:14:03 -0400315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100316
317out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200324
325 return err;
326}
327
Andrew Lunn294d7112018-02-22 22:58:32 +0100328static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329{
Andrew Lunnf6d97582019-02-23 17:43:56 +0100330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
Andrew Lunn294d7112018-02-22 22:58:32 +0100332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
Andrew Lunnf6d97582019-02-23 17:43:56 +0100338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
Andrew Lunn30953832020-01-06 17:13:48 +0100344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000347 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
Marek Behún03403762018-08-30 02:13:50 +0200350 IRQF_ONESHOT | IRQF_SHARED,
Andrew Lunn30953832020-01-06 17:13:48 +0100351 chip->irq_name, chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000352 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357}
358
359static void mv88e6xxx_irq_poll(struct kthread_work *work)
360{
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368}
369
370static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371{
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
Florian Fainelli3f8b8692019-02-21 20:09:27 -0800381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
Andrew Lunn294d7112018-02-22 22:58:32 +0100382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389}
390
391static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392{
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200395
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000396 mv88e6xxx_reg_lock(chip);
Uwe Kleine-König3d824752018-07-20 11:53:15 +0200397 mv88e6xxx_g1_irq_free_common(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000398 mv88e6xxx_reg_unlock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +0100399}
400
Russell King64d47d52020-03-14 10:15:38 +0000401static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403{
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421}
422
Russell Kinga5a68582020-03-14 10:15:43 +0000423static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
Vivien Didelotd78343d2016-11-04 03:23:36 +0100426{
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
Hubert Feurstein43c8e0a2019-07-30 12:11:42 +0200433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100434 if (err)
435 return err;
436
Russell Kingf365c6f2020-03-14 10:15:53 +0000437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
Andrew Lunn7cbbee02019-03-08 01:21:27 +0100444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
Andrew Lunn54186b92018-08-09 15:38:37 +0200447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
Russell King64d47d52020-03-14 10:15:38 +0000453 err = mv88e6xxx_port_config_interface(chip, port, mode);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100454restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
Vivien Didelot774439e52017-06-08 18:34:08 -0400456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100457
458 return err;
459}
460
Marek Vasutd700ec42018-09-12 00:15:24 +0200461static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462{
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466}
467
Russell King5d5b2312020-03-14 10:16:03 +0000468static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469{
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482}
483
Russell Kinga5a68582020-03-14 10:15:43 +0000484static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486{
487 struct mv88e6xxx_chip *chip = ds->priv;
488 u8 lane;
489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501}
502
503static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507{
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
509 u8 lane;
510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
513 if (lane)
514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519}
520
521static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522{
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
526 u8 lane;
527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
533 if (lane)
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540}
541
542static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545{
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
547 u8 lane;
548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
551 if (lane)
552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557}
558
Russell King6c422e32018-08-09 15:38:39 +0200559static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562{
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570}
571
572static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575{
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583}
584
Marek Behúne3af71a2019-02-25 12:39:55 +0100585static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588{
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597}
598
Russell King6c422e32018-08-09 15:38:39 +0200599static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602{
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608}
609
610static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613{
Andrew Lunnec260162019-02-08 22:25:44 +0100614 if (port >= 9) {
Russell King6c422e32018-08-09 15:38:39 +0200615 phylink_set(mask, 2500baseX_Full);
Andrew Lunnec260162019-02-08 22:25:44 +0100616 phylink_set(mask, 2500baseT_Full);
617 }
Russell King6c422e32018-08-09 15:38:39 +0200618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624}
625
626static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629{
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636}
637
Russell Kingc9a23562018-05-10 13:17:35 -0700638static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
639 unsigned long *supported,
640 struct phylink_link_state *state)
641{
Russell King6c422e32018-08-09 15:38:39 +0200642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
643 struct mv88e6xxx_chip *chip = ds->priv;
644
645 /* Allow all the expected bits */
646 phylink_set(mask, Autoneg);
647 phylink_set(mask, Pause);
648 phylink_set_port_modes(mask);
649
650 if (chip->info->ops->phylink_validate)
651 chip->info->ops->phylink_validate(chip, port, mask, state);
652
653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
654 bitmap_and(state->advertising, state->advertising, mask,
655 __ETHTOOL_LINK_MODE_MASK_NBITS);
656
657 /* We can only operate at 2500BaseX or 1000BaseX. If requested
658 * to advertise both, only report advertising at 2500BaseX.
659 */
660 phylink_helper_basex_speed(state);
Russell Kingc9a23562018-05-10 13:17:35 -0700661}
662
Russell Kingc9a23562018-05-10 13:17:35 -0700663static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
664 unsigned int mode,
665 const struct phylink_link_state *state)
666{
667 struct mv88e6xxx_chip *chip = ds->priv;
Russell Kingfad58192020-07-19 12:00:35 +0100668 struct mv88e6xxx_port *p;
Russell King64d47d52020-03-14 10:15:38 +0000669 int err;
Russell Kingc9a23562018-05-10 13:17:35 -0700670
Russell Kingfad58192020-07-19 12:00:35 +0100671 p = &chip->ports[port];
672
Russell King64d47d52020-03-14 10:15:38 +0000673 /* FIXME: is this the correct test? If we're in fixed mode on an
674 * internal port, why should we process this any different from
675 * PHY mode? On the other hand, the port may be automedia between
676 * an internal PHY and the serdes...
677 */
Marek Vasutd700ec42018-09-12 00:15:24 +0200678 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
Russell Kingc9a23562018-05-10 13:17:35 -0700679 return;
680
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000681 mv88e6xxx_reg_lock(chip);
Russell Kingfad58192020-07-19 12:00:35 +0100682 /* In inband mode, the link may come up at any time while the link
683 * is not forced down. Force the link down while we reconfigure the
684 * interface mode.
Russell King64d47d52020-03-14 10:15:38 +0000685 */
Russell Kingfad58192020-07-19 12:00:35 +0100686 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
687 chip->info->ops->port_set_link)
688 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
689
Russell King64d47d52020-03-14 10:15:38 +0000690 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
Russell Kinga5a68582020-03-14 10:15:43 +0000691 if (err && err != -EOPNOTSUPP)
692 goto err_unlock;
693
694 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
695 state->advertising);
696 /* FIXME: we should restart negotiation if something changed - which
697 * is something we get if we convert to using phylinks PCS operations.
698 */
699 if (err > 0)
700 err = 0;
701
Russell Kingfad58192020-07-19 12:00:35 +0100702 /* Undo the forced down state above after completing configuration
703 * irrespective of its state on entry, which allows the link to come up.
704 */
705 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
706 chip->info->ops->port_set_link)
707 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
708
709 p->interface = state->interface;
710
Russell Kinga5a68582020-03-14 10:15:43 +0000711err_unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000712 mv88e6xxx_reg_unlock(chip);
Russell Kingc9a23562018-05-10 13:17:35 -0700713
714 if (err && err != -EOPNOTSUPP)
Russell King64d47d52020-03-14 10:15:38 +0000715 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700716}
717
Russell Kingc9a23562018-05-10 13:17:35 -0700718static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
719 unsigned int mode,
720 phy_interface_t interface)
721{
Russell King30c4a5b2020-02-26 10:23:51 +0000722 struct mv88e6xxx_chip *chip = ds->priv;
723 const struct mv88e6xxx_ops *ops;
724 int err = 0;
725
726 ops = chip->info->ops;
727
Russell King5d5b2312020-03-14 10:16:03 +0000728 mv88e6xxx_reg_lock(chip);
Andrew Lunn34b5e6a2020-04-14 02:34:38 +0200729 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
730 mode == MLO_AN_FIXED) && ops->port_set_link)
Russell King30c4a5b2020-02-26 10:23:51 +0000731 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
Russell King5d5b2312020-03-14 10:16:03 +0000732 mv88e6xxx_reg_unlock(chip);
Russell King30c4a5b2020-02-26 10:23:51 +0000733
Russell King5d5b2312020-03-14 10:16:03 +0000734 if (err)
735 dev_err(chip->dev,
736 "p%d: failed to force MAC link down\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700737}
738
739static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
740 unsigned int mode, phy_interface_t interface,
Russell King5b502a72020-02-26 10:23:46 +0000741 struct phy_device *phydev,
742 int speed, int duplex,
743 bool tx_pause, bool rx_pause)
Russell Kingc9a23562018-05-10 13:17:35 -0700744{
Russell King30c4a5b2020-02-26 10:23:51 +0000745 struct mv88e6xxx_chip *chip = ds->priv;
746 const struct mv88e6xxx_ops *ops;
747 int err = 0;
748
749 ops = chip->info->ops;
750
Russell King5d5b2312020-03-14 10:16:03 +0000751 mv88e6xxx_reg_lock(chip);
Andrew Lunn34b5e6a2020-04-14 02:34:38 +0200752 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
Russell King30c4a5b2020-02-26 10:23:51 +0000753 /* FIXME: for an automedia port, should we force the link
754 * down here - what if the link comes up due to "other" media
755 * while we're bringing the port up, how is the exclusivity
Russell Kinga5a68582020-03-14 10:15:43 +0000756 * handled in the Marvell hardware? E.g. port 2 on 88E6390
Russell King30c4a5b2020-02-26 10:23:51 +0000757 * shared between internal PHY and Serdes.
758 */
Russell Kinga5a68582020-03-14 10:15:43 +0000759 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
760 duplex);
761 if (err)
762 goto error;
763
Russell Kingf365c6f2020-03-14 10:15:53 +0000764 if (ops->port_set_speed_duplex) {
765 err = ops->port_set_speed_duplex(chip, port,
766 speed, duplex);
Russell King30c4a5b2020-02-26 10:23:51 +0000767 if (err && err != -EOPNOTSUPP)
768 goto error;
769 }
770
771 if (ops->port_set_link)
772 err = ops->port_set_link(chip, port, LINK_FORCED_UP);
Russell King30c4a5b2020-02-26 10:23:51 +0000773 }
Russell King5d5b2312020-03-14 10:16:03 +0000774error:
775 mv88e6xxx_reg_unlock(chip);
776
777 if (err && err != -EOPNOTSUPP)
778 dev_err(ds->dev,
779 "p%d: failed to configure MAC link up\n", port);
Russell Kingc9a23562018-05-10 13:17:35 -0700780}
781
Andrew Lunna605a0f2016-11-21 23:26:58 +0100782static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000783{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100784 if (!chip->info->ops->stats_snapshot)
785 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000786
Andrew Lunna605a0f2016-11-21 23:26:58 +0100787 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000788}
789
Andrew Lunne413e7e2015-04-02 04:06:38 +0200790static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100791 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
792 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
793 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
794 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
795 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
796 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
797 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
798 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
799 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
800 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
801 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
802 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
803 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
804 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
805 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
806 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
807 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
808 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
809 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
810 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
811 { "single", 4, 0x14, STATS_TYPE_BANK0, },
812 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
813 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
814 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
815 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
816 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
817 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
818 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
819 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
820 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
821 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
822 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
823 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
824 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
825 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
826 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
827 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
828 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
829 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
830 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
831 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
832 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
833 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
834 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
835 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
836 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
837 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
838 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
839 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
840 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
841 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
842 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
843 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
844 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
845 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
846 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
847 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
848 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
849 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200850};
851
Vivien Didelotfad09c72016-06-21 12:28:20 -0400852static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100853 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100854 int port, u16 bank1_select,
855 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200856{
Andrew Lunn80c46272015-06-20 18:42:30 +0200857 u32 low;
858 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100859 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200860 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200861 u64 value;
862
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100863 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100864 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200865 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
866 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800867 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200868
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200869 low = reg;
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100870 if (s->size == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200871 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
872 if (err)
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800873 return U64_MAX;
Rasmus Villemoes84b3fd12019-05-29 07:02:11 +0000874 low |= ((u32)reg) << 16;
Andrew Lunn80c46272015-06-20 18:42:30 +0200875 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100876 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100877 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100878 reg = bank1_select;
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -0500879 fallthrough;
Andrew Lunndfafe442016-11-21 23:27:02 +0100880 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100881 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100882 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunncda9f4a2018-03-01 02:02:31 +0100883 if (s->size == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100884 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Gustavo A. R. Silva9fc3e4d2017-05-11 22:11:29 -0500885 break;
886 default:
Jisheng Zhang6c3442f2018-04-27 16:18:58 +0800887 return U64_MAX;
Andrew Lunn80c46272015-06-20 18:42:30 +0200888 }
Andrew Lunn6e46e2d2019-02-28 18:14:03 +0100889 value = (((u64)high) << 32) | low;
Andrew Lunn80c46272015-06-20 18:42:30 +0200890 return value;
891}
892
Andrew Lunn436fe172018-03-01 02:02:29 +0100893static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
894 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100895{
896 struct mv88e6xxx_hw_stat *stat;
897 int i, j;
898
899 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
900 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100901 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100902 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
903 ETH_GSTRING_LEN);
904 j++;
905 }
906 }
Andrew Lunn436fe172018-03-01 02:02:29 +0100907
908 return j;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100909}
910
Andrew Lunn436fe172018-03-01 02:02:29 +0100911static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
912 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100913{
Andrew Lunn436fe172018-03-01 02:02:29 +0100914 return mv88e6xxx_stats_get_strings(chip, data,
915 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
Andrew Lunndfafe442016-11-21 23:27:02 +0100916}
917
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000918static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
919 uint8_t *data)
920{
921 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
922}
923
Andrew Lunn436fe172018-03-01 02:02:29 +0100924static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
925 uint8_t *data)
Andrew Lunndfafe442016-11-21 23:27:02 +0100926{
Andrew Lunn436fe172018-03-01 02:02:29 +0100927 return mv88e6xxx_stats_get_strings(chip, data,
928 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
Andrew Lunndfafe442016-11-21 23:27:02 +0100929}
930
Andrew Lunn65f60e42018-03-28 23:50:28 +0200931static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
932 "atu_member_violation",
933 "atu_miss_violation",
934 "atu_full_violation",
935 "vtu_member_violation",
936 "vtu_miss_violation",
937};
938
939static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
940{
941 unsigned int i;
942
943 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
944 strlcpy(data + i * ETH_GSTRING_LEN,
945 mv88e6xxx_atu_vtu_stats_strings[i],
946 ETH_GSTRING_LEN);
947}
948
Andrew Lunndfafe442016-11-21 23:27:02 +0100949static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
Florian Fainelli89f09042018-04-25 12:12:50 -0700950 u32 stringset, uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100951{
Vivien Didelot04bed142016-08-31 18:06:13 -0400952 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +0100953 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100954
Florian Fainelli89f09042018-04-25 12:12:50 -0700955 if (stringset != ETH_SS_STATS)
956 return;
957
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000958 mv88e6xxx_reg_lock(chip);
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100959
Andrew Lunndfafe442016-11-21 23:27:02 +0100960 if (chip->info->ops->stats_get_strings)
Andrew Lunn436fe172018-03-01 02:02:29 +0100961 count = chip->info->ops->stats_get_strings(chip, data);
962
963 if (chip->info->ops->serdes_get_strings) {
964 data += count * ETH_GSTRING_LEN;
Andrew Lunn65f60e42018-03-28 23:50:28 +0200965 count = chip->info->ops->serdes_get_strings(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +0100966 }
Andrew Lunnc6c8cd52018-03-01 02:02:28 +0100967
Andrew Lunn65f60e42018-03-28 23:50:28 +0200968 data += count * ETH_GSTRING_LEN;
969 mv88e6xxx_atu_vtu_get_strings(data);
970
Rasmus Villemoesc9acece2019-06-20 13:50:42 +0000971 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +0100972}
973
974static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
975 int types)
976{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100977 struct mv88e6xxx_hw_stat *stat;
978 int i, j;
979
980 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
981 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100982 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100983 j++;
984 }
985 return j;
986}
987
Andrew Lunndfafe442016-11-21 23:27:02 +0100988static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
989{
990 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
991 STATS_TYPE_PORT);
992}
993
Rasmus Villemoes1f718362019-06-04 07:34:32 +0000994static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
995{
996 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
997}
998
Andrew Lunndfafe442016-11-21 23:27:02 +0100999static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1000{
1001 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1002 STATS_TYPE_BANK1);
1003}
1004
Florian Fainelli89f09042018-04-25 12:12:50 -07001005static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
Andrew Lunndfafe442016-11-21 23:27:02 +01001006{
1007 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn436fe172018-03-01 02:02:29 +01001008 int serdes_count = 0;
1009 int count = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +01001010
Florian Fainelli89f09042018-04-25 12:12:50 -07001011 if (sset != ETH_SS_STATS)
1012 return 0;
1013
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001014 mv88e6xxx_reg_lock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001015 if (chip->info->ops->stats_get_sset_count)
Andrew Lunn436fe172018-03-01 02:02:29 +01001016 count = chip->info->ops->stats_get_sset_count(chip);
1017 if (count < 0)
1018 goto out;
1019
1020 if (chip->info->ops->serdes_get_sset_count)
1021 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1022 port);
Andrew Lunn65f60e42018-03-28 23:50:28 +02001023 if (serdes_count < 0) {
Andrew Lunn436fe172018-03-01 02:02:29 +01001024 count = serdes_count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001025 goto out;
1026 }
1027 count += serdes_count;
1028 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1029
Andrew Lunn436fe172018-03-01 02:02:29 +01001030out:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001031 mv88e6xxx_reg_unlock(chip);
Andrew Lunndfafe442016-11-21 23:27:02 +01001032
Andrew Lunn436fe172018-03-01 02:02:29 +01001033 return count;
Andrew Lunndfafe442016-11-21 23:27:02 +01001034}
1035
Andrew Lunn436fe172018-03-01 02:02:29 +01001036static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1037 uint64_t *data, int types,
1038 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +01001039{
1040 struct mv88e6xxx_hw_stat *stat;
1041 int i, j;
1042
1043 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1044 stat = &mv88e6xxx_hw_stats[i];
1045 if (stat->type & types) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001046 mv88e6xxx_reg_lock(chip);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001047 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1048 bank1_select,
1049 histogram);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001050 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001051
Andrew Lunn052f9472016-11-21 23:27:03 +01001052 j++;
1053 }
1054 }
Andrew Lunn436fe172018-03-01 02:02:29 +01001055 return j;
Andrew Lunn052f9472016-11-21 23:27:03 +01001056}
1057
Andrew Lunn436fe172018-03-01 02:02:29 +01001058static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1059 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001060{
1061 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001062 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001063 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +01001064}
1065
Rasmus Villemoes1f718362019-06-04 07:34:32 +00001066static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1067 uint64_t *data)
1068{
1069 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1070 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1071}
1072
Andrew Lunn436fe172018-03-01 02:02:29 +01001073static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1074 uint64_t *data)
Andrew Lunn052f9472016-11-21 23:27:03 +01001075{
1076 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +01001077 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001078 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1079 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
Andrew Lunne0d8b612016-11-21 23:27:04 +01001080}
1081
Andrew Lunn436fe172018-03-01 02:02:29 +01001082static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1083 uint64_t *data)
Andrew Lunne0d8b612016-11-21 23:27:04 +01001084{
1085 return mv88e6xxx_stats_get_stats(chip, port, data,
1086 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
Vivien Didelot57d1ef32017-06-15 12:14:05 -04001087 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1088 0);
Andrew Lunn052f9472016-11-21 23:27:03 +01001089}
1090
Andrew Lunn65f60e42018-03-28 23:50:28 +02001091static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1092 uint64_t *data)
1093{
1094 *data++ = chip->ports[port].atu_member_violation;
1095 *data++ = chip->ports[port].atu_miss_violation;
1096 *data++ = chip->ports[port].atu_full_violation;
1097 *data++ = chip->ports[port].vtu_member_violation;
1098 *data++ = chip->ports[port].vtu_miss_violation;
1099}
1100
Andrew Lunn052f9472016-11-21 23:27:03 +01001101static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1102 uint64_t *data)
1103{
Andrew Lunn436fe172018-03-01 02:02:29 +01001104 int count = 0;
1105
Andrew Lunn052f9472016-11-21 23:27:03 +01001106 if (chip->info->ops->stats_get_stats)
Andrew Lunn436fe172018-03-01 02:02:29 +01001107 count = chip->info->ops->stats_get_stats(chip, port, data);
1108
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001109 mv88e6xxx_reg_lock(chip);
Andrew Lunn436fe172018-03-01 02:02:29 +01001110 if (chip->info->ops->serdes_get_stats) {
1111 data += count;
Andrew Lunn65f60e42018-03-28 23:50:28 +02001112 count = chip->info->ops->serdes_get_stats(chip, port, data);
Andrew Lunn436fe172018-03-01 02:02:29 +01001113 }
Andrew Lunn65f60e42018-03-28 23:50:28 +02001114 data += count;
1115 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001116 mv88e6xxx_reg_unlock(chip);
Andrew Lunn052f9472016-11-21 23:27:03 +01001117}
1118
Vivien Didelotf81ec902016-05-09 13:22:58 -04001119static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1120 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001121{
Vivien Didelot04bed142016-08-31 18:06:13 -04001122 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001123 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001124
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001125 mv88e6xxx_reg_lock(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001126
Andrew Lunna605a0f2016-11-21 23:26:58 +01001127 ret = mv88e6xxx_stats_snapshot(chip, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001128 mv88e6xxx_reg_unlock(chip);
Andrew Lunn377cda12018-02-15 14:38:34 +01001129
1130 if (ret < 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001131 return;
Andrew Lunn052f9472016-11-21 23:27:03 +01001132
1133 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001134
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001135}
Ben Hutchings98e67302011-11-25 14:36:19 +00001136
Vivien Didelotf81ec902016-05-09 13:22:58 -04001137static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001138{
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001139 struct mv88e6xxx_chip *chip = ds->priv;
1140 int len;
1141
1142 len = 32 * sizeof(u16);
1143 if (chip->info->ops->serdes_get_regs_len)
1144 len += chip->info->ops->serdes_get_regs_len(chip, port);
1145
1146 return len;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001147}
1148
Vivien Didelotf81ec902016-05-09 13:22:58 -04001149static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1150 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001151{
Vivien Didelot04bed142016-08-31 18:06:13 -04001152 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001153 int err;
1154 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001155 u16 *p = _p;
1156 int i;
1157
Vivien Didelota5f39322018-12-17 16:05:21 -05001158 regs->version = chip->info->prod_num;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001159
1160 memset(p, 0xff, 32 * sizeof(u16));
1161
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001162 mv88e6xxx_reg_lock(chip);
Vivien Didelot23062512016-05-09 13:22:45 -04001163
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001164 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001165
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001166 err = mv88e6xxx_port_read(chip, port, i, &reg);
1167 if (!err)
1168 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001169 }
Vivien Didelot23062512016-05-09 13:22:45 -04001170
Andrew Lunn0d30bbd2020-02-16 18:54:13 +01001171 if (chip->info->ops->serdes_get_regs)
1172 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1173
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001174 mv88e6xxx_reg_unlock(chip);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001175}
1176
Vivien Didelot08f50062017-08-01 16:32:41 -04001177static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1178 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001179{
Vivien Didelot5480db62017-08-01 16:32:40 -04001180 /* Nothing to do on the port's MAC */
1181 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001182}
1183
Vivien Didelot08f50062017-08-01 16:32:41 -04001184static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1185 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001186{
Vivien Didelot5480db62017-08-01 16:32:40 -04001187 /* Nothing to do on the port's MAC */
1188 return 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001189}
1190
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001191/* Mask of the local ports allowed to receive frames from a given fabric port */
Vivien Didelote5887a22017-03-30 17:37:11 -04001192static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001193{
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001194 struct dsa_switch *ds = chip->ds;
1195 struct dsa_switch_tree *dst = ds->dst;
Vivien Didelote5887a22017-03-30 17:37:11 -04001196 struct net_device *br;
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001197 struct dsa_port *dp;
1198 bool found = false;
Vivien Didelote5887a22017-03-30 17:37:11 -04001199 u16 pvlan;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001200
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001201 list_for_each_entry(dp, &dst->ports, list) {
1202 if (dp->ds->index == dev && dp->index == port) {
1203 found = true;
1204 break;
1205 }
1206 }
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001207
Vivien Didelote5887a22017-03-30 17:37:11 -04001208 /* Prevent frames from unknown switch or port */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001209 if (!found)
Vivien Didelote5887a22017-03-30 17:37:11 -04001210 return 0;
1211
1212 /* Frames from DSA links and CPU ports can egress any local port */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001213 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
Vivien Didelote5887a22017-03-30 17:37:11 -04001214 return mv88e6xxx_port_mask(chip);
1215
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001216 br = dp->bridge_dev;
Vivien Didelote5887a22017-03-30 17:37:11 -04001217 pvlan = 0;
1218
1219 /* Frames from user ports can egress any local DSA links and CPU ports,
1220 * as well as any local member of their bridge group.
1221 */
Vivien Didelot9dc8b132019-10-21 16:51:26 -04001222 list_for_each_entry(dp, &dst->ports, list)
1223 if (dp->ds == ds &&
1224 (dp->type == DSA_PORT_TYPE_CPU ||
1225 dp->type == DSA_PORT_TYPE_DSA ||
1226 (br && dp->bridge_dev == br)))
1227 pvlan |= BIT(dp->index);
Vivien Didelote5887a22017-03-30 17:37:11 -04001228
1229 return pvlan;
1230}
1231
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001232static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
Vivien Didelote5887a22017-03-30 17:37:11 -04001233{
1234 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001235
1236 /* prevent frames from going back out of the port they came in on */
1237 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001238
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001239 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001240}
1241
Vivien Didelotf81ec902016-05-09 13:22:58 -04001242static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1243 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001244{
Vivien Didelot04bed142016-08-31 18:06:13 -04001245 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot553eb542016-05-13 20:38:23 -04001246 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001247
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001248 mv88e6xxx_reg_lock(chip);
Vivien Didelotf894c292017-06-08 18:34:10 -04001249 err = mv88e6xxx_port_set_state(chip, port, state);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001250 mv88e6xxx_reg_unlock(chip);
Vivien Didelot553eb542016-05-13 20:38:23 -04001251
1252 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001253 dev_err(ds->dev, "p%d: failed to update state\n", port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001254}
1255
Vivien Didelot93e18d62018-05-11 17:16:35 -04001256static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1257{
1258 int err;
1259
1260 if (chip->info->ops->ieee_pri_map) {
1261 err = chip->info->ops->ieee_pri_map(chip);
1262 if (err)
1263 return err;
1264 }
1265
1266 if (chip->info->ops->ip_pri_map) {
1267 err = chip->info->ops->ip_pri_map(chip);
1268 if (err)
1269 return err;
1270 }
1271
1272 return 0;
1273}
1274
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001275static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1276{
Vivien Didelotc5f51762019-10-30 22:09:13 -04001277 struct dsa_switch *ds = chip->ds;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001278 int target, port;
1279 int err;
1280
1281 if (!chip->info->global2_addr)
1282 return 0;
1283
1284 /* Initialize the routing port to the 32 possible target devices */
1285 for (target = 0; target < 32; target++) {
Vivien Didelotc5f51762019-10-30 22:09:13 -04001286 port = dsa_routing_port(ds, target);
1287 if (port == ds->num_ports)
1288 port = 0x1f;
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001289
1290 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1291 if (err)
1292 return err;
1293 }
1294
Vivien Didelot02317e62018-05-09 11:38:49 -04001295 if (chip->info->ops->set_cascade_port) {
1296 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1297 err = chip->info->ops->set_cascade_port(chip, port);
1298 if (err)
1299 return err;
1300 }
1301
Vivien Didelot23c98912018-05-09 11:38:50 -04001302 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1303 if (err)
1304 return err;
1305
Vivien Didelotc7f047b2018-04-26 21:56:45 -04001306 return 0;
1307}
1308
Vivien Didelotb28f8722018-04-26 21:56:44 -04001309static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1310{
1311 /* Clear all trunk masks and mapping */
1312 if (chip->info->global2_addr)
1313 return mv88e6xxx_g2_trunk_clear(chip);
1314
1315 return 0;
1316}
1317
Vivien Didelot9e5baf92018-05-09 11:38:51 -04001318static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1319{
1320 if (chip->info->ops->rmu_disable)
1321 return chip->info->ops->rmu_disable(chip);
1322
1323 return 0;
1324}
1325
Vivien Didelot9e907d72017-07-17 13:03:43 -04001326static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1327{
1328 if (chip->info->ops->pot_clear)
1329 return chip->info->ops->pot_clear(chip);
1330
1331 return 0;
1332}
1333
Vivien Didelot51c901a2017-07-17 13:03:41 -04001334static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1335{
1336 if (chip->info->ops->mgmt_rsvd2cpu)
1337 return chip->info->ops->mgmt_rsvd2cpu(chip);
1338
1339 return 0;
1340}
1341
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001342static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1343{
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001344 int err;
1345
Vivien Didelotdaefc942017-03-11 16:12:54 -05001346 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1347 if (err)
1348 return err;
1349
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001350 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1351 if (err)
1352 return err;
1353
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001354 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1355}
1356
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04001357static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1358{
1359 int port;
1360 int err;
1361
1362 if (!chip->info->ops->irl_init_all)
1363 return 0;
1364
1365 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1366 /* Disable ingress rate limiting by resetting all per port
1367 * ingress rate limit resources to their initial state.
1368 */
1369 err = chip->info->ops->irl_init_all(chip, port);
1370 if (err)
1371 return err;
1372 }
1373
1374 return 0;
1375}
1376
Vivien Didelot04a69a12017-10-13 14:18:05 -04001377static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1378{
1379 if (chip->info->ops->set_switch_mac) {
1380 u8 addr[ETH_ALEN];
1381
1382 eth_random_addr(addr);
1383
1384 return chip->info->ops->set_switch_mac(chip, addr);
1385 }
1386
1387 return 0;
1388}
1389
Vivien Didelot17a15942017-03-30 17:37:09 -04001390static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1391{
1392 u16 pvlan = 0;
1393
1394 if (!mv88e6xxx_has_pvt(chip))
Vivien Didelotd14939b2019-10-21 16:51:25 -04001395 return 0;
Vivien Didelot17a15942017-03-30 17:37:09 -04001396
1397 /* Skip the local source device, which uses in-chip port VLAN */
1398 if (dev != chip->ds->index)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001399 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
Vivien Didelot17a15942017-03-30 17:37:09 -04001400
1401 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1402}
1403
Vivien Didelot81228992017-03-30 17:37:08 -04001404static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1405{
Vivien Didelot17a15942017-03-30 17:37:09 -04001406 int dev, port;
1407 int err;
1408
Vivien Didelot81228992017-03-30 17:37:08 -04001409 if (!mv88e6xxx_has_pvt(chip))
1410 return 0;
1411
1412 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1413 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1414 */
Vivien Didelot17a15942017-03-30 17:37:09 -04001415 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1416 if (err)
1417 return err;
1418
1419 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1420 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1421 err = mv88e6xxx_pvt_map(chip, dev, port);
1422 if (err)
1423 return err;
1424 }
1425 }
1426
1427 return 0;
Vivien Didelot81228992017-03-30 17:37:08 -04001428}
1429
Vivien Didelot749efcb2016-09-22 16:49:24 -04001430static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1431{
1432 struct mv88e6xxx_chip *chip = ds->priv;
1433 int err;
1434
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001435 mv88e6xxx_reg_lock(chip);
Vivien Didelote606ca32017-03-11 16:12:55 -05001436 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001437 mv88e6xxx_reg_unlock(chip);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001438
1439 if (err)
Vivien Didelot774439e52017-06-08 18:34:08 -04001440 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001441}
1442
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001443static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1444{
1445 if (!chip->info->max_vid)
1446 return 0;
1447
1448 return mv88e6xxx_g1_vtu_flush(chip);
1449}
1450
Vivien Didelotf1394b782017-05-01 14:05:22 -04001451static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1452 struct mv88e6xxx_vtu_entry *entry)
1453{
1454 if (!chip->info->ops->vtu_getnext)
1455 return -EOPNOTSUPP;
1456
1457 return chip->info->ops->vtu_getnext(chip, entry);
1458}
1459
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04001460static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1461 struct mv88e6xxx_vtu_entry *entry)
1462{
1463 if (!chip->info->ops->vtu_loadpurge)
1464 return -EOPNOTSUPP;
1465
1466 return chip->info->ops->vtu_loadpurge(chip, entry);
1467}
1468
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001469int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001470{
Vivien Didelot425d2d32019-08-01 14:36:34 -04001471 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001472 int i, err;
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001473 u16 fid;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001474
1475 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1476
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001477 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001478 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001479 err = mv88e6xxx_port_get_fid(chip, i, &fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001480 if (err)
1481 return err;
1482
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001483 set_bit(fid, fid_bitmap);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001484 }
1485
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001486 /* Set every FID bit used by the VLAN entries */
Vivien Didelot425d2d32019-08-01 14:36:34 -04001487 vlan.vid = chip->info->max_vid;
1488 vlan.valid = false;
1489
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001490 do {
Vivien Didelotf1394b782017-05-01 14:05:22 -04001491 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001492 if (err)
1493 return err;
1494
1495 if (!vlan.valid)
1496 break;
1497
1498 set_bit(vlan.fid, fid_bitmap);
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001499 } while (vlan.vid < chip->info->max_vid);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001500
Andrew Lunn90b6dbd2020-09-18 21:11:06 +02001501 return 0;
1502}
1503
1504static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1505{
1506 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1507 int err;
1508
1509 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1510 if (err)
1511 return err;
1512
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001513 /* The reset value 0x000 is used to indicate that multiple address
1514 * databases are not needed. Return the next positive available.
1515 */
1516 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001517 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001518 return -ENOSPC;
1519
1520 /* Clear the database */
Vivien Didelotdaefc942017-03-11 16:12:54 -05001521 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001522}
1523
Vivien Didelotda9c3592016-02-12 12:09:40 -05001524static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1525 u16 vid_begin, u16 vid_end)
1526{
Vivien Didelot04bed142016-08-31 18:06:13 -04001527 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot425d2d32019-08-01 14:36:34 -04001528 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001529 int i, err;
1530
Andrew Lunndb06ae412017-09-25 23:32:20 +02001531 /* DSA and CPU ports have to be members of multiple vlans */
1532 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1533 return 0;
1534
Vivien Didelotda9c3592016-02-12 12:09:40 -05001535 if (!vid_begin)
1536 return -EOPNOTSUPP;
1537
Vivien Didelot425d2d32019-08-01 14:36:34 -04001538 vlan.vid = vid_begin - 1;
1539 vlan.valid = false;
1540
Vivien Didelotda9c3592016-02-12 12:09:40 -05001541 do {
Vivien Didelotf1394b782017-05-01 14:05:22 -04001542 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001543 if (err)
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001544 return err;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001545
1546 if (!vlan.valid)
1547 break;
1548
1549 if (vlan.vid > vid_end)
1550 break;
1551
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001552 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotda9c3592016-02-12 12:09:40 -05001553 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1554 continue;
1555
Vivien Didelot68bb8ea2019-10-21 16:51:15 -04001556 if (!dsa_to_port(ds, i)->slave)
Andrew Lunn66e28092016-12-11 21:07:19 +01001557 continue;
1558
Vivien Didelotbd00e052017-05-01 14:05:11 -04001559 if (vlan.member[i] ==
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001560 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001561 continue;
1562
Vivien Didelotc8652c82017-10-16 11:12:19 -04001563 if (dsa_to_port(ds, i)->bridge_dev ==
Vivien Didelot68bb8ea2019-10-21 16:51:15 -04001564 dsa_to_port(ds, port)->bridge_dev)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001565 break; /* same bridge, check next VLAN */
1566
Vivien Didelotc8652c82017-10-16 11:12:19 -04001567 if (!dsa_to_port(ds, i)->bridge_dev)
Andrew Lunn66e28092016-12-11 21:07:19 +01001568 continue;
1569
Andrew Lunn743fcc22017-11-09 22:29:54 +01001570 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1571 port, vlan.vid, i,
Vivien Didelotc8652c82017-10-16 11:12:19 -04001572 netdev_name(dsa_to_port(ds, i)->bridge_dev));
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001573 return -EOPNOTSUPP;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001574 }
1575 } while (vlan.vid < vid_end);
1576
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001577 return 0;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001578}
1579
Vivien Didelotf81ec902016-05-09 13:22:58 -04001580static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
Vladimir Oltean2e554a72020-10-03 01:06:46 +03001581 bool vlan_filtering,
1582 struct switchdev_trans *trans)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001583{
Vivien Didelot04bed142016-08-31 18:06:13 -04001584 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot81c6edb2017-06-12 12:37:41 -04001585 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1586 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001587 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001588
Vladimir Oltean2e554a72020-10-03 01:06:46 +03001589 if (switchdev_trans_ph_prepare(trans))
1590 return chip->info->max_vid ? 0 : -EOPNOTSUPP;
Vivien Didelot54d77b52016-05-09 13:22:47 -04001591
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001592 mv88e6xxx_reg_lock(chip);
Vivien Didelot385a0992016-11-04 03:23:31 +01001593 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001594 mv88e6xxx_reg_unlock(chip);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001595
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001596 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001597}
1598
Vivien Didelot57d32312016-06-20 13:13:58 -04001599static int
1600mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001601 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001602{
Vivien Didelot04bed142016-08-31 18:06:13 -04001603 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001604 int err;
1605
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001606 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001607 return -EOPNOTSUPP;
1608
Vivien Didelotda9c3592016-02-12 12:09:40 -05001609 /* If the requested port doesn't belong to the same bridge as the VLAN
1610 * members, do not support it (yet) and fallback to software VLAN.
1611 */
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001612 mv88e6xxx_reg_lock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001613 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1614 vlan->vid_end);
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001615 mv88e6xxx_reg_unlock(chip);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001616
Vivien Didelot76e398a2015-11-01 12:33:55 -05001617 /* We don't need any dynamic resource from the kernel (yet),
1618 * so skip the prepare phase.
1619 */
Vivien Didelot7095a4c2019-08-01 14:36:33 -04001620 return err;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001621}
1622
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001623static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1624 const unsigned char *addr, u16 vid,
1625 u8 state)
1626{
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001627 struct mv88e6xxx_atu_entry entry;
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001628 struct mv88e6xxx_vtu_entry vlan;
1629 u16 fid;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001630 int err;
1631
1632 /* Null VLAN ID corresponds to the port private database */
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001633 if (vid == 0) {
1634 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1635 if (err)
1636 return err;
1637 } else {
1638 vlan.vid = vid - 1;
1639 vlan.valid = false;
1640
1641 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1642 if (err)
1643 return err;
1644
1645 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1646 if (vlan.vid != vid || !vlan.valid)
1647 return -EOPNOTSUPP;
1648
1649 fid = vlan.fid;
1650 }
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001651
Vivien Didelotd8291a92019-09-07 16:00:47 -04001652 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001653 ether_addr_copy(entry.mac, addr);
1654 eth_addr_dec(entry.mac);
1655
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001656 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001657 if (err)
1658 return err;
1659
1660 /* Initialize a fresh ATU entry if it isn't found */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001661 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001662 memset(&entry, 0, sizeof(entry));
1663 ether_addr_copy(entry.mac, addr);
1664 }
1665
1666 /* Purge the ATU entry only if no port is using it anymore */
Vivien Didelotd8291a92019-09-07 16:00:47 -04001667 if (!state) {
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001668 entry.portvec &= ~BIT(port);
1669 if (!entry.portvec)
Vivien Didelotd8291a92019-09-07 16:00:47 -04001670 entry.state = 0;
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001671 } else {
1672 entry.portvec |= BIT(port);
1673 entry.state = state;
1674 }
1675
Vivien Didelot5ef8d242019-08-01 14:36:35 -04001676 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
Andrew Lunna4c93ae2017-11-09 22:29:55 +01001677}
1678
Vivien Didelotda7dc872019-09-07 16:00:49 -04001679static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1680 const struct mv88e6xxx_policy *policy)
1681{
1682 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1683 enum mv88e6xxx_policy_action action = policy->action;
1684 const u8 *addr = policy->addr;
1685 u16 vid = policy->vid;
1686 u8 state;
1687 int err;
1688 int id;
1689
1690 if (!chip->info->ops->port_set_policy)
1691 return -EOPNOTSUPP;
1692
1693 switch (mapping) {
1694 case MV88E6XXX_POLICY_MAPPING_DA:
1695 case MV88E6XXX_POLICY_MAPPING_SA:
1696 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1697 state = 0; /* Dissociate the port and address */
1698 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1699 is_multicast_ether_addr(addr))
1700 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1701 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1702 is_unicast_ether_addr(addr))
1703 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1704 else
1705 return -EOPNOTSUPP;
1706
1707 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1708 state);
1709 if (err)
1710 return err;
1711 break;
1712 default:
1713 return -EOPNOTSUPP;
1714 }
1715
1716 /* Skip the port's policy clearing if the mapping is still in use */
1717 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1718 idr_for_each_entry(&chip->policies, policy, id)
1719 if (policy->port == port &&
1720 policy->mapping == mapping &&
1721 policy->action != action)
1722 return 0;
1723
1724 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1725}
1726
1727static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1728 struct ethtool_rx_flow_spec *fs)
1729{
1730 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1731 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1732 enum mv88e6xxx_policy_mapping mapping;
1733 enum mv88e6xxx_policy_action action;
1734 struct mv88e6xxx_policy *policy;
1735 u16 vid = 0;
1736 u8 *addr;
1737 int err;
1738 int id;
1739
1740 if (fs->location != RX_CLS_LOC_ANY)
1741 return -EINVAL;
1742
1743 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1744 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1745 else
1746 return -EOPNOTSUPP;
1747
1748 switch (fs->flow_type & ~FLOW_EXT) {
1749 case ETHER_FLOW:
1750 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1751 is_zero_ether_addr(mac_mask->h_source)) {
1752 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1753 addr = mac_entry->h_dest;
1754 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1755 !is_zero_ether_addr(mac_mask->h_source)) {
1756 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1757 addr = mac_entry->h_source;
1758 } else {
1759 /* Cannot support DA and SA mapping in the same rule */
1760 return -EOPNOTSUPP;
1761 }
1762 break;
1763 default:
1764 return -EOPNOTSUPP;
1765 }
1766
1767 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
Andrew Lunn04844282020-07-05 21:38:08 +02001768 if (fs->m_ext.vlan_tci != htons(0xffff))
Vivien Didelotda7dc872019-09-07 16:00:49 -04001769 return -EOPNOTSUPP;
1770 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1771 }
1772
1773 idr_for_each_entry(&chip->policies, policy, id) {
1774 if (policy->port == port && policy->mapping == mapping &&
1775 policy->action == action && policy->vid == vid &&
1776 ether_addr_equal(policy->addr, addr))
1777 return -EEXIST;
1778 }
1779
1780 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1781 if (!policy)
1782 return -ENOMEM;
1783
1784 fs->location = 0;
1785 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1786 GFP_KERNEL);
1787 if (err) {
1788 devm_kfree(chip->dev, policy);
1789 return err;
1790 }
1791
1792 memcpy(&policy->fs, fs, sizeof(*fs));
1793 ether_addr_copy(policy->addr, addr);
1794 policy->mapping = mapping;
1795 policy->action = action;
1796 policy->port = port;
1797 policy->vid = vid;
1798
1799 err = mv88e6xxx_policy_apply(chip, port, policy);
1800 if (err) {
1801 idr_remove(&chip->policies, fs->location);
1802 devm_kfree(chip->dev, policy);
1803 return err;
1804 }
1805
1806 return 0;
1807}
1808
1809static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1810 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1811{
1812 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1813 struct mv88e6xxx_chip *chip = ds->priv;
1814 struct mv88e6xxx_policy *policy;
1815 int err;
1816 int id;
1817
1818 mv88e6xxx_reg_lock(chip);
1819
1820 switch (rxnfc->cmd) {
1821 case ETHTOOL_GRXCLSRLCNT:
1822 rxnfc->data = 0;
1823 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1824 rxnfc->rule_cnt = 0;
1825 idr_for_each_entry(&chip->policies, policy, id)
1826 if (policy->port == port)
1827 rxnfc->rule_cnt++;
1828 err = 0;
1829 break;
1830 case ETHTOOL_GRXCLSRULE:
1831 err = -ENOENT;
1832 policy = idr_find(&chip->policies, fs->location);
1833 if (policy) {
1834 memcpy(fs, &policy->fs, sizeof(*fs));
1835 err = 0;
1836 }
1837 break;
1838 case ETHTOOL_GRXCLSRLALL:
1839 rxnfc->data = 0;
1840 rxnfc->rule_cnt = 0;
1841 idr_for_each_entry(&chip->policies, policy, id)
1842 if (policy->port == port)
1843 rule_locs[rxnfc->rule_cnt++] = id;
1844 err = 0;
1845 break;
1846 default:
1847 err = -EOPNOTSUPP;
1848 break;
1849 }
1850
1851 mv88e6xxx_reg_unlock(chip);
1852
1853 return err;
1854}
1855
1856static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1857 struct ethtool_rxnfc *rxnfc)
1858{
1859 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1860 struct mv88e6xxx_chip *chip = ds->priv;
1861 struct mv88e6xxx_policy *policy;
1862 int err;
1863
1864 mv88e6xxx_reg_lock(chip);
1865
1866 switch (rxnfc->cmd) {
1867 case ETHTOOL_SRXCLSRLINS:
1868 err = mv88e6xxx_policy_insert(chip, port, fs);
1869 break;
1870 case ETHTOOL_SRXCLSRLDEL:
1871 err = -ENOENT;
1872 policy = idr_remove(&chip->policies, fs->location);
1873 if (policy) {
1874 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1875 err = mv88e6xxx_policy_apply(chip, port, policy);
1876 devm_kfree(chip->dev, policy);
1877 }
1878 break;
1879 default:
1880 err = -EOPNOTSUPP;
1881 break;
1882 }
1883
1884 mv88e6xxx_reg_unlock(chip);
1885
1886 return err;
1887}
1888
Andrew Lunn87fa8862017-11-09 22:29:56 +01001889static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1890 u16 vid)
1891{
1892 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1893 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1894
1895 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1896}
1897
1898static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1899{
1900 int port;
1901 int err;
1902
1903 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1904 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1905 if (err)
1906 return err;
1907 }
1908
1909 return 0;
1910}
1911
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001912static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
Russell King933b4422020-02-26 17:14:26 +00001913 u16 vid, u8 member, bool warn)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001914{
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001915 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001916 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001917 int i, err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001918
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001919 if (!vid)
1920 return -EOPNOTSUPP;
1921
1922 vlan.vid = vid - 1;
1923 vlan.valid = false;
1924
1925 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001926 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001927 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001928
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001929 if (vlan.vid != vid || !vlan.valid) {
1930 memset(&vlan, 0, sizeof(vlan));
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001931
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001932 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1933 if (err)
1934 return err;
Andrew Lunn87fa8862017-11-09 22:29:56 +01001935
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001936 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1937 if (i == port)
1938 vlan.member[i] = member;
1939 else
1940 vlan.member[i] = non_member;
1941
1942 vlan.vid = vid;
1943 vlan.valid = true;
1944
1945 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1946 if (err)
1947 return err;
1948
1949 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1950 if (err)
1951 return err;
1952 } else if (vlan.member[port] != member) {
1953 vlan.member[port] = member;
1954
1955 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1956 if (err)
1957 return err;
Russell King933b4422020-02-26 17:14:26 +00001958 } else if (warn) {
Vivien Didelotb1ac6fb2019-08-01 14:36:37 -04001959 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1960 port, vid);
1961 }
1962
1963 return 0;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001964}
1965
Vivien Didelotf81ec902016-05-09 13:22:58 -04001966static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
Vivien Didelot80e02362017-11-30 11:23:57 -05001967 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001968{
Vivien Didelot04bed142016-08-31 18:06:13 -04001969 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001970 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1971 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
Russell King933b4422020-02-26 17:14:26 +00001972 bool warn;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001973 u8 member;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001974 u16 vid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001975
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001976 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001977 return;
1978
Vivien Didelotc91498e2017-06-07 18:12:13 -04001979 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001980 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001981 else if (untagged)
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001982 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001983 else
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04001984 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
Vivien Didelotc91498e2017-06-07 18:12:13 -04001985
Russell King933b4422020-02-26 17:14:26 +00001986 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
1987 * and then the CPU port. Do not warn for duplicates for the CPU port.
1988 */
1989 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
1990
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00001991 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001992
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
Russell King933b4422020-02-26 17:14:26 +00001994 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
Vivien Didelot774439e52017-06-08 18:34:08 -04001995 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1996 vid, untagged ? 'u' : 't');
Vivien Didelot76e398a2015-11-01 12:33:55 -05001997
Vivien Didelot77064f32016-11-04 03:23:30 +01001998 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
Vivien Didelot774439e52017-06-08 18:34:08 -04001999 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
2000 vlan->vid_end);
Vivien Didelot4d5770b2016-04-06 11:55:05 -04002001
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002002 mv88e6xxx_reg_unlock(chip);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002003}
2004
Vivien Didelot521098922019-08-01 14:36:36 -04002005static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2006 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002007{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04002008 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002009 int i, err;
2010
Vivien Didelot521098922019-08-01 14:36:36 -04002011 if (!vid)
2012 return -EOPNOTSUPP;
2013
2014 vlan.vid = vid - 1;
2015 vlan.valid = false;
2016
2017 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002018 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002019 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04002020
Vivien Didelot521098922019-08-01 14:36:36 -04002021 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2022 * tell switchdev that this VLAN is likely handled in software.
2023 */
2024 if (vlan.vid != vid || !vlan.valid ||
2025 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05002026 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002027
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002028 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002029
2030 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002031 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002032 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -04002033 if (vlan.member[i] !=
2034 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002035 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002036 break;
2037 }
2038 }
2039
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04002040 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002041 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002042 return err;
2043
Vivien Didelote606ca32017-03-11 16:12:55 -05002044 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002045}
2046
Vivien Didelotf81ec902016-05-09 13:22:58 -04002047static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2048 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002049{
Vivien Didelot04bed142016-08-31 18:06:13 -04002050 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002051 u16 pvid, vid;
2052 int err = 0;
2053
Vivien Didelot3cf3c842017-05-01 14:05:10 -04002054 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04002055 return -EOPNOTSUPP;
2056
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002057 mv88e6xxx_reg_lock(chip);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002058
Vivien Didelot77064f32016-11-04 03:23:30 +01002059 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002060 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002061 goto unlock;
2062
Vivien Didelot76e398a2015-11-01 12:33:55 -05002063 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
Vivien Didelot521098922019-08-01 14:36:36 -04002064 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002065 if (err)
2066 goto unlock;
2067
2068 if (vid == pvid) {
Vivien Didelot77064f32016-11-04 03:23:30 +01002069 err = mv88e6xxx_port_set_pvid(chip, port, 0);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002070 if (err)
2071 goto unlock;
2072 }
2073 }
2074
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002075unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002076 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002077
2078 return err;
2079}
2080
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002081static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2082 const unsigned char *addr, u16 vid)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002083{
Vivien Didelot04bed142016-08-31 18:06:13 -04002084 struct mv88e6xxx_chip *chip = ds->priv;
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002085 int err;
Vivien Didelot6630e232015-08-06 01:44:07 -04002086
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002087 mv88e6xxx_reg_lock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002088 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2089 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002090 mv88e6xxx_reg_unlock(chip);
Arkadi Sharshevsky1b6dd552017-08-06 16:15:40 +03002091
2092 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002093}
2094
Vivien Didelotf81ec902016-05-09 13:22:58 -04002095static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
Arkadi Sharshevsky6c2c1dc2017-08-06 16:15:39 +03002096 const unsigned char *addr, u16 vid)
David S. Millercdf09692015-08-11 12:00:37 -07002097{
Vivien Didelot04bed142016-08-31 18:06:13 -04002098 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002099 int err;
David S. Millercdf09692015-08-11 12:00:37 -07002100
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002101 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04002102 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002103 mv88e6xxx_reg_unlock(chip);
David S. Millercdf09692015-08-11 12:00:37 -07002104
Vivien Didelot83dabd12016-08-31 11:50:04 -04002105 return err;
David S. Millercdf09692015-08-11 12:00:37 -07002106}
2107
Vivien Didelot83dabd12016-08-31 11:50:04 -04002108static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2109 u16 fid, u16 vid, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002110 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002111{
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002112 struct mv88e6xxx_atu_entry addr;
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002113 bool is_static;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002114 int err;
2115
Vivien Didelotd8291a92019-09-07 16:00:47 -04002116 addr.state = 0;
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002117 eth_broadcast_addr(addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002118
2119 do {
Vivien Didelotdabc1a92017-03-11 16:12:53 -05002120 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002121 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002122 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002123
Vivien Didelotd8291a92019-09-07 16:00:47 -04002124 if (!addr.state)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002125 break;
2126
Vivien Didelot01bd96c2017-03-11 16:12:57 -05002127 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002128 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002129
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002130 if (!is_unicast_ether_addr(addr.mac))
2131 continue;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002132
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002133 is_static = (addr.state ==
2134 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2135 err = cb(addr.mac, vid, is_static, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002136 if (err)
2137 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002138 } while (!is_broadcast_ether_addr(addr.mac));
2139
2140 return err;
2141}
2142
Vivien Didelot83dabd12016-08-31 11:50:04 -04002143static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002144 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelot83dabd12016-08-31 11:50:04 -04002145{
Vivien Didelot425d2d32019-08-01 14:36:34 -04002146 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot83dabd12016-08-31 11:50:04 -04002147 u16 fid;
2148 int err;
2149
2150 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002151 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002152 if (err)
2153 return err;
2154
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002155 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002156 if (err)
2157 return err;
2158
2159 /* Dump VLANs' Filtering Information Databases */
Vivien Didelot425d2d32019-08-01 14:36:34 -04002160 vlan.vid = chip->info->max_vid;
2161 vlan.valid = false;
2162
Vivien Didelot83dabd12016-08-31 11:50:04 -04002163 do {
Vivien Didelotf1394b782017-05-01 14:05:22 -04002164 err = mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002165 if (err)
2166 return err;
2167
2168 if (!vlan.valid)
2169 break;
2170
2171 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002172 cb, data);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002173 if (err)
2174 return err;
Vivien Didelot3cf3c842017-05-01 14:05:10 -04002175 } while (vlan.vid < chip->info->max_vid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04002176
2177 return err;
2178}
2179
Vivien Didelotf81ec902016-05-09 13:22:58 -04002180static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
Arkadi Sharshevsky2bedde12017-08-06 16:15:49 +03002181 dsa_fdb_dump_cb_t *cb, void *data)
Vivien Didelotf33475b2015-10-22 09:34:41 -04002182{
Vivien Didelot04bed142016-08-31 18:06:13 -04002183 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotfcf15362019-06-12 12:42:47 -04002184 int err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002185
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002186 mv88e6xxx_reg_lock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002187 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002188 mv88e6xxx_reg_unlock(chip);
Vivien Didelotfcf15362019-06-12 12:42:47 -04002189
2190 return err;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002191}
2192
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002193static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2194 struct net_device *br)
2195{
Vivien Didelotef2025e2019-10-21 16:51:27 -04002196 struct dsa_switch *ds = chip->ds;
2197 struct dsa_switch_tree *dst = ds->dst;
2198 struct dsa_port *dp;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002199 int err;
2200
Vivien Didelotef2025e2019-10-21 16:51:27 -04002201 list_for_each_entry(dp, &dst->ports, list) {
2202 if (dp->bridge_dev == br) {
2203 if (dp->ds == ds) {
2204 /* This is a local bridge group member,
2205 * remap its Port VLAN Map.
2206 */
2207 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2208 if (err)
2209 return err;
2210 } else {
2211 /* This is an external bridge group member,
2212 * remap its cross-chip Port VLAN Table entry.
2213 */
2214 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2215 dp->index);
Vivien Didelote96a6e02017-03-30 17:37:13 -04002216 if (err)
2217 return err;
2218 }
2219 }
2220 }
2221
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002222 return 0;
2223}
2224
Vivien Didelotf81ec902016-05-09 13:22:58 -04002225static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vivien Didelotfae8a252017-01-27 15:29:42 -05002226 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002227{
Vivien Didelot04bed142016-08-31 18:06:13 -04002228 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002229 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002230
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002231 mv88e6xxx_reg_lock(chip);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002232 err = mv88e6xxx_bridge_map(chip, br);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002233 mv88e6xxx_reg_unlock(chip);
Vivien Didelota6692752016-02-12 12:09:39 -05002234
Vivien Didelot466dfa02016-02-26 13:16:05 -05002235 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002236}
2237
Vivien Didelotf123f2f2017-01-27 15:29:41 -05002238static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2239 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002240{
Vivien Didelot04bed142016-08-31 18:06:13 -04002241 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002242
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002243 mv88e6xxx_reg_lock(chip);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002244 if (mv88e6xxx_bridge_map(chip, br) ||
2245 mv88e6xxx_port_vlan_map(chip, port))
2246 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002247 mv88e6xxx_reg_unlock(chip);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05002248}
2249
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002250static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2251 int tree_index, int sw_index,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002252 int port, struct net_device *br)
2253{
2254 struct mv88e6xxx_chip *chip = ds->priv;
2255 int err;
2256
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002257 if (tree_index != ds->dst->index)
2258 return 0;
2259
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002260 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002261 err = mv88e6xxx_pvt_map(chip, sw_index, port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002262 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002263
2264 return err;
2265}
2266
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002267static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2268 int tree_index, int sw_index,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002269 int port, struct net_device *br)
2270{
2271 struct mv88e6xxx_chip *chip = ds->priv;
2272
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002273 if (tree_index != ds->dst->index)
2274 return;
2275
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002276 mv88e6xxx_reg_lock(chip);
Vladimir Olteanf66a6a62020-05-10 19:37:41 +03002277 if (mv88e6xxx_pvt_map(chip, sw_index, port))
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002278 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002279 mv88e6xxx_reg_unlock(chip);
Vivien Didelotaec5ac82017-03-30 17:37:15 -04002280}
2281
Vivien Didelot17e708b2016-12-05 17:30:27 -05002282static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2283{
2284 if (chip->info->ops->reset)
2285 return chip->info->ops->reset(chip);
2286
2287 return 0;
2288}
2289
Vivien Didelot309eca62016-12-05 17:30:26 -05002290static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2291{
2292 struct gpio_desc *gpiod = chip->reset;
2293
2294 /* If there is a GPIO connected to the reset pin, toggle it */
2295 if (gpiod) {
2296 gpiod_set_value_cansleep(gpiod, 1);
2297 usleep_range(10000, 20000);
2298 gpiod_set_value_cansleep(gpiod, 0);
2299 usleep_range(10000, 20000);
2300 }
2301}
2302
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002303static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2304{
2305 int i, err;
2306
2307 /* Set all ports to the Disabled state */
2308 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotf894c292017-06-08 18:34:10 -04002309 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002310 if (err)
2311 return err;
2312 }
2313
2314 /* Wait for transmit queues to drain,
2315 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2316 */
2317 usleep_range(2000, 4000);
2318
2319 return 0;
2320}
2321
Vivien Didelotfad09c72016-06-21 12:28:20 -04002322static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002323{
Vivien Didelota935c052016-09-29 12:21:53 -04002324 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002325
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002326 err = mv88e6xxx_disable_ports(chip);
2327 if (err)
2328 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002329
Vivien Didelot309eca62016-12-05 17:30:26 -05002330 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002331
Vivien Didelot17e708b2016-12-05 17:30:27 -05002332 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002333}
2334
Vivien Didelot43145572017-03-11 16:12:59 -05002335static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002336 enum mv88e6xxx_frame_mode frame,
2337 enum mv88e6xxx_egress_mode egress, u16 etype)
Andrew Lunn56995cb2016-12-03 04:35:19 +01002338{
2339 int err;
2340
Vivien Didelot43145572017-03-11 16:12:59 -05002341 if (!chip->info->ops->port_set_frame_mode)
2342 return -EOPNOTSUPP;
2343
2344 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002345 if (err)
2346 return err;
2347
Vivien Didelot43145572017-03-11 16:12:59 -05002348 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2349 if (err)
2350 return err;
2351
2352 if (chip->info->ops->port_set_ether_type)
2353 return chip->info->ops->port_set_ether_type(chip, port, etype);
2354
2355 return 0;
2356}
2357
2358static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2359{
2360 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002361 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002362 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002363}
2364
2365static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2366{
2367 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002368 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
Vivien Didelotb8109592017-06-12 12:37:45 -04002369 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
Vivien Didelot43145572017-03-11 16:12:59 -05002370}
2371
2372static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2373{
2374 return mv88e6xxx_set_port_mode(chip, port,
2375 MV88E6XXX_FRAME_MODE_ETHERTYPE,
Vivien Didelot31bef4e2017-06-08 18:34:09 -04002376 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2377 ETH_P_EDSA);
Vivien Didelot43145572017-03-11 16:12:59 -05002378}
2379
2380static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2381{
2382 if (dsa_is_dsa_port(chip->ds, port))
2383 return mv88e6xxx_set_port_mode_dsa(chip, port);
2384
Vivien Didelot2b3e9892017-10-26 11:22:54 -04002385 if (dsa_is_user_port(chip->ds, port))
Vivien Didelot43145572017-03-11 16:12:59 -05002386 return mv88e6xxx_set_port_mode_normal(chip, port);
2387
2388 /* Setup CPU port mode depending on its supported tag format */
2389 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2390 return mv88e6xxx_set_port_mode_dsa(chip, port);
2391
2392 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2393 return mv88e6xxx_set_port_mode_edsa(chip, port);
2394
2395 return -EINVAL;
2396}
2397
Vivien Didelotea698f42017-03-11 16:12:50 -05002398static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2399{
2400 bool message = dsa_is_dsa_port(chip->ds, port);
2401
2402 return mv88e6xxx_port_set_message_port(chip, port, message);
2403}
2404
Vivien Didelot601aeed2017-03-11 16:13:00 -05002405static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2406{
Vivien Didelot3ee50cb2017-12-05 15:34:09 -05002407 struct dsa_switch *ds = chip->ds;
David S. Miller407308f2019-06-15 13:35:29 -07002408 bool flood;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002409
David S. Miller407308f2019-06-15 13:35:29 -07002410 /* Upstream ports flood frames with unknown unicast or multicast DA */
2411 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2412 if (chip->info->ops->port_set_egress_floods)
2413 return chip->info->ops->port_set_egress_floods(chip, port,
2414 flood, flood);
Vivien Didelot601aeed2017-03-11 16:13:00 -05002415
David S. Miller407308f2019-06-15 13:35:29 -07002416 return 0;
Vivien Didelot601aeed2017-03-11 16:13:00 -05002417}
2418
Vivien Didelot45de77f2019-08-31 16:18:36 -04002419static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2420{
2421 struct mv88e6xxx_port *mvp = dev_id;
2422 struct mv88e6xxx_chip *chip = mvp->chip;
2423 irqreturn_t ret = IRQ_NONE;
2424 int port = mvp->port;
2425 u8 lane;
2426
2427 mv88e6xxx_reg_lock(chip);
2428 lane = mv88e6xxx_serdes_get_lane(chip, port);
2429 if (lane)
2430 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2431 mv88e6xxx_reg_unlock(chip);
2432
2433 return ret;
2434}
2435
2436static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2437 u8 lane)
2438{
2439 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2440 unsigned int irq;
2441 int err;
2442
2443 /* Nothing to request if this SERDES port has no IRQ */
2444 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2445 if (!irq)
2446 return 0;
2447
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002448 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2449 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2450
Vivien Didelot45de77f2019-08-31 16:18:36 -04002451 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2452 mv88e6xxx_reg_unlock(chip);
2453 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
Andrew Lunne6f2f6b2020-01-06 17:13:49 +01002454 IRQF_ONESHOT, dev_id->serdes_irq_name,
2455 dev_id);
Vivien Didelot45de77f2019-08-31 16:18:36 -04002456 mv88e6xxx_reg_lock(chip);
2457 if (err)
2458 return err;
2459
2460 dev_id->serdes_irq = irq;
2461
2462 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2463}
2464
2465static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2466 u8 lane)
2467{
2468 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2469 unsigned int irq = dev_id->serdes_irq;
2470 int err;
2471
2472 /* Nothing to free if no IRQ has been requested */
2473 if (!irq)
2474 return 0;
2475
2476 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2477
2478 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2479 mv88e6xxx_reg_unlock(chip);
2480 free_irq(irq, dev_id);
2481 mv88e6xxx_reg_lock(chip);
2482
2483 dev_id->serdes_irq = 0;
2484
2485 return err;
2486}
2487
Andrew Lunn6d917822017-05-26 01:03:21 +02002488static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2489 bool on)
2490{
Vivien Didelotdc272f62019-08-31 16:18:33 -04002491 u8 lane;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002492 int err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002493
Vivien Didelotdc272f62019-08-31 16:18:33 -04002494 lane = mv88e6xxx_serdes_get_lane(chip, port);
2495 if (!lane)
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002496 return 0;
2497
2498 if (on) {
Vivien Didelotdc272f62019-08-31 16:18:33 -04002499 err = mv88e6xxx_serdes_power_up(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002500 if (err)
2501 return err;
2502
Vivien Didelot45de77f2019-08-31 16:18:36 -04002503 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002504 } else {
Vivien Didelot45de77f2019-08-31 16:18:36 -04002505 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2506 if (err)
2507 return err;
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002508
Vivien Didelotdc272f62019-08-31 16:18:33 -04002509 err = mv88e6xxx_serdes_power_down(chip, port, lane);
Vivien Didelotfc0bc012019-08-19 16:00:53 -04002510 }
2511
2512 return err;
Andrew Lunn6d917822017-05-26 01:03:21 +02002513}
2514
Vivien Didelotfa371c82017-12-05 15:34:10 -05002515static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2516{
2517 struct dsa_switch *ds = chip->ds;
2518 int upstream_port;
2519 int err;
2520
Vivien Didelot07073c72017-12-05 15:34:13 -05002521 upstream_port = dsa_upstream_port(ds, port);
Vivien Didelotfa371c82017-12-05 15:34:10 -05002522 if (chip->info->ops->port_set_upstream_port) {
2523 err = chip->info->ops->port_set_upstream_port(chip, port,
2524 upstream_port);
2525 if (err)
2526 return err;
2527 }
2528
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002529 if (port == upstream_port) {
2530 if (chip->info->ops->set_cpu_port) {
2531 err = chip->info->ops->set_cpu_port(chip,
2532 upstream_port);
2533 if (err)
2534 return err;
2535 }
2536
2537 if (chip->info->ops->set_egress_port) {
2538 err = chip->info->ops->set_egress_port(chip,
Iwan R Timmer5c74c542019-11-07 22:11:13 +01002539 MV88E6XXX_EGRESS_DIR_INGRESS,
2540 upstream_port);
2541 if (err)
2542 return err;
2543
2544 err = chip->info->ops->set_egress_port(chip,
2545 MV88E6XXX_EGRESS_DIR_EGRESS,
2546 upstream_port);
Vivien Didelot0ea54dd2017-12-05 15:34:11 -05002547 if (err)
2548 return err;
2549 }
2550 }
2551
Vivien Didelotfa371c82017-12-05 15:34:10 -05002552 return 0;
2553}
2554
Vivien Didelotfad09c72016-06-21 12:28:20 -04002555static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002556{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002557 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002558 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002559 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002560
Andrew Lunn7b898462018-08-09 15:38:47 +02002561 chip->ports[port].chip = chip;
2562 chip->ports[port].port = port;
2563
Vivien Didelotd78343d2016-11-04 03:23:36 +01002564 /* MAC Forcing register: don't force link, speed, duplex or flow control
2565 * state to any particular values on physical ports, but force the CPU
2566 * port and all DSA ports to their maximum bandwidth and full duplex.
2567 */
2568 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2569 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2570 SPEED_MAX, DUPLEX_FULL,
Andrew Lunn54186b92018-08-09 15:38:37 +02002571 PAUSE_OFF,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002572 PHY_INTERFACE_MODE_NA);
2573 else
2574 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2575 SPEED_UNFORCED, DUPLEX_UNFORCED,
Andrew Lunn54186b92018-08-09 15:38:37 +02002576 PAUSE_ON,
Vivien Didelotd78343d2016-11-04 03:23:36 +01002577 PHY_INTERFACE_MODE_NA);
2578 if (err)
2579 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002580
2581 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2582 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2583 * tunneling, determine priority by looking at 802.1p and IP
2584 * priority fields (IP prio has precedence), and set STP state
2585 * to Forwarding.
2586 *
2587 * If this is the CPU link, use DSA or EDSA tagging depending
2588 * on which tagging mode was configured.
2589 *
2590 * If this is a link to another switch, use DSA tagging mode.
2591 *
2592 * If this is the upstream port for this switch, enable
2593 * forwarding of unknown unicasts and multicasts.
2594 */
Vivien Didelota89b433be2017-06-12 12:37:37 -04002595 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2596 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2597 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2598 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002599 if (err)
2600 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002601
Vivien Didelot601aeed2017-03-11 16:13:00 -05002602 err = mv88e6xxx_setup_port_mode(chip, port);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002603 if (err)
2604 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002605
Vivien Didelot601aeed2017-03-11 16:13:00 -05002606 err = mv88e6xxx_setup_egress_floods(chip, port);
Vivien Didelot43145572017-03-11 16:12:59 -05002607 if (err)
2608 return err;
2609
Vivien Didelot8efdda42015-08-13 12:52:23 -04002610 /* Port Control 2: don't force a good FCS, set the maximum frame size to
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002611 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002612 * untagged frames on this port, do a destination address lookup on all
2613 * received packets as usual, disable ARP mirroring and don't send a
2614 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002615 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002616 err = mv88e6xxx_port_set_map_da(chip, port);
2617 if (err)
2618 return err;
2619
Vivien Didelotfa371c82017-12-05 15:34:10 -05002620 err = mv88e6xxx_setup_upstream_port(chip, port);
2621 if (err)
2622 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002623
Andrew Lunna23b2962017-02-04 20:15:28 +01002624 err = mv88e6xxx_port_set_8021q_mode(chip, port,
Vivien Didelot81c6edb2017-06-12 12:37:41 -04002625 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
Andrew Lunna23b2962017-02-04 20:15:28 +01002626 if (err)
2627 return err;
2628
Vivien Didelotcd782652017-06-08 18:34:13 -04002629 if (chip->info->ops->port_set_jumbo_size) {
2630 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
Andrew Lunn5f436662016-12-03 04:45:17 +01002631 if (err)
2632 return err;
2633 }
2634
Andrew Lunn54d792f2015-05-06 01:09:47 +02002635 /* Port Association Vector: when learning source addresses
2636 * of packets, add the address to the address database using
2637 * a port bitmap that has only the bit for this port set and
2638 * the other bits clear.
2639 */
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002640 reg = 1 << port;
Vivien Didelot996ecb82016-04-14 14:42:08 -04002641 /* Disable learning for CPU port */
2642 if (dsa_is_cpu_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002643 reg = 0;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002644
Vivien Didelot2a4614e2017-06-12 12:37:43 -04002645 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2646 reg);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002647 if (err)
2648 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002649
2650 /* Egress rate control 2: disable egress rate control. */
Vivien Didelot2cb8cb12017-06-12 12:37:42 -04002651 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2652 0x0000);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002653 if (err)
2654 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002655
Vivien Didelot08984322017-06-08 18:34:12 -04002656 if (chip->info->ops->port_pause_limit) {
2657 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002658 if (err)
2659 return err;
2660 }
2661
Vivien Didelotc8c94892017-03-11 16:13:01 -05002662 if (chip->info->ops->port_disable_learn_limit) {
2663 err = chip->info->ops->port_disable_learn_limit(chip, port);
2664 if (err)
2665 return err;
2666 }
2667
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002668 if (chip->info->ops->port_disable_pri_override) {
2669 err = chip->info->ops->port_disable_pri_override(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002670 if (err)
2671 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002672 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002673
Andrew Lunnef0a7312016-12-03 04:35:16 +01002674 if (chip->info->ops->port_tag_remap) {
2675 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002676 if (err)
2677 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002678 }
2679
Andrew Lunnef70b112016-12-03 04:45:18 +01002680 if (chip->info->ops->port_egress_rate_limiting) {
2681 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002682 if (err)
2683 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002684 }
2685
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02002686 if (chip->info->ops->port_setup_message_port) {
2687 err = chip->info->ops->port_setup_message_port(chip, port);
2688 if (err)
2689 return err;
2690 }
Guenter Roeckd827e882015-03-26 18:36:29 -07002691
Vivien Didelot207afda2016-04-14 14:42:09 -04002692 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002693 * database, and allow bidirectional communication between the
2694 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07002695 */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002696 err = mv88e6xxx_port_set_fid(chip, port, 0);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002697 if (err)
2698 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002699
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002700 err = mv88e6xxx_port_vlan_map(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002701 if (err)
2702 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002703
2704 /* Default VLAN ID and priority: don't set a default VLAN
2705 * ID, and set the default packet priority to zero.
2706 */
Vivien Didelotb7929fb2017-06-12 12:37:40 -04002707 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
Andrew Lunndbde9e62015-05-06 01:09:48 +02002708}
2709
Andrew Lunn2a550ae2020-07-11 22:32:05 +02002710static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2711{
2712 struct mv88e6xxx_chip *chip = ds->priv;
2713
2714 if (chip->info->ops->port_set_jumbo_size)
2715 return 10240;
Chris Packham1baf0fa2020-07-24 11:21:22 +12002716 else if (chip->info->ops->set_max_frame_size)
2717 return 1632;
Andrew Lunn2a550ae2020-07-11 22:32:05 +02002718 return 1522;
2719}
2720
2721static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2722{
2723 struct mv88e6xxx_chip *chip = ds->priv;
2724 int ret = 0;
2725
2726 mv88e6xxx_reg_lock(chip);
2727 if (chip->info->ops->port_set_jumbo_size)
2728 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
Chris Packham1baf0fa2020-07-24 11:21:22 +12002729 else if (chip->info->ops->set_max_frame_size)
2730 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
Andrew Lunn2a550ae2020-07-11 22:32:05 +02002731 else
2732 if (new_mtu > 1522)
2733 ret = -EINVAL;
2734 mv88e6xxx_reg_unlock(chip);
2735
2736 return ret;
2737}
2738
Andrew Lunn04aca992017-05-26 01:03:24 +02002739static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2740 struct phy_device *phydev)
2741{
2742 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot523a8902017-05-26 18:02:42 -04002743 int err;
Andrew Lunn04aca992017-05-26 01:03:24 +02002744
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002745 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04002746 err = mv88e6xxx_serdes_power(chip, port, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002747 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02002748
2749 return err;
2750}
2751
Andrew Lunn75104db2019-02-24 20:44:43 +01002752static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
Andrew Lunn04aca992017-05-26 01:03:24 +02002753{
2754 struct mv88e6xxx_chip *chip = ds->priv;
2755
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002756 mv88e6xxx_reg_lock(chip);
Vivien Didelot523a8902017-05-26 18:02:42 -04002757 if (mv88e6xxx_serdes_power(chip, port, false))
2758 dev_err(chip->dev, "failed to power off SERDES\n");
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002759 mv88e6xxx_reg_unlock(chip);
Andrew Lunn04aca992017-05-26 01:03:24 +02002760}
2761
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002762static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2763 unsigned int ageing_time)
2764{
Vivien Didelot04bed142016-08-31 18:06:13 -04002765 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002766 int err;
2767
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002768 mv88e6xxx_reg_lock(chip);
Vivien Didelot720c6342017-03-11 16:12:48 -05002769 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002770 mv88e6xxx_reg_unlock(chip);
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002771
2772 return err;
2773}
2774
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002775static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04002776{
2777 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04002778
Andrew Lunnde2273872016-11-21 23:27:01 +01002779 /* Initialize the statistics unit */
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002780 if (chip->info->ops->stats_set_histogram) {
2781 err = chip->info->ops->stats_set_histogram(chip);
2782 if (err)
2783 return err;
2784 }
Andrew Lunnde2273872016-11-21 23:27:01 +01002785
Andrew Lunn40cff8f2017-11-10 00:36:41 +01002786 return mv88e6xxx_g1_stats_clear(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04002787}
2788
Andrew Lunnea890982019-01-09 00:24:03 +01002789/* Check if the errata has already been applied. */
2790static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2791{
2792 int port;
2793 int err;
2794 u16 val;
2795
2796 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02002797 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
Andrew Lunnea890982019-01-09 00:24:03 +01002798 if (err) {
2799 dev_err(chip->dev,
2800 "Error reading hidden register: %d\n", err);
2801 return false;
2802 }
2803 if (val != 0x01c0)
2804 return false;
2805 }
2806
2807 return true;
2808}
2809
2810/* The 6390 copper ports have an errata which require poking magic
2811 * values into undocumented hidden registers and then performing a
2812 * software reset.
2813 */
2814static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2815{
2816 int port;
2817 int err;
2818
2819 if (mv88e6390_setup_errata_applied(chip))
2820 return 0;
2821
2822 /* Set the ports into blocking mode */
2823 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2824 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2825 if (err)
2826 return err;
2827 }
2828
2829 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
Marek Behún60907012019-08-26 23:31:51 +02002830 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
Andrew Lunnea890982019-01-09 00:24:03 +01002831 if (err)
2832 return err;
2833 }
2834
2835 return mv88e6xxx_software_reset(chip);
2836}
2837
Andrew Lunn23e8b472019-10-25 01:03:52 +02002838static void mv88e6xxx_teardown(struct dsa_switch *ds)
2839{
2840 mv88e6xxx_teardown_devlink_params(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01002841 dsa_devlink_resources_unregister(ds);
Andrew Lunnbfb25542020-09-18 21:11:07 +02002842 mv88e6xxx_teardown_devlink_regions(ds);
Andrew Lunn23e8b472019-10-25 01:03:52 +02002843}
2844
Vivien Didelotf81ec902016-05-09 13:22:58 -04002845static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07002846{
Vivien Didelot04bed142016-08-31 18:06:13 -04002847 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002848 u8 cmode;
Vivien Didelot552238b2016-05-09 13:22:49 -04002849 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002850 int i;
2851
Vivien Didelotfad09c72016-06-21 12:28:20 -04002852 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002853 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002854
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002855 mv88e6xxx_reg_lock(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002856
Andrew Lunnea890982019-01-09 00:24:03 +01002857 if (chip->info->ops->setup_errata) {
2858 err = chip->info->ops->setup_errata(chip);
2859 if (err)
2860 goto unlock;
2861 }
2862
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002863 /* Cache the cmode of each port. */
2864 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2865 if (chip->info->ops->port_get_cmode) {
2866 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2867 if (err)
Dan Carpentere29129f2018-08-14 12:09:05 +03002868 goto unlock;
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02002869
2870 chip->ports[i].cmode = cmode;
2871 }
2872 }
2873
Vivien Didelot97299342016-07-18 20:45:30 -04002874 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002875 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelotb759f522019-08-19 16:00:52 -04002876 if (dsa_is_unused_port(ds, i))
2877 continue;
2878
Hubert Feursteinc8574862019-07-31 10:23:48 +02002879 /* Prevent the use of an invalid port. */
Vivien Didelotb759f522019-08-19 16:00:52 -04002880 if (mv88e6xxx_is_invalid_port(chip, i)) {
Hubert Feursteinc8574862019-07-31 10:23:48 +02002881 dev_err(chip->dev, "port %d is invalid\n", i);
2882 err = -EINVAL;
2883 goto unlock;
2884 }
2885
Vivien Didelot97299342016-07-18 20:45:30 -04002886 err = mv88e6xxx_setup_port(chip, i);
2887 if (err)
2888 goto unlock;
2889 }
2890
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04002891 err = mv88e6xxx_irl_setup(chip);
2892 if (err)
2893 goto unlock;
2894
Vivien Didelot04a69a12017-10-13 14:18:05 -04002895 err = mv88e6xxx_mac_setup(chip);
2896 if (err)
2897 goto unlock;
2898
Vivien Didelot1b17aed2017-05-26 18:03:05 -04002899 err = mv88e6xxx_phy_setup(chip);
2900 if (err)
2901 goto unlock;
2902
Vivien Didelotb486d7c2017-05-01 14:05:13 -04002903 err = mv88e6xxx_vtu_setup(chip);
2904 if (err)
2905 goto unlock;
2906
Vivien Didelot81228992017-03-30 17:37:08 -04002907 err = mv88e6xxx_pvt_setup(chip);
2908 if (err)
2909 goto unlock;
2910
Vivien Didelota2ac29d2017-03-11 16:12:49 -05002911 err = mv88e6xxx_atu_setup(chip);
2912 if (err)
2913 goto unlock;
2914
Andrew Lunn87fa8862017-11-09 22:29:56 +01002915 err = mv88e6xxx_broadcast_setup(chip, 0);
2916 if (err)
2917 goto unlock;
2918
Vivien Didelot9e907d72017-07-17 13:03:43 -04002919 err = mv88e6xxx_pot_setup(chip);
2920 if (err)
2921 goto unlock;
2922
Vivien Didelot9e5baf92018-05-09 11:38:51 -04002923 err = mv88e6xxx_rmu_setup(chip);
2924 if (err)
2925 goto unlock;
2926
Vivien Didelot51c901a2017-07-17 13:03:41 -04002927 err = mv88e6xxx_rsvd2cpu_setup(chip);
2928 if (err)
2929 goto unlock;
Andrew Lunn6e55f692016-12-03 04:45:16 +01002930
Vivien Didelotb28f8722018-04-26 21:56:44 -04002931 err = mv88e6xxx_trunk_setup(chip);
2932 if (err)
2933 goto unlock;
2934
Vivien Didelotc7f047b2018-04-26 21:56:45 -04002935 err = mv88e6xxx_devmap_setup(chip);
2936 if (err)
2937 goto unlock;
2938
Vivien Didelot93e18d62018-05-11 17:16:35 -04002939 err = mv88e6xxx_pri_setup(chip);
2940 if (err)
2941 goto unlock;
2942
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01002943 /* Setup PTP Hardware Clock and timestamping */
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01002944 if (chip->info->ptp_support) {
2945 err = mv88e6xxx_ptp_setup(chip);
2946 if (err)
2947 goto unlock;
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01002948
2949 err = mv88e6xxx_hwtstamp_setup(chip);
2950 if (err)
2951 goto unlock;
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01002952 }
2953
Vivien Didelot447b1bb2018-05-11 17:16:36 -04002954 err = mv88e6xxx_stats_setup(chip);
2955 if (err)
2956 goto unlock;
2957
Vivien Didelot6b17e862015-08-13 12:52:18 -04002958unlock:
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00002959 mv88e6xxx_reg_unlock(chip);
Andrew Lunndb687a52015-06-20 21:31:29 +02002960
Andrew Lunne0c69ca2019-11-05 01:13:01 +01002961 if (err)
2962 return err;
2963
2964 /* Have to be called without holding the register lock, since
2965 * they take the devlink lock, and we later take the locks in
2966 * the reverse order when getting/setting parameters or
2967 * resource occupancy.
Andrew Lunn23e8b472019-10-25 01:03:52 +02002968 */
Andrew Lunne0c69ca2019-11-05 01:13:01 +01002969 err = mv88e6xxx_setup_devlink_resources(ds);
2970 if (err)
2971 return err;
2972
2973 err = mv88e6xxx_setup_devlink_params(ds);
2974 if (err)
Andrew Lunnbfb25542020-09-18 21:11:07 +02002975 goto out_resources;
2976
2977 err = mv88e6xxx_setup_devlink_regions(ds);
2978 if (err)
2979 goto out_params;
2980
2981 return 0;
2982
2983out_params:
2984 mv88e6xxx_teardown_devlink_params(ds);
2985out_resources:
2986 dsa_devlink_resources_unregister(ds);
Andrew Lunne0c69ca2019-11-05 01:13:01 +01002987
2988 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002989}
2990
Vivien Didelote57e5e72016-08-15 17:19:00 -04002991static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002992{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002993 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2994 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002995 u16 val;
2996 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002997
Andrew Lunnee26a222017-01-24 14:53:48 +01002998 if (!chip->info->ops->phy_read)
2999 return -EOPNOTSUPP;
3000
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003001 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003002 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003003 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003004
Andrew Lunnda9f3302017-02-01 03:40:05 +01003005 if (reg == MII_PHYSID2) {
Andrew Lunnddc49ac2018-11-12 18:51:01 +01003006 /* Some internal PHYs don't have a model number. */
3007 if (chip->info->family != MV88E6XXX_FAMILY_6165)
3008 /* Then there is the 6165 family. It gets is
3009 * PHYs correct. But it can also have two
3010 * SERDES interfaces in the PHY address
3011 * space. And these don't have a model
3012 * number. But they are not PHYs, so we don't
3013 * want to give them something a PHY driver
3014 * will recognise.
3015 *
3016 * Use the mv88e6390 family model number
3017 * instead, for anything which really could be
3018 * a PHY,
3019 */
3020 if (!(val & 0x3f0))
3021 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
Andrew Lunnda9f3302017-02-01 03:40:05 +01003022 }
3023
Vivien Didelote57e5e72016-08-15 17:19:00 -04003024 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003025}
3026
Vivien Didelote57e5e72016-08-15 17:19:00 -04003027static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003028{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003029 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3030 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04003031 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003032
Andrew Lunnee26a222017-01-24 14:53:48 +01003033 if (!chip->info->ops->phy_write)
3034 return -EOPNOTSUPP;
3035
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003036 mv88e6xxx_reg_lock(chip);
Andrew Lunnee26a222017-01-24 14:53:48 +01003037 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003038 mv88e6xxx_reg_unlock(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003039
3040 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003041}
3042
Vivien Didelotfad09c72016-06-21 12:28:20 -04003043static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01003044 struct device_node *np,
3045 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02003046{
3047 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003048 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003049 struct mii_bus *bus;
3050 int err;
3051
Andrew Lunn2510bab2018-02-22 01:51:49 +01003052 if (external) {
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003053 mv88e6xxx_reg_lock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003054 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003055 mv88e6xxx_reg_unlock(chip);
Andrew Lunn2510bab2018-02-22 01:51:49 +01003056
3057 if (err)
3058 return err;
3059 }
3060
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003061 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02003062 if (!bus)
3063 return -ENOMEM;
3064
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003065 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003066 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003067 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01003068 INIT_LIST_HEAD(&mdio_bus->list);
3069 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01003070
Andrew Lunnb516d452016-06-04 21:17:06 +02003071 if (np) {
3072 bus->name = np->full_name;
Rob Herringf7ce9102017-07-18 16:43:19 -05003073 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003074 } else {
3075 bus->name = "mv88e6xxx SMI";
3076 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3077 }
3078
3079 bus->read = mv88e6xxx_mdio_read;
3080 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003081 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02003082
Andrew Lunn6f882842018-03-17 20:32:05 +01003083 if (!external) {
3084 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3085 if (err)
3086 return err;
3087 }
3088
Florian Fainelli00e798c2018-05-15 16:56:19 -07003089 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003090 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003091 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunn6f882842018-03-17 20:32:05 +01003092 mv88e6xxx_g2_irq_mdio_free(chip, bus);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003093 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02003094 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003095
3096 if (external)
3097 list_add_tail(&mdio_bus->list, &chip->mdios);
3098 else
3099 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02003100
3101 return 0;
Andrew Lunnb516d452016-06-04 21:17:06 +02003102}
3103
Andrew Lunn3126aee2017-12-07 01:05:57 +01003104static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3105
3106{
3107 struct mv88e6xxx_mdio_bus *mdio_bus;
3108 struct mii_bus *bus;
3109
3110 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3111 bus = mdio_bus->bus;
3112
Andrew Lunn6f882842018-03-17 20:32:05 +01003113 if (!mdio_bus->external)
3114 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3115
Andrew Lunn3126aee2017-12-07 01:05:57 +01003116 mdiobus_unregister(bus);
3117 }
3118}
3119
Andrew Lunna3c53be52017-01-24 14:53:50 +01003120static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3121 struct device_node *np)
3122{
Andrew Lunna3c53be52017-01-24 14:53:50 +01003123 struct device_node *child;
3124 int err;
3125
3126 /* Always register one mdio bus for the internal/default mdio
3127 * bus. This maybe represented in the device tree, but is
3128 * optional.
3129 */
3130 child = of_get_child_by_name(np, "mdio");
3131 err = mv88e6xxx_mdio_register(chip, child, false);
3132 if (err)
3133 return err;
3134
3135 /* Walk the device tree, and see if there are any other nodes
3136 * which say they are compatible with the external mdio
3137 * bus.
3138 */
3139 for_each_available_child_of_node(np, child) {
Andrew Lunnceb96fa2020-09-01 04:32:57 +02003140 if (of_device_is_compatible(
3141 child, "marvell,mv88e6xxx-mdio-external")) {
Andrew Lunna3c53be52017-01-24 14:53:50 +01003142 err = mv88e6xxx_mdio_register(chip, child, true);
Andrew Lunn3126aee2017-12-07 01:05:57 +01003143 if (err) {
3144 mv88e6xxx_mdios_unregister(chip);
Nishka Dasgupta78e42042019-07-23 16:13:07 +05303145 of_node_put(child);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003146 return err;
Andrew Lunn3126aee2017-12-07 01:05:57 +01003147 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01003148 }
3149 }
3150
3151 return 0;
3152}
3153
Vivien Didelot855b1932016-07-20 18:18:35 -04003154static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3155{
Vivien Didelot04bed142016-08-31 18:06:13 -04003156 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003157
3158 return chip->eeprom_len;
3159}
3160
Vivien Didelot855b1932016-07-20 18:18:35 -04003161static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3162 struct ethtool_eeprom *eeprom, u8 *data)
3163{
Vivien Didelot04bed142016-08-31 18:06:13 -04003164 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003165 int err;
3166
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003167 if (!chip->info->ops->get_eeprom)
3168 return -EOPNOTSUPP;
3169
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003170 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003171 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003172 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003173
3174 if (err)
3175 return err;
3176
3177 eeprom->magic = 0xc3ec4951;
3178
3179 return 0;
3180}
3181
Vivien Didelot855b1932016-07-20 18:18:35 -04003182static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3183 struct ethtool_eeprom *eeprom, u8 *data)
3184{
Vivien Didelot04bed142016-08-31 18:06:13 -04003185 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04003186 int err;
3187
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003188 if (!chip->info->ops->set_eeprom)
3189 return -EOPNOTSUPP;
3190
Vivien Didelot855b1932016-07-20 18:18:35 -04003191 if (eeprom->magic != 0xc3ec4951)
3192 return -EINVAL;
3193
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003194 mv88e6xxx_reg_lock(chip);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003195 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00003196 mv88e6xxx_reg_unlock(chip);
Vivien Didelot855b1932016-07-20 18:18:35 -04003197
3198 return err;
3199}
3200
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003201static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003202 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003203 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3204 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003205 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003206 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003207 .phy_read = mv88e6185_phy_ppu_read,
3208 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003209 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003210 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003211 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003212 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003213 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003214 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003215 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003216 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003217 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003218 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003219 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003220 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003221 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003222 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003223 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3224 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003225 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003226 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3227 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003228 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003229 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003230 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003231 .ppu_enable = mv88e6185_g1_ppu_enable,
3232 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003233 .reset = mv88e6185_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003234 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003235 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003236 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003237 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003238 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003239};
3240
3241static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003242 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003243 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3244 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003245 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003246 .phy_read = mv88e6185_phy_ppu_read,
3247 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003248 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003249 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003250 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003251 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunna23b2962017-02-04 20:15:28 +01003252 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003253 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003254 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003255 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003256 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003257 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3258 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003259 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003260 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003261 .ppu_enable = mv88e6185_g1_ppu_enable,
3262 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003263 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003264 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003265 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003266 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003267 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003268};
3269
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003270static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01003271 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003272 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3273 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003274 .irl_init_all = mv88e6352_g2_irl_init_all,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003275 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3276 .phy_read = mv88e6xxx_g2_smi_phy_read,
3277 .phy_write = mv88e6xxx_g2_smi_phy_write,
3278 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003279 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003280 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003281 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003282 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003283 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01003284 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003285 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003286 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003287 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003288 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003289 .port_setup_message_port = mv88e6xxx_setup_message_port,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003290 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003291 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003292 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3293 .stats_get_strings = mv88e6095_stats_get_strings,
3294 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003295 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3296 .set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01003297 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003298 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003299 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003300 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003301 .rmu_disable = mv88e6085_g1_rmu_disable,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003302 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003303 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003304 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003305 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003306};
3307
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003308static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003309 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003310 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3311 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003312 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003313 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003314 .phy_read = mv88e6xxx_g2_smi_phy_read,
3315 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003316 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003317 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003318 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003319 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003320 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003321 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003322 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003323 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn0ac64c32017-06-02 23:22:46 +02003324 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003325 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003326 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3327 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003328 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003329 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3330 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003331 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003332 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003333 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003334 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003335 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3336 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003337 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003338 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003339 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003340 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003341};
3342
3343static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003344 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003345 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3346 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003347 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003348 .phy_read = mv88e6185_phy_ppu_read,
3349 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003350 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003351 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003352 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003353 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003354 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003355 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01003356 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Vivien Didelotcd782652017-06-08 18:34:13 -04003357 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003358 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003359 .port_pause_limit = mv88e6097_port_pause_limit,
Andrew Lunn54186b92018-08-09 15:38:37 +02003360 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003361 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003362 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003363 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003364 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003365 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3366 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003367 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003368 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3369 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003370 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003371 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003372 .ppu_enable = mv88e6185_g1_ppu_enable,
Vivien Didelot02317e62018-05-09 11:38:49 -04003373 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003374 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003375 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003376 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003377 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003378 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003379};
3380
Vivien Didelot990e27b2017-03-28 13:50:32 -04003381static const struct mv88e6xxx_ops mv88e6141_ops = {
3382 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003383 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3384 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003385 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003386 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3387 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3388 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3389 .phy_read = mv88e6xxx_g2_smi_phy_read,
3390 .phy_write = mv88e6xxx_g2_smi_phy_write,
3391 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003392 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003393 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003394 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003395 .port_tag_remap = mv88e6095_port_tag_remap,
3396 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3397 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3398 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003399 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003400 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003401 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003402 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3403 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003404 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02003405 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003406 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003407 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003408 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003409 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3410 .stats_get_strings = mv88e6320_stats_get_strings,
3411 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003412 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3413 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003414 .watchdog_ops = &mv88e6390_watchdog_ops,
3415 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003416 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003417 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003418 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003419 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02003420 .serdes_power = mv88e6390_serdes_power,
3421 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003422 /* Check status register pause & lpa register */
3423 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3424 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3425 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3426 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003427 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003428 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003429 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003430 .gpio_ops = &mv88e6352_gpio_ops,
Marek Behúne3af71a2019-02-25 12:39:55 +01003431 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003432};
3433
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003434static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003435 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003436 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3437 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003438 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003439 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnec8378b2017-06-02 23:22:45 +02003440 .phy_read = mv88e6xxx_g2_smi_phy_read,
3441 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003442 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003443 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003444 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003445 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003446 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003447 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003448 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003449 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003450 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003451 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003452 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003453 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003454 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna6da21b2019-03-01 23:43:39 +01003455 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003456 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003457 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3458 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003459 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003460 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3461 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003462 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003463 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003464 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003465 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003466 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3467 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003468 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003469 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003470 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003471 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003472 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003473};
3474
3475static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003476 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003477 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3478 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003479 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01003481 .phy_read = mv88e6165_phy_read,
3482 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003483 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003484 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003485 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003486 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003487 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003488 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003489 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003490 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003491 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3492 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003493 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003494 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3495 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003496 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003497 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003498 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003499 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003500 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3501 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003502 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003503 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Andrew Lunna469a612018-07-18 22:38:21 +02003504 .avb_ops = &mv88e6165_avb_ops,
Andrew Lunndfa54342018-07-18 22:38:22 +02003505 .ptp_ops = &mv88e6165_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003506 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003507};
3508
3509static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003510 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003511 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3512 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003513 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003514 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003515 .phy_read = mv88e6xxx_g2_smi_phy_read,
3516 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003517 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003518 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003519 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003520 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003521 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003522 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003523 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003524 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003525 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003526 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003527 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003528 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003529 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003530 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003531 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003532 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003533 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3534 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003535 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003536 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3537 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003538 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003539 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003540 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003541 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003542 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3543 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003544 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003545 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003546 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003547};
3548
3549static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003550 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003551 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3552 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003553 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003554 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3555 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003557 .phy_read = mv88e6xxx_g2_smi_phy_read,
3558 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003559 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003560 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003561 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003562 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003563 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003564 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003565 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003566 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003567 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003568 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003569 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003570 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003571 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003572 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003573 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003574 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003575 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003576 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3577 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003578 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003579 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3580 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003581 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003582 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003583 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003584 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003585 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003586 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3587 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003588 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003589 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003590 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003591 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3592 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3593 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3594 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003595 .serdes_power = mv88e6352_serdes_power,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003596 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3597 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003598 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003599 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003600};
3601
3602static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003603 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003604 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3605 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003606 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003607 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003608 .phy_read = mv88e6xxx_g2_smi_phy_read,
3609 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003610 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003611 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003612 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003613 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003614 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003615 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003616 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003617 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003618 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003619 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003620 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003621 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003622 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003623 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003624 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003625 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003626 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3627 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003628 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003629 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3630 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003631 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003632 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003633 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003634 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003635 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3636 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003637 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003638 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003639 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003640};
3641
3642static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003643 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003644 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3645 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003646 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003647 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3648 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003649 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003650 .phy_read = mv88e6xxx_g2_smi_phy_read,
3651 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003652 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003653 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003654 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003655 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003656 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003657 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003658 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003659 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003660 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003661 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003662 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003663 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003664 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003665 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003666 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003667 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003668 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003669 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3670 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003671 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003672 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3673 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003674 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003675 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003676 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003677 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003678 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003679 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3680 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003681 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003682 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003683 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003684 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3685 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3686 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3687 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003688 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003689 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003690 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003691 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003692 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3693 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003694 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003695 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003696};
3697
3698static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003699 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003700 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3701 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003702 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelot7e20cfb2017-05-26 18:03:06 -04003703 .phy_read = mv88e6185_phy_ppu_read,
3704 .phy_write = mv88e6185_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003705 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00003706 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003707 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003708 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunnef70b112016-12-03 04:45:18 +01003709 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01003710 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn54186b92018-08-09 15:38:37 +02003711 .port_set_pause = mv88e6185_port_set_pause,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003712 .port_get_cmode = mv88e6185_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003713 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003714 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003715 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003716 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3717 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003718 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003719 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3720 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003721 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003722 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
Vivien Didelot02317e62018-05-09 11:38:49 -04003723 .set_cascade_port = mv88e6185_g1_set_cascade_port,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003724 .ppu_enable = mv88e6185_g1_ppu_enable,
3725 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003726 .reset = mv88e6185_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003727 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003728 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02003729 .phylink_validate = mv88e6185_phylink_validate,
Chris Packham1baf0fa2020-07-24 11:21:22 +12003730 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003731};
3732
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003733static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003734 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003735 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003736 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003737 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3738 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003739 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3740 .phy_read = mv88e6xxx_g2_smi_phy_read,
3741 .phy_write = mv88e6xxx_g2_smi_phy_write,
3742 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003743 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003744 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003745 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003746 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003747 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003748 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003749 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003750 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12003751 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04003752 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003753 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003754 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003755 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003756 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003757 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01003758 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003759 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003760 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3761 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003762 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003763 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3764 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003765 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003766 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003767 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003768 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003769 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003770 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3771 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04003772 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3773 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003774 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02003775 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003776 /* Check status register pause & lpa register */
3777 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3778 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3779 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3780 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003781 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003782 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003783 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01003784 .serdes_get_strings = mv88e6390_serdes_get_strings,
3785 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01003786 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3787 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003788 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003789 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003790};
3791
3792static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003793 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003794 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003795 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003796 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3797 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003798 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3799 .phy_read = mv88e6xxx_g2_smi_phy_read,
3800 .phy_write = mv88e6xxx_g2_smi_phy_write,
3801 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003802 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003803 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003804 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003805 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003806 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003807 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003808 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003809 .port_set_ether_type = mv88e6351_port_set_ether_type,
Chris Packhame8b34c62020-07-24 11:21:21 +12003810 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot08984322017-06-08 18:34:12 -04003811 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003814 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003815 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003816 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01003817 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003818 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003819 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3820 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003821 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003822 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3823 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003824 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003825 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003826 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003827 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003828 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003829 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3830 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04003831 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3832 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02003833 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02003834 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003835 /* Check status register pause & lpa register */
3836 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3837 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3838 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3839 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003840 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003841 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003842 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01003843 .serdes_get_strings = mv88e6390_serdes_get_strings,
3844 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01003845 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3846 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003847 .gpio_ops = &mv88e6352_gpio_ops,
Russell King6c422e32018-08-09 15:38:39 +02003848 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003849};
3850
3851static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003852 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01003853 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003854 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003855 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3856 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003857 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3858 .phy_read = mv88e6xxx_g2_smi_phy_read,
3859 .phy_write = mv88e6xxx_g2_smi_phy_write,
3860 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003861 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003862 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01003863 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003864 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003865 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003866 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003867 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04003868 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003869 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003870 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003871 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01003872 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003873 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01003874 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003875 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003876 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3877 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003878 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003879 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3880 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003881 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003882 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003883 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003884 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003885 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003886 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3887 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04003888 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3889 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02003890 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02003891 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003892 /* Check status register pause & lpa register */
3893 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3894 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3895 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3896 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003897 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003898 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003899 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01003900 .serdes_get_strings = mv88e6390_serdes_get_strings,
3901 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01003902 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3903 .serdes_get_regs = mv88e6390_serdes_get_regs,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003904 .avb_ops = &mv88e6390_avb_ops,
3905 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003906 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003907};
3908
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003909static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003910 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04003911 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3912 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04003913 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003914 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3915 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003916 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003917 .phy_read = mv88e6xxx_g2_smi_phy_read,
3918 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003919 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003920 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003921 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003922 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04003923 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003924 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003925 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003926 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04003927 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01003928 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04003929 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003930 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003931 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02003932 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02003933 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003934 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01003935 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003936 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3937 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003938 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04003939 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3940 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003941 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04003942 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04003943 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003944 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04003945 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02003946 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3947 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04003948 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04003949 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04003950 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00003951 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3952 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3953 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3954 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02003955 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04003956 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04003957 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04003958 .serdes_irq_status = mv88e6352_serdes_irq_status,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01003959 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3960 .serdes_get_regs = mv88e6352_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01003961 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01003962 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02003963 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02003964 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003965};
3966
Rasmus Villemoes1f718362019-06-04 07:34:32 +00003967static const struct mv88e6xxx_ops mv88e6250_ops = {
3968 /* MV88E6XXX_FAMILY_6250 */
3969 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3970 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3971 .irl_init_all = mv88e6352_g2_irl_init_all,
3972 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3973 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3974 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3975 .phy_read = mv88e6xxx_g2_smi_phy_read,
3976 .phy_write = mv88e6xxx_g2_smi_phy_write,
3977 .port_set_link = mv88e6xxx_port_set_link,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00003978 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00003979 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00003980 .port_tag_remap = mv88e6095_port_tag_remap,
3981 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3982 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3983 .port_set_ether_type = mv88e6351_port_set_ether_type,
3984 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3985 .port_pause_limit = mv88e6097_port_pause_limit,
3986 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00003987 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3988 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3989 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
3990 .stats_get_strings = mv88e6250_stats_get_strings,
3991 .stats_get_stats = mv88e6250_stats_get_stats,
3992 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3993 .set_egress_port = mv88e6095_g1_set_egress_port,
3994 .watchdog_ops = &mv88e6250_watchdog_ops,
3995 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3996 .pot_clear = mv88e6xxx_g2_pot_clear,
3997 .reset = mv88e6250_g1_reset,
3998 .vtu_getnext = mv88e6250_g1_vtu_getnext,
3999 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
Hubert Feurstein71509612019-07-31 10:23:51 +02004000 .avb_ops = &mv88e6352_avb_ops,
4001 .ptp_ops = &mv88e6250_ptp_ops,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004002 .phylink_validate = mv88e6065_phylink_validate,
4003};
4004
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004005static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004006 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004007 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004008 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004009 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4010 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004011 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4012 .phy_read = mv88e6xxx_g2_smi_phy_read,
4013 .phy_write = mv88e6xxx_g2_smi_phy_write,
4014 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004015 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004016 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004017 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004018 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004019 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004020 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004021 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004022 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelot08984322017-06-08 18:34:12 -04004023 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004024 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004025 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004026 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004027 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004028 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004029 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004030 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004031 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4032 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004033 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004034 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4035 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004036 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004037 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004038 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004039 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004040 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004041 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4042 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004043 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4044 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004045 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004046 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004047 /* Check status register pause & lpa register */
4048 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4049 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4050 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4051 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004052 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004053 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004054 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004055 .serdes_get_strings = mv88e6390_serdes_get_strings,
4056 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004057 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4058 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004059 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004060 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004061 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004062 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004063};
4064
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004065static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004066 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004067 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4068 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004069 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004070 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4071 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004072 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004073 .phy_read = mv88e6xxx_g2_smi_phy_read,
4074 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004075 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004076 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004077 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004078 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004079 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004080 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004081 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004082 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004083 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004084 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004085 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004086 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004087 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004088 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004089 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004090 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4091 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004092 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004093 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4094 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004095 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004096 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004097 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004098 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004099 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004100 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004101 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004102 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004103 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004104 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004105};
4106
4107static const struct mv88e6xxx_ops mv88e6321_ops = {
Vivien Didelotbd807202017-07-17 13:03:37 -04004108 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004109 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4110 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004111 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004112 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4113 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004114 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004115 .phy_read = mv88e6xxx_g2_smi_phy_read,
4116 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004117 .port_set_link = mv88e6xxx_port_set_link,
Russell Kingf365c6f2020-03-14 10:15:53 +00004118 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004119 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004120 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004121 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004122 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004123 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004124 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004125 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004126 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004127 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004128 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004129 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004130 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004131 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004132 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4133 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004134 .stats_get_stats = mv88e6320_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004135 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4136 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn9c7f37e2018-12-19 18:28:54 +01004137 .watchdog_ops = &mv88e6390_watchdog_ops,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004138 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004139 .vtu_getnext = mv88e6185_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004140 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004141 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004142 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004143 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004144 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004145};
4146
Vivien Didelot16e329a2017-03-28 13:50:33 -04004147static const struct mv88e6xxx_ops mv88e6341_ops = {
4148 /* MV88E6XXX_FAMILY_6341 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004149 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4150 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004151 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004152 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4153 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4154 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4155 .phy_read = mv88e6xxx_g2_smi_phy_read,
4156 .phy_write = mv88e6xxx_g2_smi_phy_write,
4157 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004158 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004159 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004160 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004161 .port_tag_remap = mv88e6095_port_tag_remap,
4162 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4163 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4164 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004165 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004166 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004167 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004168 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4169 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004170 .port_get_cmode = mv88e6352_port_get_cmode,
Marek Behún7a3007d2019-08-26 23:31:55 +02004171 .port_set_cmode = mv88e6341_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004172 .port_setup_message_port = mv88e6xxx_setup_message_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004173 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004174 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004175 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4176 .stats_get_strings = mv88e6320_stats_get_strings,
4177 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004178 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4179 .set_egress_port = mv88e6390_g1_set_egress_port,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004180 .watchdog_ops = &mv88e6390_watchdog_ops,
4181 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004182 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004183 .reset = mv88e6352_g1_reset,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004184 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004185 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004186 .serdes_power = mv88e6390_serdes_power,
4187 .serdes_get_lane = mv88e6341_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004188 /* Check status register pause & lpa register */
4189 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4190 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4191 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4192 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004193 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004194 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004195 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004196 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004197 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004198 .ptp_ops = &mv88e6352_ptp_ops,
Marek Behúne3af71a2019-02-25 12:39:55 +01004199 .phylink_validate = mv88e6341_phylink_validate,
Vivien Didelot16e329a2017-03-28 13:50:33 -04004200};
4201
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004202static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004203 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004204 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4205 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004206 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004207 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004208 .phy_read = mv88e6xxx_g2_smi_phy_read,
4209 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004210 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004211 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004212 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004213 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004214 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004215 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004216 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004217 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004218 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004219 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004220 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004221 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004222 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004223 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004224 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004225 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004226 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4227 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004228 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004229 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4230 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004231 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004232 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004233 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004234 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004235 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4236 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004237 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004238 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Russell King6c422e32018-08-09 15:38:39 +02004239 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004240};
4241
4242static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004243 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004244 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4245 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004246 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004248 .phy_read = mv88e6xxx_g2_smi_phy_read,
4249 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004250 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01004251 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004252 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004253 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004254 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004255 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004256 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004257 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004258 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004259 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004260 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004261 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004262 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004263 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004264 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004265 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004266 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4267 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004268 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004269 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4270 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004271 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004272 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004273 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004274 .reset = mv88e6352_g1_reset,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004275 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4276 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004277 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004278 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004279 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004280 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004281 .phylink_validate = mv88e6185_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004282};
4283
4284static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004285 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelot93e18d62018-05-11 17:16:35 -04004286 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4287 .ip_pri_map = mv88e6085_g1_ip_pri_map,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004288 .irl_init_all = mv88e6352_g2_irl_init_all,
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004289 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4290 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04004291 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004292 .phy_read = mv88e6xxx_g2_smi_phy_read,
4293 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01004294 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelota0a0f622016-11-04 03:23:34 +01004295 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004296 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004297 .port_tag_remap = mv88e6095_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004298 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004299 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004300 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004301 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004302 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004303 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004304 .port_pause_limit = mv88e6097_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004305 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004306 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004307 .port_get_cmode = mv88e6352_port_get_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004308 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01004309 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunn40cff8f2017-11-10 00:36:41 +01004310 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004311 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4312 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01004313 .stats_get_stats = mv88e6095_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004314 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4315 .set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01004316 .watchdog_ops = &mv88e6097_watchdog_ops,
Vivien Didelot51c901a2017-07-17 13:03:41 -04004317 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004318 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004319 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004320 .rmu_disable = mv88e6352_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004321 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4322 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelotf1394b782017-05-01 14:05:22 -04004323 .vtu_getnext = mv88e6352_g1_vtu_getnext,
Vivien Didelot0ad5daf2017-05-01 14:05:23 -04004324 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
Vivien Didelot9db4a722019-08-31 16:18:31 -04004325 .serdes_get_lane = mv88e6352_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004326 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4327 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4328 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4329 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
Andrew Lunn6d917822017-05-26 01:03:21 +02004330 .serdes_power = mv88e6352_serdes_power,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004331 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004332 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004333 .serdes_irq_status = mv88e6352_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004334 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004335 .avb_ops = &mv88e6352_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004336 .ptp_ops = &mv88e6352_ptp_ops,
Andrew Lunncda9f4a2018-03-01 02:02:31 +01004337 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4338 .serdes_get_strings = mv88e6352_serdes_get_strings,
4339 .serdes_get_stats = mv88e6352_serdes_get_stats,
Andrew Lunnd3f88a22020-02-16 18:54:14 +01004340 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4341 .serdes_get_regs = mv88e6352_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004342 .phylink_validate = mv88e6352_phylink_validate,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004343};
4344
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004345static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004346 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004347 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004348 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004349 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4350 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004351 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4352 .phy_read = mv88e6xxx_g2_smi_phy_read,
4353 .phy_write = mv88e6xxx_g2_smi_phy_write,
4354 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004355 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004356 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004357 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004358 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004359 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004360 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004361 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004362 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004363 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004364 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004365 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004366 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004367 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004368 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnfdc71ee2018-11-11 00:32:15 +01004369 .port_set_cmode = mv88e6390_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004370 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004371 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004372 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004373 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4374 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004375 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004376 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4377 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004378 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004379 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004380 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004381 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004382 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004383 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4384 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004385 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4386 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Andrew Lunn6335e9f2017-05-26 01:03:23 +02004387 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004388 .serdes_get_lane = mv88e6390_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004389 /* Check status register pause & lpa register */
4390 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4391 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4392 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4393 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004394 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004395 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004396 .serdes_irq_status = mv88e6390_serdes_irq_status,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004397 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004398 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004399 .ptp_ops = &mv88e6352_ptp_ops,
Nikita Yushchenko0df95282019-12-25 08:22:38 +03004400 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4401 .serdes_get_strings = mv88e6390_serdes_get_strings,
4402 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004403 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4404 .serdes_get_regs = mv88e6390_serdes_get_regs,
Russell King6c422e32018-08-09 15:38:39 +02004405 .phylink_validate = mv88e6390_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004406};
4407
4408static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01004409 /* MV88E6XXX_FAMILY_6390 */
Andrew Lunnea890982019-01-09 00:24:03 +01004410 .setup_errata = mv88e6390_setup_errata,
Vivien Didelotcd8da8b2017-06-19 10:55:36 -04004411 .irl_init_all = mv88e6390_g2_irl_init_all,
Vivien Didelot98fc3c62017-01-12 18:07:16 -05004412 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4413 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004414 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4415 .phy_read = mv88e6xxx_g2_smi_phy_read,
4416 .phy_write = mv88e6xxx_g2_smi_phy_write,
4417 .port_set_link = mv88e6xxx_port_set_link,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004418 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
Russell Kingf365c6f2020-03-14 10:15:53 +00004419 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
Andrew Lunn7cbbee02019-03-08 01:21:27 +01004420 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
Andrew Lunnef0a7312016-12-03 04:35:16 +01004421 .port_tag_remap = mv88e6390_port_tag_remap,
Vivien Didelotf3a2cd32019-09-07 16:00:48 -04004422 .port_set_policy = mv88e6352_port_set_policy,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004423 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05004424 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01004425 .port_set_ether_type = mv88e6351_port_set_ether_type,
Vivien Didelotcd782652017-06-08 18:34:13 -04004426 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
Andrew Lunnef70b112016-12-03 04:45:18 +01004427 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Vivien Didelot08984322017-06-08 18:34:12 -04004428 .port_pause_limit = mv88e6390_port_pause_limit,
Vivien Didelotc8c94892017-03-11 16:13:01 -05004429 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05004430 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn2d2e1dd2018-08-09 15:38:45 +02004431 .port_get_cmode = mv88e6352_port_get_cmode,
Andrew Lunnb3dce4d2018-11-11 00:32:14 +01004432 .port_set_cmode = mv88e6390x_port_set_cmode,
Hubert Feurstein121b8fe2019-07-31 10:23:49 +02004433 .port_setup_message_port = mv88e6xxx_setup_message_port,
Andrew Lunn79523472016-11-21 23:27:00 +01004434 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01004435 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01004436 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4437 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01004438 .stats_get_stats = mv88e6390_stats_get_stats,
Vivien Didelotfa8d1172017-06-08 18:34:11 -04004439 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4440 .set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01004441 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01004442 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot9e907d72017-07-17 13:03:43 -04004443 .pot_clear = mv88e6xxx_g2_pot_clear,
Vivien Didelot17e708b2016-12-05 17:30:27 -05004444 .reset = mv88e6352_g1_reset,
Vivien Didelot9e5baf92018-05-09 11:38:51 -04004445 .rmu_disable = mv88e6390_g1_rmu_disable,
Andrew Lunn23e8b472019-10-25 01:03:52 +02004446 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4447 .atu_set_hash = mv88e6165_g1_atu_set_hash,
Vivien Didelot931d1822017-05-01 14:05:27 -04004448 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4449 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
Marek Behúnd3cf7d82019-08-26 23:31:53 +02004450 .serdes_power = mv88e6390_serdes_power,
Marek Behún17deaf52019-08-26 23:31:52 +02004451 .serdes_get_lane = mv88e6390x_serdes_get_lane,
Russell Kinga5a68582020-03-14 10:15:43 +00004452 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4453 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4454 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4455 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
Vivien Didelot4241ef52019-08-31 16:18:29 -04004456 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
Vivien Didelot61a46b42019-08-31 16:18:34 -04004457 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
Vivien Didelot907b9b92019-08-31 16:18:35 -04004458 .serdes_irq_status = mv88e6390_serdes_irq_status,
Andrew Lunn4262c382020-01-18 19:40:56 +01004459 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4460 .serdes_get_strings = mv88e6390_serdes_get_strings,
4461 .serdes_get_stats = mv88e6390_serdes_get_stats,
Andrew Lunnbf3504c2020-02-16 18:54:15 +01004462 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4463 .serdes_get_regs = mv88e6390_serdes_get_regs,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004464 .gpio_ops = &mv88e6352_gpio_ops,
Brandon Streiff0d632c32018-02-14 01:07:44 +01004465 .avb_ops = &mv88e6390_avb_ops,
Andrew Lunn6d2ac8e2018-07-18 22:38:20 +02004466 .ptp_ops = &mv88e6352_ptp_ops,
Russell King6c422e32018-08-09 15:38:39 +02004467 .phylink_validate = mv88e6390x_phylink_validate,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004468};
4469
Vivien Didelotf81ec902016-05-09 13:22:58 -04004470static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4471 [MV88E6085] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004472 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004473 .family = MV88E6XXX_FAMILY_6097,
4474 .name = "Marvell 88E6085",
4475 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004476 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004477 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01004478 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004479 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004480 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004481 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004482 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004483 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004484 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004485 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004486 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004487 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004488 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004489 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004490 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004491 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004492 },
4493
4494 [MV88E6095] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004495 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004496 .family = MV88E6XXX_FAMILY_6095,
4497 .name = "Marvell 88E6095/88E6095F",
4498 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004499 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004500 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01004501 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004502 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004503 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004504 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004505 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004506 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004507 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004508 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05004509 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004510 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004511 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004512 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004513 },
4514
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004515 [MV88E6097] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004517 .family = MV88E6XXX_FAMILY_6097,
4518 .name = "Marvell 88E6097/88E6097F",
4519 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004520 .num_macs = 8192,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004521 .num_ports = 11,
Andrew Lunnbc393152018-03-17 20:32:04 +01004522 .num_internal_phys = 8,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004523 .max_vid = 4095,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004524 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004525 .phy_base_addr = 0x0,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004526 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004527 .global2_addr = 0x1c,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004528 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01004529 .g1_irqs = 8,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004530 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004531 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004532 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004533 .multi_chip = true,
Stefan Eichenberger2bfcfcd2016-12-05 14:12:42 +01004534 .tag_protocol = DSA_TAG_PROTO_EDSA,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01004535 .ops = &mv88e6097_ops,
4536 },
4537
Vivien Didelotf81ec902016-05-09 13:22:58 -04004538 [MV88E6123] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004540 .family = MV88E6XXX_FAMILY_6165,
4541 .name = "Marvell 88E6123",
4542 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004543 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004544 .num_ports = 3,
Andrew Lunnbc393152018-03-17 20:32:04 +01004545 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004546 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004547 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004548 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004549 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004550 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004551 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004552 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004553 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004554 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004555 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004556 .multi_chip = true,
Andrew Lunn5ebe31d2017-06-07 15:06:19 +02004557 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004558 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004559 },
4560
4561 [MV88E6131] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004563 .family = MV88E6XXX_FAMILY_6185,
4564 .name = "Marvell 88E6131",
4565 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004566 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004567 .num_ports = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004568 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004569 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004570 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004571 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004572 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004573 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004574 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004575 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05004576 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004577 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004578 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004579 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004580 },
4581
Vivien Didelot990e27b2017-03-28 13:50:32 -04004582 [MV88E6141] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004583 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004584 .family = MV88E6XXX_FAMILY_6341,
Uwe Kleine-König79a68b22018-03-20 10:44:40 +01004585 .name = "Marvell 88E6141",
Vivien Didelot990e27b2017-03-28 13:50:32 -04004586 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004587 .num_macs = 2048,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004588 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004589 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004590 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004591 .max_vid = 4095,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004592 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004593 .phy_base_addr = 0x10,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004594 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004595 .global2_addr = 0x1c,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004596 .age_time_coeff = 3750,
4597 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01004598 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004599 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04004600 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004601 .multi_chip = true,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004602 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelot990e27b2017-03-28 13:50:32 -04004603 .ops = &mv88e6141_ops,
4604 },
4605
Vivien Didelotf81ec902016-05-09 13:22:58 -04004606 [MV88E6161] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004607 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004608 .family = MV88E6XXX_FAMILY_6165,
4609 .name = "Marvell 88E6161",
4610 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004611 .num_macs = 1024,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004612 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004613 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004614 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004615 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004616 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004617 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004618 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004619 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004620 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004621 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004622 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004623 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004624 .multi_chip = true,
Andrew Lunn5ebe31d2017-06-07 15:06:19 +02004625 .tag_protocol = DSA_TAG_PROTO_EDSA,
Andrew Lunndfa54342018-07-18 22:38:22 +02004626 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004627 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004628 },
4629
4630 [MV88E6165] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004631 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004632 .family = MV88E6XXX_FAMILY_6165,
4633 .name = "Marvell 88E6165",
4634 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004635 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004636 .num_ports = 6,
Andrew Lunnbc393152018-03-17 20:32:04 +01004637 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004638 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004639 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004640 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004641 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004642 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004643 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004644 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004645 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004646 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004647 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004648 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004649 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunndfa54342018-07-18 22:38:22 +02004650 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004651 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004652 },
4653
4654 [MV88E6171] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004655 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004656 .family = MV88E6XXX_FAMILY_6351,
4657 .name = "Marvell 88E6171",
4658 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004659 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004660 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004661 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004662 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004663 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004664 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004665 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004666 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004667 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004668 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004669 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004670 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004671 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004672 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004673 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004674 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004675 },
4676
4677 [MV88E6172] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004678 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004679 .family = MV88E6XXX_FAMILY_6352,
4680 .name = "Marvell 88E6172",
4681 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004682 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004683 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004684 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004685 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004686 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004687 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004688 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004689 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004690 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004691 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004692 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004693 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004694 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004695 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004696 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004697 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004698 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004699 },
4700
4701 [MV88E6175] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004702 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004703 .family = MV88E6XXX_FAMILY_6351,
4704 .name = "Marvell 88E6175",
4705 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004706 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004707 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004708 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004709 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004710 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004711 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004712 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004713 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004714 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004715 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004716 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004717 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004718 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004719 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004720 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004721 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004722 },
4723
4724 [MV88E6176] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004725 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004726 .family = MV88E6XXX_FAMILY_6352,
4727 .name = "Marvell 88E6176",
4728 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004729 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004730 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004731 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004732 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004733 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004734 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004735 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004736 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004737 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004738 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004739 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004740 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004741 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004742 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004743 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004744 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004745 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004746 },
4747
4748 [MV88E6185] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004749 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004750 .family = MV88E6XXX_FAMILY_6185,
4751 .name = "Marvell 88E6185",
4752 .num_databases = 256,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004753 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004754 .num_ports = 10,
Andrew Lunnbc393152018-03-17 20:32:04 +01004755 .num_internal_phys = 0,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004756 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004757 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004758 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004759 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004760 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004761 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004762 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05004763 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004764 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004765 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004766 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004767 },
4768
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004769 [MV88E6190] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004770 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004771 .family = MV88E6XXX_FAMILY_6390,
4772 .name = "Marvell 88E6190",
4773 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004774 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004775 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004776 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004777 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004778 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004779 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004780 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004781 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004782 .global2_addr = 0x1c,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004783 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004784 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004785 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004786 .g2_irqs = 14,
Vivien Didelotf3645652017-03-30 17:37:07 -04004787 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004788 .multi_chip = true,
Vivien Didelote606ca32017-03-11 16:12:55 -05004789 .atu_move_port_mask = 0x1f,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004790 .ops = &mv88e6190_ops,
4791 },
4792
4793 [MV88E6190X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004794 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004795 .family = MV88E6XXX_FAMILY_6390,
4796 .name = "Marvell 88E6190X",
4797 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004798 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004799 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004800 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004801 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004802 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004803 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004804 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004805 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004806 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004807 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004808 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004809 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004810 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004811 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004812 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004813 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004814 .ops = &mv88e6190x_ops,
4815 },
4816
4817 [MV88E6191] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004818 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004819 .family = MV88E6XXX_FAMILY_6390,
4820 .name = "Marvell 88E6191",
4821 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004822 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004823 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004824 .num_internal_phys = 9,
Vivien Didelot931d1822017-05-01 14:05:27 -04004825 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004826 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004827 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004828 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004829 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004830 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004831 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004832 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004833 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004834 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004835 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004836 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004837 .ptp_support = true,
Vivien Didelot2cf4cefb2017-03-28 13:50:34 -04004838 .ops = &mv88e6191_ops,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004839 },
4840
Hubert Feurstein49022642019-07-31 10:23:46 +02004841 [MV88E6220] = {
4842 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4843 .family = MV88E6XXX_FAMILY_6250,
4844 .name = "Marvell 88E6220",
4845 .num_databases = 64,
4846
4847 /* Ports 2-4 are not routed to pins
4848 * => usable ports 0, 1, 5, 6
4849 */
4850 .num_ports = 7,
4851 .num_internal_phys = 2,
Hubert Feursteinc8574862019-07-31 10:23:48 +02004852 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
Hubert Feurstein49022642019-07-31 10:23:46 +02004853 .max_vid = 4095,
4854 .port_base_addr = 0x08,
4855 .phy_base_addr = 0x00,
4856 .global1_addr = 0x0f,
4857 .global2_addr = 0x07,
4858 .age_time_coeff = 15000,
4859 .g1_irqs = 9,
4860 .g2_irqs = 10,
4861 .atu_move_port_mask = 0xf,
4862 .dual_chip = true,
4863 .tag_protocol = DSA_TAG_PROTO_DSA,
Hubert Feurstein71509612019-07-31 10:23:51 +02004864 .ptp_support = true,
Hubert Feurstein49022642019-07-31 10:23:46 +02004865 .ops = &mv88e6250_ops,
4866 },
4867
Vivien Didelotf81ec902016-05-09 13:22:58 -04004868 [MV88E6240] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004869 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004870 .family = MV88E6XXX_FAMILY_6352,
4871 .name = "Marvell 88E6240",
4872 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004873 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004874 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004875 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004876 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004877 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004878 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004879 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004880 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004881 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004882 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004883 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004884 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004885 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004886 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004887 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004888 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004889 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004890 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004891 },
4892
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004893 [MV88E6250] = {
4894 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4895 .family = MV88E6XXX_FAMILY_6250,
4896 .name = "Marvell 88E6250",
4897 .num_databases = 64,
4898 .num_ports = 7,
4899 .num_internal_phys = 5,
4900 .max_vid = 4095,
4901 .port_base_addr = 0x08,
4902 .phy_base_addr = 0x00,
4903 .global1_addr = 0x0f,
4904 .global2_addr = 0x07,
4905 .age_time_coeff = 15000,
4906 .g1_irqs = 9,
4907 .g2_irqs = 10,
4908 .atu_move_port_mask = 0xf,
4909 .dual_chip = true,
4910 .tag_protocol = DSA_TAG_PROTO_DSA,
Hubert Feurstein71509612019-07-31 10:23:51 +02004911 .ptp_support = true,
Rasmus Villemoes1f718362019-06-04 07:34:32 +00004912 .ops = &mv88e6250_ops,
4913 },
4914
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004915 [MV88E6290] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004916 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004917 .family = MV88E6XXX_FAMILY_6390,
4918 .name = "Marvell 88E6290",
4919 .num_databases = 4096,
4920 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01004921 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004922 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04004923 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004924 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004925 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004926 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004927 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01004928 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004929 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04004930 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05004931 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04004932 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004933 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004934 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004935 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004936 .ops = &mv88e6290_ops,
4937 },
4938
Vivien Didelotf81ec902016-05-09 13:22:58 -04004939 [MV88E6320] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004940 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004941 .family = MV88E6XXX_FAMILY_6320,
4942 .name = "Marvell 88E6320",
4943 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004944 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004945 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004946 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004947 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004948 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004949 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004950 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004951 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004952 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004953 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004954 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004955 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004956 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04004957 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004958 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004959 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004960 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004961 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004962 },
4963
4964 [MV88E6321] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004965 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004966 .family = MV88E6XXX_FAMILY_6320,
4967 .name = "Marvell 88E6321",
4968 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004969 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004970 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01004971 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004972 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004973 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04004974 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004975 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04004976 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04004977 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04004978 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02004979 .g1_irqs = 8,
Andrew Lunnbc393152018-03-17 20:32:04 +01004980 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05004981 .atu_move_port_mask = 0xf,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04004982 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01004983 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01004984 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04004985 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004986 },
4987
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004988 [MV88E6341] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04004989 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004990 .family = MV88E6XXX_FAMILY_6341,
4991 .name = "Marvell 88E6341",
4992 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01004993 .num_macs = 2048,
Andrew Lunnbc393152018-03-17 20:32:04 +01004994 .num_internal_phys = 5,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004995 .num_ports = 6,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01004996 .num_gpio = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04004997 .max_vid = 4095,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01004998 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02004999 .phy_base_addr = 0x10,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005000 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005001 .global2_addr = 0x1c,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005002 .age_time_coeff = 3750,
Vivien Didelote606ca32017-03-11 16:12:55 -05005003 .atu_move_port_mask = 0x1f,
Andrew Lunnadfccf12018-03-17 20:32:03 +01005004 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005005 .g2_irqs = 10,
Vivien Didelotf3645652017-03-30 17:37:07 -04005006 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005007 .multi_chip = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005008 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005009 .ptp_support = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01005010 .ops = &mv88e6341_ops,
5011 },
5012
Vivien Didelotf81ec902016-05-09 13:22:58 -04005013 [MV88E6350] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005014 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005015 .family = MV88E6XXX_FAMILY_6351,
5016 .name = "Marvell 88E6350",
5017 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005018 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005019 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005020 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005021 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005022 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005023 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005024 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005025 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005026 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005027 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005028 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005029 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005030 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005031 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005032 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005033 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005034 },
5035
5036 [MV88E6351] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005037 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005038 .family = MV88E6XXX_FAMILY_6351,
5039 .name = "Marvell 88E6351",
5040 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005041 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005042 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005043 .num_internal_phys = 5,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005044 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005045 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005046 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005047 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005048 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005049 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005050 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005051 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005052 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005053 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005054 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005055 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005056 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005057 },
5058
5059 [MV88E6352] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005060 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005061 .family = MV88E6XXX_FAMILY_6352,
5062 .name = "Marvell 88E6352",
5063 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005064 .num_macs = 8192,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005065 .num_ports = 7,
Andrew Lunnbc393152018-03-17 20:32:04 +01005066 .num_internal_phys = 5,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005067 .num_gpio = 15,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04005068 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04005069 .port_base_addr = 0x10,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005070 .phy_base_addr = 0x0,
Vivien Didelota935c052016-09-29 12:21:53 -04005071 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005072 .global2_addr = 0x1c,
Vivien Didelotacddbd22016-07-18 20:45:39 -04005073 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02005074 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005075 .g2_irqs = 10,
Vivien Didelote606ca32017-03-11 16:12:55 -05005076 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04005077 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005078 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005079 .tag_protocol = DSA_TAG_PROTO_EDSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005080 .ptp_support = true,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04005081 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005082 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005083 [MV88E6390] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005085 .family = MV88E6XXX_FAMILY_6390,
5086 .name = "Marvell 88E6390",
5087 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005088 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005089 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005090 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005091 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005092 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005093 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005094 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005095 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005096 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005097 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005098 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005099 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005100 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005101 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005102 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005103 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005104 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005105 .ops = &mv88e6390_ops,
5106 },
5107 [MV88E6390X] = {
Vivien Didelot107fcc12017-06-12 12:37:36 -04005108 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005109 .family = MV88E6XXX_FAMILY_6390,
5110 .name = "Marvell 88E6390X",
5111 .num_databases = 4096,
Andrew Lunnd9ea5622019-11-05 01:12:58 +01005112 .num_macs = 16384,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005113 .num_ports = 11, /* 10 + Z80 */
Heiner Kallweit95150f22019-03-02 10:06:05 +01005114 .num_internal_phys = 9,
Brandon Streiffa73ccd62018-02-14 01:07:46 +01005115 .num_gpio = 16,
Vivien Didelot931d1822017-05-01 14:05:27 -04005116 .max_vid = 8191,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005117 .port_base_addr = 0x0,
Andrew Lunn9255bac2018-05-05 20:58:22 +02005118 .phy_base_addr = 0x0,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005119 .global1_addr = 0x1b,
Vivien Didelot9069c132017-07-17 13:03:44 -04005120 .global2_addr = 0x1c,
Andrew Lunnb91e0552017-02-02 00:46:15 +01005121 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005122 .g1_irqs = 9,
Vivien Didelotd6c5e6a2017-07-17 13:03:40 -04005123 .g2_irqs = 14,
Vivien Didelote606ca32017-03-11 16:12:55 -05005124 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04005125 .pvt = true,
Vivien Didelotb3e05aa2017-07-17 13:03:46 -04005126 .multi_chip = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01005127 .tag_protocol = DSA_TAG_PROTO_DSA,
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005128 .ptp_support = true,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005129 .ops = &mv88e6390x_ops,
5130 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04005131};
5132
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005133static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04005134{
Vivien Didelota439c062016-04-17 13:23:58 -04005135 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04005136
Vivien Didelot5f7c0362016-06-20 13:14:04 -04005137 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5138 if (mv88e6xxx_table[i].prod_num == prod_num)
5139 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04005140
Vivien Didelotb9b37712015-10-30 19:39:48 -04005141 return NULL;
5142}
5143
Vivien Didelotfad09c72016-06-21 12:28:20 -04005144static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005145{
5146 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005147 unsigned int prod_num, rev;
5148 u16 id;
5149 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005150
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005151 mv88e6xxx_reg_lock(chip);
Vivien Didelot107fcc12017-06-12 12:37:36 -04005152 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005153 mv88e6xxx_reg_unlock(chip);
Vivien Didelot8f6345b2016-07-20 18:18:36 -04005154 if (err)
5155 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005156
Vivien Didelot107fcc12017-06-12 12:37:36 -04005157 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5158 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005159
5160 info = mv88e6xxx_lookup_info(prod_num);
5161 if (!info)
5162 return -ENODEV;
5163
Vivien Didelotcaac8542016-06-20 13:14:09 -04005164 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04005165 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005166
Vivien Didelotca070c12016-09-02 14:45:34 -04005167 err = mv88e6xxx_g2_require(chip);
5168 if (err)
5169 return err;
5170
Vivien Didelotfad09c72016-06-21 12:28:20 -04005171 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5172 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005173
5174 return 0;
5175}
5176
Vivien Didelotfad09c72016-06-21 12:28:20 -04005177static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04005178{
Vivien Didelotfad09c72016-06-21 12:28:20 -04005179 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005180
Vivien Didelotfad09c72016-06-21 12:28:20 -04005181 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5182 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04005183 return NULL;
5184
Vivien Didelotfad09c72016-06-21 12:28:20 -04005185 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04005186
Vivien Didelotfad09c72016-06-21 12:28:20 -04005187 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01005188 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelotda7dc872019-09-07 16:00:49 -04005189 idr_init(&chip->policies);
Vivien Didelot469d7292016-06-20 13:14:06 -04005190
Vivien Didelotfad09c72016-06-21 12:28:20 -04005191 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04005192}
5193
Florian Fainelli5ed4e3e2017-11-10 15:22:52 -08005194static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
Florian Fainelli4d776482020-01-07 21:06:05 -08005195 int port,
5196 enum dsa_tag_protocol m)
Andrew Lunn7b314362016-08-22 16:01:01 +02005197{
Vivien Didelot04bed142016-08-31 18:06:13 -04005198 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02005199
Andrew Lunn443d5a12016-12-03 04:35:18 +01005200 return chip->info->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02005201}
5202
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005203static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
Vivien Didelot3709aad2017-11-30 11:23:58 -05005204 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005205{
5206 /* We don't need any dynamic resource from the kernel (yet),
5207 * so skip the prepare phase.
5208 */
5209
5210 return 0;
5211}
5212
5213static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
Vivien Didelot3709aad2017-11-30 11:23:58 -05005214 const struct switchdev_obj_port_mdb *mdb)
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005215{
Vivien Didelot04bed142016-08-31 18:06:13 -04005216 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005217
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005218 mv88e6xxx_reg_lock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005219 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
Vivien Didelot27c0e602017-06-15 12:14:01 -04005220 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
Vivien Didelot774439e52017-06-08 18:34:08 -04005221 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5222 port);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005223 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005224}
5225
5226static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5227 const struct switchdev_obj_port_mdb *mdb)
5228{
Vivien Didelot04bed142016-08-31 18:06:13 -04005229 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005230 int err;
5231
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005232 mv88e6xxx_reg_lock(chip);
Vivien Didelotd8291a92019-09-07 16:00:47 -04005233 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005234 mv88e6xxx_reg_unlock(chip);
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005235
5236 return err;
5237}
5238
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005239static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5240 struct dsa_mall_mirror_tc_entry *mirror,
5241 bool ingress)
5242{
5243 enum mv88e6xxx_egress_direction direction = ingress ?
5244 MV88E6XXX_EGRESS_DIR_INGRESS :
5245 MV88E6XXX_EGRESS_DIR_EGRESS;
5246 struct mv88e6xxx_chip *chip = ds->priv;
5247 bool other_mirrors = false;
5248 int i;
5249 int err;
5250
5251 if (!chip->info->ops->set_egress_port)
5252 return -EOPNOTSUPP;
5253
5254 mutex_lock(&chip->reg_lock);
5255 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5256 mirror->to_local_port) {
5257 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5258 other_mirrors |= ingress ?
5259 chip->ports[i].mirror_ingress :
5260 chip->ports[i].mirror_egress;
5261
5262 /* Can't change egress port when other mirror is active */
5263 if (other_mirrors) {
5264 err = -EBUSY;
5265 goto out;
5266 }
5267
5268 err = chip->info->ops->set_egress_port(chip,
5269 direction,
5270 mirror->to_local_port);
5271 if (err)
5272 goto out;
5273 }
5274
5275 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5276out:
5277 mutex_unlock(&chip->reg_lock);
5278
5279 return err;
5280}
5281
5282static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5283 struct dsa_mall_mirror_tc_entry *mirror)
5284{
5285 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5286 MV88E6XXX_EGRESS_DIR_INGRESS :
5287 MV88E6XXX_EGRESS_DIR_EGRESS;
5288 struct mv88e6xxx_chip *chip = ds->priv;
5289 bool other_mirrors = false;
5290 int i;
5291
5292 mutex_lock(&chip->reg_lock);
5293 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5294 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5295
5296 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5297 other_mirrors |= mirror->ingress ?
5298 chip->ports[i].mirror_ingress :
5299 chip->ports[i].mirror_egress;
5300
5301 /* Reset egress port when no other mirror is active */
5302 if (!other_mirrors) {
5303 if (chip->info->ops->set_egress_port(chip,
5304 direction,
5305 dsa_upstream_port(ds,
Colin Ian King4e4637b2019-11-12 13:05:23 +00005306 port)))
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005307 dev_err(ds->dev, "failed to set egress port\n");
5308 }
5309
5310 mutex_unlock(&chip->reg_lock);
5311}
5312
Russell King4f859012019-02-20 15:35:05 -08005313static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5314 bool unicast, bool multicast)
5315{
5316 struct mv88e6xxx_chip *chip = ds->priv;
5317 int err = -EOPNOTSUPP;
5318
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005319 mv88e6xxx_reg_lock(chip);
Russell King4f859012019-02-20 15:35:05 -08005320 if (chip->info->ops->port_set_egress_floods)
5321 err = chip->info->ops->port_set_egress_floods(chip, port,
5322 unicast,
5323 multicast);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005324 mv88e6xxx_reg_unlock(chip);
Russell King4f859012019-02-20 15:35:05 -08005325
5326 return err;
5327}
5328
Florian Fainellia82f67a2017-01-08 14:52:08 -08005329static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunn7b314362016-08-22 16:01:01 +02005330 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005331 .setup = mv88e6xxx_setup,
Andrew Lunn23e8b472019-10-25 01:03:52 +02005332 .teardown = mv88e6xxx_teardown,
Russell Kingc9a23562018-05-10 13:17:35 -07005333 .phylink_validate = mv88e6xxx_validate,
Russell Kinga5a68582020-03-14 10:15:43 +00005334 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
Russell Kingc9a23562018-05-10 13:17:35 -07005335 .phylink_mac_config = mv88e6xxx_mac_config,
Russell Kinga5a68582020-03-14 10:15:43 +00005336 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
Russell Kingc9a23562018-05-10 13:17:35 -07005337 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
5338 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005339 .get_strings = mv88e6xxx_get_strings,
5340 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
5341 .get_sset_count = mv88e6xxx_get_sset_count,
Andrew Lunn04aca992017-05-26 01:03:24 +02005342 .port_enable = mv88e6xxx_port_enable,
5343 .port_disable = mv88e6xxx_port_disable,
Andrew Lunn2a550ae2020-07-11 22:32:05 +02005344 .port_max_mtu = mv88e6xxx_get_max_mtu,
5345 .port_change_mtu = mv88e6xxx_change_mtu,
Vivien Didelot08f50062017-08-01 16:32:41 -04005346 .get_mac_eee = mv88e6xxx_get_mac_eee,
5347 .set_mac_eee = mv88e6xxx_set_mac_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02005348 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005349 .get_eeprom = mv88e6xxx_get_eeprom,
5350 .set_eeprom = mv88e6xxx_set_eeprom,
5351 .get_regs_len = mv88e6xxx_get_regs_len,
5352 .get_regs = mv88e6xxx_get_regs,
Vivien Didelotda7dc872019-09-07 16:00:49 -04005353 .get_rxnfc = mv88e6xxx_get_rxnfc,
5354 .set_rxnfc = mv88e6xxx_set_rxnfc,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04005355 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005356 .port_bridge_join = mv88e6xxx_port_bridge_join,
5357 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
Russell King4f859012019-02-20 15:35:05 -08005358 .port_egress_floods = mv88e6xxx_port_egress_floods,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005359 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04005360 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005361 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
5362 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
5363 .port_vlan_add = mv88e6xxx_port_vlan_add,
5364 .port_vlan_del = mv88e6xxx_port_vlan_del,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005365 .port_fdb_add = mv88e6xxx_port_fdb_add,
5366 .port_fdb_del = mv88e6xxx_port_fdb_del,
5367 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04005368 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
5369 .port_mdb_add = mv88e6xxx_port_mdb_add,
5370 .port_mdb_del = mv88e6xxx_port_mdb_del,
Iwan R Timmerf0942e02019-11-07 22:11:14 +01005371 .port_mirror_add = mv88e6xxx_port_mirror_add,
5372 .port_mirror_del = mv88e6xxx_port_mirror_del,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04005373 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
5374 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01005375 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
5376 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
5377 .port_txtstamp = mv88e6xxx_port_txtstamp,
5378 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
5379 .get_ts_info = mv88e6xxx_get_ts_info,
Andrew Lunn23e8b472019-10-25 01:03:52 +02005380 .devlink_param_get = mv88e6xxx_devlink_param_get,
5381 .devlink_param_set = mv88e6xxx_devlink_param_set,
Andrew Lunn93157302020-09-18 21:11:09 +02005382 .devlink_info_get = mv88e6xxx_devlink_info_get,
Vivien Didelotf81ec902016-05-09 13:22:58 -04005383};
5384
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08005385static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005386{
Vivien Didelotfad09c72016-06-21 12:28:20 -04005387 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005388 struct dsa_switch *ds;
5389
Vivien Didelot7e99e342019-10-21 16:51:30 -04005390 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005391 if (!ds)
5392 return -ENOMEM;
5393
Vivien Didelot7e99e342019-10-21 16:51:30 -04005394 ds->dev = dev;
5395 ds->num_ports = mv88e6xxx_num_ports(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04005396 ds->priv = chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005397 ds->dev = dev;
Vivien Didelot9d490b42016-08-23 12:38:56 -04005398 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelot9ff74f22017-03-15 15:53:50 -04005399 ds->ageing_time_min = chip->info->age_time_coeff;
5400 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005401
5402 dev_set_drvdata(dev, ds);
5403
Vivien Didelot23c9ee42017-05-26 18:12:51 -04005404 return dsa_register_switch(ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005405}
5406
Vivien Didelotfad09c72016-06-21 12:28:20 -04005407static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005408{
Vivien Didelotfad09c72016-06-21 12:28:20 -04005409 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04005410}
5411
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005412static const void *pdata_device_get_match_data(struct device *dev)
5413{
5414 const struct of_device_id *matches = dev->driver->of_match_table;
5415 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5416
5417 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5418 matches++) {
5419 if (!strcmp(pdata->compatible, matches->compatible))
5420 return matches->data;
5421 }
5422 return NULL;
5423}
5424
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01005425/* There is no suspend to RAM support at DSA level yet, the switch configuration
5426 * would be lost after a power cycle so prevent it to be suspended.
5427 */
5428static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5429{
5430 return -EOPNOTSUPP;
5431}
5432
5433static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5434{
5435 return 0;
5436}
5437
5438static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5439
Vivien Didelot57d32312016-06-20 13:13:58 -04005440static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005441{
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005442 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
David S. Miller7ddae242018-05-20 19:04:24 -04005443 const struct mv88e6xxx_info *compat_info = NULL;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005444 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02005445 struct device_node *np = dev->of_node;
Vivien Didelotfad09c72016-06-21 12:28:20 -04005446 struct mv88e6xxx_chip *chip;
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005447 int port;
Andrew Lunn52638f72016-05-10 23:27:22 +02005448 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005449
Andrew Lunn7bb8c992018-05-31 00:15:42 +02005450 if (!np && !pdata)
5451 return -EINVAL;
5452
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005453 if (np)
5454 compat_info = of_device_get_match_data(dev);
5455
5456 if (pdata) {
5457 compat_info = pdata_device_get_match_data(dev);
5458
5459 if (!pdata->netdev)
5460 return -EINVAL;
5461
5462 for (port = 0; port < DSA_MAX_PORTS; port++) {
5463 if (!(pdata->enabled_ports & (1 << port)))
5464 continue;
5465 if (strcmp(pdata->cd.port_names[port], "cpu"))
5466 continue;
5467 pdata->cd.netdev[port] = &pdata->netdev->dev;
5468 break;
5469 }
5470 }
5471
Vivien Didelotcaac8542016-06-20 13:14:09 -04005472 if (!compat_info)
5473 return -EINVAL;
5474
Vivien Didelotfad09c72016-06-21 12:28:20 -04005475 chip = mv88e6xxx_alloc_chip(dev);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005476 if (!chip) {
5477 err = -ENOMEM;
5478 goto out;
5479 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005480
Vivien Didelotfad09c72016-06-21 12:28:20 -04005481 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04005482
Vivien Didelotfad09c72016-06-21 12:28:20 -04005483 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04005484 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005485 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005486
Andrew Lunnb4308f02016-11-21 23:26:55 +01005487 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005488 if (IS_ERR(chip->reset)) {
5489 err = PTR_ERR(chip->reset);
5490 goto out;
5491 }
Baruch Siach7b75e492019-06-27 21:17:39 +03005492 if (chip->reset)
5493 usleep_range(1000, 2000);
Andrew Lunnb4308f02016-11-21 23:26:55 +01005494
Vivien Didelotfad09c72016-06-21 12:28:20 -04005495 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04005496 if (err)
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005497 goto out;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005498
Vivien Didelote57e5e72016-08-15 17:19:00 -04005499 mv88e6xxx_phy_init(chip);
5500
Andrew Lunn00baabe2018-05-19 22:31:35 +02005501 if (chip->info->ops->get_eeprom) {
5502 if (np)
5503 of_property_read_u32(np, "eeprom-length",
5504 &chip->eeprom_len);
5505 else
5506 chip->eeprom_len = pdata->eeprom_len;
5507 }
Andrew Lunnf8cd8752016-05-10 23:27:25 +02005508
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005509 mv88e6xxx_reg_lock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005510 err = mv88e6xxx_switch_reset(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005511 mv88e6xxx_reg_unlock(chip);
Andrew Lunnb516d452016-06-04 21:17:06 +02005512 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02005513 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02005514
Andrew Lunna27415d2019-05-01 00:10:50 +02005515 if (np) {
5516 chip->irq = of_irq_get(np, 0);
5517 if (chip->irq == -EPROBE_DEFER) {
5518 err = chip->irq;
5519 goto out;
5520 }
Andrew Lunn83c0afa2016-06-04 21:17:07 +02005521 }
5522
Andrew Lunna27415d2019-05-01 00:10:50 +02005523 if (pdata)
5524 chip->irq = pdata->irq;
5525
Andrew Lunn294d7112018-02-22 22:58:32 +01005526 /* Has to be performed before the MDIO bus is created, because
Uwe Kleine-Königa7087672018-03-20 10:44:41 +01005527 * the PHYs will link their interrupts to these interrupt
Andrew Lunn294d7112018-02-22 22:58:32 +01005528 * controllers
5529 */
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005530 mv88e6xxx_reg_lock(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01005531 if (chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02005532 err = mv88e6xxx_g1_irq_setup(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01005533 else
5534 err = mv88e6xxx_irq_poll_setup(chip);
Rasmus Villemoesc9acece2019-06-20 13:50:42 +00005535 mv88e6xxx_reg_unlock(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005536
Andrew Lunn294d7112018-02-22 22:58:32 +01005537 if (err)
5538 goto out;
5539
5540 if (chip->info->g2_irqs > 0) {
5541 err = mv88e6xxx_g2_irq_setup(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005542 if (err)
Andrew Lunn294d7112018-02-22 22:58:32 +01005543 goto out_g1_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02005544 }
5545
Andrew Lunn294d7112018-02-22 22:58:32 +01005546 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5547 if (err)
5548 goto out_g2_irq;
5549
5550 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5551 if (err)
5552 goto out_g1_atu_prob_irq;
5553
Andrew Lunna3c53be52017-01-24 14:53:50 +01005554 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02005555 if (err)
Andrew Lunn62eb1162018-01-14 02:32:45 +01005556 goto out_g1_vtu_prob_irq;
Andrew Lunndc30c352016-10-16 19:56:49 +02005557
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08005558 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005559 if (err)
5560 goto out_mdio;
5561
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005562 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02005563
5564out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01005565 mv88e6xxx_mdios_unregister(chip);
Andrew Lunn62eb1162018-01-14 02:32:45 +01005566out_g1_vtu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01005567 mv88e6xxx_g1_vtu_prob_irq_free(chip);
Andrew Lunn09776442018-01-14 02:32:44 +01005568out_g1_atu_prob_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01005569 mv88e6xxx_g1_atu_prob_irq_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005570out_g2_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01005571 if (chip->info->g2_irqs > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02005572 mv88e6xxx_g2_irq_free(chip);
5573out_g1_irq:
Andrew Lunn294d7112018-02-22 22:58:32 +01005574 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01005575 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn294d7112018-02-22 22:58:32 +01005576 else
5577 mv88e6xxx_irq_poll_free(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005578out:
Andrew Lunn877b7cb2018-05-19 22:31:34 +02005579 if (pdata)
5580 dev_put(pdata->netdev);
5581
Andrew Lunndc30c352016-10-16 19:56:49 +02005582 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005583}
5584
5585static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5586{
5587 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vivien Didelot04bed142016-08-31 18:06:13 -04005588 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005589
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01005590 if (chip->info->ptp_support) {
5591 mv88e6xxx_hwtstamp_free(chip);
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005592 mv88e6xxx_ptp_free(chip);
Brandon Streiffc6fe0ad2018-02-14 01:07:50 +01005593 }
Brandon Streiff2fa8d3a2018-02-14 01:07:45 +01005594
Andrew Lunn930188c2016-08-22 16:01:03 +02005595 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04005596 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01005597 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02005598
Andrew Lunn76f38f12018-03-17 20:21:09 +01005599 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5600 mv88e6xxx_g1_atu_prob_irq_free(chip);
5601
5602 if (chip->info->g2_irqs > 0)
5603 mv88e6xxx_g2_irq_free(chip);
5604
Andrew Lunn76f38f12018-03-17 20:21:09 +01005605 if (chip->irq > 0)
Andrew Lunn467126442016-11-20 20:14:15 +01005606 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn76f38f12018-03-17 20:21:09 +01005607 else
5608 mv88e6xxx_irq_poll_free(chip);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005609}
5610
5611static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04005612 {
5613 .compatible = "marvell,mv88e6085",
5614 .data = &mv88e6xxx_table[MV88E6085],
5615 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01005616 {
5617 .compatible = "marvell,mv88e6190",
5618 .data = &mv88e6xxx_table[MV88E6190],
5619 },
Rasmus Villemoes1f718362019-06-04 07:34:32 +00005620 {
5621 .compatible = "marvell,mv88e6250",
5622 .data = &mv88e6xxx_table[MV88E6250],
5623 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005624 { /* sentinel */ },
5625};
5626
5627MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5628
5629static struct mdio_driver mv88e6xxx_driver = {
5630 .probe = mv88e6xxx_probe,
5631 .remove = mv88e6xxx_remove,
5632 .mdiodrv.driver = {
5633 .name = "mv88e6085",
5634 .of_match_table = mv88e6xxx_of_match,
Miquel Raynalbcd3d9d2019-02-05 12:07:28 +01005635 .pm = &mv88e6xxx_pm_ops,
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02005636 },
5637};
5638
Andrew Lunn7324d502019-04-27 19:19:10 +02005639mdio_module_driver(mv88e6xxx_driver);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00005640
5641MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5642MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5643MODULE_LICENSE("GPL");